drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "link_encoder.h"
  31 #include "stream_encoder.h"
  32
  33 #include "resource.h"
  34 #include "dce110/dce110_resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "dce/dce_audio.h"
  37 #include "dce110/dce110_timing_generator.h"
  38 #include "irq/dce110/irq_service_dce110.h"
  39 #include "dce110/dce110_timing_generator_v.h"
  40 #include "dce/dce_link_encoder.h"
  41 #include "dce/dce_stream_encoder.h"
  42 #include "dce/dce_mem_input.h"
  43 #include "dce110/dce110_mem_input_v.h"
  44 #include "dce/dce_ipp.h"
  45 #include "dce/dce_transform.h"
  46 #include "dce110/dce110_transform_v.h"
  47 #include "dce/dce_opp.h"
  48 #include "dce110/dce110_opp_v.h"
  49 #include "dce/dce_clock_source.h"
  50 #include "dce/dce_hwseq.h"
  51 #include "dce110/dce110_hw_sequencer.h"
  52 #include "dce/dce_aux.h"
  53 #include "dce/dce_abm.h"
  54 #include "dce/dce_dmcu.h"
  55 #include "dce/dce_i2c.h"
  56 #include "dce/dce_panel_cntl.h"
  57
  58 #define DC_LOGGER \
  59                 dc->ctx->logger
  60
  61 #include "dce110/dce110_compressor.h"
  62
  63 #include "reg_helper.h"
  64
  65 #include "dce/dce_11_0_d.h"
  66 #include "dce/dce_11_0_sh_mask.h"
  67
  68 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
  69 #include "gmc/gmc_8_2_d.h"
  70 #include "gmc/gmc_8_2_sh_mask.h"
  71 #endif
  72
  73 #ifndef mmDP_DPHY_INTERNAL_CTRL
  74         #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
  75         #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
  76         #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
  77         #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
  78         #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
  79         #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
  80         #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
  81         #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
  82         #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
  83         #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
  84 #endif
  85
  86 #ifndef mmBIOS_SCRATCH_2
  87         #define mmBIOS_SCRATCH_2 0x05CB
  88         #define mmBIOS_SCRATCH_3 0x05CC
  89         #define mmBIOS_SCRATCH_6 0x05CF
  90 #endif
  91
  92 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
  93         #define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
  94         #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
  95         #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
  96         #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
  97         #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
  98         #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
  99         #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
 100         #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
 101 #endif
 102
 103 #ifndef mmDP_DPHY_FAST_TRAINING
 104         #define mmDP_DPHY_FAST_TRAINING                         0x4ABC
 105         #define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
 106         #define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
 107         #define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
 108         #define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
 109         #define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
 110         #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
 111         #define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
 112 #endif
 113
 114 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE
 115         #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1
 116 #endif
 117
 118 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
 119         {
 120                 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 121                 .dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
 122         },
 123         {
 124                 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 125                 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 126         },
 127         {
 128                 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 129                 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 130         },
 131         {
 132                 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 133                 .dcp =  (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 134         },
 135         {
 136                 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 137                 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 138         },
 139         {
 140                 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 141                 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 142         }
 143 };
 144
 145 /* set register offset */
 146 #define SR(reg_name)\
 147         .reg_name = mm ## reg_name
 148
 149 /* set register offset with instance */
 150 #define SRI(reg_name, block, id)\
 151         .reg_name = mm ## block ## id ## _ ## reg_name
 152
 153 static const struct dce_dmcu_registers dmcu_regs = {
 154                 DMCU_DCE110_COMMON_REG_LIST()
 155 };
 156
 157 static const struct dce_dmcu_shift dmcu_shift = {
 158                 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
 159 };
 160
 161 static const struct dce_dmcu_mask dmcu_mask = {
 162                 DMCU_MASK_SH_LIST_DCE110(_MASK)
 163 };
 164
 165 static const struct dce_abm_registers abm_regs = {
 166                 ABM_DCE110_COMMON_REG_LIST()
 167 };
 168
 169 static const struct dce_abm_shift abm_shift = {
 170                 ABM_MASK_SH_LIST_DCE110(__SHIFT)
 171 };
 172
 173 static const struct dce_abm_mask abm_mask = {
 174                 ABM_MASK_SH_LIST_DCE110(_MASK)
 175 };
 176
 177 #define ipp_regs(id)\
 178 [id] = {\
 179                 IPP_DCE110_REG_LIST_DCE_BASE(id)\
 180 }
 181
 182 static const struct dce_ipp_registers ipp_regs[] = {
 183                 ipp_regs(0),
 184                 ipp_regs(1),
 185                 ipp_regs(2)
 186 };
 187
 188 static const struct dce_ipp_shift ipp_shift = {
 189                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 190 };
 191
 192 static const struct dce_ipp_mask ipp_mask = {
 193                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 194 };
 195
 196 #define transform_regs(id)\
 197 [id] = {\
 198                 XFM_COMMON_REG_LIST_DCE110(id)\
 199 }
 200
 201 static const struct dce_transform_registers xfm_regs[] = {
 202                 transform_regs(0),
 203                 transform_regs(1),
 204                 transform_regs(2)
 205 };
 206
 207 static const struct dce_transform_shift xfm_shift = {
 208                 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 209 };
 210
 211 static const struct dce_transform_mask xfm_mask = {
 212                 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
 213 };
 214
 215 #define aux_regs(id)\
 216 [id] = {\
 217         AUX_REG_LIST(id)\
 218 }
 219
 220 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 221                 aux_regs(0),
 222                 aux_regs(1),
 223                 aux_regs(2),
 224                 aux_regs(3),
 225                 aux_regs(4),
 226                 aux_regs(5)
 227 };
 228
 229 #define hpd_regs(id)\
 230 [id] = {\
 231         HPD_REG_LIST(id)\
 232 }
 233
 234 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 235                 hpd_regs(0),
 236                 hpd_regs(1),
 237                 hpd_regs(2),
 238                 hpd_regs(3),
 239                 hpd_regs(4),
 240                 hpd_regs(5)
 241 };
 242
 243
 244 #define link_regs(id)\
 245 [id] = {\
 246         LE_DCE110_REG_LIST(id)\
 247 }
 248
 249 static const struct dce110_link_enc_registers link_enc_regs[] = {
 250         link_regs(0),
 251         link_regs(1),
 252         link_regs(2),
 253         link_regs(3),
 254         link_regs(4),
 255         link_regs(5),
 256         link_regs(6),
 257 };
 258
 259 #define stream_enc_regs(id)\
 260 [id] = {\
 261         SE_COMMON_REG_LIST(id),\
 262         .TMDS_CNTL = 0,\
 263 }
 264
 265 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 266         stream_enc_regs(0),
 267         stream_enc_regs(1),
 268         stream_enc_regs(2)
 269 };
 270
 271 static const struct dce_stream_encoder_shift se_shift = {
 272                 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 273 };
 274
 275 static const struct dce_stream_encoder_mask se_mask = {
 276                 SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
 277 };
 278
 279 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 280         { DCE_PANEL_CNTL_REG_LIST() }
 281 };
 282
 283 static const struct dce_panel_cntl_shift panel_cntl_shift = {
 284         DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 285 };
 286
 287 static const struct dce_panel_cntl_mask panel_cntl_mask = {
 288         DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
 289 };
 290
 291 static const struct dce110_aux_registers_shift aux_shift = {
 292         DCE_AUX_MASK_SH_LIST(__SHIFT)
 293 };
 294
 295 static const struct dce110_aux_registers_mask aux_mask = {
 296         DCE_AUX_MASK_SH_LIST(_MASK)
 297 };
 298
 299 #define opp_regs(id)\
 300 [id] = {\
 301         OPP_DCE_110_REG_LIST(id),\
 302 }
 303
 304 static const struct dce_opp_registers opp_regs[] = {
 305         opp_regs(0),
 306         opp_regs(1),
 307         opp_regs(2),
 308         opp_regs(3),
 309         opp_regs(4),
 310         opp_regs(5)
 311 };
 312
 313 static const struct dce_opp_shift opp_shift = {
 314         OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT)
 315 };
 316
 317 static const struct dce_opp_mask opp_mask = {
 318         OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK)
 319 };
 320
 321 #define aux_engine_regs(id)\
 322 [id] = {\
 323         AUX_COMMON_REG_LIST(id), \
 324         .AUX_RESET_MASK = 0 \
 325 }
 326
 327 static const struct dce110_aux_registers aux_engine_regs[] = {
 328                 aux_engine_regs(0),
 329                 aux_engine_regs(1),
 330                 aux_engine_regs(2),
 331                 aux_engine_regs(3),
 332                 aux_engine_regs(4),
 333                 aux_engine_regs(5)
 334 };
 335
 336 #define audio_regs(id)\
 337 [id] = {\
 338         AUD_COMMON_REG_LIST(id)\
 339 }
 340
 341 static const struct dce_audio_registers audio_regs[] = {
 342         audio_regs(0),
 343         audio_regs(1),
 344         audio_regs(2),
 345         audio_regs(3),
 346         audio_regs(4),
 347         audio_regs(5),
 348         audio_regs(6),
 349 };
 350
 351 static const struct dce_audio_shift audio_shift = {
 352                 AUD_COMMON_MASK_SH_LIST(__SHIFT)
 353 };
 354
 355 static const struct dce_audio_mask audio_mask = {
 356                 AUD_COMMON_MASK_SH_LIST(_MASK)
 357 };
 358
 359 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
 360
 361
 362 #define clk_src_regs(id)\
 363 [id] = {\
 364         CS_COMMON_REG_LIST_DCE_100_110(id),\
 365 }
 366
 367 static const struct dce110_clk_src_regs clk_src_regs[] = {
 368         clk_src_regs(0),
 369         clk_src_regs(1),
 370         clk_src_regs(2)
 371 };
 372
 373 static const struct dce110_clk_src_shift cs_shift = {
 374                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 375 };
 376
 377 static const struct dce110_clk_src_mask cs_mask = {
 378                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 379 };
 380
 381 static const struct bios_registers bios_regs = {
 382         .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
 383         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 384 };
 385
 386 static const struct resource_caps carrizo_resource_cap = {
 387                 .num_timing_generator = 3,
 388                 .num_video_plane = 1,
 389                 .num_audio = 3,
 390                 .num_stream_encoder = 3,
 391                 .num_pll = 2,
 392                 .num_ddc = 3,
 393 };
 394
 395 static const struct resource_caps stoney_resource_cap = {
 396                 .num_timing_generator = 2,
 397                 .num_video_plane = 1,
 398                 .num_audio = 3,
 399                 .num_stream_encoder = 3,
 400                 .num_pll = 2,
 401                 .num_ddc = 3,
 402 };
 403
 404 static const struct dc_plane_cap plane_cap = {
 405                 .type = DC_PLANE_TYPE_DCE_RGB,
 406                 .blends_with_below = true,
 407                 .blends_with_above = true,
 408                 .per_pixel_alpha = 1,
 409
 410                 .pixel_format_support = {
 411                                 .argb8888 = true,
 412                                 .nv12 = false,
 413                                 .fp16 = false
 414                 },
 415
 416                 .max_upscale_factor = {
 417                                 .argb8888 = 16000,
 418                                 .nv12 = 1,
 419                                 .fp16 = 1
 420                 },
 421
 422                 .max_downscale_factor = {
 423                                 .argb8888 = 250,
 424                                 .nv12 = 1,
 425                                 .fp16 = 1
 426                 },
 427                 64,
 428                 64
 429 };
 430
 431 static const struct dc_plane_cap underlay_plane_cap = {
 432                 .type = DC_PLANE_TYPE_DCE_UNDERLAY,
 433                 .blends_with_above = true,
 434                 .per_pixel_alpha = 1,
 435
 436                 .pixel_format_support = {
 437                                 .argb8888 = false,
 438                                 .nv12 = true,
 439                                 .fp16 = false
 440                 },
 441
 442                 .max_upscale_factor = {
 443                                 .argb8888 = 1,
 444                                 .nv12 = 16000,
 445                                 .fp16 = 1
 446                 },
 447
 448                 .max_downscale_factor = {
 449                                 .argb8888 = 1,
 450                                 .nv12 = 250,
 451                                 .fp16 = 1
 452                 },
 453                 64,
 454                 64
 455 };
 456
 457 #define CTX  ctx
 458 #define REG(reg) mm ## reg
 459
 460 #ifndef mmCC_DC_HDMI_STRAPS
 461 #define mmCC_DC_HDMI_STRAPS 0x4819
 462 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 463 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 464 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 465 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 466 #endif
 467
 468 static int map_transmitter_id_to_phy_instance(
 469         enum transmitter transmitter)
 470 {
 471         switch (transmitter) {
 472         case TRANSMITTER_UNIPHY_A:
 473                 return 0;
 474         break;
 475         case TRANSMITTER_UNIPHY_B:
 476                 return 1;
 477         break;
 478         case TRANSMITTER_UNIPHY_C:
 479                 return 2;
 480         break;
 481         case TRANSMITTER_UNIPHY_D:
 482                 return 3;
 483         break;
 484         case TRANSMITTER_UNIPHY_E:
 485                 return 4;
 486         break;
 487         case TRANSMITTER_UNIPHY_F:
 488                 return 5;
 489         break;
 490         case TRANSMITTER_UNIPHY_G:
 491                 return 6;
 492         break;
 493         default:
 494                 ASSERT(0);
 495                 return 0;
 496         }
 497 }
 498
 499 static void read_dce_straps(
 500         struct dc_context *ctx,
 501         struct resource_straps *straps)
 502 {
 503         REG_GET_2(CC_DC_HDMI_STRAPS,
 504                         HDMI_DISABLE, &straps->hdmi_disable,
 505                         AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 506
 507         REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 508 }
 509
 510 static struct audio *create_audio(
 511                 struct dc_context *ctx, unsigned int inst)
 512 {
 513         return dce_audio_create(ctx, inst,
 514                         &audio_regs[inst], &audio_shift, &audio_mask);
 515 }
 516
 517 static struct timing_generator *dce110_timing_generator_create(
 518                 struct dc_context *ctx,
 519                 uint32_t instance,
 520                 const struct dce110_timing_generator_offsets *offsets)
 521 {
 522         struct dce110_timing_generator *tg110 =
 523                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 524
 525         if (!tg110)
 526                 return NULL;
 527
 528         dce110_timing_generator_construct(tg110, ctx, instance, offsets);
 529         return &tg110->base;
 530 }
 531
 532 static struct stream_encoder *dce110_stream_encoder_create(
 533         enum engine_id eng_id,
 534         struct dc_context *ctx)
 535 {
 536         struct dce110_stream_encoder *enc110 =
 537                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 538
 539         if (!enc110)
 540                 return NULL;
 541
 542         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 543                                         &stream_enc_regs[eng_id],
 544                                         &se_shift, &se_mask);
 545         return &enc110->base;
 546 }
 547
 548 #define SRII(reg_name, block, id)\
 549         .reg_name[id] = mm ## block ## id ## _ ## reg_name
 550
 551 static const struct dce_hwseq_registers hwseq_stoney_reg = {
 552                 HWSEQ_ST_REG_LIST()
 553 };
 554
 555 static const struct dce_hwseq_registers hwseq_cz_reg = {
 556                 HWSEQ_CZ_REG_LIST()
 557 };
 558
 559 static const struct dce_hwseq_shift hwseq_shift = {
 560                 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT),
 561 };
 562
 563 static const struct dce_hwseq_mask hwseq_mask = {
 564                 HWSEQ_DCE11_MASK_SH_LIST(_MASK),
 565 };
 566
 567 static struct dce_hwseq *dce110_hwseq_create(
 568         struct dc_context *ctx)
 569 {
 570         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 571
 572         if (hws) {
 573                 hws->ctx = ctx;
 574                 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
 575                                 &hwseq_stoney_reg : &hwseq_cz_reg;
 576                 hws->shifts = &hwseq_shift;
 577                 hws->masks = &hwseq_mask;
 578                 hws->wa.blnd_crtc_trigger = true;
 579         }
 580         return hws;
 581 }
 582
 583 static const struct resource_create_funcs res_create_funcs = {
 584         .read_dce_straps = read_dce_straps,
 585         .create_audio = create_audio,
 586         .create_stream_encoder = dce110_stream_encoder_create,
 587         .create_hwseq = dce110_hwseq_create,
 588 };
 589
 590 #define mi_inst_regs(id) { \
 591         MI_DCE11_REG_LIST(id), \
 592         .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
 593 }
 594 static const struct dce_mem_input_registers mi_regs[] = {
 595                 mi_inst_regs(0),
 596                 mi_inst_regs(1),
 597                 mi_inst_regs(2),
 598 };
 599
 600 static const struct dce_mem_input_shift mi_shifts = {
 601                 MI_DCE11_MASK_SH_LIST(__SHIFT),
 602                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
 603 };
 604
 605 static const struct dce_mem_input_mask mi_masks = {
 606                 MI_DCE11_MASK_SH_LIST(_MASK),
 607                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
 608 };
 609
 610
 611 static struct mem_input *dce110_mem_input_create(
 612         struct dc_context *ctx,
 613         uint32_t inst)
 614 {
 615         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 616                                                GFP_KERNEL);
 617
 618         if (!dce_mi) {
 619                 BREAK_TO_DEBUGGER();
 620                 return NULL;
 621         }
 622
 623         dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 624         dce_mi->wa.single_head_rdreq_dmif_limit = 3;
 625         return &dce_mi->base;
 626 }
 627
 628 static void dce110_transform_destroy(struct transform **xfm)
 629 {
 630         kfree(TO_DCE_TRANSFORM(*xfm));
 631         *xfm = NULL;
 632 }
 633
 634 static struct transform *dce110_transform_create(
 635         struct dc_context *ctx,
 636         uint32_t inst)
 637 {
 638         struct dce_transform *transform =
 639                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 640
 641         if (!transform)
 642                 return NULL;
 643
 644         dce_transform_construct(transform, ctx, inst,
 645                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 646         return &transform->base;
 647 }
 648
 649 static struct input_pixel_processor *dce110_ipp_create(
 650         struct dc_context *ctx, uint32_t inst)
 651 {
 652         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 653
 654         if (!ipp) {
 655                 BREAK_TO_DEBUGGER();
 656                 return NULL;
 657         }
 658
 659         dce_ipp_construct(ipp, ctx, inst,
 660                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 661         return &ipp->base;
 662 }
 663
 664 static const struct encoder_feature_support link_enc_feature = {
 665                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 666                 .max_hdmi_pixel_clock = 300000,
 667                 .flags.bits.IS_HBR2_CAPABLE = true,
 668                 .flags.bits.IS_TPS3_CAPABLE = true
 669 };
 670
 671 static struct link_encoder *dce110_link_encoder_create(
 672         const struct encoder_init_data *enc_init_data)
 673 {
 674         struct dce110_link_encoder *enc110 =
 675                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 676         int link_regs_id;
 677
 678         if (!enc110)
 679                 return NULL;
 680
 681         link_regs_id =
 682                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
 683
 684         dce110_link_encoder_construct(enc110,
 685                                       enc_init_data,
 686                                       &link_enc_feature,
 687                                       &link_enc_regs[link_regs_id],
 688                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 689                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 690         return &enc110->base;
 691 }
 692
 693 static struct panel_cntl *dce110_panel_cntl_create(const struct panel_cntl_init_data *init_data)
 694 {
 695         struct dce_panel_cntl *panel_cntl =
 696                 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
 697
 698         if (!panel_cntl)
 699                 return NULL;
 700
 701         dce_panel_cntl_construct(panel_cntl,
 702                         init_data,
 703                         &panel_cntl_regs[init_data->inst],
 704                         &panel_cntl_shift,
 705                         &panel_cntl_mask);
 706
 707         return &panel_cntl->base;
 708 }
 709
 710 static struct output_pixel_processor *dce110_opp_create(
 711         struct dc_context *ctx,
 712         uint32_t inst)
 713 {
 714         struct dce110_opp *opp =
 715                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 716
 717         if (!opp)
 718                 return NULL;
 719
 720         dce110_opp_construct(opp,
 721                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 722         return &opp->base;
 723 }
 724
 725 struct dce_aux *dce110_aux_engine_create(
 726         struct dc_context *ctx,
 727         uint32_t inst)
 728 {
 729         struct aux_engine_dce110 *aux_engine =
 730                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 731
 732         if (!aux_engine)
 733                 return NULL;
 734
 735         dce110_aux_engine_construct(aux_engine, ctx, inst,
 736                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 737                                     &aux_engine_regs[inst],
 738                                         &aux_mask,
 739                                         &aux_shift,
 740                                         ctx->dc->caps.extended_aux_timeout_support);
 741
 742         return &aux_engine->base;
 743 }
 744 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 745
 746 static const struct dce_i2c_registers i2c_hw_regs[] = {
 747                 i2c_inst_regs(1),
 748                 i2c_inst_regs(2),
 749                 i2c_inst_regs(3),
 750                 i2c_inst_regs(4),
 751                 i2c_inst_regs(5),
 752                 i2c_inst_regs(6),
 753 };
 754
 755 static const struct dce_i2c_shift i2c_shifts = {
 756                 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 757 };
 758
 759 static const struct dce_i2c_mask i2c_masks = {
 760                 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
 761 };
 762
 763 struct dce_i2c_hw *dce110_i2c_hw_create(
 764         struct dc_context *ctx,
 765         uint32_t inst)
 766 {
 767         struct dce_i2c_hw *dce_i2c_hw =
 768                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 769
 770         if (!dce_i2c_hw)
 771                 return NULL;
 772
 773         dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 774                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 775
 776         return dce_i2c_hw;
 777 }
 778 struct clock_source *dce110_clock_source_create(
 779         struct dc_context *ctx,
 780         struct dc_bios *bios,
 781         enum clock_source_id id,
 782         const struct dce110_clk_src_regs *regs,
 783         bool dp_clk_src)
 784 {
 785         struct dce110_clk_src *clk_src =
 786                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 787
 788         if (!clk_src)
 789                 return NULL;
 790
 791         if (dce110_clk_src_construct(clk_src, ctx, bios, id,
 792                         regs, &cs_shift, &cs_mask)) {
 793                 clk_src->base.dp_clk_src = dp_clk_src;
 794                 return &clk_src->base;
 795         }
 796
 797         kfree(clk_src);
 798         BREAK_TO_DEBUGGER();
 799         return NULL;
 800 }
 801
 802 void dce110_clock_source_destroy(struct clock_source **clk_src)
 803 {
 804         struct dce110_clk_src *dce110_clk_src;
 805
 806         if (!clk_src)
 807                 return;
 808
 809         dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src);
 810
 811         kfree(dce110_clk_src->dp_ss_params);
 812         kfree(dce110_clk_src->hdmi_ss_params);
 813         kfree(dce110_clk_src->dvi_ss_params);
 814
 815         kfree(dce110_clk_src);
 816         *clk_src = NULL;
 817 }
 818
 819 static void dce110_resource_destruct(struct dce110_resource_pool *pool)
 820 {
 821         unsigned int i;
 822
 823         for (i = 0; i < pool->base.pipe_count; i++) {
 824                 if (pool->base.opps[i] != NULL)
 825                         dce110_opp_destroy(&pool->base.opps[i]);
 826
 827                 if (pool->base.transforms[i] != NULL)
 828                         dce110_transform_destroy(&pool->base.transforms[i]);
 829
 830                 if (pool->base.ipps[i] != NULL)
 831                         dce_ipp_destroy(&pool->base.ipps[i]);
 832
 833                 if (pool->base.mis[i] != NULL) {
 834                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 835                         pool->base.mis[i] = NULL;
 836                 }
 837
 838                 if (pool->base.timing_generators[i] != NULL)    {
 839                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 840                         pool->base.timing_generators[i] = NULL;
 841                 }
 842         }
 843
 844         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 845                 if (pool->base.engines[i] != NULL)
 846                         dce110_engine_destroy(&pool->base.engines[i]);
 847                 if (pool->base.hw_i2cs[i] != NULL) {
 848                         kfree(pool->base.hw_i2cs[i]);
 849                         pool->base.hw_i2cs[i] = NULL;
 850                 }
 851                 if (pool->base.sw_i2cs[i] != NULL) {
 852                         kfree(pool->base.sw_i2cs[i]);
 853                         pool->base.sw_i2cs[i] = NULL;
 854                 }
 855         }
 856
 857         for (i = 0; i < pool->base.stream_enc_count; i++) {
 858                 if (pool->base.stream_enc[i] != NULL)
 859                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 860         }
 861
 862         for (i = 0; i < pool->base.clk_src_count; i++) {
 863                 if (pool->base.clock_sources[i] != NULL) {
 864                         dce110_clock_source_destroy(&pool->base.clock_sources[i]);
 865                 }
 866         }
 867
 868         if (pool->base.dp_clock_source != NULL)
 869                 dce110_clock_source_destroy(&pool->base.dp_clock_source);
 870
 871         for (i = 0; i < pool->base.audio_count; i++)    {
 872                 if (pool->base.audios[i] != NULL) {
 873                         dce_aud_destroy(&pool->base.audios[i]);
 874                 }
 875         }
 876
 877         if (pool->base.abm != NULL)
 878                 dce_abm_destroy(&pool->base.abm);
 879
 880         if (pool->base.dmcu != NULL)
 881                 dce_dmcu_destroy(&pool->base.dmcu);
 882
 883         if (pool->base.irqs != NULL) {
 884                 dal_irq_service_destroy(&pool->base.irqs);
 885         }
 886 }
 887
 888
 889 static void get_pixel_clock_parameters(
 890         const struct pipe_ctx *pipe_ctx,
 891         struct pixel_clk_params *pixel_clk_params)
 892 {
 893         const struct dc_stream_state *stream = pipe_ctx->stream;
 894
 895         /*TODO: is this halved for YCbCr 420? in that case we might want to move
 896          * the pixel clock normalization for hdmi up to here instead of doing it
 897          * in pll_adjust_pix_clk
 898          */
 899         pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
 900         pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
 901         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
 902         pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
 903         /* TODO: un-hardcode*/
 904         pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
 905                                                 LINK_RATE_REF_FREQ_IN_KHZ;
 906         pixel_clk_params->flags.ENABLE_SS = 0;
 907         pixel_clk_params->color_depth =
 908                 stream->timing.display_color_depth;
 909         pixel_clk_params->flags.DISPLAY_BLANKED = 1;
 910         pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==
 911                         PIXEL_ENCODING_YCBCR420);
 912         pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
 913         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 914                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
 915         }
 916         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
 917                 pixel_clk_params->requested_pix_clk_100hz  = pixel_clk_params->requested_pix_clk_100hz / 2;
 918         }
 919         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
 920                 pixel_clk_params->requested_pix_clk_100hz *= 2;
 921
 922 }
 923
 924 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
 925 {
 926         get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
 927         pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
 928                 pipe_ctx->clock_source,
 929                 &pipe_ctx->stream_res.pix_clk_params,
 930                 &pipe_ctx->pll_settings);
 931         resource_build_bit_depth_reduction_params(pipe_ctx->stream,
 932                         &pipe_ctx->stream->bit_depth_params);
 933         pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
 934 }
 935
 936 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)
 937 {
 938         if (pipe_ctx->pipe_idx != underlay_idx)
 939                 return true;
 940         if (!pipe_ctx->plane_state)
 941                 return false;
 942         if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 943                 return false;
 944         return true;
 945 }
 946
 947 static enum dc_status build_mapped_resource(
 948                 const struct dc *dc,
 949                 struct dc_state *context,
 950                 struct dc_stream_state *stream)
 951 {
 952         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
 953
 954         if (!pipe_ctx)
 955                 return DC_ERROR_UNEXPECTED;
 956
 957         if (!is_surface_pixel_format_supported(pipe_ctx,
 958                         dc->res_pool->underlay_pipe_index))
 959                 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
 960
 961         dce110_resource_build_pipe_hw_param(pipe_ctx);
 962
 963         /* TODO: validate audio ASIC caps, encoder */
 964
 965         resource_build_info_frame(pipe_ctx);
 966
 967         return DC_OK;
 968 }
 969
 970 static bool dce110_validate_bandwidth(
 971         struct dc *dc,
 972         struct dc_state *context,
 973         bool fast_validate)
 974 {
 975         bool result = false;
 976
 977         DC_LOG_BANDWIDTH_CALCS(
 978                 "%s: start",
 979                 __func__);
 980
 981         if (bw_calcs(
 982                         dc->ctx,
 983                         dc->bw_dceip,
 984                         dc->bw_vbios,
 985                         context->res_ctx.pipe_ctx,
 986                         dc->res_pool->pipe_count,
 987                         &context->bw_ctx.bw.dce))
 988                 result =  true;
 989
 990         if (!result)
 991                 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n",
 992                         __func__,
 993                         context->streams[0]->timing.h_addressable,
 994                         context->streams[0]->timing.v_addressable,
 995                         context->streams[0]->timing.pix_clk_100hz / 10);
 996
 997         if (memcmp(&dc->current_state->bw_ctx.bw.dce,
 998                         &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
 999
1000                 DC_LOG_BANDWIDTH_CALCS(
1001                         "%s: finish,\n"
1002                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
1003                         "stutMark_b: %d stutMark_a: %d\n"
1004                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
1005                         "stutMark_b: %d stutMark_a: %d\n"
1006                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
1007                         "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
1008                         "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
1009                         "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
1010                         ,
1011                         __func__,
1012                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
1013                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
1014                         context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
1015                         context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
1016                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
1017                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
1018                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
1019                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
1020                         context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
1021                         context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
1022                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
1023                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
1024                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
1025                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
1026                         context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
1027                         context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
1028                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
1029                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
1030                         context->bw_ctx.bw.dce.stutter_mode_enable,
1031                         context->bw_ctx.bw.dce.cpuc_state_change_enable,
1032                         context->bw_ctx.bw.dce.cpup_state_change_enable,
1033                         context->bw_ctx.bw.dce.nbp_state_change_enable,
1034                         context->bw_ctx.bw.dce.all_displays_in_sync,
1035                         context->bw_ctx.bw.dce.dispclk_khz,
1036                         context->bw_ctx.bw.dce.sclk_khz,
1037                         context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
1038                         context->bw_ctx.bw.dce.yclk_khz,
1039                         context->bw_ctx.bw.dce.blackout_recovery_time_us);
1040         }
1041         return result;
1042 }
1043
1044 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
1045                                      struct dc_caps *caps)
1046 {
1047         if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||
1048             ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))
1049                 return DC_FAIL_SURFACE_VALIDATE;
1050
1051         return DC_OK;
1052 }
1053
1054 static bool dce110_validate_surface_sets(
1055                 struct dc_state *context)
1056 {
1057         int i, j;
1058
1059         for (i = 0; i < context->stream_count; i++) {
1060                 if (context->stream_status[i].plane_count == 0)
1061                         continue;
1062
1063                 if (context->stream_status[i].plane_count > 2)
1064                         return false;
1065
1066                 for (j = 0; j < context->stream_status[i].plane_count; j++) {
1067                         struct dc_plane_state *plane =
1068                                 context->stream_status[i].plane_states[j];
1069
1070                         /* underlay validation */
1071                         if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1072
1073                                 if ((plane->src_rect.width > 1920 ||
1074                                         plane->src_rect.height > 1080))
1075                                         return false;
1076
1077                                 /* we don't have the logic to support underlay
1078                                  * only yet so block the use case where we get
1079                                  * NV12 plane as top layer
1080                                  */
1081                                 if (j == 0)
1082                                         return false;
1083
1084                                 /* irrespective of plane format,
1085                                  * stream should be RGB encoded
1086                                  */
1087                                 if (context->streams[i]->timing.pixel_encoding
1088                                                 != PIXEL_ENCODING_RGB)
1089                                         return false;
1090
1091                         }
1092
1093                 }
1094         }
1095
1096         return true;
1097 }
1098
1099 enum dc_status dce110_validate_global(
1100                 struct dc *dc,
1101                 struct dc_state *context)
1102 {
1103         if (!dce110_validate_surface_sets(context))
1104                 return DC_FAIL_SURFACE_VALIDATE;
1105
1106         return DC_OK;
1107 }
1108
1109 static enum dc_status dce110_add_stream_to_ctx(
1110                 struct dc *dc,
1111                 struct dc_state *new_ctx,
1112                 struct dc_stream_state *dc_stream)
1113 {
1114         enum dc_status result = DC_ERROR_UNEXPECTED;
1115
1116         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1117
1118         if (result == DC_OK)
1119                 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
1120
1121
1122         if (result == DC_OK)
1123                 result = build_mapped_resource(dc, new_ctx, dc_stream);
1124
1125         return result;
1126 }
1127
1128 static struct pipe_ctx *dce110_acquire_underlay(
1129                 struct dc_state *context,
1130                 const struct resource_pool *pool,
1131                 struct dc_stream_state *stream)
1132 {
1133         struct dc *dc = stream->ctx->dc;
1134         struct dce_hwseq *hws = dc->hwseq;
1135         struct resource_context *res_ctx = &context->res_ctx;
1136         unsigned int underlay_idx = pool->underlay_pipe_index;
1137         struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
1138
1139         if (res_ctx->pipe_ctx[underlay_idx].stream)
1140                 return NULL;
1141
1142         pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];
1143         pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
1144         /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
1145         pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
1146         pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
1147         pipe_ctx->pipe_idx = underlay_idx;
1148
1149         pipe_ctx->stream = stream;
1150
1151         if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {
1152                 struct tg_color black_color = {0};
1153                 struct dc_bios *dcb = dc->ctx->dc_bios;
1154
1155                 hws->funcs.enable_display_power_gating(
1156                                 dc,
1157                                 pipe_ctx->stream_res.tg->inst,
1158                                 dcb, PIPE_GATING_CONTROL_DISABLE);
1159
1160                 /*
1161                  * This is for powering on underlay, so crtc does not
1162                  * need to be enabled
1163                  */
1164
1165                 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
1166                                 &stream->timing,
1167                                 0,
1168                                 0,
1169                                 0,
1170                                 0,
1171                                 pipe_ctx->stream->signal,
1172                                 false);
1173
1174                 pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
1175                                 pipe_ctx->stream_res.tg,
1176                                 true,
1177                                 &stream->timing);
1178
1179                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
1180                                 stream->timing.h_total,
1181                                 stream->timing.v_total,
1182                                 stream->timing.pix_clk_100hz / 10,
1183                                 context->stream_count);
1184
1185                 color_space_to_black_color(dc,
1186                                 COLOR_SPACE_YCBCR601, &black_color);
1187                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1188                                 pipe_ctx->stream_res.tg,
1189                                 &black_color);
1190         }
1191
1192         return pipe_ctx;
1193 }
1194
1195 static void dce110_destroy_resource_pool(struct resource_pool **pool)
1196 {
1197         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1198
1199         dce110_resource_destruct(dce110_pool);
1200         kfree(dce110_pool);
1201         *pool = NULL;
1202 }
1203
1204 struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link(
1205                 struct resource_context *res_ctx,
1206                 const struct resource_pool *pool,
1207                 struct dc_stream_state *stream)
1208 {
1209         int i;
1210         int j = -1;
1211         struct dc_link *link = stream->link;
1212
1213         for (i = 0; i < pool->stream_enc_count; i++) {
1214                 if (!res_ctx->is_stream_enc_acquired[i] &&
1215                                 pool->stream_enc[i]) {
1216                         /* Store first available for MST second display
1217                          * in daisy chain use case
1218                          */
1219                         j = i;
1220                         if (pool->stream_enc[i]->id ==
1221                                         link->link_enc->preferred_engine)
1222                                 return pool->stream_enc[i];
1223                 }
1224         }
1225
1226         /*
1227          * For CZ and later, we can allow DIG FE and BE to differ for all display types
1228          */
1229
1230         if (j >= 0)
1231                 return pool->stream_enc[j];
1232
1233         return NULL;
1234 }
1235
1236
1237 static const struct resource_funcs dce110_res_pool_funcs = {
1238         .destroy = dce110_destroy_resource_pool,
1239         .link_enc_create = dce110_link_encoder_create,
1240         .panel_cntl_create = dce110_panel_cntl_create,
1241         .validate_bandwidth = dce110_validate_bandwidth,
1242         .validate_plane = dce110_validate_plane,
1243         .acquire_idle_pipe_for_layer = dce110_acquire_underlay,
1244         .add_stream_to_ctx = dce110_add_stream_to_ctx,
1245         .validate_global = dce110_validate_global,
1246         .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
1247 };
1248
1249 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
1250 {
1251         struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv),
1252                                                              GFP_KERNEL);
1253         struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv),
1254                                                     GFP_KERNEL);
1255         struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv),
1256                                                    GFP_KERNEL);
1257         struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv),
1258                                                  GFP_KERNEL);
1259
1260         if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) {
1261                 kfree(dce110_tgv);
1262                 kfree(dce110_xfmv);
1263                 kfree(dce110_miv);
1264                 kfree(dce110_oppv);
1265                 return false;
1266         }
1267
1268         dce110_opp_v_construct(dce110_oppv, ctx);
1269
1270         dce110_timing_generator_v_construct(dce110_tgv, ctx);
1271         dce110_mem_input_v_construct(dce110_miv, ctx);
1272         dce110_transform_v_construct(dce110_xfmv, ctx);
1273
1274         pool->opps[pool->pipe_count] = &dce110_oppv->base;
1275         pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
1276         pool->mis[pool->pipe_count] = &dce110_miv->base;
1277         pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
1278         pool->pipe_count++;
1279
1280         /* update the public caps to indicate an underlay is available */
1281         ctx->dc->caps.max_slave_planes = 1;
1282         ctx->dc->caps.max_slave_planes = 1;
1283
1284         return true;
1285 }
1286
1287 static void bw_calcs_data_update_from_pplib(struct dc *dc)
1288 {
1289         struct dm_pp_clock_levels clks = {0};
1290
1291         /*do system clock*/
1292         dm_pp_get_clock_levels_by_type(
1293                         dc->ctx,
1294                         DM_PP_CLOCK_TYPE_ENGINE_CLK,
1295                         &clks);
1296         /* convert all the clock fro kHz to fix point mHz */
1297         dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1298                         clks.clocks_in_khz[clks.num_levels-1], 1000);
1299         dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1300                         clks.clocks_in_khz[clks.num_levels/8], 1000);
1301         dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1302                         clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1303         dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1304                         clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1305         dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1306                         clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1307         dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1308                         clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1309         dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1310                         clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1311         dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1312                         clks.clocks_in_khz[0], 1000);
1313         dc->sclk_lvls = clks;
1314
1315         /*do display clock*/
1316         dm_pp_get_clock_levels_by_type(
1317                         dc->ctx,
1318                         DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1319                         &clks);
1320         dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(
1321                         clks.clocks_in_khz[clks.num_levels-1], 1000);
1322         dc->bw_vbios->mid_voltage_max_dispclk  = bw_frc_to_fixed(
1323                         clks.clocks_in_khz[clks.num_levels>>1], 1000);
1324         dc->bw_vbios->low_voltage_max_dispclk  = bw_frc_to_fixed(
1325                         clks.clocks_in_khz[0], 1000);
1326
1327         /*do memory clock*/
1328         dm_pp_get_clock_levels_by_type(
1329                         dc->ctx,
1330                         DM_PP_CLOCK_TYPE_MEMORY_CLK,
1331                         &clks);
1332
1333         dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1334                 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
1335         dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1336                 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ,
1337                 1000);
1338         dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1339                 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ,
1340                 1000);
1341 }
1342
1343 const struct resource_caps *dce110_resource_cap(
1344         struct hw_asic_id *asic_id)
1345 {
1346         if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
1347                 return &stoney_resource_cap;
1348         else
1349                 return &carrizo_resource_cap;
1350 }
1351
1352 static bool dce110_resource_construct(
1353         uint8_t num_virtual_links,
1354         struct dc *dc,
1355         struct dce110_resource_pool *pool,
1356         struct hw_asic_id asic_id)
1357 {
1358         unsigned int i;
1359         struct dc_context *ctx = dc->ctx;
1360         struct dc_bios *bp;
1361
1362         ctx->dc_bios->regs = &bios_regs;
1363
1364         pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
1365         pool->base.funcs = &dce110_res_pool_funcs;
1366
1367         /*************************************************
1368          *  Resource + asic cap harcoding                *
1369          *************************************************/
1370
1371         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1372         pool->base.underlay_pipe_index = pool->base.pipe_count;
1373         pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1374         dc->caps.max_downscale_ratio = 150;
1375         dc->caps.i2c_speed_in_khz = 100;
1376         dc->caps.max_cursor_size = 128;
1377         dc->caps.is_apu = true;
1378         dc->caps.extended_aux_timeout_support = false;
1379
1380         /*************************************************
1381          *  Create resources                             *
1382          *************************************************/
1383
1384         bp = ctx->dc_bios;
1385
1386         if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1387                 pool->base.dp_clock_source =
1388                                 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1389
1390                 pool->base.clock_sources[0] =
1391                                 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0,
1392                                                 &clk_src_regs[0], false);
1393                 pool->base.clock_sources[1] =
1394                                 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1,
1395                                                 &clk_src_regs[1], false);
1396
1397                 pool->base.clk_src_count = 2;
1398
1399                 /* TODO: find out if CZ support 3 PLLs */
1400         }
1401
1402         if (pool->base.dp_clock_source == NULL) {
1403                 dm_error("DC: failed to create dp clock source!\n");
1404                 BREAK_TO_DEBUGGER();
1405                 goto res_create_fail;
1406         }
1407
1408         for (i = 0; i < pool->base.clk_src_count; i++) {
1409                 if (pool->base.clock_sources[i] == NULL) {
1410                         dm_error("DC: failed to create clock sources!\n");
1411                         BREAK_TO_DEBUGGER();
1412                         goto res_create_fail;
1413                 }
1414         }
1415
1416         pool->base.dmcu = dce_dmcu_create(ctx,
1417                         &dmcu_regs,
1418                         &dmcu_shift,
1419                         &dmcu_mask);
1420         if (pool->base.dmcu == NULL) {
1421                 dm_error("DC: failed to create dmcu!\n");
1422                 BREAK_TO_DEBUGGER();
1423                 goto res_create_fail;
1424         }
1425
1426         pool->base.abm = dce_abm_create(ctx,
1427                         &abm_regs,
1428                         &abm_shift,
1429                         &abm_mask);
1430         if (pool->base.abm == NULL) {
1431                 dm_error("DC: failed to create abm!\n");
1432                 BREAK_TO_DEBUGGER();
1433                 goto res_create_fail;
1434         }
1435
1436         {
1437                 struct irq_service_init_data init_data;
1438                 init_data.ctx = dc->ctx;
1439                 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1440                 if (!pool->base.irqs)
1441                         goto res_create_fail;
1442         }
1443
1444         for (i = 0; i < pool->base.pipe_count; i++) {
1445                 pool->base.timing_generators[i] = dce110_timing_generator_create(
1446                                 ctx, i, &dce110_tg_offsets[i]);
1447                 if (pool->base.timing_generators[i] == NULL) {
1448                         BREAK_TO_DEBUGGER();
1449                         dm_error("DC: failed to create tg!\n");
1450                         goto res_create_fail;
1451                 }
1452
1453                 pool->base.mis[i] = dce110_mem_input_create(ctx, i);
1454                 if (pool->base.mis[i] == NULL) {
1455                         BREAK_TO_DEBUGGER();
1456                         dm_error(
1457                                 "DC: failed to create memory input!\n");
1458                         goto res_create_fail;
1459                 }
1460
1461                 pool->base.ipps[i] = dce110_ipp_create(ctx, i);
1462                 if (pool->base.ipps[i] == NULL) {
1463                         BREAK_TO_DEBUGGER();
1464                         dm_error(
1465                                 "DC: failed to create input pixel processor!\n");
1466                         goto res_create_fail;
1467                 }
1468
1469                 pool->base.transforms[i] = dce110_transform_create(ctx, i);
1470                 if (pool->base.transforms[i] == NULL) {
1471                         BREAK_TO_DEBUGGER();
1472                         dm_error(
1473                                 "DC: failed to create transform!\n");
1474                         goto res_create_fail;
1475                 }
1476
1477                 pool->base.opps[i] = dce110_opp_create(ctx, i);
1478                 if (pool->base.opps[i] == NULL) {
1479                         BREAK_TO_DEBUGGER();
1480                         dm_error(
1481                                 "DC: failed to create output pixel processor!\n");
1482                         goto res_create_fail;
1483                 }
1484         }
1485
1486         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1487                 pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
1488                 if (pool->base.engines[i] == NULL) {
1489                         BREAK_TO_DEBUGGER();
1490                         dm_error(
1491                                 "DC:failed to create aux engine!!\n");
1492                         goto res_create_fail;
1493                 }
1494                 pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i);
1495                 if (pool->base.hw_i2cs[i] == NULL) {
1496                         BREAK_TO_DEBUGGER();
1497                         dm_error(
1498                                 "DC:failed to create i2c engine!!\n");
1499                         goto res_create_fail;
1500                 }
1501                 pool->base.sw_i2cs[i] = NULL;
1502         }
1503
1504         if (dc->config.fbc_support)
1505                 dc->fbc_compressor = dce110_compressor_create(ctx);
1506
1507         if (!underlay_create(ctx, &pool->base))
1508                 goto res_create_fail;
1509
1510         if (!resource_construct(num_virtual_links, dc, &pool->base,
1511                         &res_create_funcs))
1512                 goto res_create_fail;
1513
1514         /* Create hardware sequencer */
1515         dce110_hw_sequencer_construct(dc);
1516
1517         dc->caps.max_planes =  pool->base.pipe_count;
1518
1519         for (i = 0; i < pool->base.underlay_pipe_index; ++i)
1520                 dc->caps.planes[i] = plane_cap;
1521
1522         dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap;
1523
1524         bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1525
1526         bw_calcs_data_update_from_pplib(dc);
1527
1528         return true;
1529
1530 res_create_fail:
1531         dce110_resource_destruct(pool);
1532         return false;
1533 }
1534
1535 struct resource_pool *dce110_create_resource_pool(
1536         uint8_t num_virtual_links,
1537         struct dc *dc,
1538         struct hw_asic_id asic_id)
1539 {
1540         struct dce110_resource_pool *pool =
1541                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1542
1543         if (!pool)
1544                 return NULL;
1545
1546         if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id))
1547                 return &pool->base;
1548
1549         kfree(pool);
1550         BREAK_TO_DEBUGGER();
1551         return NULL;
1552 }