drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "link_encoder.h"
  31 #include "stream_encoder.h"
  32
  33 #include "resource.h"
  34 #include "dce110/dce110_resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "dce/dce_audio.h"
  37 #include "dce110/dce110_timing_generator.h"
  38 #include "irq/dce110/irq_service_dce110.h"
  39 #include "dce110/dce110_timing_generator_v.h"
  40 #include "dce/dce_link_encoder.h"
  41 #include "dce/dce_stream_encoder.h"
  42 #include "dce/dce_mem_input.h"
  43 #include "dce110/dce110_mem_input_v.h"
  44 #include "dce/dce_ipp.h"
  45 #include "dce/dce_transform.h"
  46 #include "dce110/dce110_transform_v.h"
  47 #include "dce/dce_opp.h"
  48 #include "dce110/dce110_opp_v.h"
  49 #include "dce/dce_clock_source.h"
  50 #include "dce/dce_hwseq.h"
  51 #include "dce110/dce110_hw_sequencer.h"
  52 #include "dce/dce_aux.h"
  53 #include "dce/dce_abm.h"
  54 #include "dce/dce_dmcu.h"
  55 #include "dce/dce_i2c.h"
  56
  57 #define DC_LOGGER \
  58                 dc->ctx->logger
  59
  60 #include "dce110/dce110_compressor.h"
  61
  62 #include "reg_helper.h"
  63
  64 #include "dce/dce_11_0_d.h"
  65 #include "dce/dce_11_0_sh_mask.h"
  66
  67 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
  68 #include "gmc/gmc_8_2_d.h"
  69 #include "gmc/gmc_8_2_sh_mask.h"
  70 #endif
  71
  72 #ifndef mmDP_DPHY_INTERNAL_CTRL
  73         #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
  74         #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
  75         #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
  76         #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
  77         #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
  78         #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
  79         #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
  80         #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
  81         #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
  82         #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
  83 #endif
  84
  85 #ifndef mmBIOS_SCRATCH_2
  86         #define mmBIOS_SCRATCH_2 0x05CB
  87         #define mmBIOS_SCRATCH_3 0x05CC
  88         #define mmBIOS_SCRATCH_6 0x05CF
  89 #endif
  90
  91 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
  92         #define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
  93         #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
  94         #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
  95         #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
  96         #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
  97         #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
  98         #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
  99         #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
 100 #endif
 101
 102 #ifndef mmDP_DPHY_FAST_TRAINING
 103         #define mmDP_DPHY_FAST_TRAINING                         0x4ABC
 104         #define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
 105         #define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
 106         #define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
 107         #define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
 108         #define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
 109         #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
 110         #define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
 111 #endif
 112
 113 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE
 114         #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1
 115 #endif
 116
 117 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
 118         {
 119                 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 120                 .dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
 121         },
 122         {
 123                 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 124                 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 125         },
 126         {
 127                 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 128                 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 129         },
 130         {
 131                 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 132                 .dcp =  (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 133         },
 134         {
 135                 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 136                 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 137         },
 138         {
 139                 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 140                 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 141         }
 142 };
 143
 144 /* set register offset */
 145 #define SR(reg_name)\
 146         .reg_name = mm ## reg_name
 147
 148 /* set register offset with instance */
 149 #define SRI(reg_name, block, id)\
 150         .reg_name = mm ## block ## id ## _ ## reg_name
 151
 152 static const struct dce_dmcu_registers dmcu_regs = {
 153                 DMCU_DCE110_COMMON_REG_LIST()
 154 };
 155
 156 static const struct dce_dmcu_shift dmcu_shift = {
 157                 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
 158 };
 159
 160 static const struct dce_dmcu_mask dmcu_mask = {
 161                 DMCU_MASK_SH_LIST_DCE110(_MASK)
 162 };
 163
 164 static const struct dce_abm_registers abm_regs = {
 165                 ABM_DCE110_COMMON_REG_LIST()
 166 };
 167
 168 static const struct dce_abm_shift abm_shift = {
 169                 ABM_MASK_SH_LIST_DCE110(__SHIFT)
 170 };
 171
 172 static const struct dce_abm_mask abm_mask = {
 173                 ABM_MASK_SH_LIST_DCE110(_MASK)
 174 };
 175
 176 #define ipp_regs(id)\
 177 [id] = {\
 178                 IPP_DCE110_REG_LIST_DCE_BASE(id)\
 179 }
 180
 181 static const struct dce_ipp_registers ipp_regs[] = {
 182                 ipp_regs(0),
 183                 ipp_regs(1),
 184                 ipp_regs(2)
 185 };
 186
 187 static const struct dce_ipp_shift ipp_shift = {
 188                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 189 };
 190
 191 static const struct dce_ipp_mask ipp_mask = {
 192                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 193 };
 194
 195 #define transform_regs(id)\
 196 [id] = {\
 197                 XFM_COMMON_REG_LIST_DCE110(id)\
 198 }
 199
 200 static const struct dce_transform_registers xfm_regs[] = {
 201                 transform_regs(0),
 202                 transform_regs(1),
 203                 transform_regs(2)
 204 };
 205
 206 static const struct dce_transform_shift xfm_shift = {
 207                 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 208 };
 209
 210 static const struct dce_transform_mask xfm_mask = {
 211                 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
 212 };
 213
 214 #define aux_regs(id)\
 215 [id] = {\
 216         AUX_REG_LIST(id)\
 217 }
 218
 219 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 220                 aux_regs(0),
 221                 aux_regs(1),
 222                 aux_regs(2),
 223                 aux_regs(3),
 224                 aux_regs(4),
 225                 aux_regs(5)
 226 };
 227
 228 #define hpd_regs(id)\
 229 [id] = {\
 230         HPD_REG_LIST(id)\
 231 }
 232
 233 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 234                 hpd_regs(0),
 235                 hpd_regs(1),
 236                 hpd_regs(2),
 237                 hpd_regs(3),
 238                 hpd_regs(4),
 239                 hpd_regs(5)
 240 };
 241
 242
 243 #define link_regs(id)\
 244 [id] = {\
 245         LE_DCE110_REG_LIST(id)\
 246 }
 247
 248 static const struct dce110_link_enc_registers link_enc_regs[] = {
 249         link_regs(0),
 250         link_regs(1),
 251         link_regs(2),
 252         link_regs(3),
 253         link_regs(4),
 254         link_regs(5),
 255         link_regs(6),
 256 };
 257
 258 #define stream_enc_regs(id)\
 259 [id] = {\
 260         SE_COMMON_REG_LIST(id),\
 261         .TMDS_CNTL = 0,\
 262 }
 263
 264 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 265         stream_enc_regs(0),
 266         stream_enc_regs(1),
 267         stream_enc_regs(2)
 268 };
 269
 270 static const struct dce_stream_encoder_shift se_shift = {
 271                 SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 272 };
 273
 274 static const struct dce_stream_encoder_mask se_mask = {
 275                 SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
 276 };
 277
 278 static const struct dce110_aux_registers_shift aux_shift = {
 279         DCE_AUX_MASK_SH_LIST(__SHIFT)
 280 };
 281
 282 static const struct dce110_aux_registers_mask aux_mask = {
 283         DCE_AUX_MASK_SH_LIST(_MASK)
 284 };
 285
 286 #define opp_regs(id)\
 287 [id] = {\
 288         OPP_DCE_110_REG_LIST(id),\
 289 }
 290
 291 static const struct dce_opp_registers opp_regs[] = {
 292         opp_regs(0),
 293         opp_regs(1),
 294         opp_regs(2),
 295         opp_regs(3),
 296         opp_regs(4),
 297         opp_regs(5)
 298 };
 299
 300 static const struct dce_opp_shift opp_shift = {
 301         OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT)
 302 };
 303
 304 static const struct dce_opp_mask opp_mask = {
 305         OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK)
 306 };
 307
 308 #define aux_engine_regs(id)\
 309 [id] = {\
 310         AUX_COMMON_REG_LIST(id), \
 311         .AUX_RESET_MASK = 0 \
 312 }
 313
 314 static const struct dce110_aux_registers aux_engine_regs[] = {
 315                 aux_engine_regs(0),
 316                 aux_engine_regs(1),
 317                 aux_engine_regs(2),
 318                 aux_engine_regs(3),
 319                 aux_engine_regs(4),
 320                 aux_engine_regs(5)
 321 };
 322
 323 #define audio_regs(id)\
 324 [id] = {\
 325         AUD_COMMON_REG_LIST(id)\
 326 }
 327
 328 static const struct dce_audio_registers audio_regs[] = {
 329         audio_regs(0),
 330         audio_regs(1),
 331         audio_regs(2),
 332         audio_regs(3),
 333         audio_regs(4),
 334         audio_regs(5),
 335         audio_regs(6),
 336 };
 337
 338 static const struct dce_audio_shift audio_shift = {
 339                 AUD_COMMON_MASK_SH_LIST(__SHIFT)
 340 };
 341
 342 static const struct dce_audio_mask audio_mask = {
 343                 AUD_COMMON_MASK_SH_LIST(_MASK)
 344 };
 345
 346 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
 347
 348
 349 #define clk_src_regs(id)\
 350 [id] = {\
 351         CS_COMMON_REG_LIST_DCE_100_110(id),\
 352 }
 353
 354 static const struct dce110_clk_src_regs clk_src_regs[] = {
 355         clk_src_regs(0),
 356         clk_src_regs(1),
 357         clk_src_regs(2)
 358 };
 359
 360 static const struct dce110_clk_src_shift cs_shift = {
 361                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 362 };
 363
 364 static const struct dce110_clk_src_mask cs_mask = {
 365                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 366 };
 367
 368 static const struct bios_registers bios_regs = {
 369         .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
 370         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 371 };
 372
 373 static const struct resource_caps carrizo_resource_cap = {
 374                 .num_timing_generator = 3,
 375                 .num_video_plane = 1,
 376                 .num_audio = 3,
 377                 .num_stream_encoder = 3,
 378                 .num_pll = 2,
 379                 .num_ddc = 3,
 380 };
 381
 382 static const struct resource_caps stoney_resource_cap = {
 383                 .num_timing_generator = 2,
 384                 .num_video_plane = 1,
 385                 .num_audio = 3,
 386                 .num_stream_encoder = 3,
 387                 .num_pll = 2,
 388                 .num_ddc = 3,
 389 };
 390
 391 static const struct dc_plane_cap plane_cap = {
 392                 .type = DC_PLANE_TYPE_DCE_RGB,
 393                 .blends_with_below = true,
 394                 .blends_with_above = true,
 395                 .per_pixel_alpha = 1,
 396
 397                 .pixel_format_support = {
 398                                 .argb8888 = true,
 399                                 .nv12 = false,
 400                                 .fp16 = false
 401                 },
 402
 403                 .max_upscale_factor = {
 404                                 .argb8888 = 16000,
 405                                 .nv12 = 1,
 406                                 .fp16 = 1
 407                 },
 408
 409                 .max_downscale_factor = {
 410                                 .argb8888 = 250,
 411                                 .nv12 = 1,
 412                                 .fp16 = 1
 413                 }
 414 };
 415
 416 static const struct dc_plane_cap underlay_plane_cap = {
 417                 .type = DC_PLANE_TYPE_DCE_UNDERLAY,
 418                 .blends_with_above = true,
 419                 .per_pixel_alpha = 1,
 420
 421                 .pixel_format_support = {
 422                                 .argb8888 = false,
 423                                 .nv12 = true,
 424                                 .fp16 = false
 425                 },
 426
 427                 .max_upscale_factor = {
 428                                 .argb8888 = 1,
 429                                 .nv12 = 16000,
 430                                 .fp16 = 1
 431                 },
 432
 433                 .max_downscale_factor = {
 434                                 .argb8888 = 1,
 435                                 .nv12 = 250,
 436                                 .fp16 = 1
 437                 }
 438 };
 439
 440 #define CTX  ctx
 441 #define REG(reg) mm ## reg
 442
 443 #ifndef mmCC_DC_HDMI_STRAPS
 444 #define mmCC_DC_HDMI_STRAPS 0x4819
 445 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 446 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 447 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 448 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 449 #endif
 450
 451 static int map_transmitter_id_to_phy_instance(
 452         enum transmitter transmitter)
 453 {
 454         switch (transmitter) {
 455         case TRANSMITTER_UNIPHY_A:
 456                 return 0;
 457         break;
 458         case TRANSMITTER_UNIPHY_B:
 459                 return 1;
 460         break;
 461         case TRANSMITTER_UNIPHY_C:
 462                 return 2;
 463         break;
 464         case TRANSMITTER_UNIPHY_D:
 465                 return 3;
 466         break;
 467         case TRANSMITTER_UNIPHY_E:
 468                 return 4;
 469         break;
 470         case TRANSMITTER_UNIPHY_F:
 471                 return 5;
 472         break;
 473         case TRANSMITTER_UNIPHY_G:
 474                 return 6;
 475         break;
 476         default:
 477                 ASSERT(0);
 478                 return 0;
 479         }
 480 }
 481
 482 static void read_dce_straps(
 483         struct dc_context *ctx,
 484         struct resource_straps *straps)
 485 {
 486         REG_GET_2(CC_DC_HDMI_STRAPS,
 487                         HDMI_DISABLE, &straps->hdmi_disable,
 488                         AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 489
 490         REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 491 }
 492
 493 static struct audio *create_audio(
 494                 struct dc_context *ctx, unsigned int inst)
 495 {
 496         return dce_audio_create(ctx, inst,
 497                         &audio_regs[inst], &audio_shift, &audio_mask);
 498 }
 499
 500 static struct timing_generator *dce110_timing_generator_create(
 501                 struct dc_context *ctx,
 502                 uint32_t instance,
 503                 const struct dce110_timing_generator_offsets *offsets)
 504 {
 505         struct dce110_timing_generator *tg110 =
 506                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 507
 508         if (!tg110)
 509                 return NULL;
 510
 511         dce110_timing_generator_construct(tg110, ctx, instance, offsets);
 512         return &tg110->base;
 513 }
 514
 515 static struct stream_encoder *dce110_stream_encoder_create(
 516         enum engine_id eng_id,
 517         struct dc_context *ctx)
 518 {
 519         struct dce110_stream_encoder *enc110 =
 520                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 521
 522         if (!enc110)
 523                 return NULL;
 524
 525         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 526                                         &stream_enc_regs[eng_id],
 527                                         &se_shift, &se_mask);
 528         return &enc110->base;
 529 }
 530
 531 #define SRII(reg_name, block, id)\
 532         .reg_name[id] = mm ## block ## id ## _ ## reg_name
 533
 534 static const struct dce_hwseq_registers hwseq_stoney_reg = {
 535                 HWSEQ_ST_REG_LIST()
 536 };
 537
 538 static const struct dce_hwseq_registers hwseq_cz_reg = {
 539                 HWSEQ_CZ_REG_LIST()
 540 };
 541
 542 static const struct dce_hwseq_shift hwseq_shift = {
 543                 HWSEQ_DCE11_MASK_SH_LIST(__SHIFT),
 544 };
 545
 546 static const struct dce_hwseq_mask hwseq_mask = {
 547                 HWSEQ_DCE11_MASK_SH_LIST(_MASK),
 548 };
 549
 550 static struct dce_hwseq *dce110_hwseq_create(
 551         struct dc_context *ctx)
 552 {
 553         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 554
 555         if (hws) {
 556                 hws->ctx = ctx;
 557                 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
 558                                 &hwseq_stoney_reg : &hwseq_cz_reg;
 559                 hws->shifts = &hwseq_shift;
 560                 hws->masks = &hwseq_mask;
 561                 hws->wa.blnd_crtc_trigger = true;
 562         }
 563         return hws;
 564 }
 565
 566 static const struct resource_create_funcs res_create_funcs = {
 567         .read_dce_straps = read_dce_straps,
 568         .create_audio = create_audio,
 569         .create_stream_encoder = dce110_stream_encoder_create,
 570         .create_hwseq = dce110_hwseq_create,
 571 };
 572
 573 #define mi_inst_regs(id) { \
 574         MI_DCE11_REG_LIST(id), \
 575         .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
 576 }
 577 static const struct dce_mem_input_registers mi_regs[] = {
 578                 mi_inst_regs(0),
 579                 mi_inst_regs(1),
 580                 mi_inst_regs(2),
 581 };
 582
 583 static const struct dce_mem_input_shift mi_shifts = {
 584                 MI_DCE11_MASK_SH_LIST(__SHIFT),
 585                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
 586 };
 587
 588 static const struct dce_mem_input_mask mi_masks = {
 589                 MI_DCE11_MASK_SH_LIST(_MASK),
 590                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
 591 };
 592
 593
 594 static struct mem_input *dce110_mem_input_create(
 595         struct dc_context *ctx,
 596         uint32_t inst)
 597 {
 598         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 599                                                GFP_KERNEL);
 600
 601         if (!dce_mi) {
 602                 BREAK_TO_DEBUGGER();
 603                 return NULL;
 604         }
 605
 606         dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 607         dce_mi->wa.single_head_rdreq_dmif_limit = 3;
 608         return &dce_mi->base;
 609 }
 610
 611 static void dce110_transform_destroy(struct transform **xfm)
 612 {
 613         kfree(TO_DCE_TRANSFORM(*xfm));
 614         *xfm = NULL;
 615 }
 616
 617 static struct transform *dce110_transform_create(
 618         struct dc_context *ctx,
 619         uint32_t inst)
 620 {
 621         struct dce_transform *transform =
 622                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 623
 624         if (!transform)
 625                 return NULL;
 626
 627         dce_transform_construct(transform, ctx, inst,
 628                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 629         return &transform->base;
 630 }
 631
 632 static struct input_pixel_processor *dce110_ipp_create(
 633         struct dc_context *ctx, uint32_t inst)
 634 {
 635         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 636
 637         if (!ipp) {
 638                 BREAK_TO_DEBUGGER();
 639                 return NULL;
 640         }
 641
 642         dce_ipp_construct(ipp, ctx, inst,
 643                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 644         return &ipp->base;
 645 }
 646
 647 static const struct encoder_feature_support link_enc_feature = {
 648                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 649                 .max_hdmi_pixel_clock = 300000,
 650                 .flags.bits.IS_HBR2_CAPABLE = true,
 651                 .flags.bits.IS_TPS3_CAPABLE = true
 652 };
 653
 654 static struct link_encoder *dce110_link_encoder_create(
 655         const struct encoder_init_data *enc_init_data)
 656 {
 657         struct dce110_link_encoder *enc110 =
 658                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 659         int link_regs_id;
 660
 661         if (!enc110)
 662                 return NULL;
 663
 664         link_regs_id =
 665                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
 666
 667         dce110_link_encoder_construct(enc110,
 668                                       enc_init_data,
 669                                       &link_enc_feature,
 670                                       &link_enc_regs[link_regs_id],
 671                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 672                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 673         return &enc110->base;
 674 }
 675
 676 static struct output_pixel_processor *dce110_opp_create(
 677         struct dc_context *ctx,
 678         uint32_t inst)
 679 {
 680         struct dce110_opp *opp =
 681                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 682
 683         if (!opp)
 684                 return NULL;
 685
 686         dce110_opp_construct(opp,
 687                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 688         return &opp->base;
 689 }
 690
 691 struct dce_aux *dce110_aux_engine_create(
 692         struct dc_context *ctx,
 693         uint32_t inst)
 694 {
 695         struct aux_engine_dce110 *aux_engine =
 696                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 697
 698         if (!aux_engine)
 699                 return NULL;
 700
 701         dce110_aux_engine_construct(aux_engine, ctx, inst,
 702                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 703                                     &aux_engine_regs[inst],
 704                                         &aux_mask,
 705                                         &aux_shift,
 706                                         ctx->dc->caps.extended_aux_timeout_support);
 707
 708         return &aux_engine->base;
 709 }
 710 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 711
 712 static const struct dce_i2c_registers i2c_hw_regs[] = {
 713                 i2c_inst_regs(1),
 714                 i2c_inst_regs(2),
 715                 i2c_inst_regs(3),
 716                 i2c_inst_regs(4),
 717                 i2c_inst_regs(5),
 718                 i2c_inst_regs(6),
 719 };
 720
 721 static const struct dce_i2c_shift i2c_shifts = {
 722                 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 723 };
 724
 725 static const struct dce_i2c_mask i2c_masks = {
 726                 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
 727 };
 728
 729 struct dce_i2c_hw *dce110_i2c_hw_create(
 730         struct dc_context *ctx,
 731         uint32_t inst)
 732 {
 733         struct dce_i2c_hw *dce_i2c_hw =
 734                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 735
 736         if (!dce_i2c_hw)
 737                 return NULL;
 738
 739         dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 740                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 741
 742         return dce_i2c_hw;
 743 }
 744 struct clock_source *dce110_clock_source_create(
 745         struct dc_context *ctx,
 746         struct dc_bios *bios,
 747         enum clock_source_id id,
 748         const struct dce110_clk_src_regs *regs,
 749         bool dp_clk_src)
 750 {
 751         struct dce110_clk_src *clk_src =
 752                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 753
 754         if (!clk_src)
 755                 return NULL;
 756
 757         if (dce110_clk_src_construct(clk_src, ctx, bios, id,
 758                         regs, &cs_shift, &cs_mask)) {
 759                 clk_src->base.dp_clk_src = dp_clk_src;
 760                 return &clk_src->base;
 761         }
 762
 763         kfree(clk_src);
 764         BREAK_TO_DEBUGGER();
 765         return NULL;
 766 }
 767
 768 void dce110_clock_source_destroy(struct clock_source **clk_src)
 769 {
 770         struct dce110_clk_src *dce110_clk_src;
 771
 772         if (!clk_src)
 773                 return;
 774
 775         dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src);
 776
 777         kfree(dce110_clk_src->dp_ss_params);
 778         kfree(dce110_clk_src->hdmi_ss_params);
 779         kfree(dce110_clk_src->dvi_ss_params);
 780
 781         kfree(dce110_clk_src);
 782         *clk_src = NULL;
 783 }
 784
 785 static void dce110_resource_destruct(struct dce110_resource_pool *pool)
 786 {
 787         unsigned int i;
 788
 789         for (i = 0; i < pool->base.pipe_count; i++) {
 790                 if (pool->base.opps[i] != NULL)
 791                         dce110_opp_destroy(&pool->base.opps[i]);
 792
 793                 if (pool->base.transforms[i] != NULL)
 794                         dce110_transform_destroy(&pool->base.transforms[i]);
 795
 796                 if (pool->base.ipps[i] != NULL)
 797                         dce_ipp_destroy(&pool->base.ipps[i]);
 798
 799                 if (pool->base.mis[i] != NULL) {
 800                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 801                         pool->base.mis[i] = NULL;
 802                 }
 803
 804                 if (pool->base.timing_generators[i] != NULL)    {
 805                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 806                         pool->base.timing_generators[i] = NULL;
 807                 }
 808         }
 809
 810         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 811                 if (pool->base.engines[i] != NULL)
 812                         dce110_engine_destroy(&pool->base.engines[i]);
 813                 if (pool->base.hw_i2cs[i] != NULL) {
 814                         kfree(pool->base.hw_i2cs[i]);
 815                         pool->base.hw_i2cs[i] = NULL;
 816                 }
 817                 if (pool->base.sw_i2cs[i] != NULL) {
 818                         kfree(pool->base.sw_i2cs[i]);
 819                         pool->base.sw_i2cs[i] = NULL;
 820                 }
 821         }
 822
 823         for (i = 0; i < pool->base.stream_enc_count; i++) {
 824                 if (pool->base.stream_enc[i] != NULL)
 825                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 826         }
 827
 828         for (i = 0; i < pool->base.clk_src_count; i++) {
 829                 if (pool->base.clock_sources[i] != NULL) {
 830                         dce110_clock_source_destroy(&pool->base.clock_sources[i]);
 831                 }
 832         }
 833
 834         if (pool->base.dp_clock_source != NULL)
 835                 dce110_clock_source_destroy(&pool->base.dp_clock_source);
 836
 837         for (i = 0; i < pool->base.audio_count; i++)    {
 838                 if (pool->base.audios[i] != NULL) {
 839                         dce_aud_destroy(&pool->base.audios[i]);
 840                 }
 841         }
 842
 843         if (pool->base.abm != NULL)
 844                 dce_abm_destroy(&pool->base.abm);
 845
 846         if (pool->base.dmcu != NULL)
 847                 dce_dmcu_destroy(&pool->base.dmcu);
 848
 849         if (pool->base.irqs != NULL) {
 850                 dal_irq_service_destroy(&pool->base.irqs);
 851         }
 852 }
 853
 854
 855 static void get_pixel_clock_parameters(
 856         const struct pipe_ctx *pipe_ctx,
 857         struct pixel_clk_params *pixel_clk_params)
 858 {
 859         const struct dc_stream_state *stream = pipe_ctx->stream;
 860
 861         /*TODO: is this halved for YCbCr 420? in that case we might want to move
 862          * the pixel clock normalization for hdmi up to here instead of doing it
 863          * in pll_adjust_pix_clk
 864          */
 865         pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
 866         pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
 867         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
 868         pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
 869         /* TODO: un-hardcode*/
 870         pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
 871                                                 LINK_RATE_REF_FREQ_IN_KHZ;
 872         pixel_clk_params->flags.ENABLE_SS = 0;
 873         pixel_clk_params->color_depth =
 874                 stream->timing.display_color_depth;
 875         pixel_clk_params->flags.DISPLAY_BLANKED = 1;
 876         pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==
 877                         PIXEL_ENCODING_YCBCR420);
 878         pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
 879         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 880                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
 881         }
 882         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
 883                 pixel_clk_params->requested_pix_clk_100hz  = pixel_clk_params->requested_pix_clk_100hz / 2;
 884         }
 885         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
 886                 pixel_clk_params->requested_pix_clk_100hz *= 2;
 887
 888 }
 889
 890 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
 891 {
 892         get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
 893         pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
 894                 pipe_ctx->clock_source,
 895                 &pipe_ctx->stream_res.pix_clk_params,
 896                 &pipe_ctx->pll_settings);
 897         resource_build_bit_depth_reduction_params(pipe_ctx->stream,
 898                         &pipe_ctx->stream->bit_depth_params);
 899         pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
 900 }
 901
 902 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)
 903 {
 904         if (pipe_ctx->pipe_idx != underlay_idx)
 905                 return true;
 906         if (!pipe_ctx->plane_state)
 907                 return false;
 908         if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 909                 return false;
 910         return true;
 911 }
 912
 913 static enum dc_status build_mapped_resource(
 914                 const struct dc *dc,
 915                 struct dc_state *context,
 916                 struct dc_stream_state *stream)
 917 {
 918         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
 919
 920         if (!pipe_ctx)
 921                 return DC_ERROR_UNEXPECTED;
 922
 923         if (!is_surface_pixel_format_supported(pipe_ctx,
 924                         dc->res_pool->underlay_pipe_index))
 925                 return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
 926
 927         dce110_resource_build_pipe_hw_param(pipe_ctx);
 928
 929         /* TODO: validate audio ASIC caps, encoder */
 930
 931         resource_build_info_frame(pipe_ctx);
 932
 933         return DC_OK;
 934 }
 935
 936 static bool dce110_validate_bandwidth(
 937         struct dc *dc,
 938         struct dc_state *context,
 939         bool fast_validate)
 940 {
 941         bool result = false;
 942
 943         DC_LOG_BANDWIDTH_CALCS(
 944                 "%s: start",
 945                 __func__);
 946
 947         if (bw_calcs(
 948                         dc->ctx,
 949                         dc->bw_dceip,
 950                         dc->bw_vbios,
 951                         context->res_ctx.pipe_ctx,
 952                         dc->res_pool->pipe_count,
 953                         &context->bw_ctx.bw.dce))
 954                 result =  true;
 955
 956         if (!result)
 957                 DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n",
 958                         __func__,
 959                         context->streams[0]->timing.h_addressable,
 960                         context->streams[0]->timing.v_addressable,
 961                         context->streams[0]->timing.pix_clk_100hz / 10);
 962
 963         if (memcmp(&dc->current_state->bw_ctx.bw.dce,
 964                         &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
 965
 966                 DC_LOG_BANDWIDTH_CALCS(
 967                         "%s: finish,\n"
 968                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 969                         "stutMark_b: %d stutMark_a: %d\n"
 970                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 971                         "stutMark_b: %d stutMark_a: %d\n"
 972                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 973                         "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
 974                         "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
 975                         "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
 976                         ,
 977                         __func__,
 978                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
 979                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
 980                         context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
 981                         context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
 982                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
 983                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
 984                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
 985                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
 986                         context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
 987                         context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
 988                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
 989                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
 990                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
 991                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
 992                         context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
 993                         context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
 994                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
 995                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
 996                         context->bw_ctx.bw.dce.stutter_mode_enable,
 997                         context->bw_ctx.bw.dce.cpuc_state_change_enable,
 998                         context->bw_ctx.bw.dce.cpup_state_change_enable,
 999                         context->bw_ctx.bw.dce.nbp_state_change_enable,
1000                         context->bw_ctx.bw.dce.all_displays_in_sync,
1001                         context->bw_ctx.bw.dce.dispclk_khz,
1002                         context->bw_ctx.bw.dce.sclk_khz,
1003                         context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
1004                         context->bw_ctx.bw.dce.yclk_khz,
1005                         context->bw_ctx.bw.dce.blackout_recovery_time_us);
1006         }
1007         return result;
1008 }
1009
1010 enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
1011                                      struct dc_caps *caps)
1012 {
1013         if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||
1014             ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))
1015                 return DC_FAIL_SURFACE_VALIDATE;
1016
1017         return DC_OK;
1018 }
1019
1020 static bool dce110_validate_surface_sets(
1021                 struct dc_state *context)
1022 {
1023         int i, j;
1024
1025         for (i = 0; i < context->stream_count; i++) {
1026                 if (context->stream_status[i].plane_count == 0)
1027                         continue;
1028
1029                 if (context->stream_status[i].plane_count > 2)
1030                         return false;
1031
1032                 for (j = 0; j < context->stream_status[i].plane_count; j++) {
1033                         struct dc_plane_state *plane =
1034                                 context->stream_status[i].plane_states[j];
1035
1036                         /* underlay validation */
1037                         if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1038
1039                                 if ((plane->src_rect.width > 1920 ||
1040                                         plane->src_rect.height > 1080))
1041                                         return false;
1042
1043                                 /* we don't have the logic to support underlay
1044                                  * only yet so block the use case where we get
1045                                  * NV12 plane as top layer
1046                                  */
1047                                 if (j == 0)
1048                                         return false;
1049
1050                                 /* irrespective of plane format,
1051                                  * stream should be RGB encoded
1052                                  */
1053                                 if (context->streams[i]->timing.pixel_encoding
1054                                                 != PIXEL_ENCODING_RGB)
1055                                         return false;
1056
1057                         }
1058
1059                 }
1060         }
1061
1062         return true;
1063 }
1064
1065 enum dc_status dce110_validate_global(
1066                 struct dc *dc,
1067                 struct dc_state *context)
1068 {
1069         if (!dce110_validate_surface_sets(context))
1070                 return DC_FAIL_SURFACE_VALIDATE;
1071
1072         return DC_OK;
1073 }
1074
1075 static enum dc_status dce110_add_stream_to_ctx(
1076                 struct dc *dc,
1077                 struct dc_state *new_ctx,
1078                 struct dc_stream_state *dc_stream)
1079 {
1080         enum dc_status result = DC_ERROR_UNEXPECTED;
1081
1082         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1083
1084         if (result == DC_OK)
1085                 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
1086
1087
1088         if (result == DC_OK)
1089                 result = build_mapped_resource(dc, new_ctx, dc_stream);
1090
1091         return result;
1092 }
1093
1094 static struct pipe_ctx *dce110_acquire_underlay(
1095                 struct dc_state *context,
1096                 const struct resource_pool *pool,
1097                 struct dc_stream_state *stream)
1098 {
1099         struct dc *dc = stream->ctx->dc;
1100         struct resource_context *res_ctx = &context->res_ctx;
1101         unsigned int underlay_idx = pool->underlay_pipe_index;
1102         struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
1103
1104         if (res_ctx->pipe_ctx[underlay_idx].stream)
1105                 return NULL;
1106
1107         pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];
1108         pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
1109         /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
1110         pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
1111         pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
1112         pipe_ctx->pipe_idx = underlay_idx;
1113
1114         pipe_ctx->stream = stream;
1115
1116         if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {
1117                 struct tg_color black_color = {0};
1118                 struct dc_bios *dcb = dc->ctx->dc_bios;
1119
1120                 dc->hwss.enable_display_power_gating(
1121                                 dc,
1122                                 pipe_ctx->stream_res.tg->inst,
1123                                 dcb, PIPE_GATING_CONTROL_DISABLE);
1124
1125                 /*
1126                  * This is for powering on underlay, so crtc does not
1127                  * need to be enabled
1128                  */
1129
1130                 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
1131                                 &stream->timing,
1132                                 0,
1133                                 0,
1134                                 0,
1135                                 0,
1136                                 pipe_ctx->stream->signal,
1137                                 false);
1138
1139                 pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
1140                                 pipe_ctx->stream_res.tg,
1141                                 true,
1142                                 &stream->timing);
1143
1144                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
1145                                 stream->timing.h_total,
1146                                 stream->timing.v_total,
1147                                 stream->timing.pix_clk_100hz / 10,
1148                                 context->stream_count);
1149
1150                 color_space_to_black_color(dc,
1151                                 COLOR_SPACE_YCBCR601, &black_color);
1152                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1153                                 pipe_ctx->stream_res.tg,
1154                                 &black_color);
1155         }
1156
1157         return pipe_ctx;
1158 }
1159
1160 static void dce110_destroy_resource_pool(struct resource_pool **pool)
1161 {
1162         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1163
1164         dce110_resource_destruct(dce110_pool);
1165         kfree(dce110_pool);
1166         *pool = NULL;
1167 }
1168
1169 struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link(
1170                 struct resource_context *res_ctx,
1171                 const struct resource_pool *pool,
1172                 struct dc_stream_state *stream)
1173 {
1174         int i;
1175         int j = -1;
1176         struct dc_link *link = stream->link;
1177
1178         for (i = 0; i < pool->stream_enc_count; i++) {
1179                 if (!res_ctx->is_stream_enc_acquired[i] &&
1180                                 pool->stream_enc[i]) {
1181                         /* Store first available for MST second display
1182                          * in daisy chain use case
1183                          */
1184                         j = i;
1185                         if (pool->stream_enc[i]->id ==
1186                                         link->link_enc->preferred_engine)
1187                                 return pool->stream_enc[i];
1188                 }
1189         }
1190
1191         /*
1192          * For CZ and later, we can allow DIG FE and BE to differ for all display types
1193          */
1194
1195         if (j >= 0)
1196                 return pool->stream_enc[j];
1197
1198         return NULL;
1199 }
1200
1201
1202 static const struct resource_funcs dce110_res_pool_funcs = {
1203         .destroy = dce110_destroy_resource_pool,
1204         .link_enc_create = dce110_link_encoder_create,
1205         .validate_bandwidth = dce110_validate_bandwidth,
1206         .validate_plane = dce110_validate_plane,
1207         .acquire_idle_pipe_for_layer = dce110_acquire_underlay,
1208         .add_stream_to_ctx = dce110_add_stream_to_ctx,
1209         .validate_global = dce110_validate_global,
1210         .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
1211 };
1212
1213 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
1214 {
1215         struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv),
1216                                                              GFP_KERNEL);
1217         struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv),
1218                                                     GFP_KERNEL);
1219         struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv),
1220                                                    GFP_KERNEL);
1221         struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv),
1222                                                  GFP_KERNEL);
1223
1224         if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) {
1225                 kfree(dce110_tgv);
1226                 kfree(dce110_xfmv);
1227                 kfree(dce110_miv);
1228                 kfree(dce110_oppv);
1229                 return false;
1230         }
1231
1232         dce110_opp_v_construct(dce110_oppv, ctx);
1233
1234         dce110_timing_generator_v_construct(dce110_tgv, ctx);
1235         dce110_mem_input_v_construct(dce110_miv, ctx);
1236         dce110_transform_v_construct(dce110_xfmv, ctx);
1237
1238         pool->opps[pool->pipe_count] = &dce110_oppv->base;
1239         pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
1240         pool->mis[pool->pipe_count] = &dce110_miv->base;
1241         pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
1242         pool->pipe_count++;
1243
1244         /* update the public caps to indicate an underlay is available */
1245         ctx->dc->caps.max_slave_planes = 1;
1246         ctx->dc->caps.max_slave_planes = 1;
1247
1248         return true;
1249 }
1250
1251 static void bw_calcs_data_update_from_pplib(struct dc *dc)
1252 {
1253         struct dm_pp_clock_levels clks = {0};
1254
1255         /*do system clock*/
1256         dm_pp_get_clock_levels_by_type(
1257                         dc->ctx,
1258                         DM_PP_CLOCK_TYPE_ENGINE_CLK,
1259                         &clks);
1260         /* convert all the clock fro kHz to fix point mHz */
1261         dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1262                         clks.clocks_in_khz[clks.num_levels-1], 1000);
1263         dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1264                         clks.clocks_in_khz[clks.num_levels/8], 1000);
1265         dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1266                         clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1267         dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1268                         clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1269         dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1270                         clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1271         dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1272                         clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1273         dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1274                         clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1275         dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1276                         clks.clocks_in_khz[0], 1000);
1277         dc->sclk_lvls = clks;
1278
1279         /*do display clock*/
1280         dm_pp_get_clock_levels_by_type(
1281                         dc->ctx,
1282                         DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1283                         &clks);
1284         dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(
1285                         clks.clocks_in_khz[clks.num_levels-1], 1000);
1286         dc->bw_vbios->mid_voltage_max_dispclk  = bw_frc_to_fixed(
1287                         clks.clocks_in_khz[clks.num_levels>>1], 1000);
1288         dc->bw_vbios->low_voltage_max_dispclk  = bw_frc_to_fixed(
1289                         clks.clocks_in_khz[0], 1000);
1290
1291         /*do memory clock*/
1292         dm_pp_get_clock_levels_by_type(
1293                         dc->ctx,
1294                         DM_PP_CLOCK_TYPE_MEMORY_CLK,
1295                         &clks);
1296
1297         dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1298                 clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
1299         dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1300                 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ,
1301                 1000);
1302         dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1303                 clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ,
1304                 1000);
1305 }
1306
1307 const struct resource_caps *dce110_resource_cap(
1308         struct hw_asic_id *asic_id)
1309 {
1310         if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
1311                 return &stoney_resource_cap;
1312         else
1313                 return &carrizo_resource_cap;
1314 }
1315
1316 static bool dce110_resource_construct(
1317         uint8_t num_virtual_links,
1318         struct dc *dc,
1319         struct dce110_resource_pool *pool,
1320         struct hw_asic_id asic_id)
1321 {
1322         unsigned int i;
1323         struct dc_context *ctx = dc->ctx;
1324         struct dc_bios *bp;
1325
1326         ctx->dc_bios->regs = &bios_regs;
1327
1328         pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
1329         pool->base.funcs = &dce110_res_pool_funcs;
1330
1331         /*************************************************
1332          *  Resource + asic cap harcoding                *
1333          *************************************************/
1334
1335         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1336         pool->base.underlay_pipe_index = pool->base.pipe_count;
1337         pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1338         dc->caps.max_downscale_ratio = 150;
1339         dc->caps.i2c_speed_in_khz = 100;
1340         dc->caps.max_cursor_size = 128;
1341         dc->caps.is_apu = true;
1342         dc->caps.extended_aux_timeout_support = false;
1343
1344         /*************************************************
1345          *  Create resources                             *
1346          *************************************************/
1347
1348         bp = ctx->dc_bios;
1349
1350         if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1351                 pool->base.dp_clock_source =
1352                                 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1353
1354                 pool->base.clock_sources[0] =
1355                                 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0,
1356                                                 &clk_src_regs[0], false);
1357                 pool->base.clock_sources[1] =
1358                                 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1,
1359                                                 &clk_src_regs[1], false);
1360
1361                 pool->base.clk_src_count = 2;
1362
1363                 /* TODO: find out if CZ support 3 PLLs */
1364         }
1365
1366         if (pool->base.dp_clock_source == NULL) {
1367                 dm_error("DC: failed to create dp clock source!\n");
1368                 BREAK_TO_DEBUGGER();
1369                 goto res_create_fail;
1370         }
1371
1372         for (i = 0; i < pool->base.clk_src_count; i++) {
1373                 if (pool->base.clock_sources[i] == NULL) {
1374                         dm_error("DC: failed to create clock sources!\n");
1375                         BREAK_TO_DEBUGGER();
1376                         goto res_create_fail;
1377                 }
1378         }
1379
1380         pool->base.dmcu = dce_dmcu_create(ctx,
1381                         &dmcu_regs,
1382                         &dmcu_shift,
1383                         &dmcu_mask);
1384         if (pool->base.dmcu == NULL) {
1385                 dm_error("DC: failed to create dmcu!\n");
1386                 BREAK_TO_DEBUGGER();
1387                 goto res_create_fail;
1388         }
1389
1390         pool->base.abm = dce_abm_create(ctx,
1391                         &abm_regs,
1392                         &abm_shift,
1393                         &abm_mask);
1394         if (pool->base.abm == NULL) {
1395                 dm_error("DC: failed to create abm!\n");
1396                 BREAK_TO_DEBUGGER();
1397                 goto res_create_fail;
1398         }
1399
1400         {
1401                 struct irq_service_init_data init_data;
1402                 init_data.ctx = dc->ctx;
1403                 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1404                 if (!pool->base.irqs)
1405                         goto res_create_fail;
1406         }
1407
1408         for (i = 0; i < pool->base.pipe_count; i++) {
1409                 pool->base.timing_generators[i] = dce110_timing_generator_create(
1410                                 ctx, i, &dce110_tg_offsets[i]);
1411                 if (pool->base.timing_generators[i] == NULL) {
1412                         BREAK_TO_DEBUGGER();
1413                         dm_error("DC: failed to create tg!\n");
1414                         goto res_create_fail;
1415                 }
1416
1417                 pool->base.mis[i] = dce110_mem_input_create(ctx, i);
1418                 if (pool->base.mis[i] == NULL) {
1419                         BREAK_TO_DEBUGGER();
1420                         dm_error(
1421                                 "DC: failed to create memory input!\n");
1422                         goto res_create_fail;
1423                 }
1424
1425                 pool->base.ipps[i] = dce110_ipp_create(ctx, i);
1426                 if (pool->base.ipps[i] == NULL) {
1427                         BREAK_TO_DEBUGGER();
1428                         dm_error(
1429                                 "DC: failed to create input pixel processor!\n");
1430                         goto res_create_fail;
1431                 }
1432
1433                 pool->base.transforms[i] = dce110_transform_create(ctx, i);
1434                 if (pool->base.transforms[i] == NULL) {
1435                         BREAK_TO_DEBUGGER();
1436                         dm_error(
1437                                 "DC: failed to create transform!\n");
1438                         goto res_create_fail;
1439                 }
1440
1441                 pool->base.opps[i] = dce110_opp_create(ctx, i);
1442                 if (pool->base.opps[i] == NULL) {
1443                         BREAK_TO_DEBUGGER();
1444                         dm_error(
1445                                 "DC: failed to create output pixel processor!\n");
1446                         goto res_create_fail;
1447                 }
1448         }
1449
1450         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1451                 pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
1452                 if (pool->base.engines[i] == NULL) {
1453                         BREAK_TO_DEBUGGER();
1454                         dm_error(
1455                                 "DC:failed to create aux engine!!\n");
1456                         goto res_create_fail;
1457                 }
1458                 pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i);
1459                 if (pool->base.hw_i2cs[i] == NULL) {
1460                         BREAK_TO_DEBUGGER();
1461                         dm_error(
1462                                 "DC:failed to create i2c engine!!\n");
1463                         goto res_create_fail;
1464                 }
1465                 pool->base.sw_i2cs[i] = NULL;
1466         }
1467
1468         if (dc->config.fbc_support)
1469                 dc->fbc_compressor = dce110_compressor_create(ctx);
1470
1471         if (!underlay_create(ctx, &pool->base))
1472                 goto res_create_fail;
1473
1474         if (!resource_construct(num_virtual_links, dc, &pool->base,
1475                         &res_create_funcs))
1476                 goto res_create_fail;
1477
1478         /* Create hardware sequencer */
1479         dce110_hw_sequencer_construct(dc);
1480
1481         dc->caps.max_planes =  pool->base.pipe_count;
1482
1483         for (i = 0; i < pool->base.underlay_pipe_index; ++i)
1484                 dc->caps.planes[i] = plane_cap;
1485
1486         dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap;
1487
1488         bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1489
1490         bw_calcs_data_update_from_pplib(dc);
1491
1492         return true;
1493
1494 res_create_fail:
1495         dce110_resource_destruct(pool);
1496         return false;
1497 }
1498
1499 struct resource_pool *dce110_create_resource_pool(
1500         uint8_t num_virtual_links,
1501         struct dc *dc,
1502         struct hw_asic_id asic_id)
1503 {
1504         struct dce110_resource_pool *pool =
1505                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1506
1507         if (!pool)
1508                 return NULL;
1509
1510         if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id))
1511                 return &pool->base;
1512
1513         kfree(pool);
1514         BREAK_TO_DEBUGGER();
1515         return NULL;
1516 }