2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
27 #include "dc_bios_types.h"
28 #include "core_types.h"
29 #include "core_status.h"
31 #include "dm_helpers.h"
32 #include "dce110_hw_sequencer.h"
33 #include "dce110_timing_generator.h"
34 #include "dce/dce_hwseq.h"
35 #include "gpio_service_interface.h"
37 #include "dce110_compressor.h"
39 #include "bios/bios_parser_helper.h"
40 #include "timing_generator.h"
41 #include "mem_input.h"
44 #include "transform.h"
45 #include "stream_encoder.h"
46 #include "link_encoder.h"
47 #include "link_hwss.h"
48 #include "clock_source.h"
51 #include "reg_helper.h"
53 /* include DCE11 register header files */
54 #include "dce/dce_11_0_d.h"
55 #include "dce/dce_11_0_sh_mask.h"
56 #include "custom_float.h"
58 #include "atomfirmware.h"
61 * All values are in milliseconds;
62 * For eDP, after power-up/power/down,
63 * 300/500 msec max. delay from LCDVCC to black video generation
65 #define PANEL_POWER_UP_TIMEOUT 300
66 #define PANEL_POWER_DOWN_TIMEOUT 500
67 #define HPD_CHECK_INTERVAL 10
72 #define DC_LOGGER_INIT()
78 #define FN(reg_name, field_name) \
79 hws->shifts->field_name, hws->masks->field_name
81 struct dce110_hw_seq_reg_offsets {
85 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
87 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
90 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
93 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
96 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
100 #define HW_REG_BLND(reg, id)\
101 (reg + reg_offsets[id].blnd)
103 #define HW_REG_CRTC(reg, id)\
104 (reg + reg_offsets[id].crtc)
106 #define MAX_WATERMARK 0xFFFF
107 #define SAFE_NBP_MARK 0x7FFF
109 /*******************************************************************************
110 * Private definitions
111 ******************************************************************************/
112 /***************************PIPE_CONTROL***********************************/
113 static void dce110_init_pte(struct dc_context *ctx)
117 uint32_t chunk_int = 0;
118 uint32_t chunk_mul = 0;
120 addr = mmUNP_DVMM_PTE_CONTROL;
121 value = dm_read_reg(ctx, addr);
127 DVMM_USE_SINGLE_PTE);
133 DVMM_PTE_BUFFER_MODE0);
139 DVMM_PTE_BUFFER_MODE1);
141 dm_write_reg(ctx, addr, value);
143 addr = mmDVMM_PTE_REQ;
144 value = dm_read_reg(ctx, addr);
146 chunk_int = get_reg_field_value(
149 HFLIP_PTEREQ_PER_CHUNK_INT);
151 chunk_mul = get_reg_field_value(
154 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
156 if (chunk_int != 0x4 || chunk_mul != 0x4) {
162 MAX_PTEREQ_TO_ISSUE);
168 HFLIP_PTEREQ_PER_CHUNK_INT);
174 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
176 dm_write_reg(ctx, addr, value);
179 /**************************************************************************/
181 static void enable_display_pipe_clock_gating(
182 struct dc_context *ctx,
188 static bool dce110_enable_display_power_gating(
190 uint8_t controller_id,
192 enum pipe_gating_control power_gating)
194 enum bp_result bp_result = BP_RESULT_OK;
195 enum bp_pipe_control_action cntl;
196 struct dc_context *ctx = dc->ctx;
197 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
199 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
202 if (power_gating == PIPE_GATING_CONTROL_INIT)
203 cntl = ASIC_PIPE_INIT;
204 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
205 cntl = ASIC_PIPE_ENABLE;
207 cntl = ASIC_PIPE_DISABLE;
209 if (controller_id == underlay_idx)
210 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
212 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
214 bp_result = dcb->funcs->enable_disp_power_gating(
215 dcb, controller_id + 1, cntl);
217 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
218 * by default when command table is called
220 * Bios parser accepts controller_id = 6 as indicative of
221 * underlay pipe in dce110. But we do not support more
224 if (controller_id < CONTROLLER_ID_MAX - 1)
226 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
230 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
231 dce110_init_pte(ctx);
233 if (bp_result == BP_RESULT_OK)
239 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
240 const struct dc_plane_state *plane_state)
242 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
244 switch (plane_state->format) {
245 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
246 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
247 prescale_params->scale = 0x2020;
249 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
250 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
251 prescale_params->scale = 0x2008;
253 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
254 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
255 prescale_params->scale = 0x2000;
264 dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
265 const struct dc_plane_state *plane_state)
267 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
268 const struct dc_transfer_func *tf = NULL;
269 struct ipp_prescale_params prescale_params = { 0 };
275 if (plane_state->in_transfer_func)
276 tf = plane_state->in_transfer_func;
278 build_prescale_params(&prescale_params, plane_state);
279 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
281 if (plane_state->gamma_correction &&
282 !plane_state->gamma_correction->is_identity &&
283 dce_use_lut(plane_state->format))
284 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
287 /* Default case if no input transfer function specified */
288 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
289 } else if (tf->type == TF_TYPE_PREDEFINED) {
291 case TRANSFER_FUNCTION_SRGB:
292 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
294 case TRANSFER_FUNCTION_BT709:
295 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
297 case TRANSFER_FUNCTION_LINEAR:
298 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
300 case TRANSFER_FUNCTION_PQ:
305 } else if (tf->type == TF_TYPE_BYPASS) {
306 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
308 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
315 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
316 struct curve_points *arr_points,
317 uint32_t hw_points_num)
319 struct custom_float_format fmt;
321 struct pwl_result_data *rgb = rgb_resulted;
325 fmt.exponenta_bits = 6;
326 fmt.mantissa_bits = 12;
329 if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
330 &arr_points[0].custom_float_x)) {
335 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
336 &arr_points[0].custom_float_offset)) {
341 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
342 &arr_points[0].custom_float_slope)) {
347 fmt.mantissa_bits = 10;
350 if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
351 &arr_points[1].custom_float_x)) {
356 if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
357 &arr_points[1].custom_float_y)) {
362 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
363 &arr_points[1].custom_float_slope)) {
368 fmt.mantissa_bits = 12;
371 while (i != hw_points_num) {
372 if (!convert_to_custom_float_format(rgb->red, &fmt,
378 if (!convert_to_custom_float_format(rgb->green, &fmt,
384 if (!convert_to_custom_float_format(rgb->blue, &fmt,
390 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
391 &rgb->delta_red_reg)) {
396 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
397 &rgb->delta_green_reg)) {
402 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
403 &rgb->delta_blue_reg)) {
415 #define MAX_LOW_POINT 25
416 #define NUMBER_REGIONS 16
417 #define NUMBER_SW_SEGMENTS 16
420 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
421 struct pwl_params *regamma_params)
423 struct curve_points *arr_points;
424 struct pwl_result_data *rgb_resulted;
425 struct pwl_result_data *rgb;
426 struct pwl_result_data *rgb_plus_1;
427 struct fixed31_32 y_r;
428 struct fixed31_32 y_g;
429 struct fixed31_32 y_b;
430 struct fixed31_32 y1_min;
431 struct fixed31_32 y3_max;
433 int32_t region_start, region_end;
434 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
436 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
439 arr_points = regamma_params->arr_points;
440 rgb_resulted = regamma_params->rgb_resulted;
443 memset(regamma_params, 0, sizeof(struct pwl_params));
445 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
447 * segments are from 2^-11 to 2^5
450 region_end = region_start + NUMBER_REGIONS;
452 for (i = 0; i < NUMBER_REGIONS; i++)
457 * segment is from 2^-10 to 2^1
458 * We include an extra segment for range [2^0, 2^1). This is to
459 * ensure that colors with normalized values of 1 don't miss the
483 for (k = 0; k < 16; k++) {
484 if (seg_distr[k] != -1)
485 hw_points += (1 << seg_distr[k]);
489 for (k = 0; k < (region_end - region_start); k++) {
490 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
491 start_index = (region_start + k + MAX_LOW_POINT) *
493 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
495 if (j == hw_points - 1)
497 rgb_resulted[j].red = output_tf->tf_pts.red[i];
498 rgb_resulted[j].green = output_tf->tf_pts.green[i];
499 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
505 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
506 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
507 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
508 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
510 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
511 dc_fixpt_from_int(region_start));
512 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
513 dc_fixpt_from_int(region_end));
515 y_r = rgb_resulted[0].red;
516 y_g = rgb_resulted[0].green;
517 y_b = rgb_resulted[0].blue;
519 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
521 arr_points[0].y = y1_min;
522 arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
525 y_r = rgb_resulted[hw_points - 1].red;
526 y_g = rgb_resulted[hw_points - 1].green;
527 y_b = rgb_resulted[hw_points - 1].blue;
529 /* see comment above, m_arrPoints[1].y should be the Y value for the
530 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
532 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
534 arr_points[1].y = y3_max;
536 arr_points[1].slope = dc_fixpt_zero;
538 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
539 /* for PQ, we want to have a straight line from last HW X point,
540 * and the slope to be such that we hit 1.0 at 10000 nits.
542 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
544 arr_points[1].slope = dc_fixpt_div(
545 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
546 dc_fixpt_sub(end_value, arr_points[1].x));
549 regamma_params->hw_points_num = hw_points;
552 for (k = 0; k < 16 && i < 16; k++) {
553 if (seg_distr[k] != -1) {
554 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
555 regamma_params->arr_curve_points[i].offset =
556 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
561 if (seg_distr[k] != -1)
562 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
565 rgb_plus_1 = rgb_resulted + 1;
569 while (i != hw_points + 1) {
570 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
571 rgb_plus_1->red = rgb->red;
572 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
573 rgb_plus_1->green = rgb->green;
574 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
575 rgb_plus_1->blue = rgb->blue;
577 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
578 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
579 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
586 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
592 dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
593 const struct dc_stream_state *stream)
595 struct transform *xfm = pipe_ctx->plane_res.xfm;
597 xfm->funcs->opp_power_on_regamma_lut(xfm, true);
598 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
600 if (stream->out_transfer_func &&
601 stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
602 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
603 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
604 } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
605 &xfm->regamma_params)) {
606 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
607 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
609 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
612 xfm->funcs->opp_power_on_regamma_lut(xfm, false);
617 static enum dc_status bios_parser_crtc_source_select(
618 struct pipe_ctx *pipe_ctx)
621 /* call VBIOS table to set CRTC source for the HW
623 * note: video bios clears all FMT setting here. */
624 struct bp_crtc_source_select crtc_source_select = {0};
625 const struct dc_sink *sink = pipe_ctx->stream->sink;
627 crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
628 crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1;
629 /*TODO: Need to un-hardcode color depth, dp_audio and account for
630 * the case where signal and sink signal is different (translator
632 crtc_source_select.signal = pipe_ctx->stream->signal;
633 crtc_source_select.enable_dp_audio = false;
634 crtc_source_select.sink_signal = pipe_ctx->stream->signal;
636 switch (pipe_ctx->stream->timing.display_color_depth) {
637 case COLOR_DEPTH_666:
638 crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR;
640 case COLOR_DEPTH_888:
641 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
643 case COLOR_DEPTH_101010:
644 crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR;
646 case COLOR_DEPTH_121212:
647 crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR;
651 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
655 dcb = sink->ctx->dc_bios;
657 if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
659 &crtc_source_select)) {
660 return DC_ERROR_UNEXPECTED;
666 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
671 ASSERT(pipe_ctx->stream);
673 if (pipe_ctx->stream_res.stream_enc == NULL)
674 return; /* this is not root pipe */
676 is_hdmi = dc_is_hdmi_signal(pipe_ctx->stream->signal);
677 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
679 if (!is_hdmi && !is_dp)
683 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
684 pipe_ctx->stream_res.stream_enc,
685 &pipe_ctx->stream_res.encoder_info_frame);
687 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
688 pipe_ctx->stream_res.stream_enc,
689 &pipe_ctx->stream_res.encoder_info_frame);
692 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
694 enum dc_lane_count lane_count =
695 pipe_ctx->stream->sink->link->cur_link_settings.lane_count;
697 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
698 struct dc_link *link = pipe_ctx->stream->sink->link;
701 uint32_t active_total_with_borders;
702 uint32_t early_control = 0;
703 struct timing_generator *tg = pipe_ctx->stream_res.tg;
705 /* For MST, there are multiply stream go to only one link.
706 * connect DIG back_end to front_end while enable_stream and
707 * disconnect them during disable_stream
708 * BY this, it is logic clean to separate stream and link */
709 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
710 pipe_ctx->stream_res.stream_enc->id, true);
712 /* update AVI info frame (HDMI, DP)*/
713 /* TODO: FPGA may change to hwss.update_info_frame */
714 dce110_update_info_frame(pipe_ctx);
716 /* enable early control to avoid corruption on DP monitor*/
717 active_total_with_borders =
718 timing->h_addressable
719 + timing->h_border_left
720 + timing->h_border_right;
723 early_control = active_total_with_borders % lane_count;
725 if (early_control == 0)
726 early_control = lane_count;
728 tg->funcs->set_early_control(tg, early_control);
730 /* enable audio only within mode set */
731 if (pipe_ctx->stream_res.audio != NULL) {
732 if (dc_is_dp_signal(pipe_ctx->stream->signal))
733 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
741 /*todo: cloned in stream enc, fix*/
742 static bool is_panel_backlight_on(struct dce_hwseq *hws)
746 REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
751 static bool is_panel_powered_on(struct dce_hwseq *hws)
753 uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
756 REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
758 REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
760 return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
763 static enum bp_result link_transmitter_control(
764 struct dc_bios *bios,
765 struct bp_transmitter_control *cntl)
767 enum bp_result result;
769 result = bios->funcs->transmitter_control(bios, cntl);
778 void hwss_edp_wait_for_hpd_ready(
779 struct dc_link *link,
782 struct dc_context *ctx = link->ctx;
783 struct graphics_object_id connector = link->link_enc->connector;
785 bool edp_hpd_high = false;
786 uint32_t time_elapsed = 0;
787 uint32_t timeout = power_up ?
788 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
790 if (dal_graphics_object_id_get_connector_id(connector)
791 != CONNECTOR_ID_EDP) {
798 * From KV, we will not HPD low after turning off VCC -
799 * instead, we will check the SW timer in power_up().
804 * When we power on/off the eDP panel,
805 * we need to wait until SENSE bit is high/low.
809 /* TODO what to do with this? */
810 hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
817 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
819 /* wait until timeout or panel detected */
822 uint32_t detected = 0;
824 dal_gpio_get_value(hpd, &detected);
826 if (!(detected ^ power_up)) {
831 msleep(HPD_CHECK_INTERVAL);
833 time_elapsed += HPD_CHECK_INTERVAL;
834 } while (time_elapsed < timeout);
838 dal_gpio_destroy_irq(&hpd);
840 if (false == edp_hpd_high) {
842 "%s: wait timed out!\n", __func__);
846 void hwss_edp_power_control(
847 struct dc_link *link,
850 struct dc_context *ctx = link->ctx;
851 struct dce_hwseq *hwseq = ctx->dc->hwseq;
852 struct bp_transmitter_control cntl = { 0 };
853 enum bp_result bp_result;
856 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
857 != CONNECTOR_ID_EDP) {
862 if (power_up != is_panel_powered_on(hwseq)) {
863 /* Send VBIOS command to prompt eDP panel power */
865 unsigned long long current_ts = dm_get_timestamp(ctx);
866 unsigned long long duration_in_ms =
867 div64_u64(dm_get_elapse_time_in_ns(
870 link->link_trace.time_stamp.edp_poweroff), 1000000);
871 unsigned long long wait_time_ms = 0;
873 /* max 500ms from LCDVDD off to on */
874 unsigned long long edp_poweroff_time_ms = 500;
876 if (link->local_sink != NULL)
877 edp_poweroff_time_ms =
878 500 + link->local_sink->edid_caps.panel_patch.extra_t12_ms;
879 if (link->link_trace.time_stamp.edp_poweroff == 0)
880 wait_time_ms = edp_poweroff_time_ms;
881 else if (duration_in_ms < edp_poweroff_time_ms)
882 wait_time_ms = edp_poweroff_time_ms - duration_in_ms;
885 msleep(wait_time_ms);
886 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
887 __func__, wait_time_ms);
893 "%s: Panel Power action: %s\n",
894 __func__, (power_up ? "On":"Off"));
896 cntl.action = power_up ?
897 TRANSMITTER_CONTROL_POWER_ON :
898 TRANSMITTER_CONTROL_POWER_OFF;
899 cntl.transmitter = link->link_enc->transmitter;
900 cntl.connector_obj_id = link->link_enc->connector;
901 cntl.coherent = false;
902 cntl.lanes_number = LANE_COUNT_FOUR;
903 cntl.hpd_sel = link->link_enc->hpd_source;
904 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
907 /*save driver power off time stamp*/
908 link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
910 link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
912 if (bp_result != BP_RESULT_OK)
914 "%s: Panel Power bp_result: %d\n",
915 __func__, bp_result);
918 "%s: Skipping Panel Power action: %s\n",
919 __func__, (power_up ? "On":"Off"));
923 /*todo: cloned in stream enc, fix*/
926 * eDP only. Control the backlight of the eDP panel
928 void hwss_edp_backlight_control(
929 struct dc_link *link,
932 struct dc_context *ctx = link->ctx;
933 struct dce_hwseq *hws = ctx->dc->hwseq;
934 struct bp_transmitter_control cntl = { 0 };
936 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
937 != CONNECTOR_ID_EDP) {
942 if (enable && is_panel_backlight_on(hws)) {
944 "%s: panel already powered up. Do nothing.\n",
949 /* Send VBIOS command to control eDP panel backlight */
952 "%s: backlight action: %s\n",
953 __func__, (enable ? "On":"Off"));
955 cntl.action = enable ?
956 TRANSMITTER_CONTROL_BACKLIGHT_ON :
957 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
959 /*cntl.engine_id = ctx->engine;*/
960 cntl.transmitter = link->link_enc->transmitter;
961 cntl.connector_obj_id = link->link_enc->connector;
963 cntl.lanes_number = LANE_COUNT_FOUR;
964 cntl.hpd_sel = link->link_enc->hpd_source;
965 cntl.signal = SIGNAL_TYPE_EDP;
967 /* For eDP, the following delays might need to be considered
968 * after link training completed:
969 * idle period - min. accounts for required BS-Idle pattern,
970 * max. allows for source frame synchronization);
971 * 50 msec max. delay from valid video data from source
972 * to video on dislpay or backlight enable.
974 * Disable the delay for now.
975 * Enable it in the future if necessary.
977 /* dc_service_sleep_in_milliseconds(50); */
979 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
980 edp_receiver_ready_T7(link);
981 link_transmitter_control(ctx->dc_bios, &cntl);
983 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
984 edp_receiver_ready_T9(link);
987 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
989 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
990 /* notify audio driver for audio modes of monitor */
991 struct pp_smu_funcs_rv *pp_smu = core_dc->res_pool->pp_smu;
992 unsigned int i, num_audio = 1;
994 if (pipe_ctx->stream_res.audio) {
995 for (i = 0; i < MAX_PIPES; i++) {
996 /*current_state not updated yet*/
997 if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1001 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1003 if (num_audio == 1 && pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL)
1004 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1005 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
1007 /* TODO: audio should be per stream rather than per link */
1008 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1009 pipe_ctx->stream_res.stream_enc, false);
1013 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
1015 struct dc *dc = pipe_ctx->stream->ctx->dc;
1017 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1018 pipe_ctx->stream_res.stream_enc, true);
1019 if (pipe_ctx->stream_res.audio) {
1020 if (option != KEEP_ACQUIRED_RESOURCE ||
1021 !dc->debug.az_endpoint_mute_only) {
1022 /*only disalbe az_endpoint if power down or free*/
1023 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
1026 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1027 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1028 pipe_ctx->stream_res.stream_enc);
1030 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1031 pipe_ctx->stream_res.stream_enc);
1032 /*don't free audio if it is from retrain or internal disable stream*/
1033 if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
1034 /*we have to dynamic arbitrate the audio endpoints*/
1035 /*we free the resource, need reset is_audio_acquired*/
1036 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
1037 pipe_ctx->stream_res.audio = NULL;
1040 /* TODO: notify audio driver for if audio modes list changed
1041 * add audio mode list change flag */
1042 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1043 * stream->stream_engine_id);
1048 void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
1050 struct dc_stream_state *stream = pipe_ctx->stream;
1051 struct dc_link *link = stream->sink->link;
1052 struct dc *dc = pipe_ctx->stream->ctx->dc;
1054 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1055 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1056 pipe_ctx->stream_res.stream_enc);
1058 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1059 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1060 pipe_ctx->stream_res.stream_enc);
1062 dc->hwss.disable_audio_stream(pipe_ctx, option);
1064 link->link_enc->funcs->connect_dig_be_to_fe(
1066 pipe_ctx->stream_res.stream_enc->id,
1071 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1072 struct dc_link_settings *link_settings)
1074 struct encoder_unblank_param params = { { 0 } };
1075 struct dc_stream_state *stream = pipe_ctx->stream;
1076 struct dc_link *link = stream->sink->link;
1078 /* only 3 items below are used by unblank */
1079 params.pixel_clk_khz =
1080 pipe_ctx->stream->timing.pix_clk_khz;
1081 params.link_settings.link_rate = link_settings->link_rate;
1083 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1084 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
1086 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1087 link->dc->hwss.edp_backlight_control(link, true);
1088 stream->bl_pwm_level = EDP_BACKLIGHT_RAMP_DISABLE_LEVEL;
1091 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1093 struct dc_stream_state *stream = pipe_ctx->stream;
1094 struct dc_link *link = stream->sink->link;
1096 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1097 link->dc->hwss.edp_backlight_control(link, false);
1098 dc_link_set_abm_disable(link);
1101 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1102 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1106 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1108 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1109 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1112 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1115 case CONTROLLER_ID_D0:
1116 return DTO_SOURCE_ID0;
1117 case CONTROLLER_ID_D1:
1118 return DTO_SOURCE_ID1;
1119 case CONTROLLER_ID_D2:
1120 return DTO_SOURCE_ID2;
1121 case CONTROLLER_ID_D3:
1122 return DTO_SOURCE_ID3;
1123 case CONTROLLER_ID_D4:
1124 return DTO_SOURCE_ID4;
1125 case CONTROLLER_ID_D5:
1126 return DTO_SOURCE_ID5;
1128 return DTO_SOURCE_UNKNOWN;
1132 static void build_audio_output(
1133 struct dc_state *state,
1134 const struct pipe_ctx *pipe_ctx,
1135 struct audio_output *audio_output)
1137 const struct dc_stream_state *stream = pipe_ctx->stream;
1138 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1140 audio_output->signal = pipe_ctx->stream->signal;
1142 /* audio_crtc_info */
1144 audio_output->crtc_info.h_total =
1145 stream->timing.h_total;
1148 * Audio packets are sent during actual CRTC blank physical signal, we
1149 * need to specify actual active signal portion
1151 audio_output->crtc_info.h_active =
1152 stream->timing.h_addressable
1153 + stream->timing.h_border_left
1154 + stream->timing.h_border_right;
1156 audio_output->crtc_info.v_active =
1157 stream->timing.v_addressable
1158 + stream->timing.v_border_top
1159 + stream->timing.v_border_bottom;
1161 audio_output->crtc_info.pixel_repetition = 1;
1163 audio_output->crtc_info.interlaced =
1164 stream->timing.flags.INTERLACE;
1166 audio_output->crtc_info.refresh_rate =
1167 (stream->timing.pix_clk_khz*1000)/
1168 (stream->timing.h_total*stream->timing.v_total);
1170 audio_output->crtc_info.color_depth =
1171 stream->timing.display_color_depth;
1173 audio_output->crtc_info.requested_pixel_clock =
1174 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1176 audio_output->crtc_info.calculated_pixel_clock =
1177 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1179 /*for HDMI, audio ACR is with deep color ratio factor*/
1180 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
1181 audio_output->crtc_info.requested_pixel_clock ==
1182 stream->timing.pix_clk_khz) {
1183 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1184 audio_output->crtc_info.requested_pixel_clock =
1185 audio_output->crtc_info.requested_pixel_clock/2;
1186 audio_output->crtc_info.calculated_pixel_clock =
1187 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2;
1192 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1193 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1194 audio_output->pll_info.dp_dto_source_clock_in_khz =
1195 state->dis_clk->funcs->get_dp_ref_clk_frequency(
1199 audio_output->pll_info.feed_back_divider =
1200 pipe_ctx->pll_settings.feedback_divider;
1202 audio_output->pll_info.dto_source =
1203 translate_to_dto_source(
1204 pipe_ctx->stream_res.tg->inst + 1);
1206 /* TODO hard code to enable for now. Need get from stream */
1207 audio_output->pll_info.ss_enabled = true;
1209 audio_output->pll_info.ss_percentage =
1210 pipe_ctx->pll_settings.ss_percentage;
1213 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1214 struct tg_color *color)
1216 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
1218 switch (pipe_ctx->plane_res.scl_data.format) {
1219 case PIXEL_FORMAT_ARGB8888:
1220 /* set boarder color to red */
1221 color->color_r_cr = color_value;
1224 case PIXEL_FORMAT_ARGB2101010:
1225 /* set boarder color to blue */
1226 color->color_b_cb = color_value;
1228 case PIXEL_FORMAT_420BPP8:
1229 /* set boarder color to green */
1230 color->color_g_y = color_value;
1232 case PIXEL_FORMAT_420BPP10:
1233 /* set boarder color to yellow */
1234 color->color_g_y = color_value;
1235 color->color_r_cr = color_value;
1237 case PIXEL_FORMAT_FP16:
1238 /* set boarder color to white */
1239 color->color_r_cr = color_value;
1240 color->color_b_cb = color_value;
1241 color->color_g_y = color_value;
1248 static void program_scaler(const struct dc *dc,
1249 const struct pipe_ctx *pipe_ctx)
1251 struct tg_color color = {0};
1253 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1255 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1259 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1260 get_surface_visual_confirm_color(pipe_ctx, &color);
1262 color_space_to_black_color(dc,
1263 pipe_ctx->stream->output_color_space,
1266 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1267 pipe_ctx->plane_res.xfm,
1268 pipe_ctx->plane_res.scl_data.lb_params.depth,
1269 &pipe_ctx->stream->bit_depth_params);
1271 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color)
1272 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1273 pipe_ctx->stream_res.tg,
1276 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1277 &pipe_ctx->plane_res.scl_data);
1280 static enum dc_status dce110_enable_stream_timing(
1281 struct pipe_ctx *pipe_ctx,
1282 struct dc_state *context,
1285 struct dc_stream_state *stream = pipe_ctx->stream;
1286 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1287 pipe_ctx[pipe_ctx->pipe_idx];
1288 struct tg_color black_color = {0};
1289 struct drr_params params = {0};
1290 unsigned int event_triggers = 0;
1292 if (!pipe_ctx_old->stream) {
1294 /* program blank color */
1295 color_space_to_black_color(dc,
1296 stream->output_color_space, &black_color);
1297 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1298 pipe_ctx->stream_res.tg,
1302 * Must blank CRTC after disabling power gating and before any
1303 * programming, otherwise CRTC will be hung in bad state
1305 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1307 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1308 pipe_ctx->clock_source,
1309 &pipe_ctx->stream_res.pix_clk_params,
1310 &pipe_ctx->pll_settings)) {
1311 BREAK_TO_DEBUGGER();
1312 return DC_ERROR_UNEXPECTED;
1315 pipe_ctx->stream_res.tg->funcs->program_timing(
1316 pipe_ctx->stream_res.tg,
1320 params.vertical_total_min = stream->adjust.v_total_min;
1321 params.vertical_total_max = stream->adjust.v_total_max;
1322 if (pipe_ctx->stream_res.tg->funcs->set_drr)
1323 pipe_ctx->stream_res.tg->funcs->set_drr(
1324 pipe_ctx->stream_res.tg, ¶ms);
1326 // DRR should set trigger event to monitor surface update event
1327 if (stream->adjust.v_total_min != 0 &&
1328 stream->adjust.v_total_max != 0)
1329 event_triggers = 0x80;
1330 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1331 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1332 pipe_ctx->stream_res.tg, event_triggers);
1335 if (!pipe_ctx_old->stream) {
1336 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1337 pipe_ctx->stream_res.tg)) {
1338 BREAK_TO_DEBUGGER();
1339 return DC_ERROR_UNEXPECTED;
1346 static enum dc_status apply_single_controller_ctx_to_hw(
1347 struct pipe_ctx *pipe_ctx,
1348 struct dc_state *context,
1351 struct dc_stream_state *stream = pipe_ctx->stream;
1353 if (pipe_ctx->stream_res.audio != NULL) {
1354 struct audio_output audio_output;
1356 build_audio_output(context, pipe_ctx, &audio_output);
1358 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1359 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1360 pipe_ctx->stream_res.stream_enc,
1361 pipe_ctx->stream_res.audio->inst,
1362 &pipe_ctx->stream->audio_info);
1364 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1365 pipe_ctx->stream_res.stream_enc,
1366 pipe_ctx->stream_res.audio->inst,
1367 &pipe_ctx->stream->audio_info,
1368 &audio_output.crtc_info);
1370 pipe_ctx->stream_res.audio->funcs->az_configure(
1371 pipe_ctx->stream_res.audio,
1372 pipe_ctx->stream->signal,
1373 &audio_output.crtc_info,
1374 &pipe_ctx->stream->audio_info);
1378 dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
1380 /* TODO: move to stream encoder */
1381 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1382 if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
1383 BREAK_TO_DEBUGGER();
1384 return DC_ERROR_UNEXPECTED;
1387 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1388 pipe_ctx->stream_res.opp,
1389 COLOR_SPACE_YCBCR601,
1390 stream->timing.display_color_depth,
1391 pipe_ctx->stream->signal);
1393 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1394 pipe_ctx->stream_res.opp,
1395 &stream->bit_depth_params,
1398 if (!stream->dpms_off)
1399 core_link_enable_stream(context, pipe_ctx);
1401 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1403 pipe_ctx->stream->sink->link->psr_enabled = false;
1408 /******************************************************************************/
1410 static void power_down_encoders(struct dc *dc)
1413 enum connector_id connector_id;
1414 enum signal_type signal = SIGNAL_TYPE_NONE;
1416 /* do not know BIOS back-front mapping, simply blank all. It will not
1419 for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1420 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1421 dc->res_pool->stream_enc[i]);
1424 for (i = 0; i < dc->link_count; i++) {
1425 connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
1426 if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
1427 (connector_id == CONNECTOR_ID_EDP)) {
1429 if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1430 dp_receiver_power_ctrl(dc->links[i], false);
1431 if (connector_id == CONNECTOR_ID_EDP)
1432 signal = SIGNAL_TYPE_EDP;
1435 dc->links[i]->link_enc->funcs->disable_output(
1436 dc->links[i]->link_enc, signal);
1440 static void power_down_controllers(struct dc *dc)
1444 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1445 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1446 dc->res_pool->timing_generators[i]);
1450 static void power_down_clock_sources(struct dc *dc)
1454 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1455 dc->res_pool->dp_clock_source) == false)
1456 dm_error("Failed to power down pll! (dp clk src)\n");
1458 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1459 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1460 dc->res_pool->clock_sources[i]) == false)
1461 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1465 static void power_down_all_hw_blocks(struct dc *dc)
1467 power_down_encoders(dc);
1469 power_down_controllers(dc);
1471 power_down_clock_sources(dc);
1473 if (dc->fbc_compressor)
1474 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1477 static void disable_vga_and_power_gate_all_controllers(
1481 struct timing_generator *tg;
1482 struct dc_context *ctx = dc->ctx;
1484 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1485 tg = dc->res_pool->timing_generators[i];
1487 if (tg->funcs->disable_vga)
1488 tg->funcs->disable_vga(tg);
1490 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1491 /* Enable CLOCK gating for each pipe BEFORE controller
1493 enable_display_pipe_clock_gating(ctx,
1496 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1497 dc->hwss.disable_plane(dc,
1498 &dc->current_state->res_ctx.pipe_ctx[i]);
1502 static struct dc_link *get_link_for_edp(struct dc *dc)
1506 for (i = 0; i < dc->link_count; i++) {
1507 if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
1508 return dc->links[i];
1513 static struct dc_link *get_link_for_edp_not_in_use(
1515 struct dc_state *context)
1518 struct dc_link *link = NULL;
1520 /* check if eDP panel is suppose to be set mode, if yes, no need to disable */
1521 for (i = 0; i < context->stream_count; i++) {
1522 if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
1526 /* check if there is an eDP panel not in use */
1527 for (i = 0; i < dc->link_count; i++) {
1528 if (dc->links[i]->local_sink &&
1529 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1530 link = dc->links[i];
1539 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1540 * 1. Power down all DC HW blocks
1541 * 2. Disable VGA engine on all controllers
1542 * 3. Enable power gating for controller
1543 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1545 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1548 struct dc_link *edp_link_to_turnoff = NULL;
1549 struct dc_link *edp_link = get_link_for_edp(dc);
1550 bool can_edp_fast_boot_optimize = false;
1551 bool apply_edp_fast_boot_optimization = false;
1554 /* this seems to cause blank screens on DCE8 */
1555 if ((dc->ctx->dce_version == DCE_VERSION_8_0) ||
1556 (dc->ctx->dce_version == DCE_VERSION_8_1) ||
1557 (dc->ctx->dce_version == DCE_VERSION_8_3))
1558 can_edp_fast_boot_optimize = false;
1560 can_edp_fast_boot_optimize =
1561 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc);
1564 if (can_edp_fast_boot_optimize)
1565 edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context);
1567 /* if OS doesn't light up eDP and eDP link is available, we want to disable
1568 * If resume from S4/S5, should optimization.
1570 if (can_edp_fast_boot_optimize && !edp_link_to_turnoff) {
1571 /* Find eDP stream and set optimization flag */
1572 for (i = 0; i < context->stream_count; i++) {
1573 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1574 context->streams[i]->apply_edp_fast_boot_optimization = true;
1575 apply_edp_fast_boot_optimization = true;
1580 if (!apply_edp_fast_boot_optimization) {
1581 if (edp_link_to_turnoff) {
1582 /*turn off backlight before DP_blank and encoder powered down*/
1583 dc->hwss.edp_backlight_control(edp_link_to_turnoff, false);
1585 /*resume from S3, no vbios posting, no need to power down again*/
1586 power_down_all_hw_blocks(dc);
1587 disable_vga_and_power_gate_all_controllers(dc);
1588 if (edp_link_to_turnoff)
1589 dc->hwss.edp_power_control(edp_link_to_turnoff, false);
1591 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1594 static uint32_t compute_pstate_blackout_duration(
1595 struct bw_fixed blackout_duration,
1596 const struct dc_stream_state *stream)
1598 uint32_t total_dest_line_time_ns;
1599 uint32_t pstate_blackout_duration_ns;
1601 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1603 total_dest_line_time_ns = 1000000UL *
1604 stream->timing.h_total /
1605 stream->timing.pix_clk_khz +
1606 pstate_blackout_duration_ns;
1608 return total_dest_line_time_ns;
1611 static void dce110_set_displaymarks(
1612 const struct dc *dc,
1613 struct dc_state *context)
1615 uint8_t i, num_pipes;
1616 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1618 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1619 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1620 uint32_t total_dest_line_time_ns;
1622 if (pipe_ctx->stream == NULL)
1625 total_dest_line_time_ns = compute_pstate_blackout_duration(
1626 dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1627 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1628 pipe_ctx->plane_res.mi,
1629 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1630 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1631 context->bw.dce.stutter_entry_wm_ns[num_pipes],
1632 context->bw.dce.urgent_wm_ns[num_pipes],
1633 total_dest_line_time_ns);
1634 if (i == underlay_idx) {
1636 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1637 pipe_ctx->plane_res.mi,
1638 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1639 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1640 context->bw.dce.urgent_wm_ns[num_pipes],
1641 total_dest_line_time_ns);
1647 void dce110_set_safe_displaymarks(
1648 struct resource_context *res_ctx,
1649 const struct resource_pool *pool)
1652 int underlay_idx = pool->underlay_pipe_index;
1653 struct dce_watermarks max_marks = {
1654 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1655 struct dce_watermarks nbp_marks = {
1656 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1657 struct dce_watermarks min_marks = { 0, 0, 0, 0};
1659 for (i = 0; i < MAX_PIPES; i++) {
1660 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1663 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1664 res_ctx->pipe_ctx[i].plane_res.mi,
1671 if (i == underlay_idx)
1672 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1673 res_ctx->pipe_ctx[i].plane_res.mi,
1682 /*******************************************************************************
1684 ******************************************************************************/
1686 static void set_drr(struct pipe_ctx **pipe_ctx,
1687 int num_pipes, int vmin, int vmax)
1690 struct drr_params params = {0};
1691 // DRR should set trigger event to monitor surface update event
1692 unsigned int event_triggers = 0x80;
1694 params.vertical_total_max = vmax;
1695 params.vertical_total_min = vmin;
1697 /* TODO: If multiple pipes are to be supported, you need
1698 * some GSL stuff. Static screen triggers may be programmed differently
1701 for (i = 0; i < num_pipes; i++) {
1702 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1703 pipe_ctx[i]->stream_res.tg, ¶ms);
1705 if (vmax != 0 && vmin != 0)
1706 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1707 pipe_ctx[i]->stream_res.tg,
1712 static void get_position(struct pipe_ctx **pipe_ctx,
1714 struct crtc_position *position)
1718 /* TODO: handle pipes > 1
1720 for (i = 0; i < num_pipes; i++)
1721 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1724 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1725 int num_pipes, const struct dc_static_screen_events *events)
1728 unsigned int value = 0;
1730 if (events->overlay_update)
1732 if (events->surface_update)
1734 if (events->cursor_update)
1736 if (events->force_trigger)
1740 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1742 if (dc->fbc_compressor)
1746 for (i = 0; i < num_pipes; i++)
1747 pipe_ctx[i]->stream_res.tg->funcs->
1748 set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
1751 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
1752 * may not be programmed yet
1754 static uint32_t get_max_pixel_clock_for_all_paths(
1756 struct dc_state *context)
1758 uint32_t max_pix_clk = 0;
1761 for (i = 0; i < MAX_PIPES; i++) {
1762 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1764 if (pipe_ctx->stream == NULL)
1767 /* do not check under lay */
1768 if (pipe_ctx->top_pipe)
1771 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
1773 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1780 * Check if FBC can be enabled
1782 static bool should_enable_fbc(struct dc *dc,
1783 struct dc_state *context,
1787 struct pipe_ctx *pipe_ctx = NULL;
1788 struct resource_context *res_ctx = &context->res_ctx;
1791 ASSERT(dc->fbc_compressor);
1793 /* FBC memory should be allocated */
1794 if (!dc->ctx->fbc_gpu_addr)
1797 /* Only supports single display */
1798 if (context->stream_count != 1)
1801 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1802 if (res_ctx->pipe_ctx[i].stream) {
1803 pipe_ctx = &res_ctx->pipe_ctx[i];
1809 /* Pipe context should be found */
1812 /* Only supports eDP */
1813 if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
1816 /* PSR should not be enabled */
1817 if (pipe_ctx->stream->sink->link->psr_enabled)
1820 /* Nothing to compress */
1821 if (!pipe_ctx->plane_state)
1824 /* Only for non-linear tiling */
1825 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1834 static void enable_fbc(struct dc *dc,
1835 struct dc_state *context)
1837 uint32_t pipe_idx = 0;
1839 if (should_enable_fbc(dc, context, &pipe_idx)) {
1840 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1841 struct compr_addr_and_pitch_params params = {0, 0, 0};
1842 struct compressor *compr = dc->fbc_compressor;
1843 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1846 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
1847 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
1849 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1851 compr->funcs->surface_address_and_pitch(compr, ¶ms);
1852 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1854 compr->funcs->enable_fbc(compr, ¶ms);
1858 static void dce110_reset_hw_ctx_wrap(
1860 struct dc_state *context)
1864 /* Reset old context */
1865 /* look up the targets that have been removed since last commit */
1866 for (i = 0; i < MAX_PIPES; i++) {
1867 struct pipe_ctx *pipe_ctx_old =
1868 &dc->current_state->res_ctx.pipe_ctx[i];
1869 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1871 /* Note: We need to disable output if clock sources change,
1872 * since bios does optimization and doesn't apply if changing
1873 * PHY when not already disabled.
1876 /* Skip underlay pipe since it will be handled in commit surface*/
1877 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1880 if (!pipe_ctx->stream ||
1881 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1882 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1884 /* Disable if new stream is null. O/w, if stream is
1885 * disabled already, no need to disable again.
1887 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
1888 core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
1890 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1891 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1892 dm_error("DC: failed to blank crtc!\n");
1893 BREAK_TO_DEBUGGER();
1895 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1896 pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1897 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
1899 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
1902 old_clk->funcs->cs_power_down(old_clk);
1904 dc->hwss.disable_plane(dc, pipe_ctx_old);
1906 pipe_ctx_old->stream = NULL;
1911 static void dce110_setup_audio_dto(
1913 struct dc_state *context)
1917 /* program audio wall clock. use HDMI as clock source if HDMI
1918 * audio active. Otherwise, use DP as clock source
1919 * first, loop to find any HDMI audio, if not, loop find DP audio
1921 /* Setup audio rate clock source */
1923 * Audio lag happened on DP monitor when unplug a HDMI monitor
1926 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1927 * is set to either dto0 or dto1, audio should work fine.
1928 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1929 * set to dto0 will cause audio lag.
1932 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1933 * find first available pipe with audio, setup audio wall DTO per topology
1934 * instead of per pipe.
1936 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1937 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1939 if (pipe_ctx->stream == NULL)
1942 if (pipe_ctx->top_pipe)
1945 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
1948 if (pipe_ctx->stream_res.audio != NULL) {
1949 struct audio_output audio_output;
1951 build_audio_output(context, pipe_ctx, &audio_output);
1953 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
1954 pipe_ctx->stream_res.audio,
1955 pipe_ctx->stream->signal,
1956 &audio_output.crtc_info,
1957 &audio_output.pll_info);
1962 /* no HDMI audio is found, try DP audio */
1963 if (i == dc->res_pool->pipe_count) {
1964 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1965 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1967 if (pipe_ctx->stream == NULL)
1970 if (pipe_ctx->top_pipe)
1973 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
1976 if (pipe_ctx->stream_res.audio != NULL) {
1977 struct audio_output audio_output;
1979 build_audio_output(context, pipe_ctx, &audio_output);
1981 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
1982 pipe_ctx->stream_res.audio,
1983 pipe_ctx->stream->signal,
1984 &audio_output.crtc_info,
1985 &audio_output.pll_info);
1992 enum dc_status dce110_apply_ctx_to_hw(
1994 struct dc_state *context)
1996 struct dc_bios *dcb = dc->ctx->dc_bios;
1997 enum dc_status status;
2000 /* Reset old context */
2001 /* look up the targets that have been removed since last commit */
2002 dc->hwss.reset_hw_ctx_wrap(dc, context);
2004 /* Skip applying if no targets */
2005 if (context->stream_count <= 0)
2008 /* Apply new context */
2009 dcb->funcs->set_scratch_critical_state(dcb, true);
2011 /* below is for real asic only */
2012 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2013 struct pipe_ctx *pipe_ctx_old =
2014 &dc->current_state->res_ctx.pipe_ctx[i];
2015 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2017 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2020 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2021 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2022 dce_crtc_switch_to_clk_src(dc->hwseq,
2023 pipe_ctx->clock_source, i);
2027 dc->hwss.enable_display_power_gating(
2028 dc, i, dc->ctx->dc_bios,
2029 PIPE_GATING_CONTROL_DISABLE);
2032 if (dc->fbc_compressor)
2033 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2035 dce110_setup_audio_dto(dc, context);
2037 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2038 struct pipe_ctx *pipe_ctx_old =
2039 &dc->current_state->res_ctx.pipe_ctx[i];
2040 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2042 if (pipe_ctx->stream == NULL)
2045 if (pipe_ctx->stream == pipe_ctx_old->stream)
2048 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2051 if (pipe_ctx->top_pipe)
2054 status = apply_single_controller_ctx_to_hw(
2059 if (DC_OK != status)
2063 dcb->funcs->set_scratch_critical_state(dcb, false);
2065 if (dc->fbc_compressor)
2066 enable_fbc(dc, context);
2071 /*******************************************************************************
2072 * Front End programming
2073 ******************************************************************************/
2074 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2076 struct default_adjustment default_adjust = { 0 };
2078 default_adjust.force_hw_default = false;
2079 default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2080 default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2081 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2082 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2084 /* display color depth */
2085 default_adjust.color_depth =
2086 pipe_ctx->stream->timing.display_color_depth;
2088 /* Lb color depth */
2089 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2091 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2092 pipe_ctx->plane_res.xfm, &default_adjust);
2096 /*******************************************************************************
2097 * In order to turn on/off specific surface we will program
2100 * In case that we have two surfaces and they have a different visibility
2101 * we can't turn off the CRTC since it will turn off the entire display
2103 * |----------------------------------------------- |
2104 * |bottom pipe|curr pipe | | |
2105 * |Surface |Surface | Blender | CRCT |
2106 * |visibility |visibility | Configuration| |
2107 * |------------------------------------------------|
2108 * | off | off | CURRENT_PIPE | blank |
2109 * | off | on | CURRENT_PIPE | unblank |
2110 * | on | off | OTHER_PIPE | unblank |
2111 * | on | on | BLENDING | unblank |
2112 * -------------------------------------------------|
2114 ******************************************************************************/
2115 static void program_surface_visibility(const struct dc *dc,
2116 struct pipe_ctx *pipe_ctx)
2118 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2119 bool blank_target = false;
2121 if (pipe_ctx->bottom_pipe) {
2123 /* For now we are supporting only two pipes */
2124 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2126 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2127 if (pipe_ctx->plane_state->visible)
2128 blender_mode = BLND_MODE_BLENDING;
2130 blender_mode = BLND_MODE_OTHER_PIPE;
2132 } else if (!pipe_ctx->plane_state->visible)
2133 blank_target = true;
2135 } else if (!pipe_ctx->plane_state->visible)
2136 blank_target = true;
2138 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2139 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2143 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2146 struct xfm_grph_csc_adjustment adjust;
2147 memset(&adjust, 0, sizeof(adjust));
2148 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2151 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2152 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2154 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2155 adjust.temperature_matrix[i] =
2156 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2159 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2161 static void update_plane_addr(const struct dc *dc,
2162 struct pipe_ctx *pipe_ctx)
2164 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2166 if (plane_state == NULL)
2169 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2170 pipe_ctx->plane_res.mi,
2171 &plane_state->address,
2172 plane_state->flip_immediate);
2174 plane_state->status.requested_address = plane_state->address;
2177 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2179 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2181 if (plane_state == NULL)
2184 plane_state->status.is_flip_pending =
2185 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2186 pipe_ctx->plane_res.mi);
2188 if (plane_state->status.is_flip_pending && !plane_state->visible)
2189 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2191 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2192 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2193 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2194 plane_state->status.is_right_eye =\
2195 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2199 void dce110_power_down(struct dc *dc)
2201 power_down_all_hw_blocks(dc);
2202 disable_vga_and_power_gate_all_controllers(dc);
2205 static bool wait_for_reset_trigger_to_occur(
2206 struct dc_context *dc_ctx,
2207 struct timing_generator *tg)
2211 /* To avoid endless loop we wait at most
2212 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2213 const uint32_t frames_to_wait_on_triggered_reset = 10;
2216 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2218 if (!tg->funcs->is_counter_moving(tg)) {
2219 DC_ERROR("TG counter is not moving!\n");
2223 if (tg->funcs->did_triggered_reset_occur(tg)) {
2225 /* usually occurs at i=1 */
2226 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2231 /* Wait for one frame. */
2232 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2233 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2237 DC_ERROR("GSL: Timeout on reset trigger!\n");
2242 /* Enable timing synchronization for a group of Timing Generators. */
2243 static void dce110_enable_timing_synchronization(
2247 struct pipe_ctx *grouped_pipes[])
2249 struct dc_context *dc_ctx = dc->ctx;
2250 struct dcp_gsl_params gsl_params = { 0 };
2253 DC_SYNC_INFO("GSL: Setting-up...\n");
2255 /* Designate a single TG in the group as a master.
2256 * Since HW doesn't care which one, we always assign
2257 * the 1st one in the group. */
2258 gsl_params.gsl_group = 0;
2259 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2261 for (i = 0; i < group_size; i++)
2262 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2263 grouped_pipes[i]->stream_res.tg, &gsl_params);
2265 /* Reset slave controllers on master VSync */
2266 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2268 for (i = 1 /* skip the master */; i < group_size; i++)
2269 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2270 grouped_pipes[i]->stream_res.tg,
2271 gsl_params.gsl_group);
2273 for (i = 1 /* skip the master */; i < group_size; i++) {
2274 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2275 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2276 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2277 grouped_pipes[i]->stream_res.tg);
2280 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2281 * is that the sync'ed displays will not drift out of sync over time*/
2282 DC_SYNC_INFO("GSL: Restoring register states.\n");
2283 for (i = 0; i < group_size; i++)
2284 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2286 DC_SYNC_INFO("GSL: Set-up complete.\n");
2289 static void dce110_enable_per_frame_crtc_position_reset(
2292 struct pipe_ctx *grouped_pipes[])
2294 struct dc_context *dc_ctx = dc->ctx;
2295 struct dcp_gsl_params gsl_params = { 0 };
2298 gsl_params.gsl_group = 0;
2299 gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst;
2301 for (i = 0; i < group_size; i++)
2302 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2303 grouped_pipes[i]->stream_res.tg, &gsl_params);
2305 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2307 for (i = 1; i < group_size; i++)
2308 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2309 grouped_pipes[i]->stream_res.tg,
2310 gsl_params.gsl_master,
2311 &grouped_pipes[i]->stream->triggered_crtc_reset);
2313 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2314 for (i = 1; i < group_size; i++)
2315 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2317 for (i = 0; i < group_size; i++)
2318 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2322 static void init_hw(struct dc *dc)
2326 struct transform *xfm;
2329 bp = dc->ctx->dc_bios;
2330 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2331 xfm = dc->res_pool->transforms[i];
2332 xfm->funcs->transform_reset(xfm);
2334 dc->hwss.enable_display_power_gating(
2336 PIPE_GATING_CONTROL_INIT);
2337 dc->hwss.enable_display_power_gating(
2339 PIPE_GATING_CONTROL_DISABLE);
2340 dc->hwss.enable_display_pipe_clock_gating(
2345 dce_clock_gating_power_up(dc->hwseq, false);
2346 /***************************************/
2348 for (i = 0; i < dc->link_count; i++) {
2349 /****************************************/
2350 /* Power up AND update implementation according to the
2351 * required signal (which may be different from the
2352 * default signal on connector). */
2353 struct dc_link *link = dc->links[i];
2355 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
2356 dc->hwss.edp_power_control(link, true);
2358 link->link_enc->funcs->hw_init(link->link_enc);
2361 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2362 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2364 tg->funcs->disable_vga(tg);
2366 /* Blank controller using driver code instead of
2368 tg->funcs->set_blank(tg, true);
2369 hwss_wait_for_blank_complete(tg);
2372 for (i = 0; i < dc->res_pool->audio_count; i++) {
2373 struct audio *audio = dc->res_pool->audios[i];
2374 audio->funcs->hw_init(audio);
2377 abm = dc->res_pool->abm;
2379 abm->funcs->init_backlight(abm);
2380 abm->funcs->abm_init(abm);
2383 if (dc->fbc_compressor)
2384 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2388 void dce110_fill_display_configs(
2389 const struct dc_state *context,
2390 struct dm_pp_display_configuration *pp_display_cfg)
2395 for (j = 0; j < context->stream_count; j++) {
2398 const struct dc_stream_state *stream = context->streams[j];
2399 struct dm_pp_single_disp_config *cfg =
2400 &pp_display_cfg->disp_configs[num_cfgs];
2401 const struct pipe_ctx *pipe_ctx = NULL;
2403 for (k = 0; k < MAX_PIPES; k++)
2404 if (stream == context->res_ctx.pipe_ctx[k].stream) {
2405 pipe_ctx = &context->res_ctx.pipe_ctx[k];
2409 ASSERT(pipe_ctx != NULL);
2411 /* only notify active stream */
2412 if (stream->dpms_off)
2416 cfg->signal = pipe_ctx->stream->signal;
2417 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
2418 cfg->src_height = stream->src.height;
2419 cfg->src_width = stream->src.width;
2420 cfg->ddi_channel_mapping =
2421 stream->sink->link->ddi_channel_mapping.raw;
2423 stream->sink->link->link_enc->transmitter;
2424 cfg->link_settings.lane_count =
2425 stream->sink->link->cur_link_settings.lane_count;
2426 cfg->link_settings.link_rate =
2427 stream->sink->link->cur_link_settings.link_rate;
2428 cfg->link_settings.link_spread =
2429 stream->sink->link->cur_link_settings.link_spread;
2430 cfg->sym_clock = stream->phy_pix_clk;
2431 /* Round v_refresh*/
2432 cfg->v_refresh = stream->timing.pix_clk_khz * 1000;
2433 cfg->v_refresh /= stream->timing.h_total;
2434 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
2435 / stream->timing.v_total;
2438 pp_display_cfg->display_count = num_cfgs;
2441 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
2444 uint32_t min_vertical_blank_time = -1;
2446 for (j = 0; j < context->stream_count; j++) {
2447 struct dc_stream_state *stream = context->streams[j];
2448 uint32_t vertical_blank_in_pixels = 0;
2449 uint32_t vertical_blank_time = 0;
2451 vertical_blank_in_pixels = stream->timing.h_total *
2452 (stream->timing.v_total
2453 - stream->timing.v_addressable);
2455 vertical_blank_time = vertical_blank_in_pixels
2456 * 1000 / stream->timing.pix_clk_khz;
2458 if (min_vertical_blank_time > vertical_blank_time)
2459 min_vertical_blank_time = vertical_blank_time;
2462 return min_vertical_blank_time;
2465 static int determine_sclk_from_bounding_box(
2466 const struct dc *dc,
2472 * Some asics do not give us sclk levels, so we just report the actual
2475 if (dc->sclk_lvls.num_levels == 0)
2476 return required_sclk;
2478 for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
2479 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
2480 return dc->sclk_lvls.clocks_in_khz[i];
2483 * even maximum level could not satisfy requirement, this
2484 * is unexpected at this stage, should have been caught at
2488 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
2491 static void pplib_apply_display_requirements(
2493 struct dc_state *context)
2495 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2497 pp_display_cfg->all_displays_in_sync =
2498 context->bw.dce.all_displays_in_sync;
2499 pp_display_cfg->nb_pstate_switch_disable =
2500 context->bw.dce.nbp_state_change_enable == false;
2501 pp_display_cfg->cpu_cc6_disable =
2502 context->bw.dce.cpuc_state_change_enable == false;
2503 pp_display_cfg->cpu_pstate_disable =
2504 context->bw.dce.cpup_state_change_enable == false;
2505 pp_display_cfg->cpu_pstate_separation_time =
2506 context->bw.dce.blackout_recovery_time_us;
2508 pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
2509 / MEMORY_TYPE_MULTIPLIER;
2511 pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
2513 context->bw.dce.sclk_khz);
2515 pp_display_cfg->min_engine_clock_deep_sleep_khz
2516 = context->bw.dce.sclk_deep_sleep_khz;
2518 pp_display_cfg->avail_mclk_switch_time_us =
2519 dce110_get_min_vblank_time_us(context);
2521 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
2523 pp_display_cfg->disp_clk_khz = dc->res_pool->dccg->clks.dispclk_khz;
2525 dce110_fill_display_configs(context, pp_display_cfg);
2527 /* TODO: is this still applicable?*/
2528 if (pp_display_cfg->display_count == 1) {
2529 const struct dc_crtc_timing *timing =
2530 &context->streams[0]->timing;
2532 pp_display_cfg->crtc_index =
2533 pp_display_cfg->disp_configs[0].pipe_idx;
2534 pp_display_cfg->line_time_in_us = timing->h_total * 1000
2535 / timing->pix_clk_khz;
2538 if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2539 struct dm_pp_display_configuration)) != 0)
2540 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2542 dc->prev_display_config = *pp_display_cfg;
2545 static void dce110_set_bandwidth(
2547 struct dc_state *context,
2548 bool decrease_allowed)
2550 struct dc_clocks req_clks;
2551 struct dccg *dccg = dc->res_pool->dccg;
2553 req_clks.dispclk_khz = context->bw.dce.dispclk_khz;
2554 req_clks.phyclk_khz = get_max_pixel_clock_for_all_paths(dc, context);
2556 if (decrease_allowed)
2557 dce110_set_displaymarks(dc, context);
2559 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2561 if (dccg->funcs->update_dfs_bypass)
2562 dccg->funcs->update_dfs_bypass(
2566 req_clks.dispclk_khz);
2568 dccg->funcs->update_clocks(
2572 pplib_apply_display_requirements(dc, context);
2575 static void dce110_program_front_end_for_pipe(
2576 struct dc *dc, struct pipe_ctx *pipe_ctx)
2578 struct mem_input *mi = pipe_ctx->plane_res.mi;
2579 struct pipe_ctx *old_pipe = NULL;
2580 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2581 struct xfm_grph_csc_adjustment adjust;
2582 struct out_csc_color_matrix tbl_entry;
2583 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
2586 memset(&tbl_entry, 0, sizeof(tbl_entry));
2588 if (dc->current_state)
2589 old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2591 memset(&adjust, 0, sizeof(adjust));
2592 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2594 dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2596 set_default_colors(pipe_ctx);
2597 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2599 tbl_entry.color_space =
2600 pipe_ctx->stream->output_color_space;
2602 for (i = 0; i < 12; i++)
2603 tbl_entry.regval[i] =
2604 pipe_ctx->stream->csc_color_matrix.matrix[i];
2606 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2607 (pipe_ctx->plane_res.xfm, &tbl_entry);
2610 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2611 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2613 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2614 adjust.temperature_matrix[i] =
2615 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2618 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2620 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2622 program_scaler(dc, pipe_ctx);
2624 /* fbc not applicable on Underlay pipe */
2625 if (dc->fbc_compressor && old_pipe->stream &&
2626 pipe_ctx->pipe_idx != underlay_idx) {
2627 if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2628 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2630 enable_fbc(dc, dc->current_state);
2633 mi->funcs->mem_input_program_surface_config(
2635 plane_state->format,
2636 &plane_state->tiling_info,
2637 &plane_state->plane_size,
2638 plane_state->rotation,
2641 if (mi->funcs->set_blank)
2642 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2644 if (dc->config.gpu_vm_support)
2645 mi->funcs->mem_input_program_pte_vm(
2646 pipe_ctx->plane_res.mi,
2647 plane_state->format,
2648 &plane_state->tiling_info,
2649 plane_state->rotation);
2651 /* Moved programming gamma from dc to hwss */
2652 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2653 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2654 pipe_ctx->plane_state->update_flags.bits.gamma_change)
2655 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2657 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2658 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2661 "Pipe:%d %p: addr hi:0x%x, "
2664 " %d; dst: %d, %d, %d, %d;"
2665 "clip: %d, %d, %d, %d\n",
2667 (void *) pipe_ctx->plane_state,
2668 pipe_ctx->plane_state->address.grph.addr.high_part,
2669 pipe_ctx->plane_state->address.grph.addr.low_part,
2670 pipe_ctx->plane_state->src_rect.x,
2671 pipe_ctx->plane_state->src_rect.y,
2672 pipe_ctx->plane_state->src_rect.width,
2673 pipe_ctx->plane_state->src_rect.height,
2674 pipe_ctx->plane_state->dst_rect.x,
2675 pipe_ctx->plane_state->dst_rect.y,
2676 pipe_ctx->plane_state->dst_rect.width,
2677 pipe_ctx->plane_state->dst_rect.height,
2678 pipe_ctx->plane_state->clip_rect.x,
2679 pipe_ctx->plane_state->clip_rect.y,
2680 pipe_ctx->plane_state->clip_rect.width,
2681 pipe_ctx->plane_state->clip_rect.height);
2684 "Pipe %d: width, height, x, y\n"
2685 "viewport:%d, %d, %d, %d\n"
2686 "recout: %d, %d, %d, %d\n",
2688 pipe_ctx->plane_res.scl_data.viewport.width,
2689 pipe_ctx->plane_res.scl_data.viewport.height,
2690 pipe_ctx->plane_res.scl_data.viewport.x,
2691 pipe_ctx->plane_res.scl_data.viewport.y,
2692 pipe_ctx->plane_res.scl_data.recout.width,
2693 pipe_ctx->plane_res.scl_data.recout.height,
2694 pipe_ctx->plane_res.scl_data.recout.x,
2695 pipe_ctx->plane_res.scl_data.recout.y);
2698 static void dce110_apply_ctx_for_surface(
2700 const struct dc_stream_state *stream,
2702 struct dc_state *context)
2706 if (num_planes == 0)
2709 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2710 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2711 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2713 if (stream == pipe_ctx->stream) {
2714 if (!pipe_ctx->top_pipe &&
2715 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2716 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
2720 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2721 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2723 if (pipe_ctx->stream != stream)
2726 /* Need to allocate mem before program front end for Fiji */
2727 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2728 pipe_ctx->plane_res.mi,
2729 pipe_ctx->stream->timing.h_total,
2730 pipe_ctx->stream->timing.v_total,
2731 pipe_ctx->stream->timing.pix_clk_khz,
2732 context->stream_count);
2734 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2736 dc->hwss.update_plane_addr(dc, pipe_ctx);
2738 program_surface_visibility(dc, pipe_ctx);
2742 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2743 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2744 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2746 if ((stream == pipe_ctx->stream) &&
2747 (!pipe_ctx->top_pipe) &&
2748 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2749 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
2753 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2755 int fe_idx = pipe_ctx->plane_res.mi ?
2756 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2758 /* Do not power down fe when stream is active on dce*/
2759 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2762 dc->hwss.enable_display_power_gating(
2763 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2765 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2766 dc->res_pool->transforms[fe_idx]);
2769 static void dce110_wait_for_mpcc_disconnect(
2771 struct resource_pool *res_pool,
2772 struct pipe_ctx *pipe_ctx)
2777 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
2778 enum dc_color_space colorspace,
2782 struct out_csc_color_matrix tbl_entry;
2784 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2786 enum dc_color_space color_space =
2787 pipe_ctx->stream->output_color_space;
2789 //uint16_t matrix[12];
2790 for (i = 0; i < 12; i++)
2791 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2793 tbl_entry.color_space = color_space;
2794 //tbl_entry.regval = matrix;
2795 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry);
2799 void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2801 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2802 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2803 struct mem_input *mi = pipe_ctx->plane_res.mi;
2804 struct dc_cursor_mi_param param = {
2805 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
2806 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
2807 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2808 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2809 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2810 .rotation = pipe_ctx->plane_state->rotation,
2811 .mirror = pipe_ctx->plane_state->horizontal_mirror
2814 if (pipe_ctx->plane_state->address.type
2815 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2816 pos_cpy.enable = false;
2818 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2819 pos_cpy.enable = false;
2821 if (ipp->funcs->ipp_cursor_set_position)
2822 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m);
2823 if (mi->funcs->set_cursor_position)
2824 mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m);
2827 void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2829 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2831 if (pipe_ctx->plane_res.ipp &&
2832 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2833 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2834 pipe_ctx->plane_res.ipp, attributes);
2836 if (pipe_ctx->plane_res.mi &&
2837 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2838 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2839 pipe_ctx->plane_res.mi, attributes);
2841 if (pipe_ctx->plane_res.xfm &&
2842 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2843 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2844 pipe_ctx->plane_res.xfm, attributes);
2847 static void ready_shared_resources(struct dc *dc, struct dc_state *context) {}
2849 static void optimize_shared_resources(struct dc *dc) {}
2851 static const struct hw_sequencer_funcs dce110_funcs = {
2852 .program_gamut_remap = program_gamut_remap,
2853 .program_csc_matrix = program_csc_matrix,
2855 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2856 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2857 .update_plane_addr = update_plane_addr,
2858 .update_pending_status = dce110_update_pending_status,
2859 .set_input_transfer_func = dce110_set_input_transfer_func,
2860 .set_output_transfer_func = dce110_set_output_transfer_func,
2861 .power_down = dce110_power_down,
2862 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2863 .enable_timing_synchronization = dce110_enable_timing_synchronization,
2864 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
2865 .update_info_frame = dce110_update_info_frame,
2866 .enable_stream = dce110_enable_stream,
2867 .disable_stream = dce110_disable_stream,
2868 .unblank_stream = dce110_unblank_stream,
2869 .blank_stream = dce110_blank_stream,
2870 .enable_audio_stream = dce110_enable_audio_stream,
2871 .disable_audio_stream = dce110_disable_audio_stream,
2872 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2873 .enable_display_power_gating = dce110_enable_display_power_gating,
2874 .disable_plane = dce110_power_down_fe,
2875 .pipe_control_lock = dce_pipe_control_lock,
2876 .set_bandwidth = dce110_set_bandwidth,
2878 .get_position = get_position,
2879 .set_static_screen_control = set_static_screen_control,
2880 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2881 .enable_stream_timing = dce110_enable_stream_timing,
2882 .setup_stereo = NULL,
2883 .set_avmute = dce110_set_avmute,
2884 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
2885 .ready_shared_resources = ready_shared_resources,
2886 .optimize_shared_resources = optimize_shared_resources,
2887 .pplib_apply_display_requirements = pplib_apply_display_requirements,
2888 .edp_backlight_control = hwss_edp_backlight_control,
2889 .edp_power_control = hwss_edp_power_control,
2890 .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2891 .set_cursor_position = dce110_set_cursor_position,
2892 .set_cursor_attribute = dce110_set_cursor_attribute
2895 void dce110_hw_sequencer_construct(struct dc *dc)
2897 dc->hwss = dce110_funcs;