drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27
  28 #include "dm_services.h"
  29 #include "dc.h"
  30 #include "dc_bios_types.h"
  31 #include "core_types.h"
  32 #include "core_status.h"
  33 #include "resource.h"
  34 #include "dm_helpers.h"
  35 #include "dce110_hw_sequencer.h"
  36 #include "dce110_timing_generator.h"
  37 #include "dce/dce_hwseq.h"
  38 #include "gpio_service_interface.h"
  39
  40 #include "dce110_compressor.h"
  41
  42 #include "bios/bios_parser_helper.h"
  43 #include "timing_generator.h"
  44 #include "mem_input.h"
  45 #include "opp.h"
  46 #include "ipp.h"
  47 #include "transform.h"
  48 #include "stream_encoder.h"
  49 #include "link_encoder.h"
  50 #include "link_hwss.h"
  51 #include "clock_source.h"
  52 #include "clk_mgr.h"
  53 #include "abm.h"
  54 #include "audio.h"
  55 #include "reg_helper.h"
  56
  57 /* include DCE11 register header files */
  58 #include "dce/dce_11_0_d.h"
  59 #include "dce/dce_11_0_sh_mask.h"
  60 #include "custom_float.h"
  61
  62 #include "atomfirmware.h"
  63
  64 /*
  65  * All values are in milliseconds;
  66  * For eDP, after power-up/power/down,
  67  * 300/500 msec max. delay from LCDVCC to black video generation
  68  */
  69 #define PANEL_POWER_UP_TIMEOUT 300
  70 #define PANEL_POWER_DOWN_TIMEOUT 500
  71 #define HPD_CHECK_INTERVAL 10
  72
  73 #define CTX \
  74         hws->ctx
  75
  76 #define DC_LOGGER_INIT()
  77
  78 #define REG(reg)\
  79         hws->regs->reg
  80
  81 #undef FN
  82 #define FN(reg_name, field_name) \
  83         hws->shifts->field_name, hws->masks->field_name
  84
  85 struct dce110_hw_seq_reg_offsets {
  86         uint32_t crtc;
  87 };
  88
  89 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
  90 {
  91         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  92 },
  93 {
  94         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  95 },
  96 {
  97         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  98 },
  99 {
 100         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 101 }
 102 };
 103
 104 #define HW_REG_BLND(reg, id)\
 105         (reg + reg_offsets[id].blnd)
 106
 107 #define HW_REG_CRTC(reg, id)\
 108         (reg + reg_offsets[id].crtc)
 109
 110 #define MAX_WATERMARK 0xFFFF
 111 #define SAFE_NBP_MARK 0x7FFF
 112
 113 /*******************************************************************************
 114  * Private definitions
 115  ******************************************************************************/
 116 /***************************PIPE_CONTROL***********************************/
 117 static void dce110_init_pte(struct dc_context *ctx)
 118 {
 119         uint32_t addr;
 120         uint32_t value = 0;
 121         uint32_t chunk_int = 0;
 122         uint32_t chunk_mul = 0;
 123
 124         addr = mmUNP_DVMM_PTE_CONTROL;
 125         value = dm_read_reg(ctx, addr);
 126
 127         set_reg_field_value(
 128                 value,
 129                 0,
 130                 DVMM_PTE_CONTROL,
 131                 DVMM_USE_SINGLE_PTE);
 132
 133         set_reg_field_value(
 134                 value,
 135                 1,
 136                 DVMM_PTE_CONTROL,
 137                 DVMM_PTE_BUFFER_MODE0);
 138
 139         set_reg_field_value(
 140                 value,
 141                 1,
 142                 DVMM_PTE_CONTROL,
 143                 DVMM_PTE_BUFFER_MODE1);
 144
 145         dm_write_reg(ctx, addr, value);
 146
 147         addr = mmDVMM_PTE_REQ;
 148         value = dm_read_reg(ctx, addr);
 149
 150         chunk_int = get_reg_field_value(
 151                 value,
 152                 DVMM_PTE_REQ,
 153                 HFLIP_PTEREQ_PER_CHUNK_INT);
 154
 155         chunk_mul = get_reg_field_value(
 156                 value,
 157                 DVMM_PTE_REQ,
 158                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 159
 160         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 161
 162                 set_reg_field_value(
 163                         value,
 164                         255,
 165                         DVMM_PTE_REQ,
 166                         MAX_PTEREQ_TO_ISSUE);
 167
 168                 set_reg_field_value(
 169                         value,
 170                         4,
 171                         DVMM_PTE_REQ,
 172                         HFLIP_PTEREQ_PER_CHUNK_INT);
 173
 174                 set_reg_field_value(
 175                         value,
 176                         4,
 177                         DVMM_PTE_REQ,
 178                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 179
 180                 dm_write_reg(ctx, addr, value);
 181         }
 182 }
 183 /**************************************************************************/
 184
 185 static void enable_display_pipe_clock_gating(
 186         struct dc_context *ctx,
 187         bool clock_gating)
 188 {
 189         /*TODO*/
 190 }
 191
 192 static bool dce110_enable_display_power_gating(
 193         struct dc *dc,
 194         uint8_t controller_id,
 195         struct dc_bios *dcb,
 196         enum pipe_gating_control power_gating)
 197 {
 198         enum bp_result bp_result = BP_RESULT_OK;
 199         enum bp_pipe_control_action cntl;
 200         struct dc_context *ctx = dc->ctx;
 201         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 202
 203         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
 204                 return true;
 205
 206         if (power_gating == PIPE_GATING_CONTROL_INIT)
 207                 cntl = ASIC_PIPE_INIT;
 208         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 209                 cntl = ASIC_PIPE_ENABLE;
 210         else
 211                 cntl = ASIC_PIPE_DISABLE;
 212
 213         if (controller_id == underlay_idx)
 214                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 215
 216         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
 217
 218                 bp_result = dcb->funcs->enable_disp_power_gating(
 219                                                 dcb, controller_id + 1, cntl);
 220
 221                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 222                  * by default when command table is called
 223                  *
 224                  * Bios parser accepts controller_id = 6 as indicative of
 225                  * underlay pipe in dce110. But we do not support more
 226                  * than 3.
 227                  */
 228                 if (controller_id < CONTROLLER_ID_MAX - 1)
 229                         dm_write_reg(ctx,
 230                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 231                                 0);
 232         }
 233
 234         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 235                 dce110_init_pte(ctx);
 236
 237         if (bp_result == BP_RESULT_OK)
 238                 return true;
 239         else
 240                 return false;
 241 }
 242
 243 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 244                 const struct dc_plane_state *plane_state)
 245 {
 246         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 247
 248         switch (plane_state->format) {
 249         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 250                 prescale_params->scale = 0x2082;
 251                 break;
 252         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 253         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 254                 prescale_params->scale = 0x2020;
 255                 break;
 256         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 257         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 258                 prescale_params->scale = 0x2008;
 259                 break;
 260         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 261         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 262                 prescale_params->scale = 0x2000;
 263                 break;
 264         default:
 265                 ASSERT(false);
 266                 break;
 267         }
 268 }
 269
 270 static bool
 271 dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
 272                                const struct dc_plane_state *plane_state)
 273 {
 274         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 275         const struct dc_transfer_func *tf = NULL;
 276         struct ipp_prescale_params prescale_params = { 0 };
 277         bool result = true;
 278
 279         if (ipp == NULL)
 280                 return false;
 281
 282         if (plane_state->in_transfer_func)
 283                 tf = plane_state->in_transfer_func;
 284
 285         build_prescale_params(&prescale_params, plane_state);
 286         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 287
 288         if (plane_state->gamma_correction &&
 289                         !plane_state->gamma_correction->is_identity &&
 290                         dce_use_lut(plane_state->format))
 291                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 292
 293         if (tf == NULL) {
 294                 /* Default case if no input transfer function specified */
 295                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 296         } else if (tf->type == TF_TYPE_PREDEFINED) {
 297                 switch (tf->tf) {
 298                 case TRANSFER_FUNCTION_SRGB:
 299                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 300                         break;
 301                 case TRANSFER_FUNCTION_BT709:
 302                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 303                         break;
 304                 case TRANSFER_FUNCTION_LINEAR:
 305                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 306                         break;
 307                 case TRANSFER_FUNCTION_PQ:
 308                 default:
 309                         result = false;
 310                         break;
 311                 }
 312         } else if (tf->type == TF_TYPE_BYPASS) {
 313                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 314         } else {
 315                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 316                 result = false;
 317         }
 318
 319         return result;
 320 }
 321
 322 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
 323                                     struct curve_points *arr_points,
 324                                     uint32_t hw_points_num)
 325 {
 326         struct custom_float_format fmt;
 327
 328         struct pwl_result_data *rgb = rgb_resulted;
 329
 330         uint32_t i = 0;
 331
 332         fmt.exponenta_bits = 6;
 333         fmt.mantissa_bits = 12;
 334         fmt.sign = true;
 335
 336         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 337                                             &arr_points[0].custom_float_x)) {
 338                 BREAK_TO_DEBUGGER();
 339                 return false;
 340         }
 341
 342         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 343                                             &arr_points[0].custom_float_offset)) {
 344                 BREAK_TO_DEBUGGER();
 345                 return false;
 346         }
 347
 348         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 349                                             &arr_points[0].custom_float_slope)) {
 350                 BREAK_TO_DEBUGGER();
 351                 return false;
 352         }
 353
 354         fmt.mantissa_bits = 10;
 355         fmt.sign = false;
 356
 357         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
 358                                             &arr_points[1].custom_float_x)) {
 359                 BREAK_TO_DEBUGGER();
 360                 return false;
 361         }
 362
 363         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
 364                                             &arr_points[1].custom_float_y)) {
 365                 BREAK_TO_DEBUGGER();
 366                 return false;
 367         }
 368
 369         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
 370                                             &arr_points[1].custom_float_slope)) {
 371                 BREAK_TO_DEBUGGER();
 372                 return false;
 373         }
 374
 375         fmt.mantissa_bits = 12;
 376         fmt.sign = true;
 377
 378         while (i != hw_points_num) {
 379                 if (!convert_to_custom_float_format(rgb->red, &fmt,
 380                                                     &rgb->red_reg)) {
 381                         BREAK_TO_DEBUGGER();
 382                         return false;
 383                 }
 384
 385                 if (!convert_to_custom_float_format(rgb->green, &fmt,
 386                                                     &rgb->green_reg)) {
 387                         BREAK_TO_DEBUGGER();
 388                         return false;
 389                 }
 390
 391                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
 392                                                     &rgb->blue_reg)) {
 393                         BREAK_TO_DEBUGGER();
 394                         return false;
 395                 }
 396
 397                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
 398                                                     &rgb->delta_red_reg)) {
 399                         BREAK_TO_DEBUGGER();
 400                         return false;
 401                 }
 402
 403                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
 404                                                     &rgb->delta_green_reg)) {
 405                         BREAK_TO_DEBUGGER();
 406                         return false;
 407                 }
 408
 409                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
 410                                                     &rgb->delta_blue_reg)) {
 411                         BREAK_TO_DEBUGGER();
 412                         return false;
 413                 }
 414
 415                 ++rgb;
 416                 ++i;
 417         }
 418
 419         return true;
 420 }
 421
 422 #define MAX_LOW_POINT      25
 423 #define NUMBER_REGIONS     16
 424 #define NUMBER_SW_SEGMENTS 16
 425
 426 static bool
 427 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
 428                                       struct pwl_params *regamma_params)
 429 {
 430         struct curve_points *arr_points;
 431         struct pwl_result_data *rgb_resulted;
 432         struct pwl_result_data *rgb;
 433         struct pwl_result_data *rgb_plus_1;
 434         struct fixed31_32 y_r;
 435         struct fixed31_32 y_g;
 436         struct fixed31_32 y_b;
 437         struct fixed31_32 y1_min;
 438         struct fixed31_32 y3_max;
 439
 440         int32_t region_start, region_end;
 441         uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
 442
 443         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 444                 return false;
 445
 446         arr_points = regamma_params->arr_points;
 447         rgb_resulted = regamma_params->rgb_resulted;
 448         hw_points = 0;
 449
 450         memset(regamma_params, 0, sizeof(struct pwl_params));
 451
 452         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 453                 /* 16 segments
 454                  * segments are from 2^-11 to 2^5
 455                  */
 456                 region_start = -11;
 457                 region_end = region_start + NUMBER_REGIONS;
 458
 459                 for (i = 0; i < NUMBER_REGIONS; i++)
 460                         seg_distr[i] = 4;
 461
 462         } else {
 463                 /* 10 segments
 464                  * segment is from 2^-10 to 2^1
 465                  * We include an extra segment for range [2^0, 2^1). This is to
 466                  * ensure that colors with normalized values of 1 don't miss the
 467                  * LUT.
 468                  */
 469                 region_start = -10;
 470                 region_end = 1;
 471
 472                 seg_distr[0] = 4;
 473                 seg_distr[1] = 4;
 474                 seg_distr[2] = 4;
 475                 seg_distr[3] = 4;
 476                 seg_distr[4] = 4;
 477                 seg_distr[5] = 4;
 478                 seg_distr[6] = 4;
 479                 seg_distr[7] = 4;
 480                 seg_distr[8] = 4;
 481                 seg_distr[9] = 4;
 482                 seg_distr[10] = 0;
 483                 seg_distr[11] = -1;
 484                 seg_distr[12] = -1;
 485                 seg_distr[13] = -1;
 486                 seg_distr[14] = -1;
 487                 seg_distr[15] = -1;
 488         }
 489
 490         for (k = 0; k < 16; k++) {
 491                 if (seg_distr[k] != -1)
 492                         hw_points += (1 << seg_distr[k]);
 493         }
 494
 495         j = 0;
 496         for (k = 0; k < (region_end - region_start); k++) {
 497                 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
 498                 start_index = (region_start + k + MAX_LOW_POINT) *
 499                                 NUMBER_SW_SEGMENTS;
 500                 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 501                                 i += increment) {
 502                         if (j == hw_points - 1)
 503                                 break;
 504                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 505                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 506                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 507                         j++;
 508                 }
 509         }
 510
 511         /* last point */
 512         start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
 513         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
 514         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
 515         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 516
 517         arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 518                                              dc_fixpt_from_int(region_start));
 519         arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 520                                              dc_fixpt_from_int(region_end));
 521
 522         y_r = rgb_resulted[0].red;
 523         y_g = rgb_resulted[0].green;
 524         y_b = rgb_resulted[0].blue;
 525
 526         y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 527
 528         arr_points[0].y = y1_min;
 529         arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
 530                                                  arr_points[0].x);
 531
 532         y_r = rgb_resulted[hw_points - 1].red;
 533         y_g = rgb_resulted[hw_points - 1].green;
 534         y_b = rgb_resulted[hw_points - 1].blue;
 535
 536         /* see comment above, m_arrPoints[1].y should be the Y value for the
 537          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 538          */
 539         y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 540
 541         arr_points[1].y = y3_max;
 542
 543         arr_points[1].slope = dc_fixpt_zero;
 544
 545         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 546                 /* for PQ, we want to have a straight line from last HW X point,
 547                  * and the slope to be such that we hit 1.0 at 10000 nits.
 548                  */
 549                 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
 550
 551                 arr_points[1].slope = dc_fixpt_div(
 552                                 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
 553                                 dc_fixpt_sub(end_value, arr_points[1].x));
 554         }
 555
 556         regamma_params->hw_points_num = hw_points;
 557
 558         k = 0;
 559         for (i = 1; i < 16; i++) {
 560                 if (seg_distr[k] != -1) {
 561                         regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 562                         regamma_params->arr_curve_points[i].offset =
 563                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 564                 }
 565                 k++;
 566         }
 567
 568         if (seg_distr[k] != -1)
 569                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 570
 571         rgb = rgb_resulted;
 572         rgb_plus_1 = rgb_resulted + 1;
 573
 574         i = 1;
 575
 576         while (i != hw_points + 1) {
 577                 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
 578                         rgb_plus_1->red = rgb->red;
 579                 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
 580                         rgb_plus_1->green = rgb->green;
 581                 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
 582                         rgb_plus_1->blue = rgb->blue;
 583
 584                 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
 585                 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
 586                 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
 587
 588                 ++rgb_plus_1;
 589                 ++rgb;
 590                 ++i;
 591         }
 592
 593         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 594
 595         return true;
 596 }
 597
 598 static bool
 599 dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
 600                                 const struct dc_stream_state *stream)
 601 {
 602         struct transform *xfm = pipe_ctx->plane_res.xfm;
 603
 604         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 605         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 606
 607         if (stream->out_transfer_func &&
 608             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 609             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 610                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 611         } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
 612                                                          &xfm->regamma_params)) {
 613                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 614                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 615         } else {
 616                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 617         }
 618
 619         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 620
 621         return true;
 622 }
 623
 624 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 625 {
 626         bool is_hdmi_tmds;
 627         bool is_dp;
 628
 629         ASSERT(pipe_ctx->stream);
 630
 631         if (pipe_ctx->stream_res.stream_enc == NULL)
 632                 return;  /* this is not root pipe */
 633
 634         is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
 635         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 636
 637         if (!is_hdmi_tmds && !is_dp)
 638                 return;
 639
 640         if (is_hdmi_tmds)
 641                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 642                         pipe_ctx->stream_res.stream_enc,
 643                         &pipe_ctx->stream_res.encoder_info_frame);
 644         else
 645                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 646                         pipe_ctx->stream_res.stream_enc,
 647                         &pipe_ctx->stream_res.encoder_info_frame);
 648 }
 649
 650 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 651 {
 652         enum dc_lane_count lane_count =
 653                 pipe_ctx->stream->link->cur_link_settings.lane_count;
 654
 655         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 656         struct dc_link *link = pipe_ctx->stream->link;
 657
 658
 659         uint32_t active_total_with_borders;
 660         uint32_t early_control = 0;
 661         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 662
 663         /* For MST, there are multiply stream go to only one link.
 664          * connect DIG back_end to front_end while enable_stream and
 665          * disconnect them during disable_stream
 666          * BY this, it is logic clean to separate stream and link */
 667         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
 668                                                     pipe_ctx->stream_res.stream_enc->id, true);
 669
 670         link->dc->hwss.update_info_frame(pipe_ctx);
 671
 672         /* enable early control to avoid corruption on DP monitor*/
 673         active_total_with_borders =
 674                         timing->h_addressable
 675                                 + timing->h_border_left
 676                                 + timing->h_border_right;
 677
 678         if (lane_count != 0)
 679                 early_control = active_total_with_borders % lane_count;
 680
 681         if (early_control == 0)
 682                 early_control = lane_count;
 683
 684         tg->funcs->set_early_control(tg, early_control);
 685
 686         /* enable audio only within mode set */
 687         if (pipe_ctx->stream_res.audio != NULL) {
 688                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
 689                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
 690         }
 691
 692
 693
 694
 695 }
 696
 697 /*todo: cloned in stream enc, fix*/
 698 static bool is_panel_backlight_on(struct dce_hwseq *hws)
 699 {
 700         uint32_t value;
 701
 702         REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
 703
 704         return value;
 705 }
 706
 707 static bool is_panel_powered_on(struct dce_hwseq *hws)
 708 {
 709         uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
 710
 711
 712         REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
 713
 714         REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
 715
 716         return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
 717 }
 718
 719 static enum bp_result link_transmitter_control(
 720                 struct dc_bios *bios,
 721         struct bp_transmitter_control *cntl)
 722 {
 723         enum bp_result result;
 724
 725         result = bios->funcs->transmitter_control(bios, cntl);
 726
 727         return result;
 728 }
 729
 730 /*
 731  * @brief
 732  * eDP only.
 733  */
 734 void dce110_edp_wait_for_hpd_ready(
 735                 struct dc_link *link,
 736                 bool power_up)
 737 {
 738         struct dc_context *ctx = link->ctx;
 739         struct graphics_object_id connector = link->link_enc->connector;
 740         struct gpio *hpd;
 741         bool edp_hpd_high = false;
 742         uint32_t time_elapsed = 0;
 743         uint32_t timeout = power_up ?
 744                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 745
 746         if (dal_graphics_object_id_get_connector_id(connector)
 747                         != CONNECTOR_ID_EDP) {
 748                 BREAK_TO_DEBUGGER();
 749                 return;
 750         }
 751
 752         if (!power_up)
 753                 /*
 754                  * From KV, we will not HPD low after turning off VCC -
 755                  * instead, we will check the SW timer in power_up().
 756                  */
 757                 return;
 758
 759         /*
 760          * When we power on/off the eDP panel,
 761          * we need to wait until SENSE bit is high/low.
 762          */
 763
 764         /* obtain HPD */
 765         /* TODO what to do with this? */
 766         hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 767
 768         if (!hpd) {
 769                 BREAK_TO_DEBUGGER();
 770                 return;
 771         }
 772
 773         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 774
 775         /* wait until timeout or panel detected */
 776
 777         do {
 778                 uint32_t detected = 0;
 779
 780                 dal_gpio_get_value(hpd, &detected);
 781
 782                 if (!(detected ^ power_up)) {
 783                         edp_hpd_high = true;
 784                         break;
 785                 }
 786
 787                 msleep(HPD_CHECK_INTERVAL);
 788
 789                 time_elapsed += HPD_CHECK_INTERVAL;
 790         } while (time_elapsed < timeout);
 791
 792         dal_gpio_close(hpd);
 793
 794         dal_gpio_destroy_irq(&hpd);
 795
 796         if (false == edp_hpd_high) {
 797                 DC_LOG_ERROR(
 798                                 "%s: wait timed out!\n", __func__);
 799         }
 800 }
 801
 802 void dce110_edp_power_control(
 803                 struct dc_link *link,
 804                 bool power_up)
 805 {
 806         struct dc_context *ctx = link->ctx;
 807         struct dce_hwseq *hwseq = ctx->dc->hwseq;
 808         struct bp_transmitter_control cntl = { 0 };
 809         enum bp_result bp_result;
 810
 811
 812         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 813                         != CONNECTOR_ID_EDP) {
 814                 BREAK_TO_DEBUGGER();
 815                 return;
 816         }
 817
 818         if (power_up != is_panel_powered_on(hwseq)) {
 819                 /* Send VBIOS command to prompt eDP panel power */
 820                 if (power_up) {
 821                         unsigned long long current_ts = dm_get_timestamp(ctx);
 822                         unsigned long long duration_in_ms =
 823                                         div64_u64(dm_get_elapse_time_in_ns(
 824                                                         ctx,
 825                                                         current_ts,
 826                                                         link->link_trace.time_stamp.edp_poweroff), 1000000);
 827                         unsigned long long wait_time_ms = 0;
 828
 829                         /* max 500ms from LCDVDD off to on */
 830                         unsigned long long edp_poweroff_time_ms = 500;
 831
 832                         if (link->local_sink != NULL)
 833                                 edp_poweroff_time_ms =
 834                                                 500 + link->local_sink->edid_caps.panel_patch.extra_t12_ms;
 835                         if (link->link_trace.time_stamp.edp_poweroff == 0)
 836                                 wait_time_ms = edp_poweroff_time_ms;
 837                         else if (duration_in_ms < edp_poweroff_time_ms)
 838                                 wait_time_ms = edp_poweroff_time_ms - duration_in_ms;
 839
 840                         if (wait_time_ms) {
 841                                 msleep(wait_time_ms);
 842                                 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
 843                                                 __func__, wait_time_ms);
 844                         }
 845
 846                 }
 847
 848                 DC_LOG_HW_RESUME_S3(
 849                                 "%s: Panel Power action: %s\n",
 850                                 __func__, (power_up ? "On":"Off"));
 851
 852                 cntl.action = power_up ?
 853                         TRANSMITTER_CONTROL_POWER_ON :
 854                         TRANSMITTER_CONTROL_POWER_OFF;
 855                 cntl.transmitter = link->link_enc->transmitter;
 856                 cntl.connector_obj_id = link->link_enc->connector;
 857                 cntl.coherent = false;
 858                 cntl.lanes_number = LANE_COUNT_FOUR;
 859                 cntl.hpd_sel = link->link_enc->hpd_source;
 860                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 861
 862                 if (!power_up)
 863                         /*save driver power off time stamp*/
 864                         link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
 865                 else
 866                         link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
 867
 868                 if (bp_result != BP_RESULT_OK)
 869                         DC_LOG_ERROR(
 870                                         "%s: Panel Power bp_result: %d\n",
 871                                         __func__, bp_result);
 872         } else {
 873                 DC_LOG_HW_RESUME_S3(
 874                                 "%s: Skipping Panel Power action: %s\n",
 875                                 __func__, (power_up ? "On":"Off"));
 876         }
 877 }
 878
 879 /*todo: cloned in stream enc, fix*/
 880 /*
 881  * @brief
 882  * eDP only. Control the backlight of the eDP panel
 883  */
 884 void dce110_edp_backlight_control(
 885                 struct dc_link *link,
 886                 bool enable)
 887 {
 888         struct dc_context *ctx = link->ctx;
 889         struct dce_hwseq *hws = ctx->dc->hwseq;
 890         struct bp_transmitter_control cntl = { 0 };
 891
 892         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 893                 != CONNECTOR_ID_EDP) {
 894                 BREAK_TO_DEBUGGER();
 895                 return;
 896         }
 897
 898         if (enable && is_panel_backlight_on(hws)) {
 899                 DC_LOG_HW_RESUME_S3(
 900                                 "%s: panel already powered up. Do nothing.\n",
 901                                 __func__);
 902                 return;
 903         }
 904
 905         /* Send VBIOS command to control eDP panel backlight */
 906
 907         DC_LOG_HW_RESUME_S3(
 908                         "%s: backlight action: %s\n",
 909                         __func__, (enable ? "On":"Off"));
 910
 911         cntl.action = enable ?
 912                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
 913                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
 914
 915         /*cntl.engine_id = ctx->engine;*/
 916         cntl.transmitter = link->link_enc->transmitter;
 917         cntl.connector_obj_id = link->link_enc->connector;
 918         /*todo: unhardcode*/
 919         cntl.lanes_number = LANE_COUNT_FOUR;
 920         cntl.hpd_sel = link->link_enc->hpd_source;
 921         cntl.signal = SIGNAL_TYPE_EDP;
 922
 923         /* For eDP, the following delays might need to be considered
 924          * after link training completed:
 925          * idle period - min. accounts for required BS-Idle pattern,
 926          * max. allows for source frame synchronization);
 927          * 50 msec max. delay from valid video data from source
 928          * to video on dislpay or backlight enable.
 929          *
 930          * Disable the delay for now.
 931          * Enable it in the future if necessary.
 932          */
 933         /* dc_service_sleep_in_milliseconds(50); */
 934                 /*edp 1.2*/
 935         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
 936                 edp_receiver_ready_T7(link);
 937         link_transmitter_control(ctx->dc_bios, &cntl);
 938         /*edp 1.2*/
 939         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
 940                 edp_receiver_ready_T9(link);
 941 }
 942
 943 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
 944 {
 945         /* notify audio driver for audio modes of monitor */
 946         struct dc *core_dc;
 947         struct pp_smu_funcs *pp_smu = NULL;
 948         struct clk_mgr *clk_mgr;
 949         unsigned int i, num_audio = 1;
 950
 951         if (!pipe_ctx->stream)
 952                 return;
 953
 954         core_dc = pipe_ctx->stream->ctx->dc;
 955         clk_mgr = core_dc->clk_mgr;
 956
 957         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
 958                 return;
 959
 960         if (core_dc->res_pool->pp_smu)
 961                 pp_smu = core_dc->res_pool->pp_smu;
 962
 963         if (pipe_ctx->stream_res.audio) {
 964                 for (i = 0; i < MAX_PIPES; i++) {
 965                         /*current_state not updated yet*/
 966                         if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
 967                                 num_audio++;
 968                 }
 969
 970                 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
 971
 972                 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
 973                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
 974                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
 975                 /* un-mute audio */
 976                 /* TODO: audio should be per stream rather than per link */
 977                 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
 978                                         pipe_ctx->stream_res.stream_enc, false);
 979                 if (pipe_ctx->stream_res.audio)
 980                         pipe_ctx->stream_res.audio->enabled = true;
 981         }
 982 }
 983
 984 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
 985 {
 986         struct dc *dc;
 987         struct pp_smu_funcs *pp_smu = NULL;
 988         struct clk_mgr *clk_mgr;
 989
 990         if (!pipe_ctx || !pipe_ctx->stream)
 991                 return;
 992
 993         dc = pipe_ctx->stream->ctx->dc;
 994         clk_mgr = dc->clk_mgr;
 995
 996         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
 997                 return;
 998
 999         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1000                         pipe_ctx->stream_res.stream_enc, true);
1001         if (pipe_ctx->stream_res.audio) {
1002                 pipe_ctx->stream_res.audio->enabled = false;
1003
1004                 if (dc->res_pool->pp_smu)
1005                         pp_smu = dc->res_pool->pp_smu;
1006
1007                 if (option != KEEP_ACQUIRED_RESOURCE ||
1008                                 !dc->debug.az_endpoint_mute_only)
1009                         /*only disalbe az_endpoint if power down or free*/
1010                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
1011
1012                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1013                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1014                                         pipe_ctx->stream_res.stream_enc);
1015                 else
1016                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1017                                         pipe_ctx->stream_res.stream_enc);
1018                 /*don't free audio if it is from retrain or internal disable stream*/
1019                 if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
1020                         /*we have to dynamic arbitrate the audio endpoints*/
1021                         /*we free the resource, need reset is_audio_acquired*/
1022                         update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
1023                         pipe_ctx->stream_res.audio = NULL;
1024                 }
1025                 if (clk_mgr->funcs->enable_pme_wa)
1026                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1027                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1028
1029                 /* TODO: notify audio driver for if audio modes list changed
1030                  * add audio mode list change flag */
1031                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1032                  * stream->stream_engine_id);
1033                  */
1034         }
1035 }
1036
1037 void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
1038 {
1039         struct dc_stream_state *stream = pipe_ctx->stream;
1040         struct dc_link *link = stream->link;
1041         struct dc *dc = pipe_ctx->stream->ctx->dc;
1042
1043         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1044                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1045                         pipe_ctx->stream_res.stream_enc);
1046                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1047                         pipe_ctx->stream_res.stream_enc);
1048         }
1049
1050         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1051                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1052                         pipe_ctx->stream_res.stream_enc);
1053
1054         dc->hwss.disable_audio_stream(pipe_ctx, option);
1055
1056         link->link_enc->funcs->connect_dig_be_to_fe(
1057                         link->link_enc,
1058                         pipe_ctx->stream_res.stream_enc->id,
1059                         false);
1060
1061 }
1062
1063 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1064                 struct dc_link_settings *link_settings)
1065 {
1066         struct encoder_unblank_param params = { { 0 } };
1067         struct dc_stream_state *stream = pipe_ctx->stream;
1068         struct dc_link *link = stream->link;
1069
1070         /* only 3 items below are used by unblank */
1071         params.timing = pipe_ctx->stream->timing;
1072         params.link_settings.link_rate = link_settings->link_rate;
1073
1074         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1075                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1076
1077         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1078                 link->dc->hwss.edp_backlight_control(link, true);
1079         }
1080 }
1081
1082 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1083 {
1084         struct dc_stream_state *stream = pipe_ctx->stream;
1085         struct dc_link *link = stream->link;
1086
1087         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1088                 link->dc->hwss.edp_backlight_control(link, false);
1089                 dc_link_set_abm_disable(link);
1090         }
1091
1092         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1093                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1094 }
1095
1096
1097 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1098 {
1099         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1100                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1101 }
1102
1103 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1104 {
1105         switch (crtc_id) {
1106         case CONTROLLER_ID_D0:
1107                 return DTO_SOURCE_ID0;
1108         case CONTROLLER_ID_D1:
1109                 return DTO_SOURCE_ID1;
1110         case CONTROLLER_ID_D2:
1111                 return DTO_SOURCE_ID2;
1112         case CONTROLLER_ID_D3:
1113                 return DTO_SOURCE_ID3;
1114         case CONTROLLER_ID_D4:
1115                 return DTO_SOURCE_ID4;
1116         case CONTROLLER_ID_D5:
1117                 return DTO_SOURCE_ID5;
1118         default:
1119                 return DTO_SOURCE_UNKNOWN;
1120         }
1121 }
1122
1123 static void build_audio_output(
1124         struct dc_state *state,
1125         const struct pipe_ctx *pipe_ctx,
1126         struct audio_output *audio_output)
1127 {
1128         const struct dc_stream_state *stream = pipe_ctx->stream;
1129         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1130
1131         audio_output->signal = pipe_ctx->stream->signal;
1132
1133         /* audio_crtc_info  */
1134
1135         audio_output->crtc_info.h_total =
1136                 stream->timing.h_total;
1137
1138         /*
1139          * Audio packets are sent during actual CRTC blank physical signal, we
1140          * need to specify actual active signal portion
1141          */
1142         audio_output->crtc_info.h_active =
1143                         stream->timing.h_addressable
1144                         + stream->timing.h_border_left
1145                         + stream->timing.h_border_right;
1146
1147         audio_output->crtc_info.v_active =
1148                         stream->timing.v_addressable
1149                         + stream->timing.v_border_top
1150                         + stream->timing.v_border_bottom;
1151
1152         audio_output->crtc_info.pixel_repetition = 1;
1153
1154         audio_output->crtc_info.interlaced =
1155                         stream->timing.flags.INTERLACE;
1156
1157         audio_output->crtc_info.refresh_rate =
1158                 (stream->timing.pix_clk_100hz*100)/
1159                 (stream->timing.h_total*stream->timing.v_total);
1160
1161         audio_output->crtc_info.color_depth =
1162                 stream->timing.display_color_depth;
1163
1164         audio_output->crtc_info.requested_pixel_clock_100Hz =
1165                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1166
1167         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1168                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1169
1170 /*for HDMI, audio ACR is with deep color ratio factor*/
1171         if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
1172                 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1173                                 (stream->timing.pix_clk_100hz)) {
1174                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1175                         audio_output->crtc_info.requested_pixel_clock_100Hz =
1176                                         audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1177                         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1178                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1179
1180                 }
1181         }
1182
1183         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1184                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1185                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1186                                 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1187                                                 state->clk_mgr);
1188         }
1189
1190         audio_output->pll_info.feed_back_divider =
1191                         pipe_ctx->pll_settings.feedback_divider;
1192
1193         audio_output->pll_info.dto_source =
1194                 translate_to_dto_source(
1195                         pipe_ctx->stream_res.tg->inst + 1);
1196
1197         /* TODO hard code to enable for now. Need get from stream */
1198         audio_output->pll_info.ss_enabled = true;
1199
1200         audio_output->pll_info.ss_percentage =
1201                         pipe_ctx->pll_settings.ss_percentage;
1202 }
1203
1204 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1205                 struct tg_color *color)
1206 {
1207         uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
1208
1209         switch (pipe_ctx->plane_res.scl_data.format) {
1210         case PIXEL_FORMAT_ARGB8888:
1211                 /* set boarder color to red */
1212                 color->color_r_cr = color_value;
1213                 break;
1214
1215         case PIXEL_FORMAT_ARGB2101010:
1216                 /* set boarder color to blue */
1217                 color->color_b_cb = color_value;
1218                 break;
1219         case PIXEL_FORMAT_420BPP8:
1220                 /* set boarder color to green */
1221                 color->color_g_y = color_value;
1222                 break;
1223         case PIXEL_FORMAT_420BPP10:
1224                 /* set boarder color to yellow */
1225                 color->color_g_y = color_value;
1226                 color->color_r_cr = color_value;
1227                 break;
1228         case PIXEL_FORMAT_FP16:
1229                 /* set boarder color to white */
1230                 color->color_r_cr = color_value;
1231                 color->color_b_cb = color_value;
1232                 color->color_g_y = color_value;
1233                 break;
1234         default:
1235                 break;
1236         }
1237 }
1238
1239 static void program_scaler(const struct dc *dc,
1240                 const struct pipe_ctx *pipe_ctx)
1241 {
1242         struct tg_color color = {0};
1243
1244 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1245         /* TOFPGA */
1246         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1247                 return;
1248 #endif
1249
1250         if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1251                 get_surface_visual_confirm_color(pipe_ctx, &color);
1252         else
1253                 color_space_to_black_color(dc,
1254                                 pipe_ctx->stream->output_color_space,
1255                                 &color);
1256
1257         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1258                 pipe_ctx->plane_res.xfm,
1259                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1260                 &pipe_ctx->stream->bit_depth_params);
1261
1262         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1263                 /*
1264                  * The way 420 is packed, 2 channels carry Y component, 1 channel
1265                  * alternate between Cb and Cr, so both channels need the pixel
1266                  * value for Y
1267                  */
1268                 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1269                         color.color_r_cr = color.color_g_y;
1270
1271                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1272                                 pipe_ctx->stream_res.tg,
1273                                 &color);
1274         }
1275
1276         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1277                 &pipe_ctx->plane_res.scl_data);
1278 }
1279
1280 static enum dc_status dce110_enable_stream_timing(
1281                 struct pipe_ctx *pipe_ctx,
1282                 struct dc_state *context,
1283                 struct dc *dc)
1284 {
1285         struct dc_stream_state *stream = pipe_ctx->stream;
1286         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1287                         pipe_ctx[pipe_ctx->pipe_idx];
1288         struct tg_color black_color = {0};
1289
1290         if (!pipe_ctx_old->stream) {
1291
1292                 /* program blank color */
1293                 color_space_to_black_color(dc,
1294                                 stream->output_color_space, &black_color);
1295                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1296                                 pipe_ctx->stream_res.tg,
1297                                 &black_color);
1298
1299                 /*
1300                  * Must blank CRTC after disabling power gating and before any
1301                  * programming, otherwise CRTC will be hung in bad state
1302                  */
1303                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1304
1305                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1306                                 pipe_ctx->clock_source,
1307                                 &pipe_ctx->stream_res.pix_clk_params,
1308                                 &pipe_ctx->pll_settings)) {
1309                         BREAK_TO_DEBUGGER();
1310                         return DC_ERROR_UNEXPECTED;
1311                 }
1312
1313                 pipe_ctx->stream_res.tg->funcs->program_timing(
1314                                 pipe_ctx->stream_res.tg,
1315                                 &stream->timing,
1316                                 0,
1317                                 0,
1318                                 0,
1319                                 0,
1320                                 pipe_ctx->stream->signal,
1321                                 true);
1322         }
1323
1324         if (!pipe_ctx_old->stream) {
1325                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1326                                 pipe_ctx->stream_res.tg)) {
1327                         BREAK_TO_DEBUGGER();
1328                         return DC_ERROR_UNEXPECTED;
1329                 }
1330         }
1331
1332         return DC_OK;
1333 }
1334
1335 static enum dc_status apply_single_controller_ctx_to_hw(
1336                 struct pipe_ctx *pipe_ctx,
1337                 struct dc_state *context,
1338                 struct dc *dc)
1339 {
1340         struct dc_stream_state *stream = pipe_ctx->stream;
1341         struct drr_params params = {0};
1342         unsigned int event_triggers = 0;
1343 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
1344         struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1345 #endif
1346
1347         if (dc->hwss.disable_stream_gating) {
1348                 dc->hwss.disable_stream_gating(dc, pipe_ctx);
1349         }
1350
1351         if (pipe_ctx->stream_res.audio != NULL) {
1352                 struct audio_output audio_output;
1353
1354                 build_audio_output(context, pipe_ctx, &audio_output);
1355
1356                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1357                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1358                                         pipe_ctx->stream_res.stream_enc,
1359                                         pipe_ctx->stream_res.audio->inst,
1360                                         &pipe_ctx->stream->audio_info);
1361                 else
1362                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1363                                         pipe_ctx->stream_res.stream_enc,
1364                                         pipe_ctx->stream_res.audio->inst,
1365                                         &pipe_ctx->stream->audio_info,
1366                                         &audio_output.crtc_info);
1367
1368                 pipe_ctx->stream_res.audio->funcs->az_configure(
1369                                 pipe_ctx->stream_res.audio,
1370                                 pipe_ctx->stream->signal,
1371                                 &audio_output.crtc_info,
1372                                 &pipe_ctx->stream->audio_info);
1373         }
1374
1375         /*  */
1376         /* Do not touch stream timing on seamless boot optimization. */
1377         if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1378                 dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
1379
1380         if (dc->hwss.setup_vupdate_interrupt)
1381                 dc->hwss.setup_vupdate_interrupt(pipe_ctx);
1382
1383         params.vertical_total_min = stream->adjust.v_total_min;
1384         params.vertical_total_max = stream->adjust.v_total_max;
1385         if (pipe_ctx->stream_res.tg->funcs->set_drr)
1386                 pipe_ctx->stream_res.tg->funcs->set_drr(
1387                         pipe_ctx->stream_res.tg, &params);
1388
1389         // DRR should set trigger event to monitor surface update event
1390         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1391                 event_triggers = 0x80;
1392         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1393                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1394                                 pipe_ctx->stream_res.tg, event_triggers);
1395
1396         if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1397                 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1398                         pipe_ctx->stream_res.stream_enc,
1399                         pipe_ctx->stream_res.tg->inst);
1400
1401         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1402                         pipe_ctx->stream_res.opp,
1403                         COLOR_SPACE_YCBCR601,
1404                         stream->timing.display_color_depth,
1405                         stream->signal);
1406
1407         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1408                 pipe_ctx->stream_res.opp,
1409                 &stream->bit_depth_params,
1410                 &stream->clamping);
1411 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
1412         while (odm_pipe) {
1413                 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1414                                 odm_pipe->stream_res.opp,
1415                                 COLOR_SPACE_YCBCR601,
1416                                 stream->timing.display_color_depth,
1417                                 stream->signal);
1418
1419                 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1420                                 odm_pipe->stream_res.opp,
1421                                 &stream->bit_depth_params,
1422                                 &stream->clamping);
1423                 odm_pipe = odm_pipe->next_odm_pipe;
1424         }
1425 #endif
1426
1427         if (!stream->dpms_off)
1428                 core_link_enable_stream(context, pipe_ctx);
1429
1430         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1431
1432         pipe_ctx->stream->link->psr_enabled = false;
1433
1434         return DC_OK;
1435 }
1436
1437 /******************************************************************************/
1438
1439 static void power_down_encoders(struct dc *dc)
1440 {
1441         int i;
1442         enum connector_id connector_id;
1443         enum signal_type signal = SIGNAL_TYPE_NONE;
1444
1445         /* do not know BIOS back-front mapping, simply blank all. It will not
1446          * hurt for non-DP
1447          */
1448         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1449                 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1450                                         dc->res_pool->stream_enc[i]);
1451         }
1452
1453         for (i = 0; i < dc->link_count; i++) {
1454                 connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
1455                 if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
1456                         (connector_id == CONNECTOR_ID_EDP)) {
1457
1458                         if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1459                                 dp_receiver_power_ctrl(dc->links[i], false);
1460                         if (connector_id == CONNECTOR_ID_EDP)
1461                                 signal = SIGNAL_TYPE_EDP;
1462                 }
1463
1464                 dc->links[i]->link_enc->funcs->disable_output(
1465                                 dc->links[i]->link_enc, signal);
1466         }
1467 }
1468
1469 static void power_down_controllers(struct dc *dc)
1470 {
1471         int i;
1472
1473         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1474                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1475                                 dc->res_pool->timing_generators[i]);
1476         }
1477 }
1478
1479 static void power_down_clock_sources(struct dc *dc)
1480 {
1481         int i;
1482
1483         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1484                 dc->res_pool->dp_clock_source) == false)
1485                 dm_error("Failed to power down pll! (dp clk src)\n");
1486
1487         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1488                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1489                                 dc->res_pool->clock_sources[i]) == false)
1490                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1491         }
1492 }
1493
1494 static void power_down_all_hw_blocks(struct dc *dc)
1495 {
1496         power_down_encoders(dc);
1497
1498         power_down_controllers(dc);
1499
1500         power_down_clock_sources(dc);
1501
1502         if (dc->fbc_compressor)
1503                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1504 }
1505
1506 static void disable_vga_and_power_gate_all_controllers(
1507                 struct dc *dc)
1508 {
1509         int i;
1510         struct timing_generator *tg;
1511         struct dc_context *ctx = dc->ctx;
1512
1513         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1514                 tg = dc->res_pool->timing_generators[i];
1515
1516                 if (tg->funcs->disable_vga)
1517                         tg->funcs->disable_vga(tg);
1518         }
1519         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1520                 /* Enable CLOCK gating for each pipe BEFORE controller
1521                  * powergating. */
1522                 enable_display_pipe_clock_gating(ctx,
1523                                 true);
1524
1525                 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1526                 dc->hwss.disable_plane(dc,
1527                         &dc->current_state->res_ctx.pipe_ctx[i]);
1528         }
1529 }
1530
1531
1532 static struct dc_stream_state *get_edp_stream(struct dc_state *context)
1533 {
1534         int i;
1535
1536         for (i = 0; i < context->stream_count; i++) {
1537                 if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
1538                         return context->streams[i];
1539         }
1540         return NULL;
1541 }
1542
1543 static struct dc_link *get_edp_link(struct dc *dc)
1544 {
1545         int i;
1546
1547         // report any eDP links, even unconnected DDI's
1548         for (i = 0; i < dc->link_count; i++) {
1549                 if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
1550                         return dc->links[i];
1551         }
1552         return NULL;
1553 }
1554
1555 static struct dc_link *get_edp_link_with_sink(
1556                 struct dc *dc,
1557                 struct dc_state *context)
1558 {
1559         int i;
1560         struct dc_link *link = NULL;
1561
1562         /* check if there is an eDP panel not in use */
1563         for (i = 0; i < dc->link_count; i++) {
1564                 if (dc->links[i]->local_sink &&
1565                         dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1566                         link = dc->links[i];
1567                         break;
1568                 }
1569         }
1570
1571         return link;
1572 }
1573
1574 /**
1575  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1576  *  1. Power down all DC HW blocks
1577  *  2. Disable VGA engine on all controllers
1578  *  3. Enable power gating for controller
1579  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1580  */
1581 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1582 {
1583         int i;
1584         struct dc_link *edp_link_with_sink = get_edp_link_with_sink(dc, context);
1585         struct dc_link *edp_link = get_edp_link(dc);
1586         struct dc_stream_state *edp_stream = NULL;
1587         bool can_apply_edp_fast_boot = false;
1588         bool can_apply_seamless_boot = false;
1589         bool keep_edp_vdd_on = false;
1590
1591         if (dc->hwss.init_pipes)
1592                 dc->hwss.init_pipes(dc, context);
1593
1594         edp_stream = get_edp_stream(context);
1595
1596         // Check fastboot support, disable on DCE8 because of blank screens
1597         if (edp_link && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1598                     dc->ctx->dce_version != DCE_VERSION_8_1 &&
1599                     dc->ctx->dce_version != DCE_VERSION_8_3) {
1600
1601                 // enable fastboot if backend is enabled on eDP
1602                 if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) {
1603                         /* Set optimization flag on eDP stream*/
1604                         if (edp_stream) {
1605                                 edp_stream->apply_edp_fast_boot_optimization = true;
1606                                 can_apply_edp_fast_boot = true;
1607                         }
1608                 }
1609
1610                 // We are trying to enable eDP, don't power down VDD
1611                 if (edp_stream)
1612                         keep_edp_vdd_on = true;
1613         }
1614
1615         // Check seamless boot support
1616         for (i = 0; i < context->stream_count; i++) {
1617                 if (context->streams[i]->apply_seamless_boot_optimization) {
1618                         can_apply_seamless_boot = true;
1619                         break;
1620                 }
1621         }
1622
1623         /* eDP should not have stream in resume from S4 and so even with VBios post
1624          * it should get turned off
1625          */
1626         if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1627                 if (edp_link_with_sink && !keep_edp_vdd_on) {
1628                         /*turn off backlight before DP_blank and encoder powered down*/
1629                         dc->hwss.edp_backlight_control(edp_link_with_sink, false);
1630                 }
1631                 /*resume from S3, no vbios posting, no need to power down again*/
1632                 power_down_all_hw_blocks(dc);
1633                 disable_vga_and_power_gate_all_controllers(dc);
1634                 if (edp_link_with_sink && !keep_edp_vdd_on)
1635                         dc->hwss.edp_power_control(edp_link_with_sink, false);
1636         }
1637         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1638 }
1639
1640 static uint32_t compute_pstate_blackout_duration(
1641         struct bw_fixed blackout_duration,
1642         const struct dc_stream_state *stream)
1643 {
1644         uint32_t total_dest_line_time_ns;
1645         uint32_t pstate_blackout_duration_ns;
1646
1647         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1648
1649         total_dest_line_time_ns = 1000000UL *
1650                 (stream->timing.h_total * 10) /
1651                 stream->timing.pix_clk_100hz +
1652                 pstate_blackout_duration_ns;
1653
1654         return total_dest_line_time_ns;
1655 }
1656
1657 static void dce110_set_displaymarks(
1658         const struct dc *dc,
1659         struct dc_state *context)
1660 {
1661         uint8_t i, num_pipes;
1662         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1663
1664         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1665                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1666                 uint32_t total_dest_line_time_ns;
1667
1668                 if (pipe_ctx->stream == NULL)
1669                         continue;
1670
1671                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1672                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1673                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1674                         pipe_ctx->plane_res.mi,
1675                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1676                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1677                         context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1678                         context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1679                         total_dest_line_time_ns);
1680                 if (i == underlay_idx) {
1681                         num_pipes++;
1682                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1683                                 pipe_ctx->plane_res.mi,
1684                                 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1685                                 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1686                                 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1687                                 total_dest_line_time_ns);
1688                 }
1689                 num_pipes++;
1690         }
1691 }
1692
1693 void dce110_set_safe_displaymarks(
1694                 struct resource_context *res_ctx,
1695                 const struct resource_pool *pool)
1696 {
1697         int i;
1698         int underlay_idx = pool->underlay_pipe_index;
1699         struct dce_watermarks max_marks = {
1700                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1701         struct dce_watermarks nbp_marks = {
1702                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1703         struct dce_watermarks min_marks = { 0, 0, 0, 0};
1704
1705         for (i = 0; i < MAX_PIPES; i++) {
1706                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1707                         continue;
1708
1709                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1710                                 res_ctx->pipe_ctx[i].plane_res.mi,
1711                                 nbp_marks,
1712                                 max_marks,
1713                                 min_marks,
1714                                 max_marks,
1715                                 MAX_WATERMARK);
1716
1717                 if (i == underlay_idx)
1718                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1719                                 res_ctx->pipe_ctx[i].plane_res.mi,
1720                                 nbp_marks,
1721                                 max_marks,
1722                                 max_marks,
1723                                 MAX_WATERMARK);
1724
1725         }
1726 }
1727
1728 /*******************************************************************************
1729  * Public functions
1730  ******************************************************************************/
1731
1732 static void set_drr(struct pipe_ctx **pipe_ctx,
1733                 int num_pipes, int vmin, int vmax)
1734 {
1735         int i = 0;
1736         struct drr_params params = {0};
1737         // DRR should set trigger event to monitor surface update event
1738         unsigned int event_triggers = 0x80;
1739
1740         params.vertical_total_max = vmax;
1741         params.vertical_total_min = vmin;
1742
1743         /* TODO: If multiple pipes are to be supported, you need
1744          * some GSL stuff. Static screen triggers may be programmed differently
1745          * as well.
1746          */
1747         for (i = 0; i < num_pipes; i++) {
1748                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1749                         pipe_ctx[i]->stream_res.tg, &params);
1750
1751                 if (vmax != 0 && vmin != 0)
1752                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1753                                         pipe_ctx[i]->stream_res.tg,
1754                                         event_triggers);
1755         }
1756 }
1757
1758 static void get_position(struct pipe_ctx **pipe_ctx,
1759                 int num_pipes,
1760                 struct crtc_position *position)
1761 {
1762         int i = 0;
1763
1764         /* TODO: handle pipes > 1
1765          */
1766         for (i = 0; i < num_pipes; i++)
1767                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1768 }
1769
1770 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1771                 int num_pipes, const struct dc_static_screen_events *events)
1772 {
1773         unsigned int i;
1774         unsigned int value = 0;
1775
1776         if (events->overlay_update)
1777                 value |= 0x100;
1778         if (events->surface_update)
1779                 value |= 0x80;
1780         if (events->cursor_update)
1781                 value |= 0x2;
1782         if (events->force_trigger)
1783                 value |= 0x1;
1784
1785         if (num_pipes) {
1786                 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1787
1788                 if (dc->fbc_compressor)
1789                         value |= 0x84;
1790         }
1791
1792         for (i = 0; i < num_pipes; i++)
1793                 pipe_ctx[i]->stream_res.tg->funcs->
1794                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
1795 }
1796
1797 /*
1798  *  Check if FBC can be enabled
1799  */
1800 static bool should_enable_fbc(struct dc *dc,
1801                 struct dc_state *context,
1802                 uint32_t *pipe_idx)
1803 {
1804         uint32_t i;
1805         struct pipe_ctx *pipe_ctx = NULL;
1806         struct resource_context *res_ctx = &context->res_ctx;
1807         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1808
1809
1810         ASSERT(dc->fbc_compressor);
1811
1812         /* FBC memory should be allocated */
1813         if (!dc->ctx->fbc_gpu_addr)
1814                 return false;
1815
1816         /* Only supports single display */
1817         if (context->stream_count != 1)
1818                 return false;
1819
1820         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1821                 if (res_ctx->pipe_ctx[i].stream) {
1822
1823                         pipe_ctx = &res_ctx->pipe_ctx[i];
1824
1825                         if (!pipe_ctx)
1826                                 continue;
1827
1828                         /* fbc not applicable on underlay pipe */
1829                         if (pipe_ctx->pipe_idx != underlay_idx) {
1830                                 *pipe_idx = i;
1831                                 break;
1832                         }
1833                 }
1834         }
1835
1836         if (i == dc->res_pool->pipe_count)
1837                 return false;
1838
1839         if (!pipe_ctx->stream->link)
1840                 return false;
1841
1842         /* Only supports eDP */
1843         if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
1844                 return false;
1845
1846         /* PSR should not be enabled */
1847         if (pipe_ctx->stream->link->psr_enabled)
1848                 return false;
1849
1850         /* Nothing to compress */
1851         if (!pipe_ctx->plane_state)
1852                 return false;
1853
1854         /* Only for non-linear tiling */
1855         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1856                 return false;
1857
1858         return true;
1859 }
1860
1861 /*
1862  *  Enable FBC
1863  */
1864 static void enable_fbc(
1865                 struct dc *dc,
1866                 struct dc_state *context)
1867 {
1868         uint32_t pipe_idx = 0;
1869
1870         if (should_enable_fbc(dc, context, &pipe_idx)) {
1871                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1872                 struct compr_addr_and_pitch_params params = {0, 0, 0};
1873                 struct compressor *compr = dc->fbc_compressor;
1874                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1875
1876                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
1877                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
1878                 params.inst = pipe_ctx->stream_res.tg->inst;
1879                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1880
1881                 compr->funcs->surface_address_and_pitch(compr, &params);
1882                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1883
1884                 compr->funcs->enable_fbc(compr, &params);
1885         }
1886 }
1887
1888 static void dce110_reset_hw_ctx_wrap(
1889                 struct dc *dc,
1890                 struct dc_state *context)
1891 {
1892         int i;
1893
1894         /* Reset old context */
1895         /* look up the targets that have been removed since last commit */
1896         for (i = 0; i < MAX_PIPES; i++) {
1897                 struct pipe_ctx *pipe_ctx_old =
1898                         &dc->current_state->res_ctx.pipe_ctx[i];
1899                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1900
1901                 /* Note: We need to disable output if clock sources change,
1902                  * since bios does optimization and doesn't apply if changing
1903                  * PHY when not already disabled.
1904                  */
1905
1906                 /* Skip underlay pipe since it will be handled in commit surface*/
1907                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1908                         continue;
1909
1910                 if (!pipe_ctx->stream ||
1911                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1912                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1913
1914                         /* Disable if new stream is null. O/w, if stream is
1915                          * disabled already, no need to disable again.
1916                          */
1917                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
1918                                 core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
1919
1920                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1921                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1922                                 dm_error("DC: failed to blank crtc!\n");
1923                                 BREAK_TO_DEBUGGER();
1924                         }
1925                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1926                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1927                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
1928
1929                         if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
1930                                                                                 dc->res_pool,
1931                                                                                 old_clk))
1932                                 old_clk->funcs->cs_power_down(old_clk);
1933
1934                         dc->hwss.disable_plane(dc, pipe_ctx_old);
1935
1936                         pipe_ctx_old->stream = NULL;
1937                 }
1938         }
1939 }
1940
1941 static void dce110_setup_audio_dto(
1942                 struct dc *dc,
1943                 struct dc_state *context)
1944 {
1945         int i;
1946
1947         /* program audio wall clock. use HDMI as clock source if HDMI
1948          * audio active. Otherwise, use DP as clock source
1949          * first, loop to find any HDMI audio, if not, loop find DP audio
1950          */
1951         /* Setup audio rate clock source */
1952         /* Issue:
1953         * Audio lag happened on DP monitor when unplug a HDMI monitor
1954         *
1955         * Cause:
1956         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1957         * is set to either dto0 or dto1, audio should work fine.
1958         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1959         * set to dto0 will cause audio lag.
1960         *
1961         * Solution:
1962         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1963         * find first available pipe with audio, setup audio wall DTO per topology
1964         * instead of per pipe.
1965         */
1966         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1967                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1968
1969                 if (pipe_ctx->stream == NULL)
1970                         continue;
1971
1972                 if (pipe_ctx->top_pipe)
1973                         continue;
1974
1975                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
1976                         continue;
1977
1978                 if (pipe_ctx->stream_res.audio != NULL) {
1979                         struct audio_output audio_output;
1980
1981                         build_audio_output(context, pipe_ctx, &audio_output);
1982
1983                         pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
1984                                 pipe_ctx->stream_res.audio,
1985                                 pipe_ctx->stream->signal,
1986                                 &audio_output.crtc_info,
1987                                 &audio_output.pll_info);
1988                         break;
1989                 }
1990         }
1991
1992         /* no HDMI audio is found, try DP audio */
1993         if (i == dc->res_pool->pipe_count) {
1994                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1995                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1996
1997                         if (pipe_ctx->stream == NULL)
1998                                 continue;
1999
2000                         if (pipe_ctx->top_pipe)
2001                                 continue;
2002
2003                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2004                                 continue;
2005
2006                         if (pipe_ctx->stream_res.audio != NULL) {
2007                                 struct audio_output audio_output;
2008
2009                                 build_audio_output(context, pipe_ctx, &audio_output);
2010
2011                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2012                                         pipe_ctx->stream_res.audio,
2013                                         pipe_ctx->stream->signal,
2014                                         &audio_output.crtc_info,
2015                                         &audio_output.pll_info);
2016                                 break;
2017                         }
2018                 }
2019         }
2020 }
2021
2022 enum dc_status dce110_apply_ctx_to_hw(
2023                 struct dc *dc,
2024                 struct dc_state *context)
2025 {
2026         struct dc_bios *dcb = dc->ctx->dc_bios;
2027         enum dc_status status;
2028         int i;
2029
2030         /* Reset old context */
2031         /* look up the targets that have been removed since last commit */
2032         dc->hwss.reset_hw_ctx_wrap(dc, context);
2033
2034         /* Skip applying if no targets */
2035         if (context->stream_count <= 0)
2036                 return DC_OK;
2037
2038         /* Apply new context */
2039         dcb->funcs->set_scratch_critical_state(dcb, true);
2040
2041         /* below is for real asic only */
2042         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2043                 struct pipe_ctx *pipe_ctx_old =
2044                                         &dc->current_state->res_ctx.pipe_ctx[i];
2045                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2046
2047                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2048                         continue;
2049
2050                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2051                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2052                                 dce_crtc_switch_to_clk_src(dc->hwseq,
2053                                                 pipe_ctx->clock_source, i);
2054                         continue;
2055                 }
2056
2057                 dc->hwss.enable_display_power_gating(
2058                                 dc, i, dc->ctx->dc_bios,
2059                                 PIPE_GATING_CONTROL_DISABLE);
2060         }
2061
2062         if (dc->fbc_compressor)
2063                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2064
2065         dce110_setup_audio_dto(dc, context);
2066
2067         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2068                 struct pipe_ctx *pipe_ctx_old =
2069                                         &dc->current_state->res_ctx.pipe_ctx[i];
2070                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2071
2072                 if (pipe_ctx->stream == NULL)
2073                         continue;
2074
2075                 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2076                         pipe_ctx->stream->link->link_state_valid) {
2077                         continue;
2078                 }
2079
2080                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2081                         continue;
2082
2083                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2084                         continue;
2085
2086                 status = apply_single_controller_ctx_to_hw(
2087                                 pipe_ctx,
2088                                 context,
2089                                 dc);
2090
2091                 if (DC_OK != status)
2092                         return status;
2093         }
2094
2095         if (dc->fbc_compressor)
2096                 enable_fbc(dc, dc->current_state);
2097
2098         dcb->funcs->set_scratch_critical_state(dcb, false);
2099
2100         return DC_OK;
2101 }
2102
2103 /*******************************************************************************
2104  * Front End programming
2105  ******************************************************************************/
2106 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2107 {
2108         struct default_adjustment default_adjust = { 0 };
2109
2110         default_adjust.force_hw_default = false;
2111         default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2112         default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2113         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2114         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2115
2116         /* display color depth */
2117         default_adjust.color_depth =
2118                 pipe_ctx->stream->timing.display_color_depth;
2119
2120         /* Lb color depth */
2121         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2122
2123         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2124                                         pipe_ctx->plane_res.xfm, &default_adjust);
2125 }
2126
2127
2128 /*******************************************************************************
2129  * In order to turn on/off specific surface we will program
2130  * Blender + CRTC
2131  *
2132  * In case that we have two surfaces and they have a different visibility
2133  * we can't turn off the CRTC since it will turn off the entire display
2134  *
2135  * |----------------------------------------------- |
2136  * |bottom pipe|curr pipe  |              |         |
2137  * |Surface    |Surface    | Blender      |  CRCT   |
2138  * |visibility |visibility | Configuration|         |
2139  * |------------------------------------------------|
2140  * |   off     |    off    | CURRENT_PIPE | blank   |
2141  * |   off     |    on     | CURRENT_PIPE | unblank |
2142  * |   on      |    off    | OTHER_PIPE   | unblank |
2143  * |   on      |    on     | BLENDING     | unblank |
2144  * -------------------------------------------------|
2145  *
2146  ******************************************************************************/
2147 static void program_surface_visibility(const struct dc *dc,
2148                 struct pipe_ctx *pipe_ctx)
2149 {
2150         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2151         bool blank_target = false;
2152
2153         if (pipe_ctx->bottom_pipe) {
2154
2155                 /* For now we are supporting only two pipes */
2156                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2157
2158                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2159                         if (pipe_ctx->plane_state->visible)
2160                                 blender_mode = BLND_MODE_BLENDING;
2161                         else
2162                                 blender_mode = BLND_MODE_OTHER_PIPE;
2163
2164                 } else if (!pipe_ctx->plane_state->visible)
2165                         blank_target = true;
2166
2167         } else if (!pipe_ctx->plane_state->visible)
2168                 blank_target = true;
2169
2170         dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2171         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2172
2173 }
2174
2175 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2176 {
2177         int i = 0;
2178         struct xfm_grph_csc_adjustment adjust;
2179         memset(&adjust, 0, sizeof(adjust));
2180         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2181
2182
2183         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2184                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2185
2186                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2187                         adjust.temperature_matrix[i] =
2188                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2189         }
2190
2191         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2192 }
2193 static void update_plane_addr(const struct dc *dc,
2194                 struct pipe_ctx *pipe_ctx)
2195 {
2196         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2197
2198         if (plane_state == NULL)
2199                 return;
2200
2201         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2202                         pipe_ctx->plane_res.mi,
2203                         &plane_state->address,
2204                         plane_state->flip_immediate);
2205
2206         plane_state->status.requested_address = plane_state->address;
2207 }
2208
2209 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2210 {
2211         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2212
2213         if (plane_state == NULL)
2214                 return;
2215
2216         plane_state->status.is_flip_pending =
2217                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2218                                         pipe_ctx->plane_res.mi);
2219
2220         if (plane_state->status.is_flip_pending && !plane_state->visible)
2221                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2222
2223         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2224         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2225                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2226                 plane_state->status.is_right_eye =\
2227                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2228         }
2229 }
2230
2231 void dce110_power_down(struct dc *dc)
2232 {
2233         power_down_all_hw_blocks(dc);
2234         disable_vga_and_power_gate_all_controllers(dc);
2235 }
2236
2237 static bool wait_for_reset_trigger_to_occur(
2238         struct dc_context *dc_ctx,
2239         struct timing_generator *tg)
2240 {
2241         bool rc = false;
2242
2243         /* To avoid endless loop we wait at most
2244          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2245         const uint32_t frames_to_wait_on_triggered_reset = 10;
2246         uint32_t i;
2247
2248         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2249
2250                 if (!tg->funcs->is_counter_moving(tg)) {
2251                         DC_ERROR("TG counter is not moving!\n");
2252                         break;
2253                 }
2254
2255                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2256                         rc = true;
2257                         /* usually occurs at i=1 */
2258                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2259                                         i);
2260                         break;
2261                 }
2262
2263                 /* Wait for one frame. */
2264                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2265                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2266         }
2267
2268         if (false == rc)
2269                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2270
2271         return rc;
2272 }
2273
2274 /* Enable timing synchronization for a group of Timing Generators. */
2275 static void dce110_enable_timing_synchronization(
2276                 struct dc *dc,
2277                 int group_index,
2278                 int group_size,
2279                 struct pipe_ctx *grouped_pipes[])
2280 {
2281         struct dc_context *dc_ctx = dc->ctx;
2282         struct dcp_gsl_params gsl_params = { 0 };
2283         int i;
2284
2285         DC_SYNC_INFO("GSL: Setting-up...\n");
2286
2287         /* Designate a single TG in the group as a master.
2288          * Since HW doesn't care which one, we always assign
2289          * the 1st one in the group. */
2290         gsl_params.gsl_group = 0;
2291         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2292
2293         for (i = 0; i < group_size; i++)
2294                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2295                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2296
2297         /* Reset slave controllers on master VSync */
2298         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2299
2300         for (i = 1 /* skip the master */; i < group_size; i++)
2301                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2302                                 grouped_pipes[i]->stream_res.tg,
2303                                 gsl_params.gsl_group);
2304
2305         for (i = 1 /* skip the master */; i < group_size; i++) {
2306                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2307                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2308                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2309                                 grouped_pipes[i]->stream_res.tg);
2310         }
2311
2312         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2313          * is that the sync'ed displays will not drift out of sync over time*/
2314         DC_SYNC_INFO("GSL: Restoring register states.\n");
2315         for (i = 0; i < group_size; i++)
2316                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2317
2318         DC_SYNC_INFO("GSL: Set-up complete.\n");
2319 }
2320
2321 static void dce110_enable_per_frame_crtc_position_reset(
2322                 struct dc *dc,
2323                 int group_size,
2324                 struct pipe_ctx *grouped_pipes[])
2325 {
2326         struct dc_context *dc_ctx = dc->ctx;
2327         struct dcp_gsl_params gsl_params = { 0 };
2328         int i;
2329
2330         gsl_params.gsl_group = 0;
2331         gsl_params.gsl_master = 0;
2332
2333         for (i = 0; i < group_size; i++)
2334                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2335                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2336
2337         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2338
2339         for (i = 1; i < group_size; i++)
2340                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2341                                 grouped_pipes[i]->stream_res.tg,
2342                                 gsl_params.gsl_master,
2343                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
2344
2345         DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2346         for (i = 1; i < group_size; i++)
2347                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2348
2349         for (i = 0; i < group_size; i++)
2350                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2351
2352 }
2353
2354 static void init_pipes(struct dc *dc, struct dc_state *context)
2355 {
2356         // Do nothing
2357 }
2358
2359 static void init_hw(struct dc *dc)
2360 {
2361         int i;
2362         struct dc_bios *bp;
2363         struct transform *xfm;
2364         struct abm *abm;
2365         struct dmcu *dmcu;
2366
2367         bp = dc->ctx->dc_bios;
2368         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2369                 xfm = dc->res_pool->transforms[i];
2370                 xfm->funcs->transform_reset(xfm);
2371
2372                 dc->hwss.enable_display_power_gating(
2373                                 dc, i, bp,
2374                                 PIPE_GATING_CONTROL_INIT);
2375                 dc->hwss.enable_display_power_gating(
2376                                 dc, i, bp,
2377                                 PIPE_GATING_CONTROL_DISABLE);
2378                 dc->hwss.enable_display_pipe_clock_gating(
2379                         dc->ctx,
2380                         true);
2381         }
2382
2383         dce_clock_gating_power_up(dc->hwseq, false);
2384         /***************************************/
2385
2386         for (i = 0; i < dc->link_count; i++) {
2387                 /****************************************/
2388                 /* Power up AND update implementation according to the
2389                  * required signal (which may be different from the
2390                  * default signal on connector). */
2391                 struct dc_link *link = dc->links[i];
2392
2393                 link->link_enc->funcs->hw_init(link->link_enc);
2394         }
2395
2396         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2397                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2398
2399                 tg->funcs->disable_vga(tg);
2400
2401                 /* Blank controller using driver code instead of
2402                  * command table. */
2403                 tg->funcs->set_blank(tg, true);
2404                 hwss_wait_for_blank_complete(tg);
2405         }
2406
2407         for (i = 0; i < dc->res_pool->audio_count; i++) {
2408                 struct audio *audio = dc->res_pool->audios[i];
2409                 audio->funcs->hw_init(audio);
2410         }
2411
2412         abm = dc->res_pool->abm;
2413         if (abm != NULL) {
2414                 abm->funcs->init_backlight(abm);
2415                 abm->funcs->abm_init(abm);
2416         }
2417
2418         dmcu = dc->res_pool->dmcu;
2419         if (dmcu != NULL && abm != NULL)
2420                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2421
2422         if (dc->fbc_compressor)
2423                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2424
2425 }
2426
2427
2428 void dce110_prepare_bandwidth(
2429                 struct dc *dc,
2430                 struct dc_state *context)
2431 {
2432         struct clk_mgr *dccg = dc->clk_mgr;
2433
2434         dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2435
2436         dccg->funcs->update_clocks(
2437                         dccg,
2438                         context,
2439                         false);
2440 }
2441
2442 void dce110_optimize_bandwidth(
2443                 struct dc *dc,
2444                 struct dc_state *context)
2445 {
2446         struct clk_mgr *dccg = dc->clk_mgr;
2447
2448         dce110_set_displaymarks(dc, context);
2449
2450         dccg->funcs->update_clocks(
2451                         dccg,
2452                         context,
2453                         true);
2454 }
2455
2456 static void dce110_program_front_end_for_pipe(
2457                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2458 {
2459         struct mem_input *mi = pipe_ctx->plane_res.mi;
2460         struct pipe_ctx *old_pipe = NULL;
2461         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2462         struct xfm_grph_csc_adjustment adjust;
2463         struct out_csc_color_matrix tbl_entry;
2464         unsigned int i;
2465         DC_LOGGER_INIT();
2466         memset(&tbl_entry, 0, sizeof(tbl_entry));
2467
2468         if (dc->current_state)
2469                 old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2470
2471         memset(&adjust, 0, sizeof(adjust));
2472         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2473
2474         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2475
2476         set_default_colors(pipe_ctx);
2477         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2478                         == true) {
2479                 tbl_entry.color_space =
2480                         pipe_ctx->stream->output_color_space;
2481
2482                 for (i = 0; i < 12; i++)
2483                         tbl_entry.regval[i] =
2484                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2485
2486                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2487                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2488         }
2489
2490         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2491                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2492
2493                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2494                         adjust.temperature_matrix[i] =
2495                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2496         }
2497
2498         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2499
2500         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2501
2502         program_scaler(dc, pipe_ctx);
2503
2504         mi->funcs->mem_input_program_surface_config(
2505                         mi,
2506                         plane_state->format,
2507                         &plane_state->tiling_info,
2508                         &plane_state->plane_size,
2509                         plane_state->rotation,
2510                         NULL,
2511                         false);
2512         if (mi->funcs->set_blank)
2513                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2514
2515         if (dc->config.gpu_vm_support)
2516                 mi->funcs->mem_input_program_pte_vm(
2517                                 pipe_ctx->plane_res.mi,
2518                                 plane_state->format,
2519                                 &plane_state->tiling_info,
2520                                 plane_state->rotation);
2521
2522         /* Moved programming gamma from dc to hwss */
2523         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2524                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2525                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2526                 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2527
2528         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2529                 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2530
2531         DC_LOG_SURFACE(
2532                         "Pipe:%d %p: addr hi:0x%x, "
2533                         "addr low:0x%x, "
2534                         "src: %d, %d, %d,"
2535                         " %d; dst: %d, %d, %d, %d;"
2536                         "clip: %d, %d, %d, %d\n",
2537                         pipe_ctx->pipe_idx,
2538                         (void *) pipe_ctx->plane_state,
2539                         pipe_ctx->plane_state->address.grph.addr.high_part,
2540                         pipe_ctx->plane_state->address.grph.addr.low_part,
2541                         pipe_ctx->plane_state->src_rect.x,
2542                         pipe_ctx->plane_state->src_rect.y,
2543                         pipe_ctx->plane_state->src_rect.width,
2544                         pipe_ctx->plane_state->src_rect.height,
2545                         pipe_ctx->plane_state->dst_rect.x,
2546                         pipe_ctx->plane_state->dst_rect.y,
2547                         pipe_ctx->plane_state->dst_rect.width,
2548                         pipe_ctx->plane_state->dst_rect.height,
2549                         pipe_ctx->plane_state->clip_rect.x,
2550                         pipe_ctx->plane_state->clip_rect.y,
2551                         pipe_ctx->plane_state->clip_rect.width,
2552                         pipe_ctx->plane_state->clip_rect.height);
2553
2554         DC_LOG_SURFACE(
2555                         "Pipe %d: width, height, x, y\n"
2556                         "viewport:%d, %d, %d, %d\n"
2557                         "recout:  %d, %d, %d, %d\n",
2558                         pipe_ctx->pipe_idx,
2559                         pipe_ctx->plane_res.scl_data.viewport.width,
2560                         pipe_ctx->plane_res.scl_data.viewport.height,
2561                         pipe_ctx->plane_res.scl_data.viewport.x,
2562                         pipe_ctx->plane_res.scl_data.viewport.y,
2563                         pipe_ctx->plane_res.scl_data.recout.width,
2564                         pipe_ctx->plane_res.scl_data.recout.height,
2565                         pipe_ctx->plane_res.scl_data.recout.x,
2566                         pipe_ctx->plane_res.scl_data.recout.y);
2567 }
2568
2569 static void dce110_apply_ctx_for_surface(
2570                 struct dc *dc,
2571                 const struct dc_stream_state *stream,
2572                 int num_planes,
2573                 struct dc_state *context)
2574 {
2575         int i;
2576
2577         if (num_planes == 0)
2578                 return;
2579
2580         if (dc->fbc_compressor)
2581                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2582
2583         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2584                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2585                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2586
2587                 if (stream == pipe_ctx->stream) {
2588                         if (!pipe_ctx->top_pipe &&
2589                                 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2590                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
2591                 }
2592         }
2593
2594         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2595                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2596
2597                 if (pipe_ctx->stream != stream)
2598                         continue;
2599
2600                 /* Need to allocate mem before program front end for Fiji */
2601                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2602                                 pipe_ctx->plane_res.mi,
2603                                 pipe_ctx->stream->timing.h_total,
2604                                 pipe_ctx->stream->timing.v_total,
2605                                 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2606                                 context->stream_count);
2607
2608                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2609
2610                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2611
2612                 program_surface_visibility(dc, pipe_ctx);
2613
2614         }
2615
2616         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2617                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2618                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2619
2620                 if ((stream == pipe_ctx->stream) &&
2621                         (!pipe_ctx->top_pipe) &&
2622                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2623                         dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
2624         }
2625
2626         if (dc->fbc_compressor)
2627                 enable_fbc(dc, context);
2628 }
2629
2630 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2631 {
2632         int fe_idx = pipe_ctx->plane_res.mi ?
2633                 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2634
2635         /* Do not power down fe when stream is active on dce*/
2636         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2637                 return;
2638
2639         dc->hwss.enable_display_power_gating(
2640                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2641
2642         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2643                                 dc->res_pool->transforms[fe_idx]);
2644 }
2645
2646 static void dce110_wait_for_mpcc_disconnect(
2647                 struct dc *dc,
2648                 struct resource_pool *res_pool,
2649                 struct pipe_ctx *pipe_ctx)
2650 {
2651         /* do nothing*/
2652 }
2653
2654 static void program_output_csc(struct dc *dc,
2655                 struct pipe_ctx *pipe_ctx,
2656                 enum dc_color_space colorspace,
2657                 uint16_t *matrix,
2658                 int opp_id)
2659 {
2660         int i;
2661         struct out_csc_color_matrix tbl_entry;
2662
2663         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2664                 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2665
2666                 for (i = 0; i < 12; i++)
2667                         tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2668
2669                 tbl_entry.color_space = color_space;
2670
2671                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2672                                 pipe_ctx->plane_res.xfm, &tbl_entry);
2673         }
2674 }
2675
2676 void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2677 {
2678         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2679         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2680         struct mem_input *mi = pipe_ctx->plane_res.mi;
2681         struct dc_cursor_mi_param param = {
2682                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2683                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2684                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2685                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2686                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2687                 .rotation = pipe_ctx->plane_state->rotation,
2688                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2689         };
2690
2691         if (pipe_ctx->plane_state->address.type
2692                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2693                 pos_cpy.enable = false;
2694
2695         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2696                 pos_cpy.enable = false;
2697
2698         if (ipp->funcs->ipp_cursor_set_position)
2699                 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2700         if (mi->funcs->set_cursor_position)
2701                 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2702 }
2703
2704 void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2705 {
2706         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2707
2708         if (pipe_ctx->plane_res.ipp &&
2709             pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2710                 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2711                                 pipe_ctx->plane_res.ipp, attributes);
2712
2713         if (pipe_ctx->plane_res.mi &&
2714             pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2715                 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2716                                 pipe_ctx->plane_res.mi, attributes);
2717
2718         if (pipe_ctx->plane_res.xfm &&
2719             pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2720                 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2721                                 pipe_ctx->plane_res.xfm, attributes);
2722 }
2723
2724 static const struct hw_sequencer_funcs dce110_funcs = {
2725         .program_gamut_remap = program_gamut_remap,
2726         .program_output_csc = program_output_csc,
2727         .init_hw = init_hw,
2728         .init_pipes = init_pipes,
2729         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2730         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2731         .update_plane_addr = update_plane_addr,
2732         .update_pending_status = dce110_update_pending_status,
2733         .set_input_transfer_func = dce110_set_input_transfer_func,
2734         .set_output_transfer_func = dce110_set_output_transfer_func,
2735         .power_down = dce110_power_down,
2736         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2737         .enable_timing_synchronization = dce110_enable_timing_synchronization,
2738         .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
2739         .update_info_frame = dce110_update_info_frame,
2740         .enable_stream = dce110_enable_stream,
2741         .disable_stream = dce110_disable_stream,
2742         .unblank_stream = dce110_unblank_stream,
2743         .blank_stream = dce110_blank_stream,
2744         .enable_audio_stream = dce110_enable_audio_stream,
2745         .disable_audio_stream = dce110_disable_audio_stream,
2746         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2747         .enable_display_power_gating = dce110_enable_display_power_gating,
2748         .disable_plane = dce110_power_down_fe,
2749         .pipe_control_lock = dce_pipe_control_lock,
2750         .prepare_bandwidth = dce110_prepare_bandwidth,
2751         .optimize_bandwidth = dce110_optimize_bandwidth,
2752         .set_drr = set_drr,
2753         .get_position = get_position,
2754         .set_static_screen_control = set_static_screen_control,
2755         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2756         .enable_stream_timing = dce110_enable_stream_timing,
2757         .disable_stream_gating = NULL,
2758         .enable_stream_gating = NULL,
2759         .setup_stereo = NULL,
2760         .set_avmute = dce110_set_avmute,
2761         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
2762         .edp_backlight_control = dce110_edp_backlight_control,
2763         .edp_power_control = dce110_edp_power_control,
2764         .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
2765         .set_cursor_position = dce110_set_cursor_position,
2766         .set_cursor_attribute = dce110_set_cursor_attribute
2767 };
2768
2769 void dce110_hw_sequencer_construct(struct dc *dc)
2770 {
2771         dc->hwss = dce110_funcs;
2772 }
2773