2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
27 #include "dc_bios_types.h"
28 #include "core_types.h"
29 #include "core_status.h"
31 #include "dm_helpers.h"
32 #include "dce110_hw_sequencer.h"
33 #include "dce110_timing_generator.h"
34 #include "dce/dce_hwseq.h"
35 #include "gpio_service_interface.h"
37 #include "dce110_compressor.h"
39 #include "bios/bios_parser_helper.h"
40 #include "timing_generator.h"
41 #include "mem_input.h"
44 #include "transform.h"
45 #include "stream_encoder.h"
46 #include "link_encoder.h"
47 #include "link_hwss.h"
48 #include "clock_source.h"
51 #include "reg_helper.h"
53 /* include DCE11 register header files */
54 #include "dce/dce_11_0_d.h"
55 #include "dce/dce_11_0_sh_mask.h"
56 #include "custom_float.h"
58 #include "atomfirmware.h"
61 * All values are in milliseconds;
62 * For eDP, after power-up/power/down,
63 * 300/500 msec max. delay from LCDVCC to black video generation
65 #define PANEL_POWER_UP_TIMEOUT 300
66 #define PANEL_POWER_DOWN_TIMEOUT 500
67 #define HPD_CHECK_INTERVAL 10
72 #define DC_LOGGER_INIT()
78 #define FN(reg_name, field_name) \
79 hws->shifts->field_name, hws->masks->field_name
81 struct dce110_hw_seq_reg_offsets {
85 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
87 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
90 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
93 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
96 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
100 #define HW_REG_BLND(reg, id)\
101 (reg + reg_offsets[id].blnd)
103 #define HW_REG_CRTC(reg, id)\
104 (reg + reg_offsets[id].crtc)
106 #define MAX_WATERMARK 0xFFFF
107 #define SAFE_NBP_MARK 0x7FFF
109 /*******************************************************************************
110 * Private definitions
111 ******************************************************************************/
112 /***************************PIPE_CONTROL***********************************/
113 static void dce110_init_pte(struct dc_context *ctx)
117 uint32_t chunk_int = 0;
118 uint32_t chunk_mul = 0;
120 addr = mmUNP_DVMM_PTE_CONTROL;
121 value = dm_read_reg(ctx, addr);
127 DVMM_USE_SINGLE_PTE);
133 DVMM_PTE_BUFFER_MODE0);
139 DVMM_PTE_BUFFER_MODE1);
141 dm_write_reg(ctx, addr, value);
143 addr = mmDVMM_PTE_REQ;
144 value = dm_read_reg(ctx, addr);
146 chunk_int = get_reg_field_value(
149 HFLIP_PTEREQ_PER_CHUNK_INT);
151 chunk_mul = get_reg_field_value(
154 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
156 if (chunk_int != 0x4 || chunk_mul != 0x4) {
162 MAX_PTEREQ_TO_ISSUE);
168 HFLIP_PTEREQ_PER_CHUNK_INT);
174 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
176 dm_write_reg(ctx, addr, value);
179 /**************************************************************************/
181 static void enable_display_pipe_clock_gating(
182 struct dc_context *ctx,
188 static bool dce110_enable_display_power_gating(
190 uint8_t controller_id,
192 enum pipe_gating_control power_gating)
194 enum bp_result bp_result = BP_RESULT_OK;
195 enum bp_pipe_control_action cntl;
196 struct dc_context *ctx = dc->ctx;
197 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
199 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
202 if (power_gating == PIPE_GATING_CONTROL_INIT)
203 cntl = ASIC_PIPE_INIT;
204 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
205 cntl = ASIC_PIPE_ENABLE;
207 cntl = ASIC_PIPE_DISABLE;
209 if (controller_id == underlay_idx)
210 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
212 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
214 bp_result = dcb->funcs->enable_disp_power_gating(
215 dcb, controller_id + 1, cntl);
217 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
218 * by default when command table is called
220 * Bios parser accepts controller_id = 6 as indicative of
221 * underlay pipe in dce110. But we do not support more
224 if (controller_id < CONTROLLER_ID_MAX - 1)
226 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
230 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
231 dce110_init_pte(ctx);
233 if (bp_result == BP_RESULT_OK)
239 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
240 const struct dc_plane_state *plane_state)
242 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
244 switch (plane_state->format) {
245 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
246 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
247 prescale_params->scale = 0x2020;
249 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
250 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
251 prescale_params->scale = 0x2008;
253 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
254 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
255 prescale_params->scale = 0x2000;
264 dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
265 const struct dc_plane_state *plane_state)
267 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
268 const struct dc_transfer_func *tf = NULL;
269 struct ipp_prescale_params prescale_params = { 0 };
275 if (plane_state->in_transfer_func)
276 tf = plane_state->in_transfer_func;
278 build_prescale_params(&prescale_params, plane_state);
279 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
281 if (plane_state->gamma_correction &&
282 !plane_state->gamma_correction->is_identity &&
283 dce_use_lut(plane_state->format))
284 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
287 /* Default case if no input transfer function specified */
288 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
289 } else if (tf->type == TF_TYPE_PREDEFINED) {
291 case TRANSFER_FUNCTION_SRGB:
292 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
294 case TRANSFER_FUNCTION_BT709:
295 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
297 case TRANSFER_FUNCTION_LINEAR:
298 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
300 case TRANSFER_FUNCTION_PQ:
305 } else if (tf->type == TF_TYPE_BYPASS) {
306 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
308 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
315 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
316 struct curve_points *arr_points,
317 uint32_t hw_points_num)
319 struct custom_float_format fmt;
321 struct pwl_result_data *rgb = rgb_resulted;
325 fmt.exponenta_bits = 6;
326 fmt.mantissa_bits = 12;
329 if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
330 &arr_points[0].custom_float_x)) {
335 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
336 &arr_points[0].custom_float_offset)) {
341 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
342 &arr_points[0].custom_float_slope)) {
347 fmt.mantissa_bits = 10;
350 if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
351 &arr_points[1].custom_float_x)) {
356 if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
357 &arr_points[1].custom_float_y)) {
362 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
363 &arr_points[1].custom_float_slope)) {
368 fmt.mantissa_bits = 12;
371 while (i != hw_points_num) {
372 if (!convert_to_custom_float_format(rgb->red, &fmt,
378 if (!convert_to_custom_float_format(rgb->green, &fmt,
384 if (!convert_to_custom_float_format(rgb->blue, &fmt,
390 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
391 &rgb->delta_red_reg)) {
396 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
397 &rgb->delta_green_reg)) {
402 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
403 &rgb->delta_blue_reg)) {
415 #define MAX_LOW_POINT 25
416 #define NUMBER_REGIONS 16
417 #define NUMBER_SW_SEGMENTS 16
420 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
421 struct pwl_params *regamma_params)
423 struct curve_points *arr_points;
424 struct pwl_result_data *rgb_resulted;
425 struct pwl_result_data *rgb;
426 struct pwl_result_data *rgb_plus_1;
427 struct fixed31_32 y_r;
428 struct fixed31_32 y_g;
429 struct fixed31_32 y_b;
430 struct fixed31_32 y1_min;
431 struct fixed31_32 y3_max;
433 int32_t region_start, region_end;
434 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
436 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
439 arr_points = regamma_params->arr_points;
440 rgb_resulted = regamma_params->rgb_resulted;
443 memset(regamma_params, 0, sizeof(struct pwl_params));
445 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
447 * segments are from 2^-11 to 2^5
450 region_end = region_start + NUMBER_REGIONS;
452 for (i = 0; i < NUMBER_REGIONS; i++)
457 * segment is from 2^-10 to 2^1
458 * We include an extra segment for range [2^0, 2^1). This is to
459 * ensure that colors with normalized values of 1 don't miss the
483 for (k = 0; k < 16; k++) {
484 if (seg_distr[k] != -1)
485 hw_points += (1 << seg_distr[k]);
489 for (k = 0; k < (region_end - region_start); k++) {
490 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
491 start_index = (region_start + k + MAX_LOW_POINT) *
493 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
495 if (j == hw_points - 1)
497 rgb_resulted[j].red = output_tf->tf_pts.red[i];
498 rgb_resulted[j].green = output_tf->tf_pts.green[i];
499 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
505 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
506 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
507 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
508 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
510 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
511 dc_fixpt_from_int(region_start));
512 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
513 dc_fixpt_from_int(region_end));
515 y_r = rgb_resulted[0].red;
516 y_g = rgb_resulted[0].green;
517 y_b = rgb_resulted[0].blue;
519 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
521 arr_points[0].y = y1_min;
522 arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
525 y_r = rgb_resulted[hw_points - 1].red;
526 y_g = rgb_resulted[hw_points - 1].green;
527 y_b = rgb_resulted[hw_points - 1].blue;
529 /* see comment above, m_arrPoints[1].y should be the Y value for the
530 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
532 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
534 arr_points[1].y = y3_max;
536 arr_points[1].slope = dc_fixpt_zero;
538 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
539 /* for PQ, we want to have a straight line from last HW X point,
540 * and the slope to be such that we hit 1.0 at 10000 nits.
542 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
544 arr_points[1].slope = dc_fixpt_div(
545 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
546 dc_fixpt_sub(end_value, arr_points[1].x));
549 regamma_params->hw_points_num = hw_points;
552 for (i = 1; i < 16; i++) {
553 if (seg_distr[k] != -1) {
554 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
555 regamma_params->arr_curve_points[i].offset =
556 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
561 if (seg_distr[k] != -1)
562 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
565 rgb_plus_1 = rgb_resulted + 1;
569 while (i != hw_points + 1) {
570 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
571 rgb_plus_1->red = rgb->red;
572 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
573 rgb_plus_1->green = rgb->green;
574 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
575 rgb_plus_1->blue = rgb->blue;
577 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
578 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
579 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
586 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
592 dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
593 const struct dc_stream_state *stream)
595 struct transform *xfm = pipe_ctx->plane_res.xfm;
597 xfm->funcs->opp_power_on_regamma_lut(xfm, true);
598 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
600 if (stream->out_transfer_func &&
601 stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
602 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
603 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
604 } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
605 &xfm->regamma_params)) {
606 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
607 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
609 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
612 xfm->funcs->opp_power_on_regamma_lut(xfm, false);
617 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
622 ASSERT(pipe_ctx->stream);
624 if (pipe_ctx->stream_res.stream_enc == NULL)
625 return; /* this is not root pipe */
627 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
628 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
630 if (!is_hdmi_tmds && !is_dp)
634 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
635 pipe_ctx->stream_res.stream_enc,
636 &pipe_ctx->stream_res.encoder_info_frame);
638 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
639 pipe_ctx->stream_res.stream_enc,
640 &pipe_ctx->stream_res.encoder_info_frame);
643 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
645 enum dc_lane_count lane_count =
646 pipe_ctx->stream->link->cur_link_settings.lane_count;
648 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
649 struct dc_link *link = pipe_ctx->stream->link;
652 uint32_t active_total_with_borders;
653 uint32_t early_control = 0;
654 struct timing_generator *tg = pipe_ctx->stream_res.tg;
656 /* For MST, there are multiply stream go to only one link.
657 * connect DIG back_end to front_end while enable_stream and
658 * disconnect them during disable_stream
659 * BY this, it is logic clean to separate stream and link */
660 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
661 pipe_ctx->stream_res.stream_enc->id, true);
663 /* update AVI info frame (HDMI, DP)*/
664 /* TODO: FPGA may change to hwss.update_info_frame */
665 dce110_update_info_frame(pipe_ctx);
667 /* enable early control to avoid corruption on DP monitor*/
668 active_total_with_borders =
669 timing->h_addressable
670 + timing->h_border_left
671 + timing->h_border_right;
674 early_control = active_total_with_borders % lane_count;
676 if (early_control == 0)
677 early_control = lane_count;
679 tg->funcs->set_early_control(tg, early_control);
681 /* enable audio only within mode set */
682 if (pipe_ctx->stream_res.audio != NULL) {
683 if (dc_is_dp_signal(pipe_ctx->stream->signal))
684 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
692 /*todo: cloned in stream enc, fix*/
693 static bool is_panel_backlight_on(struct dce_hwseq *hws)
697 REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
702 static bool is_panel_powered_on(struct dce_hwseq *hws)
704 uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
707 REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
709 REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
711 return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
714 static enum bp_result link_transmitter_control(
715 struct dc_bios *bios,
716 struct bp_transmitter_control *cntl)
718 enum bp_result result;
720 result = bios->funcs->transmitter_control(bios, cntl);
729 void hwss_edp_wait_for_hpd_ready(
730 struct dc_link *link,
733 struct dc_context *ctx = link->ctx;
734 struct graphics_object_id connector = link->link_enc->connector;
736 bool edp_hpd_high = false;
737 uint32_t time_elapsed = 0;
738 uint32_t timeout = power_up ?
739 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
741 if (dal_graphics_object_id_get_connector_id(connector)
742 != CONNECTOR_ID_EDP) {
749 * From KV, we will not HPD low after turning off VCC -
750 * instead, we will check the SW timer in power_up().
755 * When we power on/off the eDP panel,
756 * we need to wait until SENSE bit is high/low.
760 /* TODO what to do with this? */
761 hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
768 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
770 /* wait until timeout or panel detected */
773 uint32_t detected = 0;
775 dal_gpio_get_value(hpd, &detected);
777 if (!(detected ^ power_up)) {
782 msleep(HPD_CHECK_INTERVAL);
784 time_elapsed += HPD_CHECK_INTERVAL;
785 } while (time_elapsed < timeout);
789 dal_gpio_destroy_irq(&hpd);
791 if (false == edp_hpd_high) {
793 "%s: wait timed out!\n", __func__);
797 void hwss_edp_power_control(
798 struct dc_link *link,
801 struct dc_context *ctx = link->ctx;
802 struct dce_hwseq *hwseq = ctx->dc->hwseq;
803 struct bp_transmitter_control cntl = { 0 };
804 enum bp_result bp_result;
807 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
808 != CONNECTOR_ID_EDP) {
813 if (power_up != is_panel_powered_on(hwseq)) {
814 /* Send VBIOS command to prompt eDP panel power */
816 unsigned long long current_ts = dm_get_timestamp(ctx);
817 unsigned long long duration_in_ms =
818 div64_u64(dm_get_elapse_time_in_ns(
821 link->link_trace.time_stamp.edp_poweroff), 1000000);
822 unsigned long long wait_time_ms = 0;
824 /* max 500ms from LCDVDD off to on */
825 unsigned long long edp_poweroff_time_ms = 500;
827 if (link->local_sink != NULL)
828 edp_poweroff_time_ms =
829 500 + link->local_sink->edid_caps.panel_patch.extra_t12_ms;
830 if (link->link_trace.time_stamp.edp_poweroff == 0)
831 wait_time_ms = edp_poweroff_time_ms;
832 else if (duration_in_ms < edp_poweroff_time_ms)
833 wait_time_ms = edp_poweroff_time_ms - duration_in_ms;
836 msleep(wait_time_ms);
837 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
838 __func__, wait_time_ms);
844 "%s: Panel Power action: %s\n",
845 __func__, (power_up ? "On":"Off"));
847 cntl.action = power_up ?
848 TRANSMITTER_CONTROL_POWER_ON :
849 TRANSMITTER_CONTROL_POWER_OFF;
850 cntl.transmitter = link->link_enc->transmitter;
851 cntl.connector_obj_id = link->link_enc->connector;
852 cntl.coherent = false;
853 cntl.lanes_number = LANE_COUNT_FOUR;
854 cntl.hpd_sel = link->link_enc->hpd_source;
855 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
858 /*save driver power off time stamp*/
859 link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
861 link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
863 if (bp_result != BP_RESULT_OK)
865 "%s: Panel Power bp_result: %d\n",
866 __func__, bp_result);
869 "%s: Skipping Panel Power action: %s\n",
870 __func__, (power_up ? "On":"Off"));
874 /*todo: cloned in stream enc, fix*/
877 * eDP only. Control the backlight of the eDP panel
879 void hwss_edp_backlight_control(
880 struct dc_link *link,
883 struct dc_context *ctx = link->ctx;
884 struct dce_hwseq *hws = ctx->dc->hwseq;
885 struct bp_transmitter_control cntl = { 0 };
887 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
888 != CONNECTOR_ID_EDP) {
893 if (enable && is_panel_backlight_on(hws)) {
895 "%s: panel already powered up. Do nothing.\n",
900 /* Send VBIOS command to control eDP panel backlight */
903 "%s: backlight action: %s\n",
904 __func__, (enable ? "On":"Off"));
906 cntl.action = enable ?
907 TRANSMITTER_CONTROL_BACKLIGHT_ON :
908 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
910 /*cntl.engine_id = ctx->engine;*/
911 cntl.transmitter = link->link_enc->transmitter;
912 cntl.connector_obj_id = link->link_enc->connector;
914 cntl.lanes_number = LANE_COUNT_FOUR;
915 cntl.hpd_sel = link->link_enc->hpd_source;
916 cntl.signal = SIGNAL_TYPE_EDP;
918 /* For eDP, the following delays might need to be considered
919 * after link training completed:
920 * idle period - min. accounts for required BS-Idle pattern,
921 * max. allows for source frame synchronization);
922 * 50 msec max. delay from valid video data from source
923 * to video on dislpay or backlight enable.
925 * Disable the delay for now.
926 * Enable it in the future if necessary.
928 /* dc_service_sleep_in_milliseconds(50); */
930 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
931 edp_receiver_ready_T7(link);
932 link_transmitter_control(ctx->dc_bios, &cntl);
934 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
935 edp_receiver_ready_T9(link);
938 // Static helper function which calls the correct function
939 // based on pp_smu version
940 static void set_pme_wa_enable_by_version(struct dc *dc)
942 struct pp_smu_funcs *pp_smu = NULL;
944 if (dc->res_pool->pp_smu)
945 pp_smu = dc->res_pool->pp_smu;
948 if (pp_smu->ctx.ver == PP_SMU_VER_RV && pp_smu->rv_funcs.set_pme_wa_enable)
949 pp_smu->rv_funcs.set_pme_wa_enable(&(pp_smu->ctx));
953 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
955 /* notify audio driver for audio modes of monitor */
956 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
957 struct pp_smu_funcs *pp_smu = NULL;
958 unsigned int i, num_audio = 1;
960 if (core_dc->res_pool->pp_smu)
961 pp_smu = core_dc->res_pool->pp_smu;
963 if (pipe_ctx->stream_res.audio) {
964 for (i = 0; i < MAX_PIPES; i++) {
965 /*current_state not updated yet*/
966 if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
970 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
972 if (num_audio >= 1 && pp_smu != NULL)
973 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
974 set_pme_wa_enable_by_version(core_dc);
976 /* TODO: audio should be per stream rather than per link */
977 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
978 pipe_ctx->stream_res.stream_enc, false);
982 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
984 struct dc *dc = pipe_ctx->stream->ctx->dc;
985 struct pp_smu_funcs *pp_smu = NULL;
987 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
988 pipe_ctx->stream_res.stream_enc, true);
989 if (pipe_ctx->stream_res.audio) {
990 if (dc->res_pool->pp_smu)
991 pp_smu = dc->res_pool->pp_smu;
993 if (option != KEEP_ACQUIRED_RESOURCE ||
994 !dc->debug.az_endpoint_mute_only)
995 /*only disalbe az_endpoint if power down or free*/
996 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
998 if (dc_is_dp_signal(pipe_ctx->stream->signal))
999 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1000 pipe_ctx->stream_res.stream_enc);
1002 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1003 pipe_ctx->stream_res.stream_enc);
1004 /*don't free audio if it is from retrain or internal disable stream*/
1005 if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
1006 /*we have to dynamic arbitrate the audio endpoints*/
1007 /*we free the resource, need reset is_audio_acquired*/
1008 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
1009 pipe_ctx->stream_res.audio = NULL;
1012 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1013 set_pme_wa_enable_by_version(dc);
1015 /* TODO: notify audio driver for if audio modes list changed
1016 * add audio mode list change flag */
1017 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1018 * stream->stream_engine_id);
1023 void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
1025 struct dc_stream_state *stream = pipe_ctx->stream;
1026 struct dc_link *link = stream->link;
1027 struct dc *dc = pipe_ctx->stream->ctx->dc;
1029 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
1030 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1031 pipe_ctx->stream_res.stream_enc);
1033 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1034 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1035 pipe_ctx->stream_res.stream_enc);
1037 dc->hwss.disable_audio_stream(pipe_ctx, option);
1039 link->link_enc->funcs->connect_dig_be_to_fe(
1041 pipe_ctx->stream_res.stream_enc->id,
1046 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1047 struct dc_link_settings *link_settings)
1049 struct encoder_unblank_param params = { { 0 } };
1050 struct dc_stream_state *stream = pipe_ctx->stream;
1051 struct dc_link *link = stream->link;
1053 /* only 3 items below are used by unblank */
1054 params.timing = pipe_ctx->stream->timing;
1055 params.link_settings.link_rate = link_settings->link_rate;
1057 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1058 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
1060 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1061 link->dc->hwss.edp_backlight_control(link, true);
1065 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1067 struct dc_stream_state *stream = pipe_ctx->stream;
1068 struct dc_link *link = stream->link;
1070 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1071 link->dc->hwss.edp_backlight_control(link, false);
1072 dc_link_set_abm_disable(link);
1075 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1076 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1080 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1082 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1083 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1086 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1089 case CONTROLLER_ID_D0:
1090 return DTO_SOURCE_ID0;
1091 case CONTROLLER_ID_D1:
1092 return DTO_SOURCE_ID1;
1093 case CONTROLLER_ID_D2:
1094 return DTO_SOURCE_ID2;
1095 case CONTROLLER_ID_D3:
1096 return DTO_SOURCE_ID3;
1097 case CONTROLLER_ID_D4:
1098 return DTO_SOURCE_ID4;
1099 case CONTROLLER_ID_D5:
1100 return DTO_SOURCE_ID5;
1102 return DTO_SOURCE_UNKNOWN;
1106 static void build_audio_output(
1107 struct dc_state *state,
1108 const struct pipe_ctx *pipe_ctx,
1109 struct audio_output *audio_output)
1111 const struct dc_stream_state *stream = pipe_ctx->stream;
1112 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1114 audio_output->signal = pipe_ctx->stream->signal;
1116 /* audio_crtc_info */
1118 audio_output->crtc_info.h_total =
1119 stream->timing.h_total;
1122 * Audio packets are sent during actual CRTC blank physical signal, we
1123 * need to specify actual active signal portion
1125 audio_output->crtc_info.h_active =
1126 stream->timing.h_addressable
1127 + stream->timing.h_border_left
1128 + stream->timing.h_border_right;
1130 audio_output->crtc_info.v_active =
1131 stream->timing.v_addressable
1132 + stream->timing.v_border_top
1133 + stream->timing.v_border_bottom;
1135 audio_output->crtc_info.pixel_repetition = 1;
1137 audio_output->crtc_info.interlaced =
1138 stream->timing.flags.INTERLACE;
1140 audio_output->crtc_info.refresh_rate =
1141 (stream->timing.pix_clk_100hz*10000)/
1142 (stream->timing.h_total*stream->timing.v_total);
1144 audio_output->crtc_info.color_depth =
1145 stream->timing.display_color_depth;
1147 audio_output->crtc_info.requested_pixel_clock =
1148 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
1150 audio_output->crtc_info.calculated_pixel_clock =
1151 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
1153 /*for HDMI, audio ACR is with deep color ratio factor*/
1154 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
1155 audio_output->crtc_info.requested_pixel_clock ==
1156 (stream->timing.pix_clk_100hz / 10)) {
1157 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1158 audio_output->crtc_info.requested_pixel_clock =
1159 audio_output->crtc_info.requested_pixel_clock/2;
1160 audio_output->crtc_info.calculated_pixel_clock =
1161 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/20;
1166 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1167 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1168 audio_output->pll_info.dp_dto_source_clock_in_khz =
1169 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1173 audio_output->pll_info.feed_back_divider =
1174 pipe_ctx->pll_settings.feedback_divider;
1176 audio_output->pll_info.dto_source =
1177 translate_to_dto_source(
1178 pipe_ctx->stream_res.tg->inst + 1);
1180 /* TODO hard code to enable for now. Need get from stream */
1181 audio_output->pll_info.ss_enabled = true;
1183 audio_output->pll_info.ss_percentage =
1184 pipe_ctx->pll_settings.ss_percentage;
1187 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1188 struct tg_color *color)
1190 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
1192 switch (pipe_ctx->plane_res.scl_data.format) {
1193 case PIXEL_FORMAT_ARGB8888:
1194 /* set boarder color to red */
1195 color->color_r_cr = color_value;
1198 case PIXEL_FORMAT_ARGB2101010:
1199 /* set boarder color to blue */
1200 color->color_b_cb = color_value;
1202 case PIXEL_FORMAT_420BPP8:
1203 /* set boarder color to green */
1204 color->color_g_y = color_value;
1206 case PIXEL_FORMAT_420BPP10:
1207 /* set boarder color to yellow */
1208 color->color_g_y = color_value;
1209 color->color_r_cr = color_value;
1211 case PIXEL_FORMAT_FP16:
1212 /* set boarder color to white */
1213 color->color_r_cr = color_value;
1214 color->color_b_cb = color_value;
1215 color->color_g_y = color_value;
1222 static void program_scaler(const struct dc *dc,
1223 const struct pipe_ctx *pipe_ctx)
1225 struct tg_color color = {0};
1227 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1229 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1233 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1234 get_surface_visual_confirm_color(pipe_ctx, &color);
1236 color_space_to_black_color(dc,
1237 pipe_ctx->stream->output_color_space,
1240 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1241 pipe_ctx->plane_res.xfm,
1242 pipe_ctx->plane_res.scl_data.lb_params.depth,
1243 &pipe_ctx->stream->bit_depth_params);
1245 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1247 * The way 420 is packed, 2 channels carry Y component, 1 channel
1248 * alternate between Cb and Cr, so both channels need the pixel
1251 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1252 color.color_r_cr = color.color_g_y;
1254 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1255 pipe_ctx->stream_res.tg,
1259 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1260 &pipe_ctx->plane_res.scl_data);
1263 static enum dc_status dce110_enable_stream_timing(
1264 struct pipe_ctx *pipe_ctx,
1265 struct dc_state *context,
1268 struct dc_stream_state *stream = pipe_ctx->stream;
1269 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1270 pipe_ctx[pipe_ctx->pipe_idx];
1271 struct tg_color black_color = {0};
1273 if (!pipe_ctx_old->stream) {
1275 /* program blank color */
1276 color_space_to_black_color(dc,
1277 stream->output_color_space, &black_color);
1278 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1279 pipe_ctx->stream_res.tg,
1283 * Must blank CRTC after disabling power gating and before any
1284 * programming, otherwise CRTC will be hung in bad state
1286 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1288 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1289 pipe_ctx->clock_source,
1290 &pipe_ctx->stream_res.pix_clk_params,
1291 &pipe_ctx->pll_settings)) {
1292 BREAK_TO_DEBUGGER();
1293 return DC_ERROR_UNEXPECTED;
1296 pipe_ctx->stream_res.tg->funcs->program_timing(
1297 pipe_ctx->stream_res.tg,
1302 if (!pipe_ctx_old->stream) {
1303 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1304 pipe_ctx->stream_res.tg)) {
1305 BREAK_TO_DEBUGGER();
1306 return DC_ERROR_UNEXPECTED;
1313 static enum dc_status apply_single_controller_ctx_to_hw(
1314 struct pipe_ctx *pipe_ctx,
1315 struct dc_state *context,
1318 struct dc_stream_state *stream = pipe_ctx->stream;
1319 struct drr_params params = {0};
1320 unsigned int event_triggers = 0;
1322 if (dc->hwss.disable_stream_gating) {
1323 dc->hwss.disable_stream_gating(dc, pipe_ctx);
1326 if (pipe_ctx->stream_res.audio != NULL) {
1327 struct audio_output audio_output;
1329 build_audio_output(context, pipe_ctx, &audio_output);
1331 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1332 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1333 pipe_ctx->stream_res.stream_enc,
1334 pipe_ctx->stream_res.audio->inst,
1335 &pipe_ctx->stream->audio_info);
1337 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1338 pipe_ctx->stream_res.stream_enc,
1339 pipe_ctx->stream_res.audio->inst,
1340 &pipe_ctx->stream->audio_info,
1341 &audio_output.crtc_info);
1343 pipe_ctx->stream_res.audio->funcs->az_configure(
1344 pipe_ctx->stream_res.audio,
1345 pipe_ctx->stream->signal,
1346 &audio_output.crtc_info,
1347 &pipe_ctx->stream->audio_info);
1351 /* Do not touch stream timing on seamless boot optimization. */
1352 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1353 dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
1355 if (dc->hwss.setup_vupdate_interrupt)
1356 dc->hwss.setup_vupdate_interrupt(pipe_ctx);
1358 params.vertical_total_min = stream->adjust.v_total_min;
1359 params.vertical_total_max = stream->adjust.v_total_max;
1360 if (pipe_ctx->stream_res.tg->funcs->set_drr)
1361 pipe_ctx->stream_res.tg->funcs->set_drr(
1362 pipe_ctx->stream_res.tg, ¶ms);
1364 // DRR should set trigger event to monitor surface update event
1365 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1366 event_triggers = 0x80;
1367 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1368 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1369 pipe_ctx->stream_res.tg, event_triggers);
1371 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1372 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1373 pipe_ctx->stream_res.stream_enc,
1374 pipe_ctx->stream_res.tg->inst);
1376 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1377 pipe_ctx->stream_res.opp,
1378 COLOR_SPACE_YCBCR601,
1379 stream->timing.display_color_depth,
1382 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1383 pipe_ctx->stream_res.opp,
1384 &stream->bit_depth_params,
1387 if (!stream->dpms_off)
1388 core_link_enable_stream(context, pipe_ctx);
1390 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1392 pipe_ctx->stream->link->psr_enabled = false;
1397 /******************************************************************************/
1399 static void power_down_encoders(struct dc *dc)
1402 enum connector_id connector_id;
1403 enum signal_type signal = SIGNAL_TYPE_NONE;
1405 /* do not know BIOS back-front mapping, simply blank all. It will not
1408 for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1409 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1410 dc->res_pool->stream_enc[i]);
1413 for (i = 0; i < dc->link_count; i++) {
1414 connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
1415 if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
1416 (connector_id == CONNECTOR_ID_EDP)) {
1418 if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1419 dp_receiver_power_ctrl(dc->links[i], false);
1420 if (connector_id == CONNECTOR_ID_EDP)
1421 signal = SIGNAL_TYPE_EDP;
1424 dc->links[i]->link_enc->funcs->disable_output(
1425 dc->links[i]->link_enc, signal);
1429 static void power_down_controllers(struct dc *dc)
1433 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1434 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1435 dc->res_pool->timing_generators[i]);
1439 static void power_down_clock_sources(struct dc *dc)
1443 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1444 dc->res_pool->dp_clock_source) == false)
1445 dm_error("Failed to power down pll! (dp clk src)\n");
1447 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1448 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1449 dc->res_pool->clock_sources[i]) == false)
1450 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1454 static void power_down_all_hw_blocks(struct dc *dc)
1456 power_down_encoders(dc);
1458 power_down_controllers(dc);
1460 power_down_clock_sources(dc);
1462 if (dc->fbc_compressor)
1463 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1466 static void disable_vga_and_power_gate_all_controllers(
1470 struct timing_generator *tg;
1471 struct dc_context *ctx = dc->ctx;
1473 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1474 tg = dc->res_pool->timing_generators[i];
1476 if (tg->funcs->disable_vga)
1477 tg->funcs->disable_vga(tg);
1479 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1480 /* Enable CLOCK gating for each pipe BEFORE controller
1482 enable_display_pipe_clock_gating(ctx,
1485 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1486 dc->hwss.disable_plane(dc,
1487 &dc->current_state->res_ctx.pipe_ctx[i]);
1491 static struct dc_link *get_link_for_edp(struct dc *dc)
1495 for (i = 0; i < dc->link_count; i++) {
1496 if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
1497 return dc->links[i];
1502 static struct dc_link *get_link_for_edp_to_turn_off(
1504 struct dc_state *context)
1507 struct dc_link *link = NULL;
1509 /* check if eDP panel is suppose to be set mode, if yes, no need to disable */
1510 for (i = 0; i < context->stream_count; i++) {
1511 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1512 if (context->streams[i]->dpms_off == true)
1513 return context->streams[i]->sink->link;
1519 /* check if there is an eDP panel not in use */
1520 for (i = 0; i < dc->link_count; i++) {
1521 if (dc->links[i]->local_sink &&
1522 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1523 link = dc->links[i];
1532 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1533 * 1. Power down all DC HW blocks
1534 * 2. Disable VGA engine on all controllers
1535 * 3. Enable power gating for controller
1536 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1538 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1541 struct dc_link *edp_link_to_turnoff = NULL;
1542 struct dc_link *edp_link = get_link_for_edp(dc);
1543 bool can_edp_fast_boot_optimize = false;
1544 bool apply_edp_fast_boot_optimization = false;
1545 bool can_apply_seamless_boot = false;
1547 for (i = 0; i < context->stream_count; i++) {
1548 if (context->streams[i]->apply_seamless_boot_optimization) {
1549 can_apply_seamless_boot = true;
1554 if (dc->hwss.init_pipes)
1555 dc->hwss.init_pipes(dc, context);
1558 /* this seems to cause blank screens on DCE8 */
1559 if ((dc->ctx->dce_version == DCE_VERSION_8_0) ||
1560 (dc->ctx->dce_version == DCE_VERSION_8_1) ||
1561 (dc->ctx->dce_version == DCE_VERSION_8_3))
1562 can_edp_fast_boot_optimize = false;
1564 can_edp_fast_boot_optimize =
1565 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc);
1568 if (can_edp_fast_boot_optimize)
1569 edp_link_to_turnoff = get_link_for_edp_to_turn_off(dc, context);
1571 /* if OS doesn't light up eDP and eDP link is available, we want to disable
1572 * If resume from S4/S5, should optimization.
1574 if (can_edp_fast_boot_optimize && !edp_link_to_turnoff) {
1575 /* Find eDP stream and set optimization flag */
1576 for (i = 0; i < context->stream_count; i++) {
1577 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1578 context->streams[i]->apply_edp_fast_boot_optimization = true;
1579 apply_edp_fast_boot_optimization = true;
1584 if (!apply_edp_fast_boot_optimization && !can_apply_seamless_boot) {
1585 if (edp_link_to_turnoff) {
1586 /*turn off backlight before DP_blank and encoder powered down*/
1587 dc->hwss.edp_backlight_control(edp_link_to_turnoff, false);
1589 /*resume from S3, no vbios posting, no need to power down again*/
1590 power_down_all_hw_blocks(dc);
1591 disable_vga_and_power_gate_all_controllers(dc);
1592 if (edp_link_to_turnoff)
1593 dc->hwss.edp_power_control(edp_link_to_turnoff, false);
1595 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1598 static uint32_t compute_pstate_blackout_duration(
1599 struct bw_fixed blackout_duration,
1600 const struct dc_stream_state *stream)
1602 uint32_t total_dest_line_time_ns;
1603 uint32_t pstate_blackout_duration_ns;
1605 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1607 total_dest_line_time_ns = 1000000UL *
1608 (stream->timing.h_total * 10) /
1609 stream->timing.pix_clk_100hz +
1610 pstate_blackout_duration_ns;
1612 return total_dest_line_time_ns;
1615 static void dce110_set_displaymarks(
1616 const struct dc *dc,
1617 struct dc_state *context)
1619 uint8_t i, num_pipes;
1620 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1622 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1623 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1624 uint32_t total_dest_line_time_ns;
1626 if (pipe_ctx->stream == NULL)
1629 total_dest_line_time_ns = compute_pstate_blackout_duration(
1630 dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1631 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1632 pipe_ctx->plane_res.mi,
1633 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1634 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1635 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1636 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1637 total_dest_line_time_ns);
1638 if (i == underlay_idx) {
1640 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1641 pipe_ctx->plane_res.mi,
1642 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1643 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1644 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1645 total_dest_line_time_ns);
1651 void dce110_set_safe_displaymarks(
1652 struct resource_context *res_ctx,
1653 const struct resource_pool *pool)
1656 int underlay_idx = pool->underlay_pipe_index;
1657 struct dce_watermarks max_marks = {
1658 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1659 struct dce_watermarks nbp_marks = {
1660 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1661 struct dce_watermarks min_marks = { 0, 0, 0, 0};
1663 for (i = 0; i < MAX_PIPES; i++) {
1664 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1667 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1668 res_ctx->pipe_ctx[i].plane_res.mi,
1675 if (i == underlay_idx)
1676 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1677 res_ctx->pipe_ctx[i].plane_res.mi,
1686 /*******************************************************************************
1688 ******************************************************************************/
1690 static void set_drr(struct pipe_ctx **pipe_ctx,
1691 int num_pipes, int vmin, int vmax)
1694 struct drr_params params = {0};
1695 // DRR should set trigger event to monitor surface update event
1696 unsigned int event_triggers = 0x80;
1698 params.vertical_total_max = vmax;
1699 params.vertical_total_min = vmin;
1701 /* TODO: If multiple pipes are to be supported, you need
1702 * some GSL stuff. Static screen triggers may be programmed differently
1705 for (i = 0; i < num_pipes; i++) {
1706 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1707 pipe_ctx[i]->stream_res.tg, ¶ms);
1709 if (vmax != 0 && vmin != 0)
1710 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1711 pipe_ctx[i]->stream_res.tg,
1716 static void get_position(struct pipe_ctx **pipe_ctx,
1718 struct crtc_position *position)
1722 /* TODO: handle pipes > 1
1724 for (i = 0; i < num_pipes; i++)
1725 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1728 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1729 int num_pipes, const struct dc_static_screen_events *events)
1732 unsigned int value = 0;
1734 if (events->overlay_update)
1736 if (events->surface_update)
1738 if (events->cursor_update)
1740 if (events->force_trigger)
1744 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1746 if (dc->fbc_compressor)
1750 for (i = 0; i < num_pipes; i++)
1751 pipe_ctx[i]->stream_res.tg->funcs->
1752 set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
1756 * Check if FBC can be enabled
1758 static bool should_enable_fbc(struct dc *dc,
1759 struct dc_state *context,
1763 struct pipe_ctx *pipe_ctx = NULL;
1764 struct resource_context *res_ctx = &context->res_ctx;
1765 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1768 ASSERT(dc->fbc_compressor);
1770 /* FBC memory should be allocated */
1771 if (!dc->ctx->fbc_gpu_addr)
1774 /* Only supports single display */
1775 if (context->stream_count != 1)
1778 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1779 if (res_ctx->pipe_ctx[i].stream) {
1781 pipe_ctx = &res_ctx->pipe_ctx[i];
1786 /* fbc not applicable on underlay pipe */
1787 if (pipe_ctx->pipe_idx != underlay_idx) {
1794 if (i == dc->res_pool->pipe_count)
1797 if (!pipe_ctx->stream->link)
1800 /* Only supports eDP */
1801 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
1804 /* PSR should not be enabled */
1805 if (pipe_ctx->stream->link->psr_enabled)
1808 /* Nothing to compress */
1809 if (!pipe_ctx->plane_state)
1812 /* Only for non-linear tiling */
1813 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1822 static void enable_fbc(
1824 struct dc_state *context)
1826 uint32_t pipe_idx = 0;
1828 if (should_enable_fbc(dc, context, &pipe_idx)) {
1829 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1830 struct compr_addr_and_pitch_params params = {0, 0, 0};
1831 struct compressor *compr = dc->fbc_compressor;
1832 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1834 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
1835 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
1836 params.inst = pipe_ctx->stream_res.tg->inst;
1837 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1839 compr->funcs->surface_address_and_pitch(compr, ¶ms);
1840 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1842 compr->funcs->enable_fbc(compr, ¶ms);
1846 static void dce110_reset_hw_ctx_wrap(
1848 struct dc_state *context)
1852 /* Reset old context */
1853 /* look up the targets that have been removed since last commit */
1854 for (i = 0; i < MAX_PIPES; i++) {
1855 struct pipe_ctx *pipe_ctx_old =
1856 &dc->current_state->res_ctx.pipe_ctx[i];
1857 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1859 /* Note: We need to disable output if clock sources change,
1860 * since bios does optimization and doesn't apply if changing
1861 * PHY when not already disabled.
1864 /* Skip underlay pipe since it will be handled in commit surface*/
1865 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1868 if (!pipe_ctx->stream ||
1869 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1870 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1872 /* Disable if new stream is null. O/w, if stream is
1873 * disabled already, no need to disable again.
1875 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
1876 core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
1878 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1879 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1880 dm_error("DC: failed to blank crtc!\n");
1881 BREAK_TO_DEBUGGER();
1883 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1884 pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1885 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
1887 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
1890 old_clk->funcs->cs_power_down(old_clk);
1892 dc->hwss.disable_plane(dc, pipe_ctx_old);
1894 pipe_ctx_old->stream = NULL;
1899 static void dce110_setup_audio_dto(
1901 struct dc_state *context)
1905 /* program audio wall clock. use HDMI as clock source if HDMI
1906 * audio active. Otherwise, use DP as clock source
1907 * first, loop to find any HDMI audio, if not, loop find DP audio
1909 /* Setup audio rate clock source */
1911 * Audio lag happened on DP monitor when unplug a HDMI monitor
1914 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1915 * is set to either dto0 or dto1, audio should work fine.
1916 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1917 * set to dto0 will cause audio lag.
1920 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1921 * find first available pipe with audio, setup audio wall DTO per topology
1922 * instead of per pipe.
1924 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1925 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1927 if (pipe_ctx->stream == NULL)
1930 if (pipe_ctx->top_pipe)
1933 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
1936 if (pipe_ctx->stream_res.audio != NULL) {
1937 struct audio_output audio_output;
1939 build_audio_output(context, pipe_ctx, &audio_output);
1941 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
1942 pipe_ctx->stream_res.audio,
1943 pipe_ctx->stream->signal,
1944 &audio_output.crtc_info,
1945 &audio_output.pll_info);
1950 /* no HDMI audio is found, try DP audio */
1951 if (i == dc->res_pool->pipe_count) {
1952 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1953 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1955 if (pipe_ctx->stream == NULL)
1958 if (pipe_ctx->top_pipe)
1961 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
1964 if (pipe_ctx->stream_res.audio != NULL) {
1965 struct audio_output audio_output;
1967 build_audio_output(context, pipe_ctx, &audio_output);
1969 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
1970 pipe_ctx->stream_res.audio,
1971 pipe_ctx->stream->signal,
1972 &audio_output.crtc_info,
1973 &audio_output.pll_info);
1980 enum dc_status dce110_apply_ctx_to_hw(
1982 struct dc_state *context)
1984 struct dc_bios *dcb = dc->ctx->dc_bios;
1985 enum dc_status status;
1988 /* Reset old context */
1989 /* look up the targets that have been removed since last commit */
1990 dc->hwss.reset_hw_ctx_wrap(dc, context);
1992 /* Skip applying if no targets */
1993 if (context->stream_count <= 0)
1996 /* Apply new context */
1997 dcb->funcs->set_scratch_critical_state(dcb, true);
1999 /* below is for real asic only */
2000 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2001 struct pipe_ctx *pipe_ctx_old =
2002 &dc->current_state->res_ctx.pipe_ctx[i];
2003 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2005 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2008 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2009 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2010 dce_crtc_switch_to_clk_src(dc->hwseq,
2011 pipe_ctx->clock_source, i);
2015 dc->hwss.enable_display_power_gating(
2016 dc, i, dc->ctx->dc_bios,
2017 PIPE_GATING_CONTROL_DISABLE);
2020 if (dc->fbc_compressor)
2021 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2023 dce110_setup_audio_dto(dc, context);
2025 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2026 struct pipe_ctx *pipe_ctx_old =
2027 &dc->current_state->res_ctx.pipe_ctx[i];
2028 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2030 if (pipe_ctx->stream == NULL)
2033 if (pipe_ctx->stream == pipe_ctx_old->stream)
2036 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2039 if (pipe_ctx->top_pipe)
2042 status = apply_single_controller_ctx_to_hw(
2047 if (DC_OK != status)
2051 if (dc->fbc_compressor)
2052 enable_fbc(dc, dc->current_state);
2054 dcb->funcs->set_scratch_critical_state(dcb, false);
2059 /*******************************************************************************
2060 * Front End programming
2061 ******************************************************************************/
2062 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2064 struct default_adjustment default_adjust = { 0 };
2066 default_adjust.force_hw_default = false;
2067 default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2068 default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2069 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2070 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2072 /* display color depth */
2073 default_adjust.color_depth =
2074 pipe_ctx->stream->timing.display_color_depth;
2076 /* Lb color depth */
2077 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2079 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2080 pipe_ctx->plane_res.xfm, &default_adjust);
2084 /*******************************************************************************
2085 * In order to turn on/off specific surface we will program
2088 * In case that we have two surfaces and they have a different visibility
2089 * we can't turn off the CRTC since it will turn off the entire display
2091 * |----------------------------------------------- |
2092 * |bottom pipe|curr pipe | | |
2093 * |Surface |Surface | Blender | CRCT |
2094 * |visibility |visibility | Configuration| |
2095 * |------------------------------------------------|
2096 * | off | off | CURRENT_PIPE | blank |
2097 * | off | on | CURRENT_PIPE | unblank |
2098 * | on | off | OTHER_PIPE | unblank |
2099 * | on | on | BLENDING | unblank |
2100 * -------------------------------------------------|
2102 ******************************************************************************/
2103 static void program_surface_visibility(const struct dc *dc,
2104 struct pipe_ctx *pipe_ctx)
2106 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2107 bool blank_target = false;
2109 if (pipe_ctx->bottom_pipe) {
2111 /* For now we are supporting only two pipes */
2112 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2114 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2115 if (pipe_ctx->plane_state->visible)
2116 blender_mode = BLND_MODE_BLENDING;
2118 blender_mode = BLND_MODE_OTHER_PIPE;
2120 } else if (!pipe_ctx->plane_state->visible)
2121 blank_target = true;
2123 } else if (!pipe_ctx->plane_state->visible)
2124 blank_target = true;
2126 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2127 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2131 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2134 struct xfm_grph_csc_adjustment adjust;
2135 memset(&adjust, 0, sizeof(adjust));
2136 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2139 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2140 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2142 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2143 adjust.temperature_matrix[i] =
2144 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2147 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2149 static void update_plane_addr(const struct dc *dc,
2150 struct pipe_ctx *pipe_ctx)
2152 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2154 if (plane_state == NULL)
2157 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2158 pipe_ctx->plane_res.mi,
2159 &plane_state->address,
2160 plane_state->flip_immediate);
2162 plane_state->status.requested_address = plane_state->address;
2165 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2167 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2169 if (plane_state == NULL)
2172 plane_state->status.is_flip_pending =
2173 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2174 pipe_ctx->plane_res.mi);
2176 if (plane_state->status.is_flip_pending && !plane_state->visible)
2177 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2179 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2180 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2181 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2182 plane_state->status.is_right_eye =\
2183 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2187 void dce110_power_down(struct dc *dc)
2189 power_down_all_hw_blocks(dc);
2190 disable_vga_and_power_gate_all_controllers(dc);
2193 static bool wait_for_reset_trigger_to_occur(
2194 struct dc_context *dc_ctx,
2195 struct timing_generator *tg)
2199 /* To avoid endless loop we wait at most
2200 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2201 const uint32_t frames_to_wait_on_triggered_reset = 10;
2204 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2206 if (!tg->funcs->is_counter_moving(tg)) {
2207 DC_ERROR("TG counter is not moving!\n");
2211 if (tg->funcs->did_triggered_reset_occur(tg)) {
2213 /* usually occurs at i=1 */
2214 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2219 /* Wait for one frame. */
2220 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2221 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2225 DC_ERROR("GSL: Timeout on reset trigger!\n");
2230 /* Enable timing synchronization for a group of Timing Generators. */
2231 static void dce110_enable_timing_synchronization(
2235 struct pipe_ctx *grouped_pipes[])
2237 struct dc_context *dc_ctx = dc->ctx;
2238 struct dcp_gsl_params gsl_params = { 0 };
2241 DC_SYNC_INFO("GSL: Setting-up...\n");
2243 /* Designate a single TG in the group as a master.
2244 * Since HW doesn't care which one, we always assign
2245 * the 1st one in the group. */
2246 gsl_params.gsl_group = 0;
2247 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2249 for (i = 0; i < group_size; i++)
2250 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2251 grouped_pipes[i]->stream_res.tg, &gsl_params);
2253 /* Reset slave controllers on master VSync */
2254 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2256 for (i = 1 /* skip the master */; i < group_size; i++)
2257 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2258 grouped_pipes[i]->stream_res.tg,
2259 gsl_params.gsl_group);
2261 for (i = 1 /* skip the master */; i < group_size; i++) {
2262 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2263 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2264 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2265 grouped_pipes[i]->stream_res.tg);
2268 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2269 * is that the sync'ed displays will not drift out of sync over time*/
2270 DC_SYNC_INFO("GSL: Restoring register states.\n");
2271 for (i = 0; i < group_size; i++)
2272 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2274 DC_SYNC_INFO("GSL: Set-up complete.\n");
2277 static void dce110_enable_per_frame_crtc_position_reset(
2280 struct pipe_ctx *grouped_pipes[])
2282 struct dc_context *dc_ctx = dc->ctx;
2283 struct dcp_gsl_params gsl_params = { 0 };
2286 gsl_params.gsl_group = 0;
2287 gsl_params.gsl_master = 0;
2289 for (i = 0; i < group_size; i++)
2290 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2291 grouped_pipes[i]->stream_res.tg, &gsl_params);
2293 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2295 for (i = 1; i < group_size; i++)
2296 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2297 grouped_pipes[i]->stream_res.tg,
2298 gsl_params.gsl_master,
2299 &grouped_pipes[i]->stream->triggered_crtc_reset);
2301 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2302 for (i = 1; i < group_size; i++)
2303 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2305 for (i = 0; i < group_size; i++)
2306 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2310 static void init_pipes(struct dc *dc, struct dc_state *context)
2315 static void init_hw(struct dc *dc)
2319 struct transform *xfm;
2322 bp = dc->ctx->dc_bios;
2323 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2324 xfm = dc->res_pool->transforms[i];
2325 xfm->funcs->transform_reset(xfm);
2327 dc->hwss.enable_display_power_gating(
2329 PIPE_GATING_CONTROL_INIT);
2330 dc->hwss.enable_display_power_gating(
2332 PIPE_GATING_CONTROL_DISABLE);
2333 dc->hwss.enable_display_pipe_clock_gating(
2338 dce_clock_gating_power_up(dc->hwseq, false);
2339 /***************************************/
2341 for (i = 0; i < dc->link_count; i++) {
2342 /****************************************/
2343 /* Power up AND update implementation according to the
2344 * required signal (which may be different from the
2345 * default signal on connector). */
2346 struct dc_link *link = dc->links[i];
2348 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
2349 dc->hwss.edp_power_control(link, true);
2351 link->link_enc->funcs->hw_init(link->link_enc);
2354 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2355 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2357 tg->funcs->disable_vga(tg);
2359 /* Blank controller using driver code instead of
2361 tg->funcs->set_blank(tg, true);
2362 hwss_wait_for_blank_complete(tg);
2365 for (i = 0; i < dc->res_pool->audio_count; i++) {
2366 struct audio *audio = dc->res_pool->audios[i];
2367 audio->funcs->hw_init(audio);
2370 abm = dc->res_pool->abm;
2372 abm->funcs->init_backlight(abm);
2373 abm->funcs->abm_init(abm);
2376 if (dc->fbc_compressor)
2377 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2382 void dce110_prepare_bandwidth(
2384 struct dc_state *context)
2386 struct clk_mgr *dccg = dc->res_pool->clk_mgr;
2388 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2390 dccg->funcs->update_clocks(
2396 void dce110_optimize_bandwidth(
2398 struct dc_state *context)
2400 struct clk_mgr *dccg = dc->res_pool->clk_mgr;
2402 dce110_set_displaymarks(dc, context);
2404 dccg->funcs->update_clocks(
2410 static void dce110_program_front_end_for_pipe(
2411 struct dc *dc, struct pipe_ctx *pipe_ctx)
2413 struct mem_input *mi = pipe_ctx->plane_res.mi;
2414 struct pipe_ctx *old_pipe = NULL;
2415 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2416 struct xfm_grph_csc_adjustment adjust;
2417 struct out_csc_color_matrix tbl_entry;
2420 memset(&tbl_entry, 0, sizeof(tbl_entry));
2422 if (dc->current_state)
2423 old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2425 memset(&adjust, 0, sizeof(adjust));
2426 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2428 dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2430 set_default_colors(pipe_ctx);
2431 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2433 tbl_entry.color_space =
2434 pipe_ctx->stream->output_color_space;
2436 for (i = 0; i < 12; i++)
2437 tbl_entry.regval[i] =
2438 pipe_ctx->stream->csc_color_matrix.matrix[i];
2440 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2441 (pipe_ctx->plane_res.xfm, &tbl_entry);
2444 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2445 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2447 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2448 adjust.temperature_matrix[i] =
2449 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2452 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2454 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2456 program_scaler(dc, pipe_ctx);
2458 mi->funcs->mem_input_program_surface_config(
2460 plane_state->format,
2461 &plane_state->tiling_info,
2462 &plane_state->plane_size,
2463 plane_state->rotation,
2466 if (mi->funcs->set_blank)
2467 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2469 if (dc->config.gpu_vm_support)
2470 mi->funcs->mem_input_program_pte_vm(
2471 pipe_ctx->plane_res.mi,
2472 plane_state->format,
2473 &plane_state->tiling_info,
2474 plane_state->rotation);
2476 /* Moved programming gamma from dc to hwss */
2477 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2478 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2479 pipe_ctx->plane_state->update_flags.bits.gamma_change)
2480 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2482 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2483 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2486 "Pipe:%d %p: addr hi:0x%x, "
2489 " %d; dst: %d, %d, %d, %d;"
2490 "clip: %d, %d, %d, %d\n",
2492 (void *) pipe_ctx->plane_state,
2493 pipe_ctx->plane_state->address.grph.addr.high_part,
2494 pipe_ctx->plane_state->address.grph.addr.low_part,
2495 pipe_ctx->plane_state->src_rect.x,
2496 pipe_ctx->plane_state->src_rect.y,
2497 pipe_ctx->plane_state->src_rect.width,
2498 pipe_ctx->plane_state->src_rect.height,
2499 pipe_ctx->plane_state->dst_rect.x,
2500 pipe_ctx->plane_state->dst_rect.y,
2501 pipe_ctx->plane_state->dst_rect.width,
2502 pipe_ctx->plane_state->dst_rect.height,
2503 pipe_ctx->plane_state->clip_rect.x,
2504 pipe_ctx->plane_state->clip_rect.y,
2505 pipe_ctx->plane_state->clip_rect.width,
2506 pipe_ctx->plane_state->clip_rect.height);
2509 "Pipe %d: width, height, x, y\n"
2510 "viewport:%d, %d, %d, %d\n"
2511 "recout: %d, %d, %d, %d\n",
2513 pipe_ctx->plane_res.scl_data.viewport.width,
2514 pipe_ctx->plane_res.scl_data.viewport.height,
2515 pipe_ctx->plane_res.scl_data.viewport.x,
2516 pipe_ctx->plane_res.scl_data.viewport.y,
2517 pipe_ctx->plane_res.scl_data.recout.width,
2518 pipe_ctx->plane_res.scl_data.recout.height,
2519 pipe_ctx->plane_res.scl_data.recout.x,
2520 pipe_ctx->plane_res.scl_data.recout.y);
2523 static void dce110_apply_ctx_for_surface(
2525 const struct dc_stream_state *stream,
2527 struct dc_state *context)
2531 if (num_planes == 0)
2534 if (dc->fbc_compressor)
2535 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2537 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2538 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2539 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2541 if (stream == pipe_ctx->stream) {
2542 if (!pipe_ctx->top_pipe &&
2543 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2544 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
2548 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2549 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2551 if (pipe_ctx->stream != stream)
2554 /* Need to allocate mem before program front end for Fiji */
2555 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2556 pipe_ctx->plane_res.mi,
2557 pipe_ctx->stream->timing.h_total,
2558 pipe_ctx->stream->timing.v_total,
2559 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2560 context->stream_count);
2562 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2564 dc->hwss.update_plane_addr(dc, pipe_ctx);
2566 program_surface_visibility(dc, pipe_ctx);
2570 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2571 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2572 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2574 if ((stream == pipe_ctx->stream) &&
2575 (!pipe_ctx->top_pipe) &&
2576 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2577 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
2580 if (dc->fbc_compressor)
2581 enable_fbc(dc, context);
2584 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2586 int fe_idx = pipe_ctx->plane_res.mi ?
2587 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2589 /* Do not power down fe when stream is active on dce*/
2590 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2593 dc->hwss.enable_display_power_gating(
2594 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2596 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2597 dc->res_pool->transforms[fe_idx]);
2600 static void dce110_wait_for_mpcc_disconnect(
2602 struct resource_pool *res_pool,
2603 struct pipe_ctx *pipe_ctx)
2608 static void program_output_csc(struct dc *dc,
2609 struct pipe_ctx *pipe_ctx,
2610 enum dc_color_space colorspace,
2615 struct out_csc_color_matrix tbl_entry;
2617 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2618 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2620 for (i = 0; i < 12; i++)
2621 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2623 tbl_entry.color_space = color_space;
2625 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2626 pipe_ctx->plane_res.xfm, &tbl_entry);
2630 void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2632 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2633 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2634 struct mem_input *mi = pipe_ctx->plane_res.mi;
2635 struct dc_cursor_mi_param param = {
2636 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2637 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2638 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2639 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2640 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2641 .rotation = pipe_ctx->plane_state->rotation,
2642 .mirror = pipe_ctx->plane_state->horizontal_mirror
2645 if (pipe_ctx->plane_state->address.type
2646 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2647 pos_cpy.enable = false;
2649 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2650 pos_cpy.enable = false;
2652 if (ipp->funcs->ipp_cursor_set_position)
2653 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m);
2654 if (mi->funcs->set_cursor_position)
2655 mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m);
2658 void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2660 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2662 if (pipe_ctx->plane_res.ipp &&
2663 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2664 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2665 pipe_ctx->plane_res.ipp, attributes);
2667 if (pipe_ctx->plane_res.mi &&
2668 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2669 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2670 pipe_ctx->plane_res.mi, attributes);
2672 if (pipe_ctx->plane_res.xfm &&
2673 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2674 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2675 pipe_ctx->plane_res.xfm, attributes);
2678 static const struct hw_sequencer_funcs dce110_funcs = {
2679 .program_gamut_remap = program_gamut_remap,
2680 .program_output_csc = program_output_csc,
2682 .init_pipes = init_pipes,
2683 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2684 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2685 .update_plane_addr = update_plane_addr,
2686 .update_pending_status = dce110_update_pending_status,
2687 .set_input_transfer_func = dce110_set_input_transfer_func,
2688 .set_output_transfer_func = dce110_set_output_transfer_func,
2689 .power_down = dce110_power_down,
2690 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2691 .enable_timing_synchronization = dce110_enable_timing_synchronization,
2692 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
2693 .update_info_frame = dce110_update_info_frame,
2694 .enable_stream = dce110_enable_stream,
2695 .disable_stream = dce110_disable_stream,
2696 .unblank_stream = dce110_unblank_stream,
2697 .blank_stream = dce110_blank_stream,
2698 .enable_audio_stream = dce110_enable_audio_stream,
2699 .disable_audio_stream = dce110_disable_audio_stream,
2700 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2701 .enable_display_power_gating = dce110_enable_display_power_gating,
2702 .disable_plane = dce110_power_down_fe,
2703 .pipe_control_lock = dce_pipe_control_lock,
2704 .prepare_bandwidth = dce110_prepare_bandwidth,
2705 .optimize_bandwidth = dce110_optimize_bandwidth,
2707 .get_position = get_position,
2708 .set_static_screen_control = set_static_screen_control,
2709 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2710 .enable_stream_timing = dce110_enable_stream_timing,
2711 .disable_stream_gating = NULL,
2712 .enable_stream_gating = NULL,
2713 .setup_stereo = NULL,
2714 .set_avmute = dce110_set_avmute,
2715 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
2716 .edp_backlight_control = hwss_edp_backlight_control,
2717 .edp_power_control = hwss_edp_power_control,
2718 .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2719 .set_cursor_position = dce110_set_cursor_position,
2720 .set_cursor_attribute = dce110_set_cursor_attribute
2723 void dce110_hw_sequencer_construct(struct dc *dc)
2725 dc->hwss = dce110_funcs;