drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "dm_services.h"
  26 #include "dc.h"
  27 #include "dc_bios_types.h"
  28 #include "core_types.h"
  29 #include "core_status.h"
  30 #include "resource.h"
  31 #include "dm_helpers.h"
  32 #include "dce110_hw_sequencer.h"
  33 #include "dce110_timing_generator.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "gpio_service_interface.h"
  36
  37 #if defined(CONFIG_DRM_AMD_DC_FBC)
  38 #include "dce110_compressor.h"
  39 #endif
  40
  41 #include "bios/bios_parser_helper.h"
  42 #include "timing_generator.h"
  43 #include "mem_input.h"
  44 #include "opp.h"
  45 #include "ipp.h"
  46 #include "transform.h"
  47 #include "stream_encoder.h"
  48 #include "link_encoder.h"
  49 #include "link_hwss.h"
  50 #include "clock_source.h"
  51 #include "abm.h"
  52 #include "audio.h"
  53 #include "reg_helper.h"
  54
  55 /* include DCE11 register header files */
  56 #include "dce/dce_11_0_d.h"
  57 #include "dce/dce_11_0_sh_mask.h"
  58 #include "custom_float.h"
  59
  60 #include "atomfirmware.h"
  61
  62 /*
  63  * All values are in milliseconds;
  64  * For eDP, after power-up/power/down,
  65  * 300/500 msec max. delay from LCDVCC to black video generation
  66  */
  67 #define PANEL_POWER_UP_TIMEOUT 300
  68 #define PANEL_POWER_DOWN_TIMEOUT 500
  69 #define HPD_CHECK_INTERVAL 10
  70
  71 #define CTX \
  72         hws->ctx
  73
  74 #define DC_LOGGER_INIT()
  75
  76 #define REG(reg)\
  77         hws->regs->reg
  78
  79 #undef FN
  80 #define FN(reg_name, field_name) \
  81         hws->shifts->field_name, hws->masks->field_name
  82
  83 struct dce110_hw_seq_reg_offsets {
  84         uint32_t crtc;
  85 };
  86
  87 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
  88 {
  89         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  90 },
  91 {
  92         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  93 },
  94 {
  95         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  96 },
  97 {
  98         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  99 }
 100 };
 101
 102 #define HW_REG_BLND(reg, id)\
 103         (reg + reg_offsets[id].blnd)
 104
 105 #define HW_REG_CRTC(reg, id)\
 106         (reg + reg_offsets[id].crtc)
 107
 108 #define MAX_WATERMARK 0xFFFF
 109 #define SAFE_NBP_MARK 0x7FFF
 110
 111 /*******************************************************************************
 112  * Private definitions
 113  ******************************************************************************/
 114 /***************************PIPE_CONTROL***********************************/
 115 static void dce110_init_pte(struct dc_context *ctx)
 116 {
 117         uint32_t addr;
 118         uint32_t value = 0;
 119         uint32_t chunk_int = 0;
 120         uint32_t chunk_mul = 0;
 121
 122         addr = mmUNP_DVMM_PTE_CONTROL;
 123         value = dm_read_reg(ctx, addr);
 124
 125         set_reg_field_value(
 126                 value,
 127                 0,
 128                 DVMM_PTE_CONTROL,
 129                 DVMM_USE_SINGLE_PTE);
 130
 131         set_reg_field_value(
 132                 value,
 133                 1,
 134                 DVMM_PTE_CONTROL,
 135                 DVMM_PTE_BUFFER_MODE0);
 136
 137         set_reg_field_value(
 138                 value,
 139                 1,
 140                 DVMM_PTE_CONTROL,
 141                 DVMM_PTE_BUFFER_MODE1);
 142
 143         dm_write_reg(ctx, addr, value);
 144
 145         addr = mmDVMM_PTE_REQ;
 146         value = dm_read_reg(ctx, addr);
 147
 148         chunk_int = get_reg_field_value(
 149                 value,
 150                 DVMM_PTE_REQ,
 151                 HFLIP_PTEREQ_PER_CHUNK_INT);
 152
 153         chunk_mul = get_reg_field_value(
 154                 value,
 155                 DVMM_PTE_REQ,
 156                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 157
 158         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 159
 160                 set_reg_field_value(
 161                         value,
 162                         255,
 163                         DVMM_PTE_REQ,
 164                         MAX_PTEREQ_TO_ISSUE);
 165
 166                 set_reg_field_value(
 167                         value,
 168                         4,
 169                         DVMM_PTE_REQ,
 170                         HFLIP_PTEREQ_PER_CHUNK_INT);
 171
 172                 set_reg_field_value(
 173                         value,
 174                         4,
 175                         DVMM_PTE_REQ,
 176                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 177
 178                 dm_write_reg(ctx, addr, value);
 179         }
 180 }
 181 /**************************************************************************/
 182
 183 static void enable_display_pipe_clock_gating(
 184         struct dc_context *ctx,
 185         bool clock_gating)
 186 {
 187         /*TODO*/
 188 }
 189
 190 static bool dce110_enable_display_power_gating(
 191         struct dc *dc,
 192         uint8_t controller_id,
 193         struct dc_bios *dcb,
 194         enum pipe_gating_control power_gating)
 195 {
 196         enum bp_result bp_result = BP_RESULT_OK;
 197         enum bp_pipe_control_action cntl;
 198         struct dc_context *ctx = dc->ctx;
 199         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 200
 201         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
 202                 return true;
 203
 204         if (power_gating == PIPE_GATING_CONTROL_INIT)
 205                 cntl = ASIC_PIPE_INIT;
 206         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 207                 cntl = ASIC_PIPE_ENABLE;
 208         else
 209                 cntl = ASIC_PIPE_DISABLE;
 210
 211         if (controller_id == underlay_idx)
 212                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 213
 214         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
 215
 216                 bp_result = dcb->funcs->enable_disp_power_gating(
 217                                                 dcb, controller_id + 1, cntl);
 218
 219                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 220                  * by default when command table is called
 221                  *
 222                  * Bios parser accepts controller_id = 6 as indicative of
 223                  * underlay pipe in dce110. But we do not support more
 224                  * than 3.
 225                  */
 226                 if (controller_id < CONTROLLER_ID_MAX - 1)
 227                         dm_write_reg(ctx,
 228                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 229                                 0);
 230         }
 231
 232         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 233                 dce110_init_pte(ctx);
 234
 235         if (bp_result == BP_RESULT_OK)
 236                 return true;
 237         else
 238                 return false;
 239 }
 240
 241 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 242                 const struct dc_plane_state *plane_state)
 243 {
 244         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 245
 246         switch (plane_state->format) {
 247         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 248         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 249                 prescale_params->scale = 0x2020;
 250                 break;
 251         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 252         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 253                 prescale_params->scale = 0x2008;
 254                 break;
 255         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 256         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 257                 prescale_params->scale = 0x2000;
 258                 break;
 259         default:
 260                 ASSERT(false);
 261                 break;
 262         }
 263 }
 264
 265 static bool
 266 dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
 267                                const struct dc_plane_state *plane_state)
 268 {
 269         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 270         const struct dc_transfer_func *tf = NULL;
 271         struct ipp_prescale_params prescale_params = { 0 };
 272         bool result = true;
 273
 274         if (ipp == NULL)
 275                 return false;
 276
 277         if (plane_state->in_transfer_func)
 278                 tf = plane_state->in_transfer_func;
 279
 280         build_prescale_params(&prescale_params, plane_state);
 281         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 282
 283         if (plane_state->gamma_correction &&
 284                         !plane_state->gamma_correction->is_identity &&
 285                         dce_use_lut(plane_state->format))
 286                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 287
 288         if (tf == NULL) {
 289                 /* Default case if no input transfer function specified */
 290                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 291         } else if (tf->type == TF_TYPE_PREDEFINED) {
 292                 switch (tf->tf) {
 293                 case TRANSFER_FUNCTION_SRGB:
 294                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 295                         break;
 296                 case TRANSFER_FUNCTION_BT709:
 297                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 298                         break;
 299                 case TRANSFER_FUNCTION_LINEAR:
 300                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 301                         break;
 302                 case TRANSFER_FUNCTION_PQ:
 303                 default:
 304                         result = false;
 305                         break;
 306                 }
 307         } else if (tf->type == TF_TYPE_BYPASS) {
 308                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 309         } else {
 310                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 311                 result = false;
 312         }
 313
 314         return result;
 315 }
 316
 317 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
 318                                     struct curve_points *arr_points,
 319                                     uint32_t hw_points_num)
 320 {
 321         struct custom_float_format fmt;
 322
 323         struct pwl_result_data *rgb = rgb_resulted;
 324
 325         uint32_t i = 0;
 326
 327         fmt.exponenta_bits = 6;
 328         fmt.mantissa_bits = 12;
 329         fmt.sign = true;
 330
 331         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 332                                             &arr_points[0].custom_float_x)) {
 333                 BREAK_TO_DEBUGGER();
 334                 return false;
 335         }
 336
 337         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 338                                             &arr_points[0].custom_float_offset)) {
 339                 BREAK_TO_DEBUGGER();
 340                 return false;
 341         }
 342
 343         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 344                                             &arr_points[0].custom_float_slope)) {
 345                 BREAK_TO_DEBUGGER();
 346                 return false;
 347         }
 348
 349         fmt.mantissa_bits = 10;
 350         fmt.sign = false;
 351
 352         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
 353                                             &arr_points[1].custom_float_x)) {
 354                 BREAK_TO_DEBUGGER();
 355                 return false;
 356         }
 357
 358         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
 359                                             &arr_points[1].custom_float_y)) {
 360                 BREAK_TO_DEBUGGER();
 361                 return false;
 362         }
 363
 364         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
 365                                             &arr_points[1].custom_float_slope)) {
 366                 BREAK_TO_DEBUGGER();
 367                 return false;
 368         }
 369
 370         fmt.mantissa_bits = 12;
 371         fmt.sign = true;
 372
 373         while (i != hw_points_num) {
 374                 if (!convert_to_custom_float_format(rgb->red, &fmt,
 375                                                     &rgb->red_reg)) {
 376                         BREAK_TO_DEBUGGER();
 377                         return false;
 378                 }
 379
 380                 if (!convert_to_custom_float_format(rgb->green, &fmt,
 381                                                     &rgb->green_reg)) {
 382                         BREAK_TO_DEBUGGER();
 383                         return false;
 384                 }
 385
 386                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
 387                                                     &rgb->blue_reg)) {
 388                         BREAK_TO_DEBUGGER();
 389                         return false;
 390                 }
 391
 392                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
 393                                                     &rgb->delta_red_reg)) {
 394                         BREAK_TO_DEBUGGER();
 395                         return false;
 396                 }
 397
 398                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
 399                                                     &rgb->delta_green_reg)) {
 400                         BREAK_TO_DEBUGGER();
 401                         return false;
 402                 }
 403
 404                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
 405                                                     &rgb->delta_blue_reg)) {
 406                         BREAK_TO_DEBUGGER();
 407                         return false;
 408                 }
 409
 410                 ++rgb;
 411                 ++i;
 412         }
 413
 414         return true;
 415 }
 416
 417 #define MAX_LOW_POINT      25
 418 #define NUMBER_REGIONS     16
 419 #define NUMBER_SW_SEGMENTS 16
 420
 421 static bool
 422 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
 423                                       struct pwl_params *regamma_params)
 424 {
 425         struct curve_points *arr_points;
 426         struct pwl_result_data *rgb_resulted;
 427         struct pwl_result_data *rgb;
 428         struct pwl_result_data *rgb_plus_1;
 429         struct fixed31_32 y_r;
 430         struct fixed31_32 y_g;
 431         struct fixed31_32 y_b;
 432         struct fixed31_32 y1_min;
 433         struct fixed31_32 y3_max;
 434
 435         int32_t region_start, region_end;
 436         uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
 437
 438         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 439                 return false;
 440
 441         arr_points = regamma_params->arr_points;
 442         rgb_resulted = regamma_params->rgb_resulted;
 443         hw_points = 0;
 444
 445         memset(regamma_params, 0, sizeof(struct pwl_params));
 446
 447         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 448                 /* 16 segments
 449                  * segments are from 2^-11 to 2^5
 450                  */
 451                 region_start = -11;
 452                 region_end = region_start + NUMBER_REGIONS;
 453
 454                 for (i = 0; i < NUMBER_REGIONS; i++)
 455                         seg_distr[i] = 4;
 456
 457         } else {
 458                 /* 10 segments
 459                  * segment is from 2^-10 to 2^1
 460                  * We include an extra segment for range [2^0, 2^1). This is to
 461                  * ensure that colors with normalized values of 1 don't miss the
 462                  * LUT.
 463                  */
 464                 region_start = -10;
 465                 region_end = 1;
 466
 467                 seg_distr[0] = 4;
 468                 seg_distr[1] = 4;
 469                 seg_distr[2] = 4;
 470                 seg_distr[3] = 4;
 471                 seg_distr[4] = 4;
 472                 seg_distr[5] = 4;
 473                 seg_distr[6] = 4;
 474                 seg_distr[7] = 4;
 475                 seg_distr[8] = 4;
 476                 seg_distr[9] = 4;
 477                 seg_distr[10] = 0;
 478                 seg_distr[11] = -1;
 479                 seg_distr[12] = -1;
 480                 seg_distr[13] = -1;
 481                 seg_distr[14] = -1;
 482                 seg_distr[15] = -1;
 483         }
 484
 485         for (k = 0; k < 16; k++) {
 486                 if (seg_distr[k] != -1)
 487                         hw_points += (1 << seg_distr[k]);
 488         }
 489
 490         j = 0;
 491         for (k = 0; k < (region_end - region_start); k++) {
 492                 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
 493                 start_index = (region_start + k + MAX_LOW_POINT) *
 494                                 NUMBER_SW_SEGMENTS;
 495                 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 496                                 i += increment) {
 497                         if (j == hw_points - 1)
 498                                 break;
 499                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 500                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 501                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 502                         j++;
 503                 }
 504         }
 505
 506         /* last point */
 507         start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
 508         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
 509         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
 510         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 511
 512         arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 513                                              dc_fixpt_from_int(region_start));
 514         arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 515                                              dc_fixpt_from_int(region_end));
 516
 517         y_r = rgb_resulted[0].red;
 518         y_g = rgb_resulted[0].green;
 519         y_b = rgb_resulted[0].blue;
 520
 521         y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 522
 523         arr_points[0].y = y1_min;
 524         arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
 525                                                  arr_points[0].x);
 526
 527         y_r = rgb_resulted[hw_points - 1].red;
 528         y_g = rgb_resulted[hw_points - 1].green;
 529         y_b = rgb_resulted[hw_points - 1].blue;
 530
 531         /* see comment above, m_arrPoints[1].y should be the Y value for the
 532          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 533          */
 534         y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 535
 536         arr_points[1].y = y3_max;
 537
 538         arr_points[1].slope = dc_fixpt_zero;
 539
 540         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 541                 /* for PQ, we want to have a straight line from last HW X point,
 542                  * and the slope to be such that we hit 1.0 at 10000 nits.
 543                  */
 544                 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
 545
 546                 arr_points[1].slope = dc_fixpt_div(
 547                                 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
 548                                 dc_fixpt_sub(end_value, arr_points[1].x));
 549         }
 550
 551         regamma_params->hw_points_num = hw_points;
 552
 553         i = 1;
 554         for (k = 0; k < 16 && i < 16; k++) {
 555                 if (seg_distr[k] != -1) {
 556                         regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 557                         regamma_params->arr_curve_points[i].offset =
 558                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 559                 }
 560                 i++;
 561         }
 562
 563         if (seg_distr[k] != -1)
 564                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 565
 566         rgb = rgb_resulted;
 567         rgb_plus_1 = rgb_resulted + 1;
 568
 569         i = 1;
 570
 571         while (i != hw_points + 1) {
 572                 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
 573                         rgb_plus_1->red = rgb->red;
 574                 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
 575                         rgb_plus_1->green = rgb->green;
 576                 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
 577                         rgb_plus_1->blue = rgb->blue;
 578
 579                 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
 580                 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
 581                 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
 582
 583                 ++rgb_plus_1;
 584                 ++rgb;
 585                 ++i;
 586         }
 587
 588         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 589
 590         return true;
 591 }
 592
 593 static bool
 594 dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
 595                                 const struct dc_stream_state *stream)
 596 {
 597         struct transform *xfm = pipe_ctx->plane_res.xfm;
 598
 599         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 600         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 601
 602         if (stream->out_transfer_func &&
 603             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 604             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 605                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 606         } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
 607                                                          &xfm->regamma_params)) {
 608                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 609                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 610         } else {
 611                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 612         }
 613
 614         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 615
 616         return true;
 617 }
 618
 619 static enum dc_status bios_parser_crtc_source_select(
 620                 struct pipe_ctx *pipe_ctx)
 621 {
 622         struct dc_bios *dcb;
 623         /* call VBIOS table to set CRTC source for the HW
 624          * encoder block
 625          * note: video bios clears all FMT setting here. */
 626         struct bp_crtc_source_select crtc_source_select = {0};
 627         const struct dc_sink *sink = pipe_ctx->stream->sink;
 628
 629         crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
 630         crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1;
 631         /*TODO: Need to un-hardcode color depth, dp_audio and account for
 632          * the case where signal and sink signal is different (translator
 633          * encoder)*/
 634         crtc_source_select.signal = pipe_ctx->stream->signal;
 635         crtc_source_select.enable_dp_audio = false;
 636         crtc_source_select.sink_signal = pipe_ctx->stream->signal;
 637
 638         switch (pipe_ctx->stream->timing.display_color_depth) {
 639         case COLOR_DEPTH_666:
 640                 crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR;
 641                 break;
 642         case COLOR_DEPTH_888:
 643                 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
 644                 break;
 645         case COLOR_DEPTH_101010:
 646                 crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR;
 647                 break;
 648         case COLOR_DEPTH_121212:
 649                 crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR;
 650                 break;
 651         default:
 652                 BREAK_TO_DEBUGGER();
 653                 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
 654                 break;
 655         }
 656
 657         dcb = sink->ctx->dc_bios;
 658
 659         if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
 660                 dcb,
 661                 &crtc_source_select)) {
 662                 return DC_ERROR_UNEXPECTED;
 663         }
 664
 665         return DC_OK;
 666 }
 667
 668 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 669 {
 670         ASSERT(pipe_ctx->stream);
 671
 672         if (pipe_ctx->stream_res.stream_enc == NULL)
 673                 return;  /* this is not root pipe */
 674
 675         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
 676                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 677                         pipe_ctx->stream_res.stream_enc,
 678                         &pipe_ctx->stream_res.encoder_info_frame);
 679         else if (dc_is_dp_signal(pipe_ctx->stream->signal))
 680                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 681                         pipe_ctx->stream_res.stream_enc,
 682                         &pipe_ctx->stream_res.encoder_info_frame);
 683 }
 684
 685 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 686 {
 687         enum dc_lane_count lane_count =
 688                 pipe_ctx->stream->sink->link->cur_link_settings.lane_count;
 689
 690         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 691         struct dc_link *link = pipe_ctx->stream->sink->link;
 692
 693
 694         uint32_t active_total_with_borders;
 695         uint32_t early_control = 0;
 696         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 697
 698         /* For MST, there are multiply stream go to only one link.
 699          * connect DIG back_end to front_end while enable_stream and
 700          * disconnect them during disable_stream
 701          * BY this, it is logic clean to separate stream and link */
 702         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
 703                                                     pipe_ctx->stream_res.stream_enc->id, true);
 704
 705         /* update AVI info frame (HDMI, DP)*/
 706         /* TODO: FPGA may change to hwss.update_info_frame */
 707         dce110_update_info_frame(pipe_ctx);
 708
 709         /* enable early control to avoid corruption on DP monitor*/
 710         active_total_with_borders =
 711                         timing->h_addressable
 712                                 + timing->h_border_left
 713                                 + timing->h_border_right;
 714
 715         if (lane_count != 0)
 716                 early_control = active_total_with_borders % lane_count;
 717
 718         if (early_control == 0)
 719                 early_control = lane_count;
 720
 721         tg->funcs->set_early_control(tg, early_control);
 722
 723         /* enable audio only within mode set */
 724         if (pipe_ctx->stream_res.audio != NULL) {
 725                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
 726                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
 727         }
 728
 729
 730
 731
 732 }
 733
 734 /*todo: cloned in stream enc, fix*/
 735 static bool is_panel_backlight_on(struct dce_hwseq *hws)
 736 {
 737         uint32_t value;
 738
 739         REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
 740
 741         return value;
 742 }
 743
 744 static bool is_panel_powered_on(struct dce_hwseq *hws)
 745 {
 746         uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
 747
 748
 749         REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
 750
 751         REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
 752
 753         return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
 754 }
 755
 756 static enum bp_result link_transmitter_control(
 757                 struct dc_bios *bios,
 758         struct bp_transmitter_control *cntl)
 759 {
 760         enum bp_result result;
 761
 762         result = bios->funcs->transmitter_control(bios, cntl);
 763
 764         return result;
 765 }
 766
 767 /*
 768  * @brief
 769  * eDP only.
 770  */
 771 void hwss_edp_wait_for_hpd_ready(
 772                 struct dc_link *link,
 773                 bool power_up)
 774 {
 775         struct dc_context *ctx = link->ctx;
 776         struct graphics_object_id connector = link->link_enc->connector;
 777         struct gpio *hpd;
 778         bool edp_hpd_high = false;
 779         uint32_t time_elapsed = 0;
 780         uint32_t timeout = power_up ?
 781                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 782
 783         if (dal_graphics_object_id_get_connector_id(connector)
 784                         != CONNECTOR_ID_EDP) {
 785                 BREAK_TO_DEBUGGER();
 786                 return;
 787         }
 788
 789         if (!power_up)
 790                 /*
 791                  * From KV, we will not HPD low after turning off VCC -
 792                  * instead, we will check the SW timer in power_up().
 793                  */
 794                 return;
 795
 796         /*
 797          * When we power on/off the eDP panel,
 798          * we need to wait until SENSE bit is high/low.
 799          */
 800
 801         /* obtain HPD */
 802         /* TODO what to do with this? */
 803         hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 804
 805         if (!hpd) {
 806                 BREAK_TO_DEBUGGER();
 807                 return;
 808         }
 809
 810         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 811
 812         /* wait until timeout or panel detected */
 813
 814         do {
 815                 uint32_t detected = 0;
 816
 817                 dal_gpio_get_value(hpd, &detected);
 818
 819                 if (!(detected ^ power_up)) {
 820                         edp_hpd_high = true;
 821                         break;
 822                 }
 823
 824                 msleep(HPD_CHECK_INTERVAL);
 825
 826                 time_elapsed += HPD_CHECK_INTERVAL;
 827         } while (time_elapsed < timeout);
 828
 829         dal_gpio_close(hpd);
 830
 831         dal_gpio_destroy_irq(&hpd);
 832
 833         if (false == edp_hpd_high) {
 834                 DC_LOG_ERROR(
 835                                 "%s: wait timed out!\n", __func__);
 836         }
 837 }
 838
 839 void hwss_edp_power_control(
 840                 struct dc_link *link,
 841                 bool power_up)
 842 {
 843         struct dc_context *ctx = link->ctx;
 844         struct dce_hwseq *hwseq = ctx->dc->hwseq;
 845         struct bp_transmitter_control cntl = { 0 };
 846         enum bp_result bp_result;
 847
 848
 849         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 850                         != CONNECTOR_ID_EDP) {
 851                 BREAK_TO_DEBUGGER();
 852                 return;
 853         }
 854
 855         if (power_up != is_panel_powered_on(hwseq)) {
 856                 /* Send VBIOS command to prompt eDP panel power */
 857                 if (power_up) {
 858                         unsigned long long current_ts = dm_get_timestamp(ctx);
 859                         unsigned long long duration_in_ms =
 860                                         dm_get_elapse_time_in_ns(
 861                                                         ctx,
 862                                                         current_ts,
 863                                                         div64_u64(link->link_trace.time_stamp.edp_poweroff, 1000000));
 864                         unsigned long long wait_time_ms = 0;
 865
 866                         /* max 500ms from LCDVDD off to on */
 867                         if (link->link_trace.time_stamp.edp_poweroff == 0)
 868                                 wait_time_ms = 500;
 869                         else if (duration_in_ms < 500)
 870                                 wait_time_ms = 500 - duration_in_ms;
 871
 872                         if (wait_time_ms) {
 873                                 msleep(wait_time_ms);
 874                                 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
 875                                                 __func__, wait_time_ms);
 876                         }
 877
 878                 }
 879
 880                 DC_LOG_HW_RESUME_S3(
 881                                 "%s: Panel Power action: %s\n",
 882                                 __func__, (power_up ? "On":"Off"));
 883
 884                 cntl.action = power_up ?
 885                         TRANSMITTER_CONTROL_POWER_ON :
 886                         TRANSMITTER_CONTROL_POWER_OFF;
 887                 cntl.transmitter = link->link_enc->transmitter;
 888                 cntl.connector_obj_id = link->link_enc->connector;
 889                 cntl.coherent = false;
 890                 cntl.lanes_number = LANE_COUNT_FOUR;
 891                 cntl.hpd_sel = link->link_enc->hpd_source;
 892                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 893
 894                 if (!power_up)
 895                         /*save driver power off time stamp*/
 896                         link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
 897                 else
 898                         link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
 899
 900                 if (bp_result != BP_RESULT_OK)
 901                         DC_LOG_ERROR(
 902                                         "%s: Panel Power bp_result: %d\n",
 903                                         __func__, bp_result);
 904         } else {
 905                 DC_LOG_HW_RESUME_S3(
 906                                 "%s: Skipping Panel Power action: %s\n",
 907                                 __func__, (power_up ? "On":"Off"));
 908         }
 909 }
 910
 911 /*todo: cloned in stream enc, fix*/
 912 /*
 913  * @brief
 914  * eDP only. Control the backlight of the eDP panel
 915  */
 916 void hwss_edp_backlight_control(
 917                 struct dc_link *link,
 918                 bool enable)
 919 {
 920         struct dc_context *ctx = link->ctx;
 921         struct dce_hwseq *hws = ctx->dc->hwseq;
 922         struct bp_transmitter_control cntl = { 0 };
 923
 924         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 925                 != CONNECTOR_ID_EDP) {
 926                 BREAK_TO_DEBUGGER();
 927                 return;
 928         }
 929
 930         if (enable && is_panel_backlight_on(hws)) {
 931                 DC_LOG_HW_RESUME_S3(
 932                                 "%s: panel already powered up. Do nothing.\n",
 933                                 __func__);
 934                 return;
 935         }
 936
 937         /* Send VBIOS command to control eDP panel backlight */
 938
 939         DC_LOG_HW_RESUME_S3(
 940                         "%s: backlight action: %s\n",
 941                         __func__, (enable ? "On":"Off"));
 942
 943         cntl.action = enable ?
 944                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
 945                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
 946
 947         /*cntl.engine_id = ctx->engine;*/
 948         cntl.transmitter = link->link_enc->transmitter;
 949         cntl.connector_obj_id = link->link_enc->connector;
 950         /*todo: unhardcode*/
 951         cntl.lanes_number = LANE_COUNT_FOUR;
 952         cntl.hpd_sel = link->link_enc->hpd_source;
 953         cntl.signal = SIGNAL_TYPE_EDP;
 954
 955         /* For eDP, the following delays might need to be considered
 956          * after link training completed:
 957          * idle period - min. accounts for required BS-Idle pattern,
 958          * max. allows for source frame synchronization);
 959          * 50 msec max. delay from valid video data from source
 960          * to video on dislpay or backlight enable.
 961          *
 962          * Disable the delay for now.
 963          * Enable it in the future if necessary.
 964          */
 965         /* dc_service_sleep_in_milliseconds(50); */
 966                 /*edp 1.2*/
 967         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
 968                 edp_receiver_ready_T7(link);
 969         link_transmitter_control(ctx->dc_bios, &cntl);
 970         /*edp 1.2*/
 971         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
 972                 edp_receiver_ready_T9(link);
 973 }
 974
 975 void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
 976 {
 977         struct dc_stream_state *stream = pipe_ctx->stream;
 978         struct dc_link *link = stream->sink->link;
 979         struct dc *dc = pipe_ctx->stream->ctx->dc;
 980
 981         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
 982                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
 983                         pipe_ctx->stream_res.stream_enc);
 984
 985         if (dc_is_dp_signal(pipe_ctx->stream->signal))
 986                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
 987                         pipe_ctx->stream_res.stream_enc);
 988
 989         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
 990                         pipe_ctx->stream_res.stream_enc, true);
 991         if (pipe_ctx->stream_res.audio) {
 992                 if (option != KEEP_ACQUIRED_RESOURCE ||
 993                                 !dc->debug.az_endpoint_mute_only) {
 994                         /*only disalbe az_endpoint if power down or free*/
 995                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
 996                 }
 997
 998                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
 999                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1000                                         pipe_ctx->stream_res.stream_enc);
1001                 else
1002                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1003                                         pipe_ctx->stream_res.stream_enc);
1004                 /*don't free audio if it is from retrain or internal disable stream*/
1005                 if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
1006                         /*we have to dynamic arbitrate the audio endpoints*/
1007                         /*we free the resource, need reset is_audio_acquired*/
1008                         update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
1009                         pipe_ctx->stream_res.audio = NULL;
1010                 }
1011
1012                 /* TODO: notify audio driver for if audio modes list changed
1013                  * add audio mode list change flag */
1014                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1015                  * stream->stream_engine_id);
1016                  */
1017         }
1018
1019
1020         link->link_enc->funcs->connect_dig_be_to_fe(
1021                         link->link_enc,
1022                         pipe_ctx->stream_res.stream_enc->id,
1023                         false);
1024
1025 }
1026
1027 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1028                 struct dc_link_settings *link_settings)
1029 {
1030         struct encoder_unblank_param params = { { 0 } };
1031         struct dc_stream_state *stream = pipe_ctx->stream;
1032         struct dc_link *link = stream->sink->link;
1033
1034         /* only 3 items below are used by unblank */
1035         params.pixel_clk_khz =
1036                 pipe_ctx->stream->timing.pix_clk_khz;
1037         params.link_settings.link_rate = link_settings->link_rate;
1038
1039         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1040                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1041
1042         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1043                 link->dc->hwss.edp_backlight_control(link, true);
1044                 stream->bl_pwm_level = EDP_BACKLIGHT_RAMP_DISABLE_LEVEL;
1045         }
1046 }
1047 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1048 {
1049         struct dc_stream_state *stream = pipe_ctx->stream;
1050         struct dc_link *link = stream->sink->link;
1051
1052         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1053                 link->dc->hwss.edp_backlight_control(link, false);
1054                 dc_link_set_abm_disable(link);
1055         }
1056
1057         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1058                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1059 }
1060
1061
1062 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1063 {
1064         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1065                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1066 }
1067
1068 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1069 {
1070         switch (crtc_id) {
1071         case CONTROLLER_ID_D0:
1072                 return DTO_SOURCE_ID0;
1073         case CONTROLLER_ID_D1:
1074                 return DTO_SOURCE_ID1;
1075         case CONTROLLER_ID_D2:
1076                 return DTO_SOURCE_ID2;
1077         case CONTROLLER_ID_D3:
1078                 return DTO_SOURCE_ID3;
1079         case CONTROLLER_ID_D4:
1080                 return DTO_SOURCE_ID4;
1081         case CONTROLLER_ID_D5:
1082                 return DTO_SOURCE_ID5;
1083         default:
1084                 return DTO_SOURCE_UNKNOWN;
1085         }
1086 }
1087
1088 static void build_audio_output(
1089         struct dc_state *state,
1090         const struct pipe_ctx *pipe_ctx,
1091         struct audio_output *audio_output)
1092 {
1093         const struct dc_stream_state *stream = pipe_ctx->stream;
1094         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1095
1096         audio_output->signal = pipe_ctx->stream->signal;
1097
1098         /* audio_crtc_info  */
1099
1100         audio_output->crtc_info.h_total =
1101                 stream->timing.h_total;
1102
1103         /*
1104          * Audio packets are sent during actual CRTC blank physical signal, we
1105          * need to specify actual active signal portion
1106          */
1107         audio_output->crtc_info.h_active =
1108                         stream->timing.h_addressable
1109                         + stream->timing.h_border_left
1110                         + stream->timing.h_border_right;
1111
1112         audio_output->crtc_info.v_active =
1113                         stream->timing.v_addressable
1114                         + stream->timing.v_border_top
1115                         + stream->timing.v_border_bottom;
1116
1117         audio_output->crtc_info.pixel_repetition = 1;
1118
1119         audio_output->crtc_info.interlaced =
1120                         stream->timing.flags.INTERLACE;
1121
1122         audio_output->crtc_info.refresh_rate =
1123                 (stream->timing.pix_clk_khz*1000)/
1124                 (stream->timing.h_total*stream->timing.v_total);
1125
1126         audio_output->crtc_info.color_depth =
1127                 stream->timing.display_color_depth;
1128
1129         audio_output->crtc_info.requested_pixel_clock =
1130                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1131
1132         audio_output->crtc_info.calculated_pixel_clock =
1133                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1134
1135 /*for HDMI, audio ACR is with deep color ratio factor*/
1136         if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
1137                 audio_output->crtc_info.requested_pixel_clock ==
1138                                 stream->timing.pix_clk_khz) {
1139                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1140                         audio_output->crtc_info.requested_pixel_clock =
1141                                         audio_output->crtc_info.requested_pixel_clock/2;
1142                         audio_output->crtc_info.calculated_pixel_clock =
1143                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2;
1144
1145                 }
1146         }
1147
1148         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1149                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1150                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1151                                 state->dis_clk->funcs->get_dp_ref_clk_frequency(
1152                                                 state->dis_clk);
1153         }
1154
1155         audio_output->pll_info.feed_back_divider =
1156                         pipe_ctx->pll_settings.feedback_divider;
1157
1158         audio_output->pll_info.dto_source =
1159                 translate_to_dto_source(
1160                         pipe_ctx->stream_res.tg->inst + 1);
1161
1162         /* TODO hard code to enable for now. Need get from stream */
1163         audio_output->pll_info.ss_enabled = true;
1164
1165         audio_output->pll_info.ss_percentage =
1166                         pipe_ctx->pll_settings.ss_percentage;
1167 }
1168
1169 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1170                 struct tg_color *color)
1171 {
1172         uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
1173
1174         switch (pipe_ctx->plane_res.scl_data.format) {
1175         case PIXEL_FORMAT_ARGB8888:
1176                 /* set boarder color to red */
1177                 color->color_r_cr = color_value;
1178                 break;
1179
1180         case PIXEL_FORMAT_ARGB2101010:
1181                 /* set boarder color to blue */
1182                 color->color_b_cb = color_value;
1183                 break;
1184         case PIXEL_FORMAT_420BPP8:
1185                 /* set boarder color to green */
1186                 color->color_g_y = color_value;
1187                 break;
1188         case PIXEL_FORMAT_420BPP10:
1189                 /* set boarder color to yellow */
1190                 color->color_g_y = color_value;
1191                 color->color_r_cr = color_value;
1192                 break;
1193         case PIXEL_FORMAT_FP16:
1194                 /* set boarder color to white */
1195                 color->color_r_cr = color_value;
1196                 color->color_b_cb = color_value;
1197                 color->color_g_y = color_value;
1198                 break;
1199         default:
1200                 break;
1201         }
1202 }
1203
1204 static void program_scaler(const struct dc *dc,
1205                 const struct pipe_ctx *pipe_ctx)
1206 {
1207         struct tg_color color = {0};
1208
1209 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1210         /* TOFPGA */
1211         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1212                 return;
1213 #endif
1214
1215         if (dc->debug.surface_visual_confirm)
1216                 get_surface_visual_confirm_color(pipe_ctx, &color);
1217         else
1218                 color_space_to_black_color(dc,
1219                                 pipe_ctx->stream->output_color_space,
1220                                 &color);
1221
1222         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1223                 pipe_ctx->plane_res.xfm,
1224                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1225                 &pipe_ctx->stream->bit_depth_params);
1226
1227         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color)
1228                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1229                                 pipe_ctx->stream_res.tg,
1230                                 &color);
1231
1232         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1233                 &pipe_ctx->plane_res.scl_data);
1234 }
1235
1236 static enum dc_status dce110_enable_stream_timing(
1237                 struct pipe_ctx *pipe_ctx,
1238                 struct dc_state *context,
1239                 struct dc *dc)
1240 {
1241         struct dc_stream_state *stream = pipe_ctx->stream;
1242         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1243                         pipe_ctx[pipe_ctx->pipe_idx];
1244         struct tg_color black_color = {0};
1245
1246         if (!pipe_ctx_old->stream) {
1247
1248                 /* program blank color */
1249                 color_space_to_black_color(dc,
1250                                 stream->output_color_space, &black_color);
1251                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1252                                 pipe_ctx->stream_res.tg,
1253                                 &black_color);
1254
1255                 /*
1256                  * Must blank CRTC after disabling power gating and before any
1257                  * programming, otherwise CRTC will be hung in bad state
1258                  */
1259                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1260
1261                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1262                                 pipe_ctx->clock_source,
1263                                 &pipe_ctx->stream_res.pix_clk_params,
1264                                 &pipe_ctx->pll_settings)) {
1265                         BREAK_TO_DEBUGGER();
1266                         return DC_ERROR_UNEXPECTED;
1267                 }
1268
1269                 pipe_ctx->stream_res.tg->funcs->program_timing(
1270                                 pipe_ctx->stream_res.tg,
1271                                 &stream->timing,
1272                                 true);
1273
1274                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1275                                 pipe_ctx->stream_res.tg,
1276                                 0x182);
1277         }
1278
1279         if (!pipe_ctx_old->stream) {
1280                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1281                                 pipe_ctx->stream_res.tg)) {
1282                         BREAK_TO_DEBUGGER();
1283                         return DC_ERROR_UNEXPECTED;
1284                 }
1285         }
1286
1287
1288
1289         return DC_OK;
1290 }
1291
1292 static enum dc_status apply_single_controller_ctx_to_hw(
1293                 struct pipe_ctx *pipe_ctx,
1294                 struct dc_state *context,
1295                 struct dc *dc)
1296 {
1297         struct dc_stream_state *stream = pipe_ctx->stream;
1298         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1299                         pipe_ctx[pipe_ctx->pipe_idx];
1300
1301         /*  */
1302         dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
1303
1304         /* FPGA does not program backend */
1305         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1306                 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1307                 pipe_ctx->stream_res.opp,
1308                 COLOR_SPACE_YCBCR601,
1309                 stream->timing.display_color_depth,
1310                 pipe_ctx->stream->signal);
1311
1312                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1313                         pipe_ctx->stream_res.opp,
1314                         &stream->bit_depth_params,
1315                         &stream->clamping);
1316                 return DC_OK;
1317         }
1318         /* TODO: move to stream encoder */
1319         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1320                 if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
1321                         BREAK_TO_DEBUGGER();
1322                         return DC_ERROR_UNEXPECTED;
1323                 }
1324         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1325                         pipe_ctx->stream_res.opp,
1326                         COLOR_SPACE_YCBCR601,
1327                         stream->timing.display_color_depth,
1328                         pipe_ctx->stream->signal);
1329
1330         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1331                 stream->sink->link->link_enc->funcs->setup(
1332                         stream->sink->link->link_enc,
1333                         pipe_ctx->stream->signal);
1334
1335         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1336                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
1337                 pipe_ctx->stream_res.stream_enc,
1338                 pipe_ctx->stream_res.tg->inst,
1339                 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
1340
1341
1342         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1343                 pipe_ctx->stream_res.opp,
1344                 &stream->bit_depth_params,
1345                 &stream->clamping);
1346
1347         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1348                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
1349                         pipe_ctx->stream_res.stream_enc,
1350                         &stream->timing,
1351                         stream->output_color_space);
1352
1353         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1354                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
1355                         pipe_ctx->stream_res.stream_enc,
1356                         &stream->timing,
1357                         stream->phy_pix_clk,
1358                         pipe_ctx->stream_res.audio != NULL);
1359
1360         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
1361                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
1362                         pipe_ctx->stream_res.stream_enc,
1363                         &stream->timing,
1364                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
1365                         true : false);
1366
1367         resource_build_info_frame(pipe_ctx);
1368         dce110_update_info_frame(pipe_ctx);
1369         if (!pipe_ctx_old->stream)
1370                 core_link_enable_stream(context, pipe_ctx);
1371
1372         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1373
1374         pipe_ctx->stream->sink->link->psr_enabled = false;
1375
1376         return DC_OK;
1377 }
1378
1379 /******************************************************************************/
1380
1381 static void power_down_encoders(struct dc *dc)
1382 {
1383         int i;
1384         enum connector_id connector_id;
1385         enum signal_type signal = SIGNAL_TYPE_NONE;
1386
1387         /* do not know BIOS back-front mapping, simply blank all. It will not
1388          * hurt for non-DP
1389          */
1390         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1391                 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1392                                         dc->res_pool->stream_enc[i]);
1393         }
1394
1395         for (i = 0; i < dc->link_count; i++) {
1396                 connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
1397                 if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
1398                         (connector_id == CONNECTOR_ID_EDP)) {
1399
1400                         if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1401                                 dp_receiver_power_ctrl(dc->links[i], false);
1402                         if (connector_id == CONNECTOR_ID_EDP)
1403                                 signal = SIGNAL_TYPE_EDP;
1404                 }
1405
1406                 dc->links[i]->link_enc->funcs->disable_output(
1407                                 dc->links[i]->link_enc, signal);
1408         }
1409 }
1410
1411 static void power_down_controllers(struct dc *dc)
1412 {
1413         int i;
1414
1415         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1416                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1417                                 dc->res_pool->timing_generators[i]);
1418         }
1419 }
1420
1421 static void power_down_clock_sources(struct dc *dc)
1422 {
1423         int i;
1424
1425         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1426                 dc->res_pool->dp_clock_source) == false)
1427                 dm_error("Failed to power down pll! (dp clk src)\n");
1428
1429         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1430                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1431                                 dc->res_pool->clock_sources[i]) == false)
1432                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1433         }
1434 }
1435
1436 static void power_down_all_hw_blocks(struct dc *dc)
1437 {
1438         power_down_encoders(dc);
1439
1440         power_down_controllers(dc);
1441
1442         power_down_clock_sources(dc);
1443
1444 #if defined(CONFIG_DRM_AMD_DC_FBC)
1445         if (dc->fbc_compressor)
1446                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1447 #endif
1448 }
1449
1450 static void disable_vga_and_power_gate_all_controllers(
1451                 struct dc *dc)
1452 {
1453         int i;
1454         struct timing_generator *tg;
1455         struct dc_context *ctx = dc->ctx;
1456
1457         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1458                 tg = dc->res_pool->timing_generators[i];
1459
1460                 if (tg->funcs->disable_vga)
1461                         tg->funcs->disable_vga(tg);
1462
1463                 /* Enable CLOCK gating for each pipe BEFORE controller
1464                  * powergating. */
1465                 enable_display_pipe_clock_gating(ctx,
1466                                 true);
1467
1468                 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1469                 dc->hwss.disable_plane(dc,
1470                         &dc->current_state->res_ctx.pipe_ctx[i]);
1471         }
1472 }
1473
1474 static struct dc_link *get_link_for_edp(struct dc *dc)
1475 {
1476         int i;
1477
1478         for (i = 0; i < dc->link_count; i++) {
1479                 if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
1480                         return dc->links[i];
1481         }
1482         return NULL;
1483 }
1484
1485 static struct dc_link *get_link_for_edp_not_in_use(
1486                 struct dc *dc,
1487                 struct dc_state *context)
1488 {
1489         int i;
1490         struct dc_link *link = NULL;
1491
1492         /* check if eDP panel is suppose to be set mode, if yes, no need to disable */
1493         for (i = 0; i < context->stream_count; i++) {
1494                 if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
1495                         return NULL;
1496         }
1497
1498         /* check if there is an eDP panel not in use */
1499         for (i = 0; i < dc->link_count; i++) {
1500                 if (dc->links[i]->local_sink &&
1501                         dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1502                         link = dc->links[i];
1503                         break;
1504                 }
1505         }
1506
1507         return link;
1508 }
1509
1510 /**
1511  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1512  *  1. Power down all DC HW blocks
1513  *  2. Disable VGA engine on all controllers
1514  *  3. Enable power gating for controller
1515  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1516  */
1517 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1518 {
1519         struct dc_link *edp_link_to_turnoff = NULL;
1520         struct dc_link *edp_link = get_link_for_edp(dc);
1521         bool can_eDP_fast_boot_optimize = false;
1522
1523         if (edp_link) {
1524                 can_eDP_fast_boot_optimize =
1525                                 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc);
1526         }
1527
1528         if (can_eDP_fast_boot_optimize) {
1529                 edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context);
1530
1531                 /* if OS doesn't light up eDP and eDP link is available, we want to disable
1532                  * If resume from S4/S5, should optimization.
1533                  */
1534                 if (!edp_link_to_turnoff)
1535                         dc->apply_edp_fast_boot_optimization = true;
1536         }
1537
1538         if (!dc->apply_edp_fast_boot_optimization) {
1539                 if (edp_link_to_turnoff) {
1540                         /*turn off backlight before DP_blank and encoder powered down*/
1541                         dc->hwss.edp_backlight_control(edp_link_to_turnoff, false);
1542                 }
1543                 /*resume from S3, no vbios posting, no need to power down again*/
1544                 power_down_all_hw_blocks(dc);
1545                 disable_vga_and_power_gate_all_controllers(dc);
1546                 if (edp_link_to_turnoff)
1547                         dc->hwss.edp_power_control(edp_link_to_turnoff, false);
1548         }
1549         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1550 }
1551
1552 static uint32_t compute_pstate_blackout_duration(
1553         struct bw_fixed blackout_duration,
1554         const struct dc_stream_state *stream)
1555 {
1556         uint32_t total_dest_line_time_ns;
1557         uint32_t pstate_blackout_duration_ns;
1558
1559         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1560
1561         total_dest_line_time_ns = 1000000UL *
1562                 stream->timing.h_total /
1563                 stream->timing.pix_clk_khz +
1564                 pstate_blackout_duration_ns;
1565
1566         return total_dest_line_time_ns;
1567 }
1568
1569 static void dce110_set_displaymarks(
1570         const struct dc *dc,
1571         struct dc_state *context)
1572 {
1573         uint8_t i, num_pipes;
1574         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1575
1576         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1577                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1578                 uint32_t total_dest_line_time_ns;
1579
1580                 if (pipe_ctx->stream == NULL)
1581                         continue;
1582
1583                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1584                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1585                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1586                         pipe_ctx->plane_res.mi,
1587                         context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1588                         context->bw.dce.stutter_exit_wm_ns[num_pipes],
1589                         context->bw.dce.stutter_entry_wm_ns[num_pipes],
1590                         context->bw.dce.urgent_wm_ns[num_pipes],
1591                         total_dest_line_time_ns);
1592                 if (i == underlay_idx) {
1593                         num_pipes++;
1594                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1595                                 pipe_ctx->plane_res.mi,
1596                                 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1597                                 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1598                                 context->bw.dce.urgent_wm_ns[num_pipes],
1599                                 total_dest_line_time_ns);
1600                 }
1601                 num_pipes++;
1602         }
1603 }
1604
1605 static void set_safe_displaymarks(
1606                 struct resource_context *res_ctx,
1607                 const struct resource_pool *pool)
1608 {
1609         int i;
1610         int underlay_idx = pool->underlay_pipe_index;
1611         struct dce_watermarks max_marks = {
1612                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1613         struct dce_watermarks nbp_marks = {
1614                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1615         struct dce_watermarks min_marks = { 0, 0, 0, 0};
1616
1617         for (i = 0; i < MAX_PIPES; i++) {
1618                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1619                         continue;
1620
1621                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1622                                 res_ctx->pipe_ctx[i].plane_res.mi,
1623                                 nbp_marks,
1624                                 max_marks,
1625                                 min_marks,
1626                                 max_marks,
1627                                 MAX_WATERMARK);
1628
1629                 if (i == underlay_idx)
1630                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1631                                 res_ctx->pipe_ctx[i].plane_res.mi,
1632                                 nbp_marks,
1633                                 max_marks,
1634                                 max_marks,
1635                                 MAX_WATERMARK);
1636
1637         }
1638 }
1639
1640 /*******************************************************************************
1641  * Public functions
1642  ******************************************************************************/
1643
1644 static void set_drr(struct pipe_ctx **pipe_ctx,
1645                 int num_pipes, int vmin, int vmax)
1646 {
1647         int i = 0;
1648         struct drr_params params = {0};
1649
1650         params.vertical_total_max = vmax;
1651         params.vertical_total_min = vmin;
1652
1653         /* TODO: If multiple pipes are to be supported, you need
1654          * some GSL stuff
1655          */
1656
1657         for (i = 0; i < num_pipes; i++) {
1658                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
1659         }
1660 }
1661
1662 static void get_position(struct pipe_ctx **pipe_ctx,
1663                 int num_pipes,
1664                 struct crtc_position *position)
1665 {
1666         int i = 0;
1667
1668         /* TODO: handle pipes > 1
1669          */
1670         for (i = 0; i < num_pipes; i++)
1671                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1672 }
1673
1674 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1675                 int num_pipes, const struct dc_static_screen_events *events)
1676 {
1677         unsigned int i;
1678         unsigned int value = 0;
1679
1680         if (events->overlay_update)
1681                 value |= 0x100;
1682         if (events->surface_update)
1683                 value |= 0x80;
1684         if (events->cursor_update)
1685                 value |= 0x2;
1686         if (events->force_trigger)
1687                 value |= 0x1;
1688
1689 #if defined(CONFIG_DRM_AMD_DC_FBC)
1690         value |= 0x84;
1691 #endif
1692
1693         for (i = 0; i < num_pipes; i++)
1694                 pipe_ctx[i]->stream_res.tg->funcs->
1695                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
1696 }
1697
1698 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
1699  * may not be programmed yet.
1700  * TODO: after mode set, pre_mode_set = false,
1701  * may read PLL register to get pixel clock
1702  */
1703 static uint32_t get_max_pixel_clock_for_all_paths(
1704         struct dc *dc,
1705         struct dc_state *context,
1706         bool pre_mode_set)
1707 {
1708         uint32_t max_pix_clk = 0;
1709         int i;
1710
1711         if (!pre_mode_set) {
1712                 /* TODO: read ASIC register to get pixel clock */
1713                 ASSERT(0);
1714         }
1715
1716         for (i = 0; i < MAX_PIPES; i++) {
1717                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1718
1719                 if (pipe_ctx->stream == NULL)
1720                         continue;
1721
1722                 /* do not check under lay */
1723                 if (pipe_ctx->top_pipe)
1724                         continue;
1725
1726                 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
1727                         max_pix_clk =
1728                                 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1729         }
1730
1731         if (max_pix_clk == 0)
1732                 ASSERT(0);
1733
1734         return max_pix_clk;
1735 }
1736
1737 /*
1738  * Find clock state based on clock requested. if clock value is 0, simply
1739  * set clock state as requested without finding clock state by clock value
1740  */
1741
1742 static void apply_min_clocks(
1743         struct dc *dc,
1744         struct dc_state *context,
1745         enum dm_pp_clocks_state *clocks_state,
1746         bool pre_mode_set)
1747 {
1748         struct state_dependent_clocks req_clocks = {0};
1749
1750         if (!pre_mode_set) {
1751                 /* set clock_state without verification */
1752                 if (context->dis_clk->funcs->set_min_clocks_state) {
1753                         context->dis_clk->funcs->set_min_clocks_state(
1754                                                 context->dis_clk, *clocks_state);
1755                         return;
1756                 }
1757
1758                 /* TODO: This is incorrect. Figure out how to fix. */
1759                 context->dis_clk->funcs->apply_clock_voltage_request(
1760                                 context->dis_clk,
1761                                 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1762                                 context->dis_clk->cur_clocks_value.dispclk_in_khz,
1763                                 pre_mode_set,
1764                                 false);
1765
1766                 context->dis_clk->funcs->apply_clock_voltage_request(
1767                                 context->dis_clk,
1768                                 DM_PP_CLOCK_TYPE_PIXELCLK,
1769                                 context->dis_clk->cur_clocks_value.max_pixelclk_in_khz,
1770                                 pre_mode_set,
1771                                 false);
1772
1773                 context->dis_clk->funcs->apply_clock_voltage_request(
1774                                 context->dis_clk,
1775                                 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1776                                 context->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz,
1777                                 pre_mode_set,
1778                                 false);
1779                 return;
1780         }
1781
1782         /* get the required state based on state dependent clocks:
1783          * display clock and pixel clock
1784          */
1785         req_clocks.display_clk_khz = context->bw.dce.dispclk_khz;
1786
1787         req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
1788                         dc, context, true);
1789
1790         if (context->dis_clk->funcs->get_required_clocks_state) {
1791                 *clocks_state = context->dis_clk->funcs->get_required_clocks_state(
1792                                 context->dis_clk, &req_clocks);
1793                 context->dis_clk->funcs->set_min_clocks_state(
1794                         context->dis_clk, *clocks_state);
1795         } else {
1796                 context->dis_clk->funcs->apply_clock_voltage_request(
1797                                 context->dis_clk,
1798                                 DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1799                                 req_clocks.display_clk_khz,
1800                                 pre_mode_set,
1801                                 false);
1802
1803                 context->dis_clk->funcs->apply_clock_voltage_request(
1804                                 context->dis_clk,
1805                                 DM_PP_CLOCK_TYPE_PIXELCLK,
1806                                 req_clocks.pixel_clk_khz,
1807                                 pre_mode_set,
1808                                 false);
1809
1810                 context->dis_clk->funcs->apply_clock_voltage_request(
1811                                 context->dis_clk,
1812                                 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
1813                                 req_clocks.pixel_clk_khz,
1814                                 pre_mode_set,
1815                                 false);
1816         }
1817 }
1818
1819 #if defined(CONFIG_DRM_AMD_DC_FBC)
1820
1821 /*
1822  *  Check if FBC can be enabled
1823  */
1824 static bool should_enable_fbc(struct dc *dc,
1825                               struct dc_state *context,
1826                               uint32_t *pipe_idx)
1827 {
1828         uint32_t i;
1829         struct pipe_ctx *pipe_ctx = NULL;
1830         struct resource_context *res_ctx = &context->res_ctx;
1831
1832
1833         ASSERT(dc->fbc_compressor);
1834
1835         /* FBC memory should be allocated */
1836         if (!dc->ctx->fbc_gpu_addr)
1837                 return false;
1838
1839         /* Only supports single display */
1840         if (context->stream_count != 1)
1841                 return false;
1842
1843         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1844                 if (res_ctx->pipe_ctx[i].stream) {
1845                         pipe_ctx = &res_ctx->pipe_ctx[i];
1846                         *pipe_idx = i;
1847                         break;
1848                 }
1849         }
1850
1851         /* Pipe context should be found */
1852         ASSERT(pipe_ctx);
1853
1854         /* Only supports eDP */
1855         if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
1856                 return false;
1857
1858         /* PSR should not be enabled */
1859         if (pipe_ctx->stream->sink->link->psr_enabled)
1860                 return false;
1861
1862         /* Nothing to compress */
1863         if (!pipe_ctx->plane_state)
1864                 return false;
1865
1866         /* Only for non-linear tiling */
1867         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1868                 return false;
1869
1870         return true;
1871 }
1872
1873 /*
1874  *  Enable FBC
1875  */
1876 static void enable_fbc(struct dc *dc,
1877                        struct dc_state *context)
1878 {
1879         uint32_t pipe_idx = 0;
1880
1881         if (should_enable_fbc(dc, context, &pipe_idx)) {
1882                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1883                 struct compr_addr_and_pitch_params params = {0, 0, 0};
1884                 struct compressor *compr = dc->fbc_compressor;
1885                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1886
1887
1888                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
1889                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
1890
1891                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1892
1893                 compr->funcs->surface_address_and_pitch(compr, &params);
1894                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1895
1896                 compr->funcs->enable_fbc(compr, &params);
1897         }
1898 }
1899 #endif
1900
1901 static void dce110_reset_hw_ctx_wrap(
1902                 struct dc *dc,
1903                 struct dc_state *context)
1904 {
1905         int i;
1906
1907         /* Reset old context */
1908         /* look up the targets that have been removed since last commit */
1909         for (i = 0; i < MAX_PIPES; i++) {
1910                 struct pipe_ctx *pipe_ctx_old =
1911                         &dc->current_state->res_ctx.pipe_ctx[i];
1912                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1913
1914                 /* Note: We need to disable output if clock sources change,
1915                  * since bios does optimization and doesn't apply if changing
1916                  * PHY when not already disabled.
1917                  */
1918
1919                 /* Skip underlay pipe since it will be handled in commit surface*/
1920                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1921                         continue;
1922
1923                 if (!pipe_ctx->stream ||
1924                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1925                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1926
1927                         /* Disable if new stream is null. O/w, if stream is
1928                          * disabled already, no need to disable again.
1929                          */
1930                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
1931                                 core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
1932
1933                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1934                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1935                                 dm_error("DC: failed to blank crtc!\n");
1936                                 BREAK_TO_DEBUGGER();
1937                         }
1938                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1939                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1940                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
1941
1942                         if (old_clk)
1943                                 old_clk->funcs->cs_power_down(old_clk);
1944
1945                         dc->hwss.disable_plane(dc, pipe_ctx_old);
1946
1947                         pipe_ctx_old->stream = NULL;
1948                 }
1949         }
1950 }
1951
1952
1953 enum dc_status dce110_apply_ctx_to_hw(
1954                 struct dc *dc,
1955                 struct dc_state *context)
1956 {
1957         struct dc_bios *dcb = dc->ctx->dc_bios;
1958         enum dc_status status;
1959         int i;
1960         enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
1961
1962         /* Reset old context */
1963         /* look up the targets that have been removed since last commit */
1964         dc->hwss.reset_hw_ctx_wrap(dc, context);
1965
1966         /* Skip applying if no targets */
1967         if (context->stream_count <= 0)
1968                 return DC_OK;
1969
1970         /* Apply new context */
1971         dcb->funcs->set_scratch_critical_state(dcb, true);
1972
1973         /* below is for real asic only */
1974         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1975                 struct pipe_ctx *pipe_ctx_old =
1976                                         &dc->current_state->res_ctx.pipe_ctx[i];
1977                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1978
1979                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
1980                         continue;
1981
1982                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
1983                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
1984                                 dce_crtc_switch_to_clk_src(dc->hwseq,
1985                                                 pipe_ctx->clock_source, i);
1986                         continue;
1987                 }
1988
1989                 dc->hwss.enable_display_power_gating(
1990                                 dc, i, dc->ctx->dc_bios,
1991                                 PIPE_GATING_CONTROL_DISABLE);
1992         }
1993
1994         set_safe_displaymarks(&context->res_ctx, dc->res_pool);
1995
1996 #if defined(CONFIG_DRM_AMD_DC_FBC)
1997         if (dc->fbc_compressor)
1998                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1999 #endif
2000         /*TODO: when pplib works*/
2001         apply_min_clocks(dc, context, &clocks_state, true);
2002
2003 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2004         if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
2005                 if (context->bw.dcn.calc_clk.fclk_khz
2006                                 > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
2007                         struct dm_pp_clock_for_voltage_req clock;
2008
2009                         clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
2010                         clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
2011                         dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
2012                         dc->current_state->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
2013                         context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
2014                 }
2015                 if (context->bw.dcn.calc_clk.dcfclk_khz
2016                                 > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
2017                         struct dm_pp_clock_for_voltage_req clock;
2018
2019                         clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
2020                         clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
2021                         dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
2022                         dc->current_state->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
2023                         context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
2024                 }
2025                 if (context->bw.dcn.calc_clk.dispclk_khz
2026                                 > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
2027                         dc->res_pool->display_clock->funcs->set_clock(
2028                                         dc->res_pool->display_clock,
2029                                         context->bw.dcn.calc_clk.dispclk_khz);
2030                         dc->current_state->bw.dcn.cur_clk.dispclk_khz =
2031                                         context->bw.dcn.calc_clk.dispclk_khz;
2032                         context->bw.dcn.cur_clk.dispclk_khz =
2033                                         context->bw.dcn.calc_clk.dispclk_khz;
2034                 }
2035         } else
2036 #endif
2037         if (context->bw.dce.dispclk_khz
2038                         > dc->current_state->bw.dce.dispclk_khz) {
2039                 dc->res_pool->display_clock->funcs->set_clock(
2040                                 dc->res_pool->display_clock,
2041                                 context->bw.dce.dispclk_khz * 115 / 100);
2042         }
2043         /* program audio wall clock. use HDMI as clock source if HDMI
2044          * audio active. Otherwise, use DP as clock source
2045          * first, loop to find any HDMI audio, if not, loop find DP audio
2046          */
2047         /* Setup audio rate clock source */
2048         /* Issue:
2049         * Audio lag happened on DP monitor when unplug a HDMI monitor
2050         *
2051         * Cause:
2052         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2053         * is set to either dto0 or dto1, audio should work fine.
2054         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2055         * set to dto0 will cause audio lag.
2056         *
2057         * Solution:
2058         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2059         * find first available pipe with audio, setup audio wall DTO per topology
2060         * instead of per pipe.
2061         */
2062         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2063                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2064
2065                 if (pipe_ctx->stream == NULL)
2066                         continue;
2067
2068                 if (pipe_ctx->top_pipe)
2069                         continue;
2070
2071                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2072                         continue;
2073
2074                 if (pipe_ctx->stream_res.audio != NULL) {
2075                         struct audio_output audio_output;
2076
2077                         build_audio_output(context, pipe_ctx, &audio_output);
2078
2079                         pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2080                                 pipe_ctx->stream_res.audio,
2081                                 pipe_ctx->stream->signal,
2082                                 &audio_output.crtc_info,
2083                                 &audio_output.pll_info);
2084                         break;
2085                 }
2086         }
2087
2088         /* no HDMI audio is found, try DP audio */
2089         if (i == dc->res_pool->pipe_count) {
2090                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2091                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2092
2093                         if (pipe_ctx->stream == NULL)
2094                                 continue;
2095
2096                         if (pipe_ctx->top_pipe)
2097                                 continue;
2098
2099                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2100                                 continue;
2101
2102                         if (pipe_ctx->stream_res.audio != NULL) {
2103                                 struct audio_output audio_output;
2104
2105                                 build_audio_output(context, pipe_ctx, &audio_output);
2106
2107                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2108                                         pipe_ctx->stream_res.audio,
2109                                         pipe_ctx->stream->signal,
2110                                         &audio_output.crtc_info,
2111                                         &audio_output.pll_info);
2112                                 break;
2113                         }
2114                 }
2115         }
2116
2117         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2118                 struct pipe_ctx *pipe_ctx_old =
2119                                         &dc->current_state->res_ctx.pipe_ctx[i];
2120                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2121
2122                 if (pipe_ctx->stream == NULL)
2123                         continue;
2124
2125                 if (pipe_ctx->stream == pipe_ctx_old->stream)
2126                         continue;
2127
2128                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2129                         continue;
2130
2131                 if (pipe_ctx->top_pipe)
2132                         continue;
2133
2134                 if (context->res_ctx.pipe_ctx[i].stream_res.audio != NULL) {
2135
2136                         struct audio_output audio_output;
2137
2138                         build_audio_output(context, pipe_ctx, &audio_output);
2139
2140                         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2141                                 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
2142                                                 pipe_ctx->stream_res.stream_enc,
2143                                                 pipe_ctx->stream_res.audio->inst,
2144                                                 &pipe_ctx->stream->audio_info);
2145                         else
2146                                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
2147                                                 pipe_ctx->stream_res.stream_enc,
2148                                                 pipe_ctx->stream_res.audio->inst,
2149                                                 &pipe_ctx->stream->audio_info,
2150                                                 &audio_output.crtc_info);
2151
2152                         pipe_ctx->stream_res.audio->funcs->az_configure(
2153                                         pipe_ctx->stream_res.audio,
2154                                         pipe_ctx->stream->signal,
2155                                         &audio_output.crtc_info,
2156                                         &pipe_ctx->stream->audio_info);
2157                 }
2158
2159                 status = apply_single_controller_ctx_to_hw(
2160                                 pipe_ctx,
2161                                 context,
2162                                 dc);
2163
2164                 if (DC_OK != status)
2165                         return status;
2166         }
2167
2168         /* to save power */
2169         apply_min_clocks(dc, context, &clocks_state, false);
2170
2171         dcb->funcs->set_scratch_critical_state(dcb, false);
2172
2173 #if defined(CONFIG_DRM_AMD_DC_FBC)
2174         if (dc->fbc_compressor)
2175                 enable_fbc(dc, context);
2176
2177 #endif
2178
2179         return DC_OK;
2180 }
2181
2182 /*******************************************************************************
2183  * Front End programming
2184  ******************************************************************************/
2185 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2186 {
2187         struct default_adjustment default_adjust = { 0 };
2188
2189         default_adjust.force_hw_default = false;
2190         default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2191         default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2192         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2193         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2194
2195         /* display color depth */
2196         default_adjust.color_depth =
2197                 pipe_ctx->stream->timing.display_color_depth;
2198
2199         /* Lb color depth */
2200         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2201
2202         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2203                                         pipe_ctx->plane_res.xfm, &default_adjust);
2204 }
2205
2206
2207 /*******************************************************************************
2208  * In order to turn on/off specific surface we will program
2209  * Blender + CRTC
2210  *
2211  * In case that we have two surfaces and they have a different visibility
2212  * we can't turn off the CRTC since it will turn off the entire display
2213  *
2214  * |----------------------------------------------- |
2215  * |bottom pipe|curr pipe  |              |         |
2216  * |Surface    |Surface    | Blender      |  CRCT   |
2217  * |visibility |visibility | Configuration|         |
2218  * |------------------------------------------------|
2219  * |   off     |    off    | CURRENT_PIPE | blank   |
2220  * |   off     |    on     | CURRENT_PIPE | unblank |
2221  * |   on      |    off    | OTHER_PIPE   | unblank |
2222  * |   on      |    on     | BLENDING     | unblank |
2223  * -------------------------------------------------|
2224  *
2225  ******************************************************************************/
2226 static void program_surface_visibility(const struct dc *dc,
2227                 struct pipe_ctx *pipe_ctx)
2228 {
2229         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2230         bool blank_target = false;
2231
2232         if (pipe_ctx->bottom_pipe) {
2233
2234                 /* For now we are supporting only two pipes */
2235                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2236
2237                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2238                         if (pipe_ctx->plane_state->visible)
2239                                 blender_mode = BLND_MODE_BLENDING;
2240                         else
2241                                 blender_mode = BLND_MODE_OTHER_PIPE;
2242
2243                 } else if (!pipe_ctx->plane_state->visible)
2244                         blank_target = true;
2245
2246         } else if (!pipe_ctx->plane_state->visible)
2247                 blank_target = true;
2248
2249         dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2250         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2251
2252 }
2253
2254 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2255 {
2256         int i = 0;
2257         struct xfm_grph_csc_adjustment adjust;
2258         memset(&adjust, 0, sizeof(adjust));
2259         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2260
2261
2262         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2263                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2264
2265                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2266                         adjust.temperature_matrix[i] =
2267                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2268         }
2269
2270         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2271 }
2272 static void update_plane_addr(const struct dc *dc,
2273                 struct pipe_ctx *pipe_ctx)
2274 {
2275         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2276
2277         if (plane_state == NULL)
2278                 return;
2279
2280         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2281                         pipe_ctx->plane_res.mi,
2282                         &plane_state->address,
2283                         plane_state->flip_immediate);
2284
2285         plane_state->status.requested_address = plane_state->address;
2286 }
2287
2288 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2289 {
2290         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2291
2292         if (plane_state == NULL)
2293                 return;
2294
2295         plane_state->status.is_flip_pending =
2296                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2297                                         pipe_ctx->plane_res.mi);
2298
2299         if (plane_state->status.is_flip_pending && !plane_state->visible)
2300                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2301
2302         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2303         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2304                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2305                 plane_state->status.is_right_eye =\
2306                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2307         }
2308 }
2309
2310 void dce110_power_down(struct dc *dc)
2311 {
2312         power_down_all_hw_blocks(dc);
2313         disable_vga_and_power_gate_all_controllers(dc);
2314 }
2315
2316 static bool wait_for_reset_trigger_to_occur(
2317         struct dc_context *dc_ctx,
2318         struct timing_generator *tg)
2319 {
2320         bool rc = false;
2321
2322         /* To avoid endless loop we wait at most
2323          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2324         const uint32_t frames_to_wait_on_triggered_reset = 10;
2325         uint32_t i;
2326
2327         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2328
2329                 if (!tg->funcs->is_counter_moving(tg)) {
2330                         DC_ERROR("TG counter is not moving!\n");
2331                         break;
2332                 }
2333
2334                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2335                         rc = true;
2336                         /* usually occurs at i=1 */
2337                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2338                                         i);
2339                         break;
2340                 }
2341
2342                 /* Wait for one frame. */
2343                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2344                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2345         }
2346
2347         if (false == rc)
2348                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2349
2350         return rc;
2351 }
2352
2353 /* Enable timing synchronization for a group of Timing Generators. */
2354 static void dce110_enable_timing_synchronization(
2355                 struct dc *dc,
2356                 int group_index,
2357                 int group_size,
2358                 struct pipe_ctx *grouped_pipes[])
2359 {
2360         struct dc_context *dc_ctx = dc->ctx;
2361         struct dcp_gsl_params gsl_params = { 0 };
2362         int i;
2363
2364         DC_SYNC_INFO("GSL: Setting-up...\n");
2365
2366         /* Designate a single TG in the group as a master.
2367          * Since HW doesn't care which one, we always assign
2368          * the 1st one in the group. */
2369         gsl_params.gsl_group = 0;
2370         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2371
2372         for (i = 0; i < group_size; i++)
2373                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2374                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2375
2376         /* Reset slave controllers on master VSync */
2377         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2378
2379         for (i = 1 /* skip the master */; i < group_size; i++)
2380                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2381                                 grouped_pipes[i]->stream_res.tg,
2382                                 gsl_params.gsl_group);
2383
2384         for (i = 1 /* skip the master */; i < group_size; i++) {
2385                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2386                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2387                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2388                                 grouped_pipes[i]->stream_res.tg);
2389         }
2390
2391         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2392          * is that the sync'ed displays will not drift out of sync over time*/
2393         DC_SYNC_INFO("GSL: Restoring register states.\n");
2394         for (i = 0; i < group_size; i++)
2395                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2396
2397         DC_SYNC_INFO("GSL: Set-up complete.\n");
2398 }
2399
2400 static void dce110_enable_per_frame_crtc_position_reset(
2401                 struct dc *dc,
2402                 int group_size,
2403                 struct pipe_ctx *grouped_pipes[])
2404 {
2405         struct dc_context *dc_ctx = dc->ctx;
2406         struct dcp_gsl_params gsl_params = { 0 };
2407         int i;
2408
2409         gsl_params.gsl_group = 0;
2410         gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst;
2411
2412         for (i = 0; i < group_size; i++)
2413                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2414                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2415
2416         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2417
2418         for (i = 1; i < group_size; i++)
2419                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2420                                 grouped_pipes[i]->stream_res.tg,
2421                                 gsl_params.gsl_master,
2422                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
2423
2424         DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2425         for (i = 1; i < group_size; i++)
2426                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2427
2428         for (i = 0; i < group_size; i++)
2429                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2430
2431 }
2432
2433 static void init_hw(struct dc *dc)
2434 {
2435         int i;
2436         struct dc_bios *bp;
2437         struct transform *xfm;
2438         struct abm *abm;
2439
2440         bp = dc->ctx->dc_bios;
2441         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2442                 xfm = dc->res_pool->transforms[i];
2443                 xfm->funcs->transform_reset(xfm);
2444
2445                 dc->hwss.enable_display_power_gating(
2446                                 dc, i, bp,
2447                                 PIPE_GATING_CONTROL_INIT);
2448                 dc->hwss.enable_display_power_gating(
2449                                 dc, i, bp,
2450                                 PIPE_GATING_CONTROL_DISABLE);
2451                 dc->hwss.enable_display_pipe_clock_gating(
2452                         dc->ctx,
2453                         true);
2454         }
2455
2456         dce_clock_gating_power_up(dc->hwseq, false);
2457         /***************************************/
2458
2459         for (i = 0; i < dc->link_count; i++) {
2460                 /****************************************/
2461                 /* Power up AND update implementation according to the
2462                  * required signal (which may be different from the
2463                  * default signal on connector). */
2464                 struct dc_link *link = dc->links[i];
2465
2466                 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
2467                         dc->hwss.edp_power_control(link, true);
2468
2469                 link->link_enc->funcs->hw_init(link->link_enc);
2470         }
2471
2472         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2473                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2474
2475                 tg->funcs->disable_vga(tg);
2476
2477                 /* Blank controller using driver code instead of
2478                  * command table. */
2479                 tg->funcs->set_blank(tg, true);
2480                 hwss_wait_for_blank_complete(tg);
2481         }
2482
2483         for (i = 0; i < dc->res_pool->audio_count; i++) {
2484                 struct audio *audio = dc->res_pool->audios[i];
2485                 audio->funcs->hw_init(audio);
2486         }
2487
2488         abm = dc->res_pool->abm;
2489         if (abm != NULL) {
2490                 abm->funcs->init_backlight(abm);
2491                 abm->funcs->abm_init(abm);
2492         }
2493 #if defined(CONFIG_DRM_AMD_DC_FBC)
2494         if (dc->fbc_compressor)
2495                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2496 #endif
2497
2498 }
2499
2500 void dce110_fill_display_configs(
2501         const struct dc_state *context,
2502         struct dm_pp_display_configuration *pp_display_cfg)
2503 {
2504         int j;
2505         int num_cfgs = 0;
2506
2507         for (j = 0; j < context->stream_count; j++) {
2508                 int k;
2509
2510                 const struct dc_stream_state *stream = context->streams[j];
2511                 struct dm_pp_single_disp_config *cfg =
2512                         &pp_display_cfg->disp_configs[num_cfgs];
2513                 const struct pipe_ctx *pipe_ctx = NULL;
2514
2515                 for (k = 0; k < MAX_PIPES; k++)
2516                         if (stream == context->res_ctx.pipe_ctx[k].stream) {
2517                                 pipe_ctx = &context->res_ctx.pipe_ctx[k];
2518                                 break;
2519                         }
2520
2521                 ASSERT(pipe_ctx != NULL);
2522
2523                 /* only notify active stream */
2524                 if (stream->dpms_off)
2525                         continue;
2526
2527                 num_cfgs++;
2528                 cfg->signal = pipe_ctx->stream->signal;
2529                 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
2530                 cfg->src_height = stream->src.height;
2531                 cfg->src_width = stream->src.width;
2532                 cfg->ddi_channel_mapping =
2533                         stream->sink->link->ddi_channel_mapping.raw;
2534                 cfg->transmitter =
2535                         stream->sink->link->link_enc->transmitter;
2536                 cfg->link_settings.lane_count =
2537                         stream->sink->link->cur_link_settings.lane_count;
2538                 cfg->link_settings.link_rate =
2539                         stream->sink->link->cur_link_settings.link_rate;
2540                 cfg->link_settings.link_spread =
2541                         stream->sink->link->cur_link_settings.link_spread;
2542                 cfg->sym_clock = stream->phy_pix_clk;
2543                 /* Round v_refresh*/
2544                 cfg->v_refresh = stream->timing.pix_clk_khz * 1000;
2545                 cfg->v_refresh /= stream->timing.h_total;
2546                 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
2547                                                         / stream->timing.v_total;
2548         }
2549
2550         pp_display_cfg->display_count = num_cfgs;
2551 }
2552
2553 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
2554 {
2555         uint8_t j;
2556         uint32_t min_vertical_blank_time = -1;
2557
2558         for (j = 0; j < context->stream_count; j++) {
2559                 struct dc_stream_state *stream = context->streams[j];
2560                 uint32_t vertical_blank_in_pixels = 0;
2561                 uint32_t vertical_blank_time = 0;
2562
2563                 vertical_blank_in_pixels = stream->timing.h_total *
2564                         (stream->timing.v_total
2565                          - stream->timing.v_addressable);
2566
2567                 vertical_blank_time = vertical_blank_in_pixels
2568                         * 1000 / stream->timing.pix_clk_khz;
2569
2570                 if (min_vertical_blank_time > vertical_blank_time)
2571                         min_vertical_blank_time = vertical_blank_time;
2572         }
2573
2574         return min_vertical_blank_time;
2575 }
2576
2577 static int determine_sclk_from_bounding_box(
2578                 const struct dc *dc,
2579                 int required_sclk)
2580 {
2581         int i;
2582
2583         /*
2584          * Some asics do not give us sclk levels, so we just report the actual
2585          * required sclk
2586          */
2587         if (dc->sclk_lvls.num_levels == 0)
2588                 return required_sclk;
2589
2590         for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
2591                 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
2592                         return dc->sclk_lvls.clocks_in_khz[i];
2593         }
2594         /*
2595          * even maximum level could not satisfy requirement, this
2596          * is unexpected at this stage, should have been caught at
2597          * validation time
2598          */
2599         ASSERT(0);
2600         return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
2601 }
2602
2603 static void pplib_apply_display_requirements(
2604         struct dc *dc,
2605         struct dc_state *context)
2606 {
2607         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
2608
2609         pp_display_cfg->all_displays_in_sync =
2610                 context->bw.dce.all_displays_in_sync;
2611         pp_display_cfg->nb_pstate_switch_disable =
2612                         context->bw.dce.nbp_state_change_enable == false;
2613         pp_display_cfg->cpu_cc6_disable =
2614                         context->bw.dce.cpuc_state_change_enable == false;
2615         pp_display_cfg->cpu_pstate_disable =
2616                         context->bw.dce.cpup_state_change_enable == false;
2617         pp_display_cfg->cpu_pstate_separation_time =
2618                         context->bw.dce.blackout_recovery_time_us;
2619
2620         pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
2621                 / MEMORY_TYPE_MULTIPLIER;
2622
2623         pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
2624                         dc,
2625                         context->bw.dce.sclk_khz);
2626
2627         pp_display_cfg->min_engine_clock_deep_sleep_khz
2628                         = context->bw.dce.sclk_deep_sleep_khz;
2629
2630         pp_display_cfg->avail_mclk_switch_time_us =
2631                                                 dce110_get_min_vblank_time_us(context);
2632         /* TODO: dce11.2*/
2633         pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
2634
2635         pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz;
2636
2637         dce110_fill_display_configs(context, pp_display_cfg);
2638
2639         /* TODO: is this still applicable?*/
2640         if (pp_display_cfg->display_count == 1) {
2641                 const struct dc_crtc_timing *timing =
2642                         &context->streams[0]->timing;
2643
2644                 pp_display_cfg->crtc_index =
2645                         pp_display_cfg->disp_configs[0].pipe_idx;
2646                 pp_display_cfg->line_time_in_us = timing->h_total * 1000
2647                                                         / timing->pix_clk_khz;
2648         }
2649
2650         if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
2651                         struct dm_pp_display_configuration)) !=  0)
2652                 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
2653
2654         dc->prev_display_config = *pp_display_cfg;
2655 }
2656
2657 static void dce110_set_bandwidth(
2658                 struct dc *dc,
2659                 struct dc_state *context,
2660                 bool decrease_allowed)
2661 {
2662         dce110_set_displaymarks(dc, context);
2663
2664         if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) {
2665                 dc->res_pool->display_clock->funcs->set_clock(
2666                                 dc->res_pool->display_clock,
2667                                 context->bw.dce.dispclk_khz * 115 / 100);
2668                 dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
2669         }
2670
2671         pplib_apply_display_requirements(dc, context);
2672 }
2673
2674 static void dce110_program_front_end_for_pipe(
2675                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2676 {
2677         struct mem_input *mi = pipe_ctx->plane_res.mi;
2678         struct pipe_ctx *old_pipe = NULL;
2679         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2680         struct xfm_grph_csc_adjustment adjust;
2681         struct out_csc_color_matrix tbl_entry;
2682 #if defined(CONFIG_DRM_AMD_DC_FBC)
2683         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
2684 #endif
2685         unsigned int i;
2686         DC_LOGGER_INIT();
2687         memset(&tbl_entry, 0, sizeof(tbl_entry));
2688
2689         if (dc->current_state)
2690                 old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2691
2692         memset(&adjust, 0, sizeof(adjust));
2693         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2694
2695         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2696
2697         set_default_colors(pipe_ctx);
2698         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2699                         == true) {
2700                 tbl_entry.color_space =
2701                         pipe_ctx->stream->output_color_space;
2702
2703                 for (i = 0; i < 12; i++)
2704                         tbl_entry.regval[i] =
2705                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2706
2707                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2708                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2709         }
2710
2711         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2712                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2713
2714                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2715                         adjust.temperature_matrix[i] =
2716                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2717         }
2718
2719         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2720
2721         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2722
2723         program_scaler(dc, pipe_ctx);
2724
2725 #if defined(CONFIG_DRM_AMD_DC_FBC)
2726         /* fbc not applicable on Underlay pipe */
2727         if (dc->fbc_compressor && old_pipe->stream &&
2728             pipe_ctx->pipe_idx != underlay_idx) {
2729                 if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2730                         dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2731                 else
2732                         enable_fbc(dc, dc->current_state);
2733         }
2734 #endif
2735
2736         mi->funcs->mem_input_program_surface_config(
2737                         mi,
2738                         plane_state->format,
2739                         &plane_state->tiling_info,
2740                         &plane_state->plane_size,
2741                         plane_state->rotation,
2742                         NULL,
2743                         false);
2744         if (mi->funcs->set_blank)
2745                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2746
2747         if (dc->config.gpu_vm_support)
2748                 mi->funcs->mem_input_program_pte_vm(
2749                                 pipe_ctx->plane_res.mi,
2750                                 plane_state->format,
2751                                 &plane_state->tiling_info,
2752                                 plane_state->rotation);
2753
2754         /* Moved programming gamma from dc to hwss */
2755         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2756                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2757                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2758                 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2759
2760         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2761                 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2762
2763         DC_LOG_SURFACE(
2764                         "Pipe:%d %p: addr hi:0x%x, "
2765                         "addr low:0x%x, "
2766                         "src: %d, %d, %d,"
2767                         " %d; dst: %d, %d, %d, %d;"
2768                         "clip: %d, %d, %d, %d\n",
2769                         pipe_ctx->pipe_idx,
2770                         (void *) pipe_ctx->plane_state,
2771                         pipe_ctx->plane_state->address.grph.addr.high_part,
2772                         pipe_ctx->plane_state->address.grph.addr.low_part,
2773                         pipe_ctx->plane_state->src_rect.x,
2774                         pipe_ctx->plane_state->src_rect.y,
2775                         pipe_ctx->plane_state->src_rect.width,
2776                         pipe_ctx->plane_state->src_rect.height,
2777                         pipe_ctx->plane_state->dst_rect.x,
2778                         pipe_ctx->plane_state->dst_rect.y,
2779                         pipe_ctx->plane_state->dst_rect.width,
2780                         pipe_ctx->plane_state->dst_rect.height,
2781                         pipe_ctx->plane_state->clip_rect.x,
2782                         pipe_ctx->plane_state->clip_rect.y,
2783                         pipe_ctx->plane_state->clip_rect.width,
2784                         pipe_ctx->plane_state->clip_rect.height);
2785
2786         DC_LOG_SURFACE(
2787                         "Pipe %d: width, height, x, y\n"
2788                         "viewport:%d, %d, %d, %d\n"
2789                         "recout:  %d, %d, %d, %d\n",
2790                         pipe_ctx->pipe_idx,
2791                         pipe_ctx->plane_res.scl_data.viewport.width,
2792                         pipe_ctx->plane_res.scl_data.viewport.height,
2793                         pipe_ctx->plane_res.scl_data.viewport.x,
2794                         pipe_ctx->plane_res.scl_data.viewport.y,
2795                         pipe_ctx->plane_res.scl_data.recout.width,
2796                         pipe_ctx->plane_res.scl_data.recout.height,
2797                         pipe_ctx->plane_res.scl_data.recout.x,
2798                         pipe_ctx->plane_res.scl_data.recout.y);
2799 }
2800
2801 static void dce110_apply_ctx_for_surface(
2802                 struct dc *dc,
2803                 const struct dc_stream_state *stream,
2804                 int num_planes,
2805                 struct dc_state *context)
2806 {
2807         int i;
2808
2809         if (num_planes == 0)
2810                 return;
2811
2812         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2813                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2814                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2815
2816                 if (stream == pipe_ctx->stream) {
2817                         if (!pipe_ctx->top_pipe &&
2818                                 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2819                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
2820                 }
2821         }
2822
2823         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2824                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2825
2826                 if (pipe_ctx->stream != stream)
2827                         continue;
2828
2829                 /* Need to allocate mem before program front end for Fiji */
2830                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2831                                 pipe_ctx->plane_res.mi,
2832                                 pipe_ctx->stream->timing.h_total,
2833                                 pipe_ctx->stream->timing.v_total,
2834                                 pipe_ctx->stream->timing.pix_clk_khz,
2835                                 context->stream_count);
2836
2837                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2838
2839                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2840
2841                 program_surface_visibility(dc, pipe_ctx);
2842
2843         }
2844
2845         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2846                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2847                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2848
2849                 if ((stream == pipe_ctx->stream) &&
2850                         (!pipe_ctx->top_pipe) &&
2851                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2852                         dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
2853         }
2854 }
2855
2856 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2857 {
2858         int fe_idx = pipe_ctx->plane_res.mi ?
2859                 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2860
2861         /* Do not power down fe when stream is active on dce*/
2862         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2863                 return;
2864
2865         dc->hwss.enable_display_power_gating(
2866                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2867
2868         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2869                                 dc->res_pool->transforms[fe_idx]);
2870 }
2871
2872 static void dce110_wait_for_mpcc_disconnect(
2873                 struct dc *dc,
2874                 struct resource_pool *res_pool,
2875                 struct pipe_ctx *pipe_ctx)
2876 {
2877         /* do nothing*/
2878 }
2879
2880 static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
2881                 enum dc_color_space colorspace,
2882                 uint16_t *matrix)
2883 {
2884         int i;
2885         struct out_csc_color_matrix tbl_entry;
2886
2887         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2888                                 == true) {
2889                         enum dc_color_space color_space =
2890                                 pipe_ctx->stream->output_color_space;
2891
2892                         //uint16_t matrix[12];
2893                         for (i = 0; i < 12; i++)
2894                                 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2895
2896                         tbl_entry.color_space = color_space;
2897                         //tbl_entry.regval = matrix;
2898                         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry);
2899         }
2900 }
2901
2902 void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2903 {
2904         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2905         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2906         struct mem_input *mi = pipe_ctx->plane_res.mi;
2907         struct dc_cursor_mi_param param = {
2908                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
2909                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
2910                 .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
2911                 .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
2912                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
2913         };
2914
2915         if (pipe_ctx->plane_state->address.type
2916                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2917                 pos_cpy.enable = false;
2918
2919         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2920                 pos_cpy.enable = false;
2921
2922         if (ipp->funcs->ipp_cursor_set_position)
2923                 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2924         if (mi->funcs->set_cursor_position)
2925                 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2926 }
2927
2928 void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2929 {
2930         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2931
2932         if (pipe_ctx->plane_res.ipp &&
2933             pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2934                 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2935                                 pipe_ctx->plane_res.ipp, attributes);
2936
2937         if (pipe_ctx->plane_res.mi &&
2938             pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2939                 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2940                                 pipe_ctx->plane_res.mi, attributes);
2941
2942         if (pipe_ctx->plane_res.xfm &&
2943             pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2944                 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2945                                 pipe_ctx->plane_res.xfm, attributes);
2946 }
2947
2948 static void ready_shared_resources(struct dc *dc, struct dc_state *context) {}
2949
2950 static void optimize_shared_resources(struct dc *dc) {}
2951
2952 static const struct hw_sequencer_funcs dce110_funcs = {
2953         .program_gamut_remap = program_gamut_remap,
2954         .program_csc_matrix = program_csc_matrix,
2955         .init_hw = init_hw,
2956         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2957         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2958         .update_plane_addr = update_plane_addr,
2959         .update_pending_status = dce110_update_pending_status,
2960         .set_input_transfer_func = dce110_set_input_transfer_func,
2961         .set_output_transfer_func = dce110_set_output_transfer_func,
2962         .power_down = dce110_power_down,
2963         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2964         .enable_timing_synchronization = dce110_enable_timing_synchronization,
2965         .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
2966         .update_info_frame = dce110_update_info_frame,
2967         .enable_stream = dce110_enable_stream,
2968         .disable_stream = dce110_disable_stream,
2969         .unblank_stream = dce110_unblank_stream,
2970         .blank_stream = dce110_blank_stream,
2971         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2972         .enable_display_power_gating = dce110_enable_display_power_gating,
2973         .disable_plane = dce110_power_down_fe,
2974         .pipe_control_lock = dce_pipe_control_lock,
2975         .set_bandwidth = dce110_set_bandwidth,
2976         .set_drr = set_drr,
2977         .get_position = get_position,
2978         .set_static_screen_control = set_static_screen_control,
2979         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2980         .enable_stream_timing = dce110_enable_stream_timing,
2981         .setup_stereo = NULL,
2982         .set_avmute = dce110_set_avmute,
2983         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
2984         .ready_shared_resources = ready_shared_resources,
2985         .optimize_shared_resources = optimize_shared_resources,
2986         .pplib_apply_display_requirements = pplib_apply_display_requirements,
2987         .edp_backlight_control = hwss_edp_backlight_control,
2988         .edp_power_control = hwss_edp_power_control,
2989         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2990         .set_cursor_position = dce110_set_cursor_position,
2991         .set_cursor_attribute = dce110_set_cursor_attribute
2992 };
2993
2994 void dce110_hw_sequencer_construct(struct dc *dc)
2995 {
2996         dc->hwss = dce110_funcs;
2997 }
2998