2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/delay.h>
28 #include "dm_services.h"
30 #include "dc_bios_types.h"
31 #include "core_types.h"
32 #include "core_status.h"
34 #include "dm_helpers.h"
35 #include "dce110_hw_sequencer.h"
36 #include "dce110_timing_generator.h"
37 #include "dce/dce_hwseq.h"
38 #include "gpio_service_interface.h"
40 #include "dce110_compressor.h"
42 #include "bios/bios_parser_helper.h"
43 #include "timing_generator.h"
44 #include "mem_input.h"
47 #include "transform.h"
48 #include "stream_encoder.h"
49 #include "link_encoder.h"
50 #include "link_hwss.h"
51 #include "clock_source.h"
55 #include "reg_helper.h"
57 /* include DCE11 register header files */
58 #include "dce/dce_11_0_d.h"
59 #include "dce/dce_11_0_sh_mask.h"
60 #include "custom_float.h"
62 #include "atomfirmware.h"
65 * All values are in milliseconds;
66 * For eDP, after power-up/power/down,
67 * 300/500 msec max. delay from LCDVCC to black video generation
69 #define PANEL_POWER_UP_TIMEOUT 300
70 #define PANEL_POWER_DOWN_TIMEOUT 500
71 #define HPD_CHECK_INTERVAL 10
76 #define DC_LOGGER_INIT()
82 #define FN(reg_name, field_name) \
83 hws->shifts->field_name, hws->masks->field_name
85 struct dce110_hw_seq_reg_offsets {
89 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
91 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
94 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
97 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
100 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
104 #define HW_REG_BLND(reg, id)\
105 (reg + reg_offsets[id].blnd)
107 #define HW_REG_CRTC(reg, id)\
108 (reg + reg_offsets[id].crtc)
110 #define MAX_WATERMARK 0xFFFF
111 #define SAFE_NBP_MARK 0x7FFF
113 /*******************************************************************************
114 * Private definitions
115 ******************************************************************************/
116 /***************************PIPE_CONTROL***********************************/
117 static void dce110_init_pte(struct dc_context *ctx)
121 uint32_t chunk_int = 0;
122 uint32_t chunk_mul = 0;
124 addr = mmUNP_DVMM_PTE_CONTROL;
125 value = dm_read_reg(ctx, addr);
131 DVMM_USE_SINGLE_PTE);
137 DVMM_PTE_BUFFER_MODE0);
143 DVMM_PTE_BUFFER_MODE1);
145 dm_write_reg(ctx, addr, value);
147 addr = mmDVMM_PTE_REQ;
148 value = dm_read_reg(ctx, addr);
150 chunk_int = get_reg_field_value(
153 HFLIP_PTEREQ_PER_CHUNK_INT);
155 chunk_mul = get_reg_field_value(
158 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
160 if (chunk_int != 0x4 || chunk_mul != 0x4) {
166 MAX_PTEREQ_TO_ISSUE);
172 HFLIP_PTEREQ_PER_CHUNK_INT);
178 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
180 dm_write_reg(ctx, addr, value);
183 /**************************************************************************/
185 static void enable_display_pipe_clock_gating(
186 struct dc_context *ctx,
192 static bool dce110_enable_display_power_gating(
194 uint8_t controller_id,
196 enum pipe_gating_control power_gating)
198 enum bp_result bp_result = BP_RESULT_OK;
199 enum bp_pipe_control_action cntl;
200 struct dc_context *ctx = dc->ctx;
201 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
203 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
206 if (power_gating == PIPE_GATING_CONTROL_INIT)
207 cntl = ASIC_PIPE_INIT;
208 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
209 cntl = ASIC_PIPE_ENABLE;
211 cntl = ASIC_PIPE_DISABLE;
213 if (controller_id == underlay_idx)
214 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
216 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
218 bp_result = dcb->funcs->enable_disp_power_gating(
219 dcb, controller_id + 1, cntl);
221 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
222 * by default when command table is called
224 * Bios parser accepts controller_id = 6 as indicative of
225 * underlay pipe in dce110. But we do not support more
228 if (controller_id < CONTROLLER_ID_MAX - 1)
230 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
234 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
235 dce110_init_pte(ctx);
237 if (bp_result == BP_RESULT_OK)
243 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
244 const struct dc_plane_state *plane_state)
246 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
248 switch (plane_state->format) {
249 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
250 prescale_params->scale = 0x2082;
252 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
253 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
254 prescale_params->scale = 0x2020;
256 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
257 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
258 prescale_params->scale = 0x2008;
260 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
261 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
262 prescale_params->scale = 0x2000;
271 dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
272 const struct dc_plane_state *plane_state)
274 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
275 const struct dc_transfer_func *tf = NULL;
276 struct ipp_prescale_params prescale_params = { 0 };
282 if (plane_state->in_transfer_func)
283 tf = plane_state->in_transfer_func;
285 build_prescale_params(&prescale_params, plane_state);
286 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
288 if (plane_state->gamma_correction &&
289 !plane_state->gamma_correction->is_identity &&
290 dce_use_lut(plane_state->format))
291 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
294 /* Default case if no input transfer function specified */
295 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
296 } else if (tf->type == TF_TYPE_PREDEFINED) {
298 case TRANSFER_FUNCTION_SRGB:
299 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
301 case TRANSFER_FUNCTION_BT709:
302 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
304 case TRANSFER_FUNCTION_LINEAR:
305 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
307 case TRANSFER_FUNCTION_PQ:
312 } else if (tf->type == TF_TYPE_BYPASS) {
313 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
315 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
322 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
323 struct curve_points *arr_points,
324 uint32_t hw_points_num)
326 struct custom_float_format fmt;
328 struct pwl_result_data *rgb = rgb_resulted;
332 fmt.exponenta_bits = 6;
333 fmt.mantissa_bits = 12;
336 if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
337 &arr_points[0].custom_float_x)) {
342 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
343 &arr_points[0].custom_float_offset)) {
348 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
349 &arr_points[0].custom_float_slope)) {
354 fmt.mantissa_bits = 10;
357 if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
358 &arr_points[1].custom_float_x)) {
363 if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
364 &arr_points[1].custom_float_y)) {
369 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
370 &arr_points[1].custom_float_slope)) {
375 fmt.mantissa_bits = 12;
378 while (i != hw_points_num) {
379 if (!convert_to_custom_float_format(rgb->red, &fmt,
385 if (!convert_to_custom_float_format(rgb->green, &fmt,
391 if (!convert_to_custom_float_format(rgb->blue, &fmt,
397 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
398 &rgb->delta_red_reg)) {
403 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
404 &rgb->delta_green_reg)) {
409 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
410 &rgb->delta_blue_reg)) {
422 #define MAX_LOW_POINT 25
423 #define NUMBER_REGIONS 16
424 #define NUMBER_SW_SEGMENTS 16
427 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
428 struct pwl_params *regamma_params)
430 struct curve_points *arr_points;
431 struct pwl_result_data *rgb_resulted;
432 struct pwl_result_data *rgb;
433 struct pwl_result_data *rgb_plus_1;
434 struct fixed31_32 y_r;
435 struct fixed31_32 y_g;
436 struct fixed31_32 y_b;
437 struct fixed31_32 y1_min;
438 struct fixed31_32 y3_max;
440 int32_t region_start, region_end;
441 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
443 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
446 arr_points = regamma_params->arr_points;
447 rgb_resulted = regamma_params->rgb_resulted;
450 memset(regamma_params, 0, sizeof(struct pwl_params));
452 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
454 * segments are from 2^-11 to 2^5
457 region_end = region_start + NUMBER_REGIONS;
459 for (i = 0; i < NUMBER_REGIONS; i++)
464 * segment is from 2^-10 to 2^1
465 * We include an extra segment for range [2^0, 2^1). This is to
466 * ensure that colors with normalized values of 1 don't miss the
490 for (k = 0; k < 16; k++) {
491 if (seg_distr[k] != -1)
492 hw_points += (1 << seg_distr[k]);
496 for (k = 0; k < (region_end - region_start); k++) {
497 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
498 start_index = (region_start + k + MAX_LOW_POINT) *
500 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
502 if (j == hw_points - 1)
504 rgb_resulted[j].red = output_tf->tf_pts.red[i];
505 rgb_resulted[j].green = output_tf->tf_pts.green[i];
506 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
512 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
513 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
514 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
515 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
517 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
518 dc_fixpt_from_int(region_start));
519 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
520 dc_fixpt_from_int(region_end));
522 y_r = rgb_resulted[0].red;
523 y_g = rgb_resulted[0].green;
524 y_b = rgb_resulted[0].blue;
526 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
528 arr_points[0].y = y1_min;
529 arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
532 y_r = rgb_resulted[hw_points - 1].red;
533 y_g = rgb_resulted[hw_points - 1].green;
534 y_b = rgb_resulted[hw_points - 1].blue;
536 /* see comment above, m_arrPoints[1].y should be the Y value for the
537 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
539 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
541 arr_points[1].y = y3_max;
543 arr_points[1].slope = dc_fixpt_zero;
545 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
546 /* for PQ, we want to have a straight line from last HW X point,
547 * and the slope to be such that we hit 1.0 at 10000 nits.
549 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
551 arr_points[1].slope = dc_fixpt_div(
552 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
553 dc_fixpt_sub(end_value, arr_points[1].x));
556 regamma_params->hw_points_num = hw_points;
559 for (i = 1; i < 16; i++) {
560 if (seg_distr[k] != -1) {
561 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
562 regamma_params->arr_curve_points[i].offset =
563 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
568 if (seg_distr[k] != -1)
569 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
572 rgb_plus_1 = rgb_resulted + 1;
576 while (i != hw_points + 1) {
577 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
578 rgb_plus_1->red = rgb->red;
579 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
580 rgb_plus_1->green = rgb->green;
581 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
582 rgb_plus_1->blue = rgb->blue;
584 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
585 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
586 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
593 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
599 dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
600 const struct dc_stream_state *stream)
602 struct transform *xfm = pipe_ctx->plane_res.xfm;
604 xfm->funcs->opp_power_on_regamma_lut(xfm, true);
605 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
607 if (stream->out_transfer_func &&
608 stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
609 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
610 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
611 } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
612 &xfm->regamma_params)) {
613 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
614 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
616 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
619 xfm->funcs->opp_power_on_regamma_lut(xfm, false);
624 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
629 ASSERT(pipe_ctx->stream);
631 if (pipe_ctx->stream_res.stream_enc == NULL)
632 return; /* this is not root pipe */
634 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
635 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
637 if (!is_hdmi_tmds && !is_dp)
641 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
642 pipe_ctx->stream_res.stream_enc,
643 &pipe_ctx->stream_res.encoder_info_frame);
645 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
646 pipe_ctx->stream_res.stream_enc,
647 &pipe_ctx->stream_res.encoder_info_frame);
650 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
652 enum dc_lane_count lane_count =
653 pipe_ctx->stream->link->cur_link_settings.lane_count;
655 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
656 struct dc_link *link = pipe_ctx->stream->link;
659 uint32_t active_total_with_borders;
660 uint32_t early_control = 0;
661 struct timing_generator *tg = pipe_ctx->stream_res.tg;
663 /* For MST, there are multiply stream go to only one link.
664 * connect DIG back_end to front_end while enable_stream and
665 * disconnect them during disable_stream
666 * BY this, it is logic clean to separate stream and link */
667 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
668 pipe_ctx->stream_res.stream_enc->id, true);
670 /* update AVI info frame (HDMI, DP)*/
671 /* TODO: FPGA may change to hwss.update_info_frame */
673 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
674 if (pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL &&
675 pipe_ctx->plane_res.hubp != NULL) {
676 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
677 /* if using dynamic meta, don't set up generic infopackets */
678 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
679 pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(
680 pipe_ctx->stream_res.stream_enc,
681 true, pipe_ctx->plane_res.hubp->inst,
682 dc_is_dp_signal(pipe_ctx->stream->signal) ?
683 dmdata_dp : dmdata_hdmi);
685 pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(
686 pipe_ctx->stream_res.stream_enc,
687 false, pipe_ctx->plane_res.hubp->inst,
688 dc_is_dp_signal(pipe_ctx->stream->signal) ?
689 dmdata_dp : dmdata_hdmi);
692 dce110_update_info_frame(pipe_ctx);
694 /* enable early control to avoid corruption on DP monitor*/
695 active_total_with_borders =
696 timing->h_addressable
697 + timing->h_border_left
698 + timing->h_border_right;
701 early_control = active_total_with_borders % lane_count;
703 if (early_control == 0)
704 early_control = lane_count;
706 tg->funcs->set_early_control(tg, early_control);
708 /* enable audio only within mode set */
709 if (pipe_ctx->stream_res.audio != NULL) {
710 if (dc_is_dp_signal(pipe_ctx->stream->signal))
711 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
719 /*todo: cloned in stream enc, fix*/
720 static bool is_panel_backlight_on(struct dce_hwseq *hws)
724 REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
729 static bool is_panel_powered_on(struct dce_hwseq *hws)
731 uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
734 REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
736 REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
738 return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
741 static enum bp_result link_transmitter_control(
742 struct dc_bios *bios,
743 struct bp_transmitter_control *cntl)
745 enum bp_result result;
747 result = bios->funcs->transmitter_control(bios, cntl);
756 void hwss_edp_wait_for_hpd_ready(
757 struct dc_link *link,
760 struct dc_context *ctx = link->ctx;
761 struct graphics_object_id connector = link->link_enc->connector;
763 bool edp_hpd_high = false;
764 uint32_t time_elapsed = 0;
765 uint32_t timeout = power_up ?
766 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
768 if (dal_graphics_object_id_get_connector_id(connector)
769 != CONNECTOR_ID_EDP) {
776 * From KV, we will not HPD low after turning off VCC -
777 * instead, we will check the SW timer in power_up().
782 * When we power on/off the eDP panel,
783 * we need to wait until SENSE bit is high/low.
787 /* TODO what to do with this? */
788 hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
795 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
797 /* wait until timeout or panel detected */
800 uint32_t detected = 0;
802 dal_gpio_get_value(hpd, &detected);
804 if (!(detected ^ power_up)) {
809 msleep(HPD_CHECK_INTERVAL);
811 time_elapsed += HPD_CHECK_INTERVAL;
812 } while (time_elapsed < timeout);
816 dal_gpio_destroy_irq(&hpd);
818 if (false == edp_hpd_high) {
820 "%s: wait timed out!\n", __func__);
824 void hwss_edp_power_control(
825 struct dc_link *link,
828 struct dc_context *ctx = link->ctx;
829 struct dce_hwseq *hwseq = ctx->dc->hwseq;
830 struct bp_transmitter_control cntl = { 0 };
831 enum bp_result bp_result;
834 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
835 != CONNECTOR_ID_EDP) {
840 if (power_up != is_panel_powered_on(hwseq)) {
841 /* Send VBIOS command to prompt eDP panel power */
843 unsigned long long current_ts = dm_get_timestamp(ctx);
844 unsigned long long duration_in_ms =
845 div64_u64(dm_get_elapse_time_in_ns(
848 link->link_trace.time_stamp.edp_poweroff), 1000000);
849 unsigned long long wait_time_ms = 0;
851 /* max 500ms from LCDVDD off to on */
852 unsigned long long edp_poweroff_time_ms = 500;
854 if (link->local_sink != NULL)
855 edp_poweroff_time_ms =
856 500 + link->local_sink->edid_caps.panel_patch.extra_t12_ms;
857 if (link->link_trace.time_stamp.edp_poweroff == 0)
858 wait_time_ms = edp_poweroff_time_ms;
859 else if (duration_in_ms < edp_poweroff_time_ms)
860 wait_time_ms = edp_poweroff_time_ms - duration_in_ms;
863 msleep(wait_time_ms);
864 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
865 __func__, wait_time_ms);
871 "%s: Panel Power action: %s\n",
872 __func__, (power_up ? "On":"Off"));
874 cntl.action = power_up ?
875 TRANSMITTER_CONTROL_POWER_ON :
876 TRANSMITTER_CONTROL_POWER_OFF;
877 cntl.transmitter = link->link_enc->transmitter;
878 cntl.connector_obj_id = link->link_enc->connector;
879 cntl.coherent = false;
880 cntl.lanes_number = LANE_COUNT_FOUR;
881 cntl.hpd_sel = link->link_enc->hpd_source;
882 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
885 /*save driver power off time stamp*/
886 link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
888 link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
890 if (bp_result != BP_RESULT_OK)
892 "%s: Panel Power bp_result: %d\n",
893 __func__, bp_result);
896 "%s: Skipping Panel Power action: %s\n",
897 __func__, (power_up ? "On":"Off"));
901 /*todo: cloned in stream enc, fix*/
904 * eDP only. Control the backlight of the eDP panel
906 void hwss_edp_backlight_control(
907 struct dc_link *link,
910 struct dc_context *ctx = link->ctx;
911 struct dce_hwseq *hws = ctx->dc->hwseq;
912 struct bp_transmitter_control cntl = { 0 };
914 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
915 != CONNECTOR_ID_EDP) {
920 if (enable && is_panel_backlight_on(hws)) {
922 "%s: panel already powered up. Do nothing.\n",
927 /* Send VBIOS command to control eDP panel backlight */
930 "%s: backlight action: %s\n",
931 __func__, (enable ? "On":"Off"));
933 cntl.action = enable ?
934 TRANSMITTER_CONTROL_BACKLIGHT_ON :
935 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
937 /*cntl.engine_id = ctx->engine;*/
938 cntl.transmitter = link->link_enc->transmitter;
939 cntl.connector_obj_id = link->link_enc->connector;
941 cntl.lanes_number = LANE_COUNT_FOUR;
942 cntl.hpd_sel = link->link_enc->hpd_source;
943 cntl.signal = SIGNAL_TYPE_EDP;
945 /* For eDP, the following delays might need to be considered
946 * after link training completed:
947 * idle period - min. accounts for required BS-Idle pattern,
948 * max. allows for source frame synchronization);
949 * 50 msec max. delay from valid video data from source
950 * to video on dislpay or backlight enable.
952 * Disable the delay for now.
953 * Enable it in the future if necessary.
955 /* dc_service_sleep_in_milliseconds(50); */
957 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
958 edp_receiver_ready_T7(link);
959 link_transmitter_control(ctx->dc_bios, &cntl);
961 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
962 edp_receiver_ready_T9(link);
965 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
967 /* notify audio driver for audio modes of monitor */
968 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
969 struct pp_smu_funcs *pp_smu = NULL;
970 struct clk_mgr *clk_mgr = core_dc->clk_mgr;
971 unsigned int i, num_audio = 1;
973 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
976 if (core_dc->res_pool->pp_smu)
977 pp_smu = core_dc->res_pool->pp_smu;
979 if (pipe_ctx->stream_res.audio) {
980 for (i = 0; i < MAX_PIPES; i++) {
981 /*current_state not updated yet*/
982 if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
986 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
988 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
989 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
990 clk_mgr->funcs->enable_pme_wa(clk_mgr);
992 /* TODO: audio should be per stream rather than per link */
993 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
994 pipe_ctx->stream_res.stream_enc, false);
995 if (pipe_ctx->stream_res.audio)
996 pipe_ctx->stream_res.audio->enabled = true;
1000 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
1002 struct dc *dc = pipe_ctx->stream->ctx->dc;
1003 struct pp_smu_funcs *pp_smu = NULL;
1004 struct clk_mgr *clk_mgr = dc->clk_mgr;
1006 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1009 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1010 pipe_ctx->stream_res.stream_enc, true);
1011 if (pipe_ctx->stream_res.audio) {
1012 if (dc->res_pool->pp_smu)
1013 pp_smu = dc->res_pool->pp_smu;
1015 if (option != KEEP_ACQUIRED_RESOURCE ||
1016 !dc->debug.az_endpoint_mute_only)
1017 /*only disalbe az_endpoint if power down or free*/
1018 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
1020 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1021 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1022 pipe_ctx->stream_res.stream_enc);
1024 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1025 pipe_ctx->stream_res.stream_enc);
1026 /*don't free audio if it is from retrain or internal disable stream*/
1027 if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
1028 /*we have to dynamic arbitrate the audio endpoints*/
1029 /*we free the resource, need reset is_audio_acquired*/
1030 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
1031 pipe_ctx->stream_res.audio = NULL;
1033 if (clk_mgr->funcs->enable_pme_wa)
1034 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1035 clk_mgr->funcs->enable_pme_wa(clk_mgr);
1037 /* TODO: notify audio driver for if audio modes list changed
1038 * add audio mode list change flag */
1039 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1040 * stream->stream_engine_id);
1042 if (pipe_ctx->stream_res.audio)
1043 pipe_ctx->stream_res.audio->enabled = false;
1047 void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
1049 struct dc_stream_state *stream = pipe_ctx->stream;
1050 struct dc_link *link = stream->link;
1051 struct dc *dc = pipe_ctx->stream->ctx->dc;
1053 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
1054 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1055 pipe_ctx->stream_res.stream_enc);
1057 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1058 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1059 pipe_ctx->stream_res.stream_enc);
1061 dc->hwss.disable_audio_stream(pipe_ctx, option);
1063 link->link_enc->funcs->connect_dig_be_to_fe(
1065 pipe_ctx->stream_res.stream_enc->id,
1070 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1071 struct dc_link_settings *link_settings)
1073 struct encoder_unblank_param params = { { 0 } };
1074 struct dc_stream_state *stream = pipe_ctx->stream;
1075 struct dc_link *link = stream->link;
1077 /* only 3 items below are used by unblank */
1078 params.timing = pipe_ctx->stream->timing;
1079 params.link_settings.link_rate = link_settings->link_rate;
1081 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1082 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
1084 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1085 link->dc->hwss.edp_backlight_control(link, true);
1089 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1091 struct dc_stream_state *stream = pipe_ctx->stream;
1092 struct dc_link *link = stream->link;
1094 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1095 link->dc->hwss.edp_backlight_control(link, false);
1096 dc_link_set_abm_disable(link);
1099 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1100 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1104 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1106 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1107 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1110 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1113 case CONTROLLER_ID_D0:
1114 return DTO_SOURCE_ID0;
1115 case CONTROLLER_ID_D1:
1116 return DTO_SOURCE_ID1;
1117 case CONTROLLER_ID_D2:
1118 return DTO_SOURCE_ID2;
1119 case CONTROLLER_ID_D3:
1120 return DTO_SOURCE_ID3;
1121 case CONTROLLER_ID_D4:
1122 return DTO_SOURCE_ID4;
1123 case CONTROLLER_ID_D5:
1124 return DTO_SOURCE_ID5;
1126 return DTO_SOURCE_UNKNOWN;
1130 static void build_audio_output(
1131 struct dc_state *state,
1132 const struct pipe_ctx *pipe_ctx,
1133 struct audio_output *audio_output)
1135 const struct dc_stream_state *stream = pipe_ctx->stream;
1136 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1138 audio_output->signal = pipe_ctx->stream->signal;
1140 /* audio_crtc_info */
1142 audio_output->crtc_info.h_total =
1143 stream->timing.h_total;
1146 * Audio packets are sent during actual CRTC blank physical signal, we
1147 * need to specify actual active signal portion
1149 audio_output->crtc_info.h_active =
1150 stream->timing.h_addressable
1151 + stream->timing.h_border_left
1152 + stream->timing.h_border_right;
1154 audio_output->crtc_info.v_active =
1155 stream->timing.v_addressable
1156 + stream->timing.v_border_top
1157 + stream->timing.v_border_bottom;
1159 audio_output->crtc_info.pixel_repetition = 1;
1161 audio_output->crtc_info.interlaced =
1162 stream->timing.flags.INTERLACE;
1164 audio_output->crtc_info.refresh_rate =
1165 (stream->timing.pix_clk_100hz*10000)/
1166 (stream->timing.h_total*stream->timing.v_total);
1168 audio_output->crtc_info.color_depth =
1169 stream->timing.display_color_depth;
1171 audio_output->crtc_info.requested_pixel_clock =
1172 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
1174 audio_output->crtc_info.calculated_pixel_clock =
1175 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
1177 /*for HDMI, audio ACR is with deep color ratio factor*/
1178 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
1179 audio_output->crtc_info.requested_pixel_clock ==
1180 (stream->timing.pix_clk_100hz / 10)) {
1181 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1182 audio_output->crtc_info.requested_pixel_clock =
1183 audio_output->crtc_info.requested_pixel_clock/2;
1184 audio_output->crtc_info.calculated_pixel_clock =
1185 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/20;
1190 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1191 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1192 audio_output->pll_info.dp_dto_source_clock_in_khz =
1193 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1197 audio_output->pll_info.feed_back_divider =
1198 pipe_ctx->pll_settings.feedback_divider;
1200 audio_output->pll_info.dto_source =
1201 translate_to_dto_source(
1202 pipe_ctx->stream_res.tg->inst + 1);
1204 /* TODO hard code to enable for now. Need get from stream */
1205 audio_output->pll_info.ss_enabled = true;
1207 audio_output->pll_info.ss_percentage =
1208 pipe_ctx->pll_settings.ss_percentage;
1211 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1212 struct tg_color *color)
1214 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
1216 switch (pipe_ctx->plane_res.scl_data.format) {
1217 case PIXEL_FORMAT_ARGB8888:
1218 /* set boarder color to red */
1219 color->color_r_cr = color_value;
1222 case PIXEL_FORMAT_ARGB2101010:
1223 /* set boarder color to blue */
1224 color->color_b_cb = color_value;
1226 case PIXEL_FORMAT_420BPP8:
1227 /* set boarder color to green */
1228 color->color_g_y = color_value;
1230 case PIXEL_FORMAT_420BPP10:
1231 /* set boarder color to yellow */
1232 color->color_g_y = color_value;
1233 color->color_r_cr = color_value;
1235 case PIXEL_FORMAT_FP16:
1236 /* set boarder color to white */
1237 color->color_r_cr = color_value;
1238 color->color_b_cb = color_value;
1239 color->color_g_y = color_value;
1246 static void program_scaler(const struct dc *dc,
1247 const struct pipe_ctx *pipe_ctx)
1249 struct tg_color color = {0};
1251 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1253 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1257 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1258 get_surface_visual_confirm_color(pipe_ctx, &color);
1260 color_space_to_black_color(dc,
1261 pipe_ctx->stream->output_color_space,
1264 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1265 pipe_ctx->plane_res.xfm,
1266 pipe_ctx->plane_res.scl_data.lb_params.depth,
1267 &pipe_ctx->stream->bit_depth_params);
1269 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1271 * The way 420 is packed, 2 channels carry Y component, 1 channel
1272 * alternate between Cb and Cr, so both channels need the pixel
1275 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1276 color.color_r_cr = color.color_g_y;
1278 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1279 pipe_ctx->stream_res.tg,
1283 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1284 &pipe_ctx->plane_res.scl_data);
1287 static enum dc_status dce110_enable_stream_timing(
1288 struct pipe_ctx *pipe_ctx,
1289 struct dc_state *context,
1292 struct dc_stream_state *stream = pipe_ctx->stream;
1293 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1294 pipe_ctx[pipe_ctx->pipe_idx];
1295 struct tg_color black_color = {0};
1297 if (!pipe_ctx_old->stream) {
1299 /* program blank color */
1300 color_space_to_black_color(dc,
1301 stream->output_color_space, &black_color);
1302 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1303 pipe_ctx->stream_res.tg,
1307 * Must blank CRTC after disabling power gating and before any
1308 * programming, otherwise CRTC will be hung in bad state
1310 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1312 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1313 pipe_ctx->clock_source,
1314 &pipe_ctx->stream_res.pix_clk_params,
1315 &pipe_ctx->pll_settings)) {
1316 BREAK_TO_DEBUGGER();
1317 return DC_ERROR_UNEXPECTED;
1320 pipe_ctx->stream_res.tg->funcs->program_timing(
1321 pipe_ctx->stream_res.tg,
1327 pipe_ctx->stream->signal,
1331 if (!pipe_ctx_old->stream) {
1332 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1333 pipe_ctx->stream_res.tg)) {
1334 BREAK_TO_DEBUGGER();
1335 return DC_ERROR_UNEXPECTED;
1342 static enum dc_status apply_single_controller_ctx_to_hw(
1343 struct pipe_ctx *pipe_ctx,
1344 struct dc_state *context,
1347 struct dc_stream_state *stream = pipe_ctx->stream;
1348 struct drr_params params = {0};
1349 unsigned int event_triggers = 0;
1350 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
1351 struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
1354 if (dc->hwss.disable_stream_gating) {
1355 dc->hwss.disable_stream_gating(dc, pipe_ctx);
1358 if (pipe_ctx->stream_res.audio != NULL) {
1359 struct audio_output audio_output;
1361 build_audio_output(context, pipe_ctx, &audio_output);
1363 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1364 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1365 pipe_ctx->stream_res.stream_enc,
1366 pipe_ctx->stream_res.audio->inst,
1367 &pipe_ctx->stream->audio_info);
1369 pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1370 pipe_ctx->stream_res.stream_enc,
1371 pipe_ctx->stream_res.audio->inst,
1372 &pipe_ctx->stream->audio_info,
1373 &audio_output.crtc_info);
1375 pipe_ctx->stream_res.audio->funcs->az_configure(
1376 pipe_ctx->stream_res.audio,
1377 pipe_ctx->stream->signal,
1378 &audio_output.crtc_info,
1379 &pipe_ctx->stream->audio_info);
1383 /* Do not touch stream timing on seamless boot optimization. */
1384 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1385 dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
1387 if (dc->hwss.setup_vupdate_interrupt)
1388 dc->hwss.setup_vupdate_interrupt(pipe_ctx);
1390 params.vertical_total_min = stream->adjust.v_total_min;
1391 params.vertical_total_max = stream->adjust.v_total_max;
1392 if (pipe_ctx->stream_res.tg->funcs->set_drr)
1393 pipe_ctx->stream_res.tg->funcs->set_drr(
1394 pipe_ctx->stream_res.tg, ¶ms);
1396 // DRR should set trigger event to monitor surface update event
1397 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1398 event_triggers = 0x80;
1399 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1400 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1401 pipe_ctx->stream_res.tg, event_triggers);
1403 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1404 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1405 pipe_ctx->stream_res.stream_enc,
1406 pipe_ctx->stream_res.tg->inst);
1408 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1409 pipe_ctx->stream_res.opp,
1410 COLOR_SPACE_YCBCR601,
1411 stream->timing.display_color_depth,
1414 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1415 pipe_ctx->stream_res.opp,
1416 &stream->bit_depth_params,
1418 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
1420 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1421 odm_pipe->stream_res.opp,
1422 COLOR_SPACE_YCBCR601,
1423 stream->timing.display_color_depth,
1426 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1427 odm_pipe->stream_res.opp,
1428 &stream->bit_depth_params,
1433 if (!stream->dpms_off)
1434 core_link_enable_stream(context, pipe_ctx);
1436 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1438 pipe_ctx->stream->link->psr_enabled = false;
1443 /******************************************************************************/
1445 static void power_down_encoders(struct dc *dc)
1448 enum connector_id connector_id;
1449 enum signal_type signal = SIGNAL_TYPE_NONE;
1451 /* do not know BIOS back-front mapping, simply blank all. It will not
1454 for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1455 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1456 dc->res_pool->stream_enc[i]);
1459 for (i = 0; i < dc->link_count; i++) {
1460 connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
1461 if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
1462 (connector_id == CONNECTOR_ID_EDP)) {
1464 if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1465 dp_receiver_power_ctrl(dc->links[i], false);
1466 if (connector_id == CONNECTOR_ID_EDP)
1467 signal = SIGNAL_TYPE_EDP;
1470 dc->links[i]->link_enc->funcs->disable_output(
1471 dc->links[i]->link_enc, signal);
1475 static void power_down_controllers(struct dc *dc)
1479 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1480 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1481 dc->res_pool->timing_generators[i]);
1485 static void power_down_clock_sources(struct dc *dc)
1489 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1490 dc->res_pool->dp_clock_source) == false)
1491 dm_error("Failed to power down pll! (dp clk src)\n");
1493 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1494 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1495 dc->res_pool->clock_sources[i]) == false)
1496 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1500 static void power_down_all_hw_blocks(struct dc *dc)
1502 power_down_encoders(dc);
1504 power_down_controllers(dc);
1506 power_down_clock_sources(dc);
1508 if (dc->fbc_compressor)
1509 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1512 static void disable_vga_and_power_gate_all_controllers(
1516 struct timing_generator *tg;
1517 struct dc_context *ctx = dc->ctx;
1519 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1520 tg = dc->res_pool->timing_generators[i];
1522 if (tg->funcs->disable_vga)
1523 tg->funcs->disable_vga(tg);
1525 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1526 /* Enable CLOCK gating for each pipe BEFORE controller
1528 enable_display_pipe_clock_gating(ctx,
1531 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1532 dc->hwss.disable_plane(dc,
1533 &dc->current_state->res_ctx.pipe_ctx[i]);
1538 static struct dc_stream_state *get_edp_stream(struct dc_state *context)
1542 for (i = 0; i < context->stream_count; i++) {
1543 if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
1544 return context->streams[i];
1549 static struct dc_link *get_edp_link(struct dc *dc)
1553 // report any eDP links, even unconnected DDI's
1554 for (i = 0; i < dc->link_count; i++) {
1555 if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
1556 return dc->links[i];
1561 static struct dc_link *get_edp_link_with_sink(
1563 struct dc_state *context)
1566 struct dc_link *link = NULL;
1568 /* check if there is an eDP panel not in use */
1569 for (i = 0; i < dc->link_count; i++) {
1570 if (dc->links[i]->local_sink &&
1571 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1572 link = dc->links[i];
1581 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1582 * 1. Power down all DC HW blocks
1583 * 2. Disable VGA engine on all controllers
1584 * 3. Enable power gating for controller
1585 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1587 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1590 struct dc_link *edp_link_with_sink = get_edp_link_with_sink(dc, context);
1591 struct dc_link *edp_link = get_edp_link(dc);
1592 struct dc_stream_state *edp_stream = NULL;
1593 bool can_apply_edp_fast_boot = false;
1594 bool can_apply_seamless_boot = false;
1595 bool keep_edp_vdd_on = false;
1597 if (dc->hwss.init_pipes)
1598 dc->hwss.init_pipes(dc, context);
1600 edp_stream = get_edp_stream(context);
1602 // Check fastboot support, disable on DCE8 because of blank screens
1603 if (edp_link && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1604 dc->ctx->dce_version != DCE_VERSION_8_1 &&
1605 dc->ctx->dce_version != DCE_VERSION_8_3) {
1607 // enable fastboot if backend is enabled on eDP
1608 if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) {
1609 /* Set optimization flag on eDP stream*/
1611 edp_stream->apply_edp_fast_boot_optimization = true;
1612 can_apply_edp_fast_boot = true;
1616 // We are trying to enable eDP, don't power down VDD
1618 keep_edp_vdd_on = true;
1621 // Check seamless boot support
1622 for (i = 0; i < context->stream_count; i++) {
1623 if (context->streams[i]->apply_seamless_boot_optimization) {
1624 can_apply_seamless_boot = true;
1629 /* eDP should not have stream in resume from S4 and so even with VBios post
1630 * it should get turned off
1632 if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1633 if (edp_link_with_sink && !keep_edp_vdd_on) {
1634 /*turn off backlight before DP_blank and encoder powered down*/
1635 dc->hwss.edp_backlight_control(edp_link_with_sink, false);
1637 /*resume from S3, no vbios posting, no need to power down again*/
1638 power_down_all_hw_blocks(dc);
1639 disable_vga_and_power_gate_all_controllers(dc);
1640 if (edp_link_with_sink && !keep_edp_vdd_on)
1641 dc->hwss.edp_power_control(edp_link_with_sink, false);
1643 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1646 static uint32_t compute_pstate_blackout_duration(
1647 struct bw_fixed blackout_duration,
1648 const struct dc_stream_state *stream)
1650 uint32_t total_dest_line_time_ns;
1651 uint32_t pstate_blackout_duration_ns;
1653 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1655 total_dest_line_time_ns = 1000000UL *
1656 (stream->timing.h_total * 10) /
1657 stream->timing.pix_clk_100hz +
1658 pstate_blackout_duration_ns;
1660 return total_dest_line_time_ns;
1663 static void dce110_set_displaymarks(
1664 const struct dc *dc,
1665 struct dc_state *context)
1667 uint8_t i, num_pipes;
1668 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1670 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1671 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1672 uint32_t total_dest_line_time_ns;
1674 if (pipe_ctx->stream == NULL)
1677 total_dest_line_time_ns = compute_pstate_blackout_duration(
1678 dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1679 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1680 pipe_ctx->plane_res.mi,
1681 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1682 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1683 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1684 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1685 total_dest_line_time_ns);
1686 if (i == underlay_idx) {
1688 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1689 pipe_ctx->plane_res.mi,
1690 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1691 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1692 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1693 total_dest_line_time_ns);
1699 void dce110_set_safe_displaymarks(
1700 struct resource_context *res_ctx,
1701 const struct resource_pool *pool)
1704 int underlay_idx = pool->underlay_pipe_index;
1705 struct dce_watermarks max_marks = {
1706 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1707 struct dce_watermarks nbp_marks = {
1708 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1709 struct dce_watermarks min_marks = { 0, 0, 0, 0};
1711 for (i = 0; i < MAX_PIPES; i++) {
1712 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1715 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1716 res_ctx->pipe_ctx[i].plane_res.mi,
1723 if (i == underlay_idx)
1724 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1725 res_ctx->pipe_ctx[i].plane_res.mi,
1734 /*******************************************************************************
1736 ******************************************************************************/
1738 static void set_drr(struct pipe_ctx **pipe_ctx,
1739 int num_pipes, int vmin, int vmax)
1742 struct drr_params params = {0};
1743 // DRR should set trigger event to monitor surface update event
1744 unsigned int event_triggers = 0x80;
1746 params.vertical_total_max = vmax;
1747 params.vertical_total_min = vmin;
1749 /* TODO: If multiple pipes are to be supported, you need
1750 * some GSL stuff. Static screen triggers may be programmed differently
1753 for (i = 0; i < num_pipes; i++) {
1754 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1755 pipe_ctx[i]->stream_res.tg, ¶ms);
1757 if (vmax != 0 && vmin != 0)
1758 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1759 pipe_ctx[i]->stream_res.tg,
1764 static void get_position(struct pipe_ctx **pipe_ctx,
1766 struct crtc_position *position)
1770 /* TODO: handle pipes > 1
1772 for (i = 0; i < num_pipes; i++)
1773 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1776 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1777 int num_pipes, const struct dc_static_screen_events *events)
1780 unsigned int value = 0;
1782 if (events->overlay_update)
1784 if (events->surface_update)
1786 if (events->cursor_update)
1788 if (events->force_trigger)
1792 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1794 if (dc->fbc_compressor)
1798 for (i = 0; i < num_pipes; i++)
1799 pipe_ctx[i]->stream_res.tg->funcs->
1800 set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
1804 * Check if FBC can be enabled
1806 static bool should_enable_fbc(struct dc *dc,
1807 struct dc_state *context,
1811 struct pipe_ctx *pipe_ctx = NULL;
1812 struct resource_context *res_ctx = &context->res_ctx;
1813 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1816 ASSERT(dc->fbc_compressor);
1818 /* FBC memory should be allocated */
1819 if (!dc->ctx->fbc_gpu_addr)
1822 /* Only supports single display */
1823 if (context->stream_count != 1)
1826 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1827 if (res_ctx->pipe_ctx[i].stream) {
1829 pipe_ctx = &res_ctx->pipe_ctx[i];
1834 /* fbc not applicable on underlay pipe */
1835 if (pipe_ctx->pipe_idx != underlay_idx) {
1842 if (i == dc->res_pool->pipe_count)
1845 if (!pipe_ctx->stream->link)
1848 /* Only supports eDP */
1849 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
1852 /* PSR should not be enabled */
1853 if (pipe_ctx->stream->link->psr_enabled)
1856 /* Nothing to compress */
1857 if (!pipe_ctx->plane_state)
1860 /* Only for non-linear tiling */
1861 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1870 static void enable_fbc(
1872 struct dc_state *context)
1874 uint32_t pipe_idx = 0;
1876 if (should_enable_fbc(dc, context, &pipe_idx)) {
1877 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1878 struct compr_addr_and_pitch_params params = {0, 0, 0};
1879 struct compressor *compr = dc->fbc_compressor;
1880 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1882 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
1883 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
1884 params.inst = pipe_ctx->stream_res.tg->inst;
1885 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1887 compr->funcs->surface_address_and_pitch(compr, ¶ms);
1888 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1890 compr->funcs->enable_fbc(compr, ¶ms);
1894 static void dce110_reset_hw_ctx_wrap(
1896 struct dc_state *context)
1900 /* Reset old context */
1901 /* look up the targets that have been removed since last commit */
1902 for (i = 0; i < MAX_PIPES; i++) {
1903 struct pipe_ctx *pipe_ctx_old =
1904 &dc->current_state->res_ctx.pipe_ctx[i];
1905 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1907 /* Note: We need to disable output if clock sources change,
1908 * since bios does optimization and doesn't apply if changing
1909 * PHY when not already disabled.
1912 /* Skip underlay pipe since it will be handled in commit surface*/
1913 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1916 if (!pipe_ctx->stream ||
1917 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1918 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1920 /* Disable if new stream is null. O/w, if stream is
1921 * disabled already, no need to disable again.
1923 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
1924 core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
1926 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1927 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1928 dm_error("DC: failed to blank crtc!\n");
1929 BREAK_TO_DEBUGGER();
1931 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1932 pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1933 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
1935 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
1938 old_clk->funcs->cs_power_down(old_clk);
1940 dc->hwss.disable_plane(dc, pipe_ctx_old);
1942 pipe_ctx_old->stream = NULL;
1947 static void dce110_setup_audio_dto(
1949 struct dc_state *context)
1953 /* program audio wall clock. use HDMI as clock source if HDMI
1954 * audio active. Otherwise, use DP as clock source
1955 * first, loop to find any HDMI audio, if not, loop find DP audio
1957 /* Setup audio rate clock source */
1959 * Audio lag happened on DP monitor when unplug a HDMI monitor
1962 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1963 * is set to either dto0 or dto1, audio should work fine.
1964 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1965 * set to dto0 will cause audio lag.
1968 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1969 * find first available pipe with audio, setup audio wall DTO per topology
1970 * instead of per pipe.
1972 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1973 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1975 if (pipe_ctx->stream == NULL)
1978 if (pipe_ctx->top_pipe)
1981 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
1984 if (pipe_ctx->stream_res.audio != NULL) {
1985 struct audio_output audio_output;
1987 build_audio_output(context, pipe_ctx, &audio_output);
1989 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
1990 pipe_ctx->stream_res.audio,
1991 pipe_ctx->stream->signal,
1992 &audio_output.crtc_info,
1993 &audio_output.pll_info);
1998 /* no HDMI audio is found, try DP audio */
1999 if (i == dc->res_pool->pipe_count) {
2000 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2001 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2003 if (pipe_ctx->stream == NULL)
2006 if (pipe_ctx->top_pipe)
2009 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2012 if (pipe_ctx->stream_res.audio != NULL) {
2013 struct audio_output audio_output;
2015 build_audio_output(context, pipe_ctx, &audio_output);
2017 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2018 pipe_ctx->stream_res.audio,
2019 pipe_ctx->stream->signal,
2020 &audio_output.crtc_info,
2021 &audio_output.pll_info);
2028 enum dc_status dce110_apply_ctx_to_hw(
2030 struct dc_state *context)
2032 struct dc_bios *dcb = dc->ctx->dc_bios;
2033 enum dc_status status;
2036 /* Reset old context */
2037 /* look up the targets that have been removed since last commit */
2038 dc->hwss.reset_hw_ctx_wrap(dc, context);
2040 /* Skip applying if no targets */
2041 if (context->stream_count <= 0)
2044 /* Apply new context */
2045 dcb->funcs->set_scratch_critical_state(dcb, true);
2047 /* below is for real asic only */
2048 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2049 struct pipe_ctx *pipe_ctx_old =
2050 &dc->current_state->res_ctx.pipe_ctx[i];
2051 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2053 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2056 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2057 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2058 dce_crtc_switch_to_clk_src(dc->hwseq,
2059 pipe_ctx->clock_source, i);
2063 dc->hwss.enable_display_power_gating(
2064 dc, i, dc->ctx->dc_bios,
2065 PIPE_GATING_CONTROL_DISABLE);
2068 if (dc->fbc_compressor)
2069 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2071 dce110_setup_audio_dto(dc, context);
2073 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2074 struct pipe_ctx *pipe_ctx_old =
2075 &dc->current_state->res_ctx.pipe_ctx[i];
2076 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2078 if (pipe_ctx->stream == NULL)
2081 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2082 pipe_ctx->stream->link->link_state_valid) {
2086 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2089 if (pipe_ctx->top_pipe)
2092 status = apply_single_controller_ctx_to_hw(
2097 if (DC_OK != status)
2101 if (dc->fbc_compressor)
2102 enable_fbc(dc, dc->current_state);
2104 dcb->funcs->set_scratch_critical_state(dcb, false);
2109 /*******************************************************************************
2110 * Front End programming
2111 ******************************************************************************/
2112 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2114 struct default_adjustment default_adjust = { 0 };
2116 default_adjust.force_hw_default = false;
2117 default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2118 default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2119 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2120 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2122 /* display color depth */
2123 default_adjust.color_depth =
2124 pipe_ctx->stream->timing.display_color_depth;
2126 /* Lb color depth */
2127 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2129 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2130 pipe_ctx->plane_res.xfm, &default_adjust);
2134 /*******************************************************************************
2135 * In order to turn on/off specific surface we will program
2138 * In case that we have two surfaces and they have a different visibility
2139 * we can't turn off the CRTC since it will turn off the entire display
2141 * |----------------------------------------------- |
2142 * |bottom pipe|curr pipe | | |
2143 * |Surface |Surface | Blender | CRCT |
2144 * |visibility |visibility | Configuration| |
2145 * |------------------------------------------------|
2146 * | off | off | CURRENT_PIPE | blank |
2147 * | off | on | CURRENT_PIPE | unblank |
2148 * | on | off | OTHER_PIPE | unblank |
2149 * | on | on | BLENDING | unblank |
2150 * -------------------------------------------------|
2152 ******************************************************************************/
2153 static void program_surface_visibility(const struct dc *dc,
2154 struct pipe_ctx *pipe_ctx)
2156 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2157 bool blank_target = false;
2159 if (pipe_ctx->bottom_pipe) {
2161 /* For now we are supporting only two pipes */
2162 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2164 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2165 if (pipe_ctx->plane_state->visible)
2166 blender_mode = BLND_MODE_BLENDING;
2168 blender_mode = BLND_MODE_OTHER_PIPE;
2170 } else if (!pipe_ctx->plane_state->visible)
2171 blank_target = true;
2173 } else if (!pipe_ctx->plane_state->visible)
2174 blank_target = true;
2176 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2177 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2181 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2184 struct xfm_grph_csc_adjustment adjust;
2185 memset(&adjust, 0, sizeof(adjust));
2186 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2189 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2190 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2192 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2193 adjust.temperature_matrix[i] =
2194 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2197 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2199 static void update_plane_addr(const struct dc *dc,
2200 struct pipe_ctx *pipe_ctx)
2202 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2204 if (plane_state == NULL)
2207 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2208 pipe_ctx->plane_res.mi,
2209 &plane_state->address,
2210 plane_state->flip_immediate);
2212 plane_state->status.requested_address = plane_state->address;
2215 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2217 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2219 if (plane_state == NULL)
2222 plane_state->status.is_flip_pending =
2223 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2224 pipe_ctx->plane_res.mi);
2226 if (plane_state->status.is_flip_pending && !plane_state->visible)
2227 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2229 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2230 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2231 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2232 plane_state->status.is_right_eye =\
2233 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2237 void dce110_power_down(struct dc *dc)
2239 power_down_all_hw_blocks(dc);
2240 disable_vga_and_power_gate_all_controllers(dc);
2243 static bool wait_for_reset_trigger_to_occur(
2244 struct dc_context *dc_ctx,
2245 struct timing_generator *tg)
2249 /* To avoid endless loop we wait at most
2250 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2251 const uint32_t frames_to_wait_on_triggered_reset = 10;
2254 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2256 if (!tg->funcs->is_counter_moving(tg)) {
2257 DC_ERROR("TG counter is not moving!\n");
2261 if (tg->funcs->did_triggered_reset_occur(tg)) {
2263 /* usually occurs at i=1 */
2264 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2269 /* Wait for one frame. */
2270 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2271 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2275 DC_ERROR("GSL: Timeout on reset trigger!\n");
2280 /* Enable timing synchronization for a group of Timing Generators. */
2281 static void dce110_enable_timing_synchronization(
2285 struct pipe_ctx *grouped_pipes[])
2287 struct dc_context *dc_ctx = dc->ctx;
2288 struct dcp_gsl_params gsl_params = { 0 };
2291 DC_SYNC_INFO("GSL: Setting-up...\n");
2293 /* Designate a single TG in the group as a master.
2294 * Since HW doesn't care which one, we always assign
2295 * the 1st one in the group. */
2296 gsl_params.gsl_group = 0;
2297 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2299 for (i = 0; i < group_size; i++)
2300 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2301 grouped_pipes[i]->stream_res.tg, &gsl_params);
2303 /* Reset slave controllers on master VSync */
2304 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2306 for (i = 1 /* skip the master */; i < group_size; i++)
2307 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2308 grouped_pipes[i]->stream_res.tg,
2309 gsl_params.gsl_group);
2311 for (i = 1 /* skip the master */; i < group_size; i++) {
2312 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2313 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2314 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2315 grouped_pipes[i]->stream_res.tg);
2318 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2319 * is that the sync'ed displays will not drift out of sync over time*/
2320 DC_SYNC_INFO("GSL: Restoring register states.\n");
2321 for (i = 0; i < group_size; i++)
2322 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2324 DC_SYNC_INFO("GSL: Set-up complete.\n");
2327 static void dce110_enable_per_frame_crtc_position_reset(
2330 struct pipe_ctx *grouped_pipes[])
2332 struct dc_context *dc_ctx = dc->ctx;
2333 struct dcp_gsl_params gsl_params = { 0 };
2336 gsl_params.gsl_group = 0;
2337 gsl_params.gsl_master = 0;
2339 for (i = 0; i < group_size; i++)
2340 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2341 grouped_pipes[i]->stream_res.tg, &gsl_params);
2343 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2345 for (i = 1; i < group_size; i++)
2346 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2347 grouped_pipes[i]->stream_res.tg,
2348 gsl_params.gsl_master,
2349 &grouped_pipes[i]->stream->triggered_crtc_reset);
2351 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2352 for (i = 1; i < group_size; i++)
2353 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2355 for (i = 0; i < group_size; i++)
2356 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2360 static void init_pipes(struct dc *dc, struct dc_state *context)
2365 static void init_hw(struct dc *dc)
2369 struct transform *xfm;
2373 bp = dc->ctx->dc_bios;
2374 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2375 xfm = dc->res_pool->transforms[i];
2376 xfm->funcs->transform_reset(xfm);
2378 dc->hwss.enable_display_power_gating(
2380 PIPE_GATING_CONTROL_INIT);
2381 dc->hwss.enable_display_power_gating(
2383 PIPE_GATING_CONTROL_DISABLE);
2384 dc->hwss.enable_display_pipe_clock_gating(
2389 dce_clock_gating_power_up(dc->hwseq, false);
2390 /***************************************/
2392 for (i = 0; i < dc->link_count; i++) {
2393 /****************************************/
2394 /* Power up AND update implementation according to the
2395 * required signal (which may be different from the
2396 * default signal on connector). */
2397 struct dc_link *link = dc->links[i];
2399 link->link_enc->funcs->hw_init(link->link_enc);
2402 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2403 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2405 tg->funcs->disable_vga(tg);
2407 /* Blank controller using driver code instead of
2409 tg->funcs->set_blank(tg, true);
2410 hwss_wait_for_blank_complete(tg);
2413 for (i = 0; i < dc->res_pool->audio_count; i++) {
2414 struct audio *audio = dc->res_pool->audios[i];
2415 audio->funcs->hw_init(audio);
2418 abm = dc->res_pool->abm;
2420 abm->funcs->init_backlight(abm);
2421 abm->funcs->abm_init(abm);
2424 dmcu = dc->res_pool->dmcu;
2425 if (dmcu != NULL && abm != NULL)
2426 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2428 if (dc->fbc_compressor)
2429 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2434 void dce110_prepare_bandwidth(
2436 struct dc_state *context)
2438 struct clk_mgr *dccg = dc->clk_mgr;
2440 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2442 dccg->funcs->update_clocks(
2448 void dce110_optimize_bandwidth(
2450 struct dc_state *context)
2452 struct clk_mgr *dccg = dc->clk_mgr;
2454 dce110_set_displaymarks(dc, context);
2456 dccg->funcs->update_clocks(
2462 static void dce110_program_front_end_for_pipe(
2463 struct dc *dc, struct pipe_ctx *pipe_ctx)
2465 struct mem_input *mi = pipe_ctx->plane_res.mi;
2466 struct pipe_ctx *old_pipe = NULL;
2467 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2468 struct xfm_grph_csc_adjustment adjust;
2469 struct out_csc_color_matrix tbl_entry;
2472 memset(&tbl_entry, 0, sizeof(tbl_entry));
2474 if (dc->current_state)
2475 old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2477 memset(&adjust, 0, sizeof(adjust));
2478 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2480 dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2482 set_default_colors(pipe_ctx);
2483 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2485 tbl_entry.color_space =
2486 pipe_ctx->stream->output_color_space;
2488 for (i = 0; i < 12; i++)
2489 tbl_entry.regval[i] =
2490 pipe_ctx->stream->csc_color_matrix.matrix[i];
2492 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2493 (pipe_ctx->plane_res.xfm, &tbl_entry);
2496 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2497 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2499 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2500 adjust.temperature_matrix[i] =
2501 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2504 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2506 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2508 program_scaler(dc, pipe_ctx);
2510 mi->funcs->mem_input_program_surface_config(
2512 plane_state->format,
2513 &plane_state->tiling_info,
2514 &plane_state->plane_size,
2515 plane_state->rotation,
2518 if (mi->funcs->set_blank)
2519 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2521 if (dc->config.gpu_vm_support)
2522 mi->funcs->mem_input_program_pte_vm(
2523 pipe_ctx->plane_res.mi,
2524 plane_state->format,
2525 &plane_state->tiling_info,
2526 plane_state->rotation);
2528 /* Moved programming gamma from dc to hwss */
2529 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2530 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2531 pipe_ctx->plane_state->update_flags.bits.gamma_change)
2532 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2534 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2535 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2538 "Pipe:%d %p: addr hi:0x%x, "
2541 " %d; dst: %d, %d, %d, %d;"
2542 "clip: %d, %d, %d, %d\n",
2544 (void *) pipe_ctx->plane_state,
2545 pipe_ctx->plane_state->address.grph.addr.high_part,
2546 pipe_ctx->plane_state->address.grph.addr.low_part,
2547 pipe_ctx->plane_state->src_rect.x,
2548 pipe_ctx->plane_state->src_rect.y,
2549 pipe_ctx->plane_state->src_rect.width,
2550 pipe_ctx->plane_state->src_rect.height,
2551 pipe_ctx->plane_state->dst_rect.x,
2552 pipe_ctx->plane_state->dst_rect.y,
2553 pipe_ctx->plane_state->dst_rect.width,
2554 pipe_ctx->plane_state->dst_rect.height,
2555 pipe_ctx->plane_state->clip_rect.x,
2556 pipe_ctx->plane_state->clip_rect.y,
2557 pipe_ctx->plane_state->clip_rect.width,
2558 pipe_ctx->plane_state->clip_rect.height);
2561 "Pipe %d: width, height, x, y\n"
2562 "viewport:%d, %d, %d, %d\n"
2563 "recout: %d, %d, %d, %d\n",
2565 pipe_ctx->plane_res.scl_data.viewport.width,
2566 pipe_ctx->plane_res.scl_data.viewport.height,
2567 pipe_ctx->plane_res.scl_data.viewport.x,
2568 pipe_ctx->plane_res.scl_data.viewport.y,
2569 pipe_ctx->plane_res.scl_data.recout.width,
2570 pipe_ctx->plane_res.scl_data.recout.height,
2571 pipe_ctx->plane_res.scl_data.recout.x,
2572 pipe_ctx->plane_res.scl_data.recout.y);
2575 static void dce110_apply_ctx_for_surface(
2577 const struct dc_stream_state *stream,
2579 struct dc_state *context)
2583 if (num_planes == 0)
2586 if (dc->fbc_compressor)
2587 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2589 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2590 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2591 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2593 if (stream == pipe_ctx->stream) {
2594 if (!pipe_ctx->top_pipe &&
2595 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2596 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
2600 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2601 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2603 if (pipe_ctx->stream != stream)
2606 /* Need to allocate mem before program front end for Fiji */
2607 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2608 pipe_ctx->plane_res.mi,
2609 pipe_ctx->stream->timing.h_total,
2610 pipe_ctx->stream->timing.v_total,
2611 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2612 context->stream_count);
2614 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2616 dc->hwss.update_plane_addr(dc, pipe_ctx);
2618 program_surface_visibility(dc, pipe_ctx);
2622 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2623 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2624 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2626 if ((stream == pipe_ctx->stream) &&
2627 (!pipe_ctx->top_pipe) &&
2628 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2629 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
2632 if (dc->fbc_compressor)
2633 enable_fbc(dc, context);
2636 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2638 int fe_idx = pipe_ctx->plane_res.mi ?
2639 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2641 /* Do not power down fe when stream is active on dce*/
2642 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2645 dc->hwss.enable_display_power_gating(
2646 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2648 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2649 dc->res_pool->transforms[fe_idx]);
2652 static void dce110_wait_for_mpcc_disconnect(
2654 struct resource_pool *res_pool,
2655 struct pipe_ctx *pipe_ctx)
2660 static void program_output_csc(struct dc *dc,
2661 struct pipe_ctx *pipe_ctx,
2662 enum dc_color_space colorspace,
2667 struct out_csc_color_matrix tbl_entry;
2669 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2670 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2672 for (i = 0; i < 12; i++)
2673 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2675 tbl_entry.color_space = color_space;
2677 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2678 pipe_ctx->plane_res.xfm, &tbl_entry);
2682 void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2684 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2685 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2686 struct mem_input *mi = pipe_ctx->plane_res.mi;
2687 struct dc_cursor_mi_param param = {
2688 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2689 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2690 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2691 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2692 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2693 .rotation = pipe_ctx->plane_state->rotation,
2694 .mirror = pipe_ctx->plane_state->horizontal_mirror
2697 if (pipe_ctx->plane_state->address.type
2698 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2699 pos_cpy.enable = false;
2701 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2702 pos_cpy.enable = false;
2704 if (ipp->funcs->ipp_cursor_set_position)
2705 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m);
2706 if (mi->funcs->set_cursor_position)
2707 mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m);
2710 void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2712 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2714 if (pipe_ctx->plane_res.ipp &&
2715 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2716 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2717 pipe_ctx->plane_res.ipp, attributes);
2719 if (pipe_ctx->plane_res.mi &&
2720 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2721 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2722 pipe_ctx->plane_res.mi, attributes);
2724 if (pipe_ctx->plane_res.xfm &&
2725 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2726 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2727 pipe_ctx->plane_res.xfm, attributes);
2730 static const struct hw_sequencer_funcs dce110_funcs = {
2731 .program_gamut_remap = program_gamut_remap,
2732 .program_output_csc = program_output_csc,
2734 .init_pipes = init_pipes,
2735 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2736 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2737 .update_plane_addr = update_plane_addr,
2738 .update_pending_status = dce110_update_pending_status,
2739 .set_input_transfer_func = dce110_set_input_transfer_func,
2740 .set_output_transfer_func = dce110_set_output_transfer_func,
2741 .power_down = dce110_power_down,
2742 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2743 .enable_timing_synchronization = dce110_enable_timing_synchronization,
2744 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
2745 .update_info_frame = dce110_update_info_frame,
2746 .enable_stream = dce110_enable_stream,
2747 .disable_stream = dce110_disable_stream,
2748 .unblank_stream = dce110_unblank_stream,
2749 .blank_stream = dce110_blank_stream,
2750 .enable_audio_stream = dce110_enable_audio_stream,
2751 .disable_audio_stream = dce110_disable_audio_stream,
2752 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2753 .enable_display_power_gating = dce110_enable_display_power_gating,
2754 .disable_plane = dce110_power_down_fe,
2755 .pipe_control_lock = dce_pipe_control_lock,
2756 .prepare_bandwidth = dce110_prepare_bandwidth,
2757 .optimize_bandwidth = dce110_optimize_bandwidth,
2759 .get_position = get_position,
2760 .set_static_screen_control = set_static_screen_control,
2761 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2762 .enable_stream_timing = dce110_enable_stream_timing,
2763 .disable_stream_gating = NULL,
2764 .enable_stream_gating = NULL,
2765 .setup_stereo = NULL,
2766 .set_avmute = dce110_set_avmute,
2767 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
2768 .edp_backlight_control = hwss_edp_backlight_control,
2769 .edp_power_control = hwss_edp_power_control,
2770 .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2771 .set_cursor_position = dce110_set_cursor_position,
2772 .set_cursor_attribute = dce110_set_cursor_attribute
2775 void dce110_hw_sequencer_construct(struct dc *dc)
2777 dc->hwss = dce110_funcs;