drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27
  28 #include "dm_services.h"
  29 #include "dc.h"
  30 #include "dc_bios_types.h"
  31 #include "core_types.h"
  32 #include "core_status.h"
  33 #include "resource.h"
  34 #include "dm_helpers.h"
  35 #include "dce110_timing_generator.h"
  36 #include "dce/dce_hwseq.h"
  37 #include "gpio_service_interface.h"
  38
  39 #include "dce110_compressor.h"
  40
  41 #include "bios/bios_parser_helper.h"
  42 #include "timing_generator.h"
  43 #include "mem_input.h"
  44 #include "opp.h"
  45 #include "ipp.h"
  46 #include "transform.h"
  47 #include "stream_encoder.h"
  48 #include "link_encoder.h"
  49 #include "link_enc_cfg.h"
  50 #include "link_hwss.h"
  51 #include "dc_link_dp.h"
  52 #if defined(CONFIG_DRM_AMD_DC_DCN)
  53 #include "dccg.h"
  54 #endif
  55 #include "clock_source.h"
  56 #include "clk_mgr.h"
  57 #include "abm.h"
  58 #include "audio.h"
  59 #include "reg_helper.h"
  60 #include "panel_cntl.h"
  61 #include "inc/link_dpcd.h"
  62 #include "dpcd_defs.h"
  63 /* include DCE11 register header files */
  64 #include "dce/dce_11_0_d.h"
  65 #include "dce/dce_11_0_sh_mask.h"
  66 #include "custom_float.h"
  67
  68 #include "atomfirmware.h"
  69
  70 #include "dcn10/dcn10_hw_sequencer.h"
  71
  72 #include "dce110_hw_sequencer.h"
  73
  74 #define GAMMA_HW_POINTS_NUM 256
  75
  76 /*
  77  * All values are in milliseconds;
  78  * For eDP, after power-up/power/down,
  79  * 300/500 msec max. delay from LCDVCC to black video generation
  80  */
  81 #define PANEL_POWER_UP_TIMEOUT 300
  82 #define PANEL_POWER_DOWN_TIMEOUT 500
  83 #define HPD_CHECK_INTERVAL 10
  84 #define OLED_POST_T7_DELAY 100
  85 #define OLED_PRE_T11_DELAY 150
  86
  87 #define CTX \
  88         hws->ctx
  89
  90 #define DC_LOGGER_INIT()
  91
  92 #define REG(reg)\
  93         hws->regs->reg
  94
  95 #undef FN
  96 #define FN(reg_name, field_name) \
  97         hws->shifts->field_name, hws->masks->field_name
  98
  99 struct dce110_hw_seq_reg_offsets {
 100         uint32_t crtc;
 101 };
 102
 103 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
 104 {
 105         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 106 },
 107 {
 108         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 109 },
 110 {
 111         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 112 },
 113 {
 114         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 115 }
 116 };
 117
 118 #define HW_REG_BLND(reg, id)\
 119         (reg + reg_offsets[id].blnd)
 120
 121 #define HW_REG_CRTC(reg, id)\
 122         (reg + reg_offsets[id].crtc)
 123
 124 #define MAX_WATERMARK 0xFFFF
 125 #define SAFE_NBP_MARK 0x7FFF
 126
 127 /*******************************************************************************
 128  * Private definitions
 129  ******************************************************************************/
 130 /***************************PIPE_CONTROL***********************************/
 131 static void dce110_init_pte(struct dc_context *ctx)
 132 {
 133         uint32_t addr;
 134         uint32_t value = 0;
 135         uint32_t chunk_int = 0;
 136         uint32_t chunk_mul = 0;
 137
 138         addr = mmUNP_DVMM_PTE_CONTROL;
 139         value = dm_read_reg(ctx, addr);
 140
 141         set_reg_field_value(
 142                 value,
 143                 0,
 144                 DVMM_PTE_CONTROL,
 145                 DVMM_USE_SINGLE_PTE);
 146
 147         set_reg_field_value(
 148                 value,
 149                 1,
 150                 DVMM_PTE_CONTROL,
 151                 DVMM_PTE_BUFFER_MODE0);
 152
 153         set_reg_field_value(
 154                 value,
 155                 1,
 156                 DVMM_PTE_CONTROL,
 157                 DVMM_PTE_BUFFER_MODE1);
 158
 159         dm_write_reg(ctx, addr, value);
 160
 161         addr = mmDVMM_PTE_REQ;
 162         value = dm_read_reg(ctx, addr);
 163
 164         chunk_int = get_reg_field_value(
 165                 value,
 166                 DVMM_PTE_REQ,
 167                 HFLIP_PTEREQ_PER_CHUNK_INT);
 168
 169         chunk_mul = get_reg_field_value(
 170                 value,
 171                 DVMM_PTE_REQ,
 172                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 173
 174         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 175
 176                 set_reg_field_value(
 177                         value,
 178                         255,
 179                         DVMM_PTE_REQ,
 180                         MAX_PTEREQ_TO_ISSUE);
 181
 182                 set_reg_field_value(
 183                         value,
 184                         4,
 185                         DVMM_PTE_REQ,
 186                         HFLIP_PTEREQ_PER_CHUNK_INT);
 187
 188                 set_reg_field_value(
 189                         value,
 190                         4,
 191                         DVMM_PTE_REQ,
 192                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 193
 194                 dm_write_reg(ctx, addr, value);
 195         }
 196 }
 197 /**************************************************************************/
 198
 199 static void enable_display_pipe_clock_gating(
 200         struct dc_context *ctx,
 201         bool clock_gating)
 202 {
 203         /*TODO*/
 204 }
 205
 206 static bool dce110_enable_display_power_gating(
 207         struct dc *dc,
 208         uint8_t controller_id,
 209         struct dc_bios *dcb,
 210         enum pipe_gating_control power_gating)
 211 {
 212         enum bp_result bp_result = BP_RESULT_OK;
 213         enum bp_pipe_control_action cntl;
 214         struct dc_context *ctx = dc->ctx;
 215         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 216
 217         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
 218                 return true;
 219
 220         if (power_gating == PIPE_GATING_CONTROL_INIT)
 221                 cntl = ASIC_PIPE_INIT;
 222         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 223                 cntl = ASIC_PIPE_ENABLE;
 224         else
 225                 cntl = ASIC_PIPE_DISABLE;
 226
 227         if (controller_id == underlay_idx)
 228                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 229
 230         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
 231
 232                 bp_result = dcb->funcs->enable_disp_power_gating(
 233                                                 dcb, controller_id + 1, cntl);
 234
 235                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 236                  * by default when command table is called
 237                  *
 238                  * Bios parser accepts controller_id = 6 as indicative of
 239                  * underlay pipe in dce110. But we do not support more
 240                  * than 3.
 241                  */
 242                 if (controller_id < CONTROLLER_ID_MAX - 1)
 243                         dm_write_reg(ctx,
 244                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 245                                 0);
 246         }
 247
 248         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 249                 dce110_init_pte(ctx);
 250
 251         if (bp_result == BP_RESULT_OK)
 252                 return true;
 253         else
 254                 return false;
 255 }
 256
 257 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 258                 const struct dc_plane_state *plane_state)
 259 {
 260         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 261
 262         switch (plane_state->format) {
 263         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 264                 prescale_params->scale = 0x2082;
 265                 break;
 266         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 267         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 268                 prescale_params->scale = 0x2020;
 269                 break;
 270         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 271         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 272                 prescale_params->scale = 0x2008;
 273                 break;
 274         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 275         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 276         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 277                 prescale_params->scale = 0x2000;
 278                 break;
 279         default:
 280                 ASSERT(false);
 281                 break;
 282         }
 283 }
 284
 285 static bool
 286 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 287                                const struct dc_plane_state *plane_state)
 288 {
 289         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 290         const struct dc_transfer_func *tf = NULL;
 291         struct ipp_prescale_params prescale_params = { 0 };
 292         bool result = true;
 293
 294         if (ipp == NULL)
 295                 return false;
 296
 297         if (plane_state->in_transfer_func)
 298                 tf = plane_state->in_transfer_func;
 299
 300         build_prescale_params(&prescale_params, plane_state);
 301         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 302
 303         if (plane_state->gamma_correction &&
 304                         !plane_state->gamma_correction->is_identity &&
 305                         dce_use_lut(plane_state->format))
 306                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 307
 308         if (tf == NULL) {
 309                 /* Default case if no input transfer function specified */
 310                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 311         } else if (tf->type == TF_TYPE_PREDEFINED) {
 312                 switch (tf->tf) {
 313                 case TRANSFER_FUNCTION_SRGB:
 314                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 315                         break;
 316                 case TRANSFER_FUNCTION_BT709:
 317                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 318                         break;
 319                 case TRANSFER_FUNCTION_LINEAR:
 320                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 321                         break;
 322                 case TRANSFER_FUNCTION_PQ:
 323                 default:
 324                         result = false;
 325                         break;
 326                 }
 327         } else if (tf->type == TF_TYPE_BYPASS) {
 328                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 329         } else {
 330                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 331                 result = false;
 332         }
 333
 334         return result;
 335 }
 336
 337 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
 338                                     struct curve_points *arr_points,
 339                                     uint32_t hw_points_num)
 340 {
 341         struct custom_float_format fmt;
 342
 343         struct pwl_result_data *rgb = rgb_resulted;
 344
 345         uint32_t i = 0;
 346
 347         fmt.exponenta_bits = 6;
 348         fmt.mantissa_bits = 12;
 349         fmt.sign = true;
 350
 351         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 352                                             &arr_points[0].custom_float_x)) {
 353                 BREAK_TO_DEBUGGER();
 354                 return false;
 355         }
 356
 357         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 358                                             &arr_points[0].custom_float_offset)) {
 359                 BREAK_TO_DEBUGGER();
 360                 return false;
 361         }
 362
 363         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 364                                             &arr_points[0].custom_float_slope)) {
 365                 BREAK_TO_DEBUGGER();
 366                 return false;
 367         }
 368
 369         fmt.mantissa_bits = 10;
 370         fmt.sign = false;
 371
 372         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
 373                                             &arr_points[1].custom_float_x)) {
 374                 BREAK_TO_DEBUGGER();
 375                 return false;
 376         }
 377
 378         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
 379                                             &arr_points[1].custom_float_y)) {
 380                 BREAK_TO_DEBUGGER();
 381                 return false;
 382         }
 383
 384         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
 385                                             &arr_points[1].custom_float_slope)) {
 386                 BREAK_TO_DEBUGGER();
 387                 return false;
 388         }
 389
 390         fmt.mantissa_bits = 12;
 391         fmt.sign = true;
 392
 393         while (i != hw_points_num) {
 394                 if (!convert_to_custom_float_format(rgb->red, &fmt,
 395                                                     &rgb->red_reg)) {
 396                         BREAK_TO_DEBUGGER();
 397                         return false;
 398                 }
 399
 400                 if (!convert_to_custom_float_format(rgb->green, &fmt,
 401                                                     &rgb->green_reg)) {
 402                         BREAK_TO_DEBUGGER();
 403                         return false;
 404                 }
 405
 406                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
 407                                                     &rgb->blue_reg)) {
 408                         BREAK_TO_DEBUGGER();
 409                         return false;
 410                 }
 411
 412                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
 413                                                     &rgb->delta_red_reg)) {
 414                         BREAK_TO_DEBUGGER();
 415                         return false;
 416                 }
 417
 418                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
 419                                                     &rgb->delta_green_reg)) {
 420                         BREAK_TO_DEBUGGER();
 421                         return false;
 422                 }
 423
 424                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
 425                                                     &rgb->delta_blue_reg)) {
 426                         BREAK_TO_DEBUGGER();
 427                         return false;
 428                 }
 429
 430                 ++rgb;
 431                 ++i;
 432         }
 433
 434         return true;
 435 }
 436
 437 #define MAX_LOW_POINT      25
 438 #define NUMBER_REGIONS     16
 439 #define NUMBER_SW_SEGMENTS 16
 440
 441 static bool
 442 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
 443                                       struct pwl_params *regamma_params)
 444 {
 445         struct curve_points *arr_points;
 446         struct pwl_result_data *rgb_resulted;
 447         struct pwl_result_data *rgb;
 448         struct pwl_result_data *rgb_plus_1;
 449         struct fixed31_32 y_r;
 450         struct fixed31_32 y_g;
 451         struct fixed31_32 y_b;
 452         struct fixed31_32 y1_min;
 453         struct fixed31_32 y3_max;
 454
 455         int32_t region_start, region_end;
 456         uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
 457
 458         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 459                 return false;
 460
 461         arr_points = regamma_params->arr_points;
 462         rgb_resulted = regamma_params->rgb_resulted;
 463         hw_points = 0;
 464
 465         memset(regamma_params, 0, sizeof(struct pwl_params));
 466
 467         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 468                 /* 16 segments
 469                  * segments are from 2^-11 to 2^5
 470                  */
 471                 region_start = -11;
 472                 region_end = region_start + NUMBER_REGIONS;
 473
 474                 for (i = 0; i < NUMBER_REGIONS; i++)
 475                         seg_distr[i] = 4;
 476
 477         } else {
 478                 /* 10 segments
 479                  * segment is from 2^-10 to 2^1
 480                  * We include an extra segment for range [2^0, 2^1). This is to
 481                  * ensure that colors with normalized values of 1 don't miss the
 482                  * LUT.
 483                  */
 484                 region_start = -10;
 485                 region_end = 1;
 486
 487                 seg_distr[0] = 4;
 488                 seg_distr[1] = 4;
 489                 seg_distr[2] = 4;
 490                 seg_distr[3] = 4;
 491                 seg_distr[4] = 4;
 492                 seg_distr[5] = 4;
 493                 seg_distr[6] = 4;
 494                 seg_distr[7] = 4;
 495                 seg_distr[8] = 4;
 496                 seg_distr[9] = 4;
 497                 seg_distr[10] = 0;
 498                 seg_distr[11] = -1;
 499                 seg_distr[12] = -1;
 500                 seg_distr[13] = -1;
 501                 seg_distr[14] = -1;
 502                 seg_distr[15] = -1;
 503         }
 504
 505         for (k = 0; k < 16; k++) {
 506                 if (seg_distr[k] != -1)
 507                         hw_points += (1 << seg_distr[k]);
 508         }
 509
 510         j = 0;
 511         for (k = 0; k < (region_end - region_start); k++) {
 512                 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
 513                 start_index = (region_start + k + MAX_LOW_POINT) *
 514                                 NUMBER_SW_SEGMENTS;
 515                 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 516                                 i += increment) {
 517                         if (j == hw_points - 1)
 518                                 break;
 519                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 520                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 521                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 522                         j++;
 523                 }
 524         }
 525
 526         /* last point */
 527         start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
 528         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
 529         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
 530         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 531
 532         arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 533                                              dc_fixpt_from_int(region_start));
 534         arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 535                                              dc_fixpt_from_int(region_end));
 536
 537         y_r = rgb_resulted[0].red;
 538         y_g = rgb_resulted[0].green;
 539         y_b = rgb_resulted[0].blue;
 540
 541         y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 542
 543         arr_points[0].y = y1_min;
 544         arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
 545                                                  arr_points[0].x);
 546
 547         y_r = rgb_resulted[hw_points - 1].red;
 548         y_g = rgb_resulted[hw_points - 1].green;
 549         y_b = rgb_resulted[hw_points - 1].blue;
 550
 551         /* see comment above, m_arrPoints[1].y should be the Y value for the
 552          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 553          */
 554         y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 555
 556         arr_points[1].y = y3_max;
 557
 558         arr_points[1].slope = dc_fixpt_zero;
 559
 560         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 561                 /* for PQ, we want to have a straight line from last HW X point,
 562                  * and the slope to be such that we hit 1.0 at 10000 nits.
 563                  */
 564                 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
 565
 566                 arr_points[1].slope = dc_fixpt_div(
 567                                 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
 568                                 dc_fixpt_sub(end_value, arr_points[1].x));
 569         }
 570
 571         regamma_params->hw_points_num = hw_points;
 572
 573         k = 0;
 574         for (i = 1; i < 16; i++) {
 575                 if (seg_distr[k] != -1) {
 576                         regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 577                         regamma_params->arr_curve_points[i].offset =
 578                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 579                 }
 580                 k++;
 581         }
 582
 583         if (seg_distr[k] != -1)
 584                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 585
 586         rgb = rgb_resulted;
 587         rgb_plus_1 = rgb_resulted + 1;
 588
 589         i = 1;
 590
 591         while (i != hw_points + 1) {
 592                 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
 593                         rgb_plus_1->red = rgb->red;
 594                 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
 595                         rgb_plus_1->green = rgb->green;
 596                 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
 597                         rgb_plus_1->blue = rgb->blue;
 598
 599                 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
 600                 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
 601                 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
 602
 603                 ++rgb_plus_1;
 604                 ++rgb;
 605                 ++i;
 606         }
 607
 608         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 609
 610         return true;
 611 }
 612
 613 static bool
 614 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 615                                 const struct dc_stream_state *stream)
 616 {
 617         struct transform *xfm = pipe_ctx->plane_res.xfm;
 618
 619         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 620         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 621
 622         if (stream->out_transfer_func &&
 623             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 624             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 625                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 626         } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
 627                                                          &xfm->regamma_params)) {
 628                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 629                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 630         } else {
 631                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 632         }
 633
 634         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 635
 636         return true;
 637 }
 638
 639 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 640 {
 641         bool is_hdmi_tmds;
 642         bool is_dp;
 643
 644         ASSERT(pipe_ctx->stream);
 645
 646         if (pipe_ctx->stream_res.stream_enc == NULL)
 647                 return;  /* this is not root pipe */
 648
 649         is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
 650         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 651
 652         if (!is_hdmi_tmds && !is_dp)
 653                 return;
 654
 655         if (is_hdmi_tmds)
 656                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 657                         pipe_ctx->stream_res.stream_enc,
 658                         &pipe_ctx->stream_res.encoder_info_frame);
 659         else
 660                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 661                         pipe_ctx->stream_res.stream_enc,
 662                         &pipe_ctx->stream_res.encoder_info_frame);
 663 }
 664
 665 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 666 {
 667         enum dc_lane_count lane_count =
 668                 pipe_ctx->stream->link->cur_link_settings.lane_count;
 669         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 670         struct dc_link *link = pipe_ctx->stream->link;
 671         const struct dc *dc = link->dc;
 672
 673         uint32_t active_total_with_borders;
 674         uint32_t early_control = 0;
 675         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 676
 677         /* For MST, there are multiply stream go to only one link.
 678          * connect DIG back_end to front_end while enable_stream and
 679          * disconnect them during disable_stream
 680          * BY this, it is logic clean to separate stream and link */
 681         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
 682                                                     pipe_ctx->stream_res.stream_enc->id, true);
 683
 684         dc->hwss.update_info_frame(pipe_ctx);
 685
 686         /* enable early control to avoid corruption on DP monitor*/
 687         active_total_with_borders =
 688                         timing->h_addressable
 689                                 + timing->h_border_left
 690                                 + timing->h_border_right;
 691
 692         if (lane_count != 0)
 693                 early_control = active_total_with_borders % lane_count;
 694
 695         if (early_control == 0)
 696                 early_control = lane_count;
 697
 698         tg->funcs->set_early_control(tg, early_control);
 699
 700         /* enable audio only within mode set */
 701         if (pipe_ctx->stream_res.audio != NULL) {
 702                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
 703                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
 704         }
 705
 706
 707
 708
 709 }
 710
 711 static enum bp_result link_transmitter_control(
 712                 struct dc_bios *bios,
 713         struct bp_transmitter_control *cntl)
 714 {
 715         enum bp_result result;
 716
 717         result = bios->funcs->transmitter_control(bios, cntl);
 718
 719         return result;
 720 }
 721
 722 /*
 723  * @brief
 724  * eDP only.
 725  */
 726 void dce110_edp_wait_for_hpd_ready(
 727                 struct dc_link *link,
 728                 bool power_up)
 729 {
 730         struct dc_context *ctx = link->ctx;
 731         struct graphics_object_id connector = link->link_enc->connector;
 732         struct gpio *hpd;
 733         struct dc_sink *sink = link->local_sink;
 734         bool edp_hpd_high = false;
 735         uint32_t time_elapsed = 0;
 736         uint32_t timeout = power_up ?
 737                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 738
 739         if (dal_graphics_object_id_get_connector_id(connector)
 740                         != CONNECTOR_ID_EDP) {
 741                 BREAK_TO_DEBUGGER();
 742                 return;
 743         }
 744
 745         if (!power_up)
 746                 /*
 747                  * From KV, we will not HPD low after turning off VCC -
 748                  * instead, we will check the SW timer in power_up().
 749                  */
 750                 return;
 751
 752         /*
 753          * When we power on/off the eDP panel,
 754          * we need to wait until SENSE bit is high/low.
 755          */
 756
 757         /* obtain HPD */
 758         /* TODO what to do with this? */
 759         hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 760
 761         if (!hpd) {
 762                 BREAK_TO_DEBUGGER();
 763                 return;
 764         }
 765
 766         if (sink != NULL) {
 767                 if (sink->edid_caps.panel_patch.extra_t3_ms > 0) {
 768                         int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms;
 769
 770                         msleep(extra_t3_in_ms);
 771                 }
 772         }
 773
 774         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 775
 776         /* wait until timeout or panel detected */
 777
 778         do {
 779                 uint32_t detected = 0;
 780
 781                 dal_gpio_get_value(hpd, &detected);
 782
 783                 if (!(detected ^ power_up)) {
 784                         edp_hpd_high = true;
 785                         break;
 786                 }
 787
 788                 msleep(HPD_CHECK_INTERVAL);
 789
 790                 time_elapsed += HPD_CHECK_INTERVAL;
 791         } while (time_elapsed < timeout);
 792
 793         dal_gpio_close(hpd);
 794
 795         dal_gpio_destroy_irq(&hpd);
 796
 797         if (false == edp_hpd_high) {
 798                 DC_LOG_ERROR(
 799                                 "%s: wait timed out!\n", __func__);
 800         }
 801 }
 802
 803 void dce110_edp_power_control(
 804                 struct dc_link *link,
 805                 bool power_up)
 806 {
 807         struct dc_context *ctx = link->ctx;
 808         struct bp_transmitter_control cntl = { 0 };
 809         enum bp_result bp_result;
 810         uint8_t panel_instance;
 811
 812
 813         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 814                         != CONNECTOR_ID_EDP) {
 815                 BREAK_TO_DEBUGGER();
 816                 return;
 817         }
 818
 819         if (!link->panel_cntl)
 820                 return;
 821         if (power_up !=
 822                 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
 823
 824                 unsigned long long current_ts = dm_get_timestamp(ctx);
 825                 unsigned long long time_since_edp_poweroff_ms =
 826                                 div64_u64(dm_get_elapse_time_in_ns(
 827                                                 ctx,
 828                                                 current_ts,
 829                                                 link->link_trace.time_stamp.edp_poweroff), 1000000);
 830                 unsigned long long time_since_edp_poweron_ms =
 831                                 div64_u64(dm_get_elapse_time_in_ns(
 832                                                 ctx,
 833                                                 current_ts,
 834                                                 link->link_trace.time_stamp.edp_poweron), 1000000);
 835                 DC_LOG_HW_RESUME_S3(
 836                                 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",
 837                                 __func__,
 838                                 power_up,
 839                                 current_ts,
 840                                 link->link_trace.time_stamp.edp_poweroff,
 841                                 link->link_trace.time_stamp.edp_poweron,
 842                                 time_since_edp_poweroff_ms,
 843                                 time_since_edp_poweron_ms);
 844
 845                 /* Send VBIOS command to prompt eDP panel power */
 846                 if (power_up) {
 847                         /* edp requires a min of 500ms from LCDVDD off to on */
 848                         unsigned long long remaining_min_edp_poweroff_time_ms = 500;
 849
 850                         /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */
 851                         if (link->local_sink != NULL)
 852                                 remaining_min_edp_poweroff_time_ms +=
 853                                         link->local_sink->edid_caps.panel_patch.extra_t12_ms;
 854
 855                         /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */
 856                         if (link->link_trace.time_stamp.edp_poweroff != 0) {
 857                                 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms)
 858                                         remaining_min_edp_poweroff_time_ms =
 859                                                 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms;
 860                                 else
 861                                         remaining_min_edp_poweroff_time_ms = 0;
 862                         }
 863
 864                         if (remaining_min_edp_poweroff_time_ms) {
 865                                 DC_LOG_HW_RESUME_S3(
 866                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
 867                                                 __func__, remaining_min_edp_poweroff_time_ms);
 868                                 msleep(remaining_min_edp_poweroff_time_ms);
 869                                 DC_LOG_HW_RESUME_S3(
 870                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
 871                                                 __func__, remaining_min_edp_poweroff_time_ms);
 872                                 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
 873                                                 __func__, remaining_min_edp_poweroff_time_ms);
 874                         } else {
 875                                 DC_LOG_HW_RESUME_S3(
 876                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",
 877                                                 __func__, remaining_min_edp_poweroff_time_ms);
 878                         }
 879                 }
 880
 881                 DC_LOG_HW_RESUME_S3(
 882                                 "%s: BEGIN: Panel Power action: %s\n",
 883                                 __func__, (power_up ? "On":"Off"));
 884
 885                 cntl.action = power_up ?
 886                         TRANSMITTER_CONTROL_POWER_ON :
 887                         TRANSMITTER_CONTROL_POWER_OFF;
 888                 cntl.transmitter = link->link_enc->transmitter;
 889                 cntl.connector_obj_id = link->link_enc->connector;
 890                 cntl.coherent = false;
 891                 cntl.lanes_number = LANE_COUNT_FOUR;
 892                 cntl.hpd_sel = link->link_enc->hpd_source;
 893                 panel_instance = link->panel_cntl->inst;
 894
 895                 if (ctx->dc->ctx->dmub_srv &&
 896                                 ctx->dc->debug.dmub_command_table) {
 897                         if (cntl.action == TRANSMITTER_CONTROL_POWER_ON)
 898                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 899                                                 LVTMA_CONTROL_POWER_ON,
 900                                                 panel_instance);
 901                         else
 902                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 903                                                 LVTMA_CONTROL_POWER_OFF,
 904                                                 panel_instance);
 905                 }
 906
 907                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 908
 909                 DC_LOG_HW_RESUME_S3(
 910                                 "%s: END: Panel Power action: %s bp_result=%u\n",
 911                                 __func__, (power_up ? "On":"Off"),
 912                                 bp_result);
 913
 914                 if (!power_up)
 915                         /*save driver power off time stamp*/
 916                         link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
 917                 else
 918                         link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
 919
 920                 DC_LOG_HW_RESUME_S3(
 921                                 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",
 922                                 __func__,
 923                                 link->link_trace.time_stamp.edp_poweroff,
 924                                 link->link_trace.time_stamp.edp_poweron);
 925
 926                 if (bp_result != BP_RESULT_OK)
 927                         DC_LOG_ERROR(
 928                                         "%s: Panel Power bp_result: %d\n",
 929                                         __func__, bp_result);
 930         } else {
 931                 DC_LOG_HW_RESUME_S3(
 932                                 "%s: Skipping Panel Power action: %s\n",
 933                                 __func__, (power_up ? "On":"Off"));
 934         }
 935 }
 936
 937 void dce110_edp_wait_for_T12(
 938                 struct dc_link *link)
 939 {
 940         struct dc_context *ctx = link->ctx;
 941
 942         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 943                         != CONNECTOR_ID_EDP) {
 944                 BREAK_TO_DEBUGGER();
 945                 return;
 946         }
 947
 948         if (!link->panel_cntl)
 949                 return;
 950
 951         if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&
 952                         link->link_trace.time_stamp.edp_poweroff != 0) {
 953                 unsigned int t12_duration = 500; // Default T12 as per spec
 954                 unsigned long long current_ts = dm_get_timestamp(ctx);
 955                 unsigned long long time_since_edp_poweroff_ms =
 956                                 div64_u64(dm_get_elapse_time_in_ns(
 957                                                 ctx,
 958                                                 current_ts,
 959                                                 link->link_trace.time_stamp.edp_poweroff), 1000000);
 960
 961                 t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12
 962
 963                 if (time_since_edp_poweroff_ms < t12_duration)
 964                         msleep(t12_duration - time_since_edp_poweroff_ms);
 965         }
 966 }
 967
 968 /*todo: cloned in stream enc, fix*/
 969 /*
 970  * @brief
 971  * eDP only. Control the backlight of the eDP panel
 972  */
 973 void dce110_edp_backlight_control(
 974                 struct dc_link *link,
 975                 bool enable)
 976 {
 977         struct dc_context *ctx = link->ctx;
 978         struct bp_transmitter_control cntl = { 0 };
 979         uint8_t panel_instance;
 980
 981         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 982                 != CONNECTOR_ID_EDP) {
 983                 BREAK_TO_DEBUGGER();
 984                 return;
 985         }
 986
 987         if (link->panel_cntl) {
 988                 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
 989
 990                 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {
 991                         DC_LOG_HW_RESUME_S3(
 992                                 "%s: panel already powered up/off. Do nothing.\n",
 993                                 __func__);
 994                         return;
 995                 }
 996         }
 997
 998         /* Send VBIOS command to control eDP panel backlight */
 999
1000         DC_LOG_HW_RESUME_S3(
1001                         "%s: backlight action: %s\n",
1002                         __func__, (enable ? "On":"Off"));
1003
1004         cntl.action = enable ?
1005                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
1006                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
1007
1008         /*cntl.engine_id = ctx->engine;*/
1009         cntl.transmitter = link->link_enc->transmitter;
1010         cntl.connector_obj_id = link->link_enc->connector;
1011         /*todo: unhardcode*/
1012         cntl.lanes_number = LANE_COUNT_FOUR;
1013         cntl.hpd_sel = link->link_enc->hpd_source;
1014         cntl.signal = SIGNAL_TYPE_EDP;
1015
1016         /* For eDP, the following delays might need to be considered
1017          * after link training completed:
1018          * idle period - min. accounts for required BS-Idle pattern,
1019          * max. allows for source frame synchronization);
1020          * 50 msec max. delay from valid video data from source
1021          * to video on dislpay or backlight enable.
1022          *
1023          * Disable the delay for now.
1024          * Enable it in the future if necessary.
1025          */
1026         /* dc_service_sleep_in_milliseconds(50); */
1027                 /*edp 1.2*/
1028         panel_instance = link->panel_cntl->inst;
1029
1030         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
1031                 if (!link->dc->config.edp_no_power_sequencing)
1032                 /*
1033                  * Sometimes, DP receiver chip power-controlled externally by an
1034                  * Embedded Controller could be treated and used as eDP,
1035                  * if it drives mobile display. In this case,
1036                  * we shouldn't be doing power-sequencing, hence we can skip
1037                  * waiting for T7-ready.
1038                  */
1039                         edp_receiver_ready_T7(link);
1040                 else
1041                         DC_LOG_DC("edp_receiver_ready_T7 skipped\n");
1042         }
1043
1044         if (ctx->dc->ctx->dmub_srv &&
1045                         ctx->dc->debug.dmub_command_table) {
1046                 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
1047                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1048                                         LVTMA_CONTROL_LCD_BLON,
1049                                         panel_instance);
1050                 else
1051                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1052                                         LVTMA_CONTROL_LCD_BLOFF,
1053                                         panel_instance);
1054         }
1055
1056         link_transmitter_control(ctx->dc_bios, &cntl);
1057
1058         if (enable && link->dpcd_sink_ext_caps.bits.oled)
1059                 msleep(OLED_POST_T7_DELAY);
1060
1061         if (link->dpcd_sink_ext_caps.bits.oled ||
1062                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
1063                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
1064                 dc_link_backlight_enable_aux(link, enable);
1065
1066         /*edp 1.2*/
1067         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) {
1068                 if (!link->dc->config.edp_no_power_sequencing)
1069                 /*
1070                  * Sometimes, DP receiver chip power-controlled externally by an
1071                  * Embedded Controller could be treated and used as eDP,
1072                  * if it drives mobile display. In this case,
1073                  * we shouldn't be doing power-sequencing, hence we can skip
1074                  * waiting for T9-ready.
1075                  */
1076                         edp_add_delay_for_T9(link);
1077                 else
1078                         DC_LOG_DC("edp_receiver_ready_T9 skipped\n");
1079         }
1080
1081         if (!enable && link->dpcd_sink_ext_caps.bits.oled)
1082                 msleep(OLED_PRE_T11_DELAY);
1083 }
1084
1085 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
1086 {
1087         /* notify audio driver for audio modes of monitor */
1088         struct dc *dc;
1089         struct clk_mgr *clk_mgr;
1090         unsigned int i, num_audio = 1;
1091
1092         if (!pipe_ctx->stream)
1093                 return;
1094
1095         dc = pipe_ctx->stream->ctx->dc;
1096         clk_mgr = dc->clk_mgr;
1097
1098         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
1099                 return;
1100
1101         if (pipe_ctx->stream_res.audio) {
1102                 for (i = 0; i < MAX_PIPES; i++) {
1103                         /*current_state not updated yet*/
1104                         if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1105                                 num_audio++;
1106                 }
1107
1108                 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1109
1110                 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
1111                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1112                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1113                 /* un-mute audio */
1114                 /* TODO: audio should be per stream rather than per link */
1115 #if defined(CONFIG_DRM_AMD_DC_DCN)
1116                 if (is_dp_128b_132b_signal(pipe_ctx))
1117                         pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control(
1118                                         pipe_ctx->stream_res.hpo_dp_stream_enc, false);
1119                 else
1120                         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1121                                         pipe_ctx->stream_res.stream_enc, false);
1122 #else
1123                 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1124                                 pipe_ctx->stream_res.stream_enc, false);
1125 #endif
1126                 if (pipe_ctx->stream_res.audio)
1127                         pipe_ctx->stream_res.audio->enabled = true;
1128         }
1129
1130         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1131                 dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_ENABLE_AUDIO_STREAM);
1132 }
1133
1134 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
1135 {
1136         struct dc *dc;
1137         struct clk_mgr *clk_mgr;
1138
1139         if (!pipe_ctx || !pipe_ctx->stream)
1140                 return;
1141
1142         dc = pipe_ctx->stream->ctx->dc;
1143         clk_mgr = dc->clk_mgr;
1144
1145         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1146                 return;
1147
1148 #if defined(CONFIG_DRM_AMD_DC_DCN)
1149         if (is_dp_128b_132b_signal(pipe_ctx))
1150                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control(
1151                                 pipe_ctx->stream_res.hpo_dp_stream_enc, true);
1152         else
1153                 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1154                                 pipe_ctx->stream_res.stream_enc, true);
1155 #else
1156         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1157                         pipe_ctx->stream_res.stream_enc, true);
1158 #endif
1159         if (pipe_ctx->stream_res.audio) {
1160                 pipe_ctx->stream_res.audio->enabled = false;
1161
1162                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1163 #if defined(CONFIG_DRM_AMD_DC_DCN)
1164                         if (is_dp_128b_132b_signal(pipe_ctx))
1165                                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable(
1166                                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
1167                         else
1168                                 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1169                                                 pipe_ctx->stream_res.stream_enc);
1170 #else
1171                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1172                                         pipe_ctx->stream_res.stream_enc);
1173 #endif
1174                 else
1175                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1176                                         pipe_ctx->stream_res.stream_enc);
1177
1178                 if (clk_mgr->funcs->enable_pme_wa)
1179                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1180                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1181
1182                 /* TODO: notify audio driver for if audio modes list changed
1183                  * add audio mode list change flag */
1184                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1185                  * stream->stream_engine_id);
1186                  */
1187         }
1188
1189         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1190                 dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_DISABLE_AUDIO_STREAM);
1191 }
1192
1193 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
1194 {
1195         struct dc_stream_state *stream = pipe_ctx->stream;
1196         struct dc_link *link = stream->link;
1197         struct dc *dc = pipe_ctx->stream->ctx->dc;
1198         struct link_encoder *link_enc = NULL;
1199
1200         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1201                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1202                         pipe_ctx->stream_res.stream_enc);
1203                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1204                         pipe_ctx->stream_res.stream_enc);
1205         }
1206
1207 #if defined(CONFIG_DRM_AMD_DC_DCN)
1208         if (is_dp_128b_132b_signal(pipe_ctx)) {
1209                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(
1210                                         pipe_ctx->stream_res.hpo_dp_stream_enc);
1211         } else if (dc_is_dp_signal(pipe_ctx->stream->signal))
1212 #else
1213         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1214 #endif
1215                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1216                         pipe_ctx->stream_res.stream_enc);
1217
1218         dc->hwss.disable_audio_stream(pipe_ctx);
1219
1220         /* Link encoder may have been dynamically assigned to non-physical display endpoint. */
1221         if (link->ep_type == DISPLAY_ENDPOINT_PHY)
1222                 link_enc = link->link_enc;
1223         else if (dc->res_pool->funcs->link_encs_assign)
1224                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
1225         ASSERT(link_enc);
1226
1227 #if defined(CONFIG_DRM_AMD_DC_DCN)
1228         if (is_dp_128b_132b_signal(pipe_ctx)) {
1229                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->disable(
1230                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
1231                 setup_dp_hpo_stream(pipe_ctx, false);
1232         /* TODO - DP2.0 HW: unmap stream from link encoder here */
1233         } else {
1234                 if (link_enc)
1235                         link_enc->funcs->connect_dig_be_to_fe(
1236                                 link_enc,
1237                                 pipe_ctx->stream_res.stream_enc->id,
1238                                 false);
1239         }
1240 #else
1241         if (link_enc)
1242                 link_enc->funcs->connect_dig_be_to_fe(
1243                         link->link_enc,
1244                         pipe_ctx->stream_res.stream_enc->id,
1245                         false);
1246 #endif
1247         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1248                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE);
1249
1250 #if defined(CONFIG_DRM_AMD_DC_DCN)
1251         if (dc->hwseq->funcs.setup_hpo_hw_control && is_dp_128b_132b_signal(pipe_ctx))
1252                 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, false);
1253 #endif
1254
1255 }
1256
1257 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1258                 struct dc_link_settings *link_settings)
1259 {
1260         struct encoder_unblank_param params = { { 0 } };
1261         struct dc_stream_state *stream = pipe_ctx->stream;
1262         struct dc_link *link = stream->link;
1263         struct dce_hwseq *hws = link->dc->hwseq;
1264
1265         /* only 3 items below are used by unblank */
1266         params.timing = pipe_ctx->stream->timing;
1267         params.link_settings.link_rate = link_settings->link_rate;
1268
1269         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1270                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1271
1272         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1273                 hws->funcs.edp_backlight_control(link, true);
1274         }
1275 }
1276
1277 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1278 {
1279         struct dc_stream_state *stream = pipe_ctx->stream;
1280         struct dc_link *link = stream->link;
1281         struct dce_hwseq *hws = link->dc->hwseq;
1282
1283         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1284                 hws->funcs.edp_backlight_control(link, false);
1285                 link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
1286         }
1287
1288 #if defined(CONFIG_DRM_AMD_DC_DCN)
1289         if (is_dp_128b_132b_signal(pipe_ctx)) {
1290                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1291                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(
1292                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
1293         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1294 #else
1295         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1296 #endif
1297                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
1298
1299                 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
1300                         /*
1301                          * After output is idle pattern some sinks need time to recognize the stream
1302                          * has changed or they enter protection state and hang.
1303                          */
1304                         msleep(60);
1305                 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
1306                         edp_receiver_ready_T9(link);
1307         }
1308
1309 }
1310
1311
1312 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1313 {
1314         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1315                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1316 }
1317
1318 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1319 {
1320         switch (crtc_id) {
1321         case CONTROLLER_ID_D0:
1322                 return DTO_SOURCE_ID0;
1323         case CONTROLLER_ID_D1:
1324                 return DTO_SOURCE_ID1;
1325         case CONTROLLER_ID_D2:
1326                 return DTO_SOURCE_ID2;
1327         case CONTROLLER_ID_D3:
1328                 return DTO_SOURCE_ID3;
1329         case CONTROLLER_ID_D4:
1330                 return DTO_SOURCE_ID4;
1331         case CONTROLLER_ID_D5:
1332                 return DTO_SOURCE_ID5;
1333         default:
1334                 return DTO_SOURCE_UNKNOWN;
1335         }
1336 }
1337
1338 static void build_audio_output(
1339         struct dc_state *state,
1340         const struct pipe_ctx *pipe_ctx,
1341         struct audio_output *audio_output)
1342 {
1343         const struct dc_stream_state *stream = pipe_ctx->stream;
1344         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1345
1346         audio_output->signal = pipe_ctx->stream->signal;
1347
1348         /* audio_crtc_info  */
1349
1350         audio_output->crtc_info.h_total =
1351                 stream->timing.h_total;
1352
1353         /*
1354          * Audio packets are sent during actual CRTC blank physical signal, we
1355          * need to specify actual active signal portion
1356          */
1357         audio_output->crtc_info.h_active =
1358                         stream->timing.h_addressable
1359                         + stream->timing.h_border_left
1360                         + stream->timing.h_border_right;
1361
1362         audio_output->crtc_info.v_active =
1363                         stream->timing.v_addressable
1364                         + stream->timing.v_border_top
1365                         + stream->timing.v_border_bottom;
1366
1367         audio_output->crtc_info.pixel_repetition = 1;
1368
1369         audio_output->crtc_info.interlaced =
1370                         stream->timing.flags.INTERLACE;
1371
1372         audio_output->crtc_info.refresh_rate =
1373                 (stream->timing.pix_clk_100hz*100)/
1374                 (stream->timing.h_total*stream->timing.v_total);
1375
1376         audio_output->crtc_info.color_depth =
1377                 stream->timing.display_color_depth;
1378
1379         audio_output->crtc_info.requested_pixel_clock_100Hz =
1380                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1381
1382         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1383                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1384
1385 /*for HDMI, audio ACR is with deep color ratio factor*/
1386         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
1387                 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1388                                 (stream->timing.pix_clk_100hz)) {
1389                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1390                         audio_output->crtc_info.requested_pixel_clock_100Hz =
1391                                         audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1392                         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1393                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1394
1395                 }
1396         }
1397
1398         if (state->clk_mgr &&
1399                 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1400                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
1401                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1402                                 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1403                                                 state->clk_mgr);
1404         }
1405
1406         audio_output->pll_info.feed_back_divider =
1407                         pipe_ctx->pll_settings.feedback_divider;
1408
1409         audio_output->pll_info.dto_source =
1410                 translate_to_dto_source(
1411                         pipe_ctx->stream_res.tg->inst + 1);
1412
1413         /* TODO hard code to enable for now. Need get from stream */
1414         audio_output->pll_info.ss_enabled = true;
1415
1416         audio_output->pll_info.ss_percentage =
1417                         pipe_ctx->pll_settings.ss_percentage;
1418 }
1419
1420 static void program_scaler(const struct dc *dc,
1421                 const struct pipe_ctx *pipe_ctx)
1422 {
1423         struct tg_color color = {0};
1424
1425 #if defined(CONFIG_DRM_AMD_DC_DCN)
1426         /* TOFPGA */
1427         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1428                 return;
1429 #endif
1430
1431         if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1432                 get_surface_visual_confirm_color(pipe_ctx, &color);
1433         else
1434                 color_space_to_black_color(dc,
1435                                 pipe_ctx->stream->output_color_space,
1436                                 &color);
1437
1438         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1439                 pipe_ctx->plane_res.xfm,
1440                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1441                 &pipe_ctx->stream->bit_depth_params);
1442
1443         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1444                 /*
1445                  * The way 420 is packed, 2 channels carry Y component, 1 channel
1446                  * alternate between Cb and Cr, so both channels need the pixel
1447                  * value for Y
1448                  */
1449                 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1450                         color.color_r_cr = color.color_g_y;
1451
1452                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1453                                 pipe_ctx->stream_res.tg,
1454                                 &color);
1455         }
1456
1457         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1458                 &pipe_ctx->plane_res.scl_data);
1459 }
1460
1461 static enum dc_status dce110_enable_stream_timing(
1462                 struct pipe_ctx *pipe_ctx,
1463                 struct dc_state *context,
1464                 struct dc *dc)
1465 {
1466         struct dc_stream_state *stream = pipe_ctx->stream;
1467         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1468                         pipe_ctx[pipe_ctx->pipe_idx];
1469         struct tg_color black_color = {0};
1470
1471         if (!pipe_ctx_old->stream) {
1472
1473                 /* program blank color */
1474                 color_space_to_black_color(dc,
1475                                 stream->output_color_space, &black_color);
1476                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1477                                 pipe_ctx->stream_res.tg,
1478                                 &black_color);
1479
1480                 /*
1481                  * Must blank CRTC after disabling power gating and before any
1482                  * programming, otherwise CRTC will be hung in bad state
1483                  */
1484                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1485
1486                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1487                                 pipe_ctx->clock_source,
1488                                 &pipe_ctx->stream_res.pix_clk_params,
1489                                 &pipe_ctx->pll_settings)) {
1490                         BREAK_TO_DEBUGGER();
1491                         return DC_ERROR_UNEXPECTED;
1492                 }
1493
1494                 pipe_ctx->stream_res.tg->funcs->program_timing(
1495                                 pipe_ctx->stream_res.tg,
1496                                 &stream->timing,
1497                                 0,
1498                                 0,
1499                                 0,
1500                                 0,
1501                                 pipe_ctx->stream->signal,
1502                                 true);
1503         }
1504
1505         if (!pipe_ctx_old->stream) {
1506                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1507                                 pipe_ctx->stream_res.tg)) {
1508                         BREAK_TO_DEBUGGER();
1509                         return DC_ERROR_UNEXPECTED;
1510                 }
1511         }
1512
1513         return DC_OK;
1514 }
1515
1516 static enum dc_status apply_single_controller_ctx_to_hw(
1517                 struct pipe_ctx *pipe_ctx,
1518                 struct dc_state *context,
1519                 struct dc *dc)
1520 {
1521         struct dc_stream_state *stream = pipe_ctx->stream;
1522         struct dc_link *link = stream->link;
1523         struct drr_params params = {0};
1524         unsigned int event_triggers = 0;
1525         struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1526         struct dce_hwseq *hws = dc->hwseq;
1527
1528         if (hws->funcs.disable_stream_gating) {
1529                 hws->funcs.disable_stream_gating(dc, pipe_ctx);
1530         }
1531
1532         if (pipe_ctx->stream_res.audio != NULL) {
1533                 struct audio_output audio_output;
1534
1535                 build_audio_output(context, pipe_ctx, &audio_output);
1536
1537                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1538 #if defined(CONFIG_DRM_AMD_DC_DCN)
1539                         if (is_dp_128b_132b_signal(pipe_ctx))
1540                                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup(
1541                                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
1542                                                 pipe_ctx->stream_res.audio->inst,
1543                                                 &pipe_ctx->stream->audio_info);
1544                         else
1545                                 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1546                                                 pipe_ctx->stream_res.stream_enc,
1547                                                 pipe_ctx->stream_res.audio->inst,
1548                                                 &pipe_ctx->stream->audio_info);
1549 #else
1550                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1551                                         pipe_ctx->stream_res.stream_enc,
1552                                         pipe_ctx->stream_res.audio->inst,
1553                                         &pipe_ctx->stream->audio_info);
1554 #endif
1555                 else
1556                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1557                                         pipe_ctx->stream_res.stream_enc,
1558                                         pipe_ctx->stream_res.audio->inst,
1559                                         &pipe_ctx->stream->audio_info,
1560                                         &audio_output.crtc_info);
1561
1562                 pipe_ctx->stream_res.audio->funcs->az_configure(
1563                                 pipe_ctx->stream_res.audio,
1564                                 pipe_ctx->stream->signal,
1565                                 &audio_output.crtc_info,
1566                                 &pipe_ctx->stream->audio_info);
1567         }
1568
1569 #if defined(CONFIG_DRM_AMD_DC_DCN)
1570         /* DCN3.1 FPGA Workaround
1571          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1572          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1573          * function core_link_enable_stream
1574          */
1575         if (!(hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)))
1576 #endif
1577                 /*  */
1578                 /* Do not touch stream timing on seamless boot optimization. */
1579                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1580                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1581
1582         if (hws->funcs.setup_vupdate_interrupt)
1583                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1584
1585         params.vertical_total_min = stream->adjust.v_total_min;
1586         params.vertical_total_max = stream->adjust.v_total_max;
1587         if (pipe_ctx->stream_res.tg->funcs->set_drr)
1588                 pipe_ctx->stream_res.tg->funcs->set_drr(
1589                         pipe_ctx->stream_res.tg, &params);
1590
1591         // DRR should set trigger event to monitor surface update event
1592         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1593                 event_triggers = 0x80;
1594         /* Event triggers and num frames initialized for DRR, but can be
1595          * later updated for PSR use. Note DRR trigger events are generated
1596          * regardless of whether num frames met.
1597          */
1598         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1599                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1600                                 pipe_ctx->stream_res.tg, event_triggers, 2);
1601
1602         if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1603                 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1604                         pipe_ctx->stream_res.stream_enc,
1605                         pipe_ctx->stream_res.tg->inst);
1606
1607         if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1608                 pipe_ctx->stream_res.stream_enc->funcs->reset_fifo)
1609                 pipe_ctx->stream_res.stream_enc->funcs->reset_fifo(
1610                         pipe_ctx->stream_res.stream_enc);
1611
1612         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1613                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);
1614
1615         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1616                         pipe_ctx->stream_res.opp,
1617                         COLOR_SPACE_YCBCR601,
1618                         stream->timing.display_color_depth,
1619                         stream->signal);
1620
1621         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1622                 pipe_ctx->stream_res.opp,
1623                 &stream->bit_depth_params,
1624                 &stream->clamping);
1625         while (odm_pipe) {
1626                 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1627                                 odm_pipe->stream_res.opp,
1628                                 COLOR_SPACE_YCBCR601,
1629                                 stream->timing.display_color_depth,
1630                                 stream->signal);
1631
1632                 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1633                                 odm_pipe->stream_res.opp,
1634                                 &stream->bit_depth_params,
1635                                 &stream->clamping);
1636                 odm_pipe = odm_pipe->next_odm_pipe;
1637         }
1638
1639         if (!stream->dpms_off)
1640                 core_link_enable_stream(context, pipe_ctx);
1641
1642 #if defined(CONFIG_DRM_AMD_DC_DCN)
1643         /* DCN3.1 FPGA Workaround
1644          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1645          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1646          * function core_link_enable_stream
1647          */
1648         if (hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)) {
1649                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1650                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1651         }
1652 #endif
1653
1654         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1655
1656         pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
1657
1658         return DC_OK;
1659 }
1660
1661 /******************************************************************************/
1662
1663 static void power_down_encoders(struct dc *dc)
1664 {
1665         int i;
1666
1667         for (i = 0; i < dc->link_count; i++) {
1668                 enum signal_type signal = dc->links[i]->connector_signal;
1669
1670                 dc_link_blank_dp_stream(dc->links[i], false);
1671
1672                 if (signal != SIGNAL_TYPE_EDP)
1673                         signal = SIGNAL_TYPE_NONE;
1674
1675                 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY)
1676                         dc->links[i]->link_enc->funcs->disable_output(
1677                                         dc->links[i]->link_enc, signal);
1678
1679                 dc->links[i]->link_status.link_active = false;
1680                 memset(&dc->links[i]->cur_link_settings, 0,
1681                                 sizeof(dc->links[i]->cur_link_settings));
1682         }
1683 }
1684
1685 static void power_down_controllers(struct dc *dc)
1686 {
1687         int i;
1688
1689         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1690                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1691                                 dc->res_pool->timing_generators[i]);
1692         }
1693 }
1694
1695 static void power_down_clock_sources(struct dc *dc)
1696 {
1697         int i;
1698
1699         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1700                 dc->res_pool->dp_clock_source) == false)
1701                 dm_error("Failed to power down pll! (dp clk src)\n");
1702
1703         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1704                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1705                                 dc->res_pool->clock_sources[i]) == false)
1706                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1707         }
1708 }
1709
1710 static void power_down_all_hw_blocks(struct dc *dc)
1711 {
1712         power_down_encoders(dc);
1713
1714         power_down_controllers(dc);
1715
1716         power_down_clock_sources(dc);
1717
1718         if (dc->fbc_compressor)
1719                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1720 }
1721
1722 static void disable_vga_and_power_gate_all_controllers(
1723                 struct dc *dc)
1724 {
1725         int i;
1726         struct timing_generator *tg;
1727         struct dc_context *ctx = dc->ctx;
1728
1729         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1730                 tg = dc->res_pool->timing_generators[i];
1731
1732                 if (tg->funcs->disable_vga)
1733                         tg->funcs->disable_vga(tg);
1734         }
1735         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1736                 /* Enable CLOCK gating for each pipe BEFORE controller
1737                  * powergating. */
1738                 enable_display_pipe_clock_gating(ctx,
1739                                 true);
1740
1741                 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1742                 dc->hwss.disable_plane(dc,
1743                         &dc->current_state->res_ctx.pipe_ctx[i]);
1744         }
1745 }
1746
1747
1748 static void get_edp_streams(struct dc_state *context,
1749                 struct dc_stream_state **edp_streams,
1750                 int *edp_stream_num)
1751 {
1752         int i;
1753
1754         *edp_stream_num = 0;
1755         for (i = 0; i < context->stream_count; i++) {
1756                 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1757                         edp_streams[*edp_stream_num] = context->streams[i];
1758                         if (++(*edp_stream_num) == MAX_NUM_EDP)
1759                                 return;
1760                 }
1761         }
1762 }
1763
1764 static void get_edp_links_with_sink(
1765                 struct dc *dc,
1766                 struct dc_link **edp_links_with_sink,
1767                 int *edp_with_sink_num)
1768 {
1769         int i;
1770
1771         /* check if there is an eDP panel not in use */
1772         *edp_with_sink_num = 0;
1773         for (i = 0; i < dc->link_count; i++) {
1774                 if (dc->links[i]->local_sink &&
1775                         dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1776                         edp_links_with_sink[*edp_with_sink_num] = dc->links[i];
1777                         if (++(*edp_with_sink_num) == MAX_NUM_EDP)
1778                                 return;
1779                 }
1780         }
1781 }
1782
1783 /*
1784  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1785  *  1. Power down all DC HW blocks
1786  *  2. Disable VGA engine on all controllers
1787  *  3. Enable power gating for controller
1788  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1789  */
1790 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1791 {
1792         struct dc_link *edp_links_with_sink[MAX_NUM_EDP];
1793         struct dc_link *edp_links[MAX_NUM_EDP];
1794         struct dc_stream_state *edp_streams[MAX_NUM_EDP];
1795         struct dc_link *edp_link_with_sink = NULL;
1796         struct dc_link *edp_link = NULL;
1797         struct dce_hwseq *hws = dc->hwseq;
1798         int edp_with_sink_num;
1799         int edp_num;
1800         int edp_stream_num;
1801         int i;
1802         bool can_apply_edp_fast_boot = false;
1803         bool can_apply_seamless_boot = false;
1804         bool keep_edp_vdd_on = false;
1805         DC_LOGGER_INIT();
1806
1807
1808         get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);
1809         get_edp_links(dc, edp_links, &edp_num);
1810
1811         if (hws->funcs.init_pipes)
1812                 hws->funcs.init_pipes(dc, context);
1813
1814         get_edp_streams(context, edp_streams, &edp_stream_num);
1815
1816         // Check fastboot support, disable on DCE8 because of blank screens
1817         if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1818                     dc->ctx->dce_version != DCE_VERSION_8_1 &&
1819                     dc->ctx->dce_version != DCE_VERSION_8_3) {
1820                 for (i = 0; i < edp_num; i++) {
1821                         edp_link = edp_links[i];
1822                         if (edp_link != edp_streams[0]->link)
1823                                 continue;
1824                         // enable fastboot if backend is enabled on eDP
1825                         if (edp_link->link_enc->funcs->is_dig_enabled &&
1826                             edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
1827                             edp_link->link_status.link_active) {
1828                                 struct dc_stream_state *edp_stream = edp_streams[0];
1829
1830                                 can_apply_edp_fast_boot = !is_edp_ilr_optimization_required(edp_stream->link, &edp_stream->timing);
1831                                 edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;
1832                                 if (can_apply_edp_fast_boot)
1833                                         DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n");
1834
1835                                 break;
1836                         }
1837                 }
1838                 // We are trying to enable eDP, don't power down VDD
1839                 if (can_apply_edp_fast_boot)
1840                         keep_edp_vdd_on = true;
1841         }
1842
1843         // Check seamless boot support
1844         for (i = 0; i < context->stream_count; i++) {
1845                 if (context->streams[i]->apply_seamless_boot_optimization) {
1846                         can_apply_seamless_boot = true;
1847                         break;
1848                 }
1849         }
1850
1851         /* eDP should not have stream in resume from S4 and so even with VBios post
1852          * it should get turned off
1853          */
1854         if (edp_with_sink_num)
1855                 edp_link_with_sink = edp_links_with_sink[0];
1856
1857         if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1858                 if (edp_link_with_sink && !keep_edp_vdd_on) {
1859                         /*turn off backlight before DP_blank and encoder powered down*/
1860                         hws->funcs.edp_backlight_control(edp_link_with_sink, false);
1861                 }
1862                 /*resume from S3, no vbios posting, no need to power down again*/
1863                 power_down_all_hw_blocks(dc);
1864                 disable_vga_and_power_gate_all_controllers(dc);
1865                 if (edp_link_with_sink && !keep_edp_vdd_on)
1866                         dc->hwss.edp_power_control(edp_link_with_sink, false);
1867         }
1868         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
1869 }
1870
1871 static uint32_t compute_pstate_blackout_duration(
1872         struct bw_fixed blackout_duration,
1873         const struct dc_stream_state *stream)
1874 {
1875         uint32_t total_dest_line_time_ns;
1876         uint32_t pstate_blackout_duration_ns;
1877
1878         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1879
1880         total_dest_line_time_ns = 1000000UL *
1881                 (stream->timing.h_total * 10) /
1882                 stream->timing.pix_clk_100hz +
1883                 pstate_blackout_duration_ns;
1884
1885         return total_dest_line_time_ns;
1886 }
1887
1888 static void dce110_set_displaymarks(
1889         const struct dc *dc,
1890         struct dc_state *context)
1891 {
1892         uint8_t i, num_pipes;
1893         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1894
1895         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1896                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1897                 uint32_t total_dest_line_time_ns;
1898
1899                 if (pipe_ctx->stream == NULL)
1900                         continue;
1901
1902                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1903                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1904                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1905                         pipe_ctx->plane_res.mi,
1906                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1907                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1908                         context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1909                         context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1910                         total_dest_line_time_ns);
1911                 if (i == underlay_idx) {
1912                         num_pipes++;
1913                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1914                                 pipe_ctx->plane_res.mi,
1915                                 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1916                                 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1917                                 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1918                                 total_dest_line_time_ns);
1919                 }
1920                 num_pipes++;
1921         }
1922 }
1923
1924 void dce110_set_safe_displaymarks(
1925                 struct resource_context *res_ctx,
1926                 const struct resource_pool *pool)
1927 {
1928         int i;
1929         int underlay_idx = pool->underlay_pipe_index;
1930         struct dce_watermarks max_marks = {
1931                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1932         struct dce_watermarks nbp_marks = {
1933                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1934         struct dce_watermarks min_marks = { 0, 0, 0, 0};
1935
1936         for (i = 0; i < MAX_PIPES; i++) {
1937                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1938                         continue;
1939
1940                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1941                                 res_ctx->pipe_ctx[i].plane_res.mi,
1942                                 nbp_marks,
1943                                 max_marks,
1944                                 min_marks,
1945                                 max_marks,
1946                                 MAX_WATERMARK);
1947
1948                 if (i == underlay_idx)
1949                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1950                                 res_ctx->pipe_ctx[i].plane_res.mi,
1951                                 nbp_marks,
1952                                 max_marks,
1953                                 max_marks,
1954                                 MAX_WATERMARK);
1955
1956         }
1957 }
1958
1959 /*******************************************************************************
1960  * Public functions
1961  ******************************************************************************/
1962
1963 static void set_drr(struct pipe_ctx **pipe_ctx,
1964                 int num_pipes, struct dc_crtc_timing_adjust adjust)
1965 {
1966         int i = 0;
1967         struct drr_params params = {0};
1968         // DRR should set trigger event to monitor surface update event
1969         unsigned int event_triggers = 0x80;
1970         // Note DRR trigger events are generated regardless of whether num frames met.
1971         unsigned int num_frames = 2;
1972
1973         params.vertical_total_max = adjust.v_total_max;
1974         params.vertical_total_min = adjust.v_total_min;
1975
1976         /* TODO: If multiple pipes are to be supported, you need
1977          * some GSL stuff. Static screen triggers may be programmed differently
1978          * as well.
1979          */
1980         for (i = 0; i < num_pipes; i++) {
1981                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1982                         pipe_ctx[i]->stream_res.tg, &params);
1983
1984                 if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
1985                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1986                                         pipe_ctx[i]->stream_res.tg,
1987                                         event_triggers, num_frames);
1988         }
1989 }
1990
1991 static void get_position(struct pipe_ctx **pipe_ctx,
1992                 int num_pipes,
1993                 struct crtc_position *position)
1994 {
1995         int i = 0;
1996
1997         /* TODO: handle pipes > 1
1998          */
1999         for (i = 0; i < num_pipes; i++)
2000                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2001 }
2002
2003 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2004                 int num_pipes, const struct dc_static_screen_params *params)
2005 {
2006         unsigned int i;
2007         unsigned int triggers = 0;
2008
2009         if (params->triggers.overlay_update)
2010                 triggers |= 0x100;
2011         if (params->triggers.surface_update)
2012                 triggers |= 0x80;
2013         if (params->triggers.cursor_update)
2014                 triggers |= 0x2;
2015         if (params->triggers.force_trigger)
2016                 triggers |= 0x1;
2017
2018         if (num_pipes) {
2019                 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
2020
2021                 if (dc->fbc_compressor)
2022                         triggers |= 0x84;
2023         }
2024
2025         for (i = 0; i < num_pipes; i++)
2026                 pipe_ctx[i]->stream_res.tg->funcs->
2027                         set_static_screen_control(pipe_ctx[i]->stream_res.tg,
2028                                         triggers, params->num_frames);
2029 }
2030
2031 /*
2032  *  Check if FBC can be enabled
2033  */
2034 static bool should_enable_fbc(struct dc *dc,
2035                 struct dc_state *context,
2036                 uint32_t *pipe_idx)
2037 {
2038         uint32_t i;
2039         struct pipe_ctx *pipe_ctx = NULL;
2040         struct resource_context *res_ctx = &context->res_ctx;
2041         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
2042
2043
2044         ASSERT(dc->fbc_compressor);
2045
2046         /* FBC memory should be allocated */
2047         if (!dc->ctx->fbc_gpu_addr)
2048                 return false;
2049
2050         /* Only supports single display */
2051         if (context->stream_count != 1)
2052                 return false;
2053
2054         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2055                 if (res_ctx->pipe_ctx[i].stream) {
2056
2057                         pipe_ctx = &res_ctx->pipe_ctx[i];
2058
2059                         if (!pipe_ctx)
2060                                 continue;
2061
2062                         /* fbc not applicable on underlay pipe */
2063                         if (pipe_ctx->pipe_idx != underlay_idx) {
2064                                 *pipe_idx = i;
2065                                 break;
2066                         }
2067                 }
2068         }
2069
2070         if (i == dc->res_pool->pipe_count)
2071                 return false;
2072
2073         if (!pipe_ctx->stream->link)
2074                 return false;
2075
2076         /* Only supports eDP */
2077         if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
2078                 return false;
2079
2080         /* PSR should not be enabled */
2081         if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
2082                 return false;
2083
2084         /* Nothing to compress */
2085         if (!pipe_ctx->plane_state)
2086                 return false;
2087
2088         /* Only for non-linear tiling */
2089         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2090                 return false;
2091
2092         return true;
2093 }
2094
2095 /*
2096  *  Enable FBC
2097  */
2098 static void enable_fbc(
2099                 struct dc *dc,
2100                 struct dc_state *context)
2101 {
2102         uint32_t pipe_idx = 0;
2103
2104         if (should_enable_fbc(dc, context, &pipe_idx)) {
2105                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
2106                 struct compr_addr_and_pitch_params params = {0, 0, 0};
2107                 struct compressor *compr = dc->fbc_compressor;
2108                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2109
2110                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
2111                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
2112                 params.inst = pipe_ctx->stream_res.tg->inst;
2113                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
2114
2115                 compr->funcs->surface_address_and_pitch(compr, &params);
2116                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
2117
2118                 compr->funcs->enable_fbc(compr, &params);
2119         }
2120 }
2121
2122 static void dce110_reset_hw_ctx_wrap(
2123                 struct dc *dc,
2124                 struct dc_state *context)
2125 {
2126         int i;
2127
2128         /* Reset old context */
2129         /* look up the targets that have been removed since last commit */
2130         for (i = 0; i < MAX_PIPES; i++) {
2131                 struct pipe_ctx *pipe_ctx_old =
2132                         &dc->current_state->res_ctx.pipe_ctx[i];
2133                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2134
2135                 /* Note: We need to disable output if clock sources change,
2136                  * since bios does optimization and doesn't apply if changing
2137                  * PHY when not already disabled.
2138                  */
2139
2140                 /* Skip underlay pipe since it will be handled in commit surface*/
2141                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
2142                         continue;
2143
2144                 if (!pipe_ctx->stream ||
2145                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2146                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2147
2148                         /* Disable if new stream is null. O/w, if stream is
2149                          * disabled already, no need to disable again.
2150                          */
2151                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
2152                                 core_link_disable_stream(pipe_ctx_old);
2153
2154                                 /* free acquired resources*/
2155                                 if (pipe_ctx_old->stream_res.audio) {
2156                                         /*disable az_endpoint*/
2157                                         pipe_ctx_old->stream_res.audio->funcs->
2158                                                         az_disable(pipe_ctx_old->stream_res.audio);
2159
2160                                         /*free audio*/
2161                                         if (dc->caps.dynamic_audio == true) {
2162                                                 /*we have to dynamic arbitrate the audio endpoints*/
2163                                                 /*we free the resource, need reset is_audio_acquired*/
2164                                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2165                                                                 pipe_ctx_old->stream_res.audio, false);
2166                                                 pipe_ctx_old->stream_res.audio = NULL;
2167                                         }
2168                                 }
2169                         }
2170
2171                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
2172                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
2173                                 dm_error("DC: failed to blank crtc!\n");
2174                                 BREAK_TO_DEBUGGER();
2175                         }
2176                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
2177                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
2178                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
2179
2180                         if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
2181                                                                                 dc->res_pool,
2182                                                                                 old_clk))
2183                                 old_clk->funcs->cs_power_down(old_clk);
2184
2185                         dc->hwss.disable_plane(dc, pipe_ctx_old);
2186
2187                         pipe_ctx_old->stream = NULL;
2188                 }
2189         }
2190 }
2191
2192 static void dce110_setup_audio_dto(
2193                 struct dc *dc,
2194                 struct dc_state *context)
2195 {
2196         int i;
2197
2198         /* program audio wall clock. use HDMI as clock source if HDMI
2199          * audio active. Otherwise, use DP as clock source
2200          * first, loop to find any HDMI audio, if not, loop find DP audio
2201          */
2202         /* Setup audio rate clock source */
2203         /* Issue:
2204         * Audio lag happened on DP monitor when unplug a HDMI monitor
2205         *
2206         * Cause:
2207         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2208         * is set to either dto0 or dto1, audio should work fine.
2209         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2210         * set to dto0 will cause audio lag.
2211         *
2212         * Solution:
2213         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2214         * find first available pipe with audio, setup audio wall DTO per topology
2215         * instead of per pipe.
2216         */
2217         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2218                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2219
2220                 if (pipe_ctx->stream == NULL)
2221                         continue;
2222
2223                 if (pipe_ctx->top_pipe)
2224                         continue;
2225                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2226                         continue;
2227                 if (pipe_ctx->stream_res.audio != NULL) {
2228                         struct audio_output audio_output;
2229
2230                         build_audio_output(context, pipe_ctx, &audio_output);
2231
2232 #if defined(CONFIG_DRM_AMD_DC_DCN)
2233                         /* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */
2234                         if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
2235                                 /* disable audio DTBCLK DTO */
2236                                 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
2237                                         dc->res_pool->dccg, 0);
2238
2239                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2240                                                 pipe_ctx->stream_res.audio,
2241                                                 pipe_ctx->stream->signal,
2242                                                 &audio_output.crtc_info,
2243                                                 &audio_output.pll_info);
2244                         } else
2245                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2246                                         pipe_ctx->stream_res.audio,
2247                                         pipe_ctx->stream->signal,
2248                                         &audio_output.crtc_info,
2249                                         &audio_output.pll_info);
2250 #else
2251                         pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2252                                 pipe_ctx->stream_res.audio,
2253                                 pipe_ctx->stream->signal,
2254                                 &audio_output.crtc_info,
2255                                 &audio_output.pll_info);
2256 #endif
2257                         break;
2258                 }
2259         }
2260
2261         /* no HDMI audio is found, try DP audio */
2262         if (i == dc->res_pool->pipe_count) {
2263                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2264                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2265
2266                         if (pipe_ctx->stream == NULL)
2267                                 continue;
2268
2269                         if (pipe_ctx->top_pipe)
2270                                 continue;
2271
2272                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2273                                 continue;
2274
2275                         if (pipe_ctx->stream_res.audio != NULL) {
2276                                 struct audio_output audio_output;
2277
2278                                 build_audio_output(context, pipe_ctx, &audio_output);
2279
2280                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2281                                         pipe_ctx->stream_res.audio,
2282                                         pipe_ctx->stream->signal,
2283                                         &audio_output.crtc_info,
2284                                         &audio_output.pll_info);
2285                                 break;
2286                         }
2287                 }
2288         }
2289 }
2290
2291 enum dc_status dce110_apply_ctx_to_hw(
2292                 struct dc *dc,
2293                 struct dc_state *context)
2294 {
2295         struct dce_hwseq *hws = dc->hwseq;
2296         struct dc_bios *dcb = dc->ctx->dc_bios;
2297         enum dc_status status;
2298         int i;
2299
2300         /* Reset old context */
2301         /* look up the targets that have been removed since last commit */
2302         hws->funcs.reset_hw_ctx_wrap(dc, context);
2303
2304         /* Skip applying if no targets */
2305         if (context->stream_count <= 0)
2306                 return DC_OK;
2307
2308         /* Apply new context */
2309         dcb->funcs->set_scratch_critical_state(dcb, true);
2310
2311         /* below is for real asic only */
2312         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2313                 struct pipe_ctx *pipe_ctx_old =
2314                                         &dc->current_state->res_ctx.pipe_ctx[i];
2315                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2316
2317                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2318                         continue;
2319
2320                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2321                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2322                                 dce_crtc_switch_to_clk_src(dc->hwseq,
2323                                                 pipe_ctx->clock_source, i);
2324                         continue;
2325                 }
2326
2327                 hws->funcs.enable_display_power_gating(
2328                                 dc, i, dc->ctx->dc_bios,
2329                                 PIPE_GATING_CONTROL_DISABLE);
2330         }
2331
2332         if (dc->fbc_compressor)
2333                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2334
2335         dce110_setup_audio_dto(dc, context);
2336
2337         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2338                 struct pipe_ctx *pipe_ctx_old =
2339                                         &dc->current_state->res_ctx.pipe_ctx[i];
2340                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2341
2342                 if (pipe_ctx->stream == NULL)
2343                         continue;
2344
2345                 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2346                         pipe_ctx->stream->link->link_state_valid) {
2347                         continue;
2348                 }
2349
2350                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2351                         continue;
2352
2353                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2354                         continue;
2355
2356                 status = apply_single_controller_ctx_to_hw(
2357                                 pipe_ctx,
2358                                 context,
2359                                 dc);
2360
2361                 if (DC_OK != status)
2362                         return status;
2363         }
2364
2365         if (dc->fbc_compressor)
2366                 enable_fbc(dc, dc->current_state);
2367
2368         dcb->funcs->set_scratch_critical_state(dcb, false);
2369
2370         return DC_OK;
2371 }
2372
2373 /*******************************************************************************
2374  * Front End programming
2375  ******************************************************************************/
2376 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2377 {
2378         struct default_adjustment default_adjust = { 0 };
2379
2380         default_adjust.force_hw_default = false;
2381         default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2382         default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2383         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2384         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2385
2386         /* display color depth */
2387         default_adjust.color_depth =
2388                 pipe_ctx->stream->timing.display_color_depth;
2389
2390         /* Lb color depth */
2391         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2392
2393         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2394                                         pipe_ctx->plane_res.xfm, &default_adjust);
2395 }
2396
2397
2398 /*******************************************************************************
2399  * In order to turn on/off specific surface we will program
2400  * Blender + CRTC
2401  *
2402  * In case that we have two surfaces and they have a different visibility
2403  * we can't turn off the CRTC since it will turn off the entire display
2404  *
2405  * |----------------------------------------------- |
2406  * |bottom pipe|curr pipe  |              |         |
2407  * |Surface    |Surface    | Blender      |  CRCT   |
2408  * |visibility |visibility | Configuration|         |
2409  * |------------------------------------------------|
2410  * |   off     |    off    | CURRENT_PIPE | blank   |
2411  * |   off     |    on     | CURRENT_PIPE | unblank |
2412  * |   on      |    off    | OTHER_PIPE   | unblank |
2413  * |   on      |    on     | BLENDING     | unblank |
2414  * -------------------------------------------------|
2415  *
2416  ******************************************************************************/
2417 static void program_surface_visibility(const struct dc *dc,
2418                 struct pipe_ctx *pipe_ctx)
2419 {
2420         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2421         bool blank_target = false;
2422
2423         if (pipe_ctx->bottom_pipe) {
2424
2425                 /* For now we are supporting only two pipes */
2426                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2427
2428                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2429                         if (pipe_ctx->plane_state->visible)
2430                                 blender_mode = BLND_MODE_BLENDING;
2431                         else
2432                                 blender_mode = BLND_MODE_OTHER_PIPE;
2433
2434                 } else if (!pipe_ctx->plane_state->visible)
2435                         blank_target = true;
2436
2437         } else if (!pipe_ctx->plane_state->visible)
2438                 blank_target = true;
2439
2440         dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2441         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2442
2443 }
2444
2445 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2446 {
2447         int i = 0;
2448         struct xfm_grph_csc_adjustment adjust;
2449         memset(&adjust, 0, sizeof(adjust));
2450         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2451
2452
2453         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2454                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2455
2456                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2457                         adjust.temperature_matrix[i] =
2458                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2459         }
2460
2461         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2462 }
2463 static void update_plane_addr(const struct dc *dc,
2464                 struct pipe_ctx *pipe_ctx)
2465 {
2466         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2467
2468         if (plane_state == NULL)
2469                 return;
2470
2471         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2472                         pipe_ctx->plane_res.mi,
2473                         &plane_state->address,
2474                         plane_state->flip_immediate);
2475
2476         plane_state->status.requested_address = plane_state->address;
2477 }
2478
2479 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2480 {
2481         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2482
2483         if (plane_state == NULL)
2484                 return;
2485
2486         plane_state->status.is_flip_pending =
2487                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2488                                         pipe_ctx->plane_res.mi);
2489
2490         if (plane_state->status.is_flip_pending && !plane_state->visible)
2491                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2492
2493         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2494         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2495                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2496                 plane_state->status.is_right_eye =\
2497                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2498         }
2499 }
2500
2501 void dce110_power_down(struct dc *dc)
2502 {
2503         power_down_all_hw_blocks(dc);
2504         disable_vga_and_power_gate_all_controllers(dc);
2505 }
2506
2507 static bool wait_for_reset_trigger_to_occur(
2508         struct dc_context *dc_ctx,
2509         struct timing_generator *tg)
2510 {
2511         bool rc = false;
2512
2513         /* To avoid endless loop we wait at most
2514          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2515         const uint32_t frames_to_wait_on_triggered_reset = 10;
2516         uint32_t i;
2517
2518         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2519
2520                 if (!tg->funcs->is_counter_moving(tg)) {
2521                         DC_ERROR("TG counter is not moving!\n");
2522                         break;
2523                 }
2524
2525                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2526                         rc = true;
2527                         /* usually occurs at i=1 */
2528                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2529                                         i);
2530                         break;
2531                 }
2532
2533                 /* Wait for one frame. */
2534                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2535                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2536         }
2537
2538         if (false == rc)
2539                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2540
2541         return rc;
2542 }
2543
2544 /* Enable timing synchronization for a group of Timing Generators. */
2545 static void dce110_enable_timing_synchronization(
2546                 struct dc *dc,
2547                 int group_index,
2548                 int group_size,
2549                 struct pipe_ctx *grouped_pipes[])
2550 {
2551         struct dc_context *dc_ctx = dc->ctx;
2552         struct dcp_gsl_params gsl_params = { 0 };
2553         int i;
2554
2555         DC_SYNC_INFO("GSL: Setting-up...\n");
2556
2557         /* Designate a single TG in the group as a master.
2558          * Since HW doesn't care which one, we always assign
2559          * the 1st one in the group. */
2560         gsl_params.gsl_group = 0;
2561         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2562
2563         for (i = 0; i < group_size; i++)
2564                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2565                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2566
2567         /* Reset slave controllers on master VSync */
2568         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2569
2570         for (i = 1 /* skip the master */; i < group_size; i++)
2571                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2572                                 grouped_pipes[i]->stream_res.tg,
2573                                 gsl_params.gsl_group);
2574
2575         for (i = 1 /* skip the master */; i < group_size; i++) {
2576                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2577                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2578                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2579                                 grouped_pipes[i]->stream_res.tg);
2580         }
2581
2582         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2583          * is that the sync'ed displays will not drift out of sync over time*/
2584         DC_SYNC_INFO("GSL: Restoring register states.\n");
2585         for (i = 0; i < group_size; i++)
2586                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2587
2588         DC_SYNC_INFO("GSL: Set-up complete.\n");
2589 }
2590
2591 static void dce110_enable_per_frame_crtc_position_reset(
2592                 struct dc *dc,
2593                 int group_size,
2594                 struct pipe_ctx *grouped_pipes[])
2595 {
2596         struct dc_context *dc_ctx = dc->ctx;
2597         struct dcp_gsl_params gsl_params = { 0 };
2598         int i;
2599
2600         gsl_params.gsl_group = 0;
2601         gsl_params.gsl_master = 0;
2602
2603         for (i = 0; i < group_size; i++)
2604                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2605                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2606
2607         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2608
2609         for (i = 1; i < group_size; i++)
2610                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2611                                 grouped_pipes[i]->stream_res.tg,
2612                                 gsl_params.gsl_master,
2613                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
2614
2615         DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2616         for (i = 1; i < group_size; i++)
2617                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2618
2619         for (i = 0; i < group_size; i++)
2620                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2621
2622 }
2623
2624 static void init_pipes(struct dc *dc, struct dc_state *context)
2625 {
2626         // Do nothing
2627 }
2628
2629 static void init_hw(struct dc *dc)
2630 {
2631         int i;
2632         struct dc_bios *bp;
2633         struct transform *xfm;
2634         struct abm *abm;
2635         struct dmcu *dmcu;
2636         struct dce_hwseq *hws = dc->hwseq;
2637         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
2638
2639         bp = dc->ctx->dc_bios;
2640         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2641                 xfm = dc->res_pool->transforms[i];
2642                 xfm->funcs->transform_reset(xfm);
2643
2644                 hws->funcs.enable_display_power_gating(
2645                                 dc, i, bp,
2646                                 PIPE_GATING_CONTROL_INIT);
2647                 hws->funcs.enable_display_power_gating(
2648                                 dc, i, bp,
2649                                 PIPE_GATING_CONTROL_DISABLE);
2650                 hws->funcs.enable_display_pipe_clock_gating(
2651                         dc->ctx,
2652                         true);
2653         }
2654
2655         dce_clock_gating_power_up(dc->hwseq, false);
2656         /***************************************/
2657
2658         for (i = 0; i < dc->link_count; i++) {
2659                 /****************************************/
2660                 /* Power up AND update implementation according to the
2661                  * required signal (which may be different from the
2662                  * default signal on connector). */
2663                 struct dc_link *link = dc->links[i];
2664
2665                 link->link_enc->funcs->hw_init(link->link_enc);
2666         }
2667
2668         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2669                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2670
2671                 tg->funcs->disable_vga(tg);
2672
2673                 /* Blank controller using driver code instead of
2674                  * command table. */
2675                 tg->funcs->set_blank(tg, true);
2676                 hwss_wait_for_blank_complete(tg);
2677         }
2678
2679         for (i = 0; i < dc->res_pool->audio_count; i++) {
2680                 struct audio *audio = dc->res_pool->audios[i];
2681                 audio->funcs->hw_init(audio);
2682         }
2683
2684         for (i = 0; i < dc->link_count; i++) {
2685                 struct dc_link *link = dc->links[i];
2686
2687                 if (link->panel_cntl)
2688                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
2689         }
2690
2691         abm = dc->res_pool->abm;
2692         if (abm != NULL)
2693                 abm->funcs->abm_init(abm, backlight);
2694
2695         dmcu = dc->res_pool->dmcu;
2696         if (dmcu != NULL && abm != NULL)
2697                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2698
2699         if (dc->fbc_compressor)
2700                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2701
2702 }
2703
2704
2705 void dce110_prepare_bandwidth(
2706                 struct dc *dc,
2707                 struct dc_state *context)
2708 {
2709         struct clk_mgr *dccg = dc->clk_mgr;
2710
2711         dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2712
2713         dccg->funcs->update_clocks(
2714                         dccg,
2715                         context,
2716                         false);
2717 }
2718
2719 void dce110_optimize_bandwidth(
2720                 struct dc *dc,
2721                 struct dc_state *context)
2722 {
2723         struct clk_mgr *dccg = dc->clk_mgr;
2724
2725         dce110_set_displaymarks(dc, context);
2726
2727         dccg->funcs->update_clocks(
2728                         dccg,
2729                         context,
2730                         true);
2731 }
2732
2733 static void dce110_program_front_end_for_pipe(
2734                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2735 {
2736         struct mem_input *mi = pipe_ctx->plane_res.mi;
2737         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2738         struct xfm_grph_csc_adjustment adjust;
2739         struct out_csc_color_matrix tbl_entry;
2740         unsigned int i;
2741         struct dce_hwseq *hws = dc->hwseq;
2742
2743         DC_LOGGER_INIT();
2744         memset(&tbl_entry, 0, sizeof(tbl_entry));
2745
2746         memset(&adjust, 0, sizeof(adjust));
2747         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2748
2749         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2750
2751         set_default_colors(pipe_ctx);
2752         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2753                         == true) {
2754                 tbl_entry.color_space =
2755                         pipe_ctx->stream->output_color_space;
2756
2757                 for (i = 0; i < 12; i++)
2758                         tbl_entry.regval[i] =
2759                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2760
2761                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2762                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2763         }
2764
2765         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2766                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2767
2768                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2769                         adjust.temperature_matrix[i] =
2770                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2771         }
2772
2773         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2774
2775         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2776
2777         program_scaler(dc, pipe_ctx);
2778
2779         mi->funcs->mem_input_program_surface_config(
2780                         mi,
2781                         plane_state->format,
2782                         &plane_state->tiling_info,
2783                         &plane_state->plane_size,
2784                         plane_state->rotation,
2785                         NULL,
2786                         false);
2787         if (mi->funcs->set_blank)
2788                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2789
2790         if (dc->config.gpu_vm_support)
2791                 mi->funcs->mem_input_program_pte_vm(
2792                                 pipe_ctx->plane_res.mi,
2793                                 plane_state->format,
2794                                 &plane_state->tiling_info,
2795                                 plane_state->rotation);
2796
2797         /* Moved programming gamma from dc to hwss */
2798         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2799                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2800                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2801                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2802
2803         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2804                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2805
2806         DC_LOG_SURFACE(
2807                         "Pipe:%d %p: addr hi:0x%x, "
2808                         "addr low:0x%x, "
2809                         "src: %d, %d, %d,"
2810                         " %d; dst: %d, %d, %d, %d;"
2811                         "clip: %d, %d, %d, %d\n",
2812                         pipe_ctx->pipe_idx,
2813                         (void *) pipe_ctx->plane_state,
2814                         pipe_ctx->plane_state->address.grph.addr.high_part,
2815                         pipe_ctx->plane_state->address.grph.addr.low_part,
2816                         pipe_ctx->plane_state->src_rect.x,
2817                         pipe_ctx->plane_state->src_rect.y,
2818                         pipe_ctx->plane_state->src_rect.width,
2819                         pipe_ctx->plane_state->src_rect.height,
2820                         pipe_ctx->plane_state->dst_rect.x,
2821                         pipe_ctx->plane_state->dst_rect.y,
2822                         pipe_ctx->plane_state->dst_rect.width,
2823                         pipe_ctx->plane_state->dst_rect.height,
2824                         pipe_ctx->plane_state->clip_rect.x,
2825                         pipe_ctx->plane_state->clip_rect.y,
2826                         pipe_ctx->plane_state->clip_rect.width,
2827                         pipe_ctx->plane_state->clip_rect.height);
2828
2829         DC_LOG_SURFACE(
2830                         "Pipe %d: width, height, x, y\n"
2831                         "viewport:%d, %d, %d, %d\n"
2832                         "recout:  %d, %d, %d, %d\n",
2833                         pipe_ctx->pipe_idx,
2834                         pipe_ctx->plane_res.scl_data.viewport.width,
2835                         pipe_ctx->plane_res.scl_data.viewport.height,
2836                         pipe_ctx->plane_res.scl_data.viewport.x,
2837                         pipe_ctx->plane_res.scl_data.viewport.y,
2838                         pipe_ctx->plane_res.scl_data.recout.width,
2839                         pipe_ctx->plane_res.scl_data.recout.height,
2840                         pipe_ctx->plane_res.scl_data.recout.x,
2841                         pipe_ctx->plane_res.scl_data.recout.y);
2842 }
2843
2844 static void dce110_apply_ctx_for_surface(
2845                 struct dc *dc,
2846                 const struct dc_stream_state *stream,
2847                 int num_planes,
2848                 struct dc_state *context)
2849 {
2850         int i;
2851
2852         if (num_planes == 0)
2853                 return;
2854
2855         if (dc->fbc_compressor)
2856                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2857
2858         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2859                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2860
2861                 if (pipe_ctx->stream != stream)
2862                         continue;
2863
2864                 /* Need to allocate mem before program front end for Fiji */
2865                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2866                                 pipe_ctx->plane_res.mi,
2867                                 pipe_ctx->stream->timing.h_total,
2868                                 pipe_ctx->stream->timing.v_total,
2869                                 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2870                                 context->stream_count);
2871
2872                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2873
2874                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2875
2876                 program_surface_visibility(dc, pipe_ctx);
2877
2878         }
2879
2880         if (dc->fbc_compressor)
2881                 enable_fbc(dc, context);
2882 }
2883
2884 static void dce110_post_unlock_program_front_end(
2885                 struct dc *dc,
2886                 struct dc_state *context)
2887 {
2888 }
2889
2890 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2891 {
2892         struct dce_hwseq *hws = dc->hwseq;
2893         int fe_idx = pipe_ctx->plane_res.mi ?
2894                 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2895
2896         /* Do not power down fe when stream is active on dce*/
2897         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2898                 return;
2899
2900         hws->funcs.enable_display_power_gating(
2901                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2902
2903         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2904                                 dc->res_pool->transforms[fe_idx]);
2905 }
2906
2907 static void dce110_wait_for_mpcc_disconnect(
2908                 struct dc *dc,
2909                 struct resource_pool *res_pool,
2910                 struct pipe_ctx *pipe_ctx)
2911 {
2912         /* do nothing*/
2913 }
2914
2915 static void program_output_csc(struct dc *dc,
2916                 struct pipe_ctx *pipe_ctx,
2917                 enum dc_color_space colorspace,
2918                 uint16_t *matrix,
2919                 int opp_id)
2920 {
2921         int i;
2922         struct out_csc_color_matrix tbl_entry;
2923
2924         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2925                 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2926
2927                 for (i = 0; i < 12; i++)
2928                         tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2929
2930                 tbl_entry.color_space = color_space;
2931
2932                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2933                                 pipe_ctx->plane_res.xfm, &tbl_entry);
2934         }
2935 }
2936
2937 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2938 {
2939         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2940         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2941         struct mem_input *mi = pipe_ctx->plane_res.mi;
2942         struct dc_cursor_mi_param param = {
2943                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2944                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2945                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2946                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2947                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2948                 .rotation = pipe_ctx->plane_state->rotation,
2949                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2950         };
2951
2952         /**
2953          * If the cursor's source viewport is clipped then we need to
2954          * translate the cursor to appear in the correct position on
2955          * the screen.
2956          *
2957          * This translation isn't affected by scaling so it needs to be
2958          * done *after* we adjust the position for the scale factor.
2959          *
2960          * This is only done by opt-in for now since there are still
2961          * some usecases like tiled display that might enable the
2962          * cursor on both streams while expecting dc to clip it.
2963          */
2964         if (pos_cpy.translate_by_source) {
2965                 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;
2966                 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;
2967         }
2968
2969         if (pipe_ctx->plane_state->address.type
2970                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2971                 pos_cpy.enable = false;
2972
2973         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2974                 pos_cpy.enable = false;
2975
2976         if (ipp->funcs->ipp_cursor_set_position)
2977                 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2978         if (mi->funcs->set_cursor_position)
2979                 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2980 }
2981
2982 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2983 {
2984         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2985
2986         if (pipe_ctx->plane_res.ipp &&
2987             pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2988                 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2989                                 pipe_ctx->plane_res.ipp, attributes);
2990
2991         if (pipe_ctx->plane_res.mi &&
2992             pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2993                 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2994                                 pipe_ctx->plane_res.mi, attributes);
2995
2996         if (pipe_ctx->plane_res.xfm &&
2997             pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2998                 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2999                                 pipe_ctx->plane_res.xfm, attributes);
3000 }
3001
3002 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
3003                 uint32_t backlight_pwm_u16_16,
3004                 uint32_t frame_ramp)
3005 {
3006         struct dc_link *link = pipe_ctx->stream->link;
3007         struct dc  *dc = link->ctx->dc;
3008         struct abm *abm = pipe_ctx->stream_res.abm;
3009         struct panel_cntl *panel_cntl = link->panel_cntl;
3010         struct dmcu *dmcu = dc->res_pool->dmcu;
3011         bool fw_set_brightness = true;
3012         /* DMCU -1 for all controller id values,
3013          * therefore +1 here
3014          */
3015         uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
3016
3017         if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
3018                 return false;
3019
3020         if (dmcu)
3021                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
3022
3023         if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)
3024                 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);
3025         else
3026                 abm->funcs->set_backlight_level_pwm(
3027                                 abm,
3028                                 backlight_pwm_u16_16,
3029                                 frame_ramp,
3030                                 controller_id,
3031                                 link->panel_cntl->inst);
3032
3033         return true;
3034 }
3035
3036 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
3037 {
3038         struct abm *abm = pipe_ctx->stream_res.abm;
3039         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3040
3041         if (abm)
3042                 abm->funcs->set_abm_immediate_disable(abm,
3043                                 pipe_ctx->stream->link->panel_cntl->inst);
3044
3045         if (panel_cntl)
3046                 panel_cntl->funcs->store_backlight_level(panel_cntl);
3047 }
3048
3049 void dce110_set_pipe(struct pipe_ctx *pipe_ctx)
3050 {
3051         struct abm *abm = pipe_ctx->stream_res.abm;
3052         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3053         uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;
3054
3055         if (abm && panel_cntl)
3056                 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);
3057 }
3058
3059 static const struct hw_sequencer_funcs dce110_funcs = {
3060         .program_gamut_remap = program_gamut_remap,
3061         .program_output_csc = program_output_csc,
3062         .init_hw = init_hw,
3063         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
3064         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
3065         .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
3066         .update_plane_addr = update_plane_addr,
3067         .update_pending_status = dce110_update_pending_status,
3068         .enable_accelerated_mode = dce110_enable_accelerated_mode,
3069         .enable_timing_synchronization = dce110_enable_timing_synchronization,
3070         .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
3071         .update_info_frame = dce110_update_info_frame,
3072         .enable_stream = dce110_enable_stream,
3073         .disable_stream = dce110_disable_stream,
3074         .unblank_stream = dce110_unblank_stream,
3075         .blank_stream = dce110_blank_stream,
3076         .enable_audio_stream = dce110_enable_audio_stream,
3077         .disable_audio_stream = dce110_disable_audio_stream,
3078         .disable_plane = dce110_power_down_fe,
3079         .pipe_control_lock = dce_pipe_control_lock,
3080         .interdependent_update_lock = NULL,
3081         .cursor_lock = dce_pipe_control_lock,
3082         .prepare_bandwidth = dce110_prepare_bandwidth,
3083         .optimize_bandwidth = dce110_optimize_bandwidth,
3084         .set_drr = set_drr,
3085         .get_position = get_position,
3086         .set_static_screen_control = set_static_screen_control,
3087         .setup_stereo = NULL,
3088         .set_avmute = dce110_set_avmute,
3089         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
3090         .edp_backlight_control = dce110_edp_backlight_control,
3091         .edp_power_control = dce110_edp_power_control,
3092         .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
3093         .set_cursor_position = dce110_set_cursor_position,
3094         .set_cursor_attribute = dce110_set_cursor_attribute,
3095         .set_backlight_level = dce110_set_backlight_level,
3096         .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
3097         .set_pipe = dce110_set_pipe,
3098 };
3099
3100 static const struct hwseq_private_funcs dce110_private_funcs = {
3101         .init_pipes = init_pipes,
3102         .update_plane_addr = update_plane_addr,
3103         .set_input_transfer_func = dce110_set_input_transfer_func,
3104         .set_output_transfer_func = dce110_set_output_transfer_func,
3105         .power_down = dce110_power_down,
3106         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
3107         .enable_display_power_gating = dce110_enable_display_power_gating,
3108         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
3109         .enable_stream_timing = dce110_enable_stream_timing,
3110         .disable_stream_gating = NULL,
3111         .enable_stream_gating = NULL,
3112         .edp_backlight_control = dce110_edp_backlight_control,
3113 };
3114
3115 void dce110_hw_sequencer_construct(struct dc *dc)
3116 {
3117         dc->hwss = dce110_funcs;
3118         dc->hwseq->funcs = dce110_private_funcs;
3119 }
3120