drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27
  28 #include "dc_bios_types.h"
  29 #include "dce_stream_encoder.h"
  30 #include "reg_helper.h"
  31 #include "hw_shared.h"
  32
  33 #define DC_LOGGER \
  34                 enc110->base.ctx->logger
  35
  36
  37 #define REG(reg)\
  38         (enc110->regs->reg)
  39
  40 #undef FN
  41 #define FN(reg_name, field_name) \
  42         enc110->se_shift->field_name, enc110->se_mask->field_name
  43
  44 #define VBI_LINE_0 0
  45 #define DP_BLANK_MAX_RETRY 20
  46 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
  47
  48 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
  49         #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK       0x00000010L
  50         #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK         0x00000300L
  51         #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT     0x00000004
  52         #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT       0x00000008
  53 #endif
  54
  55 enum {
  56         DP_MST_UPDATE_MAX_RETRY = 50
  57 };
  58
  59 #define DCE110_SE(audio)\
  60         container_of(audio, struct dce110_stream_encoder, base)
  61
  62 #define CTX \
  63         enc110->base.ctx
  64
  65 static void dce110_update_generic_info_packet(
  66         struct dce110_stream_encoder *enc110,
  67         uint32_t packet_index,
  68         const struct dc_info_packet *info_packet)
  69 {
  70         uint32_t regval;
  71         /* TODOFPGA Figure out a proper number for max_retries polling for lock
  72          * use 50 for now.
  73          */
  74         uint32_t max_retries = 50;
  75
  76         /*we need turn on clock before programming AFMT block*/
  77         if (REG(AFMT_CNTL))
  78                 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
  79
  80         if (REG(AFMT_VBI_PACKET_CONTROL1)) {
  81                 if (packet_index >= 8)
  82                         ASSERT(0);
  83
  84                 /* poll dig_update_lock is not locked -> asic internal signal
  85                  * assume otg master lock will unlock it
  86                  */
  87 /*              REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
  88                                 0, 10, max_retries);*/
  89
  90                 /* check if HW reading GSP memory */
  91                 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
  92                                 0, 10, max_retries);
  93
  94                 /* HW does is not reading GSP memory not reading too long ->
  95                  * something wrong. clear GPS memory access and notify?
  96                  * hw SW is writing to GSP memory
  97                  */
  98                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
  99         }
 100         /* choose which generic packet to use */
 101         {
 102                 regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
 103                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
 104                                 AFMT_GENERIC_INDEX, packet_index);
 105         }
 106
 107         /* write generic packet header
 108          * (4th byte is for GENERIC0 only) */
 109         {
 110                 REG_SET_4(AFMT_GENERIC_HDR, 0,
 111                                 AFMT_GENERIC_HB0, info_packet->hb0,
 112                                 AFMT_GENERIC_HB1, info_packet->hb1,
 113                                 AFMT_GENERIC_HB2, info_packet->hb2,
 114                                 AFMT_GENERIC_HB3, info_packet->hb3);
 115         }
 116
 117         /* write generic packet contents
 118          * (we never use last 4 bytes)
 119          * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
 120         {
 121                 const uint32_t *content =
 122                         (const uint32_t *) &info_packet->sb[0];
 123
 124                 REG_WRITE(AFMT_GENERIC_0, *content++);
 125                 REG_WRITE(AFMT_GENERIC_1, *content++);
 126                 REG_WRITE(AFMT_GENERIC_2, *content++);
 127                 REG_WRITE(AFMT_GENERIC_3, *content++);
 128                 REG_WRITE(AFMT_GENERIC_4, *content++);
 129                 REG_WRITE(AFMT_GENERIC_5, *content++);
 130                 REG_WRITE(AFMT_GENERIC_6, *content++);
 131                 REG_WRITE(AFMT_GENERIC_7, *content);
 132         }
 133
 134         if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
 135                 /* force double-buffered packet update */
 136                 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
 137                         AFMT_GENERIC0_UPDATE, (packet_index == 0),
 138                         AFMT_GENERIC2_UPDATE, (packet_index == 2));
 139         }
 140 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 141         if (REG(AFMT_VBI_PACKET_CONTROL1)) {
 142                 switch (packet_index) {
 143                 case 0:
 144                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 145                                         AFMT_GENERIC0_FRAME_UPDATE, 1);
 146                         break;
 147                 case 1:
 148                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 149                                         AFMT_GENERIC1_FRAME_UPDATE, 1);
 150                         break;
 151                 case 2:
 152                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 153                                         AFMT_GENERIC2_FRAME_UPDATE, 1);
 154                         break;
 155                 case 3:
 156                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 157                                         AFMT_GENERIC3_FRAME_UPDATE, 1);
 158                         break;
 159                 case 4:
 160                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 161                                         AFMT_GENERIC4_FRAME_UPDATE, 1);
 162                         break;
 163                 case 5:
 164                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 165                                         AFMT_GENERIC5_FRAME_UPDATE, 1);
 166                         break;
 167                 case 6:
 168                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 169                                         AFMT_GENERIC6_FRAME_UPDATE, 1);
 170                         break;
 171                 case 7:
 172                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 173                                         AFMT_GENERIC7_FRAME_UPDATE, 1);
 174                         break;
 175                 default:
 176                         break;
 177                 }
 178         }
 179 #endif
 180 }
 181
 182 static void dce110_update_hdmi_info_packet(
 183         struct dce110_stream_encoder *enc110,
 184         uint32_t packet_index,
 185         const struct dc_info_packet *info_packet)
 186 {
 187         uint32_t cont, send, line;
 188
 189         if (info_packet->valid) {
 190                 dce110_update_generic_info_packet(
 191                         enc110,
 192                         packet_index,
 193                         info_packet);
 194
 195                 /* enable transmission of packet(s) -
 196                  * packet transmission begins on the next frame */
 197                 cont = 1;
 198                 /* send packet(s) every frame */
 199                 send = 1;
 200                 /* select line number to send packets on */
 201                 line = 2;
 202         } else {
 203                 cont = 0;
 204                 send = 0;
 205                 line = 0;
 206         }
 207
 208         /* choose which generic packet control to use */
 209         switch (packet_index) {
 210         case 0:
 211                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 212                                 HDMI_GENERIC0_CONT, cont,
 213                                 HDMI_GENERIC0_SEND, send,
 214                                 HDMI_GENERIC0_LINE, line);
 215                 break;
 216         case 1:
 217                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 218                                 HDMI_GENERIC1_CONT, cont,
 219                                 HDMI_GENERIC1_SEND, send,
 220                                 HDMI_GENERIC1_LINE, line);
 221                 break;
 222         case 2:
 223                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 224                                 HDMI_GENERIC0_CONT, cont,
 225                                 HDMI_GENERIC0_SEND, send,
 226                                 HDMI_GENERIC0_LINE, line);
 227                 break;
 228         case 3:
 229                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 230                                 HDMI_GENERIC1_CONT, cont,
 231                                 HDMI_GENERIC1_SEND, send,
 232                                 HDMI_GENERIC1_LINE, line);
 233                 break;
 234 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 235         case 4:
 236                 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 237                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 238                                         HDMI_GENERIC0_CONT, cont,
 239                                         HDMI_GENERIC0_SEND, send,
 240                                         HDMI_GENERIC0_LINE, line);
 241                 break;
 242         case 5:
 243                 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 244                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 245                                         HDMI_GENERIC1_CONT, cont,
 246                                         HDMI_GENERIC1_SEND, send,
 247                                         HDMI_GENERIC1_LINE, line);
 248                 break;
 249         case 6:
 250                 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 251                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 252                                         HDMI_GENERIC0_CONT, cont,
 253                                         HDMI_GENERIC0_SEND, send,
 254                                         HDMI_GENERIC0_LINE, line);
 255                 break;
 256         case 7:
 257                 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 258                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 259                                         HDMI_GENERIC1_CONT, cont,
 260                                         HDMI_GENERIC1_SEND, send,
 261                                         HDMI_GENERIC1_LINE, line);
 262                 break;
 263 #endif
 264         default:
 265                 /* invalid HW packet index */
 266                 DC_LOG_WARNING(
 267                         "Invalid HW packet index: %s()\n",
 268                         __func__);
 269                 return;
 270         }
 271 }
 272
 273 /* setup stream encoder in dp mode */
 274 static void dce110_stream_encoder_dp_set_stream_attribute(
 275         struct stream_encoder *enc,
 276         struct dc_crtc_timing *crtc_timing,
 277         enum dc_color_space output_color_space,
 278         bool use_vsc_sdp_for_colorimetry,
 279         uint32_t enable_sdp_splitting)
 280 {
 281 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 282         uint32_t h_active_start;
 283         uint32_t v_active_start;
 284         uint32_t misc0 = 0;
 285         uint32_t misc1 = 0;
 286         uint32_t h_blank;
 287         uint32_t h_back_porch;
 288         uint8_t synchronous_clock = 0; /* asynchronous mode */
 289         uint8_t colorimetry_bpc;
 290         uint8_t dynamic_range_rgb = 0; /*full range*/
 291         uint8_t dynamic_range_ycbcr = 1; /*bt709*/
 292 #endif
 293
 294         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 295         struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
 296         if (hw_crtc_timing.flags.INTERLACE) {
 297                 /*the input timing is in VESA spec format with Interlace flag =1*/
 298                 hw_crtc_timing.v_total /= 2;
 299                 hw_crtc_timing.v_border_top /= 2;
 300                 hw_crtc_timing.v_addressable /= 2;
 301                 hw_crtc_timing.v_border_bottom /= 2;
 302                 hw_crtc_timing.v_front_porch /= 2;
 303                 hw_crtc_timing.v_sync_width /= 2;
 304         }
 305         /* set pixel encoding */
 306         switch (hw_crtc_timing.pixel_encoding) {
 307         case PIXEL_ENCODING_YCBCR422:
 308                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 309                                 DP_PIXEL_ENCODING_TYPE_YCBCR422);
 310                 break;
 311         case PIXEL_ENCODING_YCBCR444:
 312                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 313                                 DP_PIXEL_ENCODING_TYPE_YCBCR444);
 314
 315                 if (hw_crtc_timing.flags.Y_ONLY)
 316                         if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
 317                                 /* HW testing only, no use case yet.
 318                                  * Color depth of Y-only could be
 319                                  * 8, 10, 12, 16 bits */
 320                                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 321                                                 DP_PIXEL_ENCODING_TYPE_Y_ONLY);
 322                 /* Note: DP_MSA_MISC1 bit 7 is the indicator
 323                  * of Y-only mode.
 324                  * This bit is set in HW if register
 325                  * DP_PIXEL_ENCODING is programmed to 0x4 */
 326                 break;
 327         case PIXEL_ENCODING_YCBCR420:
 328                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 329                                 DP_PIXEL_ENCODING_TYPE_YCBCR420);
 330                 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
 331                         REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
 332
 333 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 334                 if (enc110->se_mask->DP_VID_N_MUL)
 335                         REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
 336 #endif
 337                 break;
 338         default:
 339                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 340                                 DP_PIXEL_ENCODING_TYPE_RGB444);
 341                 break;
 342         }
 343
 344 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 345         if (REG(DP_MSA_MISC))
 346                 misc1 = REG_READ(DP_MSA_MISC);
 347 #endif
 348
 349         /* set color depth */
 350
 351         switch (hw_crtc_timing.display_color_depth) {
 352         case COLOR_DEPTH_666:
 353                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 354                                 0);
 355                 break;
 356         case COLOR_DEPTH_888:
 357                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 358                                 DP_COMPONENT_PIXEL_DEPTH_8BPC);
 359                 break;
 360         case COLOR_DEPTH_101010:
 361                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 362                                 DP_COMPONENT_PIXEL_DEPTH_10BPC);
 363
 364                 break;
 365         case COLOR_DEPTH_121212:
 366                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 367                                 DP_COMPONENT_PIXEL_DEPTH_12BPC);
 368                 break;
 369         default:
 370                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 371                                 DP_COMPONENT_PIXEL_DEPTH_6BPC);
 372                 break;
 373         }
 374
 375         /* set dynamic range and YCbCr range */
 376
 377
 378 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 379         switch (hw_crtc_timing.display_color_depth) {
 380         case COLOR_DEPTH_666:
 381                 colorimetry_bpc = 0;
 382                 break;
 383         case COLOR_DEPTH_888:
 384                 colorimetry_bpc = 1;
 385                 break;
 386         case COLOR_DEPTH_101010:
 387                 colorimetry_bpc = 2;
 388                 break;
 389         case COLOR_DEPTH_121212:
 390                 colorimetry_bpc = 3;
 391                 break;
 392         default:
 393                 colorimetry_bpc = 0;
 394                 break;
 395         }
 396
 397         misc0 = misc0 | synchronous_clock;
 398         misc0 = colorimetry_bpc << 5;
 399
 400         if (REG(DP_MSA_TIMING_PARAM1)) {
 401                 switch (output_color_space) {
 402                 case COLOR_SPACE_SRGB:
 403                         misc0 = misc0 | 0x0;
 404                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 405                         dynamic_range_rgb = 0; /*full range*/
 406                         break;
 407                 case COLOR_SPACE_SRGB_LIMITED:
 408                         misc0 = misc0 | 0x8; /* bit3=1 */
 409                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 410                         dynamic_range_rgb = 1; /*limited range*/
 411                         break;
 412                 case COLOR_SPACE_YCBCR601:
 413                 case COLOR_SPACE_YCBCR601_LIMITED:
 414                         misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
 415                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 416                         dynamic_range_ycbcr = 0; /*bt601*/
 417                         if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 418                                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 419                         else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
 420                                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 421                         break;
 422                 case COLOR_SPACE_YCBCR709:
 423                 case COLOR_SPACE_YCBCR709_LIMITED:
 424                 case COLOR_SPACE_YCBCR709_BLACK:
 425                         misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
 426                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 427                         dynamic_range_ycbcr = 1; /*bt709*/
 428                         if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 429                                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 430                         else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
 431                                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 432                         break;
 433                 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 434                         dynamic_range_rgb = 1; /*limited range*/
 435                         break;
 436                 case COLOR_SPACE_2020_RGB_FULLRANGE:
 437                 case COLOR_SPACE_2020_YCBCR:
 438                 case COLOR_SPACE_XR_RGB:
 439                 case COLOR_SPACE_MSREF_SCRGB:
 440                 case COLOR_SPACE_ADOBERGB:
 441                 case COLOR_SPACE_DCIP3:
 442                 case COLOR_SPACE_XV_YCC_709:
 443                 case COLOR_SPACE_XV_YCC_601:
 444                 case COLOR_SPACE_DISPLAYNATIVE:
 445                 case COLOR_SPACE_DOLBYVISION:
 446                 case COLOR_SPACE_APPCTRL:
 447                 case COLOR_SPACE_CUSTOMPOINTS:
 448                 case COLOR_SPACE_UNKNOWN:
 449                         /* do nothing */
 450                         break;
 451                 }
 452                 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
 453                         REG_UPDATE_2(
 454                                 DP_PIXEL_FORMAT,
 455                                 DP_DYN_RANGE, dynamic_range_rgb,
 456                                 DP_YCBCR_RANGE, dynamic_range_ycbcr);
 457
 458 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 459                 if (REG(DP_MSA_COLORIMETRY))
 460                         REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
 461
 462                 if (REG(DP_MSA_MISC))
 463                         REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
 464
 465         /* dcn new register
 466          * dc_crtc_timing is vesa dmt struct. data from edid
 467          */
 468                 if (REG(DP_MSA_TIMING_PARAM1))
 469                         REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
 470                                         DP_MSA_HTOTAL, hw_crtc_timing.h_total,
 471                                         DP_MSA_VTOTAL, hw_crtc_timing.v_total);
 472 #endif
 473
 474                 /* calcuate from vesa timing parameters
 475                  * h_active_start related to leading edge of sync
 476                  */
 477
 478                 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
 479                                 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
 480
 481                 h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
 482                                 hw_crtc_timing.h_sync_width;
 483
 484                 /* start at begining of left border */
 485                 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
 486
 487
 488                 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
 489                                 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
 490                                 hw_crtc_timing.v_front_porch;
 491
 492
 493 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 494                 /* start at begining of left border */
 495                 if (REG(DP_MSA_TIMING_PARAM2))
 496                         REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
 497                                 DP_MSA_HSTART, h_active_start,
 498                                 DP_MSA_VSTART, v_active_start);
 499
 500                 if (REG(DP_MSA_TIMING_PARAM3))
 501                         REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
 502                                         DP_MSA_HSYNCWIDTH,
 503                                         hw_crtc_timing.h_sync_width,
 504                                         DP_MSA_HSYNCPOLARITY,
 505                                         !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
 506                                         DP_MSA_VSYNCWIDTH,
 507                                         hw_crtc_timing.v_sync_width,
 508                                         DP_MSA_VSYNCPOLARITY,
 509                                         !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
 510
 511                 /* HWDITH include border or overscan */
 512                 if (REG(DP_MSA_TIMING_PARAM4))
 513                         REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
 514                                 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
 515                                 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
 516                                 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
 517                                 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
 518 #endif
 519         }
 520 #endif
 521 }
 522
 523 static void dce110_stream_encoder_set_stream_attribute_helper(
 524                 struct dce110_stream_encoder *enc110,
 525                 struct dc_crtc_timing *crtc_timing)
 526 {
 527         if (enc110->regs->TMDS_CNTL) {
 528                 switch (crtc_timing->pixel_encoding) {
 529                 case PIXEL_ENCODING_YCBCR422:
 530                         REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
 531                         break;
 532                 default:
 533                         REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
 534                         break;
 535                 }
 536                 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
 537         } else if (enc110->regs->DIG_FE_CNTL) {
 538                 switch (crtc_timing->pixel_encoding) {
 539                 case PIXEL_ENCODING_YCBCR422:
 540                         REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
 541                         break;
 542                 default:
 543                         REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
 544                         break;
 545                 }
 546                 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
 547         }
 548
 549 }
 550
 551 /* setup stream encoder in hdmi mode */
 552 static void dce110_stream_encoder_hdmi_set_stream_attribute(
 553         struct stream_encoder *enc,
 554         struct dc_crtc_timing *crtc_timing,
 555         int actual_pix_clk_khz,
 556         bool enable_audio)
 557 {
 558         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 559         struct bp_encoder_control cntl = {0};
 560
 561         cntl.action = ENCODER_CONTROL_SETUP;
 562         cntl.engine_id = enc110->base.id;
 563         cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 564         cntl.enable_dp_audio = enable_audio;
 565         cntl.pixel_clock = actual_pix_clk_khz;
 566         cntl.lanes_number = LANE_COUNT_FOUR;
 567
 568         if (enc110->base.bp->funcs->encoder_control(
 569                         enc110->base.bp, &cntl) != BP_RESULT_OK)
 570                 return;
 571
 572         dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
 573
 574         /* setup HDMI engine */
 575         if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
 576                 REG_UPDATE_3(HDMI_CONTROL,
 577                         HDMI_PACKET_GEN_VERSION, 1,
 578                         HDMI_KEEPOUT_MODE, 1,
 579                         HDMI_DEEP_COLOR_ENABLE, 0);
 580         } else if (enc110->regs->DIG_FE_CNTL) {
 581                 REG_UPDATE_5(HDMI_CONTROL,
 582                         HDMI_PACKET_GEN_VERSION, 1,
 583                         HDMI_KEEPOUT_MODE, 1,
 584                         HDMI_DEEP_COLOR_ENABLE, 0,
 585                         HDMI_DATA_SCRAMBLE_EN, 0,
 586                         HDMI_CLOCK_CHANNEL_RATE, 0);
 587         }
 588
 589         switch (crtc_timing->display_color_depth) {
 590         case COLOR_DEPTH_888:
 591                 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
 592                 break;
 593         case COLOR_DEPTH_101010:
 594                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 595                         REG_UPDATE_2(HDMI_CONTROL,
 596                                         HDMI_DEEP_COLOR_DEPTH, 1,
 597                                         HDMI_DEEP_COLOR_ENABLE, 0);
 598                 } else {
 599                         REG_UPDATE_2(HDMI_CONTROL,
 600                                         HDMI_DEEP_COLOR_DEPTH, 1,
 601                                         HDMI_DEEP_COLOR_ENABLE, 1);
 602                         }
 603                 break;
 604         case COLOR_DEPTH_121212:
 605                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 606                         REG_UPDATE_2(HDMI_CONTROL,
 607                                         HDMI_DEEP_COLOR_DEPTH, 2,
 608                                         HDMI_DEEP_COLOR_ENABLE, 0);
 609                 } else {
 610                         REG_UPDATE_2(HDMI_CONTROL,
 611                                         HDMI_DEEP_COLOR_DEPTH, 2,
 612                                         HDMI_DEEP_COLOR_ENABLE, 1);
 613                         }
 614                 break;
 615         case COLOR_DEPTH_161616:
 616                 REG_UPDATE_2(HDMI_CONTROL,
 617                                 HDMI_DEEP_COLOR_DEPTH, 3,
 618                                 HDMI_DEEP_COLOR_ENABLE, 1);
 619                 break;
 620         default:
 621                 break;
 622         }
 623
 624         if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
 625                 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
 626                         /* enable HDMI data scrambler
 627                          * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
 628                          * Clock channel frequency is 1/4 of character rate.
 629                          */
 630                         REG_UPDATE_2(HDMI_CONTROL,
 631                                 HDMI_DATA_SCRAMBLE_EN, 1,
 632                                 HDMI_CLOCK_CHANNEL_RATE, 1);
 633                 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
 634
 635                         /* TODO: New feature for DCE11, still need to implement */
 636
 637                         /* enable HDMI data scrambler
 638                          * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
 639                          * Clock channel frequency is the same
 640                          * as character rate
 641                          */
 642                         REG_UPDATE_2(HDMI_CONTROL,
 643                                 HDMI_DATA_SCRAMBLE_EN, 1,
 644                                 HDMI_CLOCK_CHANNEL_RATE, 0);
 645                 }
 646         }
 647
 648         REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
 649                 HDMI_GC_CONT, 1,
 650                 HDMI_GC_SEND, 1,
 651                 HDMI_NULL_SEND, 1);
 652
 653         /* following belongs to audio */
 654         REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
 655
 656         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
 657
 658         REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
 659                                 VBI_LINE_0 + 2);
 660
 661         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
 662
 663 }
 664
 665 /* setup stream encoder in dvi mode */
 666 static void dce110_stream_encoder_dvi_set_stream_attribute(
 667         struct stream_encoder *enc,
 668         struct dc_crtc_timing *crtc_timing,
 669         bool is_dual_link)
 670 {
 671         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 672         struct bp_encoder_control cntl = {0};
 673
 674         cntl.action = ENCODER_CONTROL_SETUP;
 675         cntl.engine_id = enc110->base.id;
 676         cntl.signal = is_dual_link ?
 677                         SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
 678         cntl.enable_dp_audio = false;
 679         cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
 680         cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
 681
 682         if (enc110->base.bp->funcs->encoder_control(
 683                         enc110->base.bp, &cntl) != BP_RESULT_OK)
 684                 return;
 685
 686         ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 687         ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
 688         dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
 689 }
 690
 691 /* setup stream encoder in LVDS mode */
 692 static void dce110_stream_encoder_lvds_set_stream_attribute(
 693         struct stream_encoder *enc,
 694         struct dc_crtc_timing *crtc_timing)
 695 {
 696         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 697         struct bp_encoder_control cntl = {0};
 698
 699         cntl.action = ENCODER_CONTROL_SETUP;
 700         cntl.engine_id = enc110->base.id;
 701         cntl.signal = SIGNAL_TYPE_LVDS;
 702         cntl.enable_dp_audio = false;
 703         cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
 704         cntl.lanes_number = LANE_COUNT_FOUR;
 705
 706         if (enc110->base.bp->funcs->encoder_control(
 707                         enc110->base.bp, &cntl) != BP_RESULT_OK)
 708                 return;
 709
 710         ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 711 }
 712
 713 static void dce110_stream_encoder_set_mst_bandwidth(
 714         struct stream_encoder *enc,
 715         struct fixed31_32 avg_time_slots_per_mtp)
 716 {
 717         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 718         uint32_t x = dc_fixpt_floor(
 719                 avg_time_slots_per_mtp);
 720         uint32_t y = dc_fixpt_ceil(
 721                 dc_fixpt_shl(
 722                         dc_fixpt_sub_int(
 723                                 avg_time_slots_per_mtp,
 724                                 x),
 725                         26));
 726
 727         {
 728                 REG_SET_2(DP_MSE_RATE_CNTL, 0,
 729                         DP_MSE_RATE_X, x,
 730                         DP_MSE_RATE_Y, y);
 731         }
 732
 733         /* wait for update to be completed on the link */
 734         /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
 735         /* is reset to 0 (not pending) */
 736         REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
 737                         0,
 738                         10, DP_MST_UPDATE_MAX_RETRY);
 739 }
 740
 741 static void dce110_stream_encoder_update_hdmi_info_packets(
 742         struct stream_encoder *enc,
 743         const struct encoder_info_frame *info_frame)
 744 {
 745         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 746
 747         if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
 748                         enc110->se_mask->HDMI_AVI_INFO_SEND) {
 749
 750                 if (info_frame->avi.valid) {
 751                         const uint32_t *content =
 752                                 (const uint32_t *) &info_frame->avi.sb[0];
 753                         /*we need turn on clock before programming AFMT block*/
 754                         if (REG(AFMT_CNTL))
 755                                 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
 756
 757                         REG_WRITE(AFMT_AVI_INFO0, content[0]);
 758
 759                         REG_WRITE(AFMT_AVI_INFO1, content[1]);
 760
 761                         REG_WRITE(AFMT_AVI_INFO2, content[2]);
 762
 763                         REG_WRITE(AFMT_AVI_INFO3, content[3]);
 764
 765                         REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
 766                                                 info_frame->avi.hb1);
 767
 768                         REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
 769                                         HDMI_AVI_INFO_SEND, 1,
 770                                         HDMI_AVI_INFO_CONT, 1);
 771
 772                         REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
 773                                                         VBI_LINE_0 + 2);
 774
 775                 } else {
 776                         REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
 777                                 HDMI_AVI_INFO_SEND, 0,
 778                                 HDMI_AVI_INFO_CONT, 0);
 779                 }
 780         }
 781
 782         if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
 783                         enc110->se_mask->HDMI_AVI_INFO_SEND) {
 784                 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
 785                 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
 786                 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
 787                 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
 788         }
 789
 790 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 791         if (enc110->se_mask->HDMI_DB_DISABLE) {
 792                 /* for bring up, disable dp double  TODO */
 793                 if (REG(HDMI_DB_CONTROL))
 794                         REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
 795
 796                 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
 797                 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
 798                 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
 799                 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
 800                 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
 801         }
 802 #endif
 803 }
 804
 805 static void dce110_stream_encoder_stop_hdmi_info_packets(
 806         struct stream_encoder *enc)
 807 {
 808         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 809
 810         /* stop generic packets 0 & 1 on HDMI */
 811         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
 812                 HDMI_GENERIC1_CONT, 0,
 813                 HDMI_GENERIC1_LINE, 0,
 814                 HDMI_GENERIC1_SEND, 0,
 815                 HDMI_GENERIC0_CONT, 0,
 816                 HDMI_GENERIC0_LINE, 0,
 817                 HDMI_GENERIC0_SEND, 0);
 818
 819         /* stop generic packets 2 & 3 on HDMI */
 820         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
 821                 HDMI_GENERIC0_CONT, 0,
 822                 HDMI_GENERIC0_LINE, 0,
 823                 HDMI_GENERIC0_SEND, 0,
 824                 HDMI_GENERIC1_CONT, 0,
 825                 HDMI_GENERIC1_LINE, 0,
 826                 HDMI_GENERIC1_SEND, 0);
 827
 828 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 829         /* stop generic packets 2 & 3 on HDMI */
 830         if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 831                 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
 832                         HDMI_GENERIC0_CONT, 0,
 833                         HDMI_GENERIC0_LINE, 0,
 834                         HDMI_GENERIC0_SEND, 0,
 835                         HDMI_GENERIC1_CONT, 0,
 836                         HDMI_GENERIC1_LINE, 0,
 837                         HDMI_GENERIC1_SEND, 0);
 838
 839         if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 840                 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
 841                         HDMI_GENERIC0_CONT, 0,
 842                         HDMI_GENERIC0_LINE, 0,
 843                         HDMI_GENERIC0_SEND, 0,
 844                         HDMI_GENERIC1_CONT, 0,
 845                         HDMI_GENERIC1_LINE, 0,
 846                         HDMI_GENERIC1_SEND, 0);
 847 #endif
 848 }
 849
 850 static void dce110_stream_encoder_update_dp_info_packets(
 851         struct stream_encoder *enc,
 852         const struct encoder_info_frame *info_frame)
 853 {
 854         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 855         uint32_t value = 0;
 856
 857         if (info_frame->vsc.valid)
 858                 dce110_update_generic_info_packet(
 859                                         enc110,
 860                                         0,  /* packetIndex */
 861                                         &info_frame->vsc);
 862
 863         if (info_frame->spd.valid)
 864                 dce110_update_generic_info_packet(
 865                                 enc110,
 866                                 2,  /* packetIndex */
 867                                 &info_frame->spd);
 868
 869         if (info_frame->hdrsmd.valid)
 870                 dce110_update_generic_info_packet(
 871                                 enc110,
 872                                 3,  /* packetIndex */
 873                                 &info_frame->hdrsmd);
 874
 875         /* enable/disable transmission of packet(s).
 876         *  If enabled, packet transmission begins on the next frame
 877         */
 878         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
 879         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
 880         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
 881
 882         /* This bit is the master enable bit.
 883         * When enabling secondary stream engine,
 884         * this master bit must also be set.
 885         * This register shared with audio info frame.
 886         * Therefore we need to enable master bit
 887         * if at least on of the fields is not 0
 888         */
 889         value = REG_READ(DP_SEC_CNTL);
 890         if (value)
 891                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 892 }
 893
 894 static void dce110_stream_encoder_stop_dp_info_packets(
 895         struct stream_encoder *enc)
 896 {
 897         /* stop generic packets on DP */
 898         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 899         uint32_t value = 0;
 900
 901         if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
 902                 REG_SET_7(DP_SEC_CNTL, 0,
 903                         DP_SEC_GSP0_ENABLE, 0,
 904                         DP_SEC_GSP1_ENABLE, 0,
 905                         DP_SEC_GSP2_ENABLE, 0,
 906                         DP_SEC_GSP3_ENABLE, 0,
 907                         DP_SEC_AVI_ENABLE, 0,
 908                         DP_SEC_MPG_ENABLE, 0,
 909                         DP_SEC_STREAM_ENABLE, 0);
 910         }
 911
 912         /* this register shared with audio info frame.
 913          * therefore we need to keep master enabled
 914          * if at least one of the fields is not 0 */
 915         value = REG_READ(DP_SEC_CNTL);
 916         if (value)
 917                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 918
 919 }
 920
 921 static void dce110_stream_encoder_dp_blank(
 922         struct stream_encoder *enc)
 923 {
 924         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 925         uint32_t  reg1 = 0;
 926         uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
 927
 928         /* Note: For CZ, we are changing driver default to disable
 929          * stream deferred to next VBLANK. If results are positive, we
 930          * will make the same change to all DCE versions. There are a
 931          * handful of panels that cannot handle disable stream at
 932          * HBLANK and will result in a white line flash across the
 933          * screen on stream disable. */
 934         REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
 935         if ((reg1 & 0x1) == 0)
 936                 /*stream not enabled*/
 937                 return;
 938         /* Specify the video stream disable point
 939          * (2 = start of the next vertical blank) */
 940         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
 941         /* Larger delay to wait until VBLANK - use max retry of
 942          * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
 943          * a little more because we may not trust delay accuracy.
 944          */
 945         max_retries = DP_BLANK_MAX_RETRY * 150;
 946
 947         /* disable DP stream */
 948         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
 949
 950         /* the encoder stops sending the video stream
 951          * at the start of the vertical blanking.
 952          * Poll for DP_VID_STREAM_STATUS == 0
 953          */
 954
 955         REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
 956                         0,
 957                         10, max_retries);
 958
 959         /* Tell the DP encoder to ignore timing from CRTC, must be done after
 960          * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
 961          * complete, stream status will be stuck in video stream enabled state,
 962          * i.e. DP_VID_STREAM_STATUS stuck at 1.
 963          */
 964
 965         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
 966 }
 967
 968 /* output video stream to link encoder */
 969 static void dce110_stream_encoder_dp_unblank(
 970         struct stream_encoder *enc,
 971         const struct encoder_unblank_param *param)
 972 {
 973         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 974
 975         if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
 976                 uint32_t n_vid = 0x8000;
 977                 uint32_t m_vid;
 978
 979                 /* M / N = Fstream / Flink
 980                 * m_vid / n_vid = pixel rate / link rate
 981                 */
 982
 983                 uint64_t m_vid_l = n_vid;
 984
 985                 m_vid_l *= param->timing.pix_clk_100hz / 10;
 986                 m_vid_l = div_u64(m_vid_l,
 987                         param->link_settings.link_rate
 988                                 * LINK_RATE_REF_FREQ_IN_KHZ);
 989
 990                 m_vid = (uint32_t) m_vid_l;
 991
 992                 /* enable auto measurement */
 993
 994                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
 995
 996                 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
 997                  * therefore program initial value for Mvid and Nvid
 998                  */
 999
1000                 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
1001
1002                 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
1003
1004                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
1005         }
1006
1007         /* set DIG_START to 0x1 to resync FIFO */
1008
1009         REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
1010
1011         /* switch DP encoder to CRTC data */
1012
1013         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
1014
1015         /* wait 100us for DIG/DP logic to prime
1016         * (i.e. a few video lines)
1017         */
1018         udelay(100);
1019
1020         /* the hardware would start sending video at the start of the next DP
1021         * frame (i.e. rising edge of the vblank).
1022         * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1023         * register has no effect on enable transition! HW always guarantees
1024         * VID_STREAM enable at start of next frame, and this is not
1025         * programmable
1026         */
1027
1028         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1029 }
1030
1031 static void dce110_stream_encoder_set_avmute(
1032         struct stream_encoder *enc,
1033         bool enable)
1034 {
1035         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1036         unsigned int value = enable ? 1 : 0;
1037
1038         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1039 }
1040
1041
1042 static void dce110_reset_hdmi_stream_attribute(
1043         struct stream_encoder *enc)
1044 {
1045         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1046         if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN)
1047                 REG_UPDATE_5(HDMI_CONTROL,
1048                         HDMI_PACKET_GEN_VERSION, 1,
1049                         HDMI_KEEPOUT_MODE, 1,
1050                         HDMI_DEEP_COLOR_ENABLE, 0,
1051                         HDMI_DATA_SCRAMBLE_EN, 0,
1052                         HDMI_CLOCK_CHANNEL_RATE, 0);
1053         else
1054                 REG_UPDATE_3(HDMI_CONTROL,
1055                         HDMI_PACKET_GEN_VERSION, 1,
1056                         HDMI_KEEPOUT_MODE, 1,
1057                         HDMI_DEEP_COLOR_ENABLE, 0);
1058 }
1059
1060 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1061 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1062
1063 #include "include/audio_types.h"
1064
1065 /**
1066 * speakersToChannels
1067 *
1068 * @brief
1069 *  translate speakers to channels
1070 *
1071 *  FL  - Front Left
1072 *  FR  - Front Right
1073 *  RL  - Rear Left
1074 *  RR  - Rear Right
1075 *  RC  - Rear Center
1076 *  FC  - Front Center
1077 *  FLC - Front Left Center
1078 *  FRC - Front Right Center
1079 *  RLC - Rear Left Center
1080 *  RRC - Rear Right Center
1081 *  LFE - Low Freq Effect
1082 *
1083 *               FC
1084 *          FLC      FRC
1085 *    FL                    FR
1086 *
1087 *                    LFE
1088 *              ()
1089 *
1090 *
1091 *    RL                    RR
1092 *          RLC      RRC
1093 *               RC
1094 *
1095 *             ch  8   7   6   5   4   3   2   1
1096 * 0b00000011      -   -   -   -   -   -   FR  FL
1097 * 0b00000111      -   -   -   -   -   LFE FR  FL
1098 * 0b00001011      -   -   -   -   FC  -   FR  FL
1099 * 0b00001111      -   -   -   -   FC  LFE FR  FL
1100 * 0b00010011      -   -   -   RC  -   -   FR  FL
1101 * 0b00010111      -   -   -   RC  -   LFE FR  FL
1102 * 0b00011011      -   -   -   RC  FC  -   FR  FL
1103 * 0b00011111      -   -   -   RC  FC  LFE FR  FL
1104 * 0b00110011      -   -   RR  RL  -   -   FR  FL
1105 * 0b00110111      -   -   RR  RL  -   LFE FR  FL
1106 * 0b00111011      -   -   RR  RL  FC  -   FR  FL
1107 * 0b00111111      -   -   RR  RL  FC  LFE FR  FL
1108 * 0b01110011      -   RC  RR  RL  -   -   FR  FL
1109 * 0b01110111      -   RC  RR  RL  -   LFE FR  FL
1110 * 0b01111011      -   RC  RR  RL  FC  -   FR  FL
1111 * 0b01111111      -   RC  RR  RL  FC  LFE FR  FL
1112 * 0b11110011      RRC RLC RR  RL  -   -   FR  FL
1113 * 0b11110111      RRC RLC RR  RL  -   LFE FR  FL
1114 * 0b11111011      RRC RLC RR  RL  FC  -   FR  FL
1115 * 0b11111111      RRC RLC RR  RL  FC  LFE FR  FL
1116 * 0b11000011      FRC FLC -   -   -   -   FR  FL
1117 * 0b11000111      FRC FLC -   -   -   LFE FR  FL
1118 * 0b11001011      FRC FLC -   -   FC  -   FR  FL
1119 * 0b11001111      FRC FLC -   -   FC  LFE FR  FL
1120 * 0b11010011      FRC FLC -   RC  -   -   FR  FL
1121 * 0b11010111      FRC FLC -   RC  -   LFE FR  FL
1122 * 0b11011011      FRC FLC -   RC  FC  -   FR  FL
1123 * 0b11011111      FRC FLC -   RC  FC  LFE FR  FL
1124 * 0b11110011      FRC FLC RR  RL  -   -   FR  FL
1125 * 0b11110111      FRC FLC RR  RL  -   LFE FR  FL
1126 * 0b11111011      FRC FLC RR  RL  FC  -   FR  FL
1127 * 0b11111111      FRC FLC RR  RL  FC  LFE FR  FL
1128 *
1129 * @param
1130 *  speakers - speaker information as it comes from CEA audio block
1131 */
1132 /* translate speakers to channels */
1133
1134 union audio_cea_channels {
1135         uint8_t all;
1136         struct audio_cea_channels_bits {
1137                 uint32_t FL:1;
1138                 uint32_t FR:1;
1139                 uint32_t LFE:1;
1140                 uint32_t FC:1;
1141                 uint32_t RL_RC:1;
1142                 uint32_t RR:1;
1143                 uint32_t RC_RLC_FLC:1;
1144                 uint32_t RRC_FRC:1;
1145         } channels;
1146 };
1147
1148 /* 25.2MHz/1.001*/
1149 /* 25.2MHz/1.001*/
1150 /* 25.2MHz*/
1151 /* 27MHz */
1152 /* 27MHz*1.001*/
1153 /* 27MHz*1.001*/
1154 /* 54MHz*/
1155 /* 54MHz*1.001*/
1156 /* 74.25MHz/1.001*/
1157 /* 74.25MHz*/
1158 /* 148.5MHz/1.001*/
1159 /* 148.5MHz*/
1160
1161 static const struct audio_clock_info audio_clock_info_table[16] = {
1162         {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1163         {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1164         {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1165         {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1166         {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1167         {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1168         {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1169         {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1170         {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1171         {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1172         {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1173         {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1174         {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1175         {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1176         {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1177         {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1178 };
1179
1180 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1181         {2517,  9152,  84375,  7007,  48875,  9152,  56250},
1182         {2518,  9152,  84375,  7007,  48875,  9152,  56250},
1183         {2520,  4096,  37800,  6272,  42000,  6144,  37800},
1184         {2700,  4096,  40500,  6272,  45000,  6144,  40500},
1185         {2702,  8192,  81081,  6272,  45045,  8192,  54054},
1186         {2703,  8192,  81081,  6272,  45045,  8192,  54054},
1187         {5400,  4096,  81000,  6272,  90000,  6144,  81000},
1188         {5405,  4096,  81081,  6272,  90090,  6144,  81081},
1189         {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1190         {7425, 4096, 111375,  6272, 123750,  6144, 111375},
1191         {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1192         {14850, 4096, 222750,  6272, 247500,  6144, 222750},
1193         {29670, 5824, 632812,  8918, 703125,  5824, 421875},
1194         {29700, 4096, 445500,  4704, 371250,  5120, 371250}
1195 };
1196
1197 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1198         {2517,  4576,  56250,  7007,  62500,  6864,  56250},
1199         {2518,  4576,  56250,  7007,  62500,  6864,  56250},
1200         {2520,  4096,  50400,  6272,  56000,  6144,  50400},
1201         {2700,  4096,  54000,  6272,  60000,  6144,  54000},
1202         {2702,  4096,  54054,  6267,  60060,  8192,  54054},
1203         {2703,  4096,  54054,  6272,  60060,  8192,  54054},
1204         {5400,  4096, 108000,  6272, 120000,  6144, 108000},
1205         {5405,  4096, 108108,  6272, 120120,  6144, 108108},
1206         {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1207         {7425,  4096, 148500,  6272, 165000,  6144, 148500},
1208         {14835, 11648, 843750,  8918, 468750, 11648, 281250},
1209         {14850, 4096, 297000,  6272, 330000,  6144, 297000},
1210         {29670, 5824, 843750,  4459, 468750,  5824, 562500},
1211         {29700, 3072, 445500,  4704, 495000,  5120, 495000}
1212
1213
1214 };
1215
1216 static union audio_cea_channels speakers_to_channels(
1217         struct audio_speaker_flags speaker_flags)
1218 {
1219         union audio_cea_channels cea_channels = {0};
1220
1221         /* these are one to one */
1222         cea_channels.channels.FL = speaker_flags.FL_FR;
1223         cea_channels.channels.FR = speaker_flags.FL_FR;
1224         cea_channels.channels.LFE = speaker_flags.LFE;
1225         cea_channels.channels.FC = speaker_flags.FC;
1226
1227         /* if Rear Left and Right exist move RC speaker to channel 7
1228          * otherwise to channel 5
1229          */
1230         if (speaker_flags.RL_RR) {
1231                 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1232                 cea_channels.channels.RR = speaker_flags.RL_RR;
1233                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1234         } else {
1235                 cea_channels.channels.RL_RC = speaker_flags.RC;
1236         }
1237
1238         /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1239         if (speaker_flags.FLC_FRC) {
1240                 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1241                 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1242         } else {
1243                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1244                 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1245         }
1246
1247         return cea_channels;
1248 }
1249
1250 static uint32_t calc_max_audio_packets_per_line(
1251         const struct audio_crtc_info *crtc_info)
1252 {
1253         uint32_t max_packets_per_line;
1254
1255         max_packets_per_line =
1256                 crtc_info->h_total - crtc_info->h_active;
1257
1258         if (crtc_info->pixel_repetition)
1259                 max_packets_per_line *= crtc_info->pixel_repetition;
1260
1261         /* for other hdmi features */
1262         max_packets_per_line -= 58;
1263         /* for Control Period */
1264         max_packets_per_line -= 16;
1265         /* Number of Audio Packets per Line */
1266         max_packets_per_line /= 32;
1267
1268         return max_packets_per_line;
1269 }
1270
1271 static void get_audio_clock_info(
1272         enum dc_color_depth color_depth,
1273         uint32_t crtc_pixel_clock_100Hz,
1274         uint32_t actual_pixel_clock_100Hz,
1275         struct audio_clock_info *audio_clock_info)
1276 {
1277         const struct audio_clock_info *clock_info;
1278         uint32_t index;
1279         uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1280         uint32_t audio_array_size;
1281
1282         switch (color_depth) {
1283         case COLOR_DEPTH_161616:
1284                 clock_info = audio_clock_info_table_48bpc;
1285                 audio_array_size = ARRAY_SIZE(
1286                                 audio_clock_info_table_48bpc);
1287                 break;
1288         case COLOR_DEPTH_121212:
1289                 clock_info = audio_clock_info_table_36bpc;
1290                 audio_array_size = ARRAY_SIZE(
1291                                 audio_clock_info_table_36bpc);
1292                 break;
1293         default:
1294                 clock_info = audio_clock_info_table;
1295                 audio_array_size = ARRAY_SIZE(
1296                                 audio_clock_info_table);
1297                 break;
1298         }
1299
1300         if (clock_info != NULL) {
1301                 /* search for exact pixel clock in table */
1302                 for (index = 0; index < audio_array_size; index++) {
1303                         if (clock_info[index].pixel_clock_in_10khz >
1304                                 crtc_pixel_clock_in_10khz)
1305                                 break;  /* not match */
1306                         else if (clock_info[index].pixel_clock_in_10khz ==
1307                                         crtc_pixel_clock_in_10khz) {
1308                                 /* match found */
1309                                 *audio_clock_info = clock_info[index];
1310                                 return;
1311                         }
1312                 }
1313         }
1314
1315         /* not found */
1316         if (actual_pixel_clock_100Hz == 0)
1317                 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1318
1319         /* See HDMI spec  the table entry under
1320          *  pixel clock of "Other". */
1321         audio_clock_info->pixel_clock_in_10khz =
1322                         actual_pixel_clock_100Hz / 100;
1323         audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1324         audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1325         audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1326
1327         audio_clock_info->n_32khz = 4096;
1328         audio_clock_info->n_44khz = 6272;
1329         audio_clock_info->n_48khz = 6144;
1330 }
1331
1332 static void dce110_se_audio_setup(
1333         struct stream_encoder *enc,
1334         unsigned int az_inst,
1335         struct audio_info *audio_info)
1336 {
1337         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1338
1339         uint32_t speakers = 0;
1340         uint32_t channels = 0;
1341
1342         ASSERT(audio_info);
1343         if (audio_info == NULL)
1344                 /* This should not happen.it does so we don't get BSOD*/
1345                 return;
1346
1347         speakers = audio_info->flags.info.ALLSPEAKERS;
1348         channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1349
1350         /* setup the audio stream source select (audio -> dig mapping) */
1351         REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1352
1353         /* Channel allocation */
1354         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1355 }
1356
1357 static void dce110_se_setup_hdmi_audio(
1358         struct stream_encoder *enc,
1359         const struct audio_crtc_info *crtc_info)
1360 {
1361         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1362
1363         struct audio_clock_info audio_clock_info = {0};
1364         uint32_t max_packets_per_line;
1365
1366         /* For now still do calculation, although this field is ignored when
1367         above HDMI_PACKET_GEN_VERSION set to 1 */
1368         max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1369
1370         /* HDMI_AUDIO_PACKET_CONTROL */
1371         REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1372                         HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1373                         HDMI_AUDIO_DELAY_EN, 1);
1374
1375         /* AFMT_AUDIO_PACKET_CONTROL */
1376         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1377
1378         /* AFMT_AUDIO_PACKET_CONTROL2 */
1379         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1380                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1381                         AFMT_60958_OSF_OVRD, 0);
1382
1383         /* HDMI_ACR_PACKET_CONTROL */
1384         REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1385                         HDMI_ACR_AUTO_SEND, 1,
1386                         HDMI_ACR_SOURCE, 0,
1387                         HDMI_ACR_AUDIO_PRIORITY, 0);
1388
1389         /* Program audio clock sample/regeneration parameters */
1390         get_audio_clock_info(crtc_info->color_depth,
1391                              crtc_info->requested_pixel_clock_100Hz,
1392                              crtc_info->calculated_pixel_clock_100Hz,
1393                              &audio_clock_info);
1394         DC_LOG_HW_AUDIO(
1395                         "\n%s:Input::requested_pixel_clock_100Hz = %d"  \
1396                         "calculated_pixel_clock_100Hz = %d \n", __func__,       \
1397                         crtc_info->requested_pixel_clock_100Hz,         \
1398                         crtc_info->calculated_pixel_clock_100Hz);
1399
1400         /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1401         REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1402
1403         /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1404         REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1405
1406         /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1407         REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1408
1409         /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1410         REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1411
1412         /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1413         REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1414
1415         /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1416         REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1417
1418         /* Video driver cannot know in advance which sample rate will
1419            be used by HD Audio driver
1420            HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1421            programmed below in interruppt callback */
1422
1423         /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1424         AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1425         REG_UPDATE_2(AFMT_60958_0,
1426                         AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1427                         AFMT_60958_CS_CLOCK_ACCURACY, 0);
1428
1429         /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1430         REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1431
1432         /*AFMT_60958_2 now keep this settings until
1433          *  Programming guide comes out*/
1434         REG_UPDATE_6(AFMT_60958_2,
1435                         AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1436                         AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1437                         AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1438                         AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1439                         AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1440                         AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1441 }
1442
1443 static void dce110_se_setup_dp_audio(
1444         struct stream_encoder *enc)
1445 {
1446         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1447
1448         /* --- DP Audio packet configurations --- */
1449
1450         /* ATP Configuration */
1451         REG_SET(DP_SEC_AUD_N, 0,
1452                         DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1453
1454         /* Async/auto-calc timestamp mode */
1455         REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1456                         DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1457
1458         /* --- The following are the registers
1459          *  copied from the SetupHDMI --- */
1460
1461         /* AFMT_AUDIO_PACKET_CONTROL */
1462         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1463
1464         /* AFMT_AUDIO_PACKET_CONTROL2 */
1465         /* Program the ATP and AIP next */
1466         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1467                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1468                         AFMT_60958_OSF_OVRD, 0);
1469
1470         /* AFMT_INFOFRAME_CONTROL0 */
1471         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1472
1473         /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1474         REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1475 }
1476
1477 static void dce110_se_enable_audio_clock(
1478         struct stream_encoder *enc,
1479         bool enable)
1480 {
1481         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1482
1483         if (REG(AFMT_CNTL) == 0)
1484                 return;   /* DCE8/10 does not have this register */
1485
1486         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1487
1488         /* wait for AFMT clock to turn on,
1489          * expectation: this should complete in 1-2 reads
1490          *
1491          * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1492          *
1493          * TODO: wait for clock_on does not work well. May need HW
1494          * program sequence. But audio seems work normally even without wait
1495          * for clock_on status change
1496          */
1497 }
1498
1499 static void dce110_se_enable_dp_audio(
1500         struct stream_encoder *enc)
1501 {
1502         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1503
1504         /* Enable Audio packets */
1505         REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1506
1507         /* Program the ATP and AIP next */
1508         REG_UPDATE_2(DP_SEC_CNTL,
1509                         DP_SEC_ATP_ENABLE, 1,
1510                         DP_SEC_AIP_ENABLE, 1);
1511
1512         /* Program STREAM_ENABLE after all the other enables. */
1513         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1514 }
1515
1516 static void dce110_se_disable_dp_audio(
1517         struct stream_encoder *enc)
1518 {
1519         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1520         uint32_t value = 0;
1521
1522         /* Disable Audio packets */
1523         REG_UPDATE_5(DP_SEC_CNTL,
1524                         DP_SEC_ASP_ENABLE, 0,
1525                         DP_SEC_ATP_ENABLE, 0,
1526                         DP_SEC_AIP_ENABLE, 0,
1527                         DP_SEC_ACM_ENABLE, 0,
1528                         DP_SEC_STREAM_ENABLE, 0);
1529
1530         /* This register shared with encoder info frame. Therefore we need to
1531         keep master enabled if at least on of the fields is not 0 */
1532         value = REG_READ(DP_SEC_CNTL);
1533         if (value != 0)
1534                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1535
1536 }
1537
1538 void dce110_se_audio_mute_control(
1539         struct stream_encoder *enc,
1540         bool mute)
1541 {
1542         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1543
1544         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1545 }
1546
1547 void dce110_se_dp_audio_setup(
1548         struct stream_encoder *enc,
1549         unsigned int az_inst,
1550         struct audio_info *info)
1551 {
1552         dce110_se_audio_setup(enc, az_inst, info);
1553 }
1554
1555 void dce110_se_dp_audio_enable(
1556         struct stream_encoder *enc)
1557 {
1558         dce110_se_enable_audio_clock(enc, true);
1559         dce110_se_setup_dp_audio(enc);
1560         dce110_se_enable_dp_audio(enc);
1561 }
1562
1563 void dce110_se_dp_audio_disable(
1564         struct stream_encoder *enc)
1565 {
1566         dce110_se_disable_dp_audio(enc);
1567         dce110_se_enable_audio_clock(enc, false);
1568 }
1569
1570 void dce110_se_hdmi_audio_setup(
1571         struct stream_encoder *enc,
1572         unsigned int az_inst,
1573         struct audio_info *info,
1574         struct audio_crtc_info *audio_crtc_info)
1575 {
1576         dce110_se_enable_audio_clock(enc, true);
1577         dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
1578         dce110_se_audio_setup(enc, az_inst, info);
1579 }
1580
1581 void dce110_se_hdmi_audio_disable(
1582         struct stream_encoder *enc)
1583 {
1584         dce110_se_enable_audio_clock(enc, false);
1585 }
1586
1587
1588 static void setup_stereo_sync(
1589         struct stream_encoder *enc,
1590         int tg_inst, bool enable)
1591 {
1592         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1593         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1594         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1595 }
1596
1597 static void dig_connect_to_otg(
1598         struct stream_encoder *enc,
1599         int tg_inst)
1600 {
1601         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1602
1603         REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1604 }
1605
1606 static unsigned int dig_source_otg(
1607         struct stream_encoder *enc)
1608 {
1609         uint32_t tg_inst = 0;
1610         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1611
1612         REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1613
1614         return tg_inst;
1615 }
1616
1617 static const struct stream_encoder_funcs dce110_str_enc_funcs = {
1618         .dp_set_stream_attribute =
1619                 dce110_stream_encoder_dp_set_stream_attribute,
1620         .hdmi_set_stream_attribute =
1621                 dce110_stream_encoder_hdmi_set_stream_attribute,
1622         .dvi_set_stream_attribute =
1623                 dce110_stream_encoder_dvi_set_stream_attribute,
1624         .lvds_set_stream_attribute =
1625                 dce110_stream_encoder_lvds_set_stream_attribute,
1626         .set_mst_bandwidth =
1627                 dce110_stream_encoder_set_mst_bandwidth,
1628         .update_hdmi_info_packets =
1629                 dce110_stream_encoder_update_hdmi_info_packets,
1630         .stop_hdmi_info_packets =
1631                 dce110_stream_encoder_stop_hdmi_info_packets,
1632         .update_dp_info_packets =
1633                 dce110_stream_encoder_update_dp_info_packets,
1634         .stop_dp_info_packets =
1635                 dce110_stream_encoder_stop_dp_info_packets,
1636         .dp_blank =
1637                 dce110_stream_encoder_dp_blank,
1638         .dp_unblank =
1639                 dce110_stream_encoder_dp_unblank,
1640         .audio_mute_control = dce110_se_audio_mute_control,
1641
1642         .dp_audio_setup = dce110_se_dp_audio_setup,
1643         .dp_audio_enable = dce110_se_dp_audio_enable,
1644         .dp_audio_disable = dce110_se_dp_audio_disable,
1645
1646         .hdmi_audio_setup = dce110_se_hdmi_audio_setup,
1647         .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
1648         .setup_stereo_sync  = setup_stereo_sync,
1649         .set_avmute = dce110_stream_encoder_set_avmute,
1650         .dig_connect_to_otg  = dig_connect_to_otg,
1651         .hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute,
1652         .dig_source_otg = dig_source_otg,
1653 };
1654
1655 void dce110_stream_encoder_construct(
1656         struct dce110_stream_encoder *enc110,
1657         struct dc_context *ctx,
1658         struct dc_bios *bp,
1659         enum engine_id eng_id,
1660         const struct dce110_stream_enc_registers *regs,
1661         const struct dce_stream_encoder_shift *se_shift,
1662         const struct dce_stream_encoder_mask *se_mask)
1663 {
1664         enc110->base.funcs = &dce110_str_enc_funcs;
1665         enc110->base.ctx = ctx;
1666         enc110->base.id = eng_id;
1667         enc110->base.bp = bp;
1668         enc110->regs = regs;
1669         enc110->se_shift = se_shift;
1670         enc110->se_mask = se_mask;
1671 }