drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_PANEL_CNTL__DCE_H__
  27 #define __DC_PANEL_CNTL__DCE_H__
  28
  29 #include "panel_cntl.h"
  30
  31 /* set register offset with instance */
  32 #define DCE_PANEL_CNTL_SR(reg_name, block)\
  33         .reg_name = mm ## block ## _ ## reg_name
  34
  35 #define DCE_PANEL_CNTL_REG_LIST()\
  36         DCE_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
  37         DCE_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
  38         SR(BL_PWM_CNTL), \
  39         SR(BL_PWM_CNTL2), \
  40         SR(BL_PWM_PERIOD_CNTL), \
  41         SR(BL_PWM_GRP1_REG_LOCK)
  42
  43 #define DCN_PANEL_CNTL_SR(reg_name, block)\
  44         .reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
  45                                         mm ## block ## _ ## reg_name
  46
  47 #define DCN_PANEL_CNTL_REG_LIST()\
  48         DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
  49         DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
  50         SR(BL_PWM_CNTL), \
  51         SR(BL_PWM_CNTL2), \
  52         SR(BL_PWM_PERIOD_CNTL), \
  53         SR(BL_PWM_GRP1_REG_LOCK)
  54
  55 #define DCE_PANEL_CNTL_SF(block, reg_name, field_name, post_fix)\
  56         .field_name = block ## reg_name ## __ ## block ## field_name ## post_fix
  57
  58 #define DCE_PANEL_CNTL_MASK_SH_LIST(mask_sh) \
  59         DCE_PANEL_CNTL_SF(LVTMA_, PWRSEQ_CNTL, BLON, mask_sh),\
  60         DCE_PANEL_CNTL_SF(LVTMA_, PWRSEQ_CNTL, DIGON, mask_sh),\
  61         DCE_PANEL_CNTL_SF(LVTMA_, PWRSEQ_CNTL, DIGON_OVRD, mask_sh),\
  62         DCE_PANEL_CNTL_SF(LVTMA_, PWRSEQ_STATE, PWRSEQ_TARGET_STATE_R, mask_sh), \
  63         DCE_PANEL_CNTL_SF(, BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
  64         DCE_PANEL_CNTL_SF(, BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
  65         DCE_PANEL_CNTL_SF(, BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
  66         DCE_PANEL_CNTL_SF(, BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
  67         DCE_PANEL_CNTL_SF(, BL_PWM_CNTL, BL_PWM_EN, mask_sh), \
  68         DCE_PANEL_CNTL_SF(, BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
  69         DCE_PANEL_CNTL_SF(, BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
  70         DCE_PANEL_CNTL_SF(, BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh)
  71
  72 #define DCE_PANEL_CNTL_REG_FIELD_LIST(type) \
  73         type BLON;\
  74         type DIGON;\
  75         type DIGON_OVRD;\
  76         type PWRSEQ_TARGET_STATE_R; \
  77         type BL_PWM_EN; \
  78         type BL_ACTIVE_INT_FRAC_CNT; \
  79         type BL_PWM_FRACTIONAL_EN; \
  80         type BL_PWM_PERIOD; \
  81         type BL_PWM_PERIOD_BITCNT; \
  82         type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
  83         type BL_PWM_GRP1_REG_LOCK; \
  84         type BL_PWM_GRP1_REG_UPDATE_PENDING
  85
  86 struct dce_panel_cntl_shift {
  87         DCE_PANEL_CNTL_REG_FIELD_LIST(uint8_t);
  88 };
  89
  90 struct dce_panel_cntl_mask {
  91         DCE_PANEL_CNTL_REG_FIELD_LIST(uint32_t);
  92 };
  93
  94 struct dce_panel_cntl_registers {
  95         uint32_t PWRSEQ_CNTL;
  96         uint32_t PWRSEQ_STATE;
  97         uint32_t BL_PWM_CNTL;
  98         uint32_t BL_PWM_CNTL2;
  99         uint32_t BL_PWM_PERIOD_CNTL;
 100         uint32_t BL_PWM_GRP1_REG_LOCK;
 101 };
 102
 103 struct dce_panel_cntl {
 104         struct panel_cntl base;
 105         const struct dce_panel_cntl_registers *regs;
 106         const struct dce_panel_cntl_shift *shift;
 107         const struct dce_panel_cntl_mask *mask;
 108 };
 109
 110 void dce_panel_cntl_construct(
 111         struct dce_panel_cntl *panel_cntl,
 112         const struct panel_cntl_init_data *init_data,
 113         const struct dce_panel_cntl_registers *regs,
 114         const struct dce_panel_cntl_shift *shift,
 115         const struct dce_panel_cntl_mask *mask);
 116
 117 #endif /* __DC_PANEL_CNTL__DCE_H__ */