drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27
  28 #include "reg_helper.h"
  29
  30 #include "core_types.h"
  31 #include "link_encoder.h"
  32 #include "dce_link_encoder.h"
  33 #include "stream_encoder.h"
  34 #include "i2caux_interface.h"
  35 #include "dc_bios_types.h"
  36
  37 #include "gpio_service_interface.h"
  38
  39 #include "dce/dce_11_0_d.h"
  40 #include "dce/dce_11_0_sh_mask.h"
  41 #include "dce/dce_11_0_enum.h"
  42
  43 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT
  44 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa
  45 #endif
  46
  47 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK
  48 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L
  49 #endif
  50
  51 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK
  52 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK  0x10000000L
  53 #endif
  54
  55 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT
  56 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT  0x1c
  57 #endif
  58
  59 #define CTX \
  60         enc110->base.ctx
  61 #define DC_LOGGER \
  62         enc110->base.ctx->logger
  63
  64 #define REG(reg)\
  65         (enc110->link_regs->reg)
  66
  67 #define AUX_REG(reg)\
  68         (enc110->aux_regs->reg)
  69
  70 #define HPD_REG(reg)\
  71         (enc110->hpd_regs->reg)
  72
  73 #define DEFAULT_AUX_MAX_DATA_SIZE 16
  74 #define AUX_MAX_DEFER_WRITE_RETRY 20
  75 /*
  76  * @brief
  77  * Trigger Source Select
  78  * ASIC-dependent, actual values for register programming
  79  */
  80 #define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0
  81 #define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1
  82 #define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2
  83 #define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4
  84 #define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08
  85 #define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10
  86 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
  87 #define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40
  88
  89 enum {
  90         DP_MST_UPDATE_MAX_RETRY = 50
  91 };
  92
  93 #define DIG_REG(reg)\
  94         (reg + enc110->offsets.dig)
  95
  96 #define DP_REG(reg)\
  97         (reg + enc110->offsets.dp)
  98
  99 static const struct link_encoder_funcs dce110_lnk_enc_funcs = {
 100         .validate_output_with_stream =
 101                 dce110_link_encoder_validate_output_with_stream,
 102         .hw_init = dce110_link_encoder_hw_init,
 103         .setup = dce110_link_encoder_setup,
 104         .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
 105         .enable_dp_output = dce110_link_encoder_enable_dp_output,
 106         .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
 107         .enable_lvds_output = dce110_link_encoder_enable_lvds_output,
 108         .disable_output = dce110_link_encoder_disable_output,
 109         .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
 110         .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
 111         .update_mst_stream_allocation_table =
 112                 dce110_link_encoder_update_mst_stream_allocation_table,
 113         .psr_program_dp_dphy_fast_training =
 114                         dce110_psr_program_dp_dphy_fast_training,
 115         .psr_program_secondary_packet = dce110_psr_program_secondary_packet,
 116         .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
 117         .enable_hpd = dce110_link_encoder_enable_hpd,
 118         .disable_hpd = dce110_link_encoder_disable_hpd,
 119         .is_dig_enabled = dce110_is_dig_enabled,
 120         .destroy = dce110_link_encoder_destroy
 121 };
 122
 123 static enum bp_result link_transmitter_control(
 124         struct dce110_link_encoder *enc110,
 125         struct bp_transmitter_control *cntl)
 126 {
 127         enum bp_result result;
 128         struct dc_bios *bp = enc110->base.ctx->dc_bios;
 129
 130         result = bp->funcs->transmitter_control(bp, cntl);
 131
 132         return result;
 133 }
 134
 135 static void enable_phy_bypass_mode(
 136         struct dce110_link_encoder *enc110,
 137         bool enable)
 138 {
 139         /* This register resides in DP back end block;
 140          * transmitter is used for the offset */
 141
 142         REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
 143
 144 }
 145
 146 static void disable_prbs_symbols(
 147         struct dce110_link_encoder *enc110,
 148         bool disable)
 149 {
 150         /* This register resides in DP back end block;
 151          * transmitter is used for the offset */
 152
 153         REG_UPDATE_4(DP_DPHY_CNTL,
 154                         DPHY_ATEST_SEL_LANE0, disable,
 155                         DPHY_ATEST_SEL_LANE1, disable,
 156                         DPHY_ATEST_SEL_LANE2, disable,
 157                         DPHY_ATEST_SEL_LANE3, disable);
 158 }
 159
 160 static void disable_prbs_mode(
 161         struct dce110_link_encoder *enc110)
 162 {
 163         REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
 164 }
 165
 166 static void program_pattern_symbols(
 167         struct dce110_link_encoder *enc110,
 168         uint16_t pattern_symbols[8])
 169 {
 170         /* This register resides in DP back end block;
 171          * transmitter is used for the offset */
 172
 173         REG_SET_3(DP_DPHY_SYM0, 0,
 174                         DPHY_SYM1, pattern_symbols[0],
 175                         DPHY_SYM2, pattern_symbols[1],
 176                         DPHY_SYM3, pattern_symbols[2]);
 177
 178         /* This register resides in DP back end block;
 179          * transmitter is used for the offset */
 180
 181         REG_SET_3(DP_DPHY_SYM1, 0,
 182                         DPHY_SYM4, pattern_symbols[3],
 183                         DPHY_SYM5, pattern_symbols[4],
 184                         DPHY_SYM6, pattern_symbols[5]);
 185
 186         /* This register resides in DP back end block;
 187          * transmitter is used for the offset */
 188
 189         REG_SET_2(DP_DPHY_SYM2, 0,
 190                         DPHY_SYM7, pattern_symbols[6],
 191                         DPHY_SYM8, pattern_symbols[7]);
 192 }
 193
 194 static void set_dp_phy_pattern_d102(
 195         struct dce110_link_encoder *enc110)
 196 {
 197         /* Disable PHY Bypass mode to setup the test pattern */
 198         enable_phy_bypass_mode(enc110, false);
 199
 200         /* For 10-bit PRBS or debug symbols
 201          * please use the following sequence: */
 202
 203         /* Enable debug symbols on the lanes */
 204
 205         disable_prbs_symbols(enc110, true);
 206
 207         /* Disable PRBS mode */
 208         disable_prbs_mode(enc110);
 209
 210         /* Program debug symbols to be output */
 211         {
 212                 uint16_t pattern_symbols[8] = {
 213                         0x2AA, 0x2AA, 0x2AA, 0x2AA,
 214                         0x2AA, 0x2AA, 0x2AA, 0x2AA
 215                 };
 216
 217                 program_pattern_symbols(enc110, pattern_symbols);
 218         }
 219
 220         /* Enable phy bypass mode to enable the test pattern */
 221
 222         enable_phy_bypass_mode(enc110, true);
 223 }
 224
 225 static void set_link_training_complete(
 226         struct dce110_link_encoder *enc110,
 227         bool complete)
 228 {
 229         /* This register resides in DP back end block;
 230          * transmitter is used for the offset */
 231
 232         REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
 233
 234 }
 235
 236 void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
 237         struct link_encoder *enc,
 238         uint32_t index)
 239 {
 240         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 241         /* Write Training Pattern */
 242
 243         REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
 244
 245         /* Set HW Register Training Complete to false */
 246
 247         set_link_training_complete(enc110, false);
 248
 249         /* Disable PHY Bypass mode to output Training Pattern */
 250
 251         enable_phy_bypass_mode(enc110, false);
 252
 253         /* Disable PRBS mode */
 254         disable_prbs_mode(enc110);
 255 }
 256
 257 static void setup_panel_mode(
 258         struct dce110_link_encoder *enc110,
 259         enum dp_panel_mode panel_mode)
 260 {
 261         uint32_t value;
 262         struct dc_context *ctx = enc110->base.ctx;
 263
 264         /* if psp set panel mode, dal should be program it */
 265         if (ctx->dc->caps.psp_setup_panel_mode)
 266                 return;
 267
 268         ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
 269         value = REG_READ(DP_DPHY_INTERNAL_CTRL);
 270
 271         switch (panel_mode) {
 272         case DP_PANEL_MODE_EDP:
 273                 value = 0x1;
 274                 break;
 275         case DP_PANEL_MODE_SPECIAL:
 276                 value = 0x11;
 277                 break;
 278         default:
 279                 value = 0x0;
 280                 break;
 281         }
 282
 283         REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
 284 }
 285
 286 static void set_dp_phy_pattern_symbol_error(
 287         struct dce110_link_encoder *enc110)
 288 {
 289         /* Disable PHY Bypass mode to setup the test pattern */
 290         enable_phy_bypass_mode(enc110, false);
 291
 292         /* program correct panel mode*/
 293         setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
 294
 295         /* A PRBS23 pattern is used for most DP electrical measurements. */
 296
 297         /* Enable PRBS symbols on the lanes */
 298         disable_prbs_symbols(enc110, false);
 299
 300         /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
 301         REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
 302                         DPHY_PRBS_SEL, 1,
 303                         DPHY_PRBS_EN, 1);
 304
 305         /* Enable phy bypass mode to enable the test pattern */
 306         enable_phy_bypass_mode(enc110, true);
 307 }
 308
 309 static void set_dp_phy_pattern_prbs7(
 310         struct dce110_link_encoder *enc110)
 311 {
 312         /* Disable PHY Bypass mode to setup the test pattern */
 313         enable_phy_bypass_mode(enc110, false);
 314
 315         /* A PRBS7 pattern is used for most DP electrical measurements. */
 316
 317         /* Enable PRBS symbols on the lanes */
 318         disable_prbs_symbols(enc110, false);
 319
 320         /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
 321         REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
 322                         DPHY_PRBS_SEL, 0,
 323                         DPHY_PRBS_EN, 1);
 324
 325         /* Enable phy bypass mode to enable the test pattern */
 326         enable_phy_bypass_mode(enc110, true);
 327 }
 328
 329 static void set_dp_phy_pattern_80bit_custom(
 330         struct dce110_link_encoder *enc110,
 331         const uint8_t *pattern)
 332 {
 333         /* Disable PHY Bypass mode to setup the test pattern */
 334         enable_phy_bypass_mode(enc110, false);
 335
 336         /* Enable debug symbols on the lanes */
 337
 338         disable_prbs_symbols(enc110, true);
 339
 340         /* Enable PHY bypass mode to enable the test pattern */
 341         /* TODO is it really needed ? */
 342
 343         enable_phy_bypass_mode(enc110, true);
 344
 345         /* Program 80 bit custom pattern */
 346         {
 347                 uint16_t pattern_symbols[8];
 348
 349                 pattern_symbols[0] =
 350                         ((pattern[1] & 0x03) << 8) | pattern[0];
 351                 pattern_symbols[1] =
 352                         ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
 353                 pattern_symbols[2] =
 354                         ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
 355                 pattern_symbols[3] =
 356                         (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
 357                 pattern_symbols[4] =
 358                         ((pattern[6] & 0x03) << 8) | pattern[5];
 359                 pattern_symbols[5] =
 360                         ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
 361                 pattern_symbols[6] =
 362                         ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
 363                 pattern_symbols[7] =
 364                         (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
 365
 366                 program_pattern_symbols(enc110, pattern_symbols);
 367         }
 368
 369         /* Enable phy bypass mode to enable the test pattern */
 370
 371         enable_phy_bypass_mode(enc110, true);
 372 }
 373
 374 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
 375         struct dce110_link_encoder *enc110,
 376         unsigned int cp2520_pattern)
 377 {
 378
 379         /* previously there is a register DP_HBR2_EYE_PATTERN
 380          * that is enabled to get the pattern.
 381          * But it does not work with the latest spec change,
 382          * so we are programming the following registers manually.
 383          *
 384          * The following settings have been confirmed
 385          * by Nick Chorney and Sandra Liu */
 386
 387         /* Disable PHY Bypass mode to setup the test pattern */
 388
 389         enable_phy_bypass_mode(enc110, false);
 390
 391         /* Setup DIG encoder in DP SST mode */
 392         enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT);
 393
 394         /* ensure normal panel mode. */
 395         setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
 396
 397         /* no vbid after BS (SR)
 398          * DP_LINK_FRAMING_CNTL changed history Sandra Liu
 399          * 11000260 / 11000104 / 110000FC */
 400         REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
 401                         DP_IDLE_BS_INTERVAL, 0xFC,
 402                         DP_VBID_DISABLE, 1,
 403                         DP_VID_ENHANCED_FRAME_MODE, 1);
 404
 405         /* swap every BS with SR */
 406         REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
 407
 408         /* select cp2520 patterns */
 409         if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
 410                 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
 411                                 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
 412         else
 413                 /* pre-DCE11 can only generate CP2520 pattern 2 */
 414                 ASSERT(cp2520_pattern == 2);
 415
 416         /* set link training complete */
 417         set_link_training_complete(enc110, true);
 418
 419         /* disable video stream */
 420         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
 421
 422         /* Disable PHY Bypass mode to setup the test pattern */
 423         enable_phy_bypass_mode(enc110, false);
 424 }
 425
 426 static void set_dp_phy_pattern_passthrough_mode(
 427         struct dce110_link_encoder *enc110,
 428         enum dp_panel_mode panel_mode)
 429 {
 430         /* program correct panel mode */
 431         setup_panel_mode(enc110, panel_mode);
 432
 433         /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
 434          * in case we were doing HBR2 compliance pattern before
 435          */
 436         REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
 437                         DP_IDLE_BS_INTERVAL, 0x2000,
 438                         DP_VBID_DISABLE, 0,
 439                         DP_VID_ENHANCED_FRAME_MODE, 1);
 440
 441         REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
 442
 443         /* set link training complete */
 444         set_link_training_complete(enc110, true);
 445
 446         /* Disable PHY Bypass mode to setup the test pattern */
 447         enable_phy_bypass_mode(enc110, false);
 448
 449         /* Disable PRBS mode */
 450         disable_prbs_mode(enc110);
 451 }
 452
 453 /* return value is bit-vector */
 454 static uint8_t get_frontend_source(
 455         enum engine_id engine)
 456 {
 457         switch (engine) {
 458         case ENGINE_ID_DIGA:
 459                 return DCE110_DIG_FE_SOURCE_SELECT_DIGA;
 460         case ENGINE_ID_DIGB:
 461                 return DCE110_DIG_FE_SOURCE_SELECT_DIGB;
 462         case ENGINE_ID_DIGC:
 463                 return DCE110_DIG_FE_SOURCE_SELECT_DIGC;
 464         case ENGINE_ID_DIGD:
 465                 return DCE110_DIG_FE_SOURCE_SELECT_DIGD;
 466         case ENGINE_ID_DIGE:
 467                 return DCE110_DIG_FE_SOURCE_SELECT_DIGE;
 468         case ENGINE_ID_DIGF:
 469                 return DCE110_DIG_FE_SOURCE_SELECT_DIGF;
 470         case ENGINE_ID_DIGG:
 471                 return DCE110_DIG_FE_SOURCE_SELECT_DIGG;
 472         default:
 473                 ASSERT_CRITICAL(false);
 474                 return DCE110_DIG_FE_SOURCE_SELECT_INVALID;
 475         }
 476 }
 477
 478 static void configure_encoder(
 479         struct dce110_link_encoder *enc110,
 480         const struct dc_link_settings *link_settings)
 481 {
 482         /* set number of lanes */
 483
 484         REG_SET(DP_CONFIG, 0,
 485                         DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
 486
 487         /* setup scrambler */
 488         REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
 489 }
 490
 491 static void aux_initialize(
 492         struct dce110_link_encoder *enc110)
 493 {
 494         struct dc_context *ctx = enc110->base.ctx;
 495         enum hpd_source_id hpd_source = enc110->base.hpd_source;
 496         uint32_t addr = AUX_REG(AUX_CONTROL);
 497         uint32_t value = dm_read_reg(ctx, addr);
 498
 499         set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL);
 500         set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN);
 501         dm_write_reg(ctx, addr, value);
 502
 503         addr = AUX_REG(AUX_DPHY_RX_CONTROL0);
 504         value = dm_read_reg(ctx, addr);
 505
 506         /* 1/4 window (the maximum allowed) */
 507         set_reg_field_value(value, 1,
 508                         AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW);
 509         dm_write_reg(ctx, addr, value);
 510
 511 }
 512
 513 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
 514                         bool exit_link_training_required)
 515 {
 516         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 517
 518         if (exit_link_training_required)
 519                 REG_UPDATE(DP_DPHY_FAST_TRAINING,
 520                                 DPHY_RX_FAST_TRAINING_CAPABLE, 1);
 521         else {
 522                 REG_UPDATE(DP_DPHY_FAST_TRAINING,
 523                                 DPHY_RX_FAST_TRAINING_CAPABLE, 0);
 524                 /*In DCE 11, we are able to pre-program a Force SR register
 525                  * to be able to trigger SR symbol after 5 idle patterns
 526                  * transmitted. Upon PSR Exit, DMCU can trigger
 527                  * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
 528                  * DPHY_LOAD_BS_COUNT_START and the internal counter
 529                  * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
 530                  * replaced by SR symbol once.
 531                  */
 532
 533                 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
 534         }
 535 }
 536
 537 void dce110_psr_program_secondary_packet(struct link_encoder *enc,
 538                         unsigned int sdp_transmit_line_num_deadline)
 539 {
 540         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 541
 542         REG_UPDATE_2(DP_SEC_CNTL1,
 543                 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
 544                 DP_SEC_GSP0_PRIORITY, 1);
 545 }
 546
 547 bool dce110_is_dig_enabled(struct link_encoder *enc)
 548 {
 549         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 550         uint32_t value;
 551
 552         REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
 553         return value;
 554 }
 555
 556 static void link_encoder_disable(struct dce110_link_encoder *enc110)
 557 {
 558         /* reset training pattern */
 559         REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
 560                         DPHY_TRAINING_PATTERN_SEL, 0);
 561
 562         /* reset training complete */
 563         REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
 564
 565         /* reset panel mode */
 566         setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
 567 }
 568
 569 static void hpd_initialize(
 570         struct dce110_link_encoder *enc110)
 571 {
 572         /* Associate HPD with DIG_BE */
 573         enum hpd_source_id hpd_source = enc110->base.hpd_source;
 574
 575         REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
 576 }
 577
 578 bool dce110_link_encoder_validate_dvi_output(
 579         const struct dce110_link_encoder *enc110,
 580         enum signal_type connector_signal,
 581         enum signal_type signal,
 582         const struct dc_crtc_timing *crtc_timing)
 583 {
 584         uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
 585
 586         if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
 587                 max_pixel_clock *= 2;
 588
 589         /* This handles the case of HDMI downgrade to DVI we don't want to
 590          * we don't want to cap the pixel clock if the DDI is not DVI.
 591          */
 592         if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
 593                         connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
 594                 max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock;
 595
 596         /* DVI only support RGB pixel encoding */
 597         if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
 598                 return false;
 599
 600         /*connect DVI via adpater's HDMI connector*/
 601         if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
 602                 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
 603                 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
 604                 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10))
 605                 return false;
 606         if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
 607                 return false;
 608
 609         if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
 610                 return false;
 611
 612         /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
 613         switch (crtc_timing->display_color_depth) {
 614         case COLOR_DEPTH_666:
 615         case COLOR_DEPTH_888:
 616         break;
 617         case COLOR_DEPTH_101010:
 618         case COLOR_DEPTH_161616:
 619                 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
 620                         return false;
 621         break;
 622         default:
 623                 return false;
 624         }
 625
 626         return true;
 627 }
 628
 629 static bool dce110_link_encoder_validate_hdmi_output(
 630         const struct dce110_link_encoder *enc110,
 631         const struct dc_crtc_timing *crtc_timing,
 632         int adjusted_pix_clk_khz)
 633 {
 634         enum dc_color_depth max_deep_color =
 635                         enc110->base.features.max_hdmi_deep_color;
 636
 637         if (max_deep_color < crtc_timing->display_color_depth)
 638                 return false;
 639
 640         if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
 641                 return false;
 642         if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
 643                 return false;
 644
 645         if ((adjusted_pix_clk_khz == 0) ||
 646                 (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock))
 647                 return false;
 648
 649         /* DCE11 HW does not support 420 */
 650         if (!enc110->base.features.hdmi_ycbcr420_supported &&
 651                         crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
 652                 return false;
 653
 654         if (!enc110->base.features.flags.bits.HDMI_6GB_EN &&
 655                 adjusted_pix_clk_khz >= 300000)
 656                 return false;
 657         if (enc110->base.ctx->dc->debug.hdmi20_disable &&
 658                 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
 659                 return false;
 660         return true;
 661 }
 662
 663 bool dce110_link_encoder_validate_dp_output(
 664         const struct dce110_link_encoder *enc110,
 665         const struct dc_crtc_timing *crtc_timing)
 666 {
 667         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
 668                 return false;
 669
 670         return true;
 671 }
 672
 673 void dce110_link_encoder_construct(
 674         struct dce110_link_encoder *enc110,
 675         const struct encoder_init_data *init_data,
 676         const struct encoder_feature_support *enc_features,
 677         const struct dce110_link_enc_registers *link_regs,
 678         const struct dce110_link_enc_aux_registers *aux_regs,
 679         const struct dce110_link_enc_hpd_registers *hpd_regs)
 680 {
 681         struct bp_encoder_cap_info bp_cap_info = {0};
 682         const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
 683         enum bp_result result = BP_RESULT_OK;
 684
 685         enc110->base.funcs = &dce110_lnk_enc_funcs;
 686         enc110->base.ctx = init_data->ctx;
 687         enc110->base.id = init_data->encoder;
 688
 689         enc110->base.hpd_source = init_data->hpd_source;
 690         enc110->base.connector = init_data->connector;
 691
 692         enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
 693
 694         enc110->base.features = *enc_features;
 695
 696         enc110->base.transmitter = init_data->transmitter;
 697
 698         /* set the flag to indicate whether driver poll the I2C data pin
 699          * while doing the DP sink detect
 700          */
 701
 702 /*      if (dal_adapter_service_is_feature_supported(as,
 703                 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
 704                 enc110->base.features.flags.bits.
 705                         DP_SINK_DETECT_POLL_DATA_PIN = true;*/
 706
 707         enc110->base.output_signals =
 708                 SIGNAL_TYPE_DVI_SINGLE_LINK |
 709                 SIGNAL_TYPE_DVI_DUAL_LINK |
 710                 SIGNAL_TYPE_LVDS |
 711                 SIGNAL_TYPE_DISPLAY_PORT |
 712                 SIGNAL_TYPE_DISPLAY_PORT_MST |
 713                 SIGNAL_TYPE_EDP |
 714                 SIGNAL_TYPE_HDMI_TYPE_A;
 715
 716         /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
 717          * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
 718          * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
 719          * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
 720          * Prefer DIG assignment is decided by board design.
 721          * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
 722          * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
 723          * By this, adding DIGG should not hurt DCE 8.0.
 724          * This will let DCE 8.1 share DCE 8.0 as much as possible
 725          */
 726
 727         enc110->link_regs = link_regs;
 728         enc110->aux_regs = aux_regs;
 729         enc110->hpd_regs = hpd_regs;
 730
 731         switch (enc110->base.transmitter) {
 732         case TRANSMITTER_UNIPHY_A:
 733                 enc110->base.preferred_engine = ENGINE_ID_DIGA;
 734         break;
 735         case TRANSMITTER_UNIPHY_B:
 736                 enc110->base.preferred_engine = ENGINE_ID_DIGB;
 737         break;
 738         case TRANSMITTER_UNIPHY_C:
 739                 enc110->base.preferred_engine = ENGINE_ID_DIGC;
 740         break;
 741         case TRANSMITTER_UNIPHY_D:
 742                 enc110->base.preferred_engine = ENGINE_ID_DIGD;
 743         break;
 744         case TRANSMITTER_UNIPHY_E:
 745                 enc110->base.preferred_engine = ENGINE_ID_DIGE;
 746         break;
 747         case TRANSMITTER_UNIPHY_F:
 748                 enc110->base.preferred_engine = ENGINE_ID_DIGF;
 749         break;
 750         case TRANSMITTER_UNIPHY_G:
 751                 enc110->base.preferred_engine = ENGINE_ID_DIGG;
 752         break;
 753         default:
 754                 ASSERT_CRITICAL(false);
 755                 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
 756         }
 757
 758         /* default to one to mirror Windows behavior */
 759         enc110->base.features.flags.bits.HDMI_6GB_EN = 1;
 760
 761         result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios,
 762                                                 enc110->base.id, &bp_cap_info);
 763
 764         /* Override features with DCE-specific values */
 765         if (BP_RESULT_OK == result) {
 766                 enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
 767                                 bp_cap_info.DP_HBR2_EN;
 768                 enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
 769                                 bp_cap_info.DP_HBR3_EN;
 770                 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
 771         } else {
 772                 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
 773                                 __func__,
 774                                 result);
 775         }
 776         if (enc110->base.ctx->dc->debug.hdmi20_disable) {
 777                 enc110->base.features.flags.bits.HDMI_6GB_EN = 0;
 778         }
 779 }
 780
 781 bool dce110_link_encoder_validate_output_with_stream(
 782         struct link_encoder *enc,
 783         const struct dc_stream_state *stream)
 784 {
 785         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 786         bool is_valid;
 787
 788         switch (stream->signal) {
 789         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 790         case SIGNAL_TYPE_DVI_DUAL_LINK:
 791                 is_valid = dce110_link_encoder_validate_dvi_output(
 792                         enc110,
 793                         stream->link->connector_signal,
 794                         stream->signal,
 795                         &stream->timing);
 796         break;
 797         case SIGNAL_TYPE_HDMI_TYPE_A:
 798                 is_valid = dce110_link_encoder_validate_hdmi_output(
 799                                 enc110,
 800                                 &stream->timing,
 801                                 stream->phy_pix_clk);
 802         break;
 803         case SIGNAL_TYPE_DISPLAY_PORT:
 804         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 805                 is_valid = dce110_link_encoder_validate_dp_output(
 806                                         enc110, &stream->timing);
 807         break;
 808         case SIGNAL_TYPE_EDP:
 809         case SIGNAL_TYPE_LVDS:
 810                 is_valid =
 811                         (stream->timing.
 812                                 pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
 813         break;
 814         case SIGNAL_TYPE_VIRTUAL:
 815                 is_valid = true;
 816                 break;
 817         default:
 818                 is_valid = false;
 819         break;
 820         }
 821
 822         return is_valid;
 823 }
 824
 825 void dce110_link_encoder_hw_init(
 826         struct link_encoder *enc)
 827 {
 828         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 829         struct bp_transmitter_control cntl = { 0 };
 830         enum bp_result result;
 831
 832         cntl.action = TRANSMITTER_CONTROL_INIT;
 833         cntl.engine_id = ENGINE_ID_UNKNOWN;
 834         cntl.transmitter = enc110->base.transmitter;
 835         cntl.connector_obj_id = enc110->base.connector;
 836         cntl.lanes_number = LANE_COUNT_FOUR;
 837         cntl.coherent = false;
 838         cntl.hpd_sel = enc110->base.hpd_source;
 839
 840         if (enc110->base.connector.id == CONNECTOR_ID_EDP)
 841                 cntl.signal = SIGNAL_TYPE_EDP;
 842
 843         result = link_transmitter_control(enc110, &cntl);
 844
 845         if (result != BP_RESULT_OK) {
 846                 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
 847                         __func__);
 848                 BREAK_TO_DEBUGGER();
 849                 return;
 850         }
 851
 852         if (enc110->base.connector.id == CONNECTOR_ID_LVDS) {
 853                 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
 854
 855                 result = link_transmitter_control(enc110, &cntl);
 856
 857                 ASSERT(result == BP_RESULT_OK);
 858
 859         }
 860         aux_initialize(enc110);
 861
 862         /* reinitialize HPD.
 863          * hpd_initialize() will pass DIG_FE id to HW context.
 864          * All other routine within HW context will use fe_engine_offset
 865          * as DIG_FE id even caller pass DIG_FE id.
 866          * So this routine must be called first. */
 867         hpd_initialize(enc110);
 868 }
 869
 870 void dce110_link_encoder_destroy(struct link_encoder **enc)
 871 {
 872         kfree(TO_DCE110_LINK_ENC(*enc));
 873         *enc = NULL;
 874 }
 875
 876 void dce110_link_encoder_setup(
 877         struct link_encoder *enc,
 878         enum signal_type signal)
 879 {
 880         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 881
 882         switch (signal) {
 883         case SIGNAL_TYPE_EDP:
 884         case SIGNAL_TYPE_DISPLAY_PORT:
 885                 /* DP SST */
 886                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
 887                 break;
 888         case SIGNAL_TYPE_LVDS:
 889                 /* LVDS */
 890                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
 891                 break;
 892         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 893         case SIGNAL_TYPE_DVI_DUAL_LINK:
 894                 /* TMDS-DVI */
 895                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
 896                 break;
 897         case SIGNAL_TYPE_HDMI_TYPE_A:
 898                 /* TMDS-HDMI */
 899                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
 900                 break;
 901         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 902                 /* DP MST */
 903                 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
 904                 break;
 905         default:
 906                 ASSERT_CRITICAL(false);
 907                 /* invalid mode ! */
 908                 break;
 909         }
 910
 911 }
 912
 913 /* TODO: still need depth or just pass in adjusted pixel clock? */
 914 void dce110_link_encoder_enable_tmds_output(
 915         struct link_encoder *enc,
 916         enum clock_source_id clock_source,
 917         enum dc_color_depth color_depth,
 918         enum signal_type signal,
 919         uint32_t pixel_clock)
 920 {
 921         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 922         struct bp_transmitter_control cntl = { 0 };
 923         enum bp_result result;
 924
 925         /* Enable the PHY */
 926         cntl.connector_obj_id = enc110->base.connector;
 927         cntl.action = TRANSMITTER_CONTROL_ENABLE;
 928         cntl.engine_id = enc->preferred_engine;
 929         cntl.transmitter = enc110->base.transmitter;
 930         cntl.pll_id = clock_source;
 931         cntl.signal = signal;
 932         if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
 933                 cntl.lanes_number = 8;
 934         else
 935                 cntl.lanes_number = 4;
 936
 937         cntl.hpd_sel = enc110->base.hpd_source;
 938
 939         cntl.pixel_clock = pixel_clock;
 940         cntl.color_depth = color_depth;
 941
 942         result = link_transmitter_control(enc110, &cntl);
 943
 944         if (result != BP_RESULT_OK) {
 945                 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
 946                         __func__);
 947                 BREAK_TO_DEBUGGER();
 948         }
 949 }
 950
 951 /* TODO: still need depth or just pass in adjusted pixel clock? */
 952 void dce110_link_encoder_enable_lvds_output(
 953         struct link_encoder *enc,
 954         enum clock_source_id clock_source,
 955         uint32_t pixel_clock)
 956 {
 957         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 958         struct bp_transmitter_control cntl = { 0 };
 959         enum bp_result result;
 960
 961         /* Enable the PHY */
 962         cntl.connector_obj_id = enc110->base.connector;
 963         cntl.action = TRANSMITTER_CONTROL_ENABLE;
 964         cntl.engine_id = enc->preferred_engine;
 965         cntl.transmitter = enc110->base.transmitter;
 966         cntl.pll_id = clock_source;
 967         cntl.signal = SIGNAL_TYPE_LVDS;
 968         cntl.lanes_number = 4;
 969
 970         cntl.hpd_sel = enc110->base.hpd_source;
 971
 972         cntl.pixel_clock = pixel_clock;
 973
 974         result = link_transmitter_control(enc110, &cntl);
 975
 976         if (result != BP_RESULT_OK) {
 977                 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
 978                         __func__);
 979                 BREAK_TO_DEBUGGER();
 980         }
 981 }
 982
 983 /* enables DP PHY output */
 984 void dce110_link_encoder_enable_dp_output(
 985         struct link_encoder *enc,
 986         const struct dc_link_settings *link_settings,
 987         enum clock_source_id clock_source)
 988 {
 989         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 990         struct bp_transmitter_control cntl = { 0 };
 991         enum bp_result result;
 992
 993         /* Enable the PHY */
 994
 995         /* number_of_lanes is used for pixel clock adjust,
 996          * but it's not passed to asic_control.
 997          * We need to set number of lanes manually.
 998          */
 999         configure_encoder(enc110, link_settings);
1000         cntl.connector_obj_id = enc110->base.connector;
1001         cntl.action = TRANSMITTER_CONTROL_ENABLE;
1002         cntl.engine_id = enc->preferred_engine;
1003         cntl.transmitter = enc110->base.transmitter;
1004         cntl.pll_id = clock_source;
1005         cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
1006         cntl.lanes_number = link_settings->lane_count;
1007         cntl.hpd_sel = enc110->base.hpd_source;
1008         cntl.pixel_clock = link_settings->link_rate
1009                                                 * LINK_RATE_REF_FREQ_IN_KHZ;
1010         /* TODO: check if undefined works */
1011         cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1012
1013         result = link_transmitter_control(enc110, &cntl);
1014
1015         if (result != BP_RESULT_OK) {
1016                 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1017                         __func__);
1018                 BREAK_TO_DEBUGGER();
1019         }
1020 }
1021
1022 /* enables DP PHY output in MST mode */
1023 void dce110_link_encoder_enable_dp_mst_output(
1024         struct link_encoder *enc,
1025         const struct dc_link_settings *link_settings,
1026         enum clock_source_id clock_source)
1027 {
1028         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1029         struct bp_transmitter_control cntl = { 0 };
1030         enum bp_result result;
1031
1032         /* Enable the PHY */
1033
1034         /* number_of_lanes is used for pixel clock adjust,
1035          * but it's not passed to asic_control.
1036          * We need to set number of lanes manually.
1037          */
1038         configure_encoder(enc110, link_settings);
1039
1040         cntl.action = TRANSMITTER_CONTROL_ENABLE;
1041         cntl.engine_id = ENGINE_ID_UNKNOWN;
1042         cntl.transmitter = enc110->base.transmitter;
1043         cntl.pll_id = clock_source;
1044         cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1045         cntl.lanes_number = link_settings->lane_count;
1046         cntl.hpd_sel = enc110->base.hpd_source;
1047         cntl.pixel_clock = link_settings->link_rate
1048                                                 * LINK_RATE_REF_FREQ_IN_KHZ;
1049         /* TODO: check if undefined works */
1050         cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1051
1052         result = link_transmitter_control(enc110, &cntl);
1053
1054         if (result != BP_RESULT_OK) {
1055                 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1056                         __func__);
1057                 BREAK_TO_DEBUGGER();
1058         }
1059 }
1060 /*
1061  * @brief
1062  * Disable transmitter and its encoder
1063  */
1064 void dce110_link_encoder_disable_output(
1065         struct link_encoder *enc,
1066         enum signal_type signal)
1067 {
1068         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1069         struct bp_transmitter_control cntl = { 0 };
1070         enum bp_result result;
1071
1072         if (!dce110_is_dig_enabled(enc)) {
1073                 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
1074                 return;
1075         }
1076         /* Power-down RX and disable GPU PHY should be paired.
1077          * Disabling PHY without powering down RX may cause
1078          * symbol lock loss, on which we will get DP Sink interrupt. */
1079
1080         /* There is a case for the DP active dongles
1081          * where we want to disable the PHY but keep RX powered,
1082          * for those we need to ignore DP Sink interrupt
1083          * by checking lane count that has been set
1084          * on the last do_enable_output(). */
1085
1086         /* disable transmitter */
1087         cntl.action = TRANSMITTER_CONTROL_DISABLE;
1088         cntl.transmitter = enc110->base.transmitter;
1089         cntl.hpd_sel = enc110->base.hpd_source;
1090         cntl.signal = signal;
1091         cntl.connector_obj_id = enc110->base.connector;
1092
1093         result = link_transmitter_control(enc110, &cntl);
1094
1095         if (result != BP_RESULT_OK) {
1096                 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1097                         __func__);
1098                 BREAK_TO_DEBUGGER();
1099                 return;
1100         }
1101
1102         /* disable encoder */
1103         if (dc_is_dp_signal(signal))
1104                 link_encoder_disable(enc110);
1105 }
1106
1107 void dce110_link_encoder_dp_set_lane_settings(
1108         struct link_encoder *enc,
1109         const struct link_training_settings *link_settings)
1110 {
1111         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1112         union dpcd_training_lane_set training_lane_set = { { 0 } };
1113         int32_t lane = 0;
1114         struct bp_transmitter_control cntl = { 0 };
1115
1116         if (!link_settings) {
1117                 BREAK_TO_DEBUGGER();
1118                 return;
1119         }
1120
1121         cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1122         cntl.transmitter = enc110->base.transmitter;
1123         cntl.connector_obj_id = enc110->base.connector;
1124         cntl.lanes_number = link_settings->link_settings.lane_count;
1125         cntl.hpd_sel = enc110->base.hpd_source;
1126         cntl.pixel_clock = link_settings->link_settings.link_rate *
1127                                                 LINK_RATE_REF_FREQ_IN_KHZ;
1128
1129         for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1130                 /* translate lane settings */
1131
1132                 training_lane_set.bits.VOLTAGE_SWING_SET =
1133                         link_settings->lane_settings[lane].VOLTAGE_SWING;
1134                 training_lane_set.bits.PRE_EMPHASIS_SET =
1135                         link_settings->lane_settings[lane].PRE_EMPHASIS;
1136
1137                 /* post cursor 2 setting only applies to HBR2 link rate */
1138                 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
1139                         /* this is passed to VBIOS
1140                          * to program post cursor 2 level */
1141
1142                         training_lane_set.bits.POST_CURSOR2_SET =
1143                                 link_settings->lane_settings[lane].POST_CURSOR2;
1144                 }
1145
1146                 cntl.lane_select = lane;
1147                 cntl.lane_settings = training_lane_set.raw;
1148
1149                 /* call VBIOS table to set voltage swing and pre-emphasis */
1150                 link_transmitter_control(enc110, &cntl);
1151         }
1152 }
1153
1154 /* set DP PHY test and training patterns */
1155 void dce110_link_encoder_dp_set_phy_pattern(
1156         struct link_encoder *enc,
1157         const struct encoder_set_dp_phy_pattern_param *param)
1158 {
1159         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1160
1161         switch (param->dp_phy_pattern) {
1162         case DP_TEST_PATTERN_TRAINING_PATTERN1:
1163                 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1164                 break;
1165         case DP_TEST_PATTERN_TRAINING_PATTERN2:
1166                 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1167                 break;
1168         case DP_TEST_PATTERN_TRAINING_PATTERN3:
1169                 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1170                 break;
1171         case DP_TEST_PATTERN_TRAINING_PATTERN4:
1172                 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1173                 break;
1174         case DP_TEST_PATTERN_D102:
1175                 set_dp_phy_pattern_d102(enc110);
1176                 break;
1177         case DP_TEST_PATTERN_SYMBOL_ERROR:
1178                 set_dp_phy_pattern_symbol_error(enc110);
1179                 break;
1180         case DP_TEST_PATTERN_PRBS7:
1181                 set_dp_phy_pattern_prbs7(enc110);
1182                 break;
1183         case DP_TEST_PATTERN_80BIT_CUSTOM:
1184                 set_dp_phy_pattern_80bit_custom(
1185                         enc110, param->custom_pattern);
1186                 break;
1187         case DP_TEST_PATTERN_CP2520_1:
1188                 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1);
1189                 break;
1190         case DP_TEST_PATTERN_CP2520_2:
1191                 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2);
1192                 break;
1193         case DP_TEST_PATTERN_CP2520_3:
1194                 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3);
1195                 break;
1196         case DP_TEST_PATTERN_VIDEO_MODE: {
1197                 set_dp_phy_pattern_passthrough_mode(
1198                         enc110, param->dp_panel_mode);
1199                 break;
1200         }
1201
1202         default:
1203                 /* invalid phy pattern */
1204                 ASSERT_CRITICAL(false);
1205                 break;
1206         }
1207 }
1208
1209 static void fill_stream_allocation_row_info(
1210         const struct link_mst_stream_allocation *stream_allocation,
1211         uint32_t *src,
1212         uint32_t *slots)
1213 {
1214         const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1215
1216         if (stream_enc) {
1217                 *src = stream_enc->id;
1218                 *slots = stream_allocation->slot_count;
1219         } else {
1220                 *src = 0;
1221                 *slots = 0;
1222         }
1223 }
1224
1225 /* programs DP MST VC payload allocation */
1226 void dce110_link_encoder_update_mst_stream_allocation_table(
1227         struct link_encoder *enc,
1228         const struct link_mst_stream_allocation_table *table)
1229 {
1230         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1231         uint32_t value0 = 0;
1232         uint32_t value1 = 0;
1233         uint32_t value2 = 0;
1234         uint32_t slots = 0;
1235         uint32_t src = 0;
1236         uint32_t retries = 0;
1237
1238         /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1239
1240         /* --- Set MSE Stream Attribute -
1241          * Setup VC Payload Table on Tx Side,
1242          * Issue allocation change trigger
1243          * to commit payload on both tx and rx side */
1244
1245         /* we should clean-up table each time */
1246
1247         if (table->stream_count >= 1) {
1248                 fill_stream_allocation_row_info(
1249                         &table->stream_allocations[0],
1250                         &src,
1251                         &slots);
1252         } else {
1253                 src = 0;
1254                 slots = 0;
1255         }
1256
1257         REG_UPDATE_2(DP_MSE_SAT0,
1258                         DP_MSE_SAT_SRC0, src,
1259                         DP_MSE_SAT_SLOT_COUNT0, slots);
1260
1261         if (table->stream_count >= 2) {
1262                 fill_stream_allocation_row_info(
1263                         &table->stream_allocations[1],
1264                         &src,
1265                         &slots);
1266         } else {
1267                 src = 0;
1268                 slots = 0;
1269         }
1270
1271         REG_UPDATE_2(DP_MSE_SAT0,
1272                         DP_MSE_SAT_SRC1, src,
1273                         DP_MSE_SAT_SLOT_COUNT1, slots);
1274
1275         if (table->stream_count >= 3) {
1276                 fill_stream_allocation_row_info(
1277                         &table->stream_allocations[2],
1278                         &src,
1279                         &slots);
1280         } else {
1281                 src = 0;
1282                 slots = 0;
1283         }
1284
1285         REG_UPDATE_2(DP_MSE_SAT1,
1286                         DP_MSE_SAT_SRC2, src,
1287                         DP_MSE_SAT_SLOT_COUNT2, slots);
1288
1289         if (table->stream_count >= 4) {
1290                 fill_stream_allocation_row_info(
1291                         &table->stream_allocations[3],
1292                         &src,
1293                         &slots);
1294         } else {
1295                 src = 0;
1296                 slots = 0;
1297         }
1298
1299         REG_UPDATE_2(DP_MSE_SAT1,
1300                         DP_MSE_SAT_SRC3, src,
1301                         DP_MSE_SAT_SLOT_COUNT3, slots);
1302
1303         /* --- wait for transaction finish */
1304
1305         /* send allocation change trigger (ACT) ?
1306          * this step first sends the ACT,
1307          * then double buffers the SAT into the hardware
1308          * making the new allocation active on the DP MST mode link */
1309
1310
1311         /* DP_MSE_SAT_UPDATE:
1312          * 0 - No Action
1313          * 1 - Update SAT with trigger
1314          * 2 - Update SAT without trigger */
1315
1316         REG_UPDATE(DP_MSE_SAT_UPDATE,
1317                         DP_MSE_SAT_UPDATE, 1);
1318
1319         /* wait for update to complete
1320          * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1321          * then wait for the transmission
1322          * of at least 16 MTP headers on immediate local link.
1323          * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1324          * a value of 1 indicates that DP MST mode
1325          * is in the 16 MTP keepout region after a VC has been added.
1326          * MST stream bandwidth (VC rate) can be configured
1327          * after this bit is cleared */
1328
1329         do {
1330                 udelay(10);
1331
1332                 value0 = REG_READ(DP_MSE_SAT_UPDATE);
1333
1334                 REG_GET(DP_MSE_SAT_UPDATE,
1335                                 DP_MSE_SAT_UPDATE, &value1);
1336
1337                 REG_GET(DP_MSE_SAT_UPDATE,
1338                                 DP_MSE_16_MTP_KEEPOUT, &value2);
1339
1340                 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1341                 if (!value1 && !value2)
1342                         break;
1343                 ++retries;
1344         } while (retries < DP_MST_UPDATE_MAX_RETRY);
1345 }
1346
1347 void dce110_link_encoder_connect_dig_be_to_fe(
1348         struct link_encoder *enc,
1349         enum engine_id engine,
1350         bool connect)
1351 {
1352         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1353         uint32_t field;
1354
1355         if (engine != ENGINE_ID_UNKNOWN) {
1356
1357                 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1358
1359                 if (connect)
1360                         field |= get_frontend_source(engine);
1361                 else
1362                         field &= ~get_frontend_source(engine);
1363
1364                 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1365         }
1366 }
1367
1368 void dce110_link_encoder_enable_hpd(struct link_encoder *enc)
1369 {
1370         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1371         struct dc_context *ctx = enc110->base.ctx;
1372         uint32_t addr = HPD_REG(DC_HPD_CONTROL);
1373         uint32_t hpd_enable = 0;
1374         uint32_t value = dm_read_reg(ctx, addr);
1375
1376         get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN);
1377
1378         if (hpd_enable == 0)
1379                 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN);
1380 }
1381
1382 void dce110_link_encoder_disable_hpd(struct link_encoder *enc)
1383 {
1384         struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1385         struct dc_context *ctx = enc110->base.ctx;
1386         uint32_t addr = HPD_REG(DC_HPD_CONTROL);
1387         uint32_t value = dm_read_reg(ctx, addr);
1388
1389         set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN);
1390 }