2 * Copyright 2012-16 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dce_clk_mgr.h"
28 #include "reg_helper.h"
30 #include "core_types.h"
31 #include "dal_asic_id.h"
33 #define TO_DCE_CLK_MGR(clocks)\
34 container_of(clocks, struct dce_clk_mgr, base)
37 (clk_mgr_dce->regs->reg)
40 #define FN(reg_name, field_name) \
41 clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name
48 /* Max clock values for each state indexed by "enum clocks_state": */
49 static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
50 /* ClocksStateInvalid - should not be used */
51 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
52 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
53 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
55 { .display_clk_khz = 352000, .pixel_clk_khz = 330000},
56 /* ClocksStateNominal */
57 { .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
58 /* ClocksStatePerformance */
59 { .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
61 static const struct state_dependent_clocks dce110_max_clks_by_state[] = {
62 /*ClocksStateInvalid - should not be used*/
63 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
64 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
65 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
67 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
68 /*ClocksStateNominal*/
69 { .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
70 /*ClocksStatePerformance*/
71 { .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
73 static const struct state_dependent_clocks dce112_max_clks_by_state[] = {
74 /*ClocksStateInvalid - should not be used*/
75 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
76 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
77 { .display_clk_khz = 389189, .pixel_clk_khz = 346672 },
79 { .display_clk_khz = 459000, .pixel_clk_khz = 400000 },
80 /*ClocksStateNominal*/
81 { .display_clk_khz = 667000, .pixel_clk_khz = 600000 },
82 /*ClocksStatePerformance*/
83 { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
85 static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
86 /*ClocksStateInvalid - should not be used*/
87 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
88 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
89 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
91 { .display_clk_khz = 460000, .pixel_clk_khz = 400000 },
92 /*ClocksStateNominal*/
93 { .display_clk_khz = 670000, .pixel_clk_khz = 600000 },
94 /*ClocksStatePerformance*/
95 { .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
97 int dentist_get_divider_from_did(int did)
99 if (did < DENTIST_BASE_DID_1)
100 did = DENTIST_BASE_DID_1;
101 if (did > DENTIST_MAX_DID)
102 did = DENTIST_MAX_DID;
104 if (did < DENTIST_BASE_DID_2) {
105 return DENTIST_DIVIDER_RANGE_1_START + DENTIST_DIVIDER_RANGE_1_STEP
106 * (did - DENTIST_BASE_DID_1);
107 } else if (did < DENTIST_BASE_DID_3) {
108 return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP
109 * (did - DENTIST_BASE_DID_2);
110 } else if (did < DENTIST_BASE_DID_4) {
111 return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP
112 * (did - DENTIST_BASE_DID_3);
114 return DENTIST_DIVIDER_RANGE_4_START + DENTIST_DIVIDER_RANGE_4_STEP
115 * (did - DENTIST_BASE_DID_4);
119 /* SW will adjust DP REF Clock average value for all purposes
120 * (DP DTO / DP Audio DTO and DP GTC)
121 if clock is spread for all cases:
122 -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
123 calculations for DS_INCR/DS_MODULO (this is planned to be default case)
124 -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
125 calculations (not planned to be used, but average clock should still
127 -if SS enabled on DP Ref clock and HW de-spreading disabled
128 (should not be case with CIK) then SW should program all rates
129 generated according to average value (case as with previous ASICs)
131 static int clk_mgr_adjust_dp_ref_freq_for_ss(struct dce_clk_mgr *clk_mgr_dce, int dp_ref_clk_khz)
133 if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) {
134 struct fixed31_32 ss_percentage = dc_fixpt_div_int(
135 dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage,
136 clk_mgr_dce->dprefclk_ss_divider), 200);
137 struct fixed31_32 adj_dp_ref_clk_khz;
139 ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage);
140 adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);
141 dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
143 return dp_ref_clk_khz;
146 static int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr)
148 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
149 int dprefclk_wdivider;
150 int dprefclk_src_sel;
151 int dp_ref_clk_khz = 600000;
154 /* ASSERT DP Reference Clock source is from DFS*/
155 REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
156 ASSERT(dprefclk_src_sel == 0);
158 /* Read the mmDENTIST_DISPCLK_CNTL to get the currently
159 * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
160 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
162 /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
163 target_div = dentist_get_divider_from_did(dprefclk_wdivider);
165 /* Calculate the current DFS clock, in kHz.*/
166 dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
167 * clk_mgr_dce->dentist_vco_freq_khz) / target_div;
169 return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, dp_ref_clk_khz);
172 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr)
174 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
176 return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz);
179 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
180 * may not be programmed yet
182 static uint32_t get_max_pixel_clock_for_all_paths(struct dc_state *context)
184 uint32_t max_pix_clk = 0;
187 for (i = 0; i < MAX_PIPES; i++) {
188 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
190 if (pipe_ctx->stream == NULL)
193 /* do not check under lay */
194 if (pipe_ctx->top_pipe)
197 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
198 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
200 /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS
201 * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
203 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
204 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
205 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
211 static enum dm_pp_clocks_state dce_get_required_clocks_state(
212 struct clk_mgr *clk_mgr,
213 struct dc_state *context)
215 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
217 enum dm_pp_clocks_state low_req_clk;
218 int max_pix_clk = get_max_pixel_clock_for_all_paths(context);
220 /* Iterate from highest supported to lowest valid state, and update
221 * lowest RequiredState with the lowest state that satisfies
222 * all required clocks
224 for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
225 if (context->bw.dce.dispclk_khz >
226 clk_mgr_dce->max_clks_by_state[i].display_clk_khz
228 clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz)
232 if (low_req_clk > clk_mgr_dce->max_clks_state) {
233 /* set max clock state for high phyclock, invalid on exceeding display clock */
234 if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz
235 < context->bw.dce.dispclk_khz)
236 low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
238 low_req_clk = clk_mgr_dce->max_clks_state;
244 static int dce_set_clock(
245 struct clk_mgr *clk_mgr,
246 int requested_clk_khz)
248 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
249 struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
250 struct dc_bios *bp = clk_mgr->ctx->dc_bios;
251 int actual_clock = requested_clk_khz;
252 struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
254 /* Make sure requested clock isn't lower than minimum threshold*/
255 if (requested_clk_khz > 0)
256 requested_clk_khz = max(requested_clk_khz,
257 clk_mgr_dce->dentist_vco_freq_khz / 64);
259 /* Prepare to program display clock*/
260 pxl_clk_params.target_pixel_clock = requested_clk_khz;
261 pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
263 if (clk_mgr_dce->dfs_bypass_active)
264 pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;
266 bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
268 if (clk_mgr_dce->dfs_bypass_active) {
269 /* Cache the fixed display clock*/
270 clk_mgr_dce->dfs_bypass_disp_clk =
271 pxl_clk_params.dfs_bypass_display_clock;
272 actual_clock = pxl_clk_params.dfs_bypass_display_clock;
275 /* from power down, we need mark the clock state as ClocksStateNominal
276 * from HWReset, so when resume we will call pplib voltage regulator.*/
277 if (requested_clk_khz == 0)
278 clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
280 if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
281 dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
286 int dce112_set_clock(struct clk_mgr *clk_mgr, int requested_clk_khz)
288 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
289 struct bp_set_dce_clock_parameters dce_clk_params;
290 struct dc_bios *bp = clk_mgr->ctx->dc_bios;
291 struct dc *core_dc = clk_mgr->ctx->dc;
292 struct dmcu *dmcu = core_dc->res_pool->dmcu;
293 int actual_clock = requested_clk_khz;
294 /* Prepare to program display clock*/
295 memset(&dce_clk_params, 0, sizeof(dce_clk_params));
297 /* Make sure requested clock isn't lower than minimum threshold*/
298 if (requested_clk_khz > 0)
299 requested_clk_khz = max(requested_clk_khz,
300 clk_mgr_dce->dentist_vco_freq_khz / 62);
302 dce_clk_params.target_clock_frequency = requested_clk_khz;
303 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
304 dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
306 bp->funcs->set_dce_clock(bp, &dce_clk_params);
307 actual_clock = dce_clk_params.target_clock_frequency;
309 /* from power down, we need mark the clock state as ClocksStateNominal
310 * from HWReset, so when resume we will call pplib voltage regulator.*/
311 if (requested_clk_khz == 0)
312 clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
314 /*Program DP ref Clock*/
315 /*VBIOS will determine DPREFCLK frequency, so we don't set it*/
316 dce_clk_params.target_clock_frequency = 0;
317 dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
318 if (!ASICREV_IS_VEGA20_P(clk_mgr->ctx->asic_id.hw_internal_rev))
319 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
320 (dce_clk_params.pll_id ==
321 CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
323 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
325 bp->funcs->set_dce_clock(bp, &dce_clk_params);
327 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
328 if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
329 if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
330 dmcu->funcs->set_psr_wait_loop(dmcu,
331 actual_clock / 1000 / 7);
335 clk_mgr_dce->dfs_bypass_disp_clk = actual_clock;
339 static void dce_clock_read_integrated_info(struct dce_clk_mgr *clk_mgr_dce)
341 struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
342 struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
343 struct integrated_info info = { { { 0 } } };
344 struct dc_firmware_info fw_info = { { 0 } };
347 if (bp->integrated_info)
348 info = *bp->integrated_info;
350 clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq;
351 if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
352 bp->funcs->get_firmware_info(bp, &fw_info);
353 clk_mgr_dce->dentist_vco_freq_khz =
354 fw_info.smu_gpu_pll_output_freq;
355 if (clk_mgr_dce->dentist_vco_freq_khz == 0)
356 clk_mgr_dce->dentist_vco_freq_khz = 3600000;
359 /*update the maximum display clock for each power state*/
360 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
361 enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
365 clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
369 clk_state = DM_PP_CLOCKS_STATE_LOW;
373 clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
377 clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
381 clk_state = DM_PP_CLOCKS_STATE_INVALID;
385 /*Do not allow bad VBIOS/SBIOS to override with invalid values,
386 * check for > 100MHz*/
387 if (info.disp_clk_voltage[i].max_supported_clk >= 100000)
388 clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
389 info.disp_clk_voltage[i].max_supported_clk;
392 if (!debug->disable_dfs_bypass && bp->integrated_info)
393 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
394 clk_mgr_dce->dfs_bypass_enabled = true;
397 void dce_clock_read_ss_info(struct dce_clk_mgr *clk_mgr_dce)
399 struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
400 int ss_info_num = bp->funcs->get_ss_entry_number(
401 bp, AS_SIGNAL_TYPE_GPU_PLL);
404 struct spread_spectrum_info info = { { 0 } };
405 enum bp_result result = bp->funcs->get_spread_spectrum_info(
406 bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
408 /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
409 * even if SS not enabled and in that case
410 * SSInfo.spreadSpectrumPercentage !=0 would be sign
413 if (result == BP_RESULT_OK &&
414 info.spread_spectrum_percentage != 0) {
415 clk_mgr_dce->ss_on_dprefclk = true;
416 clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
418 if (info.type.CENTER_MODE == 0) {
419 /* TODO: Currently for DP Reference clock we
420 * need only SS percentage for
422 clk_mgr_dce->dprefclk_ss_percentage =
423 info.spread_spectrum_percentage;
429 result = bp->funcs->get_spread_spectrum_info(
430 bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info);
432 /* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS
433 * even if SS not enabled and in that case
434 * SSInfo.spreadSpectrumPercentage !=0 would be sign
437 if (result == BP_RESULT_OK &&
438 info.spread_spectrum_percentage != 0) {
439 clk_mgr_dce->ss_on_dprefclk = true;
440 clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
442 if (info.type.CENTER_MODE == 0) {
443 /* Currently for DP Reference clock we
444 * need only SS percentage for
446 clk_mgr_dce->dprefclk_ss_percentage =
447 info.spread_spectrum_percentage;
453 void dce110_fill_display_configs(
454 const struct dc_state *context,
455 struct dm_pp_display_configuration *pp_display_cfg)
460 for (j = 0; j < context->stream_count; j++) {
463 const struct dc_stream_state *stream = context->streams[j];
464 struct dm_pp_single_disp_config *cfg =
465 &pp_display_cfg->disp_configs[num_cfgs];
466 const struct pipe_ctx *pipe_ctx = NULL;
468 for (k = 0; k < MAX_PIPES; k++)
469 if (stream == context->res_ctx.pipe_ctx[k].stream) {
470 pipe_ctx = &context->res_ctx.pipe_ctx[k];
474 ASSERT(pipe_ctx != NULL);
476 /* only notify active stream */
477 if (stream->dpms_off)
481 cfg->signal = pipe_ctx->stream->signal;
482 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
483 cfg->src_height = stream->src.height;
484 cfg->src_width = stream->src.width;
485 cfg->ddi_channel_mapping =
486 stream->sink->link->ddi_channel_mapping.raw;
488 stream->sink->link->link_enc->transmitter;
489 cfg->link_settings.lane_count =
490 stream->sink->link->cur_link_settings.lane_count;
491 cfg->link_settings.link_rate =
492 stream->sink->link->cur_link_settings.link_rate;
493 cfg->link_settings.link_spread =
494 stream->sink->link->cur_link_settings.link_spread;
495 cfg->sym_clock = stream->phy_pix_clk;
497 cfg->v_refresh = stream->timing.pix_clk_khz * 1000;
498 cfg->v_refresh /= stream->timing.h_total;
499 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
500 / stream->timing.v_total;
503 pp_display_cfg->display_count = num_cfgs;
506 static uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
509 uint32_t min_vertical_blank_time = -1;
511 for (j = 0; j < context->stream_count; j++) {
512 struct dc_stream_state *stream = context->streams[j];
513 uint32_t vertical_blank_in_pixels = 0;
514 uint32_t vertical_blank_time = 0;
516 vertical_blank_in_pixels = stream->timing.h_total *
517 (stream->timing.v_total
518 - stream->timing.v_addressable);
520 vertical_blank_time = vertical_blank_in_pixels
521 * 1000 / stream->timing.pix_clk_khz;
523 if (min_vertical_blank_time > vertical_blank_time)
524 min_vertical_blank_time = vertical_blank_time;
527 return min_vertical_blank_time;
530 static int determine_sclk_from_bounding_box(
537 * Some asics do not give us sclk levels, so we just report the actual
540 if (dc->sclk_lvls.num_levels == 0)
541 return required_sclk;
543 for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
544 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
545 return dc->sclk_lvls.clocks_in_khz[i];
548 * even maximum level could not satisfy requirement, this
549 * is unexpected at this stage, should have been caught at
553 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
556 static void dce_pplib_apply_display_requirements(
558 struct dc_state *context)
560 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
562 pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
564 dce110_fill_display_configs(context, pp_display_cfg);
566 if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
567 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
570 static void dce11_pplib_apply_display_requirements(
572 struct dc_state *context)
574 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
576 pp_display_cfg->all_displays_in_sync =
577 context->bw.dce.all_displays_in_sync;
578 pp_display_cfg->nb_pstate_switch_disable =
579 context->bw.dce.nbp_state_change_enable == false;
580 pp_display_cfg->cpu_cc6_disable =
581 context->bw.dce.cpuc_state_change_enable == false;
582 pp_display_cfg->cpu_pstate_disable =
583 context->bw.dce.cpup_state_change_enable == false;
584 pp_display_cfg->cpu_pstate_separation_time =
585 context->bw.dce.blackout_recovery_time_us;
587 pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
588 / MEMORY_TYPE_MULTIPLIER_CZ;
590 pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
592 context->bw.dce.sclk_khz);
594 pp_display_cfg->min_dcfclock_khz = pp_display_cfg->min_engine_clock_khz;
596 pp_display_cfg->min_engine_clock_deep_sleep_khz
597 = context->bw.dce.sclk_deep_sleep_khz;
599 pp_display_cfg->avail_mclk_switch_time_us =
600 dce110_get_min_vblank_time_us(context);
602 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
604 pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz;
606 dce110_fill_display_configs(context, pp_display_cfg);
608 /* TODO: is this still applicable?*/
609 if (pp_display_cfg->display_count == 1) {
610 const struct dc_crtc_timing *timing =
611 &context->streams[0]->timing;
613 pp_display_cfg->crtc_index =
614 pp_display_cfg->disp_configs[0].pipe_idx;
615 pp_display_cfg->line_time_in_us = timing->h_total * 1000 / timing->pix_clk_khz;
618 if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
619 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
622 static void dce_update_clocks(struct clk_mgr *clk_mgr,
623 struct dc_state *context,
626 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
627 struct dm_pp_power_level_change_request level_change_req;
628 int unpatched_disp_clk = context->bw.dce.dispclk_khz;
630 /*TODO: W/A for dal3 linux, investigate why this works */
631 if (!clk_mgr_dce->dfs_bypass_active)
632 context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100;
634 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
635 /* get max clock state from PPLIB */
636 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
637 || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
638 if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
639 clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
642 if (should_set_clock(safe_to_lower, context->bw.dce.dispclk_khz, clk_mgr->clks.dispclk_khz)) {
643 context->bw.dce.dispclk_khz = dce_set_clock(clk_mgr, context->bw.dce.dispclk_khz);
644 clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz;
646 dce_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
648 context->bw.dce.dispclk_khz = unpatched_disp_clk;
651 static void dce11_update_clocks(struct clk_mgr *clk_mgr,
652 struct dc_state *context,
655 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
656 struct dm_pp_power_level_change_request level_change_req;
658 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
659 /* get max clock state from PPLIB */
660 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
661 || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
662 if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
663 clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
666 if (should_set_clock(safe_to_lower, context->bw.dce.dispclk_khz, clk_mgr->clks.dispclk_khz)) {
667 context->bw.dce.dispclk_khz = dce_set_clock(clk_mgr, context->bw.dce.dispclk_khz);
668 clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz;
670 dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
673 static void dce112_update_clocks(struct clk_mgr *clk_mgr,
674 struct dc_state *context,
677 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
678 struct dm_pp_power_level_change_request level_change_req;
679 int unpatched_disp_clk = context->bw.dce.dispclk_khz;
681 /*TODO: W/A for dal3 linux, investigate why this works */
682 if (!clk_mgr_dce->dfs_bypass_active)
683 context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100;
685 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
686 /* get max clock state from PPLIB */
687 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
688 || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
689 if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
690 clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
693 if (should_set_clock(safe_to_lower, context->bw.dce.dispclk_khz, clk_mgr->clks.dispclk_khz)) {
694 context->bw.dce.dispclk_khz = dce112_set_clock(clk_mgr, context->bw.dce.dispclk_khz);
695 clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz;
697 dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
699 context->bw.dce.dispclk_khz = unpatched_disp_clk;
702 static void dce12_update_clocks(struct clk_mgr *clk_mgr,
703 struct dc_state *context,
706 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
707 struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
708 int max_pix_clk = get_max_pixel_clock_for_all_paths(context);
709 int unpatched_disp_clk = context->bw.dce.dispclk_khz;
711 /*TODO: W/A for dal3 linux, investigate why this works */
712 if (!clk_mgr_dce->dfs_bypass_active)
713 context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100;
715 if (should_set_clock(safe_to_lower, context->bw.dce.dispclk_khz, clk_mgr->clks.dispclk_khz)) {
716 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
717 clock_voltage_req.clocks_in_khz = context->bw.dce.dispclk_khz;
718 context->bw.dce.dispclk_khz = dce112_set_clock(clk_mgr, context->bw.dce.dispclk_khz);
719 clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz;
721 dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req);
724 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr->clks.phyclk_khz)) {
725 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK;
726 clock_voltage_req.clocks_in_khz = max_pix_clk;
727 clk_mgr->clks.phyclk_khz = max_pix_clk;
729 dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req);
731 dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
733 context->bw.dce.dispclk_khz = unpatched_disp_clk;
736 static const struct clk_mgr_funcs dce120_funcs = {
737 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
738 .update_clocks = dce12_update_clocks
741 static const struct clk_mgr_funcs dce112_funcs = {
742 .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
743 .update_clocks = dce112_update_clocks
746 static const struct clk_mgr_funcs dce110_funcs = {
747 .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
748 .update_clocks = dce11_update_clocks,
751 static const struct clk_mgr_funcs dce_funcs = {
752 .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
753 .update_clocks = dce_update_clocks
756 static void dce_clk_mgr_construct(
757 struct dce_clk_mgr *clk_mgr_dce,
758 struct dc_context *ctx,
759 const struct clk_mgr_registers *regs,
760 const struct clk_mgr_shift *clk_shift,
761 const struct clk_mgr_mask *clk_mask)
763 struct clk_mgr *base = &clk_mgr_dce->base;
764 struct dm_pp_static_clock_info static_clk_info = {0};
767 base->funcs = &dce_funcs;
769 clk_mgr_dce->regs = regs;
770 clk_mgr_dce->clk_mgr_shift = clk_shift;
771 clk_mgr_dce->clk_mgr_mask = clk_mask;
773 clk_mgr_dce->dfs_bypass_disp_clk = 0;
775 clk_mgr_dce->dprefclk_ss_percentage = 0;
776 clk_mgr_dce->dprefclk_ss_divider = 1000;
777 clk_mgr_dce->ss_on_dprefclk = false;
780 if (dm_pp_get_static_clocks(ctx, &static_clk_info))
781 clk_mgr_dce->max_clks_state = static_clk_info.max_clocks_state;
783 clk_mgr_dce->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
784 clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
786 dce_clock_read_integrated_info(clk_mgr_dce);
787 dce_clock_read_ss_info(clk_mgr_dce);
790 struct clk_mgr *dce_clk_mgr_create(
791 struct dc_context *ctx,
792 const struct clk_mgr_registers *regs,
793 const struct clk_mgr_shift *clk_shift,
794 const struct clk_mgr_mask *clk_mask)
796 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
798 if (clk_mgr_dce == NULL) {
803 memcpy(clk_mgr_dce->max_clks_by_state,
804 dce80_max_clks_by_state,
805 sizeof(dce80_max_clks_by_state));
807 dce_clk_mgr_construct(
808 clk_mgr_dce, ctx, regs, clk_shift, clk_mask);
810 return &clk_mgr_dce->base;
813 struct clk_mgr *dce110_clk_mgr_create(
814 struct dc_context *ctx,
815 const struct clk_mgr_registers *regs,
816 const struct clk_mgr_shift *clk_shift,
817 const struct clk_mgr_mask *clk_mask)
819 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
821 if (clk_mgr_dce == NULL) {
826 memcpy(clk_mgr_dce->max_clks_by_state,
827 dce110_max_clks_by_state,
828 sizeof(dce110_max_clks_by_state));
830 dce_clk_mgr_construct(
831 clk_mgr_dce, ctx, regs, clk_shift, clk_mask);
833 clk_mgr_dce->base.funcs = &dce110_funcs;
835 return &clk_mgr_dce->base;
838 struct clk_mgr *dce112_clk_mgr_create(
839 struct dc_context *ctx,
840 const struct clk_mgr_registers *regs,
841 const struct clk_mgr_shift *clk_shift,
842 const struct clk_mgr_mask *clk_mask)
844 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
846 if (clk_mgr_dce == NULL) {
851 memcpy(clk_mgr_dce->max_clks_by_state,
852 dce112_max_clks_by_state,
853 sizeof(dce112_max_clks_by_state));
855 dce_clk_mgr_construct(
856 clk_mgr_dce, ctx, regs, clk_shift, clk_mask);
858 clk_mgr_dce->base.funcs = &dce112_funcs;
860 return &clk_mgr_dce->base;
863 struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx)
865 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
867 if (clk_mgr_dce == NULL) {
872 memcpy(clk_mgr_dce->max_clks_by_state,
873 dce120_max_clks_by_state,
874 sizeof(dce120_max_clks_by_state));
876 dce_clk_mgr_construct(
877 clk_mgr_dce, ctx, NULL, NULL, NULL);
879 clk_mgr_dce->dprefclk_khz = 600000;
880 clk_mgr_dce->base.funcs = &dce120_funcs;
882 return &clk_mgr_dce->base;
885 void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr)
887 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(*clk_mgr);