drivers/gpu/drm/amd/display/dc/dce/dce_abm.h

   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #ifndef _DCE_ABM_H_
  28 #define _DCE_ABM_H_
  29
  30 #include "abm.h"
  31
  32 #define ABM_COMMON_REG_LIST_DCE_BASE() \
  33         SR(MASTER_COMM_CNTL_REG), \
  34         SR(MASTER_COMM_CMD_REG), \
  35         SR(MASTER_COMM_DATA_REG1)
  36
  37 #define ABM_DCE110_COMMON_REG_LIST() \
  38         ABM_COMMON_REG_LIST_DCE_BASE(), \
  39         SR(DC_ABM1_HG_SAMPLE_RATE), \
  40         SR(DC_ABM1_LS_SAMPLE_RATE), \
  41         SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
  42         SR(DC_ABM1_HG_MISC_CTRL), \
  43         SR(DC_ABM1_IPCSC_COEFF_SEL), \
  44         SR(BL1_PWM_CURRENT_ABM_LEVEL), \
  45         SR(BL1_PWM_TARGET_ABM_LEVEL), \
  46         SR(BL1_PWM_USER_LEVEL), \
  47         SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
  48         SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
  49         SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
  50         SR(DC_ABM1_ACE_THRES_12), \
  51         SR(BIOS_SCRATCH_2)
  52
  53 #define ABM_DCN10_REG_LIST(id)\
  54         ABM_COMMON_REG_LIST_DCE_BASE(), \
  55         SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
  56         SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
  57         SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
  58         SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
  59         SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
  60         SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
  61         SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
  62         SRI(BL1_PWM_USER_LEVEL, ABM, id), \
  63         SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
  64         SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
  65         SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
  66         SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
  67         NBIO_SR(BIOS_SCRATCH_2)
  68
  69 #define ABM_DCN20_REG_LIST() \
  70         ABM_COMMON_REG_LIST_DCE_BASE(), \
  71         SR(DC_ABM1_HG_SAMPLE_RATE), \
  72         SR(DC_ABM1_LS_SAMPLE_RATE), \
  73         SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
  74         SR(DC_ABM1_HG_MISC_CTRL), \
  75         SR(DC_ABM1_IPCSC_COEFF_SEL), \
  76         SR(BL1_PWM_CURRENT_ABM_LEVEL), \
  77         SR(BL1_PWM_TARGET_ABM_LEVEL), \
  78         SR(BL1_PWM_USER_LEVEL), \
  79         SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
  80         SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
  81         SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
  82         SR(DC_ABM1_ACE_THRES_12), \
  83         NBIO_SR(BIOS_SCRATCH_2)
  84
  85 #if defined(CONFIG_DRM_AMD_DC_DCN3_01)
  86 #define ABM_DCN301_REG_LIST(id)\
  87         ABM_COMMON_REG_LIST_DCE_BASE(), \
  88         SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
  89         SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
  90         SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
  91         SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
  92         SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
  93         SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
  94         SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
  95         SRI(BL1_PWM_USER_LEVEL, ABM, id), \
  96         SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
  97         SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
  98         NBIO_SR(BIOS_SCRATCH_2)
  99 #endif
 100
 101 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 102 #define ABM_DCN30_REG_LIST(id)\
 103         ABM_COMMON_REG_LIST_DCE_BASE(), \
 104         SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
 105         SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
 106         SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
 107         SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
 108         SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
 109         SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
 110         SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
 111         SRI(BL1_PWM_USER_LEVEL, ABM, id), \
 112         SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
 113         SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
 114         SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
 115         SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
 116         NBIO_SR(BIOS_SCRATCH_2)
 117 #endif
 118
 119 #define ABM_SF(reg_name, field_name, post_fix)\
 120         .field_name = reg_name ## __ ## field_name ## post_fix
 121
 122 #define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
 123         ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
 124         ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
 125         ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
 126         ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
 127
 128 #define ABM_MASK_SH_LIST_DCE110(mask_sh) \
 129         ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
 130         ABM_SF(DC_ABM1_HG_MISC_CTRL, \
 131                         ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
 132         ABM_SF(DC_ABM1_HG_MISC_CTRL, \
 133                         ABM1_HG_VMAX_SEL, mask_sh), \
 134         ABM_SF(DC_ABM1_HG_MISC_CTRL, \
 135                         ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
 136         ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
 137                         ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
 138         ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
 139                         ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
 140         ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
 141                         ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
 142         ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \
 143                         BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
 144         ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \
 145                         BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
 146         ABM_SF(BL1_PWM_USER_LEVEL, \
 147                         BL1_PWM_USER_LEVEL, mask_sh), \
 148         ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
 149                         ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
 150         ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
 151                         ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
 152         ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
 153                         ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
 154         ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
 155                         ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
 156         ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
 157                         ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
 158
 159 #define ABM_MASK_SH_LIST_DCN10(mask_sh) \
 160         ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
 161         ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
 162                         ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
 163         ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
 164                         ABM1_HG_VMAX_SEL, mask_sh), \
 165         ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
 166                         ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
 167         ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
 168                         ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
 169         ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
 170                         ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
 171         ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
 172                         ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
 173         ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
 174                         BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
 175         ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
 176                         BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
 177         ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
 178                         BL1_PWM_USER_LEVEL, mask_sh), \
 179         ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
 180                         ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
 181         ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
 182                         ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
 183         ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
 184                         ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
 185         ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
 186                         ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
 187         ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
 188                         ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
 189
 190 #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
 191
 192 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 193 #define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
 194 #endif
 195
 196 #define ABM_REG_FIELD_LIST(type) \
 197         type ABM1_HG_NUM_OF_BINS_SEL; \
 198         type ABM1_HG_VMAX_SEL; \
 199         type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \
 200         type ABM1_IPCSC_COEFF_SEL_R; \
 201         type ABM1_IPCSC_COEFF_SEL_G; \
 202         type ABM1_IPCSC_COEFF_SEL_B; \
 203         type BL1_PWM_CURRENT_ABM_LEVEL; \
 204         type BL1_PWM_TARGET_ABM_LEVEL; \
 205         type BL1_PWM_USER_LEVEL; \
 206         type ABM1_LS_MIN_PIXEL_VALUE_THRES; \
 207         type ABM1_LS_MAX_PIXEL_VALUE_THRES; \
 208         type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
 209         type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
 210         type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
 211         type MASTER_COMM_INTERRUPT; \
 212         type MASTER_COMM_CMD_REG_BYTE0; \
 213         type MASTER_COMM_CMD_REG_BYTE1; \
 214         type MASTER_COMM_CMD_REG_BYTE2
 215
 216 struct dce_abm_shift {
 217         ABM_REG_FIELD_LIST(uint8_t);
 218 };
 219
 220 struct dce_abm_mask {
 221         ABM_REG_FIELD_LIST(uint32_t);
 222 };
 223
 224 struct dce_abm_registers {
 225         uint32_t DC_ABM1_HG_SAMPLE_RATE;
 226         uint32_t DC_ABM1_LS_SAMPLE_RATE;
 227         uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
 228         uint32_t DC_ABM1_HG_MISC_CTRL;
 229         uint32_t DC_ABM1_IPCSC_COEFF_SEL;
 230         uint32_t BL1_PWM_CURRENT_ABM_LEVEL;
 231         uint32_t BL1_PWM_TARGET_ABM_LEVEL;
 232         uint32_t BL1_PWM_USER_LEVEL;
 233         uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
 234         uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
 235         uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0;
 236         uint32_t DC_ABM1_ACE_THRES_12;
 237         uint32_t MASTER_COMM_CNTL_REG;
 238         uint32_t MASTER_COMM_CMD_REG;
 239         uint32_t MASTER_COMM_DATA_REG1;
 240         uint32_t BIOS_SCRATCH_2;
 241 };
 242
 243 struct dce_abm {
 244         struct abm base;
 245         const struct dce_abm_registers *regs;
 246         const struct dce_abm_shift *abm_shift;
 247         const struct dce_abm_mask *abm_mask;
 248 };
 249
 250 struct abm *dce_abm_create(
 251         struct dc_context *ctx,
 252         const struct dce_abm_registers *regs,
 253         const struct dce_abm_shift *abm_shift,
 254         const struct dce_abm_mask *abm_mask);
 255
 256 void dce_abm_destroy(struct abm **abm);
 257
 258 #endif /* _DCE_ABM_H_ */