2 * Copyright 2012-16 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
32 #define ABM_COMMON_REG_LIST_DCE_BASE() \
33 SR(MASTER_COMM_CNTL_REG), \
34 SR(MASTER_COMM_CMD_REG), \
35 SR(MASTER_COMM_DATA_REG1)
37 #define ABM_DCE110_COMMON_REG_LIST() \
38 ABM_COMMON_REG_LIST_DCE_BASE(), \
39 SR(DC_ABM1_HG_SAMPLE_RATE), \
40 SR(DC_ABM1_LS_SAMPLE_RATE), \
41 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
42 SR(DC_ABM1_HG_MISC_CTRL), \
43 SR(DC_ABM1_IPCSC_COEFF_SEL), \
44 SR(BL1_PWM_CURRENT_ABM_LEVEL), \
45 SR(BL1_PWM_TARGET_ABM_LEVEL), \
46 SR(BL1_PWM_USER_LEVEL), \
47 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
48 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
49 SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
50 SR(DC_ABM1_ACE_THRES_12), \
53 #define ABM_DCN10_REG_LIST(id)\
54 ABM_COMMON_REG_LIST_DCE_BASE(), \
55 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
56 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
57 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
58 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
59 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
60 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
61 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
62 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
63 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
64 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
65 SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
66 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
67 NBIO_SR(BIOS_SCRATCH_2)
69 #define ABM_DCN20_REG_LIST() \
70 ABM_COMMON_REG_LIST_DCE_BASE(), \
71 SR(DC_ABM1_HG_SAMPLE_RATE), \
72 SR(DC_ABM1_LS_SAMPLE_RATE), \
73 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
74 SR(DC_ABM1_HG_MISC_CTRL), \
75 SR(DC_ABM1_IPCSC_COEFF_SEL), \
76 SR(BL1_PWM_CURRENT_ABM_LEVEL), \
77 SR(BL1_PWM_TARGET_ABM_LEVEL), \
78 SR(BL1_PWM_USER_LEVEL), \
79 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
80 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
81 SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
82 SR(DC_ABM1_ACE_THRES_12), \
83 NBIO_SR(BIOS_SCRATCH_2)
85 #define ABM_DCN301_REG_LIST(id)\
86 ABM_COMMON_REG_LIST_DCE_BASE(), \
87 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
88 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
89 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
90 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
91 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
92 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
93 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
94 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
95 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
96 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
97 NBIO_SR(BIOS_SCRATCH_2)
99 #define ABM_DCN302_REG_LIST(id)\
100 ABM_COMMON_REG_LIST_DCE_BASE(), \
101 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
102 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
103 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
104 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
105 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
106 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
107 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
108 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
109 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
110 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
111 SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
112 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
113 NBIO_SR(BIOS_SCRATCH_2)
115 #define ABM_DCN30_REG_LIST(id)\
116 ABM_COMMON_REG_LIST_DCE_BASE(), \
117 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
118 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
119 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
120 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
121 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
122 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
123 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
124 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
125 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
126 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
127 SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
128 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
129 NBIO_SR(BIOS_SCRATCH_2)
131 #define ABM_SF(reg_name, field_name, post_fix)\
132 .field_name = reg_name ## __ ## field_name ## post_fix
134 #define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
135 ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
136 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
137 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
138 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
140 #define ABM_MASK_SH_LIST_DCE110(mask_sh) \
141 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
142 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
143 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
144 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
145 ABM1_HG_VMAX_SEL, mask_sh), \
146 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
147 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
148 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
149 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
150 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
151 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
152 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
153 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
154 ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \
155 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
156 ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \
157 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
158 ABM_SF(BL1_PWM_USER_LEVEL, \
159 BL1_PWM_USER_LEVEL, mask_sh), \
160 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
161 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
162 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
163 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
164 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
165 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
166 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
167 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
168 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
169 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
171 #define ABM_MASK_SH_LIST_DCN10(mask_sh) \
172 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
173 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
174 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
175 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
176 ABM1_HG_VMAX_SEL, mask_sh), \
177 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
178 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
179 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
180 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
181 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
182 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
183 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
184 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
185 ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
186 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
187 ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
188 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
189 ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
190 BL1_PWM_USER_LEVEL, mask_sh), \
191 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
192 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
193 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
194 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
195 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
196 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
197 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
198 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
199 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
200 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
202 #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
204 #define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
206 #define ABM_REG_FIELD_LIST(type) \
207 type ABM1_HG_NUM_OF_BINS_SEL; \
208 type ABM1_HG_VMAX_SEL; \
209 type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \
210 type ABM1_IPCSC_COEFF_SEL_R; \
211 type ABM1_IPCSC_COEFF_SEL_G; \
212 type ABM1_IPCSC_COEFF_SEL_B; \
213 type BL1_PWM_CURRENT_ABM_LEVEL; \
214 type BL1_PWM_TARGET_ABM_LEVEL; \
215 type BL1_PWM_USER_LEVEL; \
216 type ABM1_LS_MIN_PIXEL_VALUE_THRES; \
217 type ABM1_LS_MAX_PIXEL_VALUE_THRES; \
218 type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
219 type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
220 type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
221 type MASTER_COMM_INTERRUPT; \
222 type MASTER_COMM_CMD_REG_BYTE0; \
223 type MASTER_COMM_CMD_REG_BYTE1; \
224 type MASTER_COMM_CMD_REG_BYTE2
226 struct dce_abm_shift {
227 ABM_REG_FIELD_LIST(uint8_t);
230 struct dce_abm_mask {
231 ABM_REG_FIELD_LIST(uint32_t);
234 struct dce_abm_registers {
235 uint32_t DC_ABM1_HG_SAMPLE_RATE;
236 uint32_t DC_ABM1_LS_SAMPLE_RATE;
237 uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
238 uint32_t DC_ABM1_HG_MISC_CTRL;
239 uint32_t DC_ABM1_IPCSC_COEFF_SEL;
240 uint32_t BL1_PWM_CURRENT_ABM_LEVEL;
241 uint32_t BL1_PWM_TARGET_ABM_LEVEL;
242 uint32_t BL1_PWM_USER_LEVEL;
243 uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
244 uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
245 uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0;
246 uint32_t DC_ABM1_ACE_THRES_12;
247 uint32_t MASTER_COMM_CNTL_REG;
248 uint32_t MASTER_COMM_CMD_REG;
249 uint32_t MASTER_COMM_DATA_REG1;
250 uint32_t BIOS_SCRATCH_2;
255 const struct dce_abm_registers *regs;
256 const struct dce_abm_shift *abm_shift;
257 const struct dce_abm_mask *abm_mask;
260 struct abm *dce_abm_create(
261 struct dc_context *ctx,
262 const struct dce_abm_registers *regs,
263 const struct dce_abm_shift *abm_shift,
264 const struct dce_abm_mask *abm_mask);
266 void dce_abm_destroy(struct abm **abm);
268 #endif /* _DCE_ABM_H_ */