2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
29 #include "fixed31_32.h"
30 #include "irq_types.h"
31 #include "dc_dp_types.h"
32 #include "dc_hw_types.h"
33 #include "dal_types.h"
34 #include "grph_object_defs.h"
36 /* forward declarations */
37 struct dc_plane_state;
38 struct dc_stream_state;
43 /********************************
44 * Environment definitions
45 ********************************/
46 enum dce_environment {
47 DCE_ENV_PRODUCTION_DRV = 0,
48 /* Emulation on FPGA, in "Maximus" System.
49 * This environment enforces that *only* DC registers accessed.
50 * (access to non-DC registers will hang FPGA) */
52 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
53 * requirements of Diagnostics team. */
57 /* Note: use these macro definitions instead of direct comparison! */
58 #define IS_FPGA_MAXIMUS_DC(dce_environment) \
59 (dce_environment == DCE_ENV_FPGA_MAXIMUS)
61 #define IS_DIAG_DC(dce_environment) \
62 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
67 uint32_t pci_revision_id;
68 uint32_t hw_internal_rev;
71 uint32_t feature_flags;
72 uint32_t fake_paths_num;
73 void *atombios_base_address;
76 struct dc_perf_trace {
77 unsigned long read_count;
78 unsigned long write_count;
79 unsigned long last_entry_read;
80 unsigned long last_entry_write;
86 void *driver_context; /* e.g. amdgpu_device */
87 struct dc_perf_trace *perf_trace;
90 enum dce_environment dce_environment;
91 struct hw_asic_id asic_id;
93 /* todo: below should probably move to dc. to facilitate removal
94 * of AS we will store these here
96 enum dce_version dce_version;
97 struct dc_bios *dc_bios;
99 struct gpio_service *gpio_service;
100 uint32_t dc_sink_id_count;
101 uint32_t dc_stream_id_count;
102 uint64_t fbc_gpu_addr;
106 #define DC_MAX_EDID_BUFFER_SIZE 1024
107 #define EDID_BLOCK_SIZE 128
108 #define MAX_SURFACE_NUM 4
109 #define NUM_PIXEL_FORMATS 10
111 #include "dc_ddc_types.h"
120 enum view_3d_format {
121 VIEW_3D_FORMAT_NONE = 0,
122 VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
123 VIEW_3D_FORMAT_SIDE_BY_SIDE,
124 VIEW_3D_FORMAT_TOP_AND_BOTTOM,
125 VIEW_3D_FORMAT_COUNT,
126 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
129 enum plane_stereo_format {
130 PLANE_STEREO_FORMAT_NONE = 0,
131 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
132 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
133 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
134 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
135 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
136 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
139 /* TODO: Find way to calculate number of bits
140 * Please increase if pixel_format enum increases
141 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
144 enum dc_edid_connector_type {
145 DC_EDID_CONNECTOR_UNKNOWN = 0,
146 DC_EDID_CONNECTOR_ANALOG = 1,
147 DC_EDID_CONNECTOR_DIGITAL = 10,
148 DC_EDID_CONNECTOR_DVI = 11,
149 DC_EDID_CONNECTOR_HDMIA = 12,
150 DC_EDID_CONNECTOR_MDDI = 14,
151 DC_EDID_CONNECTOR_DISPLAYPORT = 15
154 enum dc_edid_status {
162 /* audio capability from EDID*/
163 struct dc_cea_audio_mode {
164 uint8_t format_code; /* ucData[0] [6:3]*/
165 uint8_t channel_count; /* ucData[0] [2:0]*/
166 uint8_t sample_rate; /* ucData[1]*/
168 uint8_t sample_size; /* for LPCM*/
169 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
170 uint8_t max_bit_rate;
171 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
177 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
180 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
181 * is used. In this case we assume speaker location are: front left, front
182 * right and front center. */
183 #define DEFAULT_SPEAKER_LOCATION 5
185 #define DC_MAX_AUDIO_DESC_COUNT 16
187 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
189 union display_content_support {
192 unsigned int valid_content_type :1;
193 unsigned int game_content :1;
194 unsigned int cinema_content :1;
195 unsigned int photo_content :1;
196 unsigned int graphics_content :1;
197 unsigned int reserved :27;
201 struct dc_panel_patch {
202 unsigned int dppowerup_delay;
203 unsigned int extra_t12_ms;
204 unsigned int extra_delay_backlight_off;
207 struct dc_edid_caps {
208 /* sink identification */
209 uint16_t manufacturer_id;
211 uint32_t serial_number;
212 uint8_t manufacture_week;
213 uint8_t manufacture_year;
214 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
217 uint8_t speaker_flags;
218 uint32_t audio_mode_count;
219 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
220 uint32_t audio_latency;
221 uint32_t video_latency;
223 union display_content_support content_support;
229 bool lte_340mcsc_scramble;
234 struct dc_panel_patch panel_patch;
242 struct dc_mode_flags {
243 /* note: part of refresh rate flag*/
244 uint32_t INTERLACE :1;
245 /* native display timing*/
247 /* preferred is the recommended mode, one per display */
248 uint32_t PREFERRED :1;
249 /* true if this mode should use reduced blanking timings
250 *_not_ related to the Reduced Blanking adjustment*/
251 uint32_t REDUCED_BLANKING :1;
252 /* note: part of refreshrate flag*/
253 uint32_t VIDEO_OPTIMIZED_RATE :1;
254 /* should be reported to upper layers as mode_flags*/
255 uint32_t PACKED_PIXEL_FORMAT :1;
257 uint32_t PREFERRED_VIEW :1;
258 /* this timing should be used only in tiled mode*/
259 uint32_t TILED_MODE :1;
260 uint32_t DSE_MODE :1;
261 /* Refresh rate divider when Miracast sink is using a
262 different rate than the output display device
263 Must be zero for wired displays and non-zero for
265 uint32_t MIRACAST_REFRESH_DIVIDER;
269 enum dc_timing_source {
270 TIMING_SOURCE_UNDEFINED,
272 /* explicitly specifed by user, most important*/
273 TIMING_SOURCE_USER_FORCED,
274 TIMING_SOURCE_USER_OVERRIDE,
275 TIMING_SOURCE_CUSTOM,
276 TIMING_SOURCE_EXPLICIT,
278 /* explicitly specified by the display device, more important*/
279 TIMING_SOURCE_EDID_CEA_SVD_3D,
280 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
281 TIMING_SOURCE_EDID_CEA_SVD_420,
282 TIMING_SOURCE_EDID_DETAILED,
283 TIMING_SOURCE_EDID_ESTABLISHED,
284 TIMING_SOURCE_EDID_STANDARD,
285 TIMING_SOURCE_EDID_CEA_SVD,
286 TIMING_SOURCE_EDID_CVT_3BYTE,
287 TIMING_SOURCE_EDID_4BYTE,
291 TIMING_SOURCE_HDMI_VIC,
293 /* implicitly specified by display device, still safe but less important*/
294 TIMING_SOURCE_DEFAULT,
296 /* only used for custom base modes */
297 TIMING_SOURCE_CUSTOM_BASE,
299 /* these timing might not work, least important*/
300 TIMING_SOURCE_RANGELIMIT,
301 TIMING_SOURCE_OS_FORCED,
302 TIMING_SOURCE_IMPLICIT,
304 /* only used by default mode list*/
305 TIMING_SOURCE_BASICMODE,
311 struct stereo_3d_features {
316 bool singleFrameSWPacked;
319 enum dc_timing_support_method {
320 TIMING_SUPPORT_METHOD_UNDEFINED,
321 TIMING_SUPPORT_METHOD_EXPLICIT,
322 TIMING_SUPPORT_METHOD_IMPLICIT,
323 TIMING_SUPPORT_METHOD_NATIVE
326 struct dc_mode_info {
327 uint32_t pixel_width;
328 uint32_t pixel_height;
330 /* Vertical refresh rate for progressive modes.
331 * Field rate for interlaced modes.*/
333 enum dc_timing_standard timing_standard;
334 enum dc_timing_source timing_source;
335 struct dc_mode_flags flags;
338 enum dc_power_state {
339 DC_POWER_STATE_ON = 1,
340 DC_POWER_STATE_STANDBY,
341 DC_POWER_STATE_SUSPEND,
346 enum dc_video_power_state {
347 DC_VIDEO_POWER_UNSPECIFIED = 0,
348 DC_VIDEO_POWER_ON = 1,
349 DC_VIDEO_POWER_STANDBY,
350 DC_VIDEO_POWER_SUSPEND,
352 DC_VIDEO_POWER_HIBERNATE,
353 DC_VIDEO_POWER_SHUTDOWN,
354 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
355 DC_VIDEO_POWER_AFTER_RESET,
356 DC_VIDEO_POWER_MAXIMUM
359 enum dc_acpi_cm_power_state {
360 DC_ACPI_CM_POWER_STATE_D0 = 1,
361 DC_ACPI_CM_POWER_STATE_D1 = 2,
362 DC_ACPI_CM_POWER_STATE_D2 = 4,
363 DC_ACPI_CM_POWER_STATE_D3 = 8
366 enum dc_connection_type {
368 dc_connection_single,
369 dc_connection_mst_branch,
370 dc_connection_active_dongle
373 struct dc_csc_adjustments {
374 struct fixed31_32 contrast;
375 struct fixed31_32 saturation;
376 struct fixed31_32 brightness;
377 struct fixed31_32 hue;
380 enum dpcd_downstream_port_max_bpc {
381 DOWN_STREAM_MAX_8BPC = 0,
382 DOWN_STREAM_MAX_10BPC,
383 DOWN_STREAM_MAX_12BPC,
384 DOWN_STREAM_MAX_16BPC
386 struct dc_dongle_caps {
387 /* dongle type (DP converter, CV smart dongle) */
388 enum display_dongle_type dongle_type;
389 bool extendedCapValid;
390 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
391 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
392 bool is_dp_hdmi_s3d_converter;
393 bool is_dp_hdmi_ycbcr422_pass_through;
394 bool is_dp_hdmi_ycbcr420_pass_through;
395 bool is_dp_hdmi_ycbcr422_converter;
396 bool is_dp_hdmi_ycbcr420_converter;
397 uint32_t dp_hdmi_max_bpc;
398 uint32_t dp_hdmi_max_pixel_clk_in_khz;
401 enum scaling_transformation {
402 SCALING_TRANSFORMATION_UNINITIALIZED,
403 SCALING_TRANSFORMATION_IDENTITY = 0x0001,
404 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
405 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
406 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
407 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
408 SCALING_TRANSFORMATION_INVALID = 0x80000000,
410 /* Flag the first and last */
411 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
412 SCALING_TRANSFORMATION_END =
413 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
416 enum display_content_type {
417 DISPLAY_CONTENT_TYPE_NO_DATA = 0,
418 DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
419 DISPLAY_CONTENT_TYPE_PHOTO = 2,
420 DISPLAY_CONTENT_TYPE_CINEMA = 4,
421 DISPLAY_CONTENT_TYPE_GAME = 8
426 union audio_sample_rates {
427 struct sample_rates {
433 uint8_t RATE_176_4:1;
440 struct audio_speaker_flags {
448 uint32_t SUPPORT_AI:1;
451 struct audio_speaker_info {
452 uint32_t ALLSPEAKERS:7;
453 uint32_t SUPPORT_AI:1;
457 struct audio_info_flags {
461 struct audio_speaker_flags speaker_flags;
462 struct audio_speaker_info info;
468 enum audio_format_code {
469 AUDIO_FORMAT_CODE_FIRST = 1,
470 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
472 AUDIO_FORMAT_CODE_AC3,
474 AUDIO_FORMAT_CODE_MPEG1,
476 AUDIO_FORMAT_CODE_MP3,
478 AUDIO_FORMAT_CODE_MPEG2,
479 AUDIO_FORMAT_CODE_AAC,
480 AUDIO_FORMAT_CODE_DTS,
481 AUDIO_FORMAT_CODE_ATRAC,
482 AUDIO_FORMAT_CODE_1BITAUDIO,
483 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
484 AUDIO_FORMAT_CODE_DTS_HD,
485 AUDIO_FORMAT_CODE_MAT_MLP,
486 AUDIO_FORMAT_CODE_DST,
487 AUDIO_FORMAT_CODE_WMAPRO,
488 AUDIO_FORMAT_CODE_LAST,
489 AUDIO_FORMAT_CODE_COUNT =
490 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
494 /* ucData[0] [6:3] */
495 enum audio_format_code format_code;
496 /* ucData[0] [2:0] */
497 uint8_t channel_count;
499 union audio_sample_rates sample_rates;
503 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
504 uint8_t max_bit_rate;
505 /* for Audio Formats 9-15 */
506 uint8_t vendor_specific;
511 struct audio_info_flags flags;
512 uint32_t video_latency;
513 uint32_t audio_latency;
514 uint32_t display_index;
515 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
516 uint32_t manufacture_id;
518 /* PortID used for ContainerID when defined */
521 /* this field must be last in this struct */
522 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
525 enum dc_infoframe_type {
526 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
527 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
528 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
529 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
532 struct dc_info_packet {
541 #define DC_PLANE_UPDATE_TIMES_MAX 10
543 struct dc_plane_flip_time {
544 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
546 unsigned int prev_update_time_in_us;
550 unsigned char psr_version;
551 unsigned int psr_rfb_setup_time;
552 bool psr_exit_link_training_required;
553 bool psr_frame_capture_indication_req;
554 unsigned int psr_sdp_transmit_line_num_deadline;
555 bool allow_smu_optimizations;
558 union dmcu_psr_level {
560 unsigned int SKIP_CRC:1;
561 unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
562 unsigned int SKIP_PHY_POWER_DOWN:1;
563 unsigned int SKIP_AUX_ACK_CHECK:1;
564 unsigned int SKIP_CRTC_DISABLE:1;
565 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
566 unsigned int SKIP_SMU_NOTIFICATION:1;
567 unsigned int SKIP_AUTO_STATE_ADVANCE:1;
568 unsigned int DISABLE_PSR_ENTRY_ABORT:1;
569 unsigned int SKIP_SINGLE_OTG_DISABLE:1;
570 unsigned int RESERVED:22;
575 enum physical_phy_id {
587 PHYLD_UNKNOWN = (-1L)
591 PHY_TYPE_UNKNOWN = 1,
592 PHY_TYPE_PCIE_PHY = 2,
598 enum channel_id channel;
600 enum transmitter transmitterId;
601 /* Engine Id is used for Dig Be source select */
602 enum engine_id engineId;
603 /* Controller Id used for Dig Fe source select */
604 enum controller_id controllerId;
606 enum phy_type phyType;
607 /* Physical PHY Id used by SMU interpretation */
608 enum physical_phy_id smuPhyId;
609 /* Vertical total pixels from crtc timing.
610 * This is used for static screen detection.
611 * ie. If we want to detect half a frame,
612 * we use this to determine the hyst lines.
614 unsigned int crtcTimingVerticalTotal;
615 /* PSR supported from panel capabilities and
616 * current display configuration
618 bool psrSupportedDisplayConfig;
619 /* Whether fast link training is supported by the panel */
620 bool psrExitLinkTrainingRequired;
621 /* If RFB setup time is greater than the total VBLANK time,
622 * it is not possible for the sink to capture the video frame
623 * in the same frame the SDP is sent. In this case,
624 * the frame capture indication bit should be set and an extra
625 * static frame should be transmitted to the sink.
627 bool psrFrameCaptureIndicationReq;
628 /* Set the last possible line SDP may be transmitted without violating
629 * the RFB setup time or entering the active video frame.
631 unsigned int sdpTransmitLineNumDeadline;
632 /* The VSync rate in Hz used to calculate the
633 * step size for smooth brightness feature
635 unsigned int vsyncRateHz;
636 unsigned int skipPsrWaitForPllLock;
637 unsigned int numberOfControllers;
638 /* Unused, for future use. To indicate that first changed frame from
639 * state3 shouldn't result in psr_inactive, but rather to perform
640 * an automatic single frame rfb_update.
642 bool rfb_update_auto_en;
643 /* Number of frame before entering static screen */
644 unsigned int timehyst_frames;
645 /* Partial frames before entering static screen */
646 unsigned int hyst_lines;
647 /* # of repeated AUX transaction attempts to make before
648 * indicating failure to the driver
650 unsigned int aux_repeats;
651 /* Controls hw blocks to power down during PSR active state */
652 union dmcu_psr_level psr_level;
653 /* Controls additional delay after remote frame capture before
654 * continuing powerd own
656 unsigned int frame_delay;
657 bool allow_smu_optimizations;
660 struct colorspace_transform {
661 struct fixed31_32 matrix[12];
672 unsigned int memoryClock;
673 unsigned int displayClock;
674 unsigned int engineClock;
675 unsigned int maxSupportedDppClock;
676 unsigned int dppClock;
677 unsigned int socClock;
678 unsigned int dcfClockDeepSleep;
680 unsigned int phyClock;
683 #endif /* DC_TYPES_H_ */