2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
30 #include "fixed31_32.h"
31 #include "signal_types.h"
33 /******************************************************************************
34 * Data types for Virtual HW Layer of DAL3.
35 * (see DAL3 design documents for HW Layer definition)
37 * The intended uses are:
38 * 1. Generation pseudocode sequences for HW programming.
39 * 2. Implementation of real HW programming by HW Sequencer of DAL3.
41 * Note: do *not* add any types which are *not* used for HW programming - this
42 * will ensure separation of Logic layer from HW layer.
43 ******************************************************************************/
59 #define PHYSICAL_ADDRESS_LOC union large_integer
61 enum dc_plane_addr_type {
62 PLN_ADDR_TYPE_GRAPHICS = 0,
63 PLN_ADDR_TYPE_GRPH_STEREO,
64 PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
67 struct dc_plane_address {
68 enum dc_plane_addr_type type;
72 PHYSICAL_ADDRESS_LOC addr;
73 PHYSICAL_ADDRESS_LOC meta_addr;
74 union large_integer dcc_const_color;
79 PHYSICAL_ADDRESS_LOC left_addr;
80 PHYSICAL_ADDRESS_LOC left_meta_addr;
81 union large_integer left_dcc_const_color;
83 PHYSICAL_ADDRESS_LOC right_addr;
84 PHYSICAL_ADDRESS_LOC right_meta_addr;
85 union large_integer right_dcc_const_color;
91 PHYSICAL_ADDRESS_LOC luma_addr;
92 PHYSICAL_ADDRESS_LOC luma_meta_addr;
93 union large_integer luma_dcc_const_color;
95 PHYSICAL_ADDRESS_LOC chroma_addr;
96 PHYSICAL_ADDRESS_LOC chroma_meta_addr;
97 union large_integer chroma_dcc_const_color;
115 /* Grph or Video will be selected
116 * based on format above:
117 * Use Video structure if
118 * format >= DalPixelFormat_VideoBegin
119 * else use Grph structure
122 struct rect surface_size;
123 /* Graphic surface pitch in pixels.
124 * In LINEAR_GENERAL mode, pitch
125 * is 32 pixel aligned.
131 struct rect luma_size;
132 /* Graphic surface pitch in pixels.
133 * In LINEAR_GENERAL mode, pitch is
138 struct rect chroma_size;
139 /* Graphic surface pitch in pixels.
140 * In LINEAR_GENERAL mode, pitch is
147 struct dc_plane_dcc_param {
153 bool independent_64b_blks;
158 bool independent_64b_blks_l;
161 bool independent_64b_blks_c;
166 /*Displayable pixel format in fb*/
167 enum surface_pixel_format {
168 SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
169 /*TOBE REMOVED paletta 256 colors*/
170 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
171 SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
173 SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
175 SURFACE_PIXEL_FORMAT_GRPH_RGB565,
177 SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
179 SURFACE_PIXEL_FORMAT_GRPH_ABGR8888,
181 SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
183 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
184 /*TOBE REMOVED swaped, XR_BIAS has no differance
185 * for pixel layout than previous and we can
186 * delete this after discusion*/
187 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
189 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
191 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F,
193 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
194 /*grow graphics here if necessary */
195 SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888,
196 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
197 SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
198 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
199 SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
200 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
201 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
202 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
203 SURFACE_PIXEL_FORMAT_INVALID
205 /*grow 444 video here if necessary */
213 PIXEL_FORMAT_UNINITIALIZED,
216 PIXEL_FORMAT_ARGB8888,
217 PIXEL_FORMAT_ARGB2101010,
218 PIXEL_FORMAT_ARGB2101010_XRBIAS,
221 PIXEL_FORMAT_420BPP8,
222 PIXEL_FORMAT_420BPP10,
223 /*end of pixel format definition*/
224 PIXEL_FORMAT_INVALID,
226 PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
227 PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
228 PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8,
229 PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10,
233 enum tile_split_values {
234 DC_DISPLAY_MICRO_TILING = 0x0,
235 DC_THIN_MICRO_TILING = 0x1,
236 DC_DEPTH_MICRO_TILING = 0x2,
237 DC_ROTATED_MICRO_TILING = 0x3,
240 /* TODO: These values come from hardware spec. We need to readdress this
241 * if they ever change.
243 enum array_mode_values {
244 DC_ARRAY_LINEAR_GENERAL = 0,
245 DC_ARRAY_LINEAR_ALLIGNED,
246 DC_ARRAY_1D_TILED_THIN1,
247 DC_ARRAY_1D_TILED_THICK,
248 DC_ARRAY_2D_TILED_THIN1,
249 DC_ARRAY_PRT_TILED_THIN1,
250 DC_ARRAY_PRT_2D_TILED_THIN1,
251 DC_ARRAY_2D_TILED_THICK,
252 DC_ARRAY_2D_TILED_X_THICK,
253 DC_ARRAY_PRT_TILED_THICK,
254 DC_ARRAY_PRT_2D_TILED_THICK,
255 DC_ARRAY_PRT_3D_TILED_THIN1,
256 DC_ARRAY_3D_TILED_THIN1,
257 DC_ARRAY_3D_TILED_THICK,
258 DC_ARRAY_3D_TILED_X_THICK,
259 DC_ARRAY_PRT_3D_TILED_THICK,
262 enum tile_mode_values {
263 DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
264 DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
267 enum swizzle_mode_values {
293 DC_SW_UNKNOWN = DC_SW_MAX
296 union dc_tiling_info {
299 /* Specifies the number of memory banks for tiling
301 * Only applies to 2D and 3D tiling modes.
302 * POSSIBLE VALUES: 2,4,8,16
304 unsigned int num_banks;
305 /* Specifies the number of tiles in the x direction
306 * to be incorporated into the same bank.
307 * Only applies to 2D and 3D tiling modes.
308 * POSSIBLE VALUES: 1,2,4,8
310 unsigned int bank_width;
311 unsigned int bank_width_c;
312 /* Specifies the number of tiles in the y direction to
313 * be incorporated into the same bank.
314 * Only applies to 2D and 3D tiling modes.
315 * POSSIBLE VALUES: 1,2,4,8
317 unsigned int bank_height;
318 unsigned int bank_height_c;
319 /* Specifies the macro tile aspect ratio. Only applies
320 * to 2D and 3D tiling modes.
322 unsigned int tile_aspect;
323 unsigned int tile_aspect_c;
324 /* Specifies the number of bytes that will be stored
325 * contiguously for each tile.
326 * If the tile data requires more storage than this
327 * amount, it is split into multiple slices.
328 * This field must not be larger than
329 * GB_ADDR_CONFIG.DRAM_ROW_SIZE.
330 * Only applies to 2D and 3D tiling modes.
331 * For color render targets, TILE_SPLIT >= 256B.
333 enum tile_split_values tile_split;
334 enum tile_split_values tile_split_c;
335 /* Specifies the addressing within a tile.
336 * 0x0 - DISPLAY_MICRO_TILING
337 * 0x1 - THIN_MICRO_TILING
338 * 0x2 - DEPTH_MICRO_TILING
339 * 0x3 - ROTATED_MICRO_TILING
341 enum tile_mode_values tile_mode;
342 enum tile_mode_values tile_mode_c;
343 /* Specifies the number of pipes and how they are
344 * interleaved in the surface.
345 * Refer to memory addressing document for complete
346 * details and constraints.
348 unsigned int pipe_config;
349 /* Specifies the tiling mode of the surface.
350 * THIN tiles use an 8x8x1 tile size.
351 * THICK tiles use an 8x8x4 tile size.
352 * 2D tiling modes rotate banks for successive Z slices
353 * 3D tiling modes rotate pipes and banks for Z slices
354 * Refer to memory addressing document for complete
355 * details and constraints.
357 enum array_mode_values array_mode;
361 enum swizzle_mode_values swizzle;
362 unsigned int num_pipes;
363 unsigned int max_compressed_frags;
364 unsigned int pipe_interleave;
366 unsigned int num_banks;
367 unsigned int num_shader_engines;
368 unsigned int num_rb_per_se;
378 enum dc_rotation_angle {
379 ROTATION_ANGLE_0 = 0,
386 enum dc_scan_direction {
387 SCAN_DIRECTION_UNKNOWN = 0,
388 SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */
389 SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */
392 struct dc_cursor_position {
400 * This parameter indicates whether HW cursor should be enabled
406 struct dc_cursor_mi_param {
407 unsigned int pixel_clk_khz;
408 unsigned int ref_clk_khz;
409 struct rect viewport;
410 struct fixed31_32 h_scale_ratio;
411 struct fixed31_32 v_scale_ratio;
412 enum dc_rotation_angle rotation;
416 /* IPP related types */
419 GAMMA_RGB_256_ENTRIES = 256,
420 GAMMA_RGB_FLOAT_1024_ENTRIES = 1024,
421 GAMMA_CS_TFM_1D_ENTRIES = 4096,
422 GAMMA_CUSTOM_ENTRIES = 4096,
423 GAMMA_MAX_ENTRIES = 4096
428 GAMMA_RGB_FLOAT_1024 = 2,
433 struct dc_csc_transform {
435 bool enable_adjustment;
439 struct kref refcount;
440 enum dc_gamma_type type;
441 unsigned int num_entries;
443 struct dc_gamma_entries {
444 struct fixed31_32 red[GAMMA_MAX_ENTRIES];
445 struct fixed31_32 green[GAMMA_MAX_ENTRIES];
446 struct fixed31_32 blue[GAMMA_MAX_ENTRIES];
449 /* private to DC core */
450 struct dc_context *ctx;
455 /* Used by both ipp amd opp functions*/
456 /* TODO: to be consolidated with enum color_space */
459 * This enum is for programming CURSOR_MODE register field. What this register
460 * should be programmed to depends on OS requested cursor shape flags and what
461 * we stored in the cursor surface.
463 enum dc_cursor_color_format {
465 CURSOR_MODE_COLOR_1BIT_AND,
466 CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
467 CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
471 * This is all the parameters required by DAL in order to update the cursor
472 * attributes, including the new cursor image surface address, size, hotspot
473 * location, color format, etc.
476 union dc_cursor_attribute_flags {
478 uint32_t ENABLE_MAGNIFICATION:1;
479 uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
480 uint32_t HORIZONTAL_MIRROR:1;
481 uint32_t VERTICAL_MIRROR:1;
482 uint32_t INVERT_PIXEL_DATA:1;
483 uint32_t ZERO_EXPANSION:1;
484 uint32_t MIN_MAX_INVERT:1;
485 uint32_t RESERVED:25;
490 struct dc_cursor_attributes {
491 PHYSICAL_ADDRESS_LOC address;
494 /* Width and height should correspond to cursor surface width x heigh */
498 enum dc_cursor_color_format color_format;
499 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
501 /* In case we support HW Cursor rotation in the future */
502 enum dc_rotation_angle rotation_angle;
504 union dc_cursor_attribute_flags attribute_flags;
507 struct dpp_cursor_attributes {
514 enum dc_color_space {
518 COLOR_SPACE_SRGB_LIMITED,
519 COLOR_SPACE_MSREF_SCRGB,
520 COLOR_SPACE_YCBCR601,
521 COLOR_SPACE_YCBCR709,
522 COLOR_SPACE_XV_YCC_709,
523 COLOR_SPACE_XV_YCC_601,
524 COLOR_SPACE_YCBCR601_LIMITED,
525 COLOR_SPACE_YCBCR709_LIMITED,
526 COLOR_SPACE_2020_RGB_FULLRANGE,
527 COLOR_SPACE_2020_RGB_LIMITEDRANGE,
528 COLOR_SPACE_2020_YCBCR,
529 COLOR_SPACE_ADOBERGB,
531 COLOR_SPACE_DISPLAYNATIVE,
532 COLOR_SPACE_DOLBYVISION,
534 COLOR_SPACE_CUSTOMPOINTS,
537 enum dc_dither_option {
538 DITHER_OPTION_DEFAULT,
539 DITHER_OPTION_DISABLE,
543 DITHER_OPTION_SPATIAL6_FRAME_RANDOM,
544 DITHER_OPTION_SPATIAL8_FRAME_RANDOM,
545 DITHER_OPTION_SPATIAL10_FRAME_RANDOM,
546 DITHER_OPTION_SPATIAL6,
547 DITHER_OPTION_SPATIAL8,
548 DITHER_OPTION_SPATIAL10,
551 DITHER_OPTION_TRUN10,
552 DITHER_OPTION_TRUN10_SPATIAL8,
553 DITHER_OPTION_TRUN10_SPATIAL6,
554 DITHER_OPTION_TRUN10_FM8,
555 DITHER_OPTION_TRUN10_FM6,
556 DITHER_OPTION_TRUN10_SPATIAL8_FM6,
557 DITHER_OPTION_SPATIAL10_FM8,
558 DITHER_OPTION_SPATIAL10_FM6,
559 DITHER_OPTION_TRUN8_SPATIAL6,
560 DITHER_OPTION_TRUN8_FM6,
561 DITHER_OPTION_SPATIAL8_FM6,
562 DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6,
563 DITHER_OPTION_INVALID
566 enum dc_quantization_range {
567 QUANTIZATION_RANGE_UNKNOWN,
568 QUANTIZATION_RANGE_FULL,
569 QUANTIZATION_RANGE_LIMITED
574 /* used in struct dc_plane_state */
575 struct scaling_taps {
582 enum dc_timing_standard {
583 DC_TIMING_STANDARD_UNDEFINED,
584 DC_TIMING_STANDARD_DMT,
585 DC_TIMING_STANDARD_GTF,
586 DC_TIMING_STANDARD_CVT,
587 DC_TIMING_STANDARD_CVT_RB,
588 DC_TIMING_STANDARD_CEA770,
589 DC_TIMING_STANDARD_CEA861,
590 DC_TIMING_STANDARD_HDMI,
591 DC_TIMING_STANDARD_TV_NTSC,
592 DC_TIMING_STANDARD_TV_NTSC_J,
593 DC_TIMING_STANDARD_TV_PAL,
594 DC_TIMING_STANDARD_TV_PAL_M,
595 DC_TIMING_STANDARD_TV_PAL_CN,
596 DC_TIMING_STANDARD_TV_SECAM,
597 DC_TIMING_STANDARD_EXPLICIT,
598 /*!< For explicit timings from EDID, VBIOS, etc.*/
599 DC_TIMING_STANDARD_USER_OVERRIDE,
600 /*!< For mode timing override by user*/
601 DC_TIMING_STANDARD_MAX
604 enum dc_color_depth {
605 COLOR_DEPTH_UNDEFINED,
615 enum dc_pixel_encoding {
616 PIXEL_ENCODING_UNDEFINED,
618 PIXEL_ENCODING_YCBCR422,
619 PIXEL_ENCODING_YCBCR444,
620 PIXEL_ENCODING_YCBCR420,
624 enum dc_aspect_ratio {
625 ASPECT_RATIO_NO_DATA,
629 ASPECT_RATIO_256_135,
634 SCANNING_TYPE_NODATA = 0,
635 SCANNING_TYPE_OVERSCAN,
636 SCANNING_TYPE_UNDERSCAN,
637 SCANNING_TYPE_FUTURE,
638 SCANNING_TYPE_UNDEFINED
641 struct dc_crtc_timing_flags {
642 uint32_t INTERLACE :1;
643 uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
644 it is positive polarity --reversed with dal1 or video bios define*/
645 uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
646 it is positive polarity --reversed with dal1 or video bios define*/
648 uint32_t HORZ_COUNT_BY_TWO:1;
650 uint32_t EXCLUSIVE_3D :1; /* if this bit set,
651 timing can be driven in 3D format only
652 and there is no corresponding 2D timing*/
653 uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
654 (right eye = '1', left eye = '0') */
655 uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled
656 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
657 uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
658 because corresponding 2D timing also present in the list*/
659 uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
660 and we want to match priority of corresponding 3D timing*/
663 uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
664 uint32_t DTD_COUNTER :5; /* values 1 to 16 */
666 uint32_t FORCE_HDR :1;
668 /* HDMI 2.0 - Support scrambling for TMDS character
669 * rates less than or equal to 340Mcsc */
670 uint32_t LTE_340MCSC_SCRAMBLE:1;
674 enum dc_timing_3d_format {
675 TIMING_3D_FORMAT_NONE,
676 TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
677 TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
678 TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
679 /* for active DP-HDMI dongle*/
680 TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
681 TIMING_3D_FORMAT_HW_FRAME_PACKING,
682 TIMING_3D_FORMAT_SW_FRAME_PACKING,
683 TIMING_3D_FORMAT_ROW_INTERLEAVE,
684 TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
685 TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
686 TIMING_3D_FORMAT_SIDE_BY_SIDE,
687 TIMING_3D_FORMAT_TOP_AND_BOTTOM,
688 TIMING_3D_FORMAT_SBS_SW_PACKED,
689 /* Side-by-side, packed by application/driver into 2D frame*/
690 TIMING_3D_FORMAT_TB_SW_PACKED,
691 /* Top-and-bottom, packed by application/driver into 2D frame*/
693 TIMING_3D_FORMAT_MAX,
697 TRIGGER_DELAY_NEXT_PIXEL = 0,
698 TRIGGER_DELAY_NEXT_LINE,
702 CRTC_EVENT_VSYNC_RISING = 0,
703 CRTC_EVENT_VSYNC_FALLING
706 struct crtc_trigger_info {
708 struct dc_stream_state *event_source;
709 enum crtc_event event;
710 enum trigger_delay delay;
713 struct dc_crtc_timing_adjust {
714 uint32_t v_total_min;
715 uint32_t v_total_max;
718 struct dc_crtc_timing {
720 uint32_t h_border_left;
721 uint32_t h_addressable;
722 uint32_t h_border_right;
723 uint32_t h_front_porch;
724 uint32_t h_sync_width;
727 uint32_t v_border_top;
728 uint32_t v_addressable;
729 uint32_t v_border_bottom;
730 uint32_t v_front_porch;
731 uint32_t v_sync_width;
733 uint32_t pix_clk_khz;
737 enum dc_timing_3d_format timing_3d_format;
738 enum dc_color_depth display_color_depth;
739 enum dc_pixel_encoding pixel_encoding;
740 enum dc_aspect_ratio aspect_ratio;
741 enum scanning_type scan_type;
743 struct dc_crtc_timing_flags flags;
746 #define MAX_TG_COLOR_VALUE 0x3FF
748 /* Maximum 10 bits color value */
754 #endif /* DC_HW_TYPES_H */