drivers/gpu/drm/amd/display/dc/dc_hw_types.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef DC_HW_TYPES_H
  27 #define DC_HW_TYPES_H
  28
  29 #include "os_types.h"
  30 #include "fixed31_32.h"
  31 #include "signal_types.h"
  32
  33 /******************************************************************************
  34  * Data types for Virtual HW Layer of DAL3.
  35  * (see DAL3 design documents for HW Layer definition)
  36  *
  37  * The intended uses are:
  38  * 1. Generation pseudocode sequences for HW programming.
  39  * 2. Implementation of real HW programming by HW Sequencer of DAL3.
  40  *
  41  * Note: do *not* add any types which are *not* used for HW programming - this
  42  * will ensure separation of Logic layer from HW layer.
  43  ******************************************************************************/
  44
  45 union large_integer {
  46         struct {
  47                 uint32_t low_part;
  48                 int32_t high_part;
  49         };
  50
  51         struct {
  52                 uint32_t low_part;
  53                 int32_t high_part;
  54         } u;
  55
  56         int64_t quad_part;
  57 };
  58
  59 #define PHYSICAL_ADDRESS_LOC union large_integer
  60
  61 enum dc_plane_addr_type {
  62         PLN_ADDR_TYPE_GRAPHICS = 0,
  63         PLN_ADDR_TYPE_GRPH_STEREO,
  64         PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
  65         PLN_ADDR_TYPE_RGBEA
  66 };
  67
  68 struct dc_plane_address {
  69         enum dc_plane_addr_type type;
  70         bool tmz_surface;
  71         union {
  72                 struct{
  73                         PHYSICAL_ADDRESS_LOC addr;
  74                         PHYSICAL_ADDRESS_LOC cursor_cache_addr;
  75                         PHYSICAL_ADDRESS_LOC meta_addr;
  76                         union large_integer dcc_const_color;
  77                 } grph;
  78
  79                 /*stereo*/
  80                 struct {
  81                         PHYSICAL_ADDRESS_LOC left_addr;
  82                         PHYSICAL_ADDRESS_LOC left_meta_addr;
  83                         union large_integer left_dcc_const_color;
  84
  85                         PHYSICAL_ADDRESS_LOC right_addr;
  86                         PHYSICAL_ADDRESS_LOC right_meta_addr;
  87                         union large_integer right_dcc_const_color;
  88
  89                         PHYSICAL_ADDRESS_LOC left_alpha_addr;
  90                         PHYSICAL_ADDRESS_LOC left_alpha_meta_addr;
  91                         union large_integer left_alpha_dcc_const_color;
  92
  93                         PHYSICAL_ADDRESS_LOC right_alpha_addr;
  94                         PHYSICAL_ADDRESS_LOC right_alpha_meta_addr;
  95                         union large_integer right_alpha_dcc_const_color;
  96
  97                 } grph_stereo;
  98
  99                 /*video  progressive*/
 100                 struct {
 101                         PHYSICAL_ADDRESS_LOC luma_addr;
 102                         PHYSICAL_ADDRESS_LOC luma_meta_addr;
 103                         union large_integer luma_dcc_const_color;
 104
 105                         PHYSICAL_ADDRESS_LOC chroma_addr;
 106                         PHYSICAL_ADDRESS_LOC chroma_meta_addr;
 107                         union large_integer chroma_dcc_const_color;
 108                 } video_progressive;
 109
 110                 struct {
 111                         PHYSICAL_ADDRESS_LOC addr;
 112                         PHYSICAL_ADDRESS_LOC meta_addr;
 113                         union large_integer dcc_const_color;
 114
 115                         PHYSICAL_ADDRESS_LOC alpha_addr;
 116                         PHYSICAL_ADDRESS_LOC alpha_meta_addr;
 117                         union large_integer alpha_dcc_const_color;
 118                 } rgbea;
 119         };
 120
 121         union large_integer page_table_base;
 122
 123         uint8_t vmid;
 124 };
 125
 126 struct dc_size {
 127         int width;
 128         int height;
 129 };
 130
 131 struct rect {
 132         int x;
 133         int y;
 134         int width;
 135         int height;
 136 };
 137
 138 struct plane_size {
 139         /* Graphic surface pitch in pixels.
 140          * In LINEAR_GENERAL mode, pitch
 141          * is 32 pixel aligned.
 142          */
 143         int surface_pitch;
 144         int chroma_pitch;
 145         struct rect surface_size;
 146         struct rect chroma_size;
 147 };
 148
 149 struct dc_plane_dcc_param {
 150         bool enable;
 151
 152         int meta_pitch;
 153         bool independent_64b_blks;
 154         uint8_t dcc_ind_blk;
 155
 156         int meta_pitch_c;
 157         bool independent_64b_blks_c;
 158         uint8_t dcc_ind_blk_c;
 159 };
 160
 161 /*Displayable pixel format in fb*/
 162 enum surface_pixel_format {
 163         SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
 164         /*TOBE REMOVED paletta 256 colors*/
 165         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
 166                 SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
 167         /*16 bpp*/
 168         SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
 169         /*16 bpp*/
 170         SURFACE_PIXEL_FORMAT_GRPH_RGB565,
 171         /*32 bpp*/
 172         SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
 173         /*32 bpp swaped*/
 174         SURFACE_PIXEL_FORMAT_GRPH_ABGR8888,
 175
 176         SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
 177         /*swaped*/
 178         SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
 179         /*TOBE REMOVED swaped, XR_BIAS has no differance
 180          * for pixel layout than previous and we can
 181          * delete this after discusion*/
 182         SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
 183         /*64 bpp */
 184         SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
 185         /*swapped*/
 186         SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616,
 187         /*float*/
 188         SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F,
 189         /*swaped & float*/
 190         SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
 191         /*grow graphics here if necessary */
 192         SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX,
 193         SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX,
 194         SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT,
 195         SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT,
 196         SURFACE_PIXEL_FORMAT_GRPH_RGBE,
 197         SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA,
 198         SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
 199         SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
 200                 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
 201         SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
 202         SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
 203         SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
 204                 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
 205         SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010,
 206         SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102,
 207         SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888,
 208         SURFACE_PIXEL_FORMAT_INVALID
 209
 210         /*grow 444 video here if necessary */
 211 };
 212
 213
 214
 215 /* Pixel format */
 216 enum pixel_format {
 217         /*graph*/
 218         PIXEL_FORMAT_UNINITIALIZED,
 219         PIXEL_FORMAT_INDEX8,
 220         PIXEL_FORMAT_RGB565,
 221         PIXEL_FORMAT_ARGB8888,
 222         PIXEL_FORMAT_ARGB2101010,
 223         PIXEL_FORMAT_ARGB2101010_XRBIAS,
 224         PIXEL_FORMAT_FP16,
 225         /*video*/
 226         PIXEL_FORMAT_420BPP8,
 227         PIXEL_FORMAT_420BPP10,
 228         /*end of pixel format definition*/
 229         PIXEL_FORMAT_INVALID,
 230
 231         PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
 232         PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
 233         PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8,
 234         PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10,
 235         PIXEL_FORMAT_UNKNOWN
 236 };
 237
 238 enum tile_split_values {
 239         DC_DISPLAY_MICRO_TILING = 0x0,
 240         DC_THIN_MICRO_TILING = 0x1,
 241         DC_DEPTH_MICRO_TILING = 0x2,
 242         DC_ROTATED_MICRO_TILING = 0x3,
 243 };
 244
 245 enum tripleBuffer_enable {
 246         DC_TRIPLEBUFFER_DISABLE = 0x0,
 247         DC_TRIPLEBUFFER_ENABLE = 0x1,
 248 };
 249
 250 /* TODO: These values come from hardware spec. We need to readdress this
 251  * if they ever change.
 252  */
 253 enum array_mode_values {
 254         DC_ARRAY_LINEAR_GENERAL = 0,
 255         DC_ARRAY_LINEAR_ALLIGNED,
 256         DC_ARRAY_1D_TILED_THIN1,
 257         DC_ARRAY_1D_TILED_THICK,
 258         DC_ARRAY_2D_TILED_THIN1,
 259         DC_ARRAY_PRT_TILED_THIN1,
 260         DC_ARRAY_PRT_2D_TILED_THIN1,
 261         DC_ARRAY_2D_TILED_THICK,
 262         DC_ARRAY_2D_TILED_X_THICK,
 263         DC_ARRAY_PRT_TILED_THICK,
 264         DC_ARRAY_PRT_2D_TILED_THICK,
 265         DC_ARRAY_PRT_3D_TILED_THIN1,
 266         DC_ARRAY_3D_TILED_THIN1,
 267         DC_ARRAY_3D_TILED_THICK,
 268         DC_ARRAY_3D_TILED_X_THICK,
 269         DC_ARRAY_PRT_3D_TILED_THICK,
 270 };
 271
 272 enum tile_mode_values {
 273         DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
 274         DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
 275 };
 276
 277 enum swizzle_mode_values {
 278         DC_SW_LINEAR = 0,
 279         DC_SW_256B_S = 1,
 280         DC_SW_256_D = 2,
 281         DC_SW_256_R = 3,
 282         DC_SW_4KB_S = 5,
 283         DC_SW_4KB_D = 6,
 284         DC_SW_4KB_R = 7,
 285         DC_SW_64KB_S = 9,
 286         DC_SW_64KB_D = 10,
 287         DC_SW_64KB_R = 11,
 288         DC_SW_VAR_S = 13,
 289         DC_SW_VAR_D = 14,
 290         DC_SW_VAR_R = 15,
 291         DC_SW_64KB_S_T = 17,
 292         DC_SW_64KB_D_T = 18,
 293         DC_SW_4KB_S_X = 21,
 294         DC_SW_4KB_D_X = 22,
 295         DC_SW_4KB_R_X = 23,
 296         DC_SW_64KB_S_X = 25,
 297         DC_SW_64KB_D_X = 26,
 298         DC_SW_64KB_R_X = 27,
 299         DC_SW_VAR_S_X = 29,
 300         DC_SW_VAR_D_X = 30,
 301         DC_SW_VAR_R_X = 31,
 302         DC_SW_MAX = 32,
 303         DC_SW_UNKNOWN = DC_SW_MAX
 304 };
 305
 306 union dc_tiling_info {
 307
 308         struct {
 309                 /* Specifies the number of memory banks for tiling
 310                  *      purposes.
 311                  * Only applies to 2D and 3D tiling modes.
 312                  *      POSSIBLE VALUES: 2,4,8,16
 313                  */
 314                 unsigned int num_banks;
 315                 /* Specifies the number of tiles in the x direction
 316                  *      to be incorporated into the same bank.
 317                  * Only applies to 2D and 3D tiling modes.
 318                  *      POSSIBLE VALUES: 1,2,4,8
 319                  */
 320                 unsigned int bank_width;
 321                 unsigned int bank_width_c;
 322                 /* Specifies the number of tiles in the y direction to
 323                  *      be incorporated into the same bank.
 324                  * Only applies to 2D and 3D tiling modes.
 325                  *      POSSIBLE VALUES: 1,2,4,8
 326                  */
 327                 unsigned int bank_height;
 328                 unsigned int bank_height_c;
 329                 /* Specifies the macro tile aspect ratio. Only applies
 330                  * to 2D and 3D tiling modes.
 331                  */
 332                 unsigned int tile_aspect;
 333                 unsigned int tile_aspect_c;
 334                 /* Specifies the number of bytes that will be stored
 335                  *      contiguously for each tile.
 336                  * If the tile data requires more storage than this
 337                  *      amount, it is split into multiple slices.
 338                  * This field must not be larger than
 339                  *      GB_ADDR_CONFIG.DRAM_ROW_SIZE.
 340                  * Only applies to 2D and 3D tiling modes.
 341                  * For color render targets, TILE_SPLIT >= 256B.
 342                  */
 343                 enum tile_split_values tile_split;
 344                 enum tile_split_values tile_split_c;
 345                 /* Specifies the addressing within a tile.
 346                  *      0x0 - DISPLAY_MICRO_TILING
 347                  *      0x1 - THIN_MICRO_TILING
 348                  *      0x2 - DEPTH_MICRO_TILING
 349                  *      0x3 - ROTATED_MICRO_TILING
 350                  */
 351                 enum tile_mode_values tile_mode;
 352                 enum tile_mode_values tile_mode_c;
 353                 /* Specifies the number of pipes and how they are
 354                  *      interleaved in the surface.
 355                  * Refer to memory addressing document for complete
 356                  *      details and constraints.
 357                  */
 358                 unsigned int pipe_config;
 359                 /* Specifies the tiling mode of the surface.
 360                  * THIN tiles use an 8x8x1 tile size.
 361                  * THICK tiles use an 8x8x4 tile size.
 362                  * 2D tiling modes rotate banks for successive Z slices
 363                  * 3D tiling modes rotate pipes and banks for Z slices
 364                  * Refer to memory addressing document for complete
 365                  *      details and constraints.
 366                  */
 367                 enum array_mode_values array_mode;
 368         } gfx8;
 369
 370         struct {
 371                 enum swizzle_mode_values swizzle;
 372                 unsigned int num_pipes;
 373                 unsigned int max_compressed_frags;
 374                 unsigned int pipe_interleave;
 375
 376                 unsigned int num_banks;
 377                 unsigned int num_shader_engines;
 378                 unsigned int num_rb_per_se;
 379                 bool shaderEnable;
 380
 381                 bool meta_linear;
 382                 bool rb_aligned;
 383                 bool pipe_aligned;
 384                 unsigned int num_pkrs;
 385         } gfx9;
 386 };
 387
 388 /* Rotation angle */
 389 enum dc_rotation_angle {
 390         ROTATION_ANGLE_0 = 0,
 391         ROTATION_ANGLE_90,
 392         ROTATION_ANGLE_180,
 393         ROTATION_ANGLE_270,
 394         ROTATION_ANGLE_COUNT
 395 };
 396
 397 enum dc_scan_direction {
 398         SCAN_DIRECTION_UNKNOWN = 0,
 399         SCAN_DIRECTION_HORIZONTAL = 1,  /* 0, 180 rotation */
 400         SCAN_DIRECTION_VERTICAL = 2,    /* 90, 270 rotation */
 401 };
 402
 403 struct dc_cursor_position {
 404         uint32_t x;
 405         uint32_t y;
 406
 407         uint32_t x_hotspot;
 408         uint32_t y_hotspot;
 409
 410         /*
 411          * This parameter indicates whether HW cursor should be enabled
 412          */
 413         bool enable;
 414
 415         /* Translate cursor x/y by the source rectangle for each plane. */
 416         bool translate_by_source;
 417 };
 418
 419 struct dc_cursor_mi_param {
 420         unsigned int pixel_clk_khz;
 421         unsigned int ref_clk_khz;
 422         struct rect viewport;
 423         struct fixed31_32 h_scale_ratio;
 424         struct fixed31_32 v_scale_ratio;
 425         enum dc_rotation_angle rotation;
 426         bool mirror;
 427 };
 428
 429 /* IPP related types */
 430
 431 enum {
 432         GAMMA_RGB_256_ENTRIES = 256,
 433         GAMMA_RGB_FLOAT_1024_ENTRIES = 1024,
 434         GAMMA_CS_TFM_1D_ENTRIES = 4096,
 435         GAMMA_CUSTOM_ENTRIES = 4096,
 436         GAMMA_MAX_ENTRIES = 4096
 437 };
 438
 439 enum dc_gamma_type {
 440         GAMMA_RGB_256 = 1,
 441         GAMMA_RGB_FLOAT_1024 = 2,
 442         GAMMA_CS_TFM_1D = 3,
 443         GAMMA_CUSTOM = 4,
 444 };
 445
 446 struct dc_csc_transform {
 447         uint16_t matrix[12];
 448         bool enable_adjustment;
 449 };
 450
 451 struct dc_rgb_fixed {
 452         struct fixed31_32 red;
 453         struct fixed31_32 green;
 454         struct fixed31_32 blue;
 455 };
 456
 457 struct dc_gamma {
 458         struct kref refcount;
 459         enum dc_gamma_type type;
 460         unsigned int num_entries;
 461
 462         struct dc_gamma_entries {
 463                 struct fixed31_32 red[GAMMA_MAX_ENTRIES];
 464                 struct fixed31_32 green[GAMMA_MAX_ENTRIES];
 465                 struct fixed31_32 blue[GAMMA_MAX_ENTRIES];
 466         } entries;
 467
 468         /* private to DC core */
 469         struct dc_context *ctx;
 470
 471         /* is_identity is used for RGB256 gamma identity which can also be programmed in INPUT_LUT.
 472          * is_logical_identity indicates the given gamma ramp regardless of type is identity.
 473          */
 474         bool is_identity;
 475 };
 476
 477 /* Used by both ipp amd opp functions*/
 478 /* TODO: to be consolidated with enum color_space */
 479
 480 /*
 481  * This enum is for programming CURSOR_MODE register field. What this register
 482  * should be programmed to depends on OS requested cursor shape flags and what
 483  * we stored in the cursor surface.
 484  */
 485 enum dc_cursor_color_format {
 486         CURSOR_MODE_MONO,
 487         CURSOR_MODE_COLOR_1BIT_AND,
 488         CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
 489         CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA,
 490         CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED,
 491         CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED
 492 };
 493
 494 /*
 495  * This is all the parameters required by DAL in order to update the cursor
 496  * attributes, including the new cursor image surface address, size, hotspot
 497  * location, color format, etc.
 498  */
 499
 500 union dc_cursor_attribute_flags {
 501         struct {
 502                 uint32_t ENABLE_MAGNIFICATION:1;
 503                 uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
 504                 uint32_t HORIZONTAL_MIRROR:1;
 505                 uint32_t VERTICAL_MIRROR:1;
 506                 uint32_t INVERT_PIXEL_DATA:1;
 507                 uint32_t ZERO_EXPANSION:1;
 508                 uint32_t MIN_MAX_INVERT:1;
 509                 uint32_t ENABLE_CURSOR_DEGAMMA:1;
 510                 uint32_t RESERVED:24;
 511         } bits;
 512         uint32_t value;
 513 };
 514
 515 struct dc_cursor_attributes {
 516         PHYSICAL_ADDRESS_LOC address;
 517         uint32_t pitch;
 518
 519         /* Width and height should correspond to cursor surface width x heigh */
 520         uint32_t width;
 521         uint32_t height;
 522
 523         enum dc_cursor_color_format color_format;
 524         uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
 525
 526         /* In case we support HW Cursor rotation in the future */
 527         enum dc_rotation_angle rotation_angle;
 528
 529         union dc_cursor_attribute_flags attribute_flags;
 530 };
 531
 532 struct dpp_cursor_attributes {
 533         int bias;
 534         int scale;
 535 };
 536
 537 /* OPP */
 538
 539 enum dc_color_space {
 540         COLOR_SPACE_UNKNOWN,
 541         COLOR_SPACE_SRGB,
 542         COLOR_SPACE_XR_RGB,
 543         COLOR_SPACE_SRGB_LIMITED,
 544         COLOR_SPACE_MSREF_SCRGB,
 545         COLOR_SPACE_YCBCR601,
 546         COLOR_SPACE_YCBCR709,
 547         COLOR_SPACE_XV_YCC_709,
 548         COLOR_SPACE_XV_YCC_601,
 549         COLOR_SPACE_YCBCR601_LIMITED,
 550         COLOR_SPACE_YCBCR709_LIMITED,
 551         COLOR_SPACE_2020_RGB_FULLRANGE,
 552         COLOR_SPACE_2020_RGB_LIMITEDRANGE,
 553         COLOR_SPACE_2020_YCBCR,
 554         COLOR_SPACE_ADOBERGB,
 555         COLOR_SPACE_DCIP3,
 556         COLOR_SPACE_DISPLAYNATIVE,
 557         COLOR_SPACE_DOLBYVISION,
 558         COLOR_SPACE_APPCTRL,
 559         COLOR_SPACE_CUSTOMPOINTS,
 560         COLOR_SPACE_YCBCR709_BLACK,
 561 };
 562
 563 enum dc_dither_option {
 564         DITHER_OPTION_DEFAULT,
 565         DITHER_OPTION_DISABLE,
 566         DITHER_OPTION_FM6,
 567         DITHER_OPTION_FM8,
 568         DITHER_OPTION_FM10,
 569         DITHER_OPTION_SPATIAL6_FRAME_RANDOM,
 570         DITHER_OPTION_SPATIAL8_FRAME_RANDOM,
 571         DITHER_OPTION_SPATIAL10_FRAME_RANDOM,
 572         DITHER_OPTION_SPATIAL6,
 573         DITHER_OPTION_SPATIAL8,
 574         DITHER_OPTION_SPATIAL10,
 575         DITHER_OPTION_TRUN6,
 576         DITHER_OPTION_TRUN8,
 577         DITHER_OPTION_TRUN10,
 578         DITHER_OPTION_TRUN10_SPATIAL8,
 579         DITHER_OPTION_TRUN10_SPATIAL6,
 580         DITHER_OPTION_TRUN10_FM8,
 581         DITHER_OPTION_TRUN10_FM6,
 582         DITHER_OPTION_TRUN10_SPATIAL8_FM6,
 583         DITHER_OPTION_SPATIAL10_FM8,
 584         DITHER_OPTION_SPATIAL10_FM6,
 585         DITHER_OPTION_TRUN8_SPATIAL6,
 586         DITHER_OPTION_TRUN8_FM6,
 587         DITHER_OPTION_SPATIAL8_FM6,
 588         DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6,
 589         DITHER_OPTION_INVALID
 590 };
 591
 592 enum dc_quantization_range {
 593         QUANTIZATION_RANGE_UNKNOWN,
 594         QUANTIZATION_RANGE_FULL,
 595         QUANTIZATION_RANGE_LIMITED
 596 };
 597
 598 enum dc_dynamic_expansion {
 599         DYN_EXPANSION_AUTO,
 600         DYN_EXPANSION_DISABLE
 601 };
 602
 603 /* XFM */
 604
 605 /* used in  struct dc_plane_state */
 606 struct scaling_taps {
 607         uint32_t v_taps;
 608         uint32_t h_taps;
 609         uint32_t v_taps_c;
 610         uint32_t h_taps_c;
 611         bool integer_scaling;
 612 };
 613
 614 enum dc_timing_standard {
 615         DC_TIMING_STANDARD_UNDEFINED,
 616         DC_TIMING_STANDARD_DMT,
 617         DC_TIMING_STANDARD_GTF,
 618         DC_TIMING_STANDARD_CVT,
 619         DC_TIMING_STANDARD_CVT_RB,
 620         DC_TIMING_STANDARD_CEA770,
 621         DC_TIMING_STANDARD_CEA861,
 622         DC_TIMING_STANDARD_HDMI,
 623         DC_TIMING_STANDARD_TV_NTSC,
 624         DC_TIMING_STANDARD_TV_NTSC_J,
 625         DC_TIMING_STANDARD_TV_PAL,
 626         DC_TIMING_STANDARD_TV_PAL_M,
 627         DC_TIMING_STANDARD_TV_PAL_CN,
 628         DC_TIMING_STANDARD_TV_SECAM,
 629         DC_TIMING_STANDARD_EXPLICIT,
 630         /*!< For explicit timings from EDID, VBIOS, etc.*/
 631         DC_TIMING_STANDARD_USER_OVERRIDE,
 632         /*!< For mode timing override by user*/
 633         DC_TIMING_STANDARD_MAX
 634 };
 635
 636 enum dc_color_depth {
 637         COLOR_DEPTH_UNDEFINED,
 638         COLOR_DEPTH_666,
 639         COLOR_DEPTH_888,
 640         COLOR_DEPTH_101010,
 641         COLOR_DEPTH_121212,
 642         COLOR_DEPTH_141414,
 643         COLOR_DEPTH_161616,
 644         COLOR_DEPTH_999,
 645         COLOR_DEPTH_111111,
 646         COLOR_DEPTH_COUNT
 647 };
 648
 649 enum dc_pixel_encoding {
 650         PIXEL_ENCODING_UNDEFINED,
 651         PIXEL_ENCODING_RGB,
 652         PIXEL_ENCODING_YCBCR422,
 653         PIXEL_ENCODING_YCBCR444,
 654         PIXEL_ENCODING_YCBCR420,
 655         PIXEL_ENCODING_COUNT
 656 };
 657
 658 enum dc_aspect_ratio {
 659         ASPECT_RATIO_NO_DATA,
 660         ASPECT_RATIO_4_3,
 661         ASPECT_RATIO_16_9,
 662         ASPECT_RATIO_64_27,
 663         ASPECT_RATIO_256_135,
 664         ASPECT_RATIO_FUTURE
 665 };
 666
 667 enum scanning_type {
 668         SCANNING_TYPE_NODATA = 0,
 669         SCANNING_TYPE_OVERSCAN,
 670         SCANNING_TYPE_UNDERSCAN,
 671         SCANNING_TYPE_FUTURE,
 672         SCANNING_TYPE_UNDEFINED
 673 };
 674
 675 struct dc_crtc_timing_flags {
 676         uint32_t INTERLACE :1;
 677         uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
 678          it is positive polarity --reversed with dal1 or video bios define*/
 679         uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
 680          it is positive polarity --reversed with dal1 or video bios define*/
 681
 682         uint32_t HORZ_COUNT_BY_TWO:1;
 683
 684         uint32_t EXCLUSIVE_3D :1; /* if this bit set,
 685          timing can be driven in 3D format only
 686          and there is no corresponding 2D timing*/
 687         uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
 688          (right eye = '1', left eye = '0') */
 689         uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right  images subsampled
 690          when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
 691         uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
 692          because corresponding 2D timing also present in the list*/
 693         uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
 694          and we want to match priority of corresponding 3D timing*/
 695         uint32_t Y_ONLY :1;
 696
 697         uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
 698         uint32_t DTD_COUNTER :5; /* values 1 to 16 */
 699
 700         uint32_t FORCE_HDR :1;
 701
 702         /* HDMI 2.0 - Support scrambling for TMDS character
 703          * rates less than or equal to 340Mcsc */
 704         uint32_t LTE_340MCSC_SCRAMBLE:1;
 705
 706         uint32_t DSC : 1; /* Use DSC with this timing */
 707 #ifndef TRIM_FSFT
 708         uint32_t FAST_TRANSPORT: 1;
 709 #endif
 710         uint32_t VBLANK_SYNCHRONIZABLE: 1;
 711 };
 712
 713 enum dc_timing_3d_format {
 714         TIMING_3D_FORMAT_NONE,
 715         TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
 716         TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
 717         TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
 718         /* for active DP-HDMI dongle*/
 719         TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
 720         TIMING_3D_FORMAT_HW_FRAME_PACKING,
 721         TIMING_3D_FORMAT_SW_FRAME_PACKING,
 722         TIMING_3D_FORMAT_ROW_INTERLEAVE,
 723         TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
 724         TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
 725         TIMING_3D_FORMAT_SIDE_BY_SIDE,
 726         TIMING_3D_FORMAT_TOP_AND_BOTTOM,
 727         TIMING_3D_FORMAT_SBS_SW_PACKED,
 728         /* Side-by-side, packed by application/driver into 2D frame*/
 729         TIMING_3D_FORMAT_TB_SW_PACKED,
 730         /* Top-and-bottom, packed by application/driver into 2D frame*/
 731
 732         TIMING_3D_FORMAT_MAX,
 733 };
 734
 735 struct dc_dsc_config {
 736         uint32_t num_slices_h; /* Number of DSC slices - horizontal */
 737         uint32_t num_slices_v; /* Number of DSC slices - vertical */
 738         uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
 739         bool block_pred_enable; /* DSC block prediction enable */
 740         uint32_t linebuf_depth; /* DSC line buffer depth */
 741         uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */
 742         bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
 743         int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
 744         bool is_dp; /* indicate if DSC is applied based on DP's capability */
 745 };
 746 struct dc_crtc_timing {
 747         uint32_t h_total;
 748         uint32_t h_border_left;
 749         uint32_t h_addressable;
 750         uint32_t h_border_right;
 751         uint32_t h_front_porch;
 752         uint32_t h_sync_width;
 753
 754         uint32_t v_total;
 755         uint32_t v_border_top;
 756         uint32_t v_addressable;
 757         uint32_t v_border_bottom;
 758         uint32_t v_front_porch;
 759         uint32_t v_sync_width;
 760
 761         uint32_t pix_clk_100hz;
 762
 763         uint32_t vic;
 764         uint32_t hdmi_vic;
 765         enum dc_timing_3d_format timing_3d_format;
 766         enum dc_color_depth display_color_depth;
 767         enum dc_pixel_encoding pixel_encoding;
 768         enum dc_aspect_ratio aspect_ratio;
 769         enum scanning_type scan_type;
 770
 771 #ifndef TRIM_FSFT
 772         uint32_t fast_transport_output_rate_100hz;
 773 #endif
 774
 775         struct dc_crtc_timing_flags flags;
 776         uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
 777         struct dc_dsc_config dsc_cfg;
 778 };
 779
 780 enum trigger_delay {
 781         TRIGGER_DELAY_NEXT_PIXEL = 0,
 782         TRIGGER_DELAY_NEXT_LINE,
 783 };
 784
 785 enum crtc_event {
 786         CRTC_EVENT_VSYNC_RISING = 0,
 787         CRTC_EVENT_VSYNC_FALLING
 788 };
 789
 790 struct crtc_trigger_info {
 791         bool enabled;
 792         struct dc_stream_state *event_source;
 793         enum crtc_event event;
 794         enum trigger_delay delay;
 795 };
 796
 797 struct dc_crtc_timing_adjust {
 798         uint32_t v_total_min;
 799         uint32_t v_total_max;
 800         uint32_t v_total_mid;
 801         uint32_t v_total_mid_frame_num;
 802 };
 803
 804
 805 /* Passed on init */
 806 enum vram_type {
 807         VIDEO_MEMORY_TYPE_GDDR5  = 2,
 808         VIDEO_MEMORY_TYPE_DDR3   = 3,
 809         VIDEO_MEMORY_TYPE_DDR4   = 4,
 810         VIDEO_MEMORY_TYPE_HBM    = 5,
 811         VIDEO_MEMORY_TYPE_GDDR6  = 6,
 812 };
 813
 814 enum dwb_cnv_out_bpc {
 815         DWB_CNV_OUT_BPC_8BPC  = 0,
 816         DWB_CNV_OUT_BPC_10BPC = 1,
 817 };
 818
 819 enum dwb_output_depth {
 820         DWB_OUTPUT_PIXEL_DEPTH_8BPC = 0,
 821         DWB_OUTPUT_PIXEL_DEPTH_10BPC = 1,
 822 };
 823
 824 enum dwb_capture_rate {
 825         dwb_capture_rate_0 = 0, /* Every frame is captured. */
 826         dwb_capture_rate_1 = 1, /* Every other frame is captured. */
 827         dwb_capture_rate_2 = 2, /* Every 3rd frame is captured. */
 828         dwb_capture_rate_3 = 3, /* Every 4th frame is captured. */
 829 };
 830
 831 enum dwb_scaler_mode {
 832         dwb_scaler_mode_bypass444 = 0,
 833         dwb_scaler_mode_rgb444 = 1,
 834         dwb_scaler_mode_yuv444 = 2,
 835         dwb_scaler_mode_yuv420 = 3
 836 };
 837
 838 enum dwb_subsample_position {
 839         DWB_INTERSTITIAL_SUBSAMPLING = 0,
 840         DWB_COSITED_SUBSAMPLING      = 1
 841 };
 842
 843 enum dwb_stereo_eye_select {
 844         DWB_STEREO_EYE_LEFT  = 1,               /* Capture left eye only */
 845         DWB_STEREO_EYE_RIGHT = 2,               /* Capture right eye only */
 846 };
 847
 848 enum dwb_stereo_type {
 849         DWB_STEREO_TYPE_FRAME_PACKING = 0,              /* Frame packing */
 850         DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3,   /* Frame sequential */
 851 };
 852
 853 enum dwb_out_format {
 854         DWB_OUT_FORMAT_32BPP_ARGB = 0,
 855         DWB_OUT_FORMAT_32BPP_RGBA = 1,
 856         DWB_OUT_FORMAT_64BPP_ARGB = 2,
 857         DWB_OUT_FORMAT_64BPP_RGBA = 3
 858 };
 859
 860 enum dwb_out_denorm {
 861         DWB_OUT_DENORM_10BPC = 0,
 862         DWB_OUT_DENORM_8BPC = 1,
 863         DWB_OUT_DENORM_BYPASS = 2
 864 };
 865
 866 enum cm_gamut_remap_select {
 867         CM_GAMUT_REMAP_MODE_BYPASS = 0,
 868         CM_GAMUT_REMAP_MODE_RAMA_COEFF,
 869         CM_GAMUT_REMAP_MODE_RAMB_COEFF,
 870         CM_GAMUT_REMAP_MODE_RESERVED
 871 };
 872
 873 enum cm_gamut_coef_format {
 874         CM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0,
 875         CM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1
 876 };
 877
 878 struct mcif_warmup_params {
 879         union large_integer     start_address;
 880         unsigned int            address_increment;
 881         unsigned int            region_size;
 882         unsigned int            p_vmid;
 883 };
 884
 885 #define MCIF_BUF_COUNT  4
 886
 887 struct mcif_buf_params {
 888         unsigned long long      luma_address[MCIF_BUF_COUNT];
 889         unsigned long long      chroma_address[MCIF_BUF_COUNT];
 890         unsigned int            luma_pitch;
 891         unsigned int            chroma_pitch;
 892         unsigned int            warmup_pitch;
 893         unsigned int            swlock;
 894         unsigned int            p_vmid;
 895 };
 896
 897
 898 #define MAX_TG_COLOR_VALUE 0x3FF
 899 struct tg_color {
 900         /* Maximum 10 bits color value */
 901         uint16_t color_r_cr;
 902         uint16_t color_g_y;
 903         uint16_t color_b_cb;
 904 };
 905
 906 #endif /* DC_HW_TYPES_H */
 907