2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
30 #include "fixed31_32.h"
31 #include "signal_types.h"
33 /******************************************************************************
34 * Data types for Virtual HW Layer of DAL3.
35 * (see DAL3 design documents for HW Layer definition)
37 * The intended uses are:
38 * 1. Generation pseudocode sequences for HW programming.
39 * 2. Implementation of real HW programming by HW Sequencer of DAL3.
41 * Note: do *not* add any types which are *not* used for HW programming - this
42 * will ensure separation of Logic layer from HW layer.
43 ******************************************************************************/
59 #define PHYSICAL_ADDRESS_LOC union large_integer
61 enum dc_plane_addr_type {
62 PLN_ADDR_TYPE_GRAPHICS = 0,
63 PLN_ADDR_TYPE_GRPH_STEREO,
64 PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
68 struct dc_plane_address {
69 enum dc_plane_addr_type type;
73 PHYSICAL_ADDRESS_LOC addr;
74 PHYSICAL_ADDRESS_LOC cursor_cache_addr;
75 PHYSICAL_ADDRESS_LOC meta_addr;
76 union large_integer dcc_const_color;
81 PHYSICAL_ADDRESS_LOC left_addr;
82 PHYSICAL_ADDRESS_LOC left_meta_addr;
83 union large_integer left_dcc_const_color;
85 PHYSICAL_ADDRESS_LOC right_addr;
86 PHYSICAL_ADDRESS_LOC right_meta_addr;
87 union large_integer right_dcc_const_color;
89 PHYSICAL_ADDRESS_LOC left_alpha_addr;
90 PHYSICAL_ADDRESS_LOC left_alpha_meta_addr;
91 union large_integer left_alpha_dcc_const_color;
93 PHYSICAL_ADDRESS_LOC right_alpha_addr;
94 PHYSICAL_ADDRESS_LOC right_alpha_meta_addr;
95 union large_integer right_alpha_dcc_const_color;
101 PHYSICAL_ADDRESS_LOC luma_addr;
102 PHYSICAL_ADDRESS_LOC luma_meta_addr;
103 union large_integer luma_dcc_const_color;
105 PHYSICAL_ADDRESS_LOC chroma_addr;
106 PHYSICAL_ADDRESS_LOC chroma_meta_addr;
107 union large_integer chroma_dcc_const_color;
111 PHYSICAL_ADDRESS_LOC addr;
112 PHYSICAL_ADDRESS_LOC meta_addr;
113 union large_integer dcc_const_color;
115 PHYSICAL_ADDRESS_LOC alpha_addr;
116 PHYSICAL_ADDRESS_LOC alpha_meta_addr;
117 union large_integer alpha_dcc_const_color;
121 union large_integer page_table_base;
139 /* Graphic surface pitch in pixels.
140 * In LINEAR_GENERAL mode, pitch
141 * is 32 pixel aligned.
145 struct rect surface_size;
146 struct rect chroma_size;
149 struct dc_plane_dcc_param {
153 bool independent_64b_blks;
157 bool independent_64b_blks_c;
158 uint8_t dcc_ind_blk_c;
161 /*Displayable pixel format in fb*/
162 enum surface_pixel_format {
163 SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
164 /*TOBE REMOVED paletta 256 colors*/
165 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
166 SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
168 SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
170 SURFACE_PIXEL_FORMAT_GRPH_RGB565,
172 SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
174 SURFACE_PIXEL_FORMAT_GRPH_ABGR8888,
176 SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
178 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
179 /*TOBE REMOVED swaped, XR_BIAS has no differance
180 * for pixel layout than previous and we can
181 * delete this after discusion*/
182 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
184 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
186 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616,
188 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F,
190 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
191 /*grow graphics here if necessary */
192 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX,
193 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX,
194 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT,
195 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT,
196 SURFACE_PIXEL_FORMAT_GRPH_RGBE,
197 SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA,
198 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
199 SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
200 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
201 SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
202 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
203 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
204 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
205 SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010,
206 SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102,
207 SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888,
208 SURFACE_PIXEL_FORMAT_INVALID
210 /*grow 444 video here if necessary */
218 PIXEL_FORMAT_UNINITIALIZED,
221 PIXEL_FORMAT_ARGB8888,
222 PIXEL_FORMAT_ARGB2101010,
223 PIXEL_FORMAT_ARGB2101010_XRBIAS,
226 PIXEL_FORMAT_420BPP8,
227 PIXEL_FORMAT_420BPP10,
228 /*end of pixel format definition*/
229 PIXEL_FORMAT_INVALID,
231 PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
232 PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
233 PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8,
234 PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10,
238 enum tile_split_values {
239 DC_DISPLAY_MICRO_TILING = 0x0,
240 DC_THIN_MICRO_TILING = 0x1,
241 DC_DEPTH_MICRO_TILING = 0x2,
242 DC_ROTATED_MICRO_TILING = 0x3,
245 enum tripleBuffer_enable {
246 DC_TRIPLEBUFFER_DISABLE = 0x0,
247 DC_TRIPLEBUFFER_ENABLE = 0x1,
250 /* TODO: These values come from hardware spec. We need to readdress this
251 * if they ever change.
253 enum array_mode_values {
254 DC_ARRAY_LINEAR_GENERAL = 0,
255 DC_ARRAY_LINEAR_ALLIGNED,
256 DC_ARRAY_1D_TILED_THIN1,
257 DC_ARRAY_1D_TILED_THICK,
258 DC_ARRAY_2D_TILED_THIN1,
259 DC_ARRAY_PRT_TILED_THIN1,
260 DC_ARRAY_PRT_2D_TILED_THIN1,
261 DC_ARRAY_2D_TILED_THICK,
262 DC_ARRAY_2D_TILED_X_THICK,
263 DC_ARRAY_PRT_TILED_THICK,
264 DC_ARRAY_PRT_2D_TILED_THICK,
265 DC_ARRAY_PRT_3D_TILED_THIN1,
266 DC_ARRAY_3D_TILED_THIN1,
267 DC_ARRAY_3D_TILED_THICK,
268 DC_ARRAY_3D_TILED_X_THICK,
269 DC_ARRAY_PRT_3D_TILED_THICK,
272 enum tile_mode_values {
273 DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
274 DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
277 enum swizzle_mode_values {
303 DC_SW_UNKNOWN = DC_SW_MAX
306 union dc_tiling_info {
309 /* Specifies the number of memory banks for tiling
311 * Only applies to 2D and 3D tiling modes.
312 * POSSIBLE VALUES: 2,4,8,16
314 unsigned int num_banks;
315 /* Specifies the number of tiles in the x direction
316 * to be incorporated into the same bank.
317 * Only applies to 2D and 3D tiling modes.
318 * POSSIBLE VALUES: 1,2,4,8
320 unsigned int bank_width;
321 unsigned int bank_width_c;
322 /* Specifies the number of tiles in the y direction to
323 * be incorporated into the same bank.
324 * Only applies to 2D and 3D tiling modes.
325 * POSSIBLE VALUES: 1,2,4,8
327 unsigned int bank_height;
328 unsigned int bank_height_c;
329 /* Specifies the macro tile aspect ratio. Only applies
330 * to 2D and 3D tiling modes.
332 unsigned int tile_aspect;
333 unsigned int tile_aspect_c;
334 /* Specifies the number of bytes that will be stored
335 * contiguously for each tile.
336 * If the tile data requires more storage than this
337 * amount, it is split into multiple slices.
338 * This field must not be larger than
339 * GB_ADDR_CONFIG.DRAM_ROW_SIZE.
340 * Only applies to 2D and 3D tiling modes.
341 * For color render targets, TILE_SPLIT >= 256B.
343 enum tile_split_values tile_split;
344 enum tile_split_values tile_split_c;
345 /* Specifies the addressing within a tile.
346 * 0x0 - DISPLAY_MICRO_TILING
347 * 0x1 - THIN_MICRO_TILING
348 * 0x2 - DEPTH_MICRO_TILING
349 * 0x3 - ROTATED_MICRO_TILING
351 enum tile_mode_values tile_mode;
352 enum tile_mode_values tile_mode_c;
353 /* Specifies the number of pipes and how they are
354 * interleaved in the surface.
355 * Refer to memory addressing document for complete
356 * details and constraints.
358 unsigned int pipe_config;
359 /* Specifies the tiling mode of the surface.
360 * THIN tiles use an 8x8x1 tile size.
361 * THICK tiles use an 8x8x4 tile size.
362 * 2D tiling modes rotate banks for successive Z slices
363 * 3D tiling modes rotate pipes and banks for Z slices
364 * Refer to memory addressing document for complete
365 * details and constraints.
367 enum array_mode_values array_mode;
371 enum swizzle_mode_values swizzle;
372 unsigned int num_pipes;
373 unsigned int max_compressed_frags;
374 unsigned int pipe_interleave;
376 unsigned int num_banks;
377 unsigned int num_shader_engines;
378 unsigned int num_rb_per_se;
384 unsigned int num_pkrs;
389 enum dc_rotation_angle {
390 ROTATION_ANGLE_0 = 0,
397 enum dc_scan_direction {
398 SCAN_DIRECTION_UNKNOWN = 0,
399 SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */
400 SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */
403 struct dc_cursor_position {
411 * This parameter indicates whether HW cursor should be enabled
415 /* Translate cursor x/y by the source rectangle for each plane. */
416 bool translate_by_source;
419 struct dc_cursor_mi_param {
420 unsigned int pixel_clk_khz;
421 unsigned int ref_clk_khz;
422 struct rect viewport;
423 struct fixed31_32 h_scale_ratio;
424 struct fixed31_32 v_scale_ratio;
425 enum dc_rotation_angle rotation;
429 /* IPP related types */
432 GAMMA_RGB_256_ENTRIES = 256,
433 GAMMA_RGB_FLOAT_1024_ENTRIES = 1024,
434 GAMMA_CS_TFM_1D_ENTRIES = 4096,
435 GAMMA_CUSTOM_ENTRIES = 4096,
436 GAMMA_MAX_ENTRIES = 4096
441 GAMMA_RGB_FLOAT_1024 = 2,
446 struct dc_csc_transform {
448 bool enable_adjustment;
451 struct dc_rgb_fixed {
452 struct fixed31_32 red;
453 struct fixed31_32 green;
454 struct fixed31_32 blue;
458 struct kref refcount;
459 enum dc_gamma_type type;
460 unsigned int num_entries;
462 struct dc_gamma_entries {
463 struct fixed31_32 red[GAMMA_MAX_ENTRIES];
464 struct fixed31_32 green[GAMMA_MAX_ENTRIES];
465 struct fixed31_32 blue[GAMMA_MAX_ENTRIES];
468 /* private to DC core */
469 struct dc_context *ctx;
471 /* is_identity is used for RGB256 gamma identity which can also be programmed in INPUT_LUT.
472 * is_logical_identity indicates the given gamma ramp regardless of type is identity.
477 /* Used by both ipp amd opp functions*/
478 /* TODO: to be consolidated with enum color_space */
481 * This enum is for programming CURSOR_MODE register field. What this register
482 * should be programmed to depends on OS requested cursor shape flags and what
483 * we stored in the cursor surface.
485 enum dc_cursor_color_format {
487 CURSOR_MODE_COLOR_1BIT_AND,
488 CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
489 CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA,
490 CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED,
491 CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED
495 * This is all the parameters required by DAL in order to update the cursor
496 * attributes, including the new cursor image surface address, size, hotspot
497 * location, color format, etc.
500 union dc_cursor_attribute_flags {
502 uint32_t ENABLE_MAGNIFICATION:1;
503 uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
504 uint32_t HORIZONTAL_MIRROR:1;
505 uint32_t VERTICAL_MIRROR:1;
506 uint32_t INVERT_PIXEL_DATA:1;
507 uint32_t ZERO_EXPANSION:1;
508 uint32_t MIN_MAX_INVERT:1;
509 uint32_t ENABLE_CURSOR_DEGAMMA:1;
510 uint32_t RESERVED:24;
515 struct dc_cursor_attributes {
516 PHYSICAL_ADDRESS_LOC address;
519 /* Width and height should correspond to cursor surface width x heigh */
523 enum dc_cursor_color_format color_format;
524 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
526 /* In case we support HW Cursor rotation in the future */
527 enum dc_rotation_angle rotation_angle;
529 union dc_cursor_attribute_flags attribute_flags;
532 struct dpp_cursor_attributes {
539 enum dc_color_space {
543 COLOR_SPACE_SRGB_LIMITED,
544 COLOR_SPACE_MSREF_SCRGB,
545 COLOR_SPACE_YCBCR601,
546 COLOR_SPACE_YCBCR709,
547 COLOR_SPACE_XV_YCC_709,
548 COLOR_SPACE_XV_YCC_601,
549 COLOR_SPACE_YCBCR601_LIMITED,
550 COLOR_SPACE_YCBCR709_LIMITED,
551 COLOR_SPACE_2020_RGB_FULLRANGE,
552 COLOR_SPACE_2020_RGB_LIMITEDRANGE,
553 COLOR_SPACE_2020_YCBCR,
554 COLOR_SPACE_ADOBERGB,
556 COLOR_SPACE_DISPLAYNATIVE,
557 COLOR_SPACE_DOLBYVISION,
559 COLOR_SPACE_CUSTOMPOINTS,
560 COLOR_SPACE_YCBCR709_BLACK,
563 enum dc_dither_option {
564 DITHER_OPTION_DEFAULT,
565 DITHER_OPTION_DISABLE,
569 DITHER_OPTION_SPATIAL6_FRAME_RANDOM,
570 DITHER_OPTION_SPATIAL8_FRAME_RANDOM,
571 DITHER_OPTION_SPATIAL10_FRAME_RANDOM,
572 DITHER_OPTION_SPATIAL6,
573 DITHER_OPTION_SPATIAL8,
574 DITHER_OPTION_SPATIAL10,
577 DITHER_OPTION_TRUN10,
578 DITHER_OPTION_TRUN10_SPATIAL8,
579 DITHER_OPTION_TRUN10_SPATIAL6,
580 DITHER_OPTION_TRUN10_FM8,
581 DITHER_OPTION_TRUN10_FM6,
582 DITHER_OPTION_TRUN10_SPATIAL8_FM6,
583 DITHER_OPTION_SPATIAL10_FM8,
584 DITHER_OPTION_SPATIAL10_FM6,
585 DITHER_OPTION_TRUN8_SPATIAL6,
586 DITHER_OPTION_TRUN8_FM6,
587 DITHER_OPTION_SPATIAL8_FM6,
588 DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6,
589 DITHER_OPTION_INVALID
592 enum dc_quantization_range {
593 QUANTIZATION_RANGE_UNKNOWN,
594 QUANTIZATION_RANGE_FULL,
595 QUANTIZATION_RANGE_LIMITED
598 enum dc_dynamic_expansion {
600 DYN_EXPANSION_DISABLE
605 /* used in struct dc_plane_state */
606 struct scaling_taps {
611 bool integer_scaling;
614 enum dc_timing_standard {
615 DC_TIMING_STANDARD_UNDEFINED,
616 DC_TIMING_STANDARD_DMT,
617 DC_TIMING_STANDARD_GTF,
618 DC_TIMING_STANDARD_CVT,
619 DC_TIMING_STANDARD_CVT_RB,
620 DC_TIMING_STANDARD_CEA770,
621 DC_TIMING_STANDARD_CEA861,
622 DC_TIMING_STANDARD_HDMI,
623 DC_TIMING_STANDARD_TV_NTSC,
624 DC_TIMING_STANDARD_TV_NTSC_J,
625 DC_TIMING_STANDARD_TV_PAL,
626 DC_TIMING_STANDARD_TV_PAL_M,
627 DC_TIMING_STANDARD_TV_PAL_CN,
628 DC_TIMING_STANDARD_TV_SECAM,
629 DC_TIMING_STANDARD_EXPLICIT,
630 /*!< For explicit timings from EDID, VBIOS, etc.*/
631 DC_TIMING_STANDARD_USER_OVERRIDE,
632 /*!< For mode timing override by user*/
633 DC_TIMING_STANDARD_MAX
636 enum dc_color_depth {
637 COLOR_DEPTH_UNDEFINED,
649 enum dc_pixel_encoding {
650 PIXEL_ENCODING_UNDEFINED,
652 PIXEL_ENCODING_YCBCR422,
653 PIXEL_ENCODING_YCBCR444,
654 PIXEL_ENCODING_YCBCR420,
658 enum dc_aspect_ratio {
659 ASPECT_RATIO_NO_DATA,
663 ASPECT_RATIO_256_135,
668 SCANNING_TYPE_NODATA = 0,
669 SCANNING_TYPE_OVERSCAN,
670 SCANNING_TYPE_UNDERSCAN,
671 SCANNING_TYPE_FUTURE,
672 SCANNING_TYPE_UNDEFINED
675 struct dc_crtc_timing_flags {
676 uint32_t INTERLACE :1;
677 uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
678 it is positive polarity --reversed with dal1 or video bios define*/
679 uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
680 it is positive polarity --reversed with dal1 or video bios define*/
682 uint32_t HORZ_COUNT_BY_TWO:1;
684 uint32_t EXCLUSIVE_3D :1; /* if this bit set,
685 timing can be driven in 3D format only
686 and there is no corresponding 2D timing*/
687 uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
688 (right eye = '1', left eye = '0') */
689 uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled
690 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
691 uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
692 because corresponding 2D timing also present in the list*/
693 uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
694 and we want to match priority of corresponding 3D timing*/
697 uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
698 uint32_t DTD_COUNTER :5; /* values 1 to 16 */
700 uint32_t FORCE_HDR :1;
702 /* HDMI 2.0 - Support scrambling for TMDS character
703 * rates less than or equal to 340Mcsc */
704 uint32_t LTE_340MCSC_SCRAMBLE:1;
706 uint32_t DSC : 1; /* Use DSC with this timing */
708 uint32_t FAST_TRANSPORT: 1;
710 uint32_t VBLANK_SYNCHRONIZABLE: 1;
713 enum dc_timing_3d_format {
714 TIMING_3D_FORMAT_NONE,
715 TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
716 TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
717 TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
718 /* for active DP-HDMI dongle*/
719 TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
720 TIMING_3D_FORMAT_HW_FRAME_PACKING,
721 TIMING_3D_FORMAT_SW_FRAME_PACKING,
722 TIMING_3D_FORMAT_ROW_INTERLEAVE,
723 TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
724 TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
725 TIMING_3D_FORMAT_SIDE_BY_SIDE,
726 TIMING_3D_FORMAT_TOP_AND_BOTTOM,
727 TIMING_3D_FORMAT_SBS_SW_PACKED,
728 /* Side-by-side, packed by application/driver into 2D frame*/
729 TIMING_3D_FORMAT_TB_SW_PACKED,
730 /* Top-and-bottom, packed by application/driver into 2D frame*/
732 TIMING_3D_FORMAT_MAX,
735 struct dc_dsc_config {
736 uint32_t num_slices_h; /* Number of DSC slices - horizontal */
737 uint32_t num_slices_v; /* Number of DSC slices - vertical */
738 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
739 bool block_pred_enable; /* DSC block prediction enable */
740 uint32_t linebuf_depth; /* DSC line buffer depth */
741 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */
742 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
743 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
744 bool is_dp; /* indicate if DSC is applied based on DP's capability */
746 struct dc_crtc_timing {
748 uint32_t h_border_left;
749 uint32_t h_addressable;
750 uint32_t h_border_right;
751 uint32_t h_front_porch;
752 uint32_t h_sync_width;
755 uint32_t v_border_top;
756 uint32_t v_addressable;
757 uint32_t v_border_bottom;
758 uint32_t v_front_porch;
759 uint32_t v_sync_width;
761 uint32_t pix_clk_100hz;
765 enum dc_timing_3d_format timing_3d_format;
766 enum dc_color_depth display_color_depth;
767 enum dc_pixel_encoding pixel_encoding;
768 enum dc_aspect_ratio aspect_ratio;
769 enum scanning_type scan_type;
772 uint32_t fast_transport_output_rate_100hz;
775 struct dc_crtc_timing_flags flags;
776 uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
777 struct dc_dsc_config dsc_cfg;
781 TRIGGER_DELAY_NEXT_PIXEL = 0,
782 TRIGGER_DELAY_NEXT_LINE,
786 CRTC_EVENT_VSYNC_RISING = 0,
787 CRTC_EVENT_VSYNC_FALLING
790 struct crtc_trigger_info {
792 struct dc_stream_state *event_source;
793 enum crtc_event event;
794 enum trigger_delay delay;
797 struct dc_crtc_timing_adjust {
798 uint32_t v_total_min;
799 uint32_t v_total_max;
800 uint32_t v_total_mid;
801 uint32_t v_total_mid_frame_num;
807 VIDEO_MEMORY_TYPE_GDDR5 = 2,
808 VIDEO_MEMORY_TYPE_DDR3 = 3,
809 VIDEO_MEMORY_TYPE_DDR4 = 4,
810 VIDEO_MEMORY_TYPE_HBM = 5,
811 VIDEO_MEMORY_TYPE_GDDR6 = 6,
814 enum dwb_cnv_out_bpc {
815 DWB_CNV_OUT_BPC_8BPC = 0,
816 DWB_CNV_OUT_BPC_10BPC = 1,
819 enum dwb_output_depth {
820 DWB_OUTPUT_PIXEL_DEPTH_8BPC = 0,
821 DWB_OUTPUT_PIXEL_DEPTH_10BPC = 1,
824 enum dwb_capture_rate {
825 dwb_capture_rate_0 = 0, /* Every frame is captured. */
826 dwb_capture_rate_1 = 1, /* Every other frame is captured. */
827 dwb_capture_rate_2 = 2, /* Every 3rd frame is captured. */
828 dwb_capture_rate_3 = 3, /* Every 4th frame is captured. */
831 enum dwb_scaler_mode {
832 dwb_scaler_mode_bypass444 = 0,
833 dwb_scaler_mode_rgb444 = 1,
834 dwb_scaler_mode_yuv444 = 2,
835 dwb_scaler_mode_yuv420 = 3
838 enum dwb_subsample_position {
839 DWB_INTERSTITIAL_SUBSAMPLING = 0,
840 DWB_COSITED_SUBSAMPLING = 1
843 enum dwb_stereo_eye_select {
844 DWB_STEREO_EYE_LEFT = 1, /* Capture left eye only */
845 DWB_STEREO_EYE_RIGHT = 2, /* Capture right eye only */
848 enum dwb_stereo_type {
849 DWB_STEREO_TYPE_FRAME_PACKING = 0, /* Frame packing */
850 DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */
853 enum dwb_out_format {
854 DWB_OUT_FORMAT_32BPP_ARGB = 0,
855 DWB_OUT_FORMAT_32BPP_RGBA = 1,
856 DWB_OUT_FORMAT_64BPP_ARGB = 2,
857 DWB_OUT_FORMAT_64BPP_RGBA = 3
860 enum dwb_out_denorm {
861 DWB_OUT_DENORM_10BPC = 0,
862 DWB_OUT_DENORM_8BPC = 1,
863 DWB_OUT_DENORM_BYPASS = 2
866 enum cm_gamut_remap_select {
867 CM_GAMUT_REMAP_MODE_BYPASS = 0,
868 CM_GAMUT_REMAP_MODE_RAMA_COEFF,
869 CM_GAMUT_REMAP_MODE_RAMB_COEFF,
870 CM_GAMUT_REMAP_MODE_RESERVED
873 enum cm_gamut_coef_format {
874 CM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0,
875 CM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1
878 struct mcif_warmup_params {
879 union large_integer start_address;
880 unsigned int address_increment;
881 unsigned int region_size;
885 #define MCIF_BUF_COUNT 4
887 struct mcif_buf_params {
888 unsigned long long luma_address[MCIF_BUF_COUNT];
889 unsigned long long chroma_address[MCIF_BUF_COUNT];
890 unsigned int luma_pitch;
891 unsigned int chroma_pitch;
892 unsigned int warmup_pitch;
898 #define MAX_TG_COLOR_VALUE 0x3FF
900 /* Maximum 10 bits color value */
906 #endif /* DC_HW_TYPES_H */