4 * Created on: Aug 30, 2016
7 #include "dm_services.h"
10 uint32_t generic_reg_update_ex(const struct dc_context *ctx,
11 uint32_t addr, uint32_t reg_val, int n,
12 uint8_t shift1, uint32_t mask1, uint32_t field_value1,
15 uint32_t shift, mask, field_value;
19 va_start(ap, field_value1);
21 reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1);
24 shift = va_arg(ap, uint32_t);
25 mask = va_arg(ap, uint32_t);
26 field_value = va_arg(ap, uint32_t);
28 reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
32 dm_write_reg(ctx, addr, reg_val);
38 uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
39 uint8_t shift, uint32_t mask, uint32_t *field_value)
41 uint32_t reg_val = dm_read_reg(ctx, addr);
42 *field_value = get_reg_field_value_ex(reg_val, mask, shift);
46 uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
47 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
48 uint8_t shift2, uint32_t mask2, uint32_t *field_value2)
50 uint32_t reg_val = dm_read_reg(ctx, addr);
51 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
52 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
56 uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
57 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
58 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
59 uint8_t shift3, uint32_t mask3, uint32_t *field_value3)
61 uint32_t reg_val = dm_read_reg(ctx, addr);
62 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
63 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
64 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
68 uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr,
69 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
70 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
71 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
72 uint8_t shift4, uint32_t mask4, uint32_t *field_value4)
74 uint32_t reg_val = dm_read_reg(ctx, addr);
75 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
76 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
77 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
78 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
82 uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
83 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
84 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
85 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
86 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
87 uint8_t shift5, uint32_t mask5, uint32_t *field_value5)
89 uint32_t reg_val = dm_read_reg(ctx, addr);
90 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
91 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
92 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
93 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
94 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
98 /* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer
99 * compiler won't be able to check for size match and is prone to stack corruption type of bugs
101 uint32_t generic_reg_get(const struct dc_context *ctx,
102 uint32_t addr, int n, ...)
104 uint32_t shift, mask;
105 uint32_t *field_value;
109 reg_val = dm_read_reg(ctx, addr);
115 shift = va_arg(ap, uint32_t);
116 mask = va_arg(ap, uint32_t);
117 field_value = va_arg(ap, uint32_t *);
119 *field_value = get_reg_field_value_ex(reg_val, mask, shift);
129 uint32_t generic_reg_wait(const struct dc_context *ctx,
130 uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value,
131 unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
132 const char *func_name, int line)
134 uint32_t field_value;
138 /* something is terribly wrong if time out is > 200ms. (5Hz) */
139 ASSERT(delay_between_poll_us * time_out_num_tries <= 200000);
141 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
143 delay_between_poll_us = 35000;
144 time_out_num_tries = 1000;
147 for (i = 0; i <= time_out_num_tries; i++) {
149 if (delay_between_poll_us >= 1000)
150 msleep(delay_between_poll_us/1000);
151 else if (delay_between_poll_us > 0)
152 udelay(delay_between_poll_us);
155 reg_val = dm_read_reg(ctx, addr);
157 field_value = get_reg_field_value_ex(reg_val, mask, shift);
159 if (field_value == condition_value)
163 dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n",
164 delay_between_poll_us, time_out_num_tries,
167 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))