1 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
5 * Copyright 2019 Advanced Micro Devices, Inc.
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28 /* put it here temporarily until linux has the new addresses official defined */
29 /* DP Extended DSC Capabilities */
30 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
31 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
32 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
35 struct dc_dsc_bw_range {
36 uint32_t min_kbps; /* Bandwidth if min_target_bpp_x16 is used */
37 uint32_t min_target_bpp_x16;
38 uint32_t max_kbps; /* Bandwidth if max_target_bpp_x16 is used */
39 uint32_t max_target_bpp_x16;
40 uint32_t stream_kbps; /* Uncompressed stream bandwidth */
43 struct display_stream_compressor {
44 const struct dsc_funcs *funcs;
45 #ifndef AMD_EDID_UTILITY
46 struct dc_context *ctx;
51 bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data,
52 const uint8_t *dpcd_dsc_ext_data,
53 struct dsc_dec_dpcd_caps *dsc_sink_caps);
55 bool dc_dsc_compute_bandwidth_range(
56 const struct display_stream_compressor *dsc,
57 const uint32_t dsc_min_slice_height_override,
58 const uint32_t min_kbps,
59 const uint32_t max_kbps,
60 const struct dsc_dec_dpcd_caps *dsc_sink_caps,
61 const struct dc_crtc_timing *timing,
62 struct dc_dsc_bw_range *range);
64 bool dc_dsc_compute_config(
65 const struct display_stream_compressor *dsc,
66 const struct dsc_dec_dpcd_caps *dsc_sink_caps,
67 const uint32_t dsc_min_slice_height_override,
68 uint32_t target_bandwidth_kbps,
69 const struct dc_crtc_timing *timing,
70 struct dc_dsc_config *dsc_cfg);