drivers/gpu/drm/amd/display/dc/dc_dp_types.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef DC_DP_TYPES_H
  27 #define DC_DP_TYPES_H
  28
  29 #include "os_types.h"
  30
  31 enum dc_lane_count {
  32         LANE_COUNT_UNKNOWN = 0,
  33         LANE_COUNT_ONE = 1,
  34         LANE_COUNT_TWO = 2,
  35         LANE_COUNT_FOUR = 4,
  36         LANE_COUNT_EIGHT = 8,
  37         LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
  38 };
  39
  40 /* This is actually a reference clock (27MHz) multiplier
  41  * 162MBps bandwidth for 1.62GHz like rate,
  42  * 270MBps for 2.70GHz,
  43  * 324MBps for 3.24Ghz,
  44  * 540MBps for 5.40GHz
  45  * 810MBps for 8.10GHz
  46  */
  47 enum dc_link_rate {
  48         LINK_RATE_UNKNOWN = 0,
  49         LINK_RATE_LOW = 0x06,           // Rate_1 (RBR) - 1.62 Gbps/Lane
  50         LINK_RATE_RATE_2 = 0x08,        // Rate_2               - 2.16 Gbps/Lane
  51         LINK_RATE_RATE_3 = 0x09,        // Rate_3               - 2.43 Gbps/Lane
  52         LINK_RATE_HIGH = 0x0A,          // Rate_4 (HBR) - 2.70 Gbps/Lane
  53         LINK_RATE_RBR2 = 0x0C,          // Rate_5 (RBR2)- 3.24 Gbps/Lane
  54         LINK_RATE_RATE_6 = 0x10,        // Rate_6               - 4.32 Gbps/Lane
  55         LINK_RATE_HIGH2 = 0x14,         // Rate_7 (HBR2)- 5.40 Gbps/Lane
  56         LINK_RATE_HIGH3 = 0x1E          // Rate_8 (HBR3)- 8.10 Gbps/Lane
  57 };
  58
  59 enum dc_link_spread {
  60         LINK_SPREAD_DISABLED = 0x00,
  61         /* 0.5 % downspread 30 kHz */
  62         LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
  63         /* 0.5 % downspread 33 kHz */
  64         LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
  65 };
  66
  67 enum dc_voltage_swing {
  68         VOLTAGE_SWING_LEVEL0 = 0,       /* direct HW translation! */
  69         VOLTAGE_SWING_LEVEL1,
  70         VOLTAGE_SWING_LEVEL2,
  71         VOLTAGE_SWING_LEVEL3,
  72         VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
  73 };
  74
  75 enum dc_pre_emphasis {
  76         PRE_EMPHASIS_DISABLED = 0,      /* direct HW translation! */
  77         PRE_EMPHASIS_LEVEL1,
  78         PRE_EMPHASIS_LEVEL2,
  79         PRE_EMPHASIS_LEVEL3,
  80         PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
  81 };
  82 /* Post Cursor 2 is optional for transmitter
  83  * and it applies only to the main link operating at HBR2
  84  */
  85 enum dc_post_cursor2 {
  86         POST_CURSOR2_DISABLED = 0,      /* direct HW translation! */
  87         POST_CURSOR2_LEVEL1,
  88         POST_CURSOR2_LEVEL2,
  89         POST_CURSOR2_LEVEL3,
  90         POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
  91 };
  92
  93 enum dc_dp_training_pattern {
  94         DP_TRAINING_PATTERN_SEQUENCE_1 = 0,
  95         DP_TRAINING_PATTERN_SEQUENCE_2,
  96         DP_TRAINING_PATTERN_SEQUENCE_3,
  97         DP_TRAINING_PATTERN_SEQUENCE_4,
  98 };
  99
 100 struct dc_link_settings {
 101         enum dc_lane_count lane_count;
 102         enum dc_link_rate link_rate;
 103         enum dc_link_spread link_spread;
 104         bool use_link_rate_set;
 105         uint8_t link_rate_set;
 106 };
 107
 108 struct dc_lane_settings {
 109         enum dc_voltage_swing VOLTAGE_SWING;
 110         enum dc_pre_emphasis PRE_EMPHASIS;
 111         enum dc_post_cursor2 POST_CURSOR2;
 112 };
 113
 114 struct dc_link_training_settings {
 115         struct dc_link_settings link;
 116         struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
 117 };
 118
 119 struct dc_link_training_overrides {
 120         enum dc_voltage_swing *voltage_swing;
 121         enum dc_pre_emphasis *pre_emphasis;
 122         enum dc_post_cursor2 *post_cursor2;
 123
 124         uint16_t *cr_pattern_time;
 125         uint16_t *eq_pattern_time;
 126         enum dc_dp_training_pattern *pattern_for_eq;
 127
 128         enum dc_link_spread *downspread;
 129         bool *alternate_scrambler_reset;
 130         bool *enhanced_framing;
 131         bool *mst_enable;
 132         bool *fec_enable;
 133 };
 134
 135 union dpcd_rev {
 136         struct {
 137                 uint8_t MINOR:4;
 138                 uint8_t MAJOR:4;
 139         } bits;
 140         uint8_t raw;
 141 };
 142
 143 union max_lane_count {
 144         struct {
 145                 uint8_t MAX_LANE_COUNT:5;
 146                 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
 147                 uint8_t TPS3_SUPPORTED:1;
 148                 uint8_t ENHANCED_FRAME_CAP:1;
 149         } bits;
 150         uint8_t raw;
 151 };
 152
 153 union max_down_spread {
 154         struct {
 155                 uint8_t MAX_DOWN_SPREAD:1;
 156                 uint8_t RESERVED:5;
 157                 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
 158                 uint8_t TPS4_SUPPORTED:1;
 159         } bits;
 160         uint8_t raw;
 161 };
 162
 163 union mstm_cap {
 164         struct {
 165                 uint8_t MST_CAP:1;
 166                 uint8_t RESERVED:7;
 167         } bits;
 168         uint8_t raw;
 169 };
 170
 171 union lane_count_set {
 172         struct {
 173                 uint8_t LANE_COUNT_SET:5;
 174                 uint8_t POST_LT_ADJ_REQ_GRANTED:1;
 175                 uint8_t RESERVED:1;
 176                 uint8_t ENHANCED_FRAMING:1;
 177         } bits;
 178         uint8_t raw;
 179 };
 180
 181 union lane_status {
 182         struct {
 183                 uint8_t CR_DONE_0:1;
 184                 uint8_t CHANNEL_EQ_DONE_0:1;
 185                 uint8_t SYMBOL_LOCKED_0:1;
 186                 uint8_t RESERVED0:1;
 187                 uint8_t CR_DONE_1:1;
 188                 uint8_t CHANNEL_EQ_DONE_1:1;
 189                 uint8_t SYMBOL_LOCKED_1:1;
 190                 uint8_t RESERVED_1:1;
 191         } bits;
 192         uint8_t raw;
 193 };
 194
 195 union device_service_irq {
 196         struct {
 197                 uint8_t REMOTE_CONTROL_CMD_PENDING:1;
 198                 uint8_t AUTOMATED_TEST:1;
 199                 uint8_t CP_IRQ:1;
 200                 uint8_t MCCS_IRQ:1;
 201                 uint8_t DOWN_REP_MSG_RDY:1;
 202                 uint8_t UP_REQ_MSG_RDY:1;
 203                 uint8_t SINK_SPECIFIC:1;
 204                 uint8_t reserved:1;
 205         } bits;
 206         uint8_t raw;
 207 };
 208
 209 union sink_count {
 210         struct {
 211                 uint8_t SINK_COUNT:6;
 212                 uint8_t CPREADY:1;
 213                 uint8_t RESERVED:1;
 214         } bits;
 215         uint8_t raw;
 216 };
 217
 218 union lane_align_status_updated {
 219         struct {
 220                 uint8_t INTERLANE_ALIGN_DONE:1;
 221                 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
 222                 uint8_t RESERVED:4;
 223                 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
 224                 uint8_t LINK_STATUS_UPDATED:1;
 225         } bits;
 226         uint8_t raw;
 227 };
 228
 229 union lane_adjust {
 230         struct {
 231                 uint8_t VOLTAGE_SWING_LANE:2;
 232                 uint8_t PRE_EMPHASIS_LANE:2;
 233                 uint8_t RESERVED:4;
 234         } bits;
 235         uint8_t raw;
 236 };
 237
 238 union dpcd_training_pattern {
 239         struct {
 240                 uint8_t TRAINING_PATTERN_SET:4;
 241                 uint8_t RECOVERED_CLOCK_OUT_EN:1;
 242                 uint8_t SCRAMBLING_DISABLE:1;
 243                 uint8_t SYMBOL_ERROR_COUNT_SEL:2;
 244         } v1_4;
 245         struct {
 246                 uint8_t TRAINING_PATTERN_SET:2;
 247                 uint8_t LINK_QUAL_PATTERN_SET:2;
 248                 uint8_t RESERVED:4;
 249         } v1_3;
 250         uint8_t raw;
 251 };
 252
 253 /* Training Lane is used to configure downstream DP device's voltage swing
 254 and pre-emphasis levels*/
 255 /* The DPCD addresses are from 0x103 to 0x106*/
 256 union dpcd_training_lane {
 257         struct {
 258                 uint8_t VOLTAGE_SWING_SET:2;
 259                 uint8_t MAX_SWING_REACHED:1;
 260                 uint8_t PRE_EMPHASIS_SET:2;
 261                 uint8_t MAX_PRE_EMPHASIS_REACHED:1;
 262                 uint8_t RESERVED:2;
 263         } bits;
 264         uint8_t raw;
 265 };
 266
 267 /* TMDS-converter related */
 268 union dwnstream_port_caps_byte0 {
 269         struct {
 270                 uint8_t DWN_STRM_PORTX_TYPE:3;
 271                 uint8_t DWN_STRM_PORTX_HPD:1;
 272                 uint8_t RESERVERD:4;
 273         } bits;
 274         uint8_t raw;
 275 };
 276
 277 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
 278 enum dpcd_downstream_port_detailed_type {
 279         DOWN_STREAM_DETAILED_DP = 0,
 280         DOWN_STREAM_DETAILED_VGA,
 281         DOWN_STREAM_DETAILED_DVI,
 282         DOWN_STREAM_DETAILED_HDMI,
 283         DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
 284         DOWN_STREAM_DETAILED_DP_PLUS_PLUS
 285 };
 286
 287 union dwnstream_port_caps_byte2 {
 288         struct {
 289                 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
 290                 uint8_t RESERVED:6;
 291         } bits;
 292         uint8_t raw;
 293 };
 294
 295 union dp_downstream_port_present {
 296         uint8_t byte;
 297         struct {
 298                 uint8_t PORT_PRESENT:1;
 299                 uint8_t PORT_TYPE:2;
 300                 uint8_t FMT_CONVERSION:1;
 301                 uint8_t DETAILED_CAPS:1;
 302                 uint8_t RESERVED:3;
 303         } fields;
 304 };
 305
 306 union dwnstream_port_caps_byte3_dvi {
 307         struct {
 308                 uint8_t RESERVED1:1;
 309                 uint8_t DUAL_LINK:1;
 310                 uint8_t HIGH_COLOR_DEPTH:1;
 311                 uint8_t RESERVED2:5;
 312         } bits;
 313         uint8_t raw;
 314 };
 315
 316 union dwnstream_port_caps_byte3_hdmi {
 317         struct {
 318                 uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
 319                 uint8_t YCrCr422_PASS_THROUGH:1;
 320                 uint8_t YCrCr420_PASS_THROUGH:1;
 321                 uint8_t YCrCr422_CONVERSION:1;
 322                 uint8_t YCrCr420_CONVERSION:1;
 323                 uint8_t RESERVED:3;
 324         } bits;
 325         uint8_t raw;
 326 };
 327
 328 /*4-byte structure for detailed capabilities of a down-stream port
 329 (DP-to-TMDS converter).*/
 330 union dwnstream_portxcaps {
 331         struct {
 332                 union dwnstream_port_caps_byte0 byte0;
 333                 unsigned char max_TMDS_clock;   //byte1
 334                 union dwnstream_port_caps_byte2 byte2;
 335
 336                 union {
 337                         union dwnstream_port_caps_byte3_dvi byteDVI;
 338                         union dwnstream_port_caps_byte3_hdmi byteHDMI;
 339                 } byte3;
 340         } bytes;
 341
 342         unsigned char raw[4];
 343 };
 344
 345 union downstream_port {
 346         struct {
 347                 unsigned char   present:1;
 348                 unsigned char   type:2;
 349                 unsigned char   format_conv:1;
 350                 unsigned char   detailed_caps:1;
 351                 unsigned char   reserved:3;
 352         } bits;
 353         unsigned char raw;
 354 };
 355
 356
 357 union sink_status {
 358         struct {
 359                 uint8_t RX_PORT0_STATUS:1;
 360                 uint8_t RX_PORT1_STATUS:1;
 361                 uint8_t RESERVED:6;
 362         } bits;
 363         uint8_t raw;
 364 };
 365
 366 /*6-byte structure corresponding to 6 registers (200h-205h)
 367 read during handling of HPD-IRQ*/
 368 union hpd_irq_data {
 369         struct {
 370                 union sink_count sink_cnt;/* 200h */
 371                 union device_service_irq device_service_irq;/* 201h */
 372                 union lane_status lane01_status;/* 202h */
 373                 union lane_status lane23_status;/* 203h */
 374                 union lane_align_status_updated lane_status_updated;/* 204h */
 375                 union sink_status sink_status;
 376         } bytes;
 377         uint8_t raw[6];
 378 };
 379
 380 union down_stream_port_count {
 381         struct {
 382                 uint8_t DOWN_STR_PORT_COUNT:4;
 383                 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
 384                 /*Bit 6 = MSA_TIMING_PAR_IGNORED
 385                 0 = Sink device requires the MSA timing parameters
 386                 1 = Sink device is capable of rendering incoming video
 387                  stream without MSA timing parameters*/
 388                 uint8_t IGNORE_MSA_TIMING_PARAM:1;
 389                 /*Bit 7 = OUI Support
 390                 0 = OUI not supported
 391                 1 = OUI supported
 392                 (OUI and Device Identification mandatory for DP 1.2)*/
 393                 uint8_t OUI_SUPPORT:1;
 394         } bits;
 395         uint8_t raw;
 396 };
 397
 398 union down_spread_ctrl {
 399         struct {
 400                 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
 401         /* Bits 4 = SPREAD_AMP. Spreading amplitude
 402         0 = Main link signal is not downspread
 403         1 = Main link signal is downspread <= 0.5%
 404         with frequency in the range of 30kHz ~ 33kHz*/
 405                 uint8_t SPREAD_AMP:1;
 406                 uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/
 407         /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
 408         0 = Source device will send valid data for the MSA Timing Params
 409         1 = Source device may send invalid data for these MSA Timing Params*/
 410                 uint8_t IGNORE_MSA_TIMING_PARAM:1;
 411         } bits;
 412         uint8_t raw;
 413 };
 414
 415 union dpcd_edp_config {
 416         struct {
 417                 uint8_t PANEL_MODE_EDP:1;
 418                 uint8_t FRAMING_CHANGE_ENABLE:1;
 419                 uint8_t RESERVED:5;
 420                 uint8_t PANEL_SELF_TEST_ENABLE:1;
 421         } bits;
 422         uint8_t raw;
 423 };
 424
 425 struct dp_device_vendor_id {
 426         uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
 427         uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
 428 };
 429
 430 struct dp_sink_hw_fw_revision {
 431         uint8_t ieee_hw_rev;
 432         uint8_t ieee_fw_rev[2];
 433 };
 434
 435 struct dpcd_vendor_signature {
 436         bool is_valid;
 437
 438         union dpcd_ieee_vendor_signature {
 439                 struct {
 440                         uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
 441                         uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
 442                         uint8_t ieee_hw_rev;
 443                         uint8_t ieee_fw_rev[2];
 444                 };
 445                 uint8_t raw[12];
 446         } data;
 447 };
 448
 449 struct dpcd_amd_signature {
 450         uint8_t AMD_IEEE_TxSignature_byte1;
 451         uint8_t AMD_IEEE_TxSignature_byte2;
 452         uint8_t AMD_IEEE_TxSignature_byte3;
 453         uint8_t device_id_byte1;
 454         uint8_t device_id_byte2;
 455         uint8_t zero[4];
 456         uint8_t dce_version;
 457         uint8_t dal_version_byte1;
 458         uint8_t dal_version_byte2;
 459 };
 460
 461 struct dpcd_source_backlight_set {
 462         struct  {
 463                 uint8_t byte0;
 464                 uint8_t byte1;
 465                 uint8_t byte2;
 466                 uint8_t byte3;
 467         } backlight_level_millinits;
 468
 469         struct  {
 470                 uint8_t byte0;
 471                 uint8_t byte1;
 472         } backlight_transition_time_ms;
 473 };
 474
 475 union dpcd_source_backlight_get {
 476         struct {
 477                 uint32_t backlight_millinits_peak; /* 326h */
 478                 uint32_t backlight_millinits_avg; /* 32Ah */
 479         } bytes;
 480         uint8_t raw[8];
 481 };
 482
 483 /*DPCD register of DP receiver capability field bits-*/
 484 union edp_configuration_cap {
 485         struct {
 486                 uint8_t ALT_SCRAMBLER_RESET:1;
 487                 uint8_t FRAMING_CHANGE:1;
 488                 uint8_t RESERVED:1;
 489                 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
 490                 uint8_t RESERVED2:4;
 491         } bits;
 492         uint8_t raw;
 493 };
 494
 495 union dprx_feature {
 496         struct {
 497                 uint8_t GTC_CAP:1;                             // bit 0: DP 1.3+
 498                 uint8_t SST_SPLIT_SDP_CAP:1;                   // bit 1: DP 1.4
 499                 uint8_t AV_SYNC_CAP:1;                         // bit 2: DP 1.3+
 500                 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1;       // bit 3: DP 1.3+
 501                 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1;          // bit 4: DP 1.4
 502                 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4
 503                 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1;           // bit 6: DP 1.4
 504                 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1;  // bit 7: DP 1.4
 505         } bits;
 506         uint8_t raw;
 507 };
 508
 509 union training_aux_rd_interval {
 510         struct {
 511                 uint8_t TRAINIG_AUX_RD_INTERVAL:7;
 512                 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1;
 513         } bits;
 514         uint8_t raw;
 515 };
 516
 517 /* Automated test structures */
 518 union test_request {
 519         struct {
 520         uint8_t LINK_TRAINING                :1;
 521         uint8_t LINK_TEST_PATTRN             :1;
 522         uint8_t EDID_READ                    :1;
 523         uint8_t PHY_TEST_PATTERN             :1;
 524         uint8_t RESERVED                     :1;
 525         uint8_t AUDIO_TEST_PATTERN           :1;
 526         uint8_t TEST_AUDIO_DISABLED_VIDEO    :1;
 527         } bits;
 528         uint8_t raw;
 529 };
 530
 531 union test_response {
 532         struct {
 533                 uint8_t ACK         :1;
 534                 uint8_t NO_ACK      :1;
 535                 uint8_t EDID_CHECKSUM_WRITE:1;
 536                 uint8_t RESERVED    :5;
 537         } bits;
 538         uint8_t raw;
 539 };
 540
 541 union phy_test_pattern {
 542         struct {
 543                 /* DpcdPhyTestPatterns. This field is 2 bits for DP1.1
 544                  * and 3 bits for DP1.2.
 545                  */
 546                 uint8_t PATTERN     :3;
 547                 /* BY speci, bit7:2 is 0 for DP1.1. */
 548                 uint8_t RESERVED    :5;
 549         } bits;
 550         uint8_t raw;
 551 };
 552
 553 /* States of Compliance Test Specification (CTS DP1.2). */
 554 union compliance_test_state {
 555         struct {
 556                 unsigned char STEREO_3D_RUNNING        : 1;
 557                 unsigned char RESERVED                 : 7;
 558         } bits;
 559         unsigned char raw;
 560 };
 561
 562 union link_test_pattern {
 563         struct {
 564                 /* dpcd_link_test_patterns */
 565                 unsigned char PATTERN :2;
 566                 unsigned char RESERVED:6;
 567         } bits;
 568         unsigned char raw;
 569 };
 570
 571 union test_misc {
 572         struct dpcd_test_misc_bits {
 573                 unsigned char SYNC_CLOCK  :1;
 574                 /* dpcd_test_color_format */
 575                 unsigned char CLR_FORMAT  :2;
 576                 /* dpcd_test_dyn_range */
 577                 unsigned char DYN_RANGE   :1;
 578                 unsigned char YCBCR_COEFS :1;
 579                 /* dpcd_test_bit_depth */
 580                 unsigned char BPC         :3;
 581         } bits;
 582         unsigned char raw;
 583 };
 584
 585 union audio_test_mode {
 586         struct {
 587                 unsigned char sampling_rate   :4;
 588                 unsigned char channel_count   :4;
 589         } bits;
 590         unsigned char raw;
 591 };
 592
 593 union audio_test_pattern_period {
 594         struct {
 595                 unsigned char pattern_period   :4;
 596                 unsigned char reserved         :4;
 597         } bits;
 598         unsigned char raw;
 599 };
 600
 601 struct audio_test_pattern_type {
 602         unsigned char value;
 603 };
 604
 605 struct dp_audio_test_data_flags {
 606         uint8_t test_requested  :1;
 607         uint8_t disable_video   :1;
 608 };
 609
 610 struct dp_audio_test_data {
 611
 612         struct dp_audio_test_data_flags flags;
 613         uint8_t sampling_rate;
 614         uint8_t channel_count;
 615         uint8_t pattern_type;
 616         uint8_t pattern_period[8];
 617 };
 618
 619 /* FEC capability DPCD register field bits-*/
 620 union dpcd_fec_capability {
 621         struct {
 622                 uint8_t FEC_CAPABLE:1;
 623                 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
 624                 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
 625                 uint8_t BIT_ERROR_COUNT_CAPABLE:1;
 626                 uint8_t RESERVED:4;
 627         } bits;
 628         uint8_t raw;
 629 };
 630
 631 /* DSC capability DPCD register field bits-*/
 632 struct dpcd_dsc_support {
 633         uint8_t DSC_SUPPORT             :1;
 634         uint8_t DSC_PASSTHROUGH_SUPPORT :1;
 635         uint8_t RESERVED                :6;
 636 };
 637
 638 struct dpcd_dsc_algorithm_revision {
 639         uint8_t DSC_VERSION_MAJOR       :4;
 640         uint8_t DSC_VERSION_MINOR       :4;
 641 };
 642
 643 struct dpcd_dsc_rc_buffer_block_size {
 644         uint8_t RC_BLOCK_BUFFER_SIZE    :2;
 645         uint8_t RESERVED                :6;
 646 };
 647
 648 struct dpcd_dsc_slice_capability1 {
 649         uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE        :1;
 650         uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE       :1;
 651         uint8_t RESERVED                                :1;
 652         uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE      :1;
 653         uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE       :1;
 654         uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE     :1;
 655         uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE       :1;
 656         uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE    :1;
 657 };
 658
 659 struct dpcd_dsc_line_buffer_bit_depth {
 660         uint8_t LINE_BUFFER_BIT_DEPTH   :4;
 661         uint8_t RESERVED                :4;
 662 };
 663
 664 struct dpcd_dsc_block_prediction_support {
 665         uint8_t BLOCK_PREDICTION_SUPPORT:1;
 666         uint8_t RESERVED                :7;
 667 };
 668
 669 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor {
 670         uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW        :7;
 671         uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH       :7;
 672         uint8_t RESERVED                                                        :2;
 673 };
 674
 675 struct dpcd_dsc_decoder_color_format_capabilities {
 676         uint8_t RGB_SUPPORT                     :1;
 677         uint8_t Y_CB_CR_444_SUPPORT             :1;
 678         uint8_t Y_CB_CR_SIMPLE_422_SUPPORT      :1;
 679         uint8_t Y_CB_CR_NATIVE_422_SUPPORT      :1;
 680         uint8_t Y_CB_CR_NATIVE_420_SUPPORT      :1;
 681         uint8_t RESERVED                        :3;
 682 };
 683
 684 struct dpcd_dsc_decoder_color_depth_capabilities {
 685         uint8_t RESERVED0                       :1;
 686         uint8_t EIGHT_BITS_PER_COLOR_SUPPORT    :1;
 687         uint8_t TEN_BITS_PER_COLOR_SUPPORT      :1;
 688         uint8_t TWELVE_BITS_PER_COLOR_SUPPORT   :1;
 689         uint8_t RESERVED1                       :4;
 690 };
 691
 692 struct dpcd_peak_dsc_throughput_dsc_sink {
 693         uint8_t THROUGHPUT_MODE_0:4;
 694         uint8_t THROUGHPUT_MODE_1:4;
 695 };
 696
 697 struct dpcd_dsc_slice_capabilities_2 {
 698         uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE      :1;
 699         uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE       :1;
 700         uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE   :1;
 701         uint8_t RESERVED                                :5;
 702 };
 703
 704 struct dpcd_bits_per_pixel_increment{
 705         uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED   :3;
 706         uint8_t RESERVED                                :5;
 707 };
 708 union dpcd_dsc_basic_capabilities {
 709         struct {
 710                 struct dpcd_dsc_support dsc_support;
 711                 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision;
 712                 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size;
 713                 uint8_t dsc_rc_buffer_size;
 714                 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1;
 715                 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth;
 716                 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support;
 717                 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor;
 718                 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities;
 719                 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities;
 720                 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink;
 721                 uint8_t dsc_maximum_slice_width;
 722                 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2;
 723                 uint8_t reserved;
 724                 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment;
 725         } fields;
 726         uint8_t raw[16];
 727 };
 728
 729 union dpcd_dsc_ext_capabilities {
 730         struct {
 731                 uint8_t BRANCH_OVERALL_THROUGHPUT_0;
 732                 uint8_t BRANCH_OVERALL_THROUGHPUT_1;
 733                 uint8_t BRANCH_MAX_LINE_WIDTH;
 734         } fields;
 735         uint8_t raw[3];
 736 };
 737
 738 struct dpcd_dsc_capabilities {
 739         union dpcd_dsc_basic_capabilities dsc_basic_caps;
 740         union dpcd_dsc_ext_capabilities dsc_ext_caps;
 741 };
 742
 743 /* These parameters are from PSR capabilities reported by Sink DPCD */
 744 struct psr_caps {
 745         unsigned char psr_version;
 746         unsigned int psr_rfb_setup_time;
 747         bool psr_exit_link_training_required;
 748 };
 749
 750 #endif /* DC_DP_TYPES_H */