drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #ifndef DC_DDC_TYPES_H_
  26 #define DC_DDC_TYPES_H_
  27
  28 enum aux_transaction_type {
  29         AUX_TRANSACTION_TYPE_DP,
  30         AUX_TRANSACTION_TYPE_I2C
  31 };
  32
  33
  34 enum i2caux_transaction_action {
  35         I2CAUX_TRANSACTION_ACTION_I2C_WRITE = 0x00,
  36         I2CAUX_TRANSACTION_ACTION_I2C_READ = 0x10,
  37         I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 0x20,
  38
  39         I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT = 0x40,
  40         I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT = 0x50,
  41         I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT = 0x60,
  42
  43         I2CAUX_TRANSACTION_ACTION_DP_WRITE = 0x80,
  44         I2CAUX_TRANSACTION_ACTION_DP_READ = 0x90
  45 };
  46
  47 struct aux_request_transaction_data {
  48         enum aux_transaction_type type;
  49         enum i2caux_transaction_action action;
  50         /* 20-bit AUX channel transaction address */
  51         uint32_t address;
  52         /* delay, in 100-microsecond units */
  53         uint8_t delay;
  54         uint32_t length;
  55         uint8_t *data;
  56 };
  57
  58 enum aux_transaction_reply {
  59         AUX_TRANSACTION_REPLY_AUX_ACK = 0x00,
  60         AUX_TRANSACTION_REPLY_AUX_NACK = 0x01,
  61         AUX_TRANSACTION_REPLY_AUX_DEFER = 0x02,
  62         AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK = 0x04,
  63         AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER = 0x08,
  64
  65         AUX_TRANSACTION_REPLY_I2C_ACK = 0x00,
  66         AUX_TRANSACTION_REPLY_I2C_NACK = 0x10,
  67         AUX_TRANSACTION_REPLY_I2C_DEFER = 0x20,
  68
  69         AUX_TRANSACTION_REPLY_HPD_DISCON = 0x40,
  70
  71         AUX_TRANSACTION_REPLY_INVALID = 0xFF
  72 };
  73
  74 struct aux_reply_transaction_data {
  75         enum aux_transaction_reply status;
  76         uint32_t length;
  77         uint8_t *data;
  78 };
  79
  80 struct i2c_payload {
  81         bool write;
  82         uint8_t address;
  83         uint32_t length;
  84         uint8_t *data;
  85 };
  86
  87 enum i2c_command_engine {
  88         I2C_COMMAND_ENGINE_DEFAULT,
  89         I2C_COMMAND_ENGINE_SW,
  90         I2C_COMMAND_ENGINE_HW
  91 };
  92
  93 struct i2c_command {
  94         struct i2c_payload *payloads;
  95         uint8_t number_of_payloads;
  96
  97         enum i2c_command_engine engine;
  98
  99         /* expressed in KHz
 100          * zero means "use default value" */
 101         uint32_t speed;
 102 };
 103
 104 struct gpio_ddc_hw_info {
 105         bool hw_supported;
 106         uint32_t ddc_channel;
 107 };
 108
 109 struct ddc {
 110         struct gpio *pin_data;
 111         struct gpio *pin_clock;
 112         struct gpio_ddc_hw_info hw_info;
 113         struct dc_context *ctx;
 114 };
 115
 116 union ddc_wa {
 117         struct {
 118                 uint32_t DP_SKIP_POWER_OFF:1;
 119                 uint32_t DP_AUX_POWER_UP_WA_DELAY:1;
 120         } bits;
 121         uint32_t raw;
 122 };
 123
 124 struct ddc_flags {
 125         uint8_t EDID_QUERY_DONE_ONCE:1;
 126         uint8_t IS_INTERNAL_DISPLAY:1;
 127         uint8_t FORCE_READ_REPEATED_START:1;
 128         uint8_t EDID_STRESS_READ:1;
 129
 130 };
 131
 132 enum ddc_transaction_type {
 133         DDC_TRANSACTION_TYPE_NONE = 0,
 134         DDC_TRANSACTION_TYPE_I2C,
 135         DDC_TRANSACTION_TYPE_I2C_OVER_AUX,
 136         DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER,
 137         DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER
 138 };
 139
 140 enum display_dongle_type {
 141         DISPLAY_DONGLE_NONE = 0,
 142         /* Active converter types*/
 143         DISPLAY_DONGLE_DP_VGA_CONVERTER,
 144         DISPLAY_DONGLE_DP_DVI_CONVERTER,
 145         DISPLAY_DONGLE_DP_HDMI_CONVERTER,
 146         /* DP-HDMI/DVI passive dongles (Type 1 and Type 2)*/
 147         DISPLAY_DONGLE_DP_DVI_DONGLE,
 148         DISPLAY_DONGLE_DP_HDMI_DONGLE,
 149         /* Other types of dongle*/
 150         DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE,
 151 };
 152
 153 struct ddc_service {
 154         struct ddc *ddc_pin;
 155         struct ddc_flags flags;
 156         union ddc_wa wa;
 157         enum ddc_transaction_type transaction_type;
 158         enum display_dongle_type dongle_type;
 159         struct dc_context *ctx;
 160         struct dc_link *link;
 161
 162         uint32_t address;
 163         uint32_t edid_buf_len;
 164         uint8_t edid_buf[DC_MAX_EDID_BUFFER_SIZE];
 165 };
 166
 167 #endif /* DC_DDC_TYPES_H_ */