2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #if defined(CONFIG_DRM_AMD_DC_HDCP)
33 #include "hdcp_types.h"
35 #include "gpio_types.h"
36 #include "link_service_types.h"
37 #include "grph_object_ctrl_defs.h"
38 #include <inc/hw/opp.h>
40 #include "inc/hw_sequencer.h"
41 #include "inc/compressor.h"
42 #include "inc/hw/dmcu.h"
43 #include "dml/display_mode_lib.h"
45 #define DC_VER "3.2.87"
47 #define MAX_SURFACES 3
50 #define MAX_SINKS_PER_LINK 4
52 /*******************************************************************************
53 * Display Core Interfaces
54 ******************************************************************************/
57 struct dmcu_version dmcu_version;
60 enum dp_protocol_version {
65 DC_PLANE_TYPE_INVALID,
66 DC_PLANE_TYPE_DCE_RGB,
67 DC_PLANE_TYPE_DCE_UNDERLAY,
68 DC_PLANE_TYPE_DCN_UNIVERSAL,
72 enum dc_plane_type type;
73 uint32_t blends_with_above : 1;
74 uint32_t blends_with_below : 1;
75 uint32_t per_pixel_alpha : 1;
77 uint32_t argb8888 : 1;
82 } pixel_format_support;
83 // max upscaling factor x1000
84 // upscaling factors are always >= 1
85 // for example, 1080p -> 8K is 4.0, or 4000 raw value
91 // max downscale factor x1000
92 // downscale factors are always <= 1
93 // for example, 8K -> 1080p is 0.25, or 250 raw value
98 } max_downscale_factor;
101 // Color management caps (DPP and MPC)
102 struct rom_curve_caps {
105 uint16_t gamma2_2 : 1;
110 struct dpp_color_caps {
111 uint16_t dcn_arch : 1; // all DCE generations treated the same
112 // input lut is different than most LUTs, just plain 256-entry lookup
113 uint16_t input_lut_shared : 1; // shared with DGAM
115 uint16_t dgam_ram : 1;
116 uint16_t post_csc : 1; // before gamut remap
117 uint16_t gamma_corr : 1;
119 // hdr_mult and gamut remap always available in DPP (in that order)
120 // 3d lut implies shaper LUT,
121 // it may be shared with MPC - check MPC:shared_3d_lut flag
122 uint16_t hw_3d_lut : 1;
123 uint16_t ogam_ram : 1; // blnd gam
125 struct rom_curve_caps dgam_rom_caps;
126 struct rom_curve_caps ogam_rom_caps;
129 struct mpc_color_caps {
130 uint16_t gamut_remap : 1;
131 uint16_t ogam_ram : 1;
133 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT
134 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance
136 struct rom_curve_caps ogam_rom_caps;
139 struct dc_color_caps {
140 struct dpp_color_caps dpp;
141 struct mpc_color_caps mpc;
145 uint32_t max_streams;
148 uint32_t max_slave_planes;
150 uint32_t max_downscale_ratio;
151 uint32_t i2c_speed_in_khz;
152 uint32_t dmdata_alloc_size;
153 unsigned int max_cursor_size;
154 unsigned int max_video_width;
155 int linear_pitch_alignment;
156 bool dcc_const_color;
160 bool post_blend_color_processing;
161 bool force_dp_tps4_for_cp2520;
162 bool disable_dp_clk_share;
163 bool psp_setup_panel_mode;
164 bool extended_aux_timeout_support;
166 enum dp_protocol_version max_dp_protocol_version;
167 struct dc_plane_cap planes[MAX_PLANES];
168 struct dc_color_caps color;
172 bool no_connect_phy_config;
174 bool skip_clock_update;
175 bool lt_early_cr_pattern;
178 struct dc_dcc_surface_param {
179 struct dc_size surface_size;
180 enum surface_pixel_format format;
181 enum swizzle_mode_values swizzle_mode;
182 enum dc_scan_direction scan;
185 struct dc_dcc_setting {
186 unsigned int max_compressed_blk_size;
187 unsigned int max_uncompressed_blk_size;
188 bool independent_64b_blks;
191 struct dc_surface_dcc_cap {
194 struct dc_dcc_setting rgb;
198 struct dc_dcc_setting luma;
199 struct dc_dcc_setting chroma;
204 bool const_color_support;
207 struct dc_static_screen_params {
214 unsigned int num_frames;
218 /* Surface update type is used by dc_update_surfaces_and_stream
219 * The update type is determined at the very beginning of the function based
220 * on parameters passed in and decides how much programming (or updating) is
221 * going to be done during the call.
223 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
224 * logical calculations or hardware register programming. This update MUST be
225 * ISR safe on windows. Currently fast update will only be used to flip surface
228 * UPDATE_TYPE_MED is used for slower updates which require significant hw
229 * re-programming however do not affect bandwidth consumption or clock
230 * requirements. At present, this is the level at which front end updates
231 * that do not require us to run bw_calcs happen. These are in/out transfer func
232 * updates, viewport offset changes, recout size changes and pixel depth changes.
233 * This update can be done at ISR, but we want to minimize how often this happens.
235 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
236 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
237 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
238 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
239 * a full update. This cannot be done at ISR level and should be a rare event.
240 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
241 * underscan we don't expect to see this call at all.
244 enum surface_update_type {
245 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
246 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
247 UPDATE_TYPE_FULL, /* may need to shuffle resources */
250 /* Forward declaration*/
252 struct dc_plane_state;
256 struct dc_cap_funcs {
257 bool (*get_dcc_compression_cap)(const struct dc *dc,
258 const struct dc_dcc_surface_param *input,
259 struct dc_surface_dcc_cap *output);
262 struct link_training_settings;
265 /* Structure to hold configuration flags set by dm at dc creation. */
268 bool disable_disp_pll_sharing;
270 bool optimize_edp_link_rate;
271 bool disable_fractional_pwm;
272 bool allow_seamless_boot_optimization;
273 bool power_down_display_on_boot;
274 bool edp_not_connected;
277 bool allow_lttpr_non_transparent_mode;
278 bool multi_mon_pp_mclk_switch;
283 enum visual_confirm {
284 VISUAL_CONFIRM_DISABLE = 0,
285 VISUAL_CONFIRM_SURFACE = 1,
286 VISUAL_CONFIRM_HDR = 2,
287 VISUAL_CONFIRM_MPCTREE = 4,
288 VISUAL_CONFIRM_PSR = 5,
294 DCC_HALF_REQ_DISALBE = 2,
297 enum pipe_split_policy {
298 MPC_SPLIT_DYNAMIC = 0,
300 MPC_SPLIT_AVOID_MULT_DISP = 2,
303 enum wm_report_mode {
304 WM_REPORT_DEFAULT = 0,
305 WM_REPORT_OVERRIDE = 1,
308 dtm_level_p0 = 0,/*highest voltage*/
312 dtm_level_p4,/*when active_display_count = 0*/
316 DCN_PWR_STATE_UNKNOWN = -1,
317 DCN_PWR_STATE_MISSION_MODE = 0,
318 DCN_PWR_STATE_LOW_POWER = 3,
322 * For any clocks that may differ per pipe
323 * only the max is stored in this structure
330 int dcfclk_deep_sleep_khz;
334 bool p_state_change_support;
335 enum dcn_pwr_state pwr_state;
337 * Elements below are not compared for the purposes of
338 * optimization required
340 bool prev_p_state_change_support;
341 enum dtm_pstate dtm_level;
342 int max_supported_dppclk_khz;
343 int max_supported_dispclk_khz;
344 int bw_dppclk_khz; /*a copy of dppclk_khz*/
348 struct dc_bw_validation_profile {
351 unsigned long long total_ticks;
352 unsigned long long voltage_level_ticks;
353 unsigned long long watermark_ticks;
354 unsigned long long rq_dlg_ticks;
356 unsigned long long total_count;
357 unsigned long long skip_fast_count;
358 unsigned long long skip_pass_count;
359 unsigned long long skip_fail_count;
362 #define BW_VAL_TRACE_SETUP() \
363 unsigned long long end_tick = 0; \
364 unsigned long long voltage_level_tick = 0; \
365 unsigned long long watermark_tick = 0; \
366 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
367 dm_get_timestamp(dc->ctx) : 0
369 #define BW_VAL_TRACE_COUNT() \
370 if (dc->debug.bw_val_profile.enable) \
371 dc->debug.bw_val_profile.total_count++
373 #define BW_VAL_TRACE_SKIP(status) \
374 if (dc->debug.bw_val_profile.enable) { \
375 if (!voltage_level_tick) \
376 voltage_level_tick = dm_get_timestamp(dc->ctx); \
377 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
380 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
381 if (dc->debug.bw_val_profile.enable) \
382 voltage_level_tick = dm_get_timestamp(dc->ctx)
384 #define BW_VAL_TRACE_END_WATERMARKS() \
385 if (dc->debug.bw_val_profile.enable) \
386 watermark_tick = dm_get_timestamp(dc->ctx)
388 #define BW_VAL_TRACE_FINISH() \
389 if (dc->debug.bw_val_profile.enable) { \
390 end_tick = dm_get_timestamp(dc->ctx); \
391 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
392 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
393 if (watermark_tick) { \
394 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
395 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
399 struct dc_debug_options {
400 enum visual_confirm visual_confirm;
406 bool validation_trace;
407 bool bandwidth_calcs_trace;
408 int max_downscale_src_width;
410 /* stutter efficiency related */
411 bool disable_stutter;
413 enum dcc_option disable_dcc;
414 enum pipe_split_policy pipe_split_policy;
415 bool force_single_disp_pipe_split;
416 bool voltage_align_fclk;
418 bool disable_dfs_bypass;
419 bool disable_dpp_power_gate;
420 bool disable_hubp_power_gate;
421 bool disable_dsc_power_gate;
422 int dsc_min_slice_height_override;
423 int dsc_bpp_increment_div;
424 bool native422_support;
425 bool disable_pplib_wm_range;
426 enum wm_report_mode pplib_wm_report_mode;
427 unsigned int min_disp_clk_khz;
428 unsigned int min_dpp_clk_khz;
429 int sr_exit_time_dpm0_ns;
430 int sr_enter_plus_exit_time_dpm0_ns;
432 int sr_enter_plus_exit_time_ns;
433 int urgent_latency_ns;
434 uint32_t underflow_assert_delay_us;
435 int percent_of_ideal_drambw;
436 int dram_clock_change_latency_ns;
437 bool optimized_watermark;
439 bool disable_pplib_clock_request;
440 bool disable_clock_gate;
441 bool disable_mem_low_power;
444 bool force_abm_enable;
445 bool disable_stereo_support;
447 bool performance_trace;
448 bool az_endpoint_mute_only;
449 bool always_use_regamma;
450 bool p010_mpo_support;
451 bool recovery_enabled;
452 bool avoid_vbios_exec_table;
453 bool scl_reset_length10;
455 bool skip_detection_link_training;
456 bool remove_disconnect_edp;
457 unsigned int force_odm_combine; //bit vector based on otg inst
458 unsigned int force_fclk_khz;
459 bool disable_tri_buf;
460 bool dmub_offload_enabled;
461 bool dmcub_emulation;
462 bool dmub_command_table; /* for testing only */
463 struct dc_bw_validation_profile bw_val_profile;
465 bool disable_48mhz_pwrdwn;
466 /* This forces a hard min on the DCFCLK requested to SMU/PP
467 * watermarks are not affected.
469 unsigned int force_min_dcfclk_mhz;
470 bool disable_timing_sync;
472 int force_clock_mode;/*every mode change.*/
474 bool disable_dram_clock_change_vactive_support;
475 bool validate_dml_output;
476 bool enable_dmcub_surface_flip;
477 bool usbc_combo_phy_reset_wa;
479 bool enable_dram_clock_change_one_display_vactive;
482 struct dc_debug_data {
483 uint32_t ltFailCount;
484 uint32_t i2cErrorCount;
485 uint32_t auxErrorCount;
488 struct dc_phy_addr_space_config {
501 uint64_t page_table_start_addr;
502 uint64_t page_table_end_addr;
503 uint64_t page_table_base_addr;
508 uint64_t page_table_default_page_addr;
511 struct dc_virtual_addr_space_config {
512 uint64_t page_table_base_addr;
513 uint64_t page_table_start_addr;
514 uint64_t page_table_end_addr;
515 uint32_t page_table_block_size_in_bytes;
516 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
519 struct dc_bounding_box_overrides {
521 int sr_enter_plus_exit_time_ns;
522 int urgent_latency_ns;
523 int percent_of_ideal_drambw;
524 int dram_clock_change_latency_ns;
525 int dummy_clock_change_latency_ns;
526 /* This forces a hard min on the DCFCLK we use
527 * for DML. Unlike the debug option for forcing
528 * DCFCLK, this override affects watermark calculations
534 struct resource_pool;
536 struct gpu_info_soc_bounding_box_v1_0;
538 struct dc_versions versions;
540 struct dc_cap_funcs cap_funcs;
541 struct dc_config config;
542 struct dc_debug_options debug;
543 struct dc_bounding_box_overrides bb_overrides;
544 struct dc_bug_wa work_arounds;
545 struct dc_context *ctx;
546 struct dc_phy_addr_space_config vm_pa_config;
549 struct dc_link *links[MAX_PIPES * 2];
551 struct dc_state *current_state;
552 struct resource_pool *res_pool;
554 struct clk_mgr *clk_mgr;
556 /* Display Engine Clock levels */
557 struct dm_pp_clock_levels sclk_lvls;
559 /* Inputs into BW and WM calculations. */
560 struct bw_calcs_dceip *bw_dceip;
561 struct bw_calcs_vbios *bw_vbios;
562 #ifdef CONFIG_DRM_AMD_DC_DCN
563 struct dcn_soc_bounding_box *dcn_soc;
564 struct dcn_ip_params *dcn_ip;
565 struct display_mode_lib dml;
569 struct hw_sequencer_funcs hwss;
570 struct dce_hwseq *hwseq;
572 /* Require to optimize clocks and bandwidth for added/removed planes */
573 bool optimized_required;
574 bool wm_optimized_required;
576 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
577 int optimize_seamless_boot_streams;
580 struct compressor *fbc_compressor;
582 struct dc_debug_data debug_data;
583 struct dpcd_vendor_signature vendor_signature;
585 const char *build_id;
586 struct vm_helper *vm_helper;
587 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
590 enum frame_buffer_mode {
591 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
592 FRAME_BUFFER_MODE_ZFB_ONLY,
593 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
596 struct dchub_init_data {
597 int64_t zfb_phys_addr_base;
598 int64_t zfb_mc_base_addr;
599 uint64_t zfb_size_in_byte;
600 enum frame_buffer_mode fb_mode;
601 bool dchub_initialzied;
602 bool dchub_info_valid;
605 struct dc_init_data {
606 struct hw_asic_id asic_id;
607 void *driver; /* ctx */
608 struct cgs_device *cgs_device;
609 struct dc_bounding_box_overrides bb_overrides;
611 int num_virtual_links;
613 * If 'vbios_override' not NULL, it will be called instead
614 * of the real VBIOS. Intended use is Diagnostics on FPGA.
616 struct dc_bios *vbios_override;
617 enum dce_environment dce_environment;
619 struct dmub_offload_funcs *dmub_if;
620 struct dc_reg_helper_state *dmub_offload;
622 struct dc_config flags;
626 * gpu_info FW provided soc bounding box struct or 0 if not
629 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
630 struct dpcd_vendor_signature vendor_signature;
633 struct dc_callback_init {
634 #ifdef CONFIG_DRM_AMD_DC_HDCP
635 struct cp_psp cp_psp;
641 struct dc *dc_create(const struct dc_init_data *init_params);
642 void dc_hardware_init(struct dc *dc);
644 int dc_get_vmid_use_vector(struct dc *dc);
645 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
646 /* Returns the number of vmids supported */
647 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
648 void dc_init_callbacks(struct dc *dc,
649 const struct dc_callback_init *init_params);
650 void dc_deinit_callbacks(struct dc *dc);
651 void dc_destroy(struct dc **dc);
653 /*******************************************************************************
655 ******************************************************************************/
658 TRANSFER_FUNC_POINTS = 1025
661 struct dc_hdr_static_metadata {
662 /* display chromaticities and white point in units of 0.00001 */
663 unsigned int chromaticity_green_x;
664 unsigned int chromaticity_green_y;
665 unsigned int chromaticity_blue_x;
666 unsigned int chromaticity_blue_y;
667 unsigned int chromaticity_red_x;
668 unsigned int chromaticity_red_y;
669 unsigned int chromaticity_white_point_x;
670 unsigned int chromaticity_white_point_y;
672 uint32_t min_luminance;
673 uint32_t max_luminance;
674 uint32_t maximum_content_light_level;
675 uint32_t maximum_frame_average_light_level;
678 enum dc_transfer_func_type {
680 TF_TYPE_DISTRIBUTED_POINTS,
685 struct dc_transfer_func_distributed_points {
686 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
687 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
688 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
690 uint16_t end_exponent;
691 uint16_t x_point_at_y1_red;
692 uint16_t x_point_at_y1_green;
693 uint16_t x_point_at_y1_blue;
696 enum dc_transfer_func_predefined {
697 TRANSFER_FUNCTION_SRGB,
698 TRANSFER_FUNCTION_BT709,
699 TRANSFER_FUNCTION_PQ,
700 TRANSFER_FUNCTION_LINEAR,
701 TRANSFER_FUNCTION_UNITY,
702 TRANSFER_FUNCTION_HLG,
703 TRANSFER_FUNCTION_HLG12,
704 TRANSFER_FUNCTION_GAMMA22,
705 TRANSFER_FUNCTION_GAMMA24,
706 TRANSFER_FUNCTION_GAMMA26
710 struct dc_transfer_func {
711 struct kref refcount;
712 enum dc_transfer_func_type type;
713 enum dc_transfer_func_predefined tf;
714 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
715 uint32_t sdr_ref_white_level;
716 struct dc_context *ctx;
718 struct pwl_params pwl;
719 struct dc_transfer_func_distributed_points tf_pts;
724 union dc_3dlut_state {
726 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
727 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
728 uint32_t rmu_mux_num:3; /*index of mux to use*/
729 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
730 uint32_t mpc_rmu1_mux:4;
731 uint32_t mpc_rmu2_mux:4;
732 uint32_t reserved:15;
739 struct kref refcount;
740 struct tetrahedral_params lut_3d;
741 struct fixed31_32 hdr_multiplier;
742 union dc_3dlut_state state;
743 struct dc_context *ctx;
746 * This structure is filled in by dc_surface_get_status and contains
747 * the last requested address and the currently active address so the called
748 * can determine if there are any outstanding flips
750 struct dc_plane_status {
751 struct dc_plane_address requested_address;
752 struct dc_plane_address current_address;
753 bool is_flip_pending;
757 union surface_update_flags {
760 uint32_t addr_update:1;
762 uint32_t dcc_change:1;
763 uint32_t color_space_change:1;
764 uint32_t horizontal_mirror_change:1;
765 uint32_t per_pixel_alpha_change:1;
766 uint32_t global_alpha_change:1;
768 uint32_t rotation_change:1;
769 uint32_t swizzle_change:1;
770 uint32_t scaling_change:1;
771 uint32_t position_change:1;
772 uint32_t in_transfer_func_change:1;
773 uint32_t input_csc_change:1;
774 uint32_t coeff_reduction_change:1;
775 uint32_t output_tf_change:1;
776 uint32_t pixel_format_change:1;
777 uint32_t plane_size_change:1;
778 uint32_t gamut_remap_change:1;
781 uint32_t new_plane:1;
782 uint32_t bpp_change:1;
783 uint32_t gamma_change:1;
784 uint32_t bandwidth_change:1;
785 uint32_t clock_change:1;
786 uint32_t stereo_format_change:1;
787 uint32_t full_update:1;
793 struct dc_plane_state {
794 struct dc_plane_address address;
795 struct dc_plane_flip_time time;
796 bool triplebuffer_flips;
797 struct scaling_taps scaling_quality;
798 struct rect src_rect;
799 struct rect dst_rect;
800 struct rect clip_rect;
802 struct plane_size plane_size;
803 union dc_tiling_info tiling_info;
805 struct dc_plane_dcc_param dcc;
807 struct dc_gamma *gamma_correction;
808 struct dc_transfer_func *in_transfer_func;
809 struct dc_bias_and_scale *bias_and_scale;
810 struct dc_csc_transform input_csc_color_matrix;
811 struct fixed31_32 coeff_reduction_factor;
812 struct fixed31_32 hdr_mult;
813 struct colorspace_transform gamut_remap_matrix;
815 // TODO: No longer used, remove
816 struct dc_hdr_static_metadata hdr_static_ctx;
818 enum dc_color_space color_space;
820 struct dc_3dlut *lut3d_func;
821 struct dc_transfer_func *in_shaper_func;
822 struct dc_transfer_func *blend_tf;
824 enum surface_pixel_format format;
825 enum dc_rotation_angle rotation;
826 enum plane_stereo_format stereo_format;
828 bool is_tiling_rotated;
829 bool per_pixel_alpha;
831 int global_alpha_value;
834 bool horizontal_mirror;
837 union surface_update_flags update_flags;
838 /* private to DC core */
839 struct dc_plane_status status;
840 struct dc_context *ctx;
842 /* HACK: Workaround for forcing full reprogramming under some conditions */
843 bool force_full_update;
845 /* private to dc_surface.c */
846 enum dc_irq_source irq_source;
847 struct kref refcount;
850 struct dc_plane_info {
851 struct plane_size plane_size;
852 union dc_tiling_info tiling_info;
853 struct dc_plane_dcc_param dcc;
854 enum surface_pixel_format format;
855 enum dc_rotation_angle rotation;
856 enum plane_stereo_format stereo_format;
857 enum dc_color_space color_space;
858 bool horizontal_mirror;
860 bool per_pixel_alpha;
862 int global_alpha_value;
863 bool input_csc_enabled;
867 struct dc_scaling_info {
868 struct rect src_rect;
869 struct rect dst_rect;
870 struct rect clip_rect;
871 struct scaling_taps scaling_quality;
874 struct dc_surface_update {
875 struct dc_plane_state *surface;
877 /* isr safe update parameters. null means no updates */
878 const struct dc_flip_addrs *flip_addr;
879 const struct dc_plane_info *plane_info;
880 const struct dc_scaling_info *scaling_info;
881 struct fixed31_32 hdr_mult;
882 /* following updates require alloc/sleep/spin that is not isr safe,
883 * null means no updates
885 const struct dc_gamma *gamma;
886 const struct dc_transfer_func *in_transfer_func;
888 const struct dc_csc_transform *input_csc_color_matrix;
889 const struct fixed31_32 *coeff_reduction_factor;
890 const struct dc_transfer_func *func_shaper;
891 const struct dc_3dlut *lut3d_func;
892 const struct dc_transfer_func *blend_tf;
893 const struct colorspace_transform *gamut_remap_matrix;
897 * Create a new surface with default parameters;
899 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
900 const struct dc_plane_status *dc_plane_get_status(
901 const struct dc_plane_state *plane_state);
903 void dc_plane_state_retain(struct dc_plane_state *plane_state);
904 void dc_plane_state_release(struct dc_plane_state *plane_state);
906 void dc_gamma_retain(struct dc_gamma *dc_gamma);
907 void dc_gamma_release(struct dc_gamma **dc_gamma);
908 struct dc_gamma *dc_create_gamma(void);
910 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
911 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
912 struct dc_transfer_func *dc_create_transfer_func(void);
914 struct dc_3dlut *dc_create_3dlut_func(void);
915 void dc_3dlut_func_release(struct dc_3dlut *lut);
916 void dc_3dlut_func_retain(struct dc_3dlut *lut);
918 * This structure holds a surface address. There could be multiple addresses
919 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
920 * as frame durations and DCC format can also be set.
922 struct dc_flip_addrs {
923 struct dc_plane_address address;
924 unsigned int flip_timestamp_in_us;
926 /* TODO: add flip duration for FreeSync */
927 bool triplebuffer_flips;
930 bool dc_post_update_surfaces_to_stream(
933 #include "dc_stream.h"
936 * Structure to store surface/stream associations for validation
938 struct dc_validation_set {
939 struct dc_stream_state *stream;
940 struct dc_plane_state *plane_states[MAX_SURFACES];
944 bool dc_validate_seamless_boot_timing(const struct dc *dc,
945 const struct dc_sink *sink,
946 struct dc_crtc_timing *crtc_timing);
948 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
950 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
952 bool dc_set_generic_gpio_for_stereo(bool enable,
953 struct gpio_service *gpio_service);
956 * fast_validate: we return after determining if we can support the new state,
957 * but before we populate the programming info
959 enum dc_status dc_validate_global_state(
961 struct dc_state *new_ctx,
965 void dc_resource_state_construct(
967 struct dc_state *dst_ctx);
969 void dc_resource_state_copy_construct(
970 const struct dc_state *src_ctx,
971 struct dc_state *dst_ctx);
973 void dc_resource_state_copy_construct_current(
975 struct dc_state *dst_ctx);
977 void dc_resource_state_destruct(struct dc_state *context);
979 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
982 * TODO update to make it about validation sets
983 * Set up streams and links associated to drive sinks
984 * The streams parameter is an absolute set of all active streams.
987 * Phy, Encoder, Timing Generator are programmed and enabled.
988 * New streams are enabled with blank stream; no memory read.
990 bool dc_commit_state(struct dc *dc, struct dc_state *context);
993 struct dc_state *dc_create_state(struct dc *dc);
994 struct dc_state *dc_copy_state(struct dc_state *src_ctx);
995 void dc_retain_state(struct dc_state *context);
996 void dc_release_state(struct dc_state *context);
998 /*******************************************************************************
1000 ******************************************************************************/
1003 union dpcd_rev dpcd_rev;
1004 union max_lane_count max_ln_count;
1005 union max_down_spread max_down_spread;
1006 union dprx_feature dprx_feature;
1008 /* valid only for eDP v1.4 or higher*/
1009 uint8_t edp_supported_link_rates_count;
1010 enum dc_link_rate edp_supported_link_rates[8];
1012 /* dongle type (DP converter, CV smart dongle) */
1013 enum display_dongle_type dongle_type;
1014 /* branch device or sink device */
1016 /* Dongle's downstream count. */
1017 union sink_count sink_count;
1018 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
1019 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1020 struct dc_dongle_caps dongle_caps;
1022 uint32_t sink_dev_id;
1023 int8_t sink_dev_id_str[6];
1024 int8_t sink_hw_revision;
1025 int8_t sink_fw_revision[2];
1027 uint32_t branch_dev_id;
1028 int8_t branch_dev_name[6];
1029 int8_t branch_hw_revision;
1030 int8_t branch_fw_revision[2];
1032 bool allow_invalid_MSA_timing_param;
1033 bool panel_mode_edp;
1034 bool dpcd_display_control_capable;
1035 bool ext_receiver_cap_field_present;
1036 union dpcd_fec_capability fec_cap;
1037 struct dpcd_dsc_capabilities dsc_caps;
1038 struct dc_lttpr_caps lttpr_caps;
1039 struct psr_caps psr_caps;
1043 union dpcd_sink_ext_caps {
1045 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode
1046 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode.
1048 uint8_t sdr_aux_backlight_control : 1;
1049 uint8_t hdr_aux_backlight_control : 1;
1050 uint8_t reserved_1 : 2;
1052 uint8_t reserved : 3;
1057 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1058 union hdcp_rx_caps {
1063 uint8_t repeater : 1;
1064 uint8_t hdcp_capable : 1;
1065 uint8_t reserved : 6;
1073 uint8_t HDCP_CAPABLE:1;
1081 union hdcp_rx_caps rx_caps;
1082 union hdcp_bcaps bcaps;
1086 #include "dc_link.h"
1088 /*******************************************************************************
1089 * Sink Interfaces - A sink corresponds to a display output device
1090 ******************************************************************************/
1092 struct dc_container_id {
1093 // 128bit GUID in binary form
1094 unsigned char guid[16];
1095 // 8 byte port ID -> ELD.PortID
1096 unsigned int portId[2];
1097 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
1098 unsigned short manufacturerName;
1099 // 2 byte product code -> ELD.ProductCode
1100 unsigned short productCode;
1104 struct dc_sink_dsc_caps {
1105 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
1106 // 'false' if they are sink's DSC caps
1107 bool is_virtual_dpcd_dsc;
1108 struct dsc_dec_dpcd_caps dsc_dec_caps;
1111 struct dc_sink_fec_caps {
1112 bool is_rx_fec_supported;
1113 bool is_topology_fec_supported;
1117 * The sink structure contains EDID and other display device properties
1120 enum signal_type sink_signal;
1121 struct dc_edid dc_edid; /* raw edid */
1122 struct dc_edid_caps edid_caps; /* parse display caps */
1123 struct dc_container_id *dc_container_id;
1124 uint32_t dongle_max_pix_clk;
1126 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1127 bool converter_disable_audio;
1129 struct dc_sink_dsc_caps dsc_caps;
1130 struct dc_sink_fec_caps fec_caps;
1132 bool is_vsc_sdp_colorimetry_supported;
1134 /* private to DC core */
1135 struct dc_link *link;
1136 struct dc_context *ctx;
1140 /* private to dc_sink.c */
1141 // refcount must be the last member in dc_sink, since we want the
1142 // sink structure to be logically cloneable up to (but not including)
1144 struct kref refcount;
1147 void dc_sink_retain(struct dc_sink *sink);
1148 void dc_sink_release(struct dc_sink *sink);
1150 struct dc_sink_init_data {
1151 enum signal_type sink_signal;
1152 struct dc_link *link;
1153 uint32_t dongle_max_pix_clk;
1154 bool converter_disable_audio;
1155 bool sink_is_legacy;
1158 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1160 /* Newer interfaces */
1162 struct dc_plane_address address;
1163 struct dc_cursor_attributes attributes;
1167 /*******************************************************************************
1168 * Interrupt interfaces
1169 ******************************************************************************/
1170 enum dc_irq_source dc_interrupt_to_irq_source(
1174 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1175 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1176 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1177 struct dc *dc, uint32_t link_index);
1179 /*******************************************************************************
1181 ******************************************************************************/
1183 void dc_set_power_state(
1185 enum dc_acpi_cm_power_state power_state);
1186 void dc_resume(struct dc *dc);
1188 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1192 enum hdcp_message_status dc_process_hdcp_msg(
1193 enum signal_type signal,
1194 struct dc_link *link,
1195 struct hdcp_protection_message *message_info);
1197 bool dc_is_dmcu_initialized(struct dc *dc);
1199 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
1200 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1201 /*******************************************************************************
1203 ******************************************************************************/
1205 #endif /* DC_INTERFACE_H_ */