2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #include "gpio_types.h"
33 #include "link_service_types.h"
34 #include "grph_object_ctrl_defs.h"
35 #include <inc/hw/opp.h>
37 #include "inc/hw_sequencer.h"
38 #include "inc/compressor.h"
39 #include "dml/display_mode_lib.h"
41 #define DC_VER "3.1.10"
43 #define MAX_SURFACES 3
45 #define MAX_SINKS_PER_LINK 4
48 /*******************************************************************************
49 * Display Core Interfaces
50 ******************************************************************************/
55 uint32_t max_slave_planes;
57 uint32_t max_downscale_ratio;
58 uint32_t i2c_speed_in_khz;
59 unsigned int max_cursor_size;
60 unsigned int max_video_width;
66 struct dc_dcc_surface_param {
67 struct dc_size surface_size;
68 enum surface_pixel_format format;
69 enum swizzle_mode_values swizzle_mode;
70 enum dc_scan_direction scan;
73 struct dc_dcc_setting {
74 unsigned int max_compressed_blk_size;
75 unsigned int max_uncompressed_blk_size;
76 bool independent_64b_blks;
79 struct dc_surface_dcc_cap {
82 struct dc_dcc_setting rgb;
86 struct dc_dcc_setting luma;
87 struct dc_dcc_setting chroma;
92 bool const_color_support;
95 struct dc_static_screen_events {
101 /* Forward declaration*/
103 struct dc_plane_state;
106 struct dc_cap_funcs {
107 bool (*get_dcc_compression_cap)(const struct dc *dc,
108 const struct dc_dcc_surface_param *input,
109 struct dc_surface_dcc_cap *output);
112 struct dc_stream_state_funcs {
113 bool (*adjust_vmin_vmax)(struct dc *dc,
114 struct dc_stream_state **stream,
118 bool (*get_crtc_position)(struct dc *dc,
119 struct dc_stream_state **stream,
122 unsigned int *nom_v_pos);
124 bool (*set_gamut_remap)(struct dc *dc,
125 const struct dc_stream_state *stream);
127 bool (*program_csc_matrix)(struct dc *dc,
128 struct dc_stream_state *stream);
130 void (*set_static_screen_events)(struct dc *dc,
131 struct dc_stream_state **stream,
133 const struct dc_static_screen_events *events);
135 void (*set_dither_option)(struct dc_stream_state *stream,
136 enum dc_dither_option option);
138 void (*set_dpms)(struct dc *dc,
139 struct dc_stream_state *stream,
143 struct link_training_settings;
145 struct dc_link_funcs {
146 void (*set_drive_settings)(struct dc *dc,
147 struct link_training_settings *lt_settings,
148 const struct dc_link *link);
149 void (*perform_link_training)(struct dc *dc,
150 struct dc_link_settings *link_setting,
151 bool skip_video_pattern);
152 void (*set_preferred_link_settings)(struct dc *dc,
153 struct dc_link_settings *link_setting,
154 struct dc_link *link);
155 void (*enable_hpd)(const struct dc_link *link);
156 void (*disable_hpd)(const struct dc_link *link);
157 void (*set_test_pattern)(
158 struct dc_link *link,
159 enum dp_test_pattern test_pattern,
160 const struct link_training_settings *p_link_settings,
161 const unsigned char *p_custom_pattern,
162 unsigned int cust_pattern_size);
165 /* Structure to hold configuration flags set by dm at dc creation. */
168 bool disable_disp_pll_sharing;
174 DCC_HALF_REQ_DISALBE = 2,
177 enum pipe_split_policy {
178 MPC_SPLIT_DYNAMIC = 0,
180 MPC_SPLIT_AVOID_MULT_DISP = 2,
183 enum wm_report_mode {
184 WM_REPORT_DEFAULT = 0,
185 WM_REPORT_OVERRIDE = 1,
189 bool surface_visual_confirm;
195 bool validation_trace;
197 /* stutter efficiency related */
198 bool disable_stutter;
200 enum dcc_option disable_dcc;
201 enum pipe_split_policy pipe_split_policy;
202 bool force_single_disp_pipe_split;
203 bool voltage_align_fclk;
205 bool disable_dfs_bypass;
206 bool disable_dpp_power_gate;
207 bool disable_hubp_power_gate;
208 bool disable_pplib_wm_range;
209 enum wm_report_mode pplib_wm_report_mode;
210 unsigned int min_disp_clk_khz;
211 int sr_exit_time_dpm0_ns;
212 int sr_enter_plus_exit_time_dpm0_ns;
214 int sr_enter_plus_exit_time_ns;
215 int urgent_latency_ns;
216 int percent_of_ideal_drambw;
217 int dram_clock_change_latency_ns;
219 bool disable_pplib_clock_request;
220 bool disable_clock_gate;
223 bool force_abm_enable;
224 bool disable_hbup_pg;
226 bool disable_stereo_support;
228 bool performance_trace;
231 struct resource_pool;
235 struct dc_cap_funcs cap_funcs;
236 struct dc_stream_state_funcs stream_funcs;
237 struct dc_link_funcs link_funcs;
238 struct dc_config config;
239 struct dc_debug debug;
241 struct dc_context *ctx;
244 struct dc_link *links[MAX_PIPES * 2];
246 struct dc_state *current_state;
247 struct resource_pool *res_pool;
249 /* Display Engine Clock levels */
250 struct dm_pp_clock_levels sclk_lvls;
252 /* Inputs into BW and WM calculations. */
253 struct bw_calcs_dceip *bw_dceip;
254 struct bw_calcs_vbios *bw_vbios;
255 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
256 struct dcn_soc_bounding_box *dcn_soc;
257 struct dcn_ip_params *dcn_ip;
258 struct display_mode_lib dml;
262 struct hw_sequencer_funcs hwss;
263 struct dce_hwseq *hwseq;
265 /* temp store of dm_pp_display_configuration
266 * to compare to see if display config changed
268 struct dm_pp_display_configuration prev_display_config;
271 #if defined(CONFIG_DRM_AMD_DC_FBC)
272 struct compressor *fbc_compressor;
276 enum frame_buffer_mode {
277 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
278 FRAME_BUFFER_MODE_ZFB_ONLY,
279 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
282 struct dchub_init_data {
283 int64_t zfb_phys_addr_base;
284 int64_t zfb_mc_base_addr;
285 uint64_t zfb_size_in_byte;
286 enum frame_buffer_mode fb_mode;
287 bool dchub_initialzied;
288 bool dchub_info_valid;
291 struct dc_init_data {
292 struct hw_asic_id asic_id;
293 void *driver; /* ctx */
294 struct cgs_device *cgs_device;
296 int num_virtual_links;
298 * If 'vbios_override' not NULL, it will be called instead
299 * of the real VBIOS. Intended use is Diagnostics on FPGA.
301 struct dc_bios *vbios_override;
302 enum dce_environment dce_environment;
304 struct dc_config flags;
306 #if defined(CONFIG_DRM_AMD_DC_FBC)
307 uint64_t fbc_gpu_addr;
311 struct dc *dc_create(const struct dc_init_data *init_params);
313 void dc_destroy(struct dc **dc);
315 /*******************************************************************************
317 ******************************************************************************/
320 TRANSFER_FUNC_POINTS = 1025
323 // Moved here from color module for linux
324 enum color_transfer_func {
325 transfer_func_unknown,
328 transfer_func_pq2084,
329 transfer_func_pq2084_interim,
330 transfer_func_linear_0_1,
331 transfer_func_linear_0_125,
332 transfer_func_dolbyvision,
333 transfer_func_gamma_22,
334 transfer_func_gamma_26
337 struct dc_hdr_static_metadata {
338 /* display chromaticities and white point in units of 0.00001 */
339 unsigned int chromaticity_green_x;
340 unsigned int chromaticity_green_y;
341 unsigned int chromaticity_blue_x;
342 unsigned int chromaticity_blue_y;
343 unsigned int chromaticity_red_x;
344 unsigned int chromaticity_red_y;
345 unsigned int chromaticity_white_point_x;
346 unsigned int chromaticity_white_point_y;
348 uint32_t min_luminance;
349 uint32_t max_luminance;
350 uint32_t maximum_content_light_level;
351 uint32_t maximum_frame_average_light_level;
357 enum dc_transfer_func_type {
359 TF_TYPE_DISTRIBUTED_POINTS,
363 struct dc_transfer_func_distributed_points {
364 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
365 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
366 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
368 uint16_t end_exponent;
369 uint16_t x_point_at_y1_red;
370 uint16_t x_point_at_y1_green;
371 uint16_t x_point_at_y1_blue;
374 enum dc_transfer_func_predefined {
375 TRANSFER_FUNCTION_SRGB,
376 TRANSFER_FUNCTION_BT709,
377 TRANSFER_FUNCTION_PQ,
378 TRANSFER_FUNCTION_LINEAR,
381 struct dc_transfer_func {
382 struct kref refcount;
383 struct dc_transfer_func_distributed_points tf_pts;
384 enum dc_transfer_func_type type;
385 enum dc_transfer_func_predefined tf;
386 struct dc_context *ctx;
390 * This structure is filled in by dc_surface_get_status and contains
391 * the last requested address and the currently active address so the called
392 * can determine if there are any outstanding flips
394 struct dc_plane_status {
395 struct dc_plane_address requested_address;
396 struct dc_plane_address current_address;
397 bool is_flip_pending;
401 struct dc_plane_state {
402 struct dc_plane_address address;
403 struct scaling_taps scaling_quality;
404 struct rect src_rect;
405 struct rect dst_rect;
406 struct rect clip_rect;
408 union plane_size plane_size;
409 union dc_tiling_info tiling_info;
411 struct dc_plane_dcc_param dcc;
413 struct dc_gamma *gamma_correction;
414 struct dc_transfer_func *in_transfer_func;
415 struct dc_bias_and_scale *bias_and_scale;
416 struct csc_transform input_csc_color_matrix;
417 struct fixed31_32 coeff_reduction_factor;
419 // TODO: No longer used, remove
420 struct dc_hdr_static_metadata hdr_static_ctx;
422 enum dc_color_space color_space;
423 enum color_transfer_func input_tf;
425 enum surface_pixel_format format;
426 enum dc_rotation_angle rotation;
427 enum plane_stereo_format stereo_format;
429 bool per_pixel_alpha;
432 bool horizontal_mirror;
434 /* private to DC core */
435 struct dc_plane_status status;
436 struct dc_context *ctx;
438 /* private to dc_surface.c */
439 enum dc_irq_source irq_source;
440 struct kref refcount;
443 struct dc_plane_info {
444 union plane_size plane_size;
445 union dc_tiling_info tiling_info;
446 struct dc_plane_dcc_param dcc;
447 enum surface_pixel_format format;
448 enum dc_rotation_angle rotation;
449 enum plane_stereo_format stereo_format;
450 enum dc_color_space color_space;
451 enum color_transfer_func input_tf;
452 bool horizontal_mirror;
454 bool per_pixel_alpha;
455 bool input_csc_enabled;
458 struct dc_scaling_info {
459 struct rect src_rect;
460 struct rect dst_rect;
461 struct rect clip_rect;
462 struct scaling_taps scaling_quality;
465 struct dc_surface_update {
466 struct dc_plane_state *surface;
468 /* isr safe update parameters. null means no updates */
469 struct dc_flip_addrs *flip_addr;
470 struct dc_plane_info *plane_info;
471 struct dc_scaling_info *scaling_info;
473 /* following updates require alloc/sleep/spin that is not isr safe,
474 * null means no updates
476 /* gamma TO BE REMOVED */
477 struct dc_gamma *gamma;
478 struct dc_transfer_func *in_transfer_func;
480 struct csc_transform *input_csc_color_matrix;
481 struct fixed31_32 *coeff_reduction_factor;
485 * Create a new surface with default parameters;
487 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
488 const struct dc_plane_status *dc_plane_get_status(
489 const struct dc_plane_state *plane_state);
491 void dc_plane_state_retain(struct dc_plane_state *plane_state);
492 void dc_plane_state_release(struct dc_plane_state *plane_state);
494 void dc_gamma_retain(struct dc_gamma *dc_gamma);
495 void dc_gamma_release(struct dc_gamma **dc_gamma);
496 struct dc_gamma *dc_create_gamma(void);
498 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
499 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
500 struct dc_transfer_func *dc_create_transfer_func(void);
503 * This structure holds a surface address. There could be multiple addresses
504 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
505 * as frame durations and DCC format can also be set.
507 struct dc_flip_addrs {
508 struct dc_plane_address address;
510 /* TODO: add flip duration for FreeSync */
513 bool dc_post_update_surfaces_to_stream(
516 /* Surface update type is used by dc_update_surfaces_and_stream
517 * The update type is determined at the very beginning of the function based
518 * on parameters passed in and decides how much programming (or updating) is
519 * going to be done during the call.
521 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
522 * logical calculations or hardware register programming. This update MUST be
523 * ISR safe on windows. Currently fast update will only be used to flip surface
526 * UPDATE_TYPE_MED is used for slower updates which require significant hw
527 * re-programming however do not affect bandwidth consumption or clock
528 * requirements. At present, this is the level at which front end updates
529 * that do not require us to run bw_calcs happen. These are in/out transfer func
530 * updates, viewport offset changes, recout size changes and pixel depth changes.
531 * This update can be done at ISR, but we want to minimize how often this happens.
533 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
534 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
535 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
536 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
537 * a full update. This cannot be done at ISR level and should be a rare event.
538 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
539 * underscan we don't expect to see this call at all.
542 enum surface_update_type {
543 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
544 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
545 UPDATE_TYPE_FULL, /* may need to shuffle resources */
548 /*******************************************************************************
550 ******************************************************************************/
552 struct dc_stream_status {
553 int primary_otg_inst;
556 struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
559 * link this stream passes through
561 struct dc_link *link;
564 struct dc_stream_state {
565 struct dc_sink *sink;
566 struct dc_crtc_timing timing;
568 struct rect src; /* composition area */
569 struct rect dst; /* stream addressable area */
571 struct audio_info audio_info;
573 struct freesync_context freesync_ctx;
575 struct dc_hdr_static_metadata hdr_static_metadata;
576 struct dc_transfer_func *out_transfer_func;
577 struct colorspace_transform gamut_remap_matrix;
578 struct csc_transform csc_color_matrix;
580 enum signal_type output_signal;
582 enum dc_color_space output_color_space;
583 enum dc_dither_option dither_option;
585 enum view_3d_format view_format;
587 bool ignore_msa_timing_param;
588 /* TODO: custom INFO packets */
589 /* TODO: ABM info (DMCU) */
593 /* from core_stream struct */
594 struct dc_context *ctx;
596 /* used by DCP and FMT */
597 struct bit_depth_reduction_params bit_depth_params;
598 struct clamping_and_pixel_encoding_params clamping;
601 enum signal_type signal;
604 struct dc_stream_status status;
606 struct dc_cursor_attributes cursor_attributes;
608 /* from stream struct */
609 struct kref refcount;
612 struct dc_stream_update {
615 struct dc_transfer_func *out_transfer_func;
616 struct dc_hdr_static_metadata *hdr_static_metadata;
619 bool dc_is_stream_unchanged(
620 struct dc_stream_state *old_stream, struct dc_stream_state *stream);
621 bool dc_is_stream_scaling_unchanged(
622 struct dc_stream_state *old_stream, struct dc_stream_state *stream);
625 * Set up surface attributes and associate to a stream
626 * The surfaces parameter is an absolute set of all surface active for the stream.
627 * If no surfaces are provided, the stream will be blanked; no memory read.
628 * Any flip related attribute changes must be done through this interface.
631 * Surfaces attributes are programmed and configured to be composed into stream.
632 * This does not trigger a flip. No surface address is programmed.
635 bool dc_commit_planes_to_stream(
637 struct dc_plane_state **plane_states,
638 uint8_t new_plane_count,
639 struct dc_stream_state *dc_stream,
640 struct dc_state *state);
642 void dc_commit_updates_for_stream(struct dc *dc,
643 struct dc_surface_update *srf_updates,
645 struct dc_stream_state *stream,
646 struct dc_stream_update *stream_update,
647 struct dc_plane_state **plane_states,
648 struct dc_state *state);
650 * Log the current stream state.
653 const struct dc_stream_state *stream,
654 struct dal_logger *dc_logger,
655 enum dc_log_type log_type);
657 uint8_t dc_get_current_stream_count(struct dc *dc);
658 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
661 * Return the current frame counter.
663 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
665 /* TODO: Return parsed values rather than direct register read
666 * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
667 * being refactored properly to be dce-specific
669 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
670 uint32_t *v_blank_start,
671 uint32_t *v_blank_end,
672 uint32_t *h_position,
673 uint32_t *v_position);
675 enum dc_status dc_add_stream_to_ctx(
677 struct dc_state *new_ctx,
678 struct dc_stream_state *stream);
680 enum dc_status dc_remove_stream_from_ctx(
682 struct dc_state *new_ctx,
683 struct dc_stream_state *stream);
686 bool dc_add_plane_to_context(
688 struct dc_stream_state *stream,
689 struct dc_plane_state *plane_state,
690 struct dc_state *context);
692 bool dc_remove_plane_from_context(
694 struct dc_stream_state *stream,
695 struct dc_plane_state *plane_state,
696 struct dc_state *context);
698 bool dc_rem_all_planes_for_stream(
700 struct dc_stream_state *stream,
701 struct dc_state *context);
703 bool dc_add_all_planes_for_stream(
705 struct dc_stream_state *stream,
706 struct dc_plane_state * const *plane_states,
708 struct dc_state *context);
711 * Structure to store surface/stream associations for validation
713 struct dc_validation_set {
714 struct dc_stream_state *stream;
715 struct dc_plane_state *plane_states[MAX_SURFACES];
719 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
721 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
723 enum dc_status dc_validate_global_state(
725 struct dc_state *new_ctx);
728 * This function takes a stream and checks if it is guaranteed to be supported.
729 * Guaranteed means that MAX_COFUNC similar streams are supported.
732 * No hardware is programmed for call. Only validation is done.
736 void dc_resource_state_construct(
738 struct dc_state *dst_ctx);
740 void dc_resource_state_copy_construct(
741 const struct dc_state *src_ctx,
742 struct dc_state *dst_ctx);
744 void dc_resource_state_copy_construct_current(
746 struct dc_state *dst_ctx);
748 void dc_resource_state_destruct(struct dc_state *context);
751 * TODO update to make it about validation sets
752 * Set up streams and links associated to drive sinks
753 * The streams parameter is an absolute set of all active streams.
756 * Phy, Encoder, Timing Generator are programmed and enabled.
757 * New streams are enabled with blank stream; no memory read.
759 bool dc_commit_state(struct dc *dc, struct dc_state *context);
762 * Set up streams and links associated to drive sinks
763 * The streams parameter is an absolute set of all active streams.
766 * Phy, Encoder, Timing Generator are programmed and enabled.
767 * New streams are enabled with blank stream; no memory read.
770 * Enable stereo when commit_streams is not required,
771 * for example, frame alternate.
773 bool dc_enable_stereo(
775 struct dc_state *context,
776 struct dc_stream_state *streams[],
777 uint8_t stream_count);
780 * Create a new default stream for the requested sink
782 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
784 void dc_stream_retain(struct dc_stream_state *dc_stream);
785 void dc_stream_release(struct dc_stream_state *dc_stream);
787 struct dc_stream_status *dc_stream_get_status(
788 struct dc_stream_state *dc_stream);
790 enum surface_update_type dc_check_update_surfaces_for_stream(
792 struct dc_surface_update *updates,
794 struct dc_stream_update *stream_update,
795 const struct dc_stream_status *stream_status);
798 struct dc_state *dc_create_state(void);
799 void dc_retain_state(struct dc_state *context);
800 void dc_release_state(struct dc_state *context);
802 /*******************************************************************************
804 ******************************************************************************/
807 union dpcd_rev dpcd_rev;
808 union max_lane_count max_ln_count;
809 union max_down_spread max_down_spread;
811 /* dongle type (DP converter, CV smart dongle) */
812 enum display_dongle_type dongle_type;
813 /* Dongle's downstream count. */
814 union sink_count sink_count;
815 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
816 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
817 struct dc_dongle_caps dongle_caps;
819 uint32_t sink_dev_id;
820 uint32_t branch_dev_id;
821 int8_t branch_dev_name[6];
822 int8_t branch_hw_revision;
824 bool allow_invalid_MSA_timing_param;
826 bool dpcd_display_control_capable;
829 struct dc_link_status {
830 struct dpcd_caps *dpcd_caps;
833 /* DP MST stream allocation (payload bandwidth number) */
834 struct link_mst_stream_allocation {
836 const struct stream_encoder *stream_enc;
837 /* associate DRM payload table with DC stream encoder */
839 /* number of slots required for the DP stream in transport packet */
843 /* DP MST stream allocation table */
844 struct link_mst_stream_allocation_table {
845 /* number of DP video streams */
847 /* array of stream allocations */
848 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
852 * A link contains one or more sinks and their connected status.
853 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
856 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
857 unsigned int sink_count;
858 struct dc_sink *local_sink;
859 unsigned int link_index;
860 enum dc_connection_type type;
861 enum signal_type connector_signal;
862 enum dc_irq_source irq_source_hpd;
863 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */
864 /* caps is the same as reported_link_cap. link_traing use
865 * reported_link_cap. Will clean up. TODO
867 struct dc_link_settings reported_link_cap;
868 struct dc_link_settings verified_link_cap;
869 struct dc_link_settings cur_link_settings;
870 struct dc_lane_settings cur_lane_setting;
871 struct dc_link_settings preferred_link_setting;
877 uint8_t link_enc_hw_inst;
879 bool test_pattern_enabled;
880 union compliance_test_state compliance_test_state;
884 struct ddc_service *ddc;
888 /* Private to DC core */
892 struct dc_context *ctx;
894 struct link_encoder *link_enc;
895 struct graphics_object_id link_id;
896 union ddi_channel_mapping ddi_channel_mapping;
897 struct connector_device_tag_info device_tag;
898 struct dpcd_caps dpcd_caps;
899 unsigned short chip_caps;
900 unsigned int dpcd_sink_count;
901 enum edp_revision edp_revision;
904 /* MST record stream using this link */
906 bool dp_keep_receiver_powered;
908 struct link_mst_stream_allocation_table mst_stream_alloc_table;
910 struct dc_link_status link_status;
914 const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
917 * Return an enumerated dc_link. dc_link order is constant and determined at
918 * boot time. They cannot be created or destroyed.
919 * Use dc_get_caps() to get number of links.
921 static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
923 return dc->links[link_index];
926 /* Set backlight level of an embedded panel (eDP, LVDS). */
927 bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
928 uint32_t frame_ramp, const struct dc_stream_state *stream);
930 bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait);
932 bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
934 bool dc_link_setup_psr(struct dc_link *dc_link,
935 const struct dc_stream_state *stream, struct psr_config *psr_config,
936 struct psr_context *psr_context);
938 /* Request DC to detect if there is a Panel connected.
939 * boot - If this call is during initial boot.
940 * Return false for any type of detection failure or MST detection
941 * true otherwise. True meaning further action is required (status update
942 * and OS notification).
944 enum dc_detect_reason {
950 bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
952 /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
954 * true - Downstream port status changed. DM should call DC to do the
956 * false - no change in Downstream port status. No further action required
958 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
959 union hpd_irq_data *hpd_irq_dpcd_data);
961 struct dc_sink_init_data;
963 struct dc_sink *dc_link_add_remote_sink(
964 struct dc_link *dc_link,
967 struct dc_sink_init_data *init_data);
969 void dc_link_remove_remote_sink(
970 struct dc_link *link,
971 struct dc_sink *sink);
973 /* Used by diagnostics for virtual link at the moment */
975 void dc_link_dp_set_drive_settings(
976 struct dc_link *link,
977 struct link_training_settings *lt_settings);
979 enum link_training_result dc_link_dp_perform_link_training(
980 struct dc_link *link,
981 const struct dc_link_settings *link_setting,
982 bool skip_video_pattern);
984 void dc_link_dp_enable_hpd(const struct dc_link *link);
986 void dc_link_dp_disable_hpd(const struct dc_link *link);
988 bool dc_link_dp_set_test_pattern(
989 struct dc_link *link,
990 enum dp_test_pattern test_pattern,
991 const struct link_training_settings *p_link_settings,
992 const unsigned char *p_custom_pattern,
993 unsigned int cust_pattern_size);
995 /*******************************************************************************
996 * Sink Interfaces - A sink corresponds to a display output device
997 ******************************************************************************/
999 struct dc_container_id {
1000 // 128bit GUID in binary form
1001 unsigned char guid[16];
1002 // 8 byte port ID -> ELD.PortID
1003 unsigned int portId[2];
1004 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
1005 unsigned short manufacturerName;
1006 // 2 byte product code -> ELD.ProductCode
1007 unsigned short productCode;
1013 * The sink structure contains EDID and other display device properties
1016 enum signal_type sink_signal;
1017 struct dc_edid dc_edid; /* raw edid */
1018 struct dc_edid_caps edid_caps; /* parse display caps */
1019 struct dc_container_id *dc_container_id;
1020 uint32_t dongle_max_pix_clk;
1022 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1023 bool converter_disable_audio;
1025 /* private to DC core */
1026 struct dc_link *link;
1027 struct dc_context *ctx;
1029 /* private to dc_sink.c */
1030 struct kref refcount;
1033 void dc_sink_retain(struct dc_sink *sink);
1034 void dc_sink_release(struct dc_sink *sink);
1036 struct dc_sink_init_data {
1037 enum signal_type sink_signal;
1038 struct dc_link *link;
1039 uint32_t dongle_max_pix_clk;
1040 bool converter_disable_audio;
1043 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1045 /*******************************************************************************
1046 * Cursor interfaces - To manages the cursor within a stream
1047 ******************************************************************************/
1048 /* TODO: Deprecated once we switch to dc_set_cursor_position */
1049 bool dc_stream_set_cursor_attributes(
1050 struct dc_stream_state *stream,
1051 const struct dc_cursor_attributes *attributes);
1053 bool dc_stream_set_cursor_position(
1054 struct dc_stream_state *stream,
1055 const struct dc_cursor_position *position);
1057 /* Newer interfaces */
1059 struct dc_plane_address address;
1060 struct dc_cursor_attributes attributes;
1063 /*******************************************************************************
1064 * Interrupt interfaces
1065 ******************************************************************************/
1066 enum dc_irq_source dc_interrupt_to_irq_source(
1070 void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1071 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1072 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1073 struct dc *dc, uint32_t link_index);
1075 /*******************************************************************************
1077 ******************************************************************************/
1079 void dc_set_power_state(
1081 enum dc_acpi_cm_power_state power_state);
1082 void dc_resume(struct dc *dc);
1085 * DPCD access interfaces
1090 uint32_t link_index,
1091 struct i2c_command *cmd);
1094 #endif /* DC_INTERFACE_H_ */