2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #include "gpio_types.h"
33 #include "link_service_types.h"
34 #include "grph_object_ctrl_defs.h"
35 #include <inc/hw/opp.h>
37 #include "inc/hw_sequencer.h"
38 #include "inc/compressor.h"
39 #include "inc/hw/dmcu.h"
40 #include "dml/display_mode_lib.h"
42 #define DC_VER "3.2.17"
44 #define MAX_SURFACES 3
46 #define MAX_SINKS_PER_LINK 4
48 /*******************************************************************************
49 * Display Core Interfaces
50 ******************************************************************************/
53 struct dmcu_version dmcu_version;
60 uint32_t max_slave_planes;
62 uint32_t max_downscale_ratio;
63 uint32_t i2c_speed_in_khz;
64 uint32_t dmdata_alloc_size;
65 unsigned int max_cursor_size;
66 unsigned int max_video_width;
67 int linear_pitch_alignment;
72 bool post_blend_color_processing;
73 bool force_dp_tps4_for_cp2520;
74 bool disable_dp_clk_share;
75 bool psp_setup_panel_mode;
78 struct dc_dcc_surface_param {
79 struct dc_size surface_size;
80 enum surface_pixel_format format;
81 enum swizzle_mode_values swizzle_mode;
82 enum dc_scan_direction scan;
85 struct dc_dcc_setting {
86 unsigned int max_compressed_blk_size;
87 unsigned int max_uncompressed_blk_size;
88 bool independent_64b_blks;
91 struct dc_surface_dcc_cap {
94 struct dc_dcc_setting rgb;
98 struct dc_dcc_setting luma;
99 struct dc_dcc_setting chroma;
104 bool const_color_support;
107 struct dc_static_screen_events {
115 /* Surface update type is used by dc_update_surfaces_and_stream
116 * The update type is determined at the very beginning of the function based
117 * on parameters passed in and decides how much programming (or updating) is
118 * going to be done during the call.
120 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
121 * logical calculations or hardware register programming. This update MUST be
122 * ISR safe on windows. Currently fast update will only be used to flip surface
125 * UPDATE_TYPE_MED is used for slower updates which require significant hw
126 * re-programming however do not affect bandwidth consumption or clock
127 * requirements. At present, this is the level at which front end updates
128 * that do not require us to run bw_calcs happen. These are in/out transfer func
129 * updates, viewport offset changes, recout size changes and pixel depth changes.
130 * This update can be done at ISR, but we want to minimize how often this happens.
132 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
133 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
134 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
135 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
136 * a full update. This cannot be done at ISR level and should be a rare event.
137 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
138 * underscan we don't expect to see this call at all.
141 enum surface_update_type {
142 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
143 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
144 UPDATE_TYPE_FULL, /* may need to shuffle resources */
147 /* Forward declaration*/
149 struct dc_plane_state;
153 struct dc_cap_funcs {
154 bool (*get_dcc_compression_cap)(const struct dc *dc,
155 const struct dc_dcc_surface_param *input,
156 struct dc_surface_dcc_cap *output);
159 struct link_training_settings;
162 /* Structure to hold configuration flags set by dm at dc creation. */
165 bool disable_disp_pll_sharing;
169 enum visual_confirm {
170 VISUAL_CONFIRM_DISABLE = 0,
171 VISUAL_CONFIRM_SURFACE = 1,
172 VISUAL_CONFIRM_HDR = 2,
178 DCC_HALF_REQ_DISALBE = 2,
181 enum pipe_split_policy {
182 MPC_SPLIT_DYNAMIC = 0,
184 MPC_SPLIT_AVOID_MULT_DISP = 2,
187 enum wm_report_mode {
188 WM_REPORT_DEFAULT = 0,
189 WM_REPORT_OVERRIDE = 1,
193 * For any clocks that may differ per pipe
194 * only the max is stored in this structure
198 int max_supported_dppclk_khz;
202 int dcfclk_deep_sleep_khz;
208 struct dc_debug_options {
209 enum visual_confirm visual_confirm;
215 bool validation_trace;
216 bool bandwidth_calcs_trace;
217 int max_downscale_src_width;
219 /* stutter efficiency related */
220 bool disable_stutter;
222 enum dcc_option disable_dcc;
223 enum pipe_split_policy pipe_split_policy;
224 bool force_single_disp_pipe_split;
225 bool voltage_align_fclk;
227 bool disable_dfs_bypass;
228 bool disable_dpp_power_gate;
229 bool disable_hubp_power_gate;
230 bool disable_pplib_wm_range;
231 enum wm_report_mode pplib_wm_report_mode;
232 unsigned int min_disp_clk_khz;
233 int sr_exit_time_dpm0_ns;
234 int sr_enter_plus_exit_time_dpm0_ns;
236 int sr_enter_plus_exit_time_ns;
237 int urgent_latency_ns;
238 int percent_of_ideal_drambw;
239 int dram_clock_change_latency_ns;
240 bool optimized_watermark;
242 bool disable_pplib_clock_request;
243 bool disable_clock_gate;
246 bool force_abm_enable;
247 bool disable_stereo_support;
249 bool performance_trace;
250 bool az_endpoint_mute_only;
251 bool always_use_regamma;
252 bool p010_mpo_support;
253 bool recovery_enabled;
254 bool avoid_vbios_exec_table;
255 bool scl_reset_length10;
257 bool skip_detection_link_training;
258 unsigned int force_odm_combine; //bit vector based on otg inst
259 unsigned int force_fclk_khz;
262 struct dc_debug_data {
263 uint32_t ltFailCount;
264 uint32_t i2cErrorCount;
265 uint32_t auxErrorCount;
269 struct resource_pool;
272 struct dc_versions versions;
274 struct dc_cap_funcs cap_funcs;
275 struct dc_config config;
276 struct dc_debug_options debug;
277 struct dc_context *ctx;
280 struct dc_link *links[MAX_PIPES * 2];
282 struct dc_state *current_state;
283 struct resource_pool *res_pool;
285 /* Display Engine Clock levels */
286 struct dm_pp_clock_levels sclk_lvls;
288 /* Inputs into BW and WM calculations. */
289 struct bw_calcs_dceip *bw_dceip;
290 struct bw_calcs_vbios *bw_vbios;
291 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
292 struct dcn_soc_bounding_box *dcn_soc;
293 struct dcn_ip_params *dcn_ip;
294 struct display_mode_lib dml;
298 struct hw_sequencer_funcs hwss;
299 struct dce_hwseq *hwseq;
301 bool optimized_required;
304 struct compressor *fbc_compressor;
306 struct dc_debug_data debug_data;
308 const char *build_id;
311 enum frame_buffer_mode {
312 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
313 FRAME_BUFFER_MODE_ZFB_ONLY,
314 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
317 struct dchub_init_data {
318 int64_t zfb_phys_addr_base;
319 int64_t zfb_mc_base_addr;
320 uint64_t zfb_size_in_byte;
321 enum frame_buffer_mode fb_mode;
322 bool dchub_initialzied;
323 bool dchub_info_valid;
326 struct dc_init_data {
327 struct hw_asic_id asic_id;
328 void *driver; /* ctx */
329 struct cgs_device *cgs_device;
331 int num_virtual_links;
333 * If 'vbios_override' not NULL, it will be called instead
334 * of the real VBIOS. Intended use is Diagnostics on FPGA.
336 struct dc_bios *vbios_override;
337 enum dce_environment dce_environment;
339 struct dc_config flags;
343 struct dc_callback_init {
347 struct dc *dc_create(const struct dc_init_data *init_params);
348 void dc_init_callbacks(struct dc *dc,
349 const struct dc_callback_init *init_params);
350 void dc_destroy(struct dc **dc);
352 /*******************************************************************************
354 ******************************************************************************/
357 TRANSFER_FUNC_POINTS = 1025
360 struct dc_hdr_static_metadata {
361 /* display chromaticities and white point in units of 0.00001 */
362 unsigned int chromaticity_green_x;
363 unsigned int chromaticity_green_y;
364 unsigned int chromaticity_blue_x;
365 unsigned int chromaticity_blue_y;
366 unsigned int chromaticity_red_x;
367 unsigned int chromaticity_red_y;
368 unsigned int chromaticity_white_point_x;
369 unsigned int chromaticity_white_point_y;
371 uint32_t min_luminance;
372 uint32_t max_luminance;
373 uint32_t maximum_content_light_level;
374 uint32_t maximum_frame_average_light_level;
377 enum dc_transfer_func_type {
379 TF_TYPE_DISTRIBUTED_POINTS,
384 struct dc_transfer_func_distributed_points {
385 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
386 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
387 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
389 uint16_t end_exponent;
390 uint16_t x_point_at_y1_red;
391 uint16_t x_point_at_y1_green;
392 uint16_t x_point_at_y1_blue;
395 enum dc_transfer_func_predefined {
396 TRANSFER_FUNCTION_SRGB,
397 TRANSFER_FUNCTION_BT709,
398 TRANSFER_FUNCTION_PQ,
399 TRANSFER_FUNCTION_LINEAR,
400 TRANSFER_FUNCTION_UNITY,
401 TRANSFER_FUNCTION_HLG,
402 TRANSFER_FUNCTION_HLG12,
403 TRANSFER_FUNCTION_GAMMA22
406 struct dc_transfer_func {
407 struct kref refcount;
408 enum dc_transfer_func_type type;
409 enum dc_transfer_func_predefined tf;
410 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
411 uint32_t sdr_ref_white_level;
412 struct dc_context *ctx;
414 struct pwl_params pwl;
415 struct dc_transfer_func_distributed_points tf_pts;
420 * This structure is filled in by dc_surface_get_status and contains
421 * the last requested address and the currently active address so the called
422 * can determine if there are any outstanding flips
424 struct dc_plane_status {
425 struct dc_plane_address requested_address;
426 struct dc_plane_address current_address;
427 bool is_flip_pending;
431 union surface_update_flags {
435 uint32_t dcc_change:1;
436 uint32_t color_space_change:1;
437 uint32_t horizontal_mirror_change:1;
438 uint32_t per_pixel_alpha_change:1;
439 uint32_t global_alpha_change:1;
440 uint32_t rotation_change:1;
441 uint32_t swizzle_change:1;
442 uint32_t scaling_change:1;
443 uint32_t position_change:1;
444 uint32_t in_transfer_func_change:1;
445 uint32_t input_csc_change:1;
446 uint32_t coeff_reduction_change:1;
447 uint32_t output_tf_change:1;
448 uint32_t pixel_format_change:1;
449 uint32_t plane_size_change:1;
452 uint32_t new_plane:1;
453 uint32_t bpp_change:1;
454 uint32_t gamma_change:1;
455 uint32_t bandwidth_change:1;
456 uint32_t clock_change:1;
457 uint32_t stereo_format_change:1;
458 uint32_t full_update:1;
464 struct dc_plane_state {
465 struct dc_plane_address address;
466 struct dc_plane_flip_time time;
467 struct scaling_taps scaling_quality;
468 struct rect src_rect;
469 struct rect dst_rect;
470 struct rect clip_rect;
472 union plane_size plane_size;
473 union dc_tiling_info tiling_info;
475 struct dc_plane_dcc_param dcc;
477 struct dc_gamma *gamma_correction;
478 struct dc_transfer_func *in_transfer_func;
479 struct dc_bias_and_scale *bias_and_scale;
480 struct dc_csc_transform input_csc_color_matrix;
481 struct fixed31_32 coeff_reduction_factor;
482 uint32_t sdr_white_level;
484 // TODO: No longer used, remove
485 struct dc_hdr_static_metadata hdr_static_ctx;
487 enum dc_color_space color_space;
489 enum surface_pixel_format format;
490 enum dc_rotation_angle rotation;
491 enum plane_stereo_format stereo_format;
493 bool is_tiling_rotated;
494 bool per_pixel_alpha;
496 int global_alpha_value;
499 bool horizontal_mirror;
501 union surface_update_flags update_flags;
502 /* private to DC core */
503 struct dc_plane_status status;
504 struct dc_context *ctx;
506 /* private to dc_surface.c */
507 enum dc_irq_source irq_source;
508 struct kref refcount;
511 struct dc_plane_info {
512 union plane_size plane_size;
513 union dc_tiling_info tiling_info;
514 struct dc_plane_dcc_param dcc;
515 enum surface_pixel_format format;
516 enum dc_rotation_angle rotation;
517 enum plane_stereo_format stereo_format;
518 enum dc_color_space color_space;
519 unsigned int sdr_white_level;
520 bool horizontal_mirror;
522 bool per_pixel_alpha;
524 int global_alpha_value;
525 bool input_csc_enabled;
528 struct dc_scaling_info {
529 struct rect src_rect;
530 struct rect dst_rect;
531 struct rect clip_rect;
532 struct scaling_taps scaling_quality;
535 struct dc_surface_update {
536 struct dc_plane_state *surface;
538 /* isr safe update parameters. null means no updates */
539 const struct dc_flip_addrs *flip_addr;
540 const struct dc_plane_info *plane_info;
541 const struct dc_scaling_info *scaling_info;
543 /* following updates require alloc/sleep/spin that is not isr safe,
544 * null means no updates
546 const struct dc_gamma *gamma;
547 const struct dc_transfer_func *in_transfer_func;
549 const struct dc_csc_transform *input_csc_color_matrix;
550 const struct fixed31_32 *coeff_reduction_factor;
554 * Create a new surface with default parameters;
556 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
557 const struct dc_plane_status *dc_plane_get_status(
558 const struct dc_plane_state *plane_state);
560 void dc_plane_state_retain(struct dc_plane_state *plane_state);
561 void dc_plane_state_release(struct dc_plane_state *plane_state);
563 void dc_gamma_retain(struct dc_gamma *dc_gamma);
564 void dc_gamma_release(struct dc_gamma **dc_gamma);
565 struct dc_gamma *dc_create_gamma(void);
567 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
568 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
569 struct dc_transfer_func *dc_create_transfer_func(void);
572 * This structure holds a surface address. There could be multiple addresses
573 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
574 * as frame durations and DCC format can also be set.
576 struct dc_flip_addrs {
577 struct dc_plane_address address;
578 unsigned int flip_timestamp_in_us;
580 /* TODO: add flip duration for FreeSync */
583 bool dc_post_update_surfaces_to_stream(
586 #include "dc_stream.h"
589 * Structure to store surface/stream associations for validation
591 struct dc_validation_set {
592 struct dc_stream_state *stream;
593 struct dc_plane_state *plane_states[MAX_SURFACES];
597 bool dc_validate_seamless_boot_timing(struct dc *dc,
598 const struct dc_sink *sink,
599 struct dc_crtc_timing *crtc_timing);
601 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
603 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
605 enum dc_status dc_validate_global_state(
607 struct dc_state *new_ctx);
610 void dc_resource_state_construct(
612 struct dc_state *dst_ctx);
614 void dc_resource_state_copy_construct(
615 const struct dc_state *src_ctx,
616 struct dc_state *dst_ctx);
618 void dc_resource_state_copy_construct_current(
620 struct dc_state *dst_ctx);
622 void dc_resource_state_destruct(struct dc_state *context);
625 * TODO update to make it about validation sets
626 * Set up streams and links associated to drive sinks
627 * The streams parameter is an absolute set of all active streams.
630 * Phy, Encoder, Timing Generator are programmed and enabled.
631 * New streams are enabled with blank stream; no memory read.
633 bool dc_commit_state(struct dc *dc, struct dc_state *context);
636 struct dc_state *dc_create_state(void);
637 void dc_retain_state(struct dc_state *context);
638 void dc_release_state(struct dc_state *context);
640 /*******************************************************************************
642 ******************************************************************************/
645 union dpcd_rev dpcd_rev;
646 union max_lane_count max_ln_count;
647 union max_down_spread max_down_spread;
649 /* dongle type (DP converter, CV smart dongle) */
650 enum display_dongle_type dongle_type;
651 /* Dongle's downstream count. */
652 union sink_count sink_count;
653 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
654 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
655 struct dc_dongle_caps dongle_caps;
657 uint32_t sink_dev_id;
658 int8_t sink_dev_id_str[6];
659 int8_t sink_hw_revision;
660 int8_t sink_fw_revision[2];
662 uint32_t branch_dev_id;
663 int8_t branch_dev_name[6];
664 int8_t branch_hw_revision;
665 int8_t branch_fw_revision[2];
666 uint8_t link_rate_set;
668 bool allow_invalid_MSA_timing_param;
670 bool dpcd_display_control_capable;
675 /*******************************************************************************
676 * Sink Interfaces - A sink corresponds to a display output device
677 ******************************************************************************/
679 struct dc_container_id {
680 // 128bit GUID in binary form
681 unsigned char guid[16];
682 // 8 byte port ID -> ELD.PortID
683 unsigned int portId[2];
684 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
685 unsigned short manufacturerName;
686 // 2 byte product code -> ELD.ProductCode
687 unsigned short productCode;
693 * The sink structure contains EDID and other display device properties
696 enum signal_type sink_signal;
697 struct dc_edid dc_edid; /* raw edid */
698 struct dc_edid_caps edid_caps; /* parse display caps */
699 struct dc_container_id *dc_container_id;
700 uint32_t dongle_max_pix_clk;
702 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
703 bool converter_disable_audio;
705 /* private to DC core */
706 struct dc_link *link;
707 struct dc_context *ctx;
711 /* private to dc_sink.c */
712 // refcount must be the last member in dc_sink, since we want the
713 // sink structure to be logically cloneable up to (but not including)
715 struct kref refcount;
718 void dc_sink_retain(struct dc_sink *sink);
719 void dc_sink_release(struct dc_sink *sink);
721 struct dc_sink_init_data {
722 enum signal_type sink_signal;
723 struct dc_link *link;
724 uint32_t dongle_max_pix_clk;
725 bool converter_disable_audio;
728 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
730 /* Newer interfaces */
732 struct dc_plane_address address;
733 struct dc_cursor_attributes attributes;
737 /*******************************************************************************
738 * Interrupt interfaces
739 ******************************************************************************/
740 enum dc_irq_source dc_interrupt_to_irq_source(
744 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
745 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
746 enum dc_irq_source dc_get_hpd_irq_source_at_index(
747 struct dc *dc, uint32_t link_index);
749 /*******************************************************************************
751 ******************************************************************************/
753 void dc_set_power_state(
755 enum dc_acpi_cm_power_state power_state);
756 void dc_resume(struct dc *dc);
757 unsigned int dc_get_current_backlight_pwm(struct dc *dc);
758 unsigned int dc_get_target_backlight_pwm(struct dc *dc);
760 bool dc_is_dmcu_initialized(struct dc *dc);
762 #endif /* DC_INTERFACE_H_ */