2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/slab.h>
28 #include "dm_services.h"
31 #include "include/irq_service_interface.h"
32 #include "link_encoder.h"
33 #include "stream_encoder.h"
35 #include "timing_generator.h"
36 #include "transform.h"
40 #include "core_types.h"
41 #include "set_mode_types.h"
42 #include "virtual/virtual_stream_encoder.h"
43 #include "dpcd_defs.h"
44 #include "link_enc_cfg.h"
45 #include "dc_link_dp.h"
47 #if defined(CONFIG_DRM_AMD_DC_SI)
48 #include "dce60/dce60_resource.h"
50 #include "dce80/dce80_resource.h"
51 #include "dce100/dce100_resource.h"
52 #include "dce110/dce110_resource.h"
53 #include "dce112/dce112_resource.h"
54 #include "dce120/dce120_resource.h"
55 #if defined(CONFIG_DRM_AMD_DC_DCN)
56 #include "dcn10/dcn10_resource.h"
57 #include "dcn20/dcn20_resource.h"
58 #include "dcn21/dcn21_resource.h"
59 #include "dcn201/dcn201_resource.h"
60 #include "dcn30/dcn30_resource.h"
61 #include "dcn301/dcn301_resource.h"
62 #include "dcn302/dcn302_resource.h"
63 #include "dcn303/dcn303_resource.h"
64 #include "dcn31/dcn31_resource.h"
67 #define DC_LOGGER_INIT(logger)
69 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
71 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
72 switch (asic_id.chip_family) {
74 #if defined(CONFIG_DRM_AMD_DC_SI)
76 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
77 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
78 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
79 dc_version = DCE_VERSION_6_0;
80 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
81 dc_version = DCE_VERSION_6_4;
83 dc_version = DCE_VERSION_6_1;
87 dc_version = DCE_VERSION_8_0;
90 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
91 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
92 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
93 dc_version = DCE_VERSION_8_3;
95 dc_version = DCE_VERSION_8_1;
98 dc_version = DCE_VERSION_11_0;
102 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
103 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
104 dc_version = DCE_VERSION_10_0;
107 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
108 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
109 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
110 dc_version = DCE_VERSION_11_2;
112 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
113 dc_version = DCE_VERSION_11_22;
116 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
117 dc_version = DCE_VERSION_12_1;
119 dc_version = DCE_VERSION_12_0;
121 #if defined(CONFIG_DRM_AMD_DC_DCN)
123 dc_version = DCN_VERSION_1_0;
124 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
125 dc_version = DCN_VERSION_1_01;
126 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
127 dc_version = DCN_VERSION_2_1;
128 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
129 dc_version = DCN_VERSION_2_1;
133 dc_version = DCN_VERSION_2_0;
134 if (asic_id.chip_id == DEVICE_ID_NV_13FE) {
135 dc_version = DCN_VERSION_2_01;
138 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
139 dc_version = DCN_VERSION_3_0;
140 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))
141 dc_version = DCN_VERSION_3_02;
142 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev))
143 dc_version = DCN_VERSION_3_03;
147 dc_version = DCN_VERSION_3_01;
150 case FAMILY_YELLOW_CARP:
151 if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev))
152 dc_version = DCN_VERSION_3_1;
157 dc_version = DCE_VERSION_UNKNOWN;
163 struct resource_pool *dc_create_resource_pool(struct dc *dc,
164 const struct dc_init_data *init_data,
165 enum dce_version dc_version)
167 struct resource_pool *res_pool = NULL;
169 switch (dc_version) {
170 #if defined(CONFIG_DRM_AMD_DC_SI)
171 case DCE_VERSION_6_0:
172 res_pool = dce60_create_resource_pool(
173 init_data->num_virtual_links, dc);
175 case DCE_VERSION_6_1:
176 res_pool = dce61_create_resource_pool(
177 init_data->num_virtual_links, dc);
179 case DCE_VERSION_6_4:
180 res_pool = dce64_create_resource_pool(
181 init_data->num_virtual_links, dc);
184 case DCE_VERSION_8_0:
185 res_pool = dce80_create_resource_pool(
186 init_data->num_virtual_links, dc);
188 case DCE_VERSION_8_1:
189 res_pool = dce81_create_resource_pool(
190 init_data->num_virtual_links, dc);
192 case DCE_VERSION_8_3:
193 res_pool = dce83_create_resource_pool(
194 init_data->num_virtual_links, dc);
196 case DCE_VERSION_10_0:
197 res_pool = dce100_create_resource_pool(
198 init_data->num_virtual_links, dc);
200 case DCE_VERSION_11_0:
201 res_pool = dce110_create_resource_pool(
202 init_data->num_virtual_links, dc,
205 case DCE_VERSION_11_2:
206 case DCE_VERSION_11_22:
207 res_pool = dce112_create_resource_pool(
208 init_data->num_virtual_links, dc);
210 case DCE_VERSION_12_0:
211 case DCE_VERSION_12_1:
212 res_pool = dce120_create_resource_pool(
213 init_data->num_virtual_links, dc);
216 #if defined(CONFIG_DRM_AMD_DC_DCN)
217 case DCN_VERSION_1_0:
218 case DCN_VERSION_1_01:
219 res_pool = dcn10_create_resource_pool(init_data, dc);
221 case DCN_VERSION_2_0:
222 res_pool = dcn20_create_resource_pool(init_data, dc);
224 case DCN_VERSION_2_1:
225 res_pool = dcn21_create_resource_pool(init_data, dc);
227 case DCN_VERSION_2_01:
228 res_pool = dcn201_create_resource_pool(init_data, dc);
230 case DCN_VERSION_3_0:
231 res_pool = dcn30_create_resource_pool(init_data, dc);
233 case DCN_VERSION_3_01:
234 res_pool = dcn301_create_resource_pool(init_data, dc);
236 case DCN_VERSION_3_02:
237 res_pool = dcn302_create_resource_pool(init_data, dc);
239 case DCN_VERSION_3_03:
240 res_pool = dcn303_create_resource_pool(init_data, dc);
242 case DCN_VERSION_3_1:
243 res_pool = dcn31_create_resource_pool(init_data, dc);
250 if (res_pool != NULL) {
251 if (dc->ctx->dc_bios->fw_info_valid) {
252 res_pool->ref_clocks.xtalin_clock_inKhz =
253 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
254 /* initialize with firmware data first, no all
255 * ASIC have DCCG SW component. FPGA or
256 * simulation need initialization of
257 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
258 * with xtalin_clock_inKhz
260 res_pool->ref_clocks.dccg_ref_clock_inKhz =
261 res_pool->ref_clocks.xtalin_clock_inKhz;
262 res_pool->ref_clocks.dchub_ref_clock_inKhz =
263 res_pool->ref_clocks.xtalin_clock_inKhz;
265 ASSERT_CRITICAL(false);
271 void dc_destroy_resource_pool(struct dc *dc)
275 dc->res_pool->funcs->destroy(&dc->res_pool);
281 static void update_num_audio(
282 const struct resource_straps *straps,
283 unsigned int *num_audio,
284 struct audio_support *aud_support)
286 aud_support->dp_audio = true;
287 aud_support->hdmi_audio_native = false;
288 aud_support->hdmi_audio_on_dongle = false;
290 if (straps->hdmi_disable == 0) {
291 if (straps->dc_pinstraps_audio & 0x2) {
292 aud_support->hdmi_audio_on_dongle = true;
293 aud_support->hdmi_audio_native = true;
297 switch (straps->audio_stream_number) {
298 case 0: /* multi streams supported */
300 case 1: /* multi streams not supported */
304 DC_ERR("DC: unexpected audio fuse!\n");
308 bool resource_construct(
309 unsigned int num_virtual_links,
311 struct resource_pool *pool,
312 const struct resource_create_funcs *create_funcs)
314 struct dc_context *ctx = dc->ctx;
315 const struct resource_caps *caps = pool->res_cap;
317 unsigned int num_audio = caps->num_audio;
318 struct resource_straps straps = {0};
320 if (create_funcs->read_dce_straps)
321 create_funcs->read_dce_straps(dc->ctx, &straps);
323 pool->audio_count = 0;
324 if (create_funcs->create_audio) {
325 /* find the total number of streams available via the
326 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
327 * registers (one for each pin) starting from pin 1
328 * up to the max number of audio pins.
329 * We stop on the first pin where
330 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
332 update_num_audio(&straps, &num_audio, &pool->audio_support);
333 for (i = 0; i < caps->num_audio; i++) {
334 struct audio *aud = create_funcs->create_audio(ctx, i);
337 DC_ERR("DC: failed to create audio!\n");
340 if (!aud->funcs->endpoint_valid(aud)) {
341 aud->funcs->destroy(&aud);
344 pool->audios[i] = aud;
349 pool->stream_enc_count = 0;
350 if (create_funcs->create_stream_encoder) {
351 for (i = 0; i < caps->num_stream_encoder; i++) {
352 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
353 if (pool->stream_enc[i] == NULL)
354 DC_ERR("DC: failed to create stream_encoder!\n");
355 pool->stream_enc_count++;
359 #if defined(CONFIG_DRM_AMD_DC_DCN)
360 pool->hpo_dp_stream_enc_count = 0;
361 if (create_funcs->create_hpo_dp_stream_encoder) {
362 for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) {
363 pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx);
364 if (pool->hpo_dp_stream_enc[i] == NULL)
365 DC_ERR("DC: failed to create HPO DP stream encoder!\n");
366 pool->hpo_dp_stream_enc_count++;
371 pool->hpo_dp_link_enc_count = 0;
372 if (create_funcs->create_hpo_dp_link_encoder) {
373 for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) {
374 pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx);
375 if (pool->hpo_dp_link_enc[i] == NULL)
376 DC_ERR("DC: failed to create HPO DP link encoder!\n");
377 pool->hpo_dp_link_enc_count++;
382 #if defined(CONFIG_DRM_AMD_DC_DCN)
383 for (i = 0; i < caps->num_mpc_3dlut; i++) {
384 pool->mpc_lut[i] = dc_create_3dlut_func();
385 if (pool->mpc_lut[i] == NULL)
386 DC_ERR("DC: failed to create MPC 3dlut!\n");
387 pool->mpc_shaper[i] = dc_create_transfer_func();
388 if (pool->mpc_shaper[i] == NULL)
389 DC_ERR("DC: failed to create MPC shaper!\n");
392 dc->caps.dynamic_audio = false;
393 if (pool->audio_count < pool->stream_enc_count) {
394 dc->caps.dynamic_audio = true;
396 for (i = 0; i < num_virtual_links; i++) {
397 pool->stream_enc[pool->stream_enc_count] =
398 virtual_stream_encoder_create(
400 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
401 DC_ERR("DC: failed to create stream_encoder!\n");
404 pool->stream_enc_count++;
407 dc->hwseq = create_funcs->create_hwseq(ctx);
411 static int find_matching_clock_source(
412 const struct resource_pool *pool,
413 struct clock_source *clock_source)
418 for (i = 0; i < pool->clk_src_count; i++) {
419 if (pool->clock_sources[i] == clock_source)
425 void resource_unreference_clock_source(
426 struct resource_context *res_ctx,
427 const struct resource_pool *pool,
428 struct clock_source *clock_source)
430 int i = find_matching_clock_source(pool, clock_source);
433 res_ctx->clock_source_ref_count[i]--;
435 if (pool->dp_clock_source == clock_source)
436 res_ctx->dp_clock_source_ref_count--;
439 void resource_reference_clock_source(
440 struct resource_context *res_ctx,
441 const struct resource_pool *pool,
442 struct clock_source *clock_source)
444 int i = find_matching_clock_source(pool, clock_source);
447 res_ctx->clock_source_ref_count[i]++;
449 if (pool->dp_clock_source == clock_source)
450 res_ctx->dp_clock_source_ref_count++;
453 int resource_get_clock_source_reference(
454 struct resource_context *res_ctx,
455 const struct resource_pool *pool,
456 struct clock_source *clock_source)
458 int i = find_matching_clock_source(pool, clock_source);
461 return res_ctx->clock_source_ref_count[i];
463 if (pool->dp_clock_source == clock_source)
464 return res_ctx->dp_clock_source_ref_count;
469 bool resource_are_vblanks_synchronizable(
470 struct dc_stream_state *stream1,
471 struct dc_stream_state *stream2)
473 uint32_t base60_refresh_rates[] = {10, 20, 5};
475 uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates);
476 uint64_t frame_time_diff;
478 if (stream1->ctx->dc->config.vblank_alignment_dto_params &&
479 stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 &&
480 dc_is_dp_signal(stream1->signal) &&
481 dc_is_dp_signal(stream2->signal) &&
482 false == stream1->has_non_synchronizable_pclk &&
483 false == stream2->has_non_synchronizable_pclk &&
484 stream1->timing.flags.VBLANK_SYNCHRONIZABLE &&
485 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) {
486 /* disable refresh rates higher than 60Hz for now */
487 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/
488 stream1->timing.v_total > 60)
490 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/
491 stream2->timing.v_total > 60)
493 frame_time_diff = (uint64_t)10000 *
494 stream1->timing.h_total *
495 stream1->timing.v_total *
496 stream2->timing.pix_clk_100hz;
497 frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz);
498 frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total);
499 frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total);
500 for (i = 0; i < rr_count; i++) {
501 int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000;
505 if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff)
512 bool resource_are_streams_timing_synchronizable(
513 struct dc_stream_state *stream1,
514 struct dc_stream_state *stream2)
516 if (stream1->timing.h_total != stream2->timing.h_total)
519 if (stream1->timing.v_total != stream2->timing.v_total)
522 if (stream1->timing.h_addressable
523 != stream2->timing.h_addressable)
526 if (stream1->timing.v_addressable
527 != stream2->timing.v_addressable)
530 if (stream1->timing.v_front_porch
531 != stream2->timing.v_front_porch)
534 if (stream1->timing.pix_clk_100hz
535 != stream2->timing.pix_clk_100hz)
538 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
541 if (stream1->phy_pix_clk != stream2->phy_pix_clk
542 && (!dc_is_dp_signal(stream1->signal)
543 || !dc_is_dp_signal(stream2->signal)))
546 if (stream1->view_format != stream2->view_format)
549 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
554 static bool is_dp_and_hdmi_sharable(
555 struct dc_stream_state *stream1,
556 struct dc_stream_state *stream2)
558 if (stream1->ctx->dc->caps.disable_dp_clk_share)
561 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
562 stream2->clamping.c_depth != COLOR_DEPTH_888)
569 static bool is_sharable_clk_src(
570 const struct pipe_ctx *pipe_with_clk_src,
571 const struct pipe_ctx *pipe)
573 if (pipe_with_clk_src->clock_source == NULL)
576 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
579 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
580 (dc_is_dp_signal(pipe->stream->signal) &&
581 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
585 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
586 && dc_is_dual_link_signal(pipe->stream->signal))
589 if (dc_is_hdmi_signal(pipe->stream->signal)
590 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
593 if (!resource_are_streams_timing_synchronizable(
594 pipe_with_clk_src->stream, pipe->stream))
600 struct clock_source *resource_find_used_clk_src_for_sharing(
601 struct resource_context *res_ctx,
602 struct pipe_ctx *pipe_ctx)
606 for (i = 0; i < MAX_PIPES; i++) {
607 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
608 return res_ctx->pipe_ctx[i].clock_source;
614 static enum pixel_format convert_pixel_format_to_dalsurface(
615 enum surface_pixel_format surface_pixel_format)
617 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
619 switch (surface_pixel_format) {
620 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
621 dal_pixel_format = PIXEL_FORMAT_INDEX8;
623 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
624 dal_pixel_format = PIXEL_FORMAT_RGB565;
626 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
627 dal_pixel_format = PIXEL_FORMAT_RGB565;
629 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
630 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
632 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
633 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
635 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
636 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
638 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
639 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
641 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
642 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
644 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
645 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
646 dal_pixel_format = PIXEL_FORMAT_FP16;
648 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
649 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
650 dal_pixel_format = PIXEL_FORMAT_420BPP8;
652 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
653 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
654 dal_pixel_format = PIXEL_FORMAT_420BPP10;
656 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
657 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
659 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
662 return dal_pixel_format;
665 static inline void get_vp_scan_direction(
666 enum dc_rotation_angle rotation,
667 bool horizontal_mirror,
668 bool *orthogonal_rotation,
669 bool *flip_vert_scan_dir,
670 bool *flip_horz_scan_dir)
672 *orthogonal_rotation = false;
673 *flip_vert_scan_dir = false;
674 *flip_horz_scan_dir = false;
675 if (rotation == ROTATION_ANGLE_180) {
676 *flip_vert_scan_dir = true;
677 *flip_horz_scan_dir = true;
678 } else if (rotation == ROTATION_ANGLE_90) {
679 *orthogonal_rotation = true;
680 *flip_horz_scan_dir = true;
681 } else if (rotation == ROTATION_ANGLE_270) {
682 *orthogonal_rotation = true;
683 *flip_vert_scan_dir = true;
686 if (horizontal_mirror)
687 *flip_horz_scan_dir = !*flip_horz_scan_dir;
690 int get_num_mpc_splits(struct pipe_ctx *pipe)
692 int mpc_split_count = 0;
693 struct pipe_ctx *other_pipe = pipe->bottom_pipe;
695 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
697 other_pipe = other_pipe->bottom_pipe;
699 other_pipe = pipe->top_pipe;
700 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
702 other_pipe = other_pipe->top_pipe;
705 return mpc_split_count;
708 int get_num_odm_splits(struct pipe_ctx *pipe)
710 int odm_split_count = 0;
711 struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
714 next_pipe = next_pipe->next_odm_pipe;
716 pipe = pipe->prev_odm_pipe;
719 pipe = pipe->prev_odm_pipe;
721 return odm_split_count;
724 static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx)
726 *split_count = get_num_odm_splits(pipe_ctx);
728 if (*split_count == 0) {
729 /*Check for mpc split*/
730 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
732 *split_count = get_num_mpc_splits(pipe_ctx);
733 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
735 split_pipe = split_pipe->top_pipe;
738 /*Get odm split index*/
739 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;
743 split_pipe = split_pipe->prev_odm_pipe;
749 * This is a preliminary vp size calculation to allow us to check taps support.
750 * The result is completely overridden afterwards.
752 static void calculate_viewport_size(struct pipe_ctx *pipe_ctx)
754 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
756 data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width));
757 data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height));
758 data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width));
759 data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height));
760 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
761 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
762 swap(data->viewport.width, data->viewport.height);
763 swap(data->viewport_c.width, data->viewport_c.height);
767 static void calculate_recout(struct pipe_ctx *pipe_ctx)
769 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
770 const struct dc_stream_state *stream = pipe_ctx->stream;
771 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
772 struct rect surf_clip = plane_state->clip_rect;
773 bool split_tb = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
774 int split_count, split_idx;
776 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
777 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
781 * Only the leftmost ODM pipe should be offset by a nonzero distance
783 if (!pipe_ctx->prev_odm_pipe || split_idx == split_count) {
784 data->recout.x = stream->dst.x;
785 if (stream->src.x < surf_clip.x)
786 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
791 if (stream->src.x > surf_clip.x)
792 surf_clip.width -= stream->src.x - surf_clip.x;
793 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
794 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
795 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
797 data->recout.y = stream->dst.y;
798 if (stream->src.y < surf_clip.y)
799 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height
800 / stream->src.height;
801 else if (stream->src.y > surf_clip.y)
802 surf_clip.height -= stream->src.y - surf_clip.y;
804 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height;
805 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height)
806 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y;
808 /* Handle h & v split */
810 ASSERT(data->recout.height % 2 == 0);
811 data->recout.height /= 2;
812 } else if (split_count) {
813 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) {
814 /* extra pixels in the division remainder need to go to pipes after
815 * the extra pixel index minus one(epimo) defined here as:
817 int epimo = split_count - data->recout.width % (split_count + 1);
819 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx;
820 if (split_idx > epimo)
821 data->recout.x += split_idx - epimo - 1;
822 ASSERT(stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE || data->recout.width % 2 == 0);
823 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
826 if (split_idx == split_count) {
827 /* rightmost pipe is the remainder recout */
828 data->recout.width -= data->h_active * split_count - data->recout.x;
830 /* ODM combine cases with MPO we can get negative widths */
831 if (data->recout.width < 0)
832 data->recout.width = 0;
836 data->recout.width = data->h_active - data->recout.x;
841 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
843 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
844 const struct dc_stream_state *stream = pipe_ctx->stream;
845 struct rect surf_src = plane_state->src_rect;
846 const int in_w = stream->src.width;
847 const int in_h = stream->src.height;
848 const int out_w = stream->dst.width;
849 const int out_h = stream->dst.height;
851 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
852 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
853 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
854 swap(surf_src.height, surf_src.width);
856 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
858 plane_state->dst_rect.width);
859 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
861 plane_state->dst_rect.height);
863 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
864 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
865 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
866 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
868 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
869 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
870 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
871 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
873 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
874 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
876 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
877 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
878 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
879 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
881 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
882 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
883 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
884 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
885 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
886 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
887 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
888 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
893 * We completely calculate vp offset, size and inits here based entirely on scaling
894 * ratios and recout for pixel perfect pipe combine.
896 static void calculate_init_and_vp(
898 int recout_offset_within_recout_full,
902 struct fixed31_32 ratio,
903 struct fixed31_32 *init,
907 struct fixed31_32 temp;
911 * First of the taps starts sampling pixel number <init_int_part> corresponding to recout
912 * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on.
913 * All following calculations are based on this logic.
915 * Init calculated according to formula:
916 * init = (scaling_ratio + number_of_taps + 1) / 2
917 * init_bot = init + scaling_ratio
918 * to get pixel perfect combine add the fraction from calculating vp offset
920 temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full);
921 *vp_offset = dc_fixpt_floor(temp);
922 temp.value &= 0xffffffff;
923 *init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int(
924 dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19);
926 * If viewport has non 0 offset and there are more taps than covered by init then
927 * we should decrease the offset and increase init so we are never sampling
928 * outside of viewport.
930 int_part = dc_fixpt_floor(*init);
931 if (int_part < taps) {
932 int_part = taps - int_part;
933 if (int_part > *vp_offset)
934 int_part = *vp_offset;
935 *vp_offset -= int_part;
936 *init = dc_fixpt_add_int(*init, int_part);
939 * If taps are sampling outside of viewport at end of recout and there are more pixels
940 * available in the surface we should increase the viewport size, regardless set vp to
943 temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1));
944 *vp_size = dc_fixpt_floor(temp);
945 if (*vp_size + *vp_offset > src_size)
946 *vp_size = src_size - *vp_offset;
948 /* We did all the math assuming we are scanning same direction as display does,
949 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction
950 * is flipped we simply need to calculate offset from the other side of plane.
951 * Note that outside of viewport all scaling hardware works in recout space.
954 *vp_offset = src_size - *vp_offset - *vp_size;
957 static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)
959 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
960 const struct dc_stream_state *stream = pipe_ctx->stream;
961 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
962 struct rect src = plane_state->src_rect;
963 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
964 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
965 int split_count, split_idx, ro_lb, ro_tb, recout_full_x, recout_full_y;
966 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
968 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
970 * recout full is what the recout would have been if we didnt clip
971 * the source plane at all. We only care about left(ro_lb) and top(ro_tb)
972 * offsets of recout within recout full because those are the directions
973 * we scan from and therefore the only ones that affect inits.
975 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
976 * stream->dst.width / stream->src.width;
977 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
978 * stream->dst.height / stream->src.height;
979 if (pipe_ctx->prev_odm_pipe && split_idx)
980 ro_lb = data->h_active * split_idx - recout_full_x;
982 ro_lb = data->recout.x - recout_full_x;
983 ro_tb = data->recout.y - recout_full_y;
984 ASSERT(ro_lb >= 0 && ro_tb >= 0);
987 * Work in recout rotation since that requires less transformations
989 get_vp_scan_direction(
990 plane_state->rotation,
991 plane_state->horizontal_mirror,
992 &orthogonal_rotation,
994 &flip_horz_scan_dir);
996 if (orthogonal_rotation) {
997 swap(src.width, src.height);
998 swap(flip_vert_scan_dir, flip_horz_scan_dir);
1001 calculate_init_and_vp(
1010 &data->viewport.width);
1011 calculate_init_and_vp(
1015 src.width / vpc_div,
1016 data->taps.h_taps_c,
1017 data->ratios.horz_c,
1019 &data->viewport_c.x,
1020 &data->viewport_c.width);
1021 calculate_init_and_vp(
1024 data->recout.height,
1030 &data->viewport.height);
1031 calculate_init_and_vp(
1034 data->recout.height,
1035 src.height / vpc_div,
1036 data->taps.v_taps_c,
1037 data->ratios.vert_c,
1039 &data->viewport_c.y,
1040 &data->viewport_c.height);
1041 if (orthogonal_rotation) {
1042 swap(data->viewport.x, data->viewport.y);
1043 swap(data->viewport.width, data->viewport.height);
1044 swap(data->viewport_c.x, data->viewport_c.y);
1045 swap(data->viewport_c.width, data->viewport_c.height);
1047 data->viewport.x += src.x;
1048 data->viewport.y += src.y;
1049 ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0);
1050 data->viewport_c.x += src.x / vpc_div;
1051 data->viewport_c.y += src.y / vpc_div;
1054 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
1056 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1057 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
1059 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1061 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
1062 pipe_ctx->plane_state->format);
1064 /* Timing borders are part of vactive that we are also supposed to skip in addition
1065 * to any stream dst offset. Since dm logic assumes dst is in addressable
1066 * space we need to add the left and top borders to dst offsets temporarily.
1067 * TODO: fix in DM, stream dst is supposed to be in vactive
1069 pipe_ctx->stream->dst.x += timing->h_border_left;
1070 pipe_ctx->stream->dst.y += timing->v_border_top;
1072 /* Calculate H and V active size */
1073 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable +
1074 timing->h_border_left + timing->h_border_right;
1075 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable +
1076 timing->v_border_top + timing->v_border_bottom;
1077 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe)
1078 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;
1080 /* depends on h_active */
1081 calculate_recout(pipe_ctx);
1082 /* depends on pixel format */
1083 calculate_scaling_ratios(pipe_ctx);
1084 /* depends on scaling ratios and recout, does not calculate offset yet */
1085 calculate_viewport_size(pipe_ctx);
1087 /* Stopgap for validation of ODM + MPO on one side of screen case */
1088 if (pipe_ctx->plane_res.scl_data.viewport.height < 1 ||
1089 pipe_ctx->plane_res.scl_data.viewport.width < 1)
1093 * LB calculations depend on vp size, h/v_active and scaling ratios
1094 * Setting line buffer pixel depth to 24bpp yields banding
1095 * on certain displays, such as the Sharp 4k. 36bpp is needed
1096 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
1097 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
1098 * precision on at least DCN display engines. However, at least
1099 * Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
1100 * so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3
1101 * did not show such problems, so this seems to be the exception.
1103 if (plane_state->ctx->dce_version > DCE_VERSION_11_0)
1104 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
1106 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1108 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
1110 if (pipe_ctx->plane_res.xfm != NULL)
1111 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1112 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1114 if (pipe_ctx->plane_res.dpp != NULL)
1115 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1116 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1120 /* Try 24 bpp linebuffer */
1121 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
1123 if (pipe_ctx->plane_res.xfm != NULL)
1124 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1125 pipe_ctx->plane_res.xfm,
1126 &pipe_ctx->plane_res.scl_data,
1127 &plane_state->scaling_quality);
1129 if (pipe_ctx->plane_res.dpp != NULL)
1130 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1131 pipe_ctx->plane_res.dpp,
1132 &pipe_ctx->plane_res.scl_data,
1133 &plane_state->scaling_quality);
1137 * Depends on recout, scaling ratios, h_active and taps
1138 * May need to re-check lb size after this in some obscure scenario
1141 calculate_inits_and_viewports(pipe_ctx);
1144 * Handle side by side and top bottom 3d recout offsets after vp calculation
1145 * since 3d is special and needs to calculate vp as if there is no recout offset
1146 * This may break with rotation, good thing we aren't mixing hw rotation and 3d
1148 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {
1149 ASSERT(plane_state->rotation == ROTATION_ANGLE_0 ||
1150 (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM &&
1151 pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE));
1152 if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
1153 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;
1154 else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
1155 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
1158 if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) {
1159 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE ||
1160 pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
1163 /* Clamp minimum viewport size */
1164 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE)
1165 pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;
1166 if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
1167 pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;
1170 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n"
1171 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n",
1174 pipe_ctx->plane_res.scl_data.viewport.height,
1175 pipe_ctx->plane_res.scl_data.viewport.width,
1176 pipe_ctx->plane_res.scl_data.viewport.x,
1177 pipe_ctx->plane_res.scl_data.viewport.y,
1178 pipe_ctx->plane_res.scl_data.recout.height,
1179 pipe_ctx->plane_res.scl_data.recout.width,
1180 pipe_ctx->plane_res.scl_data.recout.x,
1181 pipe_ctx->plane_res.scl_data.recout.y,
1182 pipe_ctx->plane_res.scl_data.h_active,
1183 pipe_ctx->plane_res.scl_data.v_active,
1184 plane_state->src_rect.height,
1185 plane_state->src_rect.width,
1186 plane_state->src_rect.x,
1187 plane_state->src_rect.y,
1188 plane_state->dst_rect.height,
1189 plane_state->dst_rect.width,
1190 plane_state->dst_rect.x,
1191 plane_state->dst_rect.y,
1192 plane_state->clip_rect.height,
1193 plane_state->clip_rect.width,
1194 plane_state->clip_rect.x,
1195 plane_state->clip_rect.y);
1197 pipe_ctx->stream->dst.x -= timing->h_border_left;
1198 pipe_ctx->stream->dst.y -= timing->v_border_top;
1204 enum dc_status resource_build_scaling_params_for_context(
1205 const struct dc *dc,
1206 struct dc_state *context)
1210 for (i = 0; i < MAX_PIPES; i++) {
1211 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
1212 context->res_ctx.pipe_ctx[i].stream != NULL)
1213 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
1214 return DC_FAIL_SCALING;
1220 struct pipe_ctx *find_idle_secondary_pipe(
1221 struct resource_context *res_ctx,
1222 const struct resource_pool *pool,
1223 const struct pipe_ctx *primary_pipe)
1226 struct pipe_ctx *secondary_pipe = NULL;
1229 * We add a preferred pipe mapping to avoid the chance that
1230 * MPCCs already in use will need to be reassigned to other trees.
1231 * For example, if we went with the strict, assign backwards logic:
1234 * Display A on, no surface, top pipe = 0
1235 * Display B on, no surface, top pipe = 1
1238 * Display A on, no surface, top pipe = 0
1239 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1242 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1243 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1245 * The state 2->3 transition requires remapping MPCC 5 from display B
1248 * However, with the preferred pipe logic, state 2 would look like:
1251 * Display A on, no surface, top pipe = 0
1252 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1254 * This would then cause 2->3 to not require remapping any MPCCs.
1257 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1258 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1259 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1260 secondary_pipe->pipe_idx = preferred_pipe_idx;
1265 * search backwards for the second pipe to keep pipe
1266 * assignment more consistent
1268 if (!secondary_pipe)
1269 for (i = pool->pipe_count - 1; i >= 0; i--) {
1270 if (res_ctx->pipe_ctx[i].stream == NULL) {
1271 secondary_pipe = &res_ctx->pipe_ctx[i];
1272 secondary_pipe->pipe_idx = i;
1277 return secondary_pipe;
1280 struct pipe_ctx *resource_get_head_pipe_for_stream(
1281 struct resource_context *res_ctx,
1282 struct dc_stream_state *stream)
1286 for (i = 0; i < MAX_PIPES; i++) {
1287 if (res_ctx->pipe_ctx[i].stream == stream
1288 && !res_ctx->pipe_ctx[i].top_pipe
1289 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
1290 return &res_ctx->pipe_ctx[i];
1295 static struct pipe_ctx *resource_get_tail_pipe(
1296 struct resource_context *res_ctx,
1297 struct pipe_ctx *head_pipe)
1299 struct pipe_ctx *tail_pipe;
1301 tail_pipe = head_pipe->bottom_pipe;
1304 head_pipe = tail_pipe;
1305 tail_pipe = tail_pipe->bottom_pipe;
1312 * A free_pipe for a stream is defined here as a pipe
1313 * that has no surface attached yet
1315 static struct pipe_ctx *acquire_free_pipe_for_head(
1316 struct dc_state *context,
1317 const struct resource_pool *pool,
1318 struct pipe_ctx *head_pipe)
1321 struct resource_context *res_ctx = &context->res_ctx;
1323 if (!head_pipe->plane_state)
1326 /* Re-use pipe already acquired for this stream if available*/
1327 for (i = pool->pipe_count - 1; i >= 0; i--) {
1328 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
1329 !res_ctx->pipe_ctx[i].plane_state) {
1330 return &res_ctx->pipe_ctx[i];
1335 * At this point we have no re-useable pipe for this stream and we need
1336 * to acquire an idle one to satisfy the request
1339 if (!pool->funcs->acquire_idle_pipe_for_layer)
1342 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
1345 #if defined(CONFIG_DRM_AMD_DC_DCN)
1346 static int acquire_first_split_pipe(
1347 struct resource_context *res_ctx,
1348 const struct resource_pool *pool,
1349 struct dc_stream_state *stream)
1353 for (i = 0; i < pool->pipe_count; i++) {
1354 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1356 if (split_pipe->top_pipe &&
1357 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1358 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1359 if (split_pipe->bottom_pipe)
1360 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1362 if (split_pipe->top_pipe->plane_state)
1363 resource_build_scaling_params(split_pipe->top_pipe);
1365 memset(split_pipe, 0, sizeof(*split_pipe));
1366 split_pipe->stream_res.tg = pool->timing_generators[i];
1367 split_pipe->plane_res.hubp = pool->hubps[i];
1368 split_pipe->plane_res.ipp = pool->ipps[i];
1369 split_pipe->plane_res.dpp = pool->dpps[i];
1370 split_pipe->stream_res.opp = pool->opps[i];
1371 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1372 split_pipe->pipe_idx = i;
1374 split_pipe->stream = stream;
1382 bool dc_add_plane_to_context(
1383 const struct dc *dc,
1384 struct dc_stream_state *stream,
1385 struct dc_plane_state *plane_state,
1386 struct dc_state *context)
1389 struct resource_pool *pool = dc->res_pool;
1390 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
1391 struct dc_stream_status *stream_status = NULL;
1393 for (i = 0; i < context->stream_count; i++)
1394 if (context->streams[i] == stream) {
1395 stream_status = &context->stream_status[i];
1398 if (stream_status == NULL) {
1399 dm_error("Existing stream not found; failed to attach surface!\n");
1404 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1405 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1406 plane_state, MAX_SURFACE_NUM);
1410 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1413 dm_error("Head pipe not found for stream_state %p !\n", stream);
1417 /* retain new surface, but only once per stream */
1418 dc_plane_state_retain(plane_state);
1421 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
1423 #if defined(CONFIG_DRM_AMD_DC_DCN)
1425 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1427 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1431 dc_plane_state_release(plane_state);
1435 free_pipe->plane_state = plane_state;
1437 if (head_pipe != free_pipe) {
1438 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1440 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1441 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1442 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1443 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1444 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1445 free_pipe->clock_source = tail_pipe->clock_source;
1446 free_pipe->top_pipe = tail_pipe;
1447 tail_pipe->bottom_pipe = free_pipe;
1448 if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) {
1449 free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe;
1450 tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe;
1452 if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) {
1453 free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
1454 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe;
1457 head_pipe = head_pipe->next_odm_pipe;
1459 /* assign new surfaces*/
1460 stream_status->plane_states[stream_status->plane_count] = plane_state;
1462 stream_status->plane_count++;
1467 bool dc_remove_plane_from_context(
1468 const struct dc *dc,
1469 struct dc_stream_state *stream,
1470 struct dc_plane_state *plane_state,
1471 struct dc_state *context)
1474 struct dc_stream_status *stream_status = NULL;
1475 struct resource_pool *pool = dc->res_pool;
1477 for (i = 0; i < context->stream_count; i++)
1478 if (context->streams[i] == stream) {
1479 stream_status = &context->stream_status[i];
1483 if (stream_status == NULL) {
1484 dm_error("Existing stream not found; failed to remove plane.\n");
1488 /* release pipe for plane*/
1489 for (i = pool->pipe_count - 1; i >= 0; i--) {
1490 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1492 if (pipe_ctx->plane_state == plane_state) {
1493 if (pipe_ctx->top_pipe)
1494 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1496 /* Second condition is to avoid setting NULL to top pipe
1497 * of tail pipe making it look like head pipe in subsequent
1500 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1501 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1504 * For head pipe detach surfaces from pipe for tail
1505 * pipe just zero it out
1507 if (!pipe_ctx->top_pipe)
1508 pipe_ctx->plane_state = NULL;
1510 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1515 for (i = 0; i < stream_status->plane_count; i++) {
1516 if (stream_status->plane_states[i] == plane_state) {
1518 dc_plane_state_release(stream_status->plane_states[i]);
1523 if (i == stream_status->plane_count) {
1524 dm_error("Existing plane_state not found; failed to detach it!\n");
1528 stream_status->plane_count--;
1530 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1531 for (; i < stream_status->plane_count; i++)
1532 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1534 stream_status->plane_states[stream_status->plane_count] = NULL;
1539 bool dc_rem_all_planes_for_stream(
1540 const struct dc *dc,
1541 struct dc_stream_state *stream,
1542 struct dc_state *context)
1544 int i, old_plane_count;
1545 struct dc_stream_status *stream_status = NULL;
1546 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1548 for (i = 0; i < context->stream_count; i++)
1549 if (context->streams[i] == stream) {
1550 stream_status = &context->stream_status[i];
1554 if (stream_status == NULL) {
1555 dm_error("Existing stream %p not found!\n", stream);
1559 old_plane_count = stream_status->plane_count;
1561 for (i = 0; i < old_plane_count; i++)
1562 del_planes[i] = stream_status->plane_states[i];
1564 for (i = 0; i < old_plane_count; i++)
1565 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1571 static bool add_all_planes_for_stream(
1572 const struct dc *dc,
1573 struct dc_stream_state *stream,
1574 const struct dc_validation_set set[],
1576 struct dc_state *context)
1580 for (i = 0; i < set_count; i++)
1581 if (set[i].stream == stream)
1584 if (i == set_count) {
1585 dm_error("Stream %p not found in set!\n", stream);
1589 for (j = 0; j < set[i].plane_count; j++)
1590 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1596 bool dc_add_all_planes_for_stream(
1597 const struct dc *dc,
1598 struct dc_stream_state *stream,
1599 struct dc_plane_state * const *plane_states,
1601 struct dc_state *context)
1603 struct dc_validation_set set;
1606 set.stream = stream;
1607 set.plane_count = plane_count;
1609 for (i = 0; i < plane_count; i++)
1610 set.plane_states[i] = plane_states[i];
1612 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1615 static bool is_timing_changed(struct dc_stream_state *cur_stream,
1616 struct dc_stream_state *new_stream)
1618 if (cur_stream == NULL)
1621 /* If output color space is changed, need to reprogram info frames */
1622 if (cur_stream->output_color_space != new_stream->output_color_space)
1626 &cur_stream->timing,
1627 &new_stream->timing,
1628 sizeof(struct dc_crtc_timing)) != 0;
1631 static bool are_stream_backends_same(
1632 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
1634 if (stream_a == stream_b)
1637 if (stream_a == NULL || stream_b == NULL)
1640 if (is_timing_changed(stream_a, stream_b))
1643 if (stream_a->dpms_off != stream_b->dpms_off)
1650 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1652 * Checks if there a difference between the two states
1653 * that would require a mode change.
1655 * Does not compare cursor position or attributes.
1657 bool dc_is_stream_unchanged(
1658 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1661 if (!are_stream_backends_same(old_stream, stream))
1664 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
1667 // Only Have Audio left to check whether it is same or not. This is a corner case for Tiled sinks
1668 if (old_stream->audio_info.mode_count != stream->audio_info.mode_count)
1675 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1677 bool dc_is_stream_scaling_unchanged(
1678 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1680 if (old_stream == stream)
1683 if (old_stream == NULL || stream == NULL)
1686 if (memcmp(&old_stream->src,
1688 sizeof(struct rect)) != 0)
1691 if (memcmp(&old_stream->dst,
1693 sizeof(struct rect)) != 0)
1699 static void update_stream_engine_usage(
1700 struct resource_context *res_ctx,
1701 const struct resource_pool *pool,
1702 struct stream_encoder *stream_enc,
1707 for (i = 0; i < pool->stream_enc_count; i++) {
1708 if (pool->stream_enc[i] == stream_enc)
1709 res_ctx->is_stream_enc_acquired[i] = acquired;
1713 #if defined(CONFIG_DRM_AMD_DC_DCN)
1714 static void update_hpo_dp_stream_engine_usage(
1715 struct resource_context *res_ctx,
1716 const struct resource_pool *pool,
1717 struct hpo_dp_stream_encoder *hpo_dp_stream_enc,
1722 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
1723 if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc)
1724 res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired;
1728 static inline int find_acquired_hpo_dp_link_enc_for_link(
1729 const struct resource_context *res_ctx,
1730 const struct dc_link *link)
1734 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++)
1735 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 &&
1736 res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index)
1742 static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx,
1743 const struct resource_pool *pool)
1747 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++)
1748 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0)
1751 return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) &&
1752 i < pool->hpo_dp_link_enc_count) ? i : -1;
1755 static inline void acquire_hpo_dp_link_enc(
1756 struct resource_context *res_ctx,
1757 unsigned int link_index,
1760 res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index;
1761 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1;
1764 static inline void retain_hpo_dp_link_enc(
1765 struct resource_context *res_ctx,
1768 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++;
1771 static inline void release_hpo_dp_link_enc(
1772 struct resource_context *res_ctx,
1775 ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
1776 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--;
1779 static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
1780 const struct resource_pool *pool,
1781 struct pipe_ctx *pipe_ctx,
1782 struct dc_stream_state *stream)
1786 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
1788 if (enc_index >= 0) {
1789 retain_hpo_dp_link_enc(res_ctx, enc_index);
1791 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
1793 acquire_hpo_dp_link_enc(res_ctx, stream->link->link_index, enc_index);
1797 pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
1799 return pipe_ctx->link_res.hpo_dp_link_enc != NULL;
1802 static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
1803 struct pipe_ctx *pipe_ctx,
1804 struct dc_stream_state *stream)
1808 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
1810 if (enc_index >= 0) {
1811 release_hpo_dp_link_enc(res_ctx, enc_index);
1812 pipe_ctx->link_res.hpo_dp_link_enc = NULL;
1817 /* TODO: release audio object */
1818 void update_audio_usage(
1819 struct resource_context *res_ctx,
1820 const struct resource_pool *pool,
1821 struct audio *audio,
1825 for (i = 0; i < pool->audio_count; i++) {
1826 if (pool->audios[i] == audio)
1827 res_ctx->is_audio_acquired[i] = acquired;
1831 static int acquire_first_free_pipe(
1832 struct resource_context *res_ctx,
1833 const struct resource_pool *pool,
1834 struct dc_stream_state *stream)
1838 for (i = 0; i < pool->pipe_count; i++) {
1839 if (!res_ctx->pipe_ctx[i].stream) {
1840 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1842 pipe_ctx->stream_res.tg = pool->timing_generators[i];
1843 pipe_ctx->plane_res.mi = pool->mis[i];
1844 pipe_ctx->plane_res.hubp = pool->hubps[i];
1845 pipe_ctx->plane_res.ipp = pool->ipps[i];
1846 pipe_ctx->plane_res.xfm = pool->transforms[i];
1847 pipe_ctx->plane_res.dpp = pool->dpps[i];
1848 pipe_ctx->stream_res.opp = pool->opps[i];
1850 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
1851 pipe_ctx->pipe_idx = i;
1854 pipe_ctx->stream = stream;
1861 #if defined(CONFIG_DRM_AMD_DC_DCN)
1862 static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link(
1863 struct resource_context *res_ctx,
1864 const struct resource_pool *pool,
1865 struct dc_stream_state *stream)
1869 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
1870 if (!res_ctx->is_hpo_dp_stream_enc_acquired[i] &&
1871 pool->hpo_dp_stream_enc[i]) {
1873 return pool->hpo_dp_stream_enc[i];
1881 static struct audio *find_first_free_audio(
1882 struct resource_context *res_ctx,
1883 const struct resource_pool *pool,
1885 enum dce_version dc_version)
1887 int i, available_audio_count;
1889 available_audio_count = pool->audio_count;
1891 for (i = 0; i < available_audio_count; i++) {
1892 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
1893 /*we have enough audio endpoint, find the matching inst*/
1896 return pool->audios[i];
1900 /* use engine id to find free audio */
1901 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
1902 return pool->audios[id];
1904 /*not found the matching one, first come first serve*/
1905 for (i = 0; i < available_audio_count; i++) {
1906 if (res_ctx->is_audio_acquired[i] == false) {
1907 return pool->audios[i];
1914 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1916 enum dc_status dc_add_stream_to_ctx(
1918 struct dc_state *new_ctx,
1919 struct dc_stream_state *stream)
1922 DC_LOGGER_INIT(dc->ctx->logger);
1924 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
1925 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1926 return DC_ERROR_UNEXPECTED;
1929 new_ctx->streams[new_ctx->stream_count] = stream;
1930 dc_stream_retain(stream);
1931 new_ctx->stream_count++;
1933 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1935 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1941 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1943 enum dc_status dc_remove_stream_from_ctx(
1945 struct dc_state *new_ctx,
1946 struct dc_stream_state *stream)
1949 struct dc_context *dc_ctx = dc->ctx;
1950 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
1951 struct pipe_ctx *odm_pipe;
1954 DC_ERROR("Pipe not found for stream %p !\n", stream);
1955 return DC_ERROR_UNEXPECTED;
1958 odm_pipe = del_pipe->next_odm_pipe;
1960 /* Release primary pipe */
1961 ASSERT(del_pipe->stream_res.stream_enc);
1962 update_stream_engine_usage(
1965 del_pipe->stream_res.stream_enc,
1967 /* Release link encoder from stream in new dc_state. */
1968 if (dc->res_pool->funcs->link_enc_unassign)
1969 dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
1971 #if defined(CONFIG_DRM_AMD_DC_DCN)
1972 if (is_dp_128b_132b_signal(del_pipe)) {
1973 update_hpo_dp_stream_engine_usage(
1974 &new_ctx->res_ctx, dc->res_pool,
1975 del_pipe->stream_res.hpo_dp_stream_enc,
1977 remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
1981 if (del_pipe->stream_res.audio)
1985 del_pipe->stream_res.audio,
1988 resource_unreference_clock_source(&new_ctx->res_ctx,
1990 del_pipe->clock_source);
1992 if (dc->res_pool->funcs->remove_stream_from_ctx)
1993 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1996 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1998 memset(odm_pipe, 0, sizeof(*odm_pipe));
1999 odm_pipe = next_odm_pipe;
2001 memset(del_pipe, 0, sizeof(*del_pipe));
2003 for (i = 0; i < new_ctx->stream_count; i++)
2004 if (new_ctx->streams[i] == stream)
2007 if (new_ctx->streams[i] != stream) {
2008 DC_ERROR("Context doesn't have stream %p !\n", stream);
2009 return DC_ERROR_UNEXPECTED;
2012 dc_stream_release(new_ctx->streams[i]);
2013 new_ctx->stream_count--;
2015 /* Trim back arrays */
2016 for (; i < new_ctx->stream_count; i++) {
2017 new_ctx->streams[i] = new_ctx->streams[i + 1];
2018 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
2021 new_ctx->streams[new_ctx->stream_count] = NULL;
2023 &new_ctx->stream_status[new_ctx->stream_count],
2025 sizeof(new_ctx->stream_status[0]));
2030 static struct dc_stream_state *find_pll_sharable_stream(
2031 struct dc_stream_state *stream_needs_pll,
2032 struct dc_state *context)
2036 for (i = 0; i < context->stream_count; i++) {
2037 struct dc_stream_state *stream_has_pll = context->streams[i];
2039 /* We are looking for non dp, non virtual stream */
2040 if (resource_are_streams_timing_synchronizable(
2041 stream_needs_pll, stream_has_pll)
2042 && !dc_is_dp_signal(stream_has_pll->signal)
2043 && stream_has_pll->link->connector_signal
2044 != SIGNAL_TYPE_VIRTUAL)
2045 return stream_has_pll;
2052 static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
2054 uint32_t pix_clk = timing->pix_clk_100hz;
2055 uint32_t normalized_pix_clk = pix_clk;
2057 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2059 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
2060 switch (timing->display_color_depth) {
2061 case COLOR_DEPTH_666:
2062 case COLOR_DEPTH_888:
2063 normalized_pix_clk = pix_clk;
2065 case COLOR_DEPTH_101010:
2066 normalized_pix_clk = (pix_clk * 30) / 24;
2068 case COLOR_DEPTH_121212:
2069 normalized_pix_clk = (pix_clk * 36) / 24;
2071 case COLOR_DEPTH_161616:
2072 normalized_pix_clk = (pix_clk * 48) / 24;
2079 return normalized_pix_clk;
2082 static void calculate_phy_pix_clks(struct dc_stream_state *stream)
2084 /* update actual pixel clock on all streams */
2085 if (dc_is_hdmi_signal(stream->signal))
2086 stream->phy_pix_clk = get_norm_pix_clk(
2087 &stream->timing) / 10;
2089 stream->phy_pix_clk =
2090 stream->timing.pix_clk_100hz / 10;
2092 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2093 stream->phy_pix_clk *= 2;
2096 static int acquire_resource_from_hw_enabled_state(
2097 struct resource_context *res_ctx,
2098 const struct resource_pool *pool,
2099 struct dc_stream_state *stream)
2101 struct dc_link *link = stream->link;
2102 unsigned int i, inst, tg_inst = 0;
2104 /* Check for enabled DIG to identify enabled display */
2105 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
2108 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2110 if (inst == ENGINE_ID_UNKNOWN)
2113 for (i = 0; i < pool->stream_enc_count; i++) {
2114 if (pool->stream_enc[i]->id == inst) {
2115 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
2116 pool->stream_enc[i]);
2121 // tg_inst not found
2122 if (i == pool->stream_enc_count)
2125 if (tg_inst >= pool->timing_generator_count)
2128 if (!res_ctx->pipe_ctx[tg_inst].stream) {
2129 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
2131 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2132 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
2133 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
2134 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
2135 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
2136 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
2137 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
2139 if (pool->dpps[tg_inst]) {
2140 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
2142 // Read DPP->MPCC->OPP Pipe from HW State
2143 if (pool->mpc->funcs->read_mpcc_state) {
2144 struct mpcc_state s = {0};
2146 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
2148 if (s.dpp_id < MAX_MPCC)
2149 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id;
2151 if (s.bot_mpcc_id < MAX_MPCC)
2152 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
2153 &pool->mpc->mpcc_array[s.bot_mpcc_id];
2155 if (s.opp_id < MAX_OPP)
2156 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
2159 pipe_ctx->pipe_idx = tg_inst;
2161 pipe_ctx->stream = stream;
2168 static void mark_seamless_boot_stream(
2169 const struct dc *dc,
2170 struct dc_stream_state *stream)
2172 struct dc_bios *dcb = dc->ctx->dc_bios;
2174 if (dc->config.allow_seamless_boot_optimization &&
2175 !dcb->funcs->is_accelerated_mode(dcb)) {
2176 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
2177 stream->apply_seamless_boot_optimization = true;
2181 enum dc_status resource_map_pool_resources(
2182 const struct dc *dc,
2183 struct dc_state *context,
2184 struct dc_stream_state *stream)
2186 const struct resource_pool *pool = dc->res_pool;
2188 struct dc_context *dc_ctx = dc->ctx;
2189 struct pipe_ctx *pipe_ctx = NULL;
2192 calculate_phy_pix_clks(stream);
2194 mark_seamless_boot_stream(dc, stream);
2196 if (stream->apply_seamless_boot_optimization) {
2197 pipe_idx = acquire_resource_from_hw_enabled_state(
2202 /* hw resource was assigned to other stream */
2203 stream->apply_seamless_boot_optimization = false;
2207 /* acquire new resources */
2208 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
2210 #ifdef CONFIG_DRM_AMD_DC_DCN
2212 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
2215 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
2216 return DC_NO_CONTROLLER_RESOURCE;
2218 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2220 pipe_ctx->stream_res.stream_enc =
2221 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
2222 &context->res_ctx, pool, stream);
2224 if (!pipe_ctx->stream_res.stream_enc)
2225 return DC_NO_STREAM_ENC_RESOURCE;
2227 update_stream_engine_usage(
2228 &context->res_ctx, pool,
2229 pipe_ctx->stream_res.stream_enc,
2232 #if defined(CONFIG_DRM_AMD_DC_DCN)
2233 /* Allocate DP HPO Stream Encoder based on signal, hw capabilities
2236 if (dc_is_dp_signal(stream->signal) &&
2238 struct dc_link_settings link_settings = {0};
2240 decide_link_settings(stream, &link_settings);
2241 if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING) {
2242 pipe_ctx->stream_res.hpo_dp_stream_enc =
2243 find_first_free_match_hpo_dp_stream_enc_for_link(
2244 &context->res_ctx, pool, stream);
2246 if (!pipe_ctx->stream_res.hpo_dp_stream_enc)
2247 return DC_NO_STREAM_ENC_RESOURCE;
2249 update_hpo_dp_stream_engine_usage(
2250 &context->res_ctx, pool,
2251 pipe_ctx->stream_res.hpo_dp_stream_enc,
2253 if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))
2254 return DC_NO_LINK_ENC_RESOURCE;
2259 /* TODO: Add check if ASIC support and EDID audio */
2260 if (!stream->converter_disable_audio &&
2261 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
2262 stream->audio_info.mode_count && stream->audio_info.flags.all) {
2263 pipe_ctx->stream_res.audio = find_first_free_audio(
2264 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
2267 * Audio assigned in order first come first get.
2268 * There are asics which has number of audio
2269 * resources less then number of pipes
2271 if (pipe_ctx->stream_res.audio)
2272 update_audio_usage(&context->res_ctx, pool,
2273 pipe_ctx->stream_res.audio, true);
2276 /* Add ABM to the resource if on EDP */
2277 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {
2278 #if defined(CONFIG_DRM_AMD_DC_DCN)
2280 pipe_ctx->stream_res.abm = pool->abm;
2282 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
2284 pipe_ctx->stream_res.abm = pool->abm;
2288 for (i = 0; i < context->stream_count; i++)
2289 if (context->streams[i] == stream) {
2290 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
2291 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
2292 context->stream_status[i].audio_inst =
2293 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2298 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2299 return DC_ERROR_UNEXPECTED;
2303 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2304 * Is a shallow copy. Increments refcounts on existing streams and planes.
2305 * @dc: copy out of dc->current_state
2306 * @dst_ctx: copy into this
2308 void dc_resource_state_copy_construct_current(
2309 const struct dc *dc,
2310 struct dc_state *dst_ctx)
2312 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
2316 void dc_resource_state_construct(
2317 const struct dc *dc,
2318 struct dc_state *dst_ctx)
2320 dst_ctx->clk_mgr = dc->clk_mgr;
2322 /* Initialise DIG link encoder resource tracking variables. */
2323 link_enc_cfg_init(dc, dst_ctx);
2327 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
2329 return dc->res_pool->res_cap->num_dsc > 0;
2334 * dc_validate_global_state() - Determine if HW can support a given state
2335 * Checks HW resource availability and bandwidth requirement.
2336 * @dc: dc struct for this driver
2337 * @new_ctx: state to be validated
2338 * @fast_validate: set to true if only yes/no to support matters
2340 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2342 enum dc_status dc_validate_global_state(
2344 struct dc_state *new_ctx,
2347 enum dc_status result = DC_ERROR_UNEXPECTED;
2351 return DC_ERROR_UNEXPECTED;
2353 if (dc->res_pool->funcs->validate_global) {
2354 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2355 if (result != DC_OK)
2359 for (i = 0; i < new_ctx->stream_count; i++) {
2360 struct dc_stream_state *stream = new_ctx->streams[i];
2362 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2363 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2365 if (pipe_ctx->stream != stream)
2368 if (dc->res_pool->funcs->patch_unknown_plane_state &&
2369 pipe_ctx->plane_state &&
2370 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2371 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);
2372 if (result != DC_OK)
2376 /* Switch to dp clock source only if there is
2377 * no non dp stream that shares the same timing
2378 * with the dp stream.
2380 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2381 !find_pll_sharable_stream(stream, new_ctx)) {
2383 resource_unreference_clock_source(
2386 pipe_ctx->clock_source);
2388 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2389 resource_reference_clock_source(
2392 pipe_ctx->clock_source);
2397 result = resource_build_scaling_params_for_context(dc, new_ctx);
2399 if (result == DC_OK)
2400 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
2401 result = DC_FAIL_BANDWIDTH_VALIDATE;
2403 #if defined(CONFIG_DRM_AMD_DC_DCN)
2405 * Only update link encoder to stream assignment after bandwidth validation passed.
2406 * TODO: Split out assignment and validation.
2408 if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false)
2409 dc->res_pool->funcs->link_encs_assign(
2410 dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
2416 static void patch_gamut_packet_checksum(
2417 struct dc_info_packet *gamut_packet)
2419 /* For gamut we recalc checksum */
2420 if (gamut_packet->valid) {
2421 uint8_t chk_sum = 0;
2425 /*start of the Gamut data. */
2426 ptr = &gamut_packet->sb[3];
2428 for (i = 0; i <= gamut_packet->sb[1]; i++)
2431 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
2435 static void set_avi_info_frame(
2436 struct dc_info_packet *info_packet,
2437 struct pipe_ctx *pipe_ctx)
2439 struct dc_stream_state *stream = pipe_ctx->stream;
2440 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
2441 uint32_t pixel_encoding = 0;
2442 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2443 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2445 uint8_t itc_value = 0;
2446 uint8_t cn0_cn1 = 0;
2447 unsigned int cn0_cn1_value = 0;
2448 uint8_t *check_sum = NULL;
2449 uint8_t byte_index = 0;
2450 union hdmi_info_packet hdmi_info;
2451 union display_content_support support = {0};
2452 unsigned int vic = pipe_ctx->stream->timing.vic;
2453 enum dc_timing_3d_format format;
2455 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2457 color_space = pipe_ctx->stream->output_color_space;
2458 if (color_space == COLOR_SPACE_UNKNOWN)
2459 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
2460 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
2462 /* Initialize header */
2463 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
2464 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2465 * not be used in HDMI 2.0 (Section 10.1) */
2466 hdmi_info.bits.header.version = 2;
2467 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
2470 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2471 * according to HDMI 2.0 spec (Section 10.1)
2474 switch (stream->timing.pixel_encoding) {
2475 case PIXEL_ENCODING_YCBCR422:
2479 case PIXEL_ENCODING_YCBCR444:
2482 case PIXEL_ENCODING_YCBCR420:
2486 case PIXEL_ENCODING_RGB:
2491 /* Y0_Y1_Y2 : The pixel encoding */
2492 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
2493 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
2495 /* A0 = 1 Active Format Information valid */
2496 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
2498 /* B0, B1 = 3; Bar info data is valid */
2499 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
2501 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
2503 /* S0, S1 : Underscan / Overscan */
2504 /* TODO: un-hardcode scan type */
2505 scan_type = SCANNING_TYPE_UNDERSCAN;
2506 hdmi_info.bits.S0_S1 = scan_type;
2508 /* C0, C1 : Colorimetry */
2509 if (color_space == COLOR_SPACE_YCBCR709 ||
2510 color_space == COLOR_SPACE_YCBCR709_LIMITED)
2511 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
2512 else if (color_space == COLOR_SPACE_YCBCR601 ||
2513 color_space == COLOR_SPACE_YCBCR601_LIMITED)
2514 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
2516 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
2518 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
2519 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2520 color_space == COLOR_SPACE_2020_YCBCR) {
2521 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2522 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
2523 } else if (color_space == COLOR_SPACE_ADOBERGB) {
2524 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2525 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
2528 /* TODO: un-hardcode aspect ratio */
2529 aspect = stream->timing.aspect_ratio;
2532 case ASPECT_RATIO_4_3:
2533 case ASPECT_RATIO_16_9:
2534 hdmi_info.bits.M0_M1 = aspect;
2537 case ASPECT_RATIO_NO_DATA:
2538 case ASPECT_RATIO_64_27:
2539 case ASPECT_RATIO_256_135:
2541 hdmi_info.bits.M0_M1 = 0;
2544 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
2545 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
2547 /* TODO: un-hardcode cn0_cn1 and itc */
2555 support = stream->content_support;
2558 if (!support.bits.valid_content_type) {
2561 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2562 if (support.bits.graphics_content == 1) {
2565 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2566 if (support.bits.photo_content == 1) {
2572 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2573 if (support.bits.cinema_content == 1) {
2579 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2580 if (support.bits.game_content == 1) {
2588 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2589 hdmi_info.bits.ITC = itc_value;
2592 if (stream->qs_bit == 1) {
2593 if (color_space == COLOR_SPACE_SRGB ||
2594 color_space == COLOR_SPACE_2020_RGB_FULLRANGE)
2595 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2596 else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2597 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
2598 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2600 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2602 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2604 /* TODO : We should handle YCC quantization */
2605 /* but we do not have matrix calculation */
2606 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2609 format = stream->timing.timing_3d_format;
2610 /*todo, add 3DStereo support*/
2611 if (format != TIMING_3D_FORMAT_NONE) {
2612 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
2613 switch (pipe_ctx->stream->timing.hdmi_vic) {
2630 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
2631 hdmi_info.bits.VIC0_VIC7 = vic;
2633 hdmi_info.bits.header.version = 3;
2634 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2635 * the Source shall use 20 AVI InfoFrame Version 4
2637 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2638 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2639 hdmi_info.bits.header.version = 4;
2640 hdmi_info.bits.header.length = 14;
2644 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2645 * repetition start from 1 */
2646 hdmi_info.bits.PR0_PR3 = 0;
2649 * barTop: Line Number of End of Top Bar.
2650 * barBottom: Line Number of Start of Bottom Bar.
2651 * barLeft: Pixel Number of End of Left Bar.
2652 * barRight: Pixel Number of Start of Right Bar. */
2653 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2654 hdmi_info.bits.bar_bottom = (stream->timing.v_total
2655 - stream->timing.v_border_bottom + 1);
2656 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2657 hdmi_info.bits.bar_right = (stream->timing.h_total
2658 - stream->timing.h_border_right + 1);
2660 /* Additional Colorimetry Extension
2661 * Used in conduction with C0-C1 and EC0-EC2
2662 * 0 = DCI-P3 RGB (D65)
2663 * 1 = DCI-P3 RGB (theater)
2665 hdmi_info.bits.ACE0_ACE3 = 0;
2667 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
2668 check_sum = &hdmi_info.packet_raw_data.sb[0];
2670 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
2672 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
2673 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
2675 /* one byte complement */
2676 *check_sum = (uint8_t) (0x100 - *check_sum);
2678 /* Store in hw_path_mode */
2679 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2680 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2681 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
2683 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2684 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
2686 info_packet->valid = true;
2689 static void set_vendor_info_packet(
2690 struct dc_info_packet *info_packet,
2691 struct dc_stream_state *stream)
2693 /* SPD info packet for FreeSync */
2695 /* Check if Freesync is supported. Return if false. If true,
2696 * set the corresponding bit in the info packet
2698 if (!stream->vsp_infopacket.valid)
2701 *info_packet = stream->vsp_infopacket;
2704 static void set_spd_info_packet(
2705 struct dc_info_packet *info_packet,
2706 struct dc_stream_state *stream)
2708 /* SPD info packet for FreeSync */
2710 /* Check if Freesync is supported. Return if false. If true,
2711 * set the corresponding bit in the info packet
2713 if (!stream->vrr_infopacket.valid)
2716 *info_packet = stream->vrr_infopacket;
2719 static void set_hdr_static_info_packet(
2720 struct dc_info_packet *info_packet,
2721 struct dc_stream_state *stream)
2723 /* HDR Static Metadata info packet for HDR10 */
2725 if (!stream->hdr_static_metadata.valid ||
2726 stream->use_dynamic_meta)
2729 *info_packet = stream->hdr_static_metadata;
2732 static void set_vsc_info_packet(
2733 struct dc_info_packet *info_packet,
2734 struct dc_stream_state *stream)
2736 if (!stream->vsc_infopacket.valid)
2739 *info_packet = stream->vsc_infopacket;
2742 void dc_resource_state_destruct(struct dc_state *context)
2746 for (i = 0; i < context->stream_count; i++) {
2747 for (j = 0; j < context->stream_status[i].plane_count; j++)
2748 dc_plane_state_release(
2749 context->stream_status[i].plane_states[j]);
2751 context->stream_status[i].plane_count = 0;
2752 dc_stream_release(context->streams[i]);
2753 context->streams[i] = NULL;
2755 context->stream_count = 0;
2758 void dc_resource_state_copy_construct(
2759 const struct dc_state *src_ctx,
2760 struct dc_state *dst_ctx)
2763 struct kref refcount = dst_ctx->refcount;
2765 *dst_ctx = *src_ctx;
2767 for (i = 0; i < MAX_PIPES; i++) {
2768 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2770 if (cur_pipe->top_pipe)
2771 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2773 if (cur_pipe->bottom_pipe)
2774 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2776 if (cur_pipe->next_odm_pipe)
2777 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2779 if (cur_pipe->prev_odm_pipe)
2780 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
2783 for (i = 0; i < dst_ctx->stream_count; i++) {
2784 dc_stream_retain(dst_ctx->streams[i]);
2785 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2786 dc_plane_state_retain(
2787 dst_ctx->stream_status[i].plane_states[j]);
2790 /* context refcount should not be overridden */
2791 dst_ctx->refcount = refcount;
2795 struct clock_source *dc_resource_find_first_free_pll(
2796 struct resource_context *res_ctx,
2797 const struct resource_pool *pool)
2801 for (i = 0; i < pool->clk_src_count; ++i) {
2802 if (res_ctx->clock_source_ref_count[i] == 0)
2803 return pool->clock_sources[i];
2809 void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2811 enum signal_type signal = SIGNAL_TYPE_NONE;
2812 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
2814 /* default all packets to invalid */
2815 info->avi.valid = false;
2816 info->gamut.valid = false;
2817 info->vendor.valid = false;
2818 info->spd.valid = false;
2819 info->hdrsmd.valid = false;
2820 info->vsc.valid = false;
2822 signal = pipe_ctx->stream->signal;
2824 /* HDMi and DP have different info packets*/
2825 if (dc_is_hdmi_signal(signal)) {
2826 set_avi_info_frame(&info->avi, pipe_ctx);
2828 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2830 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2832 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
2834 } else if (dc_is_dp_signal(signal)) {
2835 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2837 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2839 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
2842 patch_gamut_packet_checksum(&info->gamut);
2845 enum dc_status resource_map_clock_resources(
2846 const struct dc *dc,
2847 struct dc_state *context,
2848 struct dc_stream_state *stream)
2850 /* acquire new resources */
2851 const struct resource_pool *pool = dc->res_pool;
2852 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2853 &context->res_ctx, stream);
2856 return DC_ERROR_UNEXPECTED;
2858 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2859 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2860 pipe_ctx->clock_source = pool->dp_clock_source;
2862 pipe_ctx->clock_source = NULL;
2864 if (!dc->config.disable_disp_pll_sharing)
2865 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
2869 if (pipe_ctx->clock_source == NULL)
2870 pipe_ctx->clock_source =
2871 dc_resource_find_first_free_pll(
2876 if (pipe_ctx->clock_source == NULL)
2877 return DC_NO_CLOCK_SOURCE_RESOURCE;
2879 resource_reference_clock_source(
2880 &context->res_ctx, pool,
2881 pipe_ctx->clock_source);
2887 * Note: We need to disable output if clock sources change,
2888 * since bios does optimization and doesn't apply if changing
2889 * PHY when not already disabled.
2891 bool pipe_need_reprogram(
2892 struct pipe_ctx *pipe_ctx_old,
2893 struct pipe_ctx *pipe_ctx)
2895 if (!pipe_ctx_old->stream)
2898 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2901 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2904 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
2907 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2908 && pipe_ctx_old->stream != pipe_ctx->stream)
2911 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
2914 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2917 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2920 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2921 false == pipe_ctx_old->stream->dpms_off)
2924 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
2927 #if defined(CONFIG_DRM_AMD_DC_DCN)
2928 if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)
2930 if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc)
2934 /* DIG link encoder resource assignment for stream changed. */
2935 if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) {
2936 bool need_reprogram = false;
2937 struct dc *dc = pipe_ctx_old->stream->ctx->dc;
2938 enum link_enc_cfg_mode mode = dc->current_state->res_ctx.link_enc_cfg_ctx.mode;
2940 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;
2941 if (link_enc_cfg_get_link_enc_used_by_stream(dc, pipe_ctx_old->stream) != pipe_ctx->stream->link_enc)
2942 need_reprogram = true;
2943 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = mode;
2945 return need_reprogram;
2951 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
2952 struct bit_depth_reduction_params *fmt_bit_depth)
2954 enum dc_dither_option option = stream->dither_option;
2955 enum dc_pixel_encoding pixel_encoding =
2956 stream->timing.pixel_encoding;
2958 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2960 if (option == DITHER_OPTION_DEFAULT) {
2961 switch (stream->timing.display_color_depth) {
2962 case COLOR_DEPTH_666:
2963 option = DITHER_OPTION_SPATIAL6;
2965 case COLOR_DEPTH_888:
2966 option = DITHER_OPTION_SPATIAL8;
2968 case COLOR_DEPTH_101010:
2969 option = DITHER_OPTION_SPATIAL10;
2972 option = DITHER_OPTION_DISABLE;
2976 if (option == DITHER_OPTION_DISABLE)
2979 if (option == DITHER_OPTION_TRUN6) {
2980 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2981 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2982 } else if (option == DITHER_OPTION_TRUN8 ||
2983 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2984 option == DITHER_OPTION_TRUN8_FM6) {
2985 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2986 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2987 } else if (option == DITHER_OPTION_TRUN10 ||
2988 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2989 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2990 option == DITHER_OPTION_TRUN10_FM8 ||
2991 option == DITHER_OPTION_TRUN10_FM6 ||
2992 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2993 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2994 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2997 /* special case - Formatter can only reduce by 4 bits at most.
2998 * When reducing from 12 to 6 bits,
2999 * HW recommends we use trunc with round mode
3000 * (if we did nothing, trunc to 10 bits would be used)
3001 * note that any 12->10 bit reduction is ignored prior to DCE8,
3002 * as the input was 10 bits.
3004 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
3005 option == DITHER_OPTION_SPATIAL6 ||
3006 option == DITHER_OPTION_FM6) {
3007 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
3008 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
3009 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
3013 * note that spatial modes 1-3 are never used
3015 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
3016 option == DITHER_OPTION_SPATIAL6 ||
3017 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
3018 option == DITHER_OPTION_TRUN8_SPATIAL6) {
3019 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
3020 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
3021 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
3022 fmt_bit_depth->flags.RGB_RANDOM =
3023 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
3024 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
3025 option == DITHER_OPTION_SPATIAL8 ||
3026 option == DITHER_OPTION_SPATIAL8_FM6 ||
3027 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
3028 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
3029 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
3030 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
3031 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
3032 fmt_bit_depth->flags.RGB_RANDOM =
3033 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
3034 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
3035 option == DITHER_OPTION_SPATIAL10 ||
3036 option == DITHER_OPTION_SPATIAL10_FM8 ||
3037 option == DITHER_OPTION_SPATIAL10_FM6) {
3038 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
3039 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
3040 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
3041 fmt_bit_depth->flags.RGB_RANDOM =
3042 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
3045 if (option == DITHER_OPTION_SPATIAL6 ||
3046 option == DITHER_OPTION_SPATIAL8 ||
3047 option == DITHER_OPTION_SPATIAL10) {
3048 fmt_bit_depth->flags.FRAME_RANDOM = 0;
3050 fmt_bit_depth->flags.FRAME_RANDOM = 1;
3053 //////////////////////
3054 //// temporal dither
3055 //////////////////////
3056 if (option == DITHER_OPTION_FM6 ||
3057 option == DITHER_OPTION_SPATIAL8_FM6 ||
3058 option == DITHER_OPTION_SPATIAL10_FM6 ||
3059 option == DITHER_OPTION_TRUN10_FM6 ||
3060 option == DITHER_OPTION_TRUN8_FM6 ||
3061 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
3062 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
3063 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
3064 } else if (option == DITHER_OPTION_FM8 ||
3065 option == DITHER_OPTION_SPATIAL10_FM8 ||
3066 option == DITHER_OPTION_TRUN10_FM8) {
3067 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
3068 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
3069 } else if (option == DITHER_OPTION_FM10) {
3070 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
3071 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
3074 fmt_bit_depth->pixel_encoding = pixel_encoding;
3077 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
3079 struct dc_link *link = stream->link;
3080 struct timing_generator *tg = dc->res_pool->timing_generators[0];
3081 enum dc_status res = DC_OK;
3083 calculate_phy_pix_clks(stream);
3085 if (!tg->funcs->validate_timing(tg, &stream->timing))
3086 res = DC_FAIL_CONTROLLER_VALIDATE;
3089 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
3090 !link->link_enc->funcs->validate_output_with_stream(
3091 link->link_enc, stream))
3092 res = DC_FAIL_ENC_VALIDATE;
3095 /* TODO: validate audio ASIC caps, encoder */
3098 res = dc_link_validate_mode_timing(stream,
3105 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
3107 enum dc_status res = DC_OK;
3109 /* check if surface has invalid dimensions */
3110 if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 ||
3111 plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0)
3112 return DC_FAIL_SURFACE_VALIDATE;
3114 /* TODO For now validates pixel format only */
3115 if (dc->res_pool->funcs->validate_plane)
3116 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
3121 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
3124 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
3126 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
3127 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
3129 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
3130 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
3131 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
3132 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
3134 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
3135 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
3136 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
3137 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
3138 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
3139 #if defined(CONFIG_DRM_AMD_DC_DCN)
3140 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
3141 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
3144 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
3145 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
3146 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
3147 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
3150 ASSERT_CRITICAL(false);
3154 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
3157 if (modes->sample_rates.rate.RATE_192)
3159 if (modes->sample_rates.rate.RATE_176_4)
3161 if (modes->sample_rates.rate.RATE_96)
3163 if (modes->sample_rates.rate.RATE_88_2)
3165 if (modes->sample_rates.rate.RATE_48)
3167 if (modes->sample_rates.rate.RATE_44_1)
3169 if (modes->sample_rates.rate.RATE_32)
3172 /*original logic when no audio info*/
3176 void get_audio_check(struct audio_info *aud_modes,
3177 struct audio_check *audio_chk)
3180 unsigned int max_sample_rate = 0;
3183 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
3185 audio_chk->max_audiosample_rate = 0;
3186 for (i = 0; i < aud_modes->mode_count; i++) {
3187 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
3188 if (audio_chk->max_audiosample_rate < max_sample_rate)
3189 audio_chk->max_audiosample_rate = max_sample_rate;
3190 /*dts takes the same as type 2: AP = 0.25*/
3192 /*check which one take more bandwidth*/
3193 if (audio_chk->max_audiosample_rate > 192000)
3194 audio_chk->audio_packet_type = 0x9;/*AP =1*/
3195 audio_chk->acat = 0;/*not support*/
3199 #if defined(CONFIG_DRM_AMD_DC_DCN)
3200 struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
3201 const struct resource_context *res_ctx,
3202 const struct resource_pool *pool,
3203 const struct dc_link *link)
3205 struct hpo_dp_link_encoder *hpo_dp_link_enc = NULL;
3208 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link);
3211 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
3214 hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
3216 return hpo_dp_link_enc;
3220 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
3221 struct dc_state *context)
3224 struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd;
3226 /* If pipe backend is reset, need to reset pipe syncd status */
3227 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3228 pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i];
3229 pipe_ctx = &context->res_ctx.pipe_ctx[i];
3231 if (!pipe_ctx_old->stream)
3234 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
3237 if (!pipe_ctx->stream ||
3238 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
3240 /* Reset all the syncd pipes from the disabled pipe */
3241 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3242 pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j];
3243 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_syncd) == pipe_ctx_old->pipe_idx) ||
3244 !IS_PIPE_SYNCD_VALID(pipe_ctx_syncd))
3245 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_syncd, j);
3251 void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
3252 struct dc_state *context,
3253 uint8_t disabled_master_pipe_idx)
3256 struct pipe_ctx *pipe_ctx, *pipe_ctx_check;
3258 pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];
3259 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) ||
3260 !IS_PIPE_SYNCD_VALID(pipe_ctx))
3261 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx);
3263 /* for the pipe disabled, check if any slave pipe exists and assert */
3264 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3265 pipe_ctx_check = &context->res_ctx.pipe_ctx[i];
3267 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) &&
3268 IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx))
3269 DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n",
3270 i, disabled_master_pipe_idx);
3274 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)
3276 /* TODO - get transmitter to phy idx mapping from DMUB */
3277 uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
3279 #if defined(CONFIG_DRM_AMD_DC_DCN)
3280 if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
3281 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
3282 switch (transmitter) {
3283 case TRANSMITTER_UNIPHY_A:
3286 case TRANSMITTER_UNIPHY_B:
3289 case TRANSMITTER_UNIPHY_C:
3292 case TRANSMITTER_UNIPHY_D:
3295 case TRANSMITTER_UNIPHY_E: