drivers/gpu/drm/amd/display/dc/core/dc_resource.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "resource.h"
  31 #include "include/irq_service_interface.h"
  32 #include "link_encoder.h"
  33 #include "stream_encoder.h"
  34 #include "opp.h"
  35 #include "timing_generator.h"
  36 #include "transform.h"
  37 #include "dccg.h"
  38 #include "dchubbub.h"
  39 #include "dpp.h"
  40 #include "core_types.h"
  41 #include "set_mode_types.h"
  42 #include "virtual/virtual_stream_encoder.h"
  43 #include "dpcd_defs.h"
  44
  45 #include "dce80/dce80_resource.h"
  46 #include "dce100/dce100_resource.h"
  47 #include "dce110/dce110_resource.h"
  48 #include "dce112/dce112_resource.h"
  49 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  50 #include "dcn10/dcn10_resource.h"
  51 #endif
  52 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  53 #include "dcn20/dcn20_resource.h"
  54 #endif
  55 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
  56 #include "dcn21/dcn21_resource.h"
  57 #endif
  58 #include "dce120/dce120_resource.h"
  59
  60 #define DC_LOGGER_INIT(logger)
  61
  62 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
  63 {
  64         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
  65         switch (asic_id.chip_family) {
  66
  67         case FAMILY_CI:
  68                 dc_version = DCE_VERSION_8_0;
  69                 break;
  70         case FAMILY_KV:
  71                 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
  72                     ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
  73                     ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
  74                         dc_version = DCE_VERSION_8_3;
  75                 else
  76                         dc_version = DCE_VERSION_8_1;
  77                 break;
  78         case FAMILY_CZ:
  79                 dc_version = DCE_VERSION_11_0;
  80                 break;
  81
  82         case FAMILY_VI:
  83                 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
  84                                 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
  85                         dc_version = DCE_VERSION_10_0;
  86                         break;
  87                 }
  88                 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
  89                                 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
  90                                 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
  91                         dc_version = DCE_VERSION_11_2;
  92                 }
  93                 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
  94                         dc_version = DCE_VERSION_11_22;
  95                 break;
  96         case FAMILY_AI:
  97                 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
  98                         dc_version = DCE_VERSION_12_1;
  99                 else
 100                         dc_version = DCE_VERSION_12_0;
 101                 break;
 102 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 103         case FAMILY_RV:
 104                 dc_version = DCN_VERSION_1_0;
 105                 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
 106                         dc_version = DCN_VERSION_1_01;
 107 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 108                 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
 109                         dc_version = DCN_VERSION_2_1;
 110 #endif
 111                 break;
 112 #endif
 113
 114 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 115         case FAMILY_NV:
 116                 dc_version = DCN_VERSION_2_0;
 117                 break;
 118 #endif
 119         default:
 120                 dc_version = DCE_VERSION_UNKNOWN;
 121                 break;
 122         }
 123         return dc_version;
 124 }
 125
 126 struct resource_pool *dc_create_resource_pool(struct dc  *dc,
 127                                               const struct dc_init_data *init_data,
 128                                               enum dce_version dc_version)
 129 {
 130         struct resource_pool *res_pool = NULL;
 131
 132         switch (dc_version) {
 133         case DCE_VERSION_8_0:
 134                 res_pool = dce80_create_resource_pool(
 135                                 init_data->num_virtual_links, dc);
 136                 break;
 137         case DCE_VERSION_8_1:
 138                 res_pool = dce81_create_resource_pool(
 139                                 init_data->num_virtual_links, dc);
 140                 break;
 141         case DCE_VERSION_8_3:
 142                 res_pool = dce83_create_resource_pool(
 143                                 init_data->num_virtual_links, dc);
 144                 break;
 145         case DCE_VERSION_10_0:
 146                 res_pool = dce100_create_resource_pool(
 147                                 init_data->num_virtual_links, dc);
 148                 break;
 149         case DCE_VERSION_11_0:
 150                 res_pool = dce110_create_resource_pool(
 151                                 init_data->num_virtual_links, dc,
 152                                 init_data->asic_id);
 153                 break;
 154         case DCE_VERSION_11_2:
 155         case DCE_VERSION_11_22:
 156                 res_pool = dce112_create_resource_pool(
 157                                 init_data->num_virtual_links, dc);
 158                 break;
 159         case DCE_VERSION_12_0:
 160         case DCE_VERSION_12_1:
 161                 res_pool = dce120_create_resource_pool(
 162                                 init_data->num_virtual_links, dc);
 163                 break;
 164
 165 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 166         case DCN_VERSION_1_0:
 167         case DCN_VERSION_1_01:
 168                 res_pool = dcn10_create_resource_pool(init_data, dc);
 169                 break;
 170 #endif
 171
 172
 173 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 174         case DCN_VERSION_2_0:
 175                 res_pool = dcn20_create_resource_pool(init_data, dc);
 176                 break;
 177 #endif
 178 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 179         case DCN_VERSION_2_1:
 180                 res_pool = dcn21_create_resource_pool(init_data, dc);
 181                 break;
 182 #endif
 183
 184         default:
 185                 break;
 186         }
 187
 188         if (res_pool != NULL) {
 189                 if (dc->ctx->dc_bios->fw_info_valid) {
 190                         res_pool->ref_clocks.xtalin_clock_inKhz =
 191                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 192                         /* initialize with firmware data first, no all
 193                          * ASIC have DCCG SW component. FPGA or
 194                          * simulation need initialization of
 195                          * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
 196                          * with xtalin_clock_inKhz
 197                          */
 198                         res_pool->ref_clocks.dccg_ref_clock_inKhz =
 199                                 res_pool->ref_clocks.xtalin_clock_inKhz;
 200                         res_pool->ref_clocks.dchub_ref_clock_inKhz =
 201                                 res_pool->ref_clocks.xtalin_clock_inKhz;
 202                 } else
 203                         ASSERT_CRITICAL(false);
 204         }
 205
 206         return res_pool;
 207 }
 208
 209 void dc_destroy_resource_pool(struct dc  *dc)
 210 {
 211         if (dc) {
 212                 if (dc->res_pool)
 213                         dc->res_pool->funcs->destroy(&dc->res_pool);
 214
 215                 kfree(dc->hwseq);
 216         }
 217 }
 218
 219 static void update_num_audio(
 220         const struct resource_straps *straps,
 221         unsigned int *num_audio,
 222         struct audio_support *aud_support)
 223 {
 224         aud_support->dp_audio = true;
 225         aud_support->hdmi_audio_native = false;
 226         aud_support->hdmi_audio_on_dongle = false;
 227
 228         if (straps->hdmi_disable == 0) {
 229                 if (straps->dc_pinstraps_audio & 0x2) {
 230                         aud_support->hdmi_audio_on_dongle = true;
 231                         aud_support->hdmi_audio_native = true;
 232                 }
 233         }
 234
 235         switch (straps->audio_stream_number) {
 236         case 0: /* multi streams supported */
 237                 break;
 238         case 1: /* multi streams not supported */
 239                 *num_audio = 1;
 240                 break;
 241         default:
 242                 DC_ERR("DC: unexpected audio fuse!\n");
 243         }
 244 }
 245
 246 bool resource_construct(
 247         unsigned int num_virtual_links,
 248         struct dc  *dc,
 249         struct resource_pool *pool,
 250         const struct resource_create_funcs *create_funcs)
 251 {
 252         struct dc_context *ctx = dc->ctx;
 253         const struct resource_caps *caps = pool->res_cap;
 254         int i;
 255         unsigned int num_audio = caps->num_audio;
 256         struct resource_straps straps = {0};
 257
 258         if (create_funcs->read_dce_straps)
 259                 create_funcs->read_dce_straps(dc->ctx, &straps);
 260
 261         pool->audio_count = 0;
 262         if (create_funcs->create_audio) {
 263                 /* find the total number of streams available via the
 264                  * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
 265                  * registers (one for each pin) starting from pin 1
 266                  * up to the max number of audio pins.
 267                  * We stop on the first pin where
 268                  * PORT_CONNECTIVITY == 1 (as instructed by HW team).
 269                  */
 270                 update_num_audio(&straps, &num_audio, &pool->audio_support);
 271                 for (i = 0; i < caps->num_audio; i++) {
 272                         struct audio *aud = create_funcs->create_audio(ctx, i);
 273
 274                         if (aud == NULL) {
 275                                 DC_ERR("DC: failed to create audio!\n");
 276                                 return false;
 277                         }
 278                         if (!aud->funcs->endpoint_valid(aud)) {
 279                                 aud->funcs->destroy(&aud);
 280                                 break;
 281                         }
 282                         pool->audios[i] = aud;
 283                         pool->audio_count++;
 284                 }
 285         }
 286
 287         pool->stream_enc_count = 0;
 288         if (create_funcs->create_stream_encoder) {
 289                 for (i = 0; i < caps->num_stream_encoder; i++) {
 290                         pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
 291                         if (pool->stream_enc[i] == NULL)
 292                                 DC_ERR("DC: failed to create stream_encoder!\n");
 293                         pool->stream_enc_count++;
 294                 }
 295         }
 296
 297         dc->caps.dynamic_audio = false;
 298         if (pool->audio_count < pool->stream_enc_count) {
 299                 dc->caps.dynamic_audio = true;
 300         }
 301         for (i = 0; i < num_virtual_links; i++) {
 302                 pool->stream_enc[pool->stream_enc_count] =
 303                         virtual_stream_encoder_create(
 304                                         ctx, ctx->dc_bios);
 305                 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
 306                         DC_ERR("DC: failed to create stream_encoder!\n");
 307                         return false;
 308                 }
 309                 pool->stream_enc_count++;
 310         }
 311
 312         dc->hwseq = create_funcs->create_hwseq(ctx);
 313
 314         return true;
 315 }
 316 static int find_matching_clock_source(
 317                 const struct resource_pool *pool,
 318                 struct clock_source *clock_source)
 319 {
 320
 321         int i;
 322
 323         for (i = 0; i < pool->clk_src_count; i++) {
 324                 if (pool->clock_sources[i] == clock_source)
 325                         return i;
 326         }
 327         return -1;
 328 }
 329
 330 void resource_unreference_clock_source(
 331                 struct resource_context *res_ctx,
 332                 const struct resource_pool *pool,
 333                 struct clock_source *clock_source)
 334 {
 335         int i = find_matching_clock_source(pool, clock_source);
 336
 337         if (i > -1)
 338                 res_ctx->clock_source_ref_count[i]--;
 339
 340         if (pool->dp_clock_source == clock_source)
 341                 res_ctx->dp_clock_source_ref_count--;
 342 }
 343
 344 void resource_reference_clock_source(
 345                 struct resource_context *res_ctx,
 346                 const struct resource_pool *pool,
 347                 struct clock_source *clock_source)
 348 {
 349         int i = find_matching_clock_source(pool, clock_source);
 350
 351         if (i > -1)
 352                 res_ctx->clock_source_ref_count[i]++;
 353
 354         if (pool->dp_clock_source == clock_source)
 355                 res_ctx->dp_clock_source_ref_count++;
 356 }
 357
 358 int resource_get_clock_source_reference(
 359                 struct resource_context *res_ctx,
 360                 const struct resource_pool *pool,
 361                 struct clock_source *clock_source)
 362 {
 363         int i = find_matching_clock_source(pool, clock_source);
 364
 365         if (i > -1)
 366                 return res_ctx->clock_source_ref_count[i];
 367
 368         if (pool->dp_clock_source == clock_source)
 369                 return res_ctx->dp_clock_source_ref_count;
 370
 371         return -1;
 372 }
 373
 374 bool resource_are_streams_timing_synchronizable(
 375         struct dc_stream_state *stream1,
 376         struct dc_stream_state *stream2)
 377 {
 378         if (stream1->timing.h_total != stream2->timing.h_total)
 379                 return false;
 380
 381         if (stream1->timing.v_total != stream2->timing.v_total)
 382                 return false;
 383
 384         if (stream1->timing.h_addressable
 385                                 != stream2->timing.h_addressable)
 386                 return false;
 387
 388         if (stream1->timing.v_addressable
 389                                 != stream2->timing.v_addressable)
 390                 return false;
 391
 392         if (stream1->timing.pix_clk_100hz
 393                                 != stream2->timing.pix_clk_100hz)
 394                 return false;
 395
 396         if (stream1->clamping.c_depth != stream2->clamping.c_depth)
 397                 return false;
 398
 399         if (stream1->phy_pix_clk != stream2->phy_pix_clk
 400                         && (!dc_is_dp_signal(stream1->signal)
 401                         || !dc_is_dp_signal(stream2->signal)))
 402                 return false;
 403
 404         if (stream1->view_format != stream2->view_format)
 405                 return false;
 406
 407         return true;
 408 }
 409 static bool is_dp_and_hdmi_sharable(
 410                 struct dc_stream_state *stream1,
 411                 struct dc_stream_state *stream2)
 412 {
 413         if (stream1->ctx->dc->caps.disable_dp_clk_share)
 414                 return false;
 415
 416         if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
 417                 stream2->clamping.c_depth != COLOR_DEPTH_888)
 418                 return false;
 419
 420         return true;
 421
 422 }
 423
 424 static bool is_sharable_clk_src(
 425         const struct pipe_ctx *pipe_with_clk_src,
 426         const struct pipe_ctx *pipe)
 427 {
 428         if (pipe_with_clk_src->clock_source == NULL)
 429                 return false;
 430
 431         if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
 432                 return false;
 433
 434         if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
 435                 (dc_is_dp_signal(pipe->stream->signal) &&
 436                 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
 437                                      pipe->stream)))
 438                 return false;
 439
 440         if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
 441                         && dc_is_dual_link_signal(pipe->stream->signal))
 442                 return false;
 443
 444         if (dc_is_hdmi_signal(pipe->stream->signal)
 445                         && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
 446                 return false;
 447
 448         if (!resource_are_streams_timing_synchronizable(
 449                         pipe_with_clk_src->stream, pipe->stream))
 450                 return false;
 451
 452         return true;
 453 }
 454
 455 struct clock_source *resource_find_used_clk_src_for_sharing(
 456                                         struct resource_context *res_ctx,
 457                                         struct pipe_ctx *pipe_ctx)
 458 {
 459         int i;
 460
 461         for (i = 0; i < MAX_PIPES; i++) {
 462                 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
 463                         return res_ctx->pipe_ctx[i].clock_source;
 464         }
 465
 466         return NULL;
 467 }
 468
 469 static enum pixel_format convert_pixel_format_to_dalsurface(
 470                 enum surface_pixel_format surface_pixel_format)
 471 {
 472         enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
 473
 474         switch (surface_pixel_format) {
 475         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
 476                 dal_pixel_format = PIXEL_FORMAT_INDEX8;
 477                 break;
 478         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 479                 dal_pixel_format = PIXEL_FORMAT_RGB565;
 480                 break;
 481         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 482                 dal_pixel_format = PIXEL_FORMAT_RGB565;
 483                 break;
 484         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 485                 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
 486                 break;
 487         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 488                 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
 489                 break;
 490         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 491                 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
 492                 break;
 493         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 494                 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
 495                 break;
 496         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
 497                 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
 498                 break;
 499         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 500         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 501                 dal_pixel_format = PIXEL_FORMAT_FP16;
 502                 break;
 503         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 504         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 505                 dal_pixel_format = PIXEL_FORMAT_420BPP8;
 506                 break;
 507         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 508         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 509                 dal_pixel_format = PIXEL_FORMAT_420BPP10;
 510                 break;
 511         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 512         default:
 513                 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
 514                 break;
 515         }
 516         return dal_pixel_format;
 517 }
 518
 519 static inline void get_vp_scan_direction(
 520         enum dc_rotation_angle rotation,
 521         bool horizontal_mirror,
 522         bool *orthogonal_rotation,
 523         bool *flip_vert_scan_dir,
 524         bool *flip_horz_scan_dir)
 525 {
 526         *orthogonal_rotation = false;
 527         *flip_vert_scan_dir = false;
 528         *flip_horz_scan_dir = false;
 529         if (rotation == ROTATION_ANGLE_180) {
 530                 *flip_vert_scan_dir = true;
 531                 *flip_horz_scan_dir = true;
 532         } else if (rotation == ROTATION_ANGLE_90) {
 533                 *orthogonal_rotation = true;
 534                 *flip_horz_scan_dir = true;
 535         } else if (rotation == ROTATION_ANGLE_270) {
 536                 *orthogonal_rotation = true;
 537                 *flip_vert_scan_dir = true;
 538         }
 539
 540         if (horizontal_mirror)
 541                 *flip_horz_scan_dir = !*flip_horz_scan_dir;
 542 }
 543
 544 static void calculate_viewport(struct pipe_ctx *pipe_ctx)
 545 {
 546         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 547         const struct dc_stream_state *stream = pipe_ctx->stream;
 548         struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
 549         struct rect surf_src = plane_state->src_rect;
 550         struct rect clip, dest;
 551         int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
 552                         || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
 553         bool pri_split = pipe_ctx->bottom_pipe &&
 554                         pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
 555         bool sec_split = pipe_ctx->top_pipe &&
 556                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
 557         bool orthogonal_rotation, flip_y_start, flip_x_start;
 558
 559         if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
 560                 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
 561                 pri_split = false;
 562                 sec_split = false;
 563         }
 564
 565         /* The actual clip is an intersection between stream
 566          * source and surface clip
 567          */
 568         dest = plane_state->dst_rect;
 569         clip.x = stream->src.x > plane_state->clip_rect.x ?
 570                         stream->src.x : plane_state->clip_rect.x;
 571
 572         clip.width = stream->src.x + stream->src.width <
 573                         plane_state->clip_rect.x + plane_state->clip_rect.width ?
 574                         stream->src.x + stream->src.width - clip.x :
 575                         plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
 576
 577         clip.y = stream->src.y > plane_state->clip_rect.y ?
 578                         stream->src.y : plane_state->clip_rect.y;
 579
 580         clip.height = stream->src.y + stream->src.height <
 581                         plane_state->clip_rect.y + plane_state->clip_rect.height ?
 582                         stream->src.y + stream->src.height - clip.y :
 583                         plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
 584
 585         /*
 586          * Need to calculate how scan origin is shifted in vp space
 587          * to correctly rotate clip and dst
 588          */
 589         get_vp_scan_direction(
 590                         plane_state->rotation,
 591                         plane_state->horizontal_mirror,
 592                         &orthogonal_rotation,
 593                         &flip_y_start,
 594                         &flip_x_start);
 595
 596         if (orthogonal_rotation) {
 597                 swap(clip.x, clip.y);
 598                 swap(clip.width, clip.height);
 599                 swap(dest.x, dest.y);
 600                 swap(dest.width, dest.height);
 601         }
 602         if (flip_x_start) {
 603                 clip.x = dest.x + dest.width - clip.x - clip.width;
 604                 dest.x = 0;
 605         }
 606         if (flip_y_start) {
 607                 clip.y = dest.y + dest.height - clip.y - clip.height;
 608                 dest.y = 0;
 609         }
 610
 611         /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
 612          * num_pixels = clip.num_pix * scl_ratio
 613          */
 614         data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
 615         data->viewport.width = clip.width * surf_src.width / dest.width;
 616
 617         data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
 618         data->viewport.height = clip.height * surf_src.height / dest.height;
 619
 620         /* Handle split */
 621         if (pri_split || sec_split) {
 622                 if (orthogonal_rotation) {
 623                         if (flip_y_start != pri_split)
 624                                 data->viewport.height /= 2;
 625                         else {
 626                                 data->viewport.y +=  data->viewport.height / 2;
 627                                 /* Ceil offset pipe */
 628                                 data->viewport.height = (data->viewport.height + 1) / 2;
 629                         }
 630                 } else {
 631                         if (flip_x_start != pri_split)
 632                                 data->viewport.width /= 2;
 633                         else {
 634                                 data->viewport.x +=  data->viewport.width / 2;
 635                                 /* Ceil offset pipe */
 636                                 data->viewport.width = (data->viewport.width + 1) / 2;
 637                         }
 638                 }
 639         }
 640
 641         /* Round down, compensate in init */
 642         data->viewport_c.x = data->viewport.x / vpc_div;
 643         data->viewport_c.y = data->viewport.y / vpc_div;
 644         data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
 645         data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
 646
 647         /* Round up, assume original video size always even dimensions */
 648         data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
 649         data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
 650 }
 651
 652 static void calculate_recout(struct pipe_ctx *pipe_ctx)
 653 {
 654         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 655         const struct dc_stream_state *stream = pipe_ctx->stream;
 656         struct rect surf_clip = plane_state->clip_rect;
 657         bool pri_split = pipe_ctx->bottom_pipe &&
 658                         pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
 659         bool sec_split = pipe_ctx->top_pipe &&
 660                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
 661         bool top_bottom_split = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
 662
 663         pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
 664         if (stream->src.x < surf_clip.x)
 665                 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
 666                         - stream->src.x) * stream->dst.width
 667                                                 / stream->src.width;
 668
 669         pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
 670                         stream->dst.width / stream->src.width;
 671         if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
 672                         stream->dst.x + stream->dst.width)
 673                 pipe_ctx->plane_res.scl_data.recout.width =
 674                         stream->dst.x + stream->dst.width
 675                                                 - pipe_ctx->plane_res.scl_data.recout.x;
 676
 677         pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
 678         if (stream->src.y < surf_clip.y)
 679                 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
 680                         - stream->src.y) * stream->dst.height
 681                                                 / stream->src.height;
 682
 683         pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
 684                         stream->dst.height / stream->src.height;
 685         if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
 686                         stream->dst.y + stream->dst.height)
 687                 pipe_ctx->plane_res.scl_data.recout.height =
 688                         stream->dst.y + stream->dst.height
 689                                                 - pipe_ctx->plane_res.scl_data.recout.y;
 690
 691         /* Handle h & v split, handle rotation using viewport */
 692         if (sec_split && top_bottom_split) {
 693                 pipe_ctx->plane_res.scl_data.recout.y +=
 694                                 pipe_ctx->plane_res.scl_data.recout.height / 2;
 695                 /* Floor primary pipe, ceil 2ndary pipe */
 696                 pipe_ctx->plane_res.scl_data.recout.height =
 697                                 (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
 698         } else if (pri_split && top_bottom_split)
 699                 pipe_ctx->plane_res.scl_data.recout.height /= 2;
 700         else if (sec_split) {
 701                 pipe_ctx->plane_res.scl_data.recout.x +=
 702                                 pipe_ctx->plane_res.scl_data.recout.width / 2;
 703                 /* Ceil offset pipe */
 704                 pipe_ctx->plane_res.scl_data.recout.width =
 705                                 (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
 706         } else if (pri_split)
 707                 pipe_ctx->plane_res.scl_data.recout.width /= 2;
 708 }
 709
 710 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
 711 {
 712         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 713         const struct dc_stream_state *stream = pipe_ctx->stream;
 714         struct rect surf_src = plane_state->src_rect;
 715         const int in_w = stream->src.width;
 716         const int in_h = stream->src.height;
 717         const int out_w = stream->dst.width;
 718         const int out_h = stream->dst.height;
 719
 720         /*Swap surf_src height and width since scaling ratios are in recout rotation*/
 721         if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
 722                         pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
 723                 swap(surf_src.height, surf_src.width);
 724
 725         pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
 726                                         surf_src.width,
 727                                         plane_state->dst_rect.width);
 728         pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
 729                                         surf_src.height,
 730                                         plane_state->dst_rect.height);
 731
 732         if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
 733                 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
 734         else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
 735                 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
 736
 737         pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
 738                 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
 739         pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
 740                 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
 741
 742         pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
 743         pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
 744
 745         if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
 746                         || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
 747                 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
 748                 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
 749         }
 750         pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
 751                         pipe_ctx->plane_res.scl_data.ratios.horz, 19);
 752         pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
 753                         pipe_ctx->plane_res.scl_data.ratios.vert, 19);
 754         pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
 755                         pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
 756         pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
 757                         pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
 758 }
 759
 760 static inline void adjust_vp_and_init_for_seamless_clip(
 761                 bool flip_scan_dir,
 762                 int recout_skip,
 763                 int src_size,
 764                 int taps,
 765                 struct fixed31_32 ratio,
 766                 struct fixed31_32 *init,
 767                 int *vp_offset,
 768                 int *vp_size)
 769 {
 770         if (!flip_scan_dir) {
 771                 /* Adjust for viewport end clip-off */
 772                 if ((*vp_offset + *vp_size) < src_size) {
 773                         int vp_clip = src_size - *vp_size - *vp_offset;
 774                         int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
 775
 776                         int_part = int_part > 0 ? int_part : 0;
 777                         *vp_size += int_part < vp_clip ? int_part : vp_clip;
 778                 }
 779
 780                 /* Adjust for non-0 viewport offset */
 781                 if (*vp_offset) {
 782                         int int_part;
 783
 784                         *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
 785                         int_part = dc_fixpt_floor(*init) - *vp_offset;
 786                         if (int_part < taps) {
 787                                 int int_adj = *vp_offset >= (taps - int_part) ?
 788                                                         (taps - int_part) : *vp_offset;
 789                                 *vp_offset -= int_adj;
 790                                 *vp_size += int_adj;
 791                                 int_part += int_adj;
 792                         } else if (int_part > taps) {
 793                                 *vp_offset += int_part - taps;
 794                                 *vp_size -= int_part - taps;
 795                                 int_part = taps;
 796                         }
 797                         init->value &= 0xffffffff;
 798                         *init = dc_fixpt_add_int(*init, int_part);
 799                 }
 800         } else {
 801                 /* Adjust for non-0 viewport offset */
 802                 if (*vp_offset) {
 803                         int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
 804
 805                         int_part = int_part > 0 ? int_part : 0;
 806                         *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
 807                         *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
 808                 }
 809
 810                 /* Adjust for viewport end clip-off */
 811                 if ((*vp_offset + *vp_size) < src_size) {
 812                         int int_part;
 813                         int end_offset = src_size - *vp_offset - *vp_size;
 814
 815                         /*
 816                          * this is init if vp had no offset, keep in mind this is from the
 817                          * right side of vp due to scan direction
 818                          */
 819                         *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
 820                         /*
 821                          * this is the difference between first pixel of viewport available to read
 822                          * and init position, takning into account scan direction
 823                          */
 824                         int_part = dc_fixpt_floor(*init) - end_offset;
 825                         if (int_part < taps) {
 826                                 int int_adj = end_offset >= (taps - int_part) ?
 827                                                         (taps - int_part) : end_offset;
 828                                 *vp_size += int_adj;
 829                                 int_part += int_adj;
 830                         } else if (int_part > taps) {
 831                                 *vp_size += int_part - taps;
 832                                 int_part = taps;
 833                         }
 834                         init->value &= 0xffffffff;
 835                         *init = dc_fixpt_add_int(*init, int_part);
 836                 }
 837         }
 838 }
 839
 840 static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
 841 {
 842         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 843         const struct dc_stream_state *stream = pipe_ctx->stream;
 844         struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
 845         struct rect src = pipe_ctx->plane_state->src_rect;
 846         int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
 847         int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
 848                         || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
 849         bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
 850
 851         /*
 852          * Need to calculate the scan direction for viewport to make adjustments
 853          */
 854         get_vp_scan_direction(
 855                         plane_state->rotation,
 856                         plane_state->horizontal_mirror,
 857                         &orthogonal_rotation,
 858                         &flip_vert_scan_dir,
 859                         &flip_horz_scan_dir);
 860
 861         /* Calculate src rect rotation adjusted to recout space */
 862         surf_size_h = src.x + src.width;
 863         surf_size_v = src.y + src.height;
 864         if (flip_horz_scan_dir)
 865                 src.x = 0;
 866         if (flip_vert_scan_dir)
 867                 src.y = 0;
 868         if (orthogonal_rotation) {
 869                 swap(src.x, src.y);
 870                 swap(src.width, src.height);
 871         }
 872
 873         /* Recout matching initial vp offset = recout_offset - (stream dst offset +
 874          *                      ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
 875          *                      - (surf surf_src offset * 1/ full scl ratio))
 876          */
 877         recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
 878                                         * stream->dst.width / stream->src.width -
 879                                         src.x * plane_state->dst_rect.width / src.width
 880                                         * stream->dst.width / stream->src.width);
 881         recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
 882                                         * stream->dst.height / stream->src.height -
 883                                         src.y * plane_state->dst_rect.height / src.height
 884                                         * stream->dst.height / stream->src.height);
 885         if (orthogonal_rotation)
 886                 swap(recout_skip_h, recout_skip_v);
 887         /*
 888          * Init calculated according to formula:
 889          *      init = (scaling_ratio + number_of_taps + 1) / 2
 890          *      init_bot = init + scaling_ratio
 891          *      init_c = init + truncated_vp_c_offset(from calculate viewport)
 892          */
 893         data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
 894                         dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
 895
 896         data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
 897                         dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
 898
 899         data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
 900                         dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
 901
 902         data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
 903                         dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
 904
 905         /*
 906          * Taps, inits and scaling ratios are in recout space need to rotate
 907          * to viewport rotation before adjustment
 908          */
 909         adjust_vp_and_init_for_seamless_clip(
 910                         flip_horz_scan_dir,
 911                         recout_skip_h,
 912                         surf_size_h,
 913                         orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
 914                         orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
 915                         orthogonal_rotation ? &data->inits.v : &data->inits.h,
 916                         &data->viewport.x,
 917                         &data->viewport.width);
 918         adjust_vp_and_init_for_seamless_clip(
 919                         flip_horz_scan_dir,
 920                         recout_skip_h,
 921                         surf_size_h / vpc_div,
 922                         orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
 923                         orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
 924                         orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
 925                         &data->viewport_c.x,
 926                         &data->viewport_c.width);
 927         adjust_vp_and_init_for_seamless_clip(
 928                         flip_vert_scan_dir,
 929                         recout_skip_v,
 930                         surf_size_v,
 931                         orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
 932                         orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
 933                         orthogonal_rotation ? &data->inits.h : &data->inits.v,
 934                         &data->viewport.y,
 935                         &data->viewport.height);
 936         adjust_vp_and_init_for_seamless_clip(
 937                         flip_vert_scan_dir,
 938                         recout_skip_v,
 939                         surf_size_v / vpc_div,
 940                         orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
 941                         orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
 942                         orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
 943                         &data->viewport_c.y,
 944                         &data->viewport_c.height);
 945
 946         /* Interlaced inits based on final vert inits */
 947         data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
 948         data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
 949
 950 }
 951 static bool are_rect_integer_multiples(struct rect src, struct rect dest)
 952 {
 953         if (dest.width  >= src.width  && dest.width  % src.width  == 0 &&
 954                 dest.height >= src.height && dest.height % src.height == 0)
 955                 return true;
 956
 957         return false;
 958 }
 959 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 960 {
 961         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 962         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 963         bool res = false;
 964         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
 965         /* Important: scaling ratio calculation requires pixel format,
 966          * lb depth calculation requires recout and taps require scaling ratios.
 967          * Inits require viewport, taps, ratios and recout of split pipe
 968          */
 969         pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
 970                         pipe_ctx->plane_state->format);
 971
 972         calculate_scaling_ratios(pipe_ctx);
 973
 974         calculate_viewport(pipe_ctx);
 975
 976         if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
 977                 return false;
 978
 979         calculate_recout(pipe_ctx);
 980
 981         /**
 982          * Setting line buffer pixel depth to 24bpp yields banding
 983          * on certain displays, such as the Sharp 4k
 984          */
 985         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
 986
 987         pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
 988         pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
 989
 990         pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
 991         pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
 992
 993         /* Taps calculations */
 994         if (pipe_ctx->plane_res.xfm != NULL)
 995                 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
 996                                 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
 997
 998         if (pipe_ctx->plane_res.dpp != NULL)
 999                 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1000                                 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1001
1002         if (res &&
1003             plane_state->scaling_quality.integer_scaling &&
1004             are_rect_integer_multiples(pipe_ctx->plane_res.scl_data.viewport,
1005                                        pipe_ctx->plane_res.scl_data.recout)) {
1006                 pipe_ctx->plane_res.scl_data.taps.v_taps = 1;
1007                 pipe_ctx->plane_res.scl_data.taps.h_taps = 1;
1008         }
1009
1010         if (!res) {
1011                 /* Try 24 bpp linebuffer */
1012                 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
1013
1014                 if (pipe_ctx->plane_res.xfm != NULL)
1015                         res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1016                                         pipe_ctx->plane_res.xfm,
1017                                         &pipe_ctx->plane_res.scl_data,
1018                                         &plane_state->scaling_quality);
1019
1020                 if (pipe_ctx->plane_res.dpp != NULL)
1021                         res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1022                                         pipe_ctx->plane_res.dpp,
1023                                         &pipe_ctx->plane_res.scl_data,
1024                                         &plane_state->scaling_quality);
1025         }
1026
1027         if (res)
1028                 /* May need to re-check lb size after this in some obscure scenario */
1029                 calculate_inits_and_adj_vp(pipe_ctx);
1030
1031         DC_LOG_SCALER(
1032                                 "%s: Viewport:\nheight:%d width:%d x:%d "
1033                                 "y:%d\n dst_rect:\nheight:%d width:%d x:%d "
1034                                 "y:%d\n",
1035                                 __func__,
1036                                 pipe_ctx->plane_res.scl_data.viewport.height,
1037                                 pipe_ctx->plane_res.scl_data.viewport.width,
1038                                 pipe_ctx->plane_res.scl_data.viewport.x,
1039                                 pipe_ctx->plane_res.scl_data.viewport.y,
1040                                 plane_state->dst_rect.height,
1041                                 plane_state->dst_rect.width,
1042                                 plane_state->dst_rect.x,
1043                                 plane_state->dst_rect.y);
1044
1045         return res;
1046 }
1047
1048
1049 enum dc_status resource_build_scaling_params_for_context(
1050         const struct dc  *dc,
1051         struct dc_state *context)
1052 {
1053         int i;
1054
1055         for (i = 0; i < MAX_PIPES; i++) {
1056                 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
1057                                 context->res_ctx.pipe_ctx[i].stream != NULL)
1058                         if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
1059                                 return DC_FAIL_SCALING;
1060         }
1061
1062         return DC_OK;
1063 }
1064
1065 struct pipe_ctx *find_idle_secondary_pipe(
1066                 struct resource_context *res_ctx,
1067                 const struct resource_pool *pool,
1068                 const struct pipe_ctx *primary_pipe)
1069 {
1070         int i;
1071         struct pipe_ctx *secondary_pipe = NULL;
1072
1073         /*
1074          * We add a preferred pipe mapping to avoid the chance that
1075          * MPCCs already in use will need to be reassigned to other trees.
1076          * For example, if we went with the strict, assign backwards logic:
1077          *
1078          * (State 1)
1079          * Display A on, no surface, top pipe = 0
1080          * Display B on, no surface, top pipe = 1
1081          *
1082          * (State 2)
1083          * Display A on, no surface, top pipe = 0
1084          * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1085          *
1086          * (State 3)
1087          * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1088          * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1089          *
1090          * The state 2->3 transition requires remapping MPCC 5 from display B
1091          * to display A.
1092          *
1093          * However, with the preferred pipe logic, state 2 would look like:
1094          *
1095          * (State 2)
1096          * Display A on, no surface, top pipe = 0
1097          * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1098          *
1099          * This would then cause 2->3 to not require remapping any MPCCs.
1100          */
1101         if (primary_pipe) {
1102                 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1103                 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1104                         secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1105                         secondary_pipe->pipe_idx = preferred_pipe_idx;
1106                 }
1107         }
1108
1109         /*
1110          * search backwards for the second pipe to keep pipe
1111          * assignment more consistent
1112          */
1113         if (!secondary_pipe)
1114                 for (i = pool->pipe_count - 1; i >= 0; i--) {
1115                         if (res_ctx->pipe_ctx[i].stream == NULL) {
1116                                 secondary_pipe = &res_ctx->pipe_ctx[i];
1117                                 secondary_pipe->pipe_idx = i;
1118                                 break;
1119                         }
1120                 }
1121
1122         return secondary_pipe;
1123 }
1124
1125 struct pipe_ctx *resource_get_head_pipe_for_stream(
1126                 struct resource_context *res_ctx,
1127                 struct dc_stream_state *stream)
1128 {
1129         int i;
1130
1131         for (i = 0; i < MAX_PIPES; i++) {
1132                 if (res_ctx->pipe_ctx[i].stream == stream
1133                                 && !res_ctx->pipe_ctx[i].top_pipe
1134                                 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
1135                         return &res_ctx->pipe_ctx[i];
1136         }
1137         return NULL;
1138 }
1139
1140 static struct pipe_ctx *resource_get_tail_pipe(
1141                 struct resource_context *res_ctx,
1142                 struct pipe_ctx *head_pipe)
1143 {
1144         struct pipe_ctx *tail_pipe;
1145
1146         tail_pipe = head_pipe->bottom_pipe;
1147
1148         while (tail_pipe) {
1149                 head_pipe = tail_pipe;
1150                 tail_pipe = tail_pipe->bottom_pipe;
1151         }
1152
1153         return head_pipe;
1154 }
1155
1156 /*
1157  * A free_pipe for a stream is defined here as a pipe
1158  * that has no surface attached yet
1159  */
1160 static struct pipe_ctx *acquire_free_pipe_for_head(
1161                 struct dc_state *context,
1162                 const struct resource_pool *pool,
1163                 struct pipe_ctx *head_pipe)
1164 {
1165         int i;
1166         struct resource_context *res_ctx = &context->res_ctx;
1167
1168         if (!head_pipe->plane_state)
1169                 return head_pipe;
1170
1171         /* Re-use pipe already acquired for this stream if available*/
1172         for (i = pool->pipe_count - 1; i >= 0; i--) {
1173                 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
1174                                 !res_ctx->pipe_ctx[i].plane_state) {
1175                         return &res_ctx->pipe_ctx[i];
1176                 }
1177         }
1178
1179         /*
1180          * At this point we have no re-useable pipe for this stream and we need
1181          * to acquire an idle one to satisfy the request
1182          */
1183
1184         if (!pool->funcs->acquire_idle_pipe_for_layer)
1185                 return NULL;
1186
1187         return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
1188 }
1189
1190 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1191 static int acquire_first_split_pipe(
1192                 struct resource_context *res_ctx,
1193                 const struct resource_pool *pool,
1194                 struct dc_stream_state *stream)
1195 {
1196         int i;
1197
1198         for (i = 0; i < pool->pipe_count; i++) {
1199                 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1200
1201                 if (split_pipe->top_pipe &&
1202                                 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1203                         split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1204                         if (split_pipe->bottom_pipe)
1205                                 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1206
1207                         if (split_pipe->top_pipe->plane_state)
1208                                 resource_build_scaling_params(split_pipe->top_pipe);
1209
1210                         memset(split_pipe, 0, sizeof(*split_pipe));
1211                         split_pipe->stream_res.tg = pool->timing_generators[i];
1212                         split_pipe->plane_res.hubp = pool->hubps[i];
1213                         split_pipe->plane_res.ipp = pool->ipps[i];
1214                         split_pipe->plane_res.dpp = pool->dpps[i];
1215                         split_pipe->stream_res.opp = pool->opps[i];
1216                         split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1217                         split_pipe->pipe_idx = i;
1218
1219                         split_pipe->stream = stream;
1220                         return i;
1221                 }
1222         }
1223         return -1;
1224 }
1225 #endif
1226
1227 bool dc_add_plane_to_context(
1228                 const struct dc *dc,
1229                 struct dc_stream_state *stream,
1230                 struct dc_plane_state *plane_state,
1231                 struct dc_state *context)
1232 {
1233         int i;
1234         struct resource_pool *pool = dc->res_pool;
1235         struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
1236         struct dc_stream_status *stream_status = NULL;
1237
1238         for (i = 0; i < context->stream_count; i++)
1239                 if (context->streams[i] == stream) {
1240                         stream_status = &context->stream_status[i];
1241                         break;
1242                 }
1243         if (stream_status == NULL) {
1244                 dm_error("Existing stream not found; failed to attach surface!\n");
1245                 return false;
1246         }
1247
1248
1249         if (stream_status->plane_count == MAX_SURFACE_NUM) {
1250                 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1251                                 plane_state, MAX_SURFACE_NUM);
1252                 return false;
1253         }
1254
1255         head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1256
1257         if (!head_pipe) {
1258                 dm_error("Head pipe not found for stream_state %p !\n", stream);
1259                 return false;
1260         }
1261
1262         /* retain new surface, but only once per stream */
1263         dc_plane_state_retain(plane_state);
1264
1265         while (head_pipe) {
1266                 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1267                 ASSERT(tail_pipe);
1268
1269                 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
1270
1271         #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1272                 if (!free_pipe) {
1273                         int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1274                         if (pipe_idx >= 0)
1275                                 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1276                 }
1277         #endif
1278                 if (!free_pipe) {
1279                         dc_plane_state_release(plane_state);
1280                         return false;
1281                 }
1282
1283                 free_pipe->plane_state = plane_state;
1284
1285                 if (head_pipe != free_pipe) {
1286                         free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1287                         free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1288                         free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1289                         free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1290                         free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1291                         free_pipe->clock_source = tail_pipe->clock_source;
1292                         free_pipe->top_pipe = tail_pipe;
1293                         tail_pipe->bottom_pipe = free_pipe;
1294                 }
1295                 head_pipe = head_pipe->next_odm_pipe;
1296         }
1297         /* assign new surfaces*/
1298         stream_status->plane_states[stream_status->plane_count] = plane_state;
1299
1300         stream_status->plane_count++;
1301
1302         return true;
1303 }
1304
1305 bool dc_remove_plane_from_context(
1306                 const struct dc *dc,
1307                 struct dc_stream_state *stream,
1308                 struct dc_plane_state *plane_state,
1309                 struct dc_state *context)
1310 {
1311         int i;
1312         struct dc_stream_status *stream_status = NULL;
1313         struct resource_pool *pool = dc->res_pool;
1314
1315         for (i = 0; i < context->stream_count; i++)
1316                 if (context->streams[i] == stream) {
1317                         stream_status = &context->stream_status[i];
1318                         break;
1319                 }
1320
1321         if (stream_status == NULL) {
1322                 dm_error("Existing stream not found; failed to remove plane.\n");
1323                 return false;
1324         }
1325
1326         /* release pipe for plane*/
1327         for (i = pool->pipe_count - 1; i >= 0; i--) {
1328                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1329
1330                 if (pipe_ctx->plane_state == plane_state) {
1331                         if (pipe_ctx->top_pipe)
1332                                 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1333
1334                         /* Second condition is to avoid setting NULL to top pipe
1335                          * of tail pipe making it look like head pipe in subsequent
1336                          * deletes
1337                          */
1338                         if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1339                                 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1340
1341                         /*
1342                          * For head pipe detach surfaces from pipe for tail
1343                          * pipe just zero it out
1344                          */
1345                         if (!pipe_ctx->top_pipe)
1346                                 pipe_ctx->plane_state = NULL;
1347                         else
1348                                 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1349                 }
1350         }
1351
1352
1353         for (i = 0; i < stream_status->plane_count; i++) {
1354                 if (stream_status->plane_states[i] == plane_state) {
1355
1356                         dc_plane_state_release(stream_status->plane_states[i]);
1357                         break;
1358                 }
1359         }
1360
1361         if (i == stream_status->plane_count) {
1362                 dm_error("Existing plane_state not found; failed to detach it!\n");
1363                 return false;
1364         }
1365
1366         stream_status->plane_count--;
1367
1368         /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1369         for (; i < stream_status->plane_count; i++)
1370                 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1371
1372         stream_status->plane_states[stream_status->plane_count] = NULL;
1373
1374         return true;
1375 }
1376
1377 bool dc_rem_all_planes_for_stream(
1378                 const struct dc *dc,
1379                 struct dc_stream_state *stream,
1380                 struct dc_state *context)
1381 {
1382         int i, old_plane_count;
1383         struct dc_stream_status *stream_status = NULL;
1384         struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1385
1386         for (i = 0; i < context->stream_count; i++)
1387                         if (context->streams[i] == stream) {
1388                                 stream_status = &context->stream_status[i];
1389                                 break;
1390                         }
1391
1392         if (stream_status == NULL) {
1393                 dm_error("Existing stream %p not found!\n", stream);
1394                 return false;
1395         }
1396
1397         old_plane_count = stream_status->plane_count;
1398
1399         for (i = 0; i < old_plane_count; i++)
1400                 del_planes[i] = stream_status->plane_states[i];
1401
1402         for (i = 0; i < old_plane_count; i++)
1403                 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1404                         return false;
1405
1406         return true;
1407 }
1408
1409 static bool add_all_planes_for_stream(
1410                 const struct dc *dc,
1411                 struct dc_stream_state *stream,
1412                 const struct dc_validation_set set[],
1413                 int set_count,
1414                 struct dc_state *context)
1415 {
1416         int i, j;
1417
1418         for (i = 0; i < set_count; i++)
1419                 if (set[i].stream == stream)
1420                         break;
1421
1422         if (i == set_count) {
1423                 dm_error("Stream %p not found in set!\n", stream);
1424                 return false;
1425         }
1426
1427         for (j = 0; j < set[i].plane_count; j++)
1428                 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1429                         return false;
1430
1431         return true;
1432 }
1433
1434 bool dc_add_all_planes_for_stream(
1435                 const struct dc *dc,
1436                 struct dc_stream_state *stream,
1437                 struct dc_plane_state * const *plane_states,
1438                 int plane_count,
1439                 struct dc_state *context)
1440 {
1441         struct dc_validation_set set;
1442         int i;
1443
1444         set.stream = stream;
1445         set.plane_count = plane_count;
1446
1447         for (i = 0; i < plane_count; i++)
1448                 set.plane_states[i] = plane_states[i];
1449
1450         return add_all_planes_for_stream(dc, stream, &set, 1, context);
1451 }
1452
1453
1454 static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
1455         struct dc_stream_state *new_stream)
1456 {
1457         if (cur_stream == NULL)
1458                 return true;
1459
1460         if (memcmp(&cur_stream->hdr_static_metadata,
1461                         &new_stream->hdr_static_metadata,
1462                         sizeof(struct dc_info_packet)) != 0)
1463                 return true;
1464
1465         return false;
1466 }
1467
1468 static bool is_vsc_info_packet_changed(struct dc_stream_state *cur_stream,
1469                 struct dc_stream_state *new_stream)
1470 {
1471         if (cur_stream == NULL)
1472                 return true;
1473
1474         if (memcmp(&cur_stream->vsc_infopacket,
1475                         &new_stream->vsc_infopacket,
1476                         sizeof(struct dc_info_packet)) != 0)
1477                 return true;
1478
1479         return false;
1480 }
1481
1482 static bool is_timing_changed(struct dc_stream_state *cur_stream,
1483                 struct dc_stream_state *new_stream)
1484 {
1485         if (cur_stream == NULL)
1486                 return true;
1487
1488         /* If sink pointer changed, it means this is a hotplug, we should do
1489          * full hw setting.
1490          */
1491         if (cur_stream->sink != new_stream->sink)
1492                 return true;
1493
1494         /* If output color space is changed, need to reprogram info frames */
1495         if (cur_stream->output_color_space != new_stream->output_color_space)
1496                 return true;
1497
1498         return memcmp(
1499                 &cur_stream->timing,
1500                 &new_stream->timing,
1501                 sizeof(struct dc_crtc_timing)) != 0;
1502 }
1503
1504 static bool are_stream_backends_same(
1505         struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
1506 {
1507         if (stream_a == stream_b)
1508                 return true;
1509
1510         if (stream_a == NULL || stream_b == NULL)
1511                 return false;
1512
1513         if (is_timing_changed(stream_a, stream_b))
1514                 return false;
1515
1516         if (is_hdr_static_meta_changed(stream_a, stream_b))
1517                 return false;
1518
1519         if (stream_a->dpms_off != stream_b->dpms_off)
1520                 return false;
1521
1522         if (is_vsc_info_packet_changed(stream_a, stream_b))
1523                 return false;
1524
1525         return true;
1526 }
1527
1528 /**
1529  * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1530  *
1531  * Checks if there a difference between the two states
1532  * that would require a mode change.
1533  *
1534  * Does not compare cursor position or attributes.
1535  */
1536 bool dc_is_stream_unchanged(
1537         struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1538 {
1539
1540         if (!are_stream_backends_same(old_stream, stream))
1541                 return false;
1542
1543         return true;
1544 }
1545
1546 /**
1547  * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1548  */
1549 bool dc_is_stream_scaling_unchanged(
1550         struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1551 {
1552         if (old_stream == stream)
1553                 return true;
1554
1555         if (old_stream == NULL || stream == NULL)
1556                 return false;
1557
1558         if (memcmp(&old_stream->src,
1559                         &stream->src,
1560                         sizeof(struct rect)) != 0)
1561                 return false;
1562
1563         if (memcmp(&old_stream->dst,
1564                         &stream->dst,
1565                         sizeof(struct rect)) != 0)
1566                 return false;
1567
1568         return true;
1569 }
1570
1571 static void update_stream_engine_usage(
1572                 struct resource_context *res_ctx,
1573                 const struct resource_pool *pool,
1574                 struct stream_encoder *stream_enc,
1575                 bool acquired)
1576 {
1577         int i;
1578
1579         for (i = 0; i < pool->stream_enc_count; i++) {
1580                 if (pool->stream_enc[i] == stream_enc)
1581                         res_ctx->is_stream_enc_acquired[i] = acquired;
1582         }
1583 }
1584
1585 /* TODO: release audio object */
1586 void update_audio_usage(
1587                 struct resource_context *res_ctx,
1588                 const struct resource_pool *pool,
1589                 struct audio *audio,
1590                 bool acquired)
1591 {
1592         int i;
1593         for (i = 0; i < pool->audio_count; i++) {
1594                 if (pool->audios[i] == audio)
1595                         res_ctx->is_audio_acquired[i] = acquired;
1596         }
1597 }
1598
1599 static int acquire_first_free_pipe(
1600                 struct resource_context *res_ctx,
1601                 const struct resource_pool *pool,
1602                 struct dc_stream_state *stream)
1603 {
1604         int i;
1605
1606         for (i = 0; i < pool->pipe_count; i++) {
1607                 if (!res_ctx->pipe_ctx[i].stream) {
1608                         struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1609
1610                         pipe_ctx->stream_res.tg = pool->timing_generators[i];
1611                         pipe_ctx->plane_res.mi = pool->mis[i];
1612                         pipe_ctx->plane_res.hubp = pool->hubps[i];
1613                         pipe_ctx->plane_res.ipp = pool->ipps[i];
1614                         pipe_ctx->plane_res.xfm = pool->transforms[i];
1615                         pipe_ctx->plane_res.dpp = pool->dpps[i];
1616                         pipe_ctx->stream_res.opp = pool->opps[i];
1617                         if (pool->dpps[i])
1618                                 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
1619                         pipe_ctx->pipe_idx = i;
1620
1621
1622                         pipe_ctx->stream = stream;
1623                         return i;
1624                 }
1625         }
1626         return -1;
1627 }
1628
1629 static struct audio *find_first_free_audio(
1630                 struct resource_context *res_ctx,
1631                 const struct resource_pool *pool,
1632                 enum engine_id id)
1633 {
1634         int i, available_audio_count;
1635
1636         available_audio_count = pool->audio_count;
1637
1638         for (i = 0; i < available_audio_count; i++) {
1639                 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
1640                         /*we have enough audio endpoint, find the matching inst*/
1641                         if (id != i)
1642                                 continue;
1643                         return pool->audios[i];
1644                 }
1645         }
1646
1647         /* use engine id to find free audio */
1648         if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
1649                 return pool->audios[id];
1650         }
1651         /*not found the matching one, first come first serve*/
1652         for (i = 0; i < available_audio_count; i++) {
1653                 if (res_ctx->is_audio_acquired[i] == false) {
1654                         return pool->audios[i];
1655                 }
1656         }
1657         return 0;
1658 }
1659
1660 bool resource_is_stream_unchanged(
1661         struct dc_state *old_context, struct dc_stream_state *stream)
1662 {
1663         int i;
1664
1665         for (i = 0; i < old_context->stream_count; i++) {
1666                 struct dc_stream_state *old_stream = old_context->streams[i];
1667
1668                 if (are_stream_backends_same(old_stream, stream))
1669                                 return true;
1670         }
1671
1672         return false;
1673 }
1674
1675 /**
1676  * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1677  */
1678 enum dc_status dc_add_stream_to_ctx(
1679                 struct dc *dc,
1680                 struct dc_state *new_ctx,
1681                 struct dc_stream_state *stream)
1682 {
1683         enum dc_status res;
1684         DC_LOGGER_INIT(dc->ctx->logger);
1685
1686         if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
1687                 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1688                 return DC_ERROR_UNEXPECTED;
1689         }
1690
1691         new_ctx->streams[new_ctx->stream_count] = stream;
1692         dc_stream_retain(stream);
1693         new_ctx->stream_count++;
1694
1695         res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1696         if (res != DC_OK)
1697                 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1698
1699         return res;
1700 }
1701
1702 /**
1703  * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1704  */
1705 enum dc_status dc_remove_stream_from_ctx(
1706                         struct dc *dc,
1707                         struct dc_state *new_ctx,
1708                         struct dc_stream_state *stream)
1709 {
1710         int i;
1711         struct dc_context *dc_ctx = dc->ctx;
1712         struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
1713         struct pipe_ctx *odm_pipe;
1714
1715         if (!del_pipe) {
1716                 DC_ERROR("Pipe not found for stream %p !\n", stream);
1717                 return DC_ERROR_UNEXPECTED;
1718         }
1719
1720         odm_pipe = del_pipe->next_odm_pipe;
1721
1722         /* Release primary pipe */
1723         ASSERT(del_pipe->stream_res.stream_enc);
1724         update_stream_engine_usage(
1725                         &new_ctx->res_ctx,
1726                                 dc->res_pool,
1727                         del_pipe->stream_res.stream_enc,
1728                         false);
1729
1730         if (del_pipe->stream_res.audio)
1731                 update_audio_usage(
1732                         &new_ctx->res_ctx,
1733                         dc->res_pool,
1734                         del_pipe->stream_res.audio,
1735                         false);
1736
1737         resource_unreference_clock_source(&new_ctx->res_ctx,
1738                                           dc->res_pool,
1739                                           del_pipe->clock_source);
1740
1741         if (dc->res_pool->funcs->remove_stream_from_ctx)
1742                 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1743
1744         while (odm_pipe) {
1745                 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1746
1747                 memset(odm_pipe, 0, sizeof(*odm_pipe));
1748                 odm_pipe = next_odm_pipe;
1749         }
1750         memset(del_pipe, 0, sizeof(*del_pipe));
1751
1752         for (i = 0; i < new_ctx->stream_count; i++)
1753                 if (new_ctx->streams[i] == stream)
1754                         break;
1755
1756         if (new_ctx->streams[i] != stream) {
1757                 DC_ERROR("Context doesn't have stream %p !\n", stream);
1758                 return DC_ERROR_UNEXPECTED;
1759         }
1760
1761         dc_stream_release(new_ctx->streams[i]);
1762         new_ctx->stream_count--;
1763
1764         /* Trim back arrays */
1765         for (; i < new_ctx->stream_count; i++) {
1766                 new_ctx->streams[i] = new_ctx->streams[i + 1];
1767                 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1768         }
1769
1770         new_ctx->streams[new_ctx->stream_count] = NULL;
1771         memset(
1772                         &new_ctx->stream_status[new_ctx->stream_count],
1773                         0,
1774                         sizeof(new_ctx->stream_status[0]));
1775
1776         return DC_OK;
1777 }
1778
1779 static struct dc_stream_state *find_pll_sharable_stream(
1780                 struct dc_stream_state *stream_needs_pll,
1781                 struct dc_state *context)
1782 {
1783         int i;
1784
1785         for (i = 0; i < context->stream_count; i++) {
1786                 struct dc_stream_state *stream_has_pll = context->streams[i];
1787
1788                 /* We are looking for non dp, non virtual stream */
1789                 if (resource_are_streams_timing_synchronizable(
1790                         stream_needs_pll, stream_has_pll)
1791                         && !dc_is_dp_signal(stream_has_pll->signal)
1792                         && stream_has_pll->link->connector_signal
1793                         != SIGNAL_TYPE_VIRTUAL)
1794                         return stream_has_pll;
1795
1796         }
1797
1798         return NULL;
1799 }
1800
1801 static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1802 {
1803         uint32_t pix_clk = timing->pix_clk_100hz;
1804         uint32_t normalized_pix_clk = pix_clk;
1805
1806         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1807                 pix_clk /= 2;
1808         if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1809                 switch (timing->display_color_depth) {
1810                 case COLOR_DEPTH_666:
1811                 case COLOR_DEPTH_888:
1812                         normalized_pix_clk = pix_clk;
1813                         break;
1814                 case COLOR_DEPTH_101010:
1815                         normalized_pix_clk = (pix_clk * 30) / 24;
1816                         break;
1817                 case COLOR_DEPTH_121212:
1818                         normalized_pix_clk = (pix_clk * 36) / 24;
1819                 break;
1820                 case COLOR_DEPTH_161616:
1821                         normalized_pix_clk = (pix_clk * 48) / 24;
1822                 break;
1823                 default:
1824                         ASSERT(0);
1825                 break;
1826                 }
1827         }
1828         return normalized_pix_clk;
1829 }
1830
1831 static void calculate_phy_pix_clks(struct dc_stream_state *stream)
1832 {
1833         /* update actual pixel clock on all streams */
1834         if (dc_is_hdmi_signal(stream->signal))
1835                 stream->phy_pix_clk = get_norm_pix_clk(
1836                         &stream->timing) / 10;
1837         else
1838                 stream->phy_pix_clk =
1839                         stream->timing.pix_clk_100hz / 10;
1840
1841         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1842                 stream->phy_pix_clk *= 2;
1843 }
1844
1845 static int acquire_resource_from_hw_enabled_state(
1846                 struct resource_context *res_ctx,
1847                 const struct resource_pool *pool,
1848                 struct dc_stream_state *stream)
1849 {
1850         struct dc_link *link = stream->link;
1851         unsigned int inst, tg_inst;
1852
1853         /* Check for enabled DIG to identify enabled display */
1854         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1855                 return -1;
1856
1857         /* Check for which front end is used by this encoder.
1858          * Note the inst is 1 indexed, where 0 is undefined.
1859          * Note that DIG_FE can source from different OTG but our
1860          * current implementation always map 1-to-1, so this code makes
1861          * the same assumption and doesn't check OTG source.
1862          */
1863         inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1864
1865         /* Instance should be within the range of the pool */
1866         if (inst >= pool->pipe_count)
1867                 return -1;
1868
1869         if (inst >= pool->stream_enc_count)
1870                 return -1;
1871
1872         tg_inst = pool->stream_enc[inst]->funcs->dig_source_otg(pool->stream_enc[inst]);
1873
1874         if (tg_inst >= pool->timing_generator_count)
1875                 return false;
1876
1877         if (!res_ctx->pipe_ctx[tg_inst].stream) {
1878                 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
1879
1880                 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
1881                 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
1882                 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
1883                 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
1884                 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
1885                 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
1886                 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
1887
1888                 if (pool->dpps[tg_inst])
1889                         pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
1890                 pipe_ctx->pipe_idx = tg_inst;
1891
1892                 pipe_ctx->stream = stream;
1893                 return tg_inst;
1894         }
1895
1896         return -1;
1897 }
1898
1899 enum dc_status resource_map_pool_resources(
1900                 const struct dc  *dc,
1901                 struct dc_state *context,
1902                 struct dc_stream_state *stream)
1903 {
1904         const struct resource_pool *pool = dc->res_pool;
1905         int i;
1906         struct dc_context *dc_ctx = dc->ctx;
1907         struct pipe_ctx *pipe_ctx = NULL;
1908         int pipe_idx = -1;
1909         struct dc_bios *dcb = dc->ctx->dc_bios;
1910
1911         /* TODO Check if this is needed */
1912         /*if (!resource_is_stream_unchanged(old_context, stream)) {
1913                         if (stream != NULL && old_context->streams[i] != NULL) {
1914                                 stream->bit_depth_params =
1915                                                 old_context->streams[i]->bit_depth_params;
1916                                 stream->clamping = old_context->streams[i]->clamping;
1917                                 continue;
1918                         }
1919                 }
1920         */
1921
1922         calculate_phy_pix_clks(stream);
1923
1924         /* TODO: Check Linux */
1925         if (dc->config.allow_seamless_boot_optimization &&
1926                         !dcb->funcs->is_accelerated_mode(dcb)) {
1927                 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
1928                         stream->apply_seamless_boot_optimization = true;
1929         }
1930
1931         if (stream->apply_seamless_boot_optimization)
1932                 pipe_idx = acquire_resource_from_hw_enabled_state(
1933                                 &context->res_ctx,
1934                                 pool,
1935                                 stream);
1936
1937         if (pipe_idx < 0)
1938                 /* acquire new resources */
1939                 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
1940
1941 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
1942         if (pipe_idx < 0)
1943                 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1944 #endif
1945
1946         if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
1947                 return DC_NO_CONTROLLER_RESOURCE;
1948
1949         pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1950
1951         pipe_ctx->stream_res.stream_enc =
1952                 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
1953                         &context->res_ctx, pool, stream);
1954
1955         if (!pipe_ctx->stream_res.stream_enc)
1956                 return DC_NO_STREAM_ENC_RESOURCE;
1957
1958         update_stream_engine_usage(
1959                 &context->res_ctx, pool,
1960                 pipe_ctx->stream_res.stream_enc,
1961                 true);
1962
1963         /* TODO: Add check if ASIC support and EDID audio */
1964         if (!stream->converter_disable_audio &&
1965             dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
1966             stream->audio_info.mode_count && stream->audio_info.flags.all) {
1967                 pipe_ctx->stream_res.audio = find_first_free_audio(
1968                 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
1969
1970                 /*
1971                  * Audio assigned in order first come first get.
1972                  * There are asics which has number of audio
1973                  * resources less then number of pipes
1974                  */
1975                 if (pipe_ctx->stream_res.audio)
1976                         update_audio_usage(&context->res_ctx, pool,
1977                                            pipe_ctx->stream_res.audio, true);
1978         }
1979
1980         /* Add ABM to the resource if on EDP */
1981         if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
1982                 pipe_ctx->stream_res.abm = pool->abm;
1983
1984         for (i = 0; i < context->stream_count; i++)
1985                 if (context->streams[i] == stream) {
1986                         context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
1987                         context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
1988                         context->stream_status[i].audio_inst =
1989                                 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
1990
1991                         return DC_OK;
1992                 }
1993
1994         DC_ERROR("Stream %p not found in new ctx!\n", stream);
1995         return DC_ERROR_UNEXPECTED;
1996 }
1997
1998 /**
1999  * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2000  * Is a shallow copy.  Increments refcounts on existing streams and planes.
2001  * @dc: copy out of dc->current_state
2002  * @dst_ctx: copy into this
2003  */
2004 void dc_resource_state_copy_construct_current(
2005                 const struct dc *dc,
2006                 struct dc_state *dst_ctx)
2007 {
2008         dc_resource_state_copy_construct(dc->current_state, dst_ctx);
2009 }
2010
2011
2012 void dc_resource_state_construct(
2013                 const struct dc *dc,
2014                 struct dc_state *dst_ctx)
2015 {
2016         dst_ctx->clk_mgr = dc->clk_mgr;
2017 }
2018
2019 /**
2020  * dc_validate_global_state() - Determine if HW can support a given state
2021  * Checks HW resource availability and bandwidth requirement.
2022  * @dc: dc struct for this driver
2023  * @new_ctx: state to be validated
2024  * @fast_validate: set to true if only yes/no to support matters
2025  *
2026  * Return: DC_OK if the result can be programmed.  Otherwise, an error code.
2027  */
2028 enum dc_status dc_validate_global_state(
2029                 struct dc *dc,
2030                 struct dc_state *new_ctx,
2031                 bool fast_validate)
2032 {
2033         enum dc_status result = DC_ERROR_UNEXPECTED;
2034         int i, j;
2035
2036         if (!new_ctx)
2037                 return DC_ERROR_UNEXPECTED;
2038
2039         if (dc->res_pool->funcs->validate_global) {
2040                 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2041                 if (result != DC_OK)
2042                         return result;
2043         }
2044
2045         for (i = 0; i < new_ctx->stream_count; i++) {
2046                 struct dc_stream_state *stream = new_ctx->streams[i];
2047
2048                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2049                         struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2050
2051                         if (pipe_ctx->stream != stream)
2052                                 continue;
2053
2054                         if (dc->res_pool->funcs->get_default_swizzle_mode &&
2055                                         pipe_ctx->plane_state &&
2056                                         pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2057                                 result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
2058                                 if (result != DC_OK)
2059                                         return result;
2060                         }
2061
2062                         /* Switch to dp clock source only if there is
2063                          * no non dp stream that shares the same timing
2064                          * with the dp stream.
2065                          */
2066                         if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2067                                 !find_pll_sharable_stream(stream, new_ctx)) {
2068
2069                                 resource_unreference_clock_source(
2070                                                 &new_ctx->res_ctx,
2071                                                 dc->res_pool,
2072                                                 pipe_ctx->clock_source);
2073
2074                                 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2075                                 resource_reference_clock_source(
2076                                                 &new_ctx->res_ctx,
2077                                                 dc->res_pool,
2078                                                  pipe_ctx->clock_source);
2079                         }
2080                 }
2081         }
2082
2083         result = resource_build_scaling_params_for_context(dc, new_ctx);
2084
2085         if (result == DC_OK)
2086                 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
2087                         result = DC_FAIL_BANDWIDTH_VALIDATE;
2088
2089         return result;
2090 }
2091
2092 static void patch_gamut_packet_checksum(
2093                 struct dc_info_packet *gamut_packet)
2094 {
2095         /* For gamut we recalc checksum */
2096         if (gamut_packet->valid) {
2097                 uint8_t chk_sum = 0;
2098                 uint8_t *ptr;
2099                 uint8_t i;
2100
2101                 /*start of the Gamut data. */
2102                 ptr = &gamut_packet->sb[3];
2103
2104                 for (i = 0; i <= gamut_packet->sb[1]; i++)
2105                         chk_sum += ptr[i];
2106
2107                 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
2108         }
2109 }
2110
2111 static void set_avi_info_frame(
2112                 struct dc_info_packet *info_packet,
2113                 struct pipe_ctx *pipe_ctx)
2114 {
2115         struct dc_stream_state *stream = pipe_ctx->stream;
2116         enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
2117         uint32_t pixel_encoding = 0;
2118         enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2119         enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2120         bool itc = false;
2121         uint8_t itc_value = 0;
2122         uint8_t cn0_cn1 = 0;
2123         unsigned int cn0_cn1_value = 0;
2124         uint8_t *check_sum = NULL;
2125         uint8_t byte_index = 0;
2126         union hdmi_info_packet hdmi_info;
2127         union display_content_support support = {0};
2128         unsigned int vic = pipe_ctx->stream->timing.vic;
2129         enum dc_timing_3d_format format;
2130
2131         memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2132
2133         color_space = pipe_ctx->stream->output_color_space;
2134         if (color_space == COLOR_SPACE_UNKNOWN)
2135                 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
2136                         COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
2137
2138         /* Initialize header */
2139         hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
2140         /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2141         * not be used in HDMI 2.0 (Section 10.1) */
2142         hdmi_info.bits.header.version = 2;
2143         hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
2144
2145         /*
2146          * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2147          * according to HDMI 2.0 spec (Section 10.1)
2148          */
2149
2150         switch (stream->timing.pixel_encoding) {
2151         case PIXEL_ENCODING_YCBCR422:
2152                 pixel_encoding = 1;
2153                 break;
2154
2155         case PIXEL_ENCODING_YCBCR444:
2156                 pixel_encoding = 2;
2157                 break;
2158         case PIXEL_ENCODING_YCBCR420:
2159                 pixel_encoding = 3;
2160                 break;
2161
2162         case PIXEL_ENCODING_RGB:
2163         default:
2164                 pixel_encoding = 0;
2165         }
2166
2167         /* Y0_Y1_Y2 : The pixel encoding */
2168         /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
2169         hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
2170
2171         /* A0 = 1 Active Format Information valid */
2172         hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
2173
2174         /* B0, B1 = 3; Bar info data is valid */
2175         hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
2176
2177         hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
2178
2179         /* S0, S1 : Underscan / Overscan */
2180         /* TODO: un-hardcode scan type */
2181         scan_type = SCANNING_TYPE_UNDERSCAN;
2182         hdmi_info.bits.S0_S1 = scan_type;
2183
2184         /* C0, C1 : Colorimetry */
2185         if (color_space == COLOR_SPACE_YCBCR709 ||
2186                         color_space == COLOR_SPACE_YCBCR709_LIMITED)
2187                 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
2188         else if (color_space == COLOR_SPACE_YCBCR601 ||
2189                         color_space == COLOR_SPACE_YCBCR601_LIMITED)
2190                 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
2191         else {
2192                 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
2193         }
2194         if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
2195                         color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2196                         color_space == COLOR_SPACE_2020_YCBCR) {
2197                 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2198                 hdmi_info.bits.C0_C1   = COLORIMETRY_EXTENDED;
2199         } else if (color_space == COLOR_SPACE_ADOBERGB) {
2200                 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2201                 hdmi_info.bits.C0_C1   = COLORIMETRY_EXTENDED;
2202         }
2203
2204         /* TODO: un-hardcode aspect ratio */
2205         aspect = stream->timing.aspect_ratio;
2206
2207         switch (aspect) {
2208         case ASPECT_RATIO_4_3:
2209         case ASPECT_RATIO_16_9:
2210                 hdmi_info.bits.M0_M1 = aspect;
2211                 break;
2212
2213         case ASPECT_RATIO_NO_DATA:
2214         case ASPECT_RATIO_64_27:
2215         case ASPECT_RATIO_256_135:
2216         default:
2217                 hdmi_info.bits.M0_M1 = 0;
2218         }
2219
2220         /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
2221         hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
2222
2223         /* TODO: un-hardcode cn0_cn1 and itc */
2224
2225         cn0_cn1 = 0;
2226         cn0_cn1_value = 0;
2227
2228         itc = true;
2229         itc_value = 1;
2230
2231         support = stream->content_support;
2232
2233         if (itc) {
2234                 if (!support.bits.valid_content_type) {
2235                         cn0_cn1_value = 0;
2236                 } else {
2237                         if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2238                                 if (support.bits.graphics_content == 1) {
2239                                         cn0_cn1_value = 0;
2240                                 }
2241                         } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2242                                 if (support.bits.photo_content == 1) {
2243                                         cn0_cn1_value = 1;
2244                                 } else {
2245                                         cn0_cn1_value = 0;
2246                                         itc_value = 0;
2247                                 }
2248                         } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2249                                 if (support.bits.cinema_content == 1) {
2250                                         cn0_cn1_value = 2;
2251                                 } else {
2252                                         cn0_cn1_value = 0;
2253                                         itc_value = 0;
2254                                 }
2255                         } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2256                                 if (support.bits.game_content == 1) {
2257                                         cn0_cn1_value = 3;
2258                                 } else {
2259                                         cn0_cn1_value = 0;
2260                                         itc_value = 0;
2261                                 }
2262                         }
2263                 }
2264                 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2265                 hdmi_info.bits.ITC = itc_value;
2266         }
2267
2268         /* TODO : We should handle YCC quantization */
2269         /* but we do not have matrix calculation */
2270         if (stream->qs_bit == 1 &&
2271                         stream->qy_bit == 1) {
2272                 if (color_space == COLOR_SPACE_SRGB ||
2273                         color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
2274                         hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_FULL_RANGE;
2275                         hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
2276                 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2277                                         color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
2278                         hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_LIMITED_RANGE;
2279                         hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2280                 } else {
2281                         hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_DEFAULT_RANGE;
2282                         hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2283                 }
2284         } else {
2285                 hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_DEFAULT_RANGE;
2286                 hdmi_info.bits.YQ0_YQ1   = YYC_QUANTIZATION_LIMITED_RANGE;
2287         }
2288
2289         ///VIC
2290         format = stream->timing.timing_3d_format;
2291         /*todo, add 3DStereo support*/
2292         if (format != TIMING_3D_FORMAT_NONE) {
2293                 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
2294                 switch (pipe_ctx->stream->timing.hdmi_vic) {
2295                 case 1:
2296                         vic = 95;
2297                         break;
2298                 case 2:
2299                         vic = 94;
2300                         break;
2301                 case 3:
2302                         vic = 93;
2303                         break;
2304                 case 4:
2305                         vic = 98;
2306                         break;
2307                 default:
2308                         break;
2309                 }
2310         }
2311         /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
2312         hdmi_info.bits.VIC0_VIC7 = vic;
2313         if (vic >= 128)
2314                 hdmi_info.bits.header.version = 3;
2315         /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2316          * the Source shall use 20 AVI InfoFrame Version 4
2317          */
2318         if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2319                         hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2320                 hdmi_info.bits.header.version = 4;
2321                 hdmi_info.bits.header.length = 14;
2322         }
2323
2324         /* pixel repetition
2325          * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2326          * repetition start from 1 */
2327         hdmi_info.bits.PR0_PR3 = 0;
2328
2329         /* Bar Info
2330          * barTop:    Line Number of End of Top Bar.
2331          * barBottom: Line Number of Start of Bottom Bar.
2332          * barLeft:   Pixel Number of End of Left Bar.
2333          * barRight:  Pixel Number of Start of Right Bar. */
2334         hdmi_info.bits.bar_top = stream->timing.v_border_top;
2335         hdmi_info.bits.bar_bottom = (stream->timing.v_total
2336                         - stream->timing.v_border_bottom + 1);
2337         hdmi_info.bits.bar_left  = stream->timing.h_border_left;
2338         hdmi_info.bits.bar_right = (stream->timing.h_total
2339                         - stream->timing.h_border_right + 1);
2340
2341     /* Additional Colorimetry Extension
2342      * Used in conduction with C0-C1 and EC0-EC2
2343      * 0 = DCI-P3 RGB (D65)
2344      * 1 = DCI-P3 RGB (theater)
2345      */
2346         hdmi_info.bits.ACE0_ACE3 = 0;
2347
2348         /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
2349         check_sum = &hdmi_info.packet_raw_data.sb[0];
2350
2351         *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
2352
2353         for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
2354                 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
2355
2356         /* one byte complement */
2357         *check_sum = (uint8_t) (0x100 - *check_sum);
2358
2359         /* Store in hw_path_mode */
2360         info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2361         info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2362         info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
2363
2364         for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2365                 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
2366
2367         info_packet->valid = true;
2368 }
2369
2370 static void set_vendor_info_packet(
2371                 struct dc_info_packet *info_packet,
2372                 struct dc_stream_state *stream)
2373 {
2374         /* SPD info packet for FreeSync */
2375
2376         /* Check if Freesync is supported. Return if false. If true,
2377          * set the corresponding bit in the info packet
2378          */
2379         if (!stream->vsp_infopacket.valid)
2380                 return;
2381
2382         *info_packet = stream->vsp_infopacket;
2383 }
2384
2385 static void set_spd_info_packet(
2386                 struct dc_info_packet *info_packet,
2387                 struct dc_stream_state *stream)
2388 {
2389         /* SPD info packet for FreeSync */
2390
2391         /* Check if Freesync is supported. Return if false. If true,
2392          * set the corresponding bit in the info packet
2393          */
2394         if (!stream->vrr_infopacket.valid)
2395                 return;
2396
2397         *info_packet = stream->vrr_infopacket;
2398 }
2399
2400 static void set_hdr_static_info_packet(
2401                 struct dc_info_packet *info_packet,
2402                 struct dc_stream_state *stream)
2403 {
2404         /* HDR Static Metadata info packet for HDR10 */
2405
2406         if (!stream->hdr_static_metadata.valid ||
2407                         stream->use_dynamic_meta)
2408                 return;
2409
2410         *info_packet = stream->hdr_static_metadata;
2411 }
2412
2413 static void set_vsc_info_packet(
2414                 struct dc_info_packet *info_packet,
2415                 struct dc_stream_state *stream)
2416 {
2417         if (!stream->vsc_infopacket.valid)
2418                 return;
2419
2420         *info_packet = stream->vsc_infopacket;
2421 }
2422
2423 void dc_resource_state_destruct(struct dc_state *context)
2424 {
2425         int i, j;
2426
2427         for (i = 0; i < context->stream_count; i++) {
2428                 for (j = 0; j < context->stream_status[i].plane_count; j++)
2429                         dc_plane_state_release(
2430                                 context->stream_status[i].plane_states[j]);
2431
2432                 context->stream_status[i].plane_count = 0;
2433                 dc_stream_release(context->streams[i]);
2434                 context->streams[i] = NULL;
2435         }
2436 }
2437
2438 void dc_resource_state_copy_construct(
2439                 const struct dc_state *src_ctx,
2440                 struct dc_state *dst_ctx)
2441 {
2442         int i, j;
2443         struct kref refcount = dst_ctx->refcount;
2444
2445         *dst_ctx = *src_ctx;
2446
2447         for (i = 0; i < MAX_PIPES; i++) {
2448                 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2449
2450                 if (cur_pipe->top_pipe)
2451                         cur_pipe->top_pipe =  &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2452
2453                 if (cur_pipe->bottom_pipe)
2454                         cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2455
2456                 if (cur_pipe->next_odm_pipe)
2457                         cur_pipe->next_odm_pipe =  &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2458
2459                 if (cur_pipe->prev_odm_pipe)
2460                         cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
2461         }
2462
2463         for (i = 0; i < dst_ctx->stream_count; i++) {
2464                 dc_stream_retain(dst_ctx->streams[i]);
2465                 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2466                         dc_plane_state_retain(
2467                                 dst_ctx->stream_status[i].plane_states[j]);
2468         }
2469
2470         /* context refcount should not be overridden */
2471         dst_ctx->refcount = refcount;
2472
2473 }
2474
2475 struct clock_source *dc_resource_find_first_free_pll(
2476                 struct resource_context *res_ctx,
2477                 const struct resource_pool *pool)
2478 {
2479         int i;
2480
2481         for (i = 0; i < pool->clk_src_count; ++i) {
2482                 if (res_ctx->clock_source_ref_count[i] == 0)
2483                         return pool->clock_sources[i];
2484         }
2485
2486         return NULL;
2487 }
2488
2489 void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2490 {
2491         enum signal_type signal = SIGNAL_TYPE_NONE;
2492         struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
2493
2494         /* default all packets to invalid */
2495         info->avi.valid = false;
2496         info->gamut.valid = false;
2497         info->vendor.valid = false;
2498         info->spd.valid = false;
2499         info->hdrsmd.valid = false;
2500         info->vsc.valid = false;
2501
2502         signal = pipe_ctx->stream->signal;
2503
2504         /* HDMi and DP have different info packets*/
2505         if (dc_is_hdmi_signal(signal)) {
2506                 set_avi_info_frame(&info->avi, pipe_ctx);
2507
2508                 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2509
2510                 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2511
2512                 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
2513
2514         } else if (dc_is_dp_signal(signal)) {
2515                 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2516
2517                 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2518
2519                 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
2520         }
2521
2522         patch_gamut_packet_checksum(&info->gamut);
2523 }
2524
2525 enum dc_status resource_map_clock_resources(
2526                 const struct dc  *dc,
2527                 struct dc_state *context,
2528                 struct dc_stream_state *stream)
2529 {
2530         /* acquire new resources */
2531         const struct resource_pool *pool = dc->res_pool;
2532         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2533                                 &context->res_ctx, stream);
2534
2535         if (!pipe_ctx)
2536                 return DC_ERROR_UNEXPECTED;
2537
2538         if (dc_is_dp_signal(pipe_ctx->stream->signal)
2539                 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2540                 pipe_ctx->clock_source = pool->dp_clock_source;
2541         else {
2542                 pipe_ctx->clock_source = NULL;
2543
2544                 if (!dc->config.disable_disp_pll_sharing)
2545                         pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
2546                                 &context->res_ctx,
2547                                 pipe_ctx);
2548
2549                 if (pipe_ctx->clock_source == NULL)
2550                         pipe_ctx->clock_source =
2551                                 dc_resource_find_first_free_pll(
2552                                         &context->res_ctx,
2553                                         pool);
2554         }
2555
2556         if (pipe_ctx->clock_source == NULL)
2557                 return DC_NO_CLOCK_SOURCE_RESOURCE;
2558
2559         resource_reference_clock_source(
2560                 &context->res_ctx, pool,
2561                 pipe_ctx->clock_source);
2562
2563         return DC_OK;
2564 }
2565
2566 /*
2567  * Note: We need to disable output if clock sources change,
2568  * since bios does optimization and doesn't apply if changing
2569  * PHY when not already disabled.
2570  */
2571 bool pipe_need_reprogram(
2572                 struct pipe_ctx *pipe_ctx_old,
2573                 struct pipe_ctx *pipe_ctx)
2574 {
2575         if (!pipe_ctx_old->stream)
2576                 return false;
2577
2578         if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2579                 return true;
2580
2581         if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2582                 return true;
2583
2584         if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
2585                 return true;
2586
2587         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2588                         && pipe_ctx_old->stream != pipe_ctx->stream)
2589                 return true;
2590
2591         if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
2592                 return true;
2593
2594         if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2595                 return true;
2596
2597         if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2598                 return true;
2599
2600         if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2601                 return true;
2602
2603         if (is_vsc_info_packet_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2604                 return true;
2605
2606         if (false == pipe_ctx_old->stream->link->link_state_valid &&
2607                 false == pipe_ctx_old->stream->dpms_off)
2608                 return true;
2609
2610         return false;
2611 }
2612
2613 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
2614                 struct bit_depth_reduction_params *fmt_bit_depth)
2615 {
2616         enum dc_dither_option option = stream->dither_option;
2617         enum dc_pixel_encoding pixel_encoding =
2618                         stream->timing.pixel_encoding;
2619
2620         memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2621
2622         if (option == DITHER_OPTION_DEFAULT) {
2623                 switch (stream->timing.display_color_depth) {
2624                 case COLOR_DEPTH_666:
2625                         option = DITHER_OPTION_SPATIAL6;
2626                         break;
2627                 case COLOR_DEPTH_888:
2628                         option = DITHER_OPTION_SPATIAL8;
2629                         break;
2630                 case COLOR_DEPTH_101010:
2631                         option = DITHER_OPTION_SPATIAL10;
2632                         break;
2633                 default:
2634                         option = DITHER_OPTION_DISABLE;
2635                 }
2636         }
2637
2638         if (option == DITHER_OPTION_DISABLE)
2639                 return;
2640
2641         if (option == DITHER_OPTION_TRUN6) {
2642                 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2643                 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2644         } else if (option == DITHER_OPTION_TRUN8 ||
2645                         option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2646                         option == DITHER_OPTION_TRUN8_FM6) {
2647                 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2648                 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2649         } else if (option == DITHER_OPTION_TRUN10        ||
2650                         option == DITHER_OPTION_TRUN10_SPATIAL6   ||
2651                         option == DITHER_OPTION_TRUN10_SPATIAL8   ||
2652                         option == DITHER_OPTION_TRUN10_FM8     ||
2653                         option == DITHER_OPTION_TRUN10_FM6     ||
2654                         option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2655                 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2656                 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2657         }
2658
2659         /* special case - Formatter can only reduce by 4 bits at most.
2660          * When reducing from 12 to 6 bits,
2661          * HW recommends we use trunc with round mode
2662          * (if we did nothing, trunc to 10 bits would be used)
2663          * note that any 12->10 bit reduction is ignored prior to DCE8,
2664          * as the input was 10 bits.
2665          */
2666         if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2667                         option == DITHER_OPTION_SPATIAL6 ||
2668                         option == DITHER_OPTION_FM6) {
2669                 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2670                 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2671                 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2672         }
2673
2674         /* spatial dither
2675          * note that spatial modes 1-3 are never used
2676          */
2677         if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM            ||
2678                         option == DITHER_OPTION_SPATIAL6 ||
2679                         option == DITHER_OPTION_TRUN10_SPATIAL6      ||
2680                         option == DITHER_OPTION_TRUN8_SPATIAL6) {
2681                 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2682                 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2683                 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2684                 fmt_bit_depth->flags.RGB_RANDOM =
2685                                 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2686         } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM            ||
2687                         option == DITHER_OPTION_SPATIAL8 ||
2688                         option == DITHER_OPTION_SPATIAL8_FM6        ||
2689                         option == DITHER_OPTION_TRUN10_SPATIAL8      ||
2690                         option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2691                 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2692                 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2693                 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2694                 fmt_bit_depth->flags.RGB_RANDOM =
2695                                 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2696         } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2697                         option == DITHER_OPTION_SPATIAL10 ||
2698                         option == DITHER_OPTION_SPATIAL10_FM8 ||
2699                         option == DITHER_OPTION_SPATIAL10_FM6) {
2700                 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2701                 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2702                 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2703                 fmt_bit_depth->flags.RGB_RANDOM =
2704                                 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2705         }
2706
2707         if (option == DITHER_OPTION_SPATIAL6 ||
2708                         option == DITHER_OPTION_SPATIAL8 ||
2709                         option == DITHER_OPTION_SPATIAL10) {
2710                 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2711         } else {
2712                 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2713         }
2714
2715         //////////////////////
2716         //// temporal dither
2717         //////////////////////
2718         if (option == DITHER_OPTION_FM6           ||
2719                         option == DITHER_OPTION_SPATIAL8_FM6     ||
2720                         option == DITHER_OPTION_SPATIAL10_FM6     ||
2721                         option == DITHER_OPTION_TRUN10_FM6     ||
2722                         option == DITHER_OPTION_TRUN8_FM6      ||
2723                         option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2724                 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2725                 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2726         } else if (option == DITHER_OPTION_FM8        ||
2727                         option == DITHER_OPTION_SPATIAL10_FM8  ||
2728                         option == DITHER_OPTION_TRUN10_FM8) {
2729                 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2730                 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2731         } else if (option == DITHER_OPTION_FM10) {
2732                 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2733                 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2734         }
2735
2736         fmt_bit_depth->pixel_encoding = pixel_encoding;
2737 }
2738
2739 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
2740 {
2741         struct dc  *core_dc = dc;
2742         struct dc_link *link = stream->link;
2743         struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
2744         enum dc_status res = DC_OK;
2745
2746         calculate_phy_pix_clks(stream);
2747
2748         if (!tg->funcs->validate_timing(tg, &stream->timing))
2749                 res = DC_FAIL_CONTROLLER_VALIDATE;
2750
2751         if (res == DC_OK) {
2752                 if (!link->link_enc->funcs->validate_output_with_stream(
2753                                                 link->link_enc, stream))
2754                         res = DC_FAIL_ENC_VALIDATE;
2755         }
2756
2757         /* TODO: validate audio ASIC caps, encoder */
2758
2759         if (res == DC_OK)
2760                 res = dc_link_validate_mode_timing(stream,
2761                       link,
2762                       &stream->timing);
2763
2764         return res;
2765 }
2766
2767 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
2768 {
2769         enum dc_status res = DC_OK;
2770
2771         /* TODO For now validates pixel format only */
2772         if (dc->res_pool->funcs->validate_plane)
2773                 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
2774
2775         return res;
2776 }
2777
2778 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2779 {
2780         switch (format) {
2781         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2782                 return 8;
2783         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2784         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2785                 return 12;
2786         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2787         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2788         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2789         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2790                 return 16;
2791         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2792         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2793         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2794         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2795         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2796                 return 32;
2797         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2798         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2799         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2800                 return 64;
2801         default:
2802                 ASSERT_CRITICAL(false);
2803                 return -1;
2804         }
2805 }