drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2
   3
   4 #include "dm_services.h"
   5 #include "dc.h"
   6 #include "inc/core_types.h"
   7 #include "include/ddc_service_types.h"
   8 #include "include/i2caux_interface.h"
   9 #include "link_hwss.h"
  10 #include "hw_sequencer.h"
  11 #include "dc_link_dp.h"
  12 #include "dc_link_ddc.h"
  13 #include "dm_helpers.h"
  14 #include "dpcd_defs.h"
  15 #include "dsc.h"
  16 #include "resource.h"
  17 #include "clk_mgr.h"
  18
  19 static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
  20 {
  21         switch (lttpr_repeater_count) {
  22         case 0x80: // 1 lttpr repeater
  23                 return 1;
  24         case 0x40: // 2 lttpr repeaters
  25                 return 2;
  26         case 0x20: // 3 lttpr repeaters
  27                 return 3;
  28         case 0x10: // 4 lttpr repeaters
  29                 return 4;
  30         case 0x08: // 5 lttpr repeaters
  31                 return 5;
  32         case 0x04: // 6 lttpr repeaters
  33                 return 6;
  34         case 0x02: // 7 lttpr repeaters
  35                 return 7;
  36         case 0x01: // 8 lttpr repeaters
  37                 return 8;
  38         default:
  39                 break;
  40         }
  41         return 0; // invalid value
  42 }
  43
  44 static inline bool is_immediate_downstream(struct dc_link *link, uint32_t offset)
  45 {
  46         return (convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == offset);
  47 }
  48
  49 enum dc_status core_link_read_dpcd(
  50         struct dc_link *link,
  51         uint32_t address,
  52         uint8_t *data,
  53         uint32_t size)
  54 {
  55         if (!link->aux_access_disabled &&
  56                         !dm_helpers_dp_read_dpcd(link->ctx,
  57                         link, address, data, size)) {
  58                 return DC_ERROR_UNEXPECTED;
  59         }
  60
  61         return DC_OK;
  62 }
  63
  64 enum dc_status core_link_write_dpcd(
  65         struct dc_link *link,
  66         uint32_t address,
  67         const uint8_t *data,
  68         uint32_t size)
  69 {
  70         if (!link->aux_access_disabled &&
  71                         !dm_helpers_dp_write_dpcd(link->ctx,
  72                         link, address, data, size)) {
  73                 return DC_ERROR_UNEXPECTED;
  74         }
  75
  76         return DC_OK;
  77 }
  78
  79 void dp_receiver_power_ctrl(struct dc_link *link, bool on)
  80 {
  81         uint8_t state;
  82
  83         state = on ? DP_POWER_STATE_D0 : DP_POWER_STATE_D3;
  84
  85         if (link->sync_lt_in_progress)
  86                 return;
  87
  88         core_link_write_dpcd(link, DP_SET_POWER, &state,
  89                         sizeof(state));
  90 }
  91
  92 void dp_enable_link_phy(
  93         struct dc_link *link,
  94         enum signal_type signal,
  95         enum clock_source_id clock_source,
  96         const struct dc_link_settings *link_settings)
  97 {
  98         struct link_encoder *link_enc = link->link_enc;
  99         struct dc  *dc = link->ctx->dc;
 100         struct dmcu *dmcu = dc->res_pool->dmcu;
 101
 102         struct pipe_ctx *pipes =
 103                         link->dc->current_state->res_ctx.pipe_ctx;
 104         struct clock_source *dp_cs =
 105                         link->dc->res_pool->dp_clock_source;
 106         unsigned int i;
 107         /* If the current pixel clock source is not DTO(happens after
 108          * switching from HDMI passive dongle to DP on the same connector),
 109          * switch the pixel clock source to DTO.
 110          */
 111         for (i = 0; i < MAX_PIPES; i++) {
 112                 if (pipes[i].stream != NULL &&
 113                         pipes[i].stream->link == link) {
 114                         if (pipes[i].clock_source != NULL &&
 115                                         pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
 116                                 pipes[i].clock_source = dp_cs;
 117                                 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
 118                                                 pipes[i].stream->timing.pix_clk_100hz;
 119                                 pipes[i].clock_source->funcs->program_pix_clk(
 120                                                         pipes[i].clock_source,
 121                                                         &pipes[i].stream_res.pix_clk_params,
 122                                                         &pipes[i].pll_settings);
 123                         }
 124                 }
 125         }
 126
 127         link->cur_link_settings = *link_settings;
 128
 129         if (dc->clk_mgr->funcs->notify_link_rate_change)
 130                 dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
 131
 132         if (dmcu != NULL && dmcu->funcs->lock_phy)
 133                 dmcu->funcs->lock_phy(dmcu);
 134
 135         if (dc_is_dp_sst_signal(signal)) {
 136                 link_enc->funcs->enable_dp_output(
 137                                                 link_enc,
 138                                                 link_settings,
 139                                                 clock_source);
 140         } else {
 141                 link_enc->funcs->enable_dp_mst_output(
 142                                                 link_enc,
 143                                                 link_settings,
 144                                                 clock_source);
 145         }
 146
 147         if (dmcu != NULL && dmcu->funcs->unlock_phy)
 148                 dmcu->funcs->unlock_phy(dmcu);
 149
 150         dp_receiver_power_ctrl(link, true);
 151 }
 152
 153 bool edp_receiver_ready_T9(struct dc_link *link)
 154 {
 155         unsigned int tries = 0;
 156         unsigned char sinkstatus = 0;
 157         unsigned char edpRev = 0;
 158         enum dc_status result;
 159
 160         result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
 161
 162      /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
 163         if (result == DC_OK && edpRev >= DP_EDP_12) {
 164                 do {
 165                         sinkstatus = 1;
 166                         result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
 167                         if (sinkstatus == 0)
 168                                 break;
 169                         if (result != DC_OK)
 170                                 break;
 171                         udelay(100); //MAx T9
 172                 } while (++tries < 50);
 173         }
 174
 175         if (link->local_sink &&
 176                         link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
 177                 udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);
 178
 179         return result;
 180 }
 181 bool edp_receiver_ready_T7(struct dc_link *link)
 182 {
 183         unsigned char sinkstatus = 0;
 184         unsigned char edpRev = 0;
 185         enum dc_status result;
 186
 187         /* use absolute time stamp to constrain max T7*/
 188         unsigned long long enter_timestamp = 0;
 189         unsigned long long finish_timestamp = 0;
 190         unsigned long long time_taken_in_ns = 0;
 191
 192         result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
 193
 194         if (result == DC_OK && edpRev >= DP_EDP_12) {
 195                 /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
 196                 enter_timestamp = dm_get_timestamp(link->ctx);
 197                 do {
 198                         sinkstatus = 0;
 199                         result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
 200                         if (sinkstatus == 1)
 201                                 break;
 202                         if (result != DC_OK)
 203                                 break;
 204                         udelay(25);
 205                         finish_timestamp = dm_get_timestamp(link->ctx);
 206                         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, enter_timestamp);
 207                 } while (time_taken_in_ns < 50 * 1000000); //MAx T7 is 50ms
 208         }
 209
 210         if (link->local_sink &&
 211                         link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0)
 212                 udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 1000);
 213
 214         return result;
 215 }
 216
 217 void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
 218 {
 219         struct dc  *dc = link->ctx->dc;
 220         struct dmcu *dmcu = dc->res_pool->dmcu;
 221
 222         if (!link->wa_flags.dp_keep_receiver_powered)
 223                 dp_receiver_power_ctrl(link, false);
 224
 225         if (signal == SIGNAL_TYPE_EDP) {
 226                 link->link_enc->funcs->disable_output(link->link_enc, signal);
 227                 link->dc->hwss.edp_power_control(link, false);
 228         } else {
 229                 if (dmcu != NULL && dmcu->funcs->lock_phy)
 230                         dmcu->funcs->lock_phy(dmcu);
 231
 232                 link->link_enc->funcs->disable_output(link->link_enc, signal);
 233
 234                 if (dmcu != NULL && dmcu->funcs->unlock_phy)
 235                         dmcu->funcs->unlock_phy(dmcu);
 236         }
 237
 238         /* Clear current link setting.*/
 239         memset(&link->cur_link_settings, 0,
 240                         sizeof(link->cur_link_settings));
 241
 242         if (dc->clk_mgr->funcs->notify_link_rate_change)
 243                 dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
 244 }
 245
 246 void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal)
 247 {
 248         /* MST disable link only when no stream use the link */
 249         if (link->mst_stream_alloc_table.stream_count > 0)
 250                 return;
 251
 252         dp_disable_link_phy(link, signal);
 253
 254         /* set the sink to SST mode after disabling the link */
 255         dp_enable_mst_on_sink(link, false);
 256 }
 257
 258 bool dp_set_hw_training_pattern(
 259         struct dc_link *link,
 260         enum dc_dp_training_pattern pattern,
 261         uint32_t offset)
 262 {
 263         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 264
 265         switch (pattern) {
 266         case DP_TRAINING_PATTERN_SEQUENCE_1:
 267                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN1;
 268                 break;
 269         case DP_TRAINING_PATTERN_SEQUENCE_2:
 270                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN2;
 271                 break;
 272         case DP_TRAINING_PATTERN_SEQUENCE_3:
 273                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3;
 274                 break;
 275         case DP_TRAINING_PATTERN_SEQUENCE_4:
 276                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
 277                 break;
 278         default:
 279                 break;
 280         }
 281
 282         dp_set_hw_test_pattern(link, test_pattern, NULL, 0);
 283
 284         return true;
 285 }
 286
 287 void dp_set_hw_lane_settings(
 288         struct dc_link *link,
 289         const struct link_training_settings *link_settings,
 290         uint32_t offset)
 291 {
 292         struct link_encoder *encoder = link->link_enc;
 293
 294         if (link->lttpr_non_transparent_mode && !is_immediate_downstream(link, offset))
 295                 return;
 296
 297         /* call Encoder to set lane settings */
 298         encoder->funcs->dp_set_lane_settings(encoder, link_settings);
 299 }
 300
 301 void dp_set_hw_test_pattern(
 302         struct dc_link *link,
 303         enum dp_test_pattern test_pattern,
 304         uint8_t *custom_pattern,
 305         uint32_t custom_pattern_size)
 306 {
 307         struct encoder_set_dp_phy_pattern_param pattern_param = {0};
 308         struct link_encoder *encoder = link->link_enc;
 309
 310         pattern_param.dp_phy_pattern = test_pattern;
 311         pattern_param.custom_pattern = custom_pattern;
 312         pattern_param.custom_pattern_size = custom_pattern_size;
 313         pattern_param.dp_panel_mode = dp_get_panel_mode(link);
 314
 315         encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param);
 316 }
 317
 318 void dp_retrain_link_dp_test(struct dc_link *link,
 319                         struct dc_link_settings *link_setting,
 320                         bool skip_video_pattern)
 321 {
 322         struct pipe_ctx *pipes =
 323                         &link->dc->current_state->res_ctx.pipe_ctx[0];
 324         unsigned int i;
 325
 326         for (i = 0; i < MAX_PIPES; i++) {
 327                 if (pipes[i].stream != NULL &&
 328                         !pipes[i].top_pipe && !pipes[i].prev_odm_pipe &&
 329                         pipes[i].stream->link != NULL &&
 330                         pipes[i].stream_res.stream_enc != NULL &&
 331                         pipes[i].stream->link == link) {
 332                         udelay(100);
 333
 334                         pipes[i].stream_res.stream_enc->funcs->dp_blank(
 335                                         pipes[i].stream_res.stream_enc);
 336
 337                         /* disable any test pattern that might be active */
 338                         dp_set_hw_test_pattern(link,
 339                                         DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
 340
 341                         dp_receiver_power_ctrl(link, false);
 342
 343                         link->dc->hwss.disable_stream(&pipes[i]);
 344                         if ((&pipes[i])->stream_res.audio && !link->dc->debug.az_endpoint_mute_only)
 345                                 (&pipes[i])->stream_res.audio->funcs->az_disable((&pipes[i])->stream_res.audio);
 346
 347                         link->link_enc->funcs->disable_output(
 348                                         link->link_enc,
 349                                         SIGNAL_TYPE_DISPLAY_PORT);
 350
 351                         /* Clear current link setting. */
 352                         memset(&link->cur_link_settings, 0,
 353                                 sizeof(link->cur_link_settings));
 354
 355                         perform_link_training_with_retries(
 356                                         link_setting,
 357                                         skip_video_pattern,
 358                                         LINK_TRAINING_ATTEMPTS,
 359                                         &pipes[i],
 360                                         SIGNAL_TYPE_DISPLAY_PORT);
 361
 362                         link->dc->hwss.enable_stream(&pipes[i]);
 363
 364                         link->dc->hwss.unblank_stream(&pipes[i],
 365                                         link_setting);
 366
 367                         if (pipes[i].stream_res.audio) {
 368                                 /* notify audio driver for
 369                                  * audio modes of monitor */
 370                                 pipes[i].stream_res.audio->funcs->az_enable(
 371                                                 pipes[i].stream_res.audio);
 372
 373                                 /* un-mute audio */
 374                                 /* TODO: audio should be per stream rather than
 375                                  * per link */
 376                                 pipes[i].stream_res.stream_enc->funcs->
 377                                 audio_mute_control(
 378                                         pipes[i].stream_res.stream_enc, false);
 379                         }
 380                 }
 381         }
 382 }
 383
 384 #define DC_LOGGER \
 385         dsc->ctx->logger
 386 static void dsc_optc_config_log(struct display_stream_compressor *dsc,
 387                 struct dsc_optc_config *config)
 388 {
 389         uint32_t precision = 1 << 28;
 390         uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision;
 391         uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision;
 392         uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod;
 393
 394         /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC
 395          * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is
 396          * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal
 397          */
 398         ll_bytes_per_pix_fraq *= 10000000;
 399         ll_bytes_per_pix_fraq /= precision;
 400
 401         DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)",
 402                         config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq);
 403         DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444);
 404         DC_LOG_DSC("\tslice_width %d", config->slice_width);
 405 }
 406
 407 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
 408 {
 409         struct dc *dc = pipe_ctx->stream->ctx->dc;
 410         struct dc_stream_state *stream = pipe_ctx->stream;
 411         bool result = false;
 412
 413         if (dc_is_virtual_signal(stream->signal) || IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
 414                 result = true;
 415         else
 416                 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable);
 417         return result;
 418 }
 419
 420 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first,
 421  * i.e. after dp_enable_dsc_on_rx() had been called
 422  */
 423 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 424 {
 425         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 426         struct dc *dc = pipe_ctx->stream->ctx->dc;
 427         struct dc_stream_state *stream = pipe_ctx->stream;
 428         struct pipe_ctx *odm_pipe;
 429         int opp_cnt = 1;
 430
 431         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 432                 opp_cnt++;
 433
 434         if (enable) {
 435                 struct dsc_config dsc_cfg;
 436                 struct dsc_optc_config dsc_optc_cfg;
 437                 enum optc_dsc_mode optc_dsc_mode;
 438
 439                 /* Enable DSC hw block */
 440                 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
 441                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
 442                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
 443                 dsc_cfg.color_depth = stream->timing.display_color_depth;
 444                 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
 445                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
 446                 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
 447                 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
 448
 449                 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
 450                 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
 451                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 452                         struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
 453
 454                         odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
 455                         odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
 456                 }
 457                 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
 458                 dsc_cfg.pic_width *= opp_cnt;
 459
 460                 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
 461
 462                 /* Enable DSC in encoder */
 463                 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 464                         DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
 465                         dsc_optc_config_log(dsc, &dsc_optc_cfg);
 466                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
 467                                                                         optc_dsc_mode,
 468                                                                         dsc_optc_cfg.bytes_per_pixel,
 469                                                                         dsc_optc_cfg.slice_width);
 470
 471                         /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */
 472                 }
 473
 474                 /* Enable DSC in OPTC */
 475                 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
 476                 dsc_optc_config_log(dsc, &dsc_optc_cfg);
 477                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
 478                                                         optc_dsc_mode,
 479                                                         dsc_optc_cfg.bytes_per_pixel,
 480                                                         dsc_optc_cfg.slice_width);
 481         } else {
 482                 /* disable DSC in OPTC */
 483                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
 484                                 pipe_ctx->stream_res.tg,
 485                                 OPTC_DSC_DISABLED, 0, 0);
 486
 487                 /* disable DSC in stream encoder */
 488                 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 489                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
 490                                         pipe_ctx->stream_res.stream_enc,
 491                                         OPTC_DSC_DISABLED, 0, 0);
 492
 493                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
 494                                         pipe_ctx->stream_res.stream_enc, false, NULL);
 495                 }
 496
 497                 /* disable DSC block */
 498                 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
 499                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 500                         odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
 501         }
 502 }
 503
 504 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
 505 {
 506         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 507         bool result = false;
 508
 509         if (!pipe_ctx->stream->timing.flags.DSC)
 510                 goto out;
 511         if (!dsc)
 512                 goto out;
 513
 514         if (enable) {
 515                 if (dp_set_dsc_on_rx(pipe_ctx, true)) {
 516                         dp_set_dsc_on_stream(pipe_ctx, true);
 517                         result = true;
 518                 }
 519         } else {
 520                 dp_set_dsc_on_rx(pipe_ctx, false);
 521                 dp_set_dsc_on_stream(pipe_ctx, false);
 522                 result = true;
 523         }
 524 out:
 525         return result;
 526 }
 527
 528 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
 529 {
 530         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 531         struct dc *dc = pipe_ctx->stream->ctx->dc;
 532         struct dc_stream_state *stream = pipe_ctx->stream;
 533
 534         if (!pipe_ctx->stream->timing.flags.DSC || !dsc)
 535                 return false;
 536
 537         if (enable) {
 538                 struct dsc_config dsc_cfg;
 539                 uint8_t dsc_packed_pps[128];
 540
 541                 memset(&dsc_cfg, 0, sizeof(dsc_cfg));
 542                 memset(dsc_packed_pps, 0, 128);
 543
 544                 /* Enable DSC hw block */
 545                 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
 546                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
 547                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
 548                 dsc_cfg.color_depth = stream->timing.display_color_depth;
 549                 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
 550                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
 551
 552                 DC_LOG_DSC(" ");
 553                 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
 554                 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 555                         DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
 556                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
 557                                                                         pipe_ctx->stream_res.stream_enc,
 558                                                                         true,
 559                                                                         &dsc_packed_pps[0]);
 560                 }
 561         } else {
 562                 /* disable DSC PPS in stream encoder */
 563                 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 564                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
 565                                                 pipe_ctx->stream_res.stream_enc, false, NULL);
 566                 }
 567         }
 568
 569         return true;
 570 }
 571
 572
 573 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
 574 {
 575         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 576
 577         if (!pipe_ctx->stream->timing.flags.DSC)
 578                 return false;
 579         if (!dsc)
 580                 return false;
 581
 582         dp_set_dsc_on_stream(pipe_ctx, true);
 583         dp_set_dsc_pps_sdp(pipe_ctx, true);
 584         return true;
 585 }
 586