drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2
   3
   4 #include "dm_services.h"
   5 #include "dc.h"
   6 #include "inc/core_types.h"
   7 #include "include/ddc_service_types.h"
   8 #include "include/i2caux_interface.h"
   9 #include "link_hwss.h"
  10 #include "hw_sequencer.h"
  11 #include "dc_link_dp.h"
  12 #include "dc_link_ddc.h"
  13 #include "dm_helpers.h"
  14 #include "dpcd_defs.h"
  15 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
  16 #include "dsc.h"
  17 #endif
  18 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  19 #include "resource.h"
  20 #endif
  21
  22 static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
  23 {
  24         switch (lttpr_repeater_count) {
  25         case 0x80: // 1 lttpr repeater
  26                 return 1;
  27         case 0x40: // 2 lttpr repeaters
  28                 return 2;
  29         case 0x20: // 3 lttpr repeaters
  30                 return 3;
  31         case 0x10: // 4 lttpr repeaters
  32                 return 4;
  33         case 0x08: // 5 lttpr repeaters
  34                 return 5;
  35         case 0x04: // 6 lttpr repeaters
  36                 return 6;
  37         case 0x02: // 7 lttpr repeaters
  38                 return 7;
  39         case 0x01: // 8 lttpr repeaters
  40                 return 8;
  41         default:
  42                 break;
  43         }
  44         return 0; // invalid value
  45 }
  46
  47 static inline bool is_immediate_downstream(struct dc_link *link, uint32_t offset)
  48 {
  49         return (convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == offset);
  50 }
  51
  52 enum dc_status core_link_read_dpcd(
  53         struct dc_link *link,
  54         uint32_t address,
  55         uint8_t *data,
  56         uint32_t size)
  57 {
  58         if (!link->aux_access_disabled &&
  59                         !dm_helpers_dp_read_dpcd(link->ctx,
  60                         link, address, data, size)) {
  61                 return DC_ERROR_UNEXPECTED;
  62         }
  63
  64         return DC_OK;
  65 }
  66
  67 enum dc_status core_link_write_dpcd(
  68         struct dc_link *link,
  69         uint32_t address,
  70         const uint8_t *data,
  71         uint32_t size)
  72 {
  73         if (!link->aux_access_disabled &&
  74                         !dm_helpers_dp_write_dpcd(link->ctx,
  75                         link, address, data, size)) {
  76                 return DC_ERROR_UNEXPECTED;
  77         }
  78
  79         return DC_OK;
  80 }
  81
  82 void dp_receiver_power_ctrl(struct dc_link *link, bool on)
  83 {
  84         uint8_t state;
  85
  86         state = on ? DP_POWER_STATE_D0 : DP_POWER_STATE_D3;
  87
  88         if (link->sync_lt_in_progress)
  89                 return;
  90
  91         core_link_write_dpcd(link, DP_SET_POWER, &state,
  92                         sizeof(state));
  93 }
  94
  95 void dp_enable_link_phy(
  96         struct dc_link *link,
  97         enum signal_type signal,
  98         enum clock_source_id clock_source,
  99         const struct dc_link_settings *link_settings)
 100 {
 101         struct link_encoder *link_enc = link->link_enc;
 102         struct dc  *core_dc = link->ctx->dc;
 103         struct dmcu *dmcu = core_dc->res_pool->dmcu;
 104
 105         struct pipe_ctx *pipes =
 106                         link->dc->current_state->res_ctx.pipe_ctx;
 107         struct clock_source *dp_cs =
 108                         link->dc->res_pool->dp_clock_source;
 109         unsigned int i;
 110         /* If the current pixel clock source is not DTO(happens after
 111          * switching from HDMI passive dongle to DP on the same connector),
 112          * switch the pixel clock source to DTO.
 113          */
 114         for (i = 0; i < MAX_PIPES; i++) {
 115                 if (pipes[i].stream != NULL &&
 116                         pipes[i].stream->link == link) {
 117                         if (pipes[i].clock_source != NULL &&
 118                                         pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
 119                                 pipes[i].clock_source = dp_cs;
 120                                 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
 121                                                 pipes[i].stream->timing.pix_clk_100hz;
 122                                 pipes[i].clock_source->funcs->program_pix_clk(
 123                                                         pipes[i].clock_source,
 124                                                         &pipes[i].stream_res.pix_clk_params,
 125                                                         &pipes[i].pll_settings);
 126                         }
 127                 }
 128         }
 129
 130         if (dmcu != NULL && dmcu->funcs->lock_phy)
 131                 dmcu->funcs->lock_phy(dmcu);
 132
 133         if (dc_is_dp_sst_signal(signal)) {
 134                 link_enc->funcs->enable_dp_output(
 135                                                 link_enc,
 136                                                 link_settings,
 137                                                 clock_source);
 138         } else {
 139                 link_enc->funcs->enable_dp_mst_output(
 140                                                 link_enc,
 141                                                 link_settings,
 142                                                 clock_source);
 143         }
 144
 145         if (dmcu != NULL && dmcu->funcs->unlock_phy)
 146                 dmcu->funcs->unlock_phy(dmcu);
 147
 148         link->cur_link_settings = *link_settings;
 149
 150         dp_receiver_power_ctrl(link, true);
 151 }
 152
 153 bool edp_receiver_ready_T9(struct dc_link *link)
 154 {
 155         unsigned int tries = 0;
 156         unsigned char sinkstatus = 0;
 157         unsigned char edpRev = 0;
 158         enum dc_status result = DC_OK;
 159         result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
 160         if (edpRev < DP_EDP_12)
 161                 return true;
 162         /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
 163         do {
 164                 sinkstatus = 1;
 165                 result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
 166                 if (sinkstatus == 0)
 167                         break;
 168                 if (result != DC_OK)
 169                         break;
 170                 udelay(100); //MAx T9
 171         } while (++tries < 50);
 172
 173         if (link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
 174                 udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);
 175
 176         return result;
 177 }
 178 bool edp_receiver_ready_T7(struct dc_link *link)
 179 {
 180         unsigned int tries = 0;
 181         unsigned char sinkstatus = 0;
 182         unsigned char edpRev = 0;
 183         enum dc_status result = DC_OK;
 184
 185         result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
 186         if (result == DC_OK && edpRev < DP_EDP_12)
 187                 return true;
 188         /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
 189         do {
 190                 sinkstatus = 0;
 191                 result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
 192                 if (sinkstatus == 1)
 193                         break;
 194                 if (result != DC_OK)
 195                         break;
 196                 udelay(25); //MAx T7 is 50ms
 197         } while (++tries < 300);
 198
 199         if (link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0)
 200                 udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 1000);
 201
 202         return result;
 203 }
 204
 205 void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
 206 {
 207         struct dc  *core_dc = link->ctx->dc;
 208         struct dmcu *dmcu = core_dc->res_pool->dmcu;
 209
 210         if (!link->wa_flags.dp_keep_receiver_powered)
 211                 dp_receiver_power_ctrl(link, false);
 212
 213         if (signal == SIGNAL_TYPE_EDP) {
 214                 link->link_enc->funcs->disable_output(link->link_enc, signal);
 215                 link->dc->hwss.edp_power_control(link, false);
 216         } else {
 217                 if (dmcu != NULL && dmcu->funcs->lock_phy)
 218                         dmcu->funcs->lock_phy(dmcu);
 219
 220                 link->link_enc->funcs->disable_output(link->link_enc, signal);
 221
 222                 if (dmcu != NULL && dmcu->funcs->unlock_phy)
 223                         dmcu->funcs->unlock_phy(dmcu);
 224         }
 225
 226         /* Clear current link setting.*/
 227         memset(&link->cur_link_settings, 0,
 228                         sizeof(link->cur_link_settings));
 229 }
 230
 231 void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal)
 232 {
 233         /* MST disable link only when no stream use the link */
 234         if (link->mst_stream_alloc_table.stream_count > 0)
 235                 return;
 236
 237         dp_disable_link_phy(link, signal);
 238
 239         /* set the sink to SST mode after disabling the link */
 240         dp_enable_mst_on_sink(link, false);
 241 }
 242
 243 bool dp_set_hw_training_pattern(
 244         struct dc_link *link,
 245         enum dc_dp_training_pattern pattern,
 246         uint32_t offset)
 247 {
 248         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 249
 250         switch (pattern) {
 251         case DP_TRAINING_PATTERN_SEQUENCE_1:
 252                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN1;
 253                 break;
 254         case DP_TRAINING_PATTERN_SEQUENCE_2:
 255                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN2;
 256                 break;
 257         case DP_TRAINING_PATTERN_SEQUENCE_3:
 258                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3;
 259                 break;
 260         case DP_TRAINING_PATTERN_SEQUENCE_4:
 261                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
 262                 break;
 263         default:
 264                 break;
 265         }
 266
 267         dp_set_hw_test_pattern(link, test_pattern, NULL, 0);
 268
 269         return true;
 270 }
 271
 272 void dp_set_hw_lane_settings(
 273         struct dc_link *link,
 274         const struct link_training_settings *link_settings,
 275         uint32_t offset)
 276 {
 277         struct link_encoder *encoder = link->link_enc;
 278
 279         if (!link->is_lttpr_mode_transparent && !is_immediate_downstream(link, offset))
 280                 return;
 281
 282         /* call Encoder to set lane settings */
 283         encoder->funcs->dp_set_lane_settings(encoder, link_settings);
 284 }
 285
 286 void dp_set_hw_test_pattern(
 287         struct dc_link *link,
 288         enum dp_test_pattern test_pattern,
 289         uint8_t *custom_pattern,
 290         uint32_t custom_pattern_size)
 291 {
 292         struct encoder_set_dp_phy_pattern_param pattern_param = {0};
 293         struct link_encoder *encoder = link->link_enc;
 294
 295         pattern_param.dp_phy_pattern = test_pattern;
 296         pattern_param.custom_pattern = custom_pattern;
 297         pattern_param.custom_pattern_size = custom_pattern_size;
 298         pattern_param.dp_panel_mode = dp_get_panel_mode(link);
 299
 300         encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param);
 301 }
 302
 303 void dp_retrain_link_dp_test(struct dc_link *link,
 304                         struct dc_link_settings *link_setting,
 305                         bool skip_video_pattern)
 306 {
 307         struct pipe_ctx *pipes =
 308                         &link->dc->current_state->res_ctx.pipe_ctx[0];
 309         unsigned int i;
 310
 311         for (i = 0; i < MAX_PIPES; i++) {
 312                 if (pipes[i].stream != NULL &&
 313                         !pipes[i].top_pipe && !pipes[i].prev_odm_pipe &&
 314                         pipes[i].stream->link != NULL &&
 315                         pipes[i].stream_res.stream_enc != NULL &&
 316                         pipes[i].stream->link == link) {
 317                         udelay(100);
 318
 319                         pipes[i].stream_res.stream_enc->funcs->dp_blank(
 320                                         pipes[i].stream_res.stream_enc);
 321
 322                         /* disable any test pattern that might be active */
 323                         dp_set_hw_test_pattern(link,
 324                                         DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
 325
 326                         dp_receiver_power_ctrl(link, false);
 327
 328                         link->dc->hwss.disable_stream(&pipes[i]);
 329                         if ((&pipes[i])->stream_res.audio && !link->dc->debug.az_endpoint_mute_only)
 330                                 (&pipes[i])->stream_res.audio->funcs->az_disable((&pipes[i])->stream_res.audio);
 331
 332                         link->link_enc->funcs->disable_output(
 333                                         link->link_enc,
 334                                         SIGNAL_TYPE_DISPLAY_PORT);
 335
 336                         /* Clear current link setting. */
 337                         memset(&link->cur_link_settings, 0,
 338                                 sizeof(link->cur_link_settings));
 339
 340                         link->link_enc->funcs->enable_dp_output(
 341                                                 link->link_enc,
 342                                                 link_setting,
 343                                                 pipes[i].clock_source->id);
 344                         link->cur_link_settings = *link_setting;
 345
 346                         dp_receiver_power_ctrl(link, true);
 347
 348                         perform_link_training_with_retries(
 349                                         link,
 350                                         link_setting,
 351                                         skip_video_pattern,
 352                                         LINK_TRAINING_ATTEMPTS);
 353
 354
 355                         link->dc->hwss.enable_stream(&pipes[i]);
 356
 357                         link->dc->hwss.unblank_stream(&pipes[i],
 358                                         link_setting);
 359
 360                         if (pipes[i].stream_res.audio) {
 361                                 /* notify audio driver for
 362                                  * audio modes of monitor */
 363                                 pipes[i].stream_res.audio->funcs->az_enable(
 364                                                 pipes[i].stream_res.audio);
 365
 366                                 /* un-mute audio */
 367                                 /* TODO: audio should be per stream rather than
 368                                  * per link */
 369                                 pipes[i].stream_res.stream_enc->funcs->
 370                                 audio_mute_control(
 371                                         pipes[i].stream_res.stream_enc, false);
 372                         }
 373                 }
 374         }
 375 }
 376
 377 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 378 #define DC_LOGGER \
 379         dsc->ctx->logger
 380 static void dsc_optc_config_log(struct display_stream_compressor *dsc,
 381                 struct dsc_optc_config *config)
 382 {
 383         uint32_t precision = 1 << 28;
 384         uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision;
 385         uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision;
 386         uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod;
 387
 388         /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC
 389          * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is
 390          * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal
 391          */
 392         ll_bytes_per_pix_fraq *= 10000000;
 393         ll_bytes_per_pix_fraq /= precision;
 394
 395         DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)",
 396                         config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq);
 397         DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444);
 398         DC_LOG_DSC("\tslice_width %d", config->slice_width);
 399 }
 400
 401 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
 402 {
 403         struct dc *core_dc = pipe_ctx->stream->ctx->dc;
 404         struct dc_stream_state *stream = pipe_ctx->stream;
 405         bool result = false;
 406
 407         if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
 408                 result = true;
 409         else
 410                 result = dm_helpers_dp_write_dsc_enable(core_dc->ctx, stream, enable);
 411         return result;
 412 }
 413
 414 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first,
 415  * i.e. after dp_enable_dsc_on_rx() had been called
 416  */
 417 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 418 {
 419         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 420         struct dc *core_dc = pipe_ctx->stream->ctx->dc;
 421         struct dc_stream_state *stream = pipe_ctx->stream;
 422         struct pipe_ctx *odm_pipe;
 423         int opp_cnt = 1;
 424
 425         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 426                 opp_cnt++;
 427
 428         if (enable) {
 429                 struct dsc_config dsc_cfg;
 430                 struct dsc_optc_config dsc_optc_cfg;
 431                 enum optc_dsc_mode optc_dsc_mode;
 432
 433                 /* Enable DSC hw block */
 434                 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
 435                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
 436                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
 437                 dsc_cfg.color_depth = stream->timing.display_color_depth;
 438                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
 439                 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
 440                 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
 441
 442                 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
 443                 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
 444                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 445                         struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
 446
 447                         odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
 448                         odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
 449                 }
 450                 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
 451                 dsc_cfg.pic_width *= opp_cnt;
 452
 453                 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
 454
 455                 /* Enable DSC in encoder */
 456                 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
 457                         DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
 458                         dsc_optc_config_log(dsc, &dsc_optc_cfg);
 459                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
 460                                                                         optc_dsc_mode,
 461                                                                         dsc_optc_cfg.bytes_per_pixel,
 462                                                                         dsc_optc_cfg.slice_width);
 463
 464                         /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */
 465                 }
 466
 467                 /* Enable DSC in OPTC */
 468                 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
 469                 dsc_optc_config_log(dsc, &dsc_optc_cfg);
 470                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
 471                                                         optc_dsc_mode,
 472                                                         dsc_optc_cfg.bytes_per_pixel,
 473                                                         dsc_optc_cfg.slice_width);
 474         } else {
 475                 /* disable DSC in OPTC */
 476                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
 477                                 pipe_ctx->stream_res.tg,
 478                                 OPTC_DSC_DISABLED, 0, 0);
 479
 480                 /* disable DSC in stream encoder */
 481                 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
 482                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
 483                                         pipe_ctx->stream_res.stream_enc,
 484                                         OPTC_DSC_DISABLED, 0, 0);
 485
 486                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
 487                                         pipe_ctx->stream_res.stream_enc, false, NULL);
 488                 }
 489
 490                 /* disable DSC block */
 491                 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
 492                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 493                         odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
 494         }
 495 }
 496
 497 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
 498 {
 499         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 500         bool result = false;
 501
 502         if (!pipe_ctx->stream->timing.flags.DSC)
 503                 goto out;
 504         if (!dsc)
 505                 goto out;
 506
 507         if (enable) {
 508                 if (dp_set_dsc_on_rx(pipe_ctx, true)) {
 509                         dp_set_dsc_on_stream(pipe_ctx, true);
 510                         result = true;
 511                 }
 512         } else {
 513                 dp_set_dsc_on_rx(pipe_ctx, false);
 514                 dp_set_dsc_on_stream(pipe_ctx, false);
 515                 result = true;
 516         }
 517 out:
 518         return result;
 519 }
 520
 521 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
 522 {
 523         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 524         struct dc *core_dc = pipe_ctx->stream->ctx->dc;
 525         struct dc_stream_state *stream = pipe_ctx->stream;
 526
 527         if (!pipe_ctx->stream->timing.flags.DSC || !dsc)
 528                 return false;
 529
 530         if (enable) {
 531                 struct dsc_config dsc_cfg;
 532                 uint8_t dsc_packed_pps[128];
 533
 534                 /* Enable DSC hw block */
 535                 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
 536                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
 537                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
 538                 dsc_cfg.color_depth = stream->timing.display_color_depth;
 539                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
 540
 541                 DC_LOG_DSC(" ");
 542                 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
 543                 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
 544                         DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
 545                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
 546                                                                         pipe_ctx->stream_res.stream_enc,
 547                                                                         true,
 548                                                                         &dsc_packed_pps[0]);
 549                 }
 550         } else {
 551                 /* disable DSC PPS in stream encoder */
 552                 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
 553                         pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
 554                                                 pipe_ctx->stream_res.stream_enc, false, NULL);
 555                 }
 556         }
 557
 558         return true;
 559 }
 560
 561
 562 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
 563 {
 564         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
 565
 566         if (!pipe_ctx->stream->timing.flags.DSC)
 567                 return false;
 568         if (!dsc)
 569                 return false;
 570
 571         dp_set_dsc_on_stream(pipe_ctx, true);
 572         dp_set_dsc_pps_sdp(pipe_ctx, true);
 573         return true;
 574 }
 575 #endif
 576