drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24 #include "dm_services.h"
  25 #include "dc.h"
  26 #include "dc_link_dp.h"
  27 #include "dm_helpers.h"
  28 #include "opp.h"
  29 #include "dsc.h"
  30 #include "resource.h"
  31
  32 #include "inc/core_types.h"
  33 #include "link_hwss.h"
  34 #include "dc_link_ddc.h"
  35 #include "core_status.h"
  36 #include "dpcd_defs.h"
  37 #include "dc_dmub_srv.h"
  38 #include "dce/dmub_hw_lock_mgr.h"
  39 #include "inc/dc_link_dpia.h"
  40 #include "inc/link_enc_cfg.h"
  41
  42 /*Travis*/
  43 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
  44 /*Nutmeg*/
  45 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
  46
  47 #define DC_LOGGER \
  48         link->ctx->logger
  49 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
  50
  51 #include "link_dpcd.h"
  52
  53         /* maximum pre emphasis level allowed for each voltage swing level*/
  54         static const enum dc_pre_emphasis
  55         voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
  56                                             PRE_EMPHASIS_LEVEL2,
  57                                             PRE_EMPHASIS_LEVEL1,
  58                                             PRE_EMPHASIS_DISABLED };
  59
  60 enum {
  61         POST_LT_ADJ_REQ_LIMIT = 6,
  62         POST_LT_ADJ_REQ_TIMEOUT = 200
  63 };
  64
  65 #if defined(CONFIG_DRM_AMD_DC_DCN)
  66 struct dp_lt_fallback_entry {
  67         enum dc_lane_count lane_count;
  68         enum dc_link_rate link_rate;
  69 };
  70
  71 static const struct dp_lt_fallback_entry dp_lt_fallbacks[] = {
  72                 /* This link training fallback array is ordered by
  73                  * link bandwidth from highest to lowest.
  74                  * DP specs makes it a normative policy to always
  75                  * choose the next highest link bandwidth during
  76                  * link training fallback.
  77                  */
  78                 {LANE_COUNT_FOUR, LINK_RATE_UHBR20},
  79                 {LANE_COUNT_FOUR, LINK_RATE_UHBR13_5},
  80                 {LANE_COUNT_TWO, LINK_RATE_UHBR20},
  81                 {LANE_COUNT_FOUR, LINK_RATE_UHBR10},
  82                 {LANE_COUNT_TWO, LINK_RATE_UHBR13_5},
  83                 {LANE_COUNT_FOUR, LINK_RATE_HIGH3},
  84                 {LANE_COUNT_ONE, LINK_RATE_UHBR20},
  85                 {LANE_COUNT_TWO, LINK_RATE_UHBR10},
  86                 {LANE_COUNT_FOUR, LINK_RATE_HIGH2},
  87                 {LANE_COUNT_ONE, LINK_RATE_UHBR13_5},
  88                 {LANE_COUNT_TWO, LINK_RATE_HIGH3},
  89                 {LANE_COUNT_ONE, LINK_RATE_UHBR10},
  90                 {LANE_COUNT_TWO, LINK_RATE_HIGH2},
  91                 {LANE_COUNT_FOUR, LINK_RATE_HIGH},
  92                 {LANE_COUNT_ONE, LINK_RATE_HIGH3},
  93                 {LANE_COUNT_FOUR, LINK_RATE_LOW},
  94                 {LANE_COUNT_ONE, LINK_RATE_HIGH2},
  95                 {LANE_COUNT_TWO, LINK_RATE_HIGH},
  96                 {LANE_COUNT_TWO, LINK_RATE_LOW},
  97                 {LANE_COUNT_ONE, LINK_RATE_HIGH},
  98                 {LANE_COUNT_ONE, LINK_RATE_LOW},
  99 };
 100 #endif
 101
 102 static bool decide_fallback_link_setting(
 103                 struct dc_link_settings initial_link_settings,
 104                 struct dc_link_settings *current_link_setting,
 105                 enum link_training_result training_result);
 106 static struct dc_link_settings get_common_supported_link_settings(
 107                 struct dc_link_settings link_setting_a,
 108                 struct dc_link_settings link_setting_b);
 109 static void maximize_lane_settings(const struct link_training_settings *lt_settings,
 110                 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
 111 static void override_lane_settings(const struct link_training_settings *lt_settings,
 112                 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
 113
 114 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
 115                 const struct dc_link_settings *link_settings)
 116 {
 117         union training_aux_rd_interval training_rd_interval;
 118         uint32_t wait_in_micro_secs = 100;
 119 #if defined(CONFIG_DRM_AMD_DC_DCN)
 120         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
 121         if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING &&
 122                         link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
 123                 core_link_read_dpcd(
 124                                 link,
 125                                 DP_TRAINING_AUX_RD_INTERVAL,
 126                                 (uint8_t *)&training_rd_interval,
 127                                 sizeof(training_rd_interval));
 128                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
 129                         wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
 130         }
 131 #else
 132         core_link_read_dpcd(
 133                         link,
 134                         DP_TRAINING_AUX_RD_INTERVAL,
 135                         (uint8_t *)&training_rd_interval,
 136                         sizeof(training_rd_interval));
 137         if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
 138                 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
 139 #endif
 140         return wait_in_micro_secs;
 141 }
 142
 143 static uint32_t get_eq_training_aux_rd_interval(
 144         struct dc_link *link,
 145         const struct dc_link_settings *link_settings)
 146 {
 147 #if defined(CONFIG_DRM_AMD_DC_DCN)
 148         union training_aux_rd_interval training_rd_interval;
 149
 150         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
 151         if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
 152                 core_link_read_dpcd(
 153                                 link,
 154                                 DP_128b_132b_TRAINING_AUX_RD_INTERVAL,
 155                                 (uint8_t *)&training_rd_interval,
 156                                 sizeof(training_rd_interval));
 157         } else if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING &&
 158                         link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
 159                 core_link_read_dpcd(
 160                                 link,
 161                                 DP_TRAINING_AUX_RD_INTERVAL,
 162                                 (uint8_t *)&training_rd_interval,
 163                                 sizeof(training_rd_interval));
 164         }
 165
 166         switch (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL) {
 167         case 0: return 400;
 168         case 1: return 4000;
 169         case 2: return 8000;
 170         case 3: return 12000;
 171         case 4: return 16000;
 172         case 5: return 32000;
 173         case 6: return 64000;
 174         default: return 400;
 175         }
 176 #else
 177         union training_aux_rd_interval training_rd_interval;
 178         uint32_t wait_in_micro_secs = 400;
 179
 180         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
 181         /* overwrite the delay if rev > 1.1*/
 182         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
 183                 /* DP 1.2 or later - retrieve delay through
 184                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
 185                 core_link_read_dpcd(
 186                         link,
 187                         DP_TRAINING_AUX_RD_INTERVAL,
 188                         (uint8_t *)&training_rd_interval,
 189                         sizeof(training_rd_interval));
 190
 191                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
 192                         wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
 193         }
 194
 195         return wait_in_micro_secs;
 196 #endif
 197 }
 198
 199 void dp_wait_for_training_aux_rd_interval(
 200         struct dc_link *link,
 201         uint32_t wait_in_micro_secs)
 202 {
 203 #if defined(CONFIG_DRM_AMD_DC_DCN)
 204         if (wait_in_micro_secs > 16000)
 205                 msleep(wait_in_micro_secs/1000);
 206         else
 207                 udelay(wait_in_micro_secs);
 208 #else
 209         udelay(wait_in_micro_secs);
 210 #endif
 211
 212         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
 213                 __func__,
 214                 wait_in_micro_secs);
 215 }
 216
 217 enum dpcd_training_patterns
 218         dc_dp_training_pattern_to_dpcd_training_pattern(
 219         struct dc_link *link,
 220         enum dc_dp_training_pattern pattern)
 221 {
 222         enum dpcd_training_patterns dpcd_tr_pattern =
 223         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 224
 225         switch (pattern) {
 226         case DP_TRAINING_PATTERN_SEQUENCE_1:
 227                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 228                 break;
 229         case DP_TRAINING_PATTERN_SEQUENCE_2:
 230                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 231                 break;
 232         case DP_TRAINING_PATTERN_SEQUENCE_3:
 233                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 234                 break;
 235         case DP_TRAINING_PATTERN_SEQUENCE_4:
 236                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 237                 break;
 238 #if defined(CONFIG_DRM_AMD_DC_DCN)
 239         case DP_128b_132b_TPS1:
 240                 dpcd_tr_pattern = DPCD_128b_132b_TPS1;
 241                 break;
 242         case DP_128b_132b_TPS2:
 243                 dpcd_tr_pattern = DPCD_128b_132b_TPS2;
 244                 break;
 245         case DP_128b_132b_TPS2_CDS:
 246                 dpcd_tr_pattern = DPCD_128b_132b_TPS2_CDS;
 247                 break;
 248 #endif
 249         case DP_TRAINING_PATTERN_VIDEOIDLE:
 250                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
 251                 break;
 252         default:
 253                 ASSERT(0);
 254                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 255                         __func__, pattern);
 256                 break;
 257         }
 258
 259         return dpcd_tr_pattern;
 260 }
 261
 262 static void dpcd_set_training_pattern(
 263         struct dc_link *link,
 264         enum dc_dp_training_pattern training_pattern)
 265 {
 266         union dpcd_training_pattern dpcd_pattern = {0};
 267
 268         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 269                         dc_dp_training_pattern_to_dpcd_training_pattern(
 270                                         link, training_pattern);
 271
 272         core_link_write_dpcd(
 273                 link,
 274                 DP_TRAINING_PATTERN_SET,
 275                 &dpcd_pattern.raw,
 276                 1);
 277
 278         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
 279                 __func__,
 280                 DP_TRAINING_PATTERN_SET,
 281                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 282 }
 283
 284 static enum dc_dp_training_pattern decide_cr_training_pattern(
 285                 const struct dc_link_settings *link_settings)
 286 {
 287         switch (dp_get_link_encoding_format(link_settings)) {
 288         case DP_8b_10b_ENCODING:
 289         default:
 290                 return DP_TRAINING_PATTERN_SEQUENCE_1;
 291 #if defined(CONFIG_DRM_AMD_DC_DCN)
 292         case DP_128b_132b_ENCODING:
 293                 return DP_128b_132b_TPS1;
 294 #endif
 295         }
 296 }
 297
 298 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
 299                 const struct dc_link_settings *link_settings)
 300 {
 301         struct link_encoder *link_enc;
 302 #if defined(CONFIG_DRM_AMD_DC_DCN)
 303         struct encoder_feature_support *enc_caps;
 304         struct dpcd_caps *rx_caps = &link->dpcd_caps;
 305         enum dc_dp_training_pattern pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
 306
 307         /* Access link encoder capability based on whether it is statically
 308          * or dynamically assigned to a link.
 309          */
 310         if (link->is_dig_mapping_flexible &&
 311                         link->dc->res_pool->funcs->link_encs_assign)
 312                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
 313         else
 314                 link_enc = link->link_enc;
 315         ASSERT(link_enc);
 316         enc_caps = &link_enc->features;
 317
 318         switch (dp_get_link_encoding_format(link_settings)) {
 319         case DP_8b_10b_ENCODING:
 320                 if (enc_caps->flags.bits.IS_TPS4_CAPABLE &&
 321                                 rx_caps->max_down_spread.bits.TPS4_SUPPORTED)
 322                         pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 323                 else if (enc_caps->flags.bits.IS_TPS3_CAPABLE &&
 324                                 rx_caps->max_ln_count.bits.TPS3_SUPPORTED)
 325                         pattern = DP_TRAINING_PATTERN_SEQUENCE_3;
 326                 else
 327                         pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
 328                 break;
 329         case DP_128b_132b_ENCODING:
 330                 pattern = DP_128b_132b_TPS2;
 331                 break;
 332         default:
 333                 pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
 334                 break;
 335         }
 336         return pattern;
 337 #else
 338         enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
 339         struct encoder_feature_support *features;
 340         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 341
 342         /* Access link encoder capability based on whether it is statically
 343          * or dynamically assigned to a link.
 344          */
 345         if (link->is_dig_mapping_flexible &&
 346                         link->dc->res_pool->funcs->link_encs_assign)
 347                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
 348         else
 349                 link_enc = link->link_enc;
 350         ASSERT(link_enc);
 351         features = &link_enc->features;
 352
 353         if (features->flags.bits.IS_TPS3_CAPABLE)
 354                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 355
 356         if (features->flags.bits.IS_TPS4_CAPABLE)
 357                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
 358
 359         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 360                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
 361                 return DP_TRAINING_PATTERN_SEQUENCE_4;
 362
 363         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 364                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
 365                 return DP_TRAINING_PATTERN_SEQUENCE_3;
 366
 367         return DP_TRAINING_PATTERN_SEQUENCE_2;
 368 #endif
 369 }
 370
 371 #if defined(CONFIG_DRM_AMD_DC_DCN)
 372 static uint8_t get_dpcd_link_rate(const struct dc_link_settings *link_settings)
 373 {
 374         uint8_t link_rate = 0;
 375         enum dp_link_encoding encoding = dp_get_link_encoding_format(link_settings);
 376
 377         if (encoding == DP_128b_132b_ENCODING)
 378                 switch (link_settings->link_rate) {
 379                 case LINK_RATE_UHBR10:
 380                         link_rate = 0x1;
 381                         break;
 382                 case LINK_RATE_UHBR20:
 383                         link_rate = 0x2;
 384                         break;
 385                 case LINK_RATE_UHBR13_5:
 386                         link_rate = 0x4;
 387                         break;
 388                 default:
 389                         link_rate = 0;
 390                         break;
 391                 }
 392         else if (encoding == DP_8b_10b_ENCODING)
 393                 link_rate = (uint8_t) link_settings->link_rate;
 394         else
 395                 link_rate = 0;
 396
 397         return link_rate;
 398 }
 399 #endif
 400
 401 static void vendor_specific_lttpr_wa_one_start(struct dc_link *link)
 402 {
 403         const uint8_t vendor_lttpr_write_data[4] = {0x1, 0x50, 0x63, 0xff};
 404         const uint8_t offset = dp_convert_to_count(
 405                         link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
 406         uint32_t vendor_lttpr_write_address = 0xF004F;
 407
 408         if (offset != 0xFF)
 409                 vendor_lttpr_write_address +=
 410                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 411
 412         /* W/A for certain LTTPR to reset their lane settings, part one of two */
 413         core_link_write_dpcd(
 414                         link,
 415                         vendor_lttpr_write_address,
 416                         &vendor_lttpr_write_data[0],
 417                         sizeof(vendor_lttpr_write_data));
 418 }
 419
 420 static void vendor_specific_lttpr_wa_one_end(
 421         struct dc_link *link,
 422         uint8_t retry_count)
 423 {
 424         const uint8_t vendor_lttpr_write_data[4] = {0x1, 0x50, 0x63, 0x0};
 425         const uint8_t offset = dp_convert_to_count(
 426                         link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
 427         uint32_t vendor_lttpr_write_address = 0xF004F;
 428
 429         if (!retry_count) {
 430                 if (offset != 0xFF)
 431                         vendor_lttpr_write_address +=
 432                                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 433
 434                 /* W/A for certain LTTPR to reset their lane settings, part two of two */
 435                 core_link_write_dpcd(
 436                                 link,
 437                                 vendor_lttpr_write_address,
 438                                 &vendor_lttpr_write_data[0],
 439                                 sizeof(vendor_lttpr_write_data));
 440         }
 441 }
 442
 443 static void vendor_specific_lttpr_wa_one_two(
 444         struct dc_link *link,
 445         const uint8_t rate)
 446 {
 447         if (link->apply_vendor_specific_lttpr_link_rate_wa) {
 448                 uint8_t toggle_rate = 0x0;
 449
 450                 if (rate == 0x6)
 451                         toggle_rate = 0xA;
 452                 else
 453                         toggle_rate = 0x6;
 454
 455                 if (link->vendor_specific_lttpr_link_rate_wa == rate) {
 456                         /* W/A for certain LTTPR to reset internal state for link training */
 457                         core_link_write_dpcd(
 458                                         link,
 459                                         DP_LINK_BW_SET,
 460                                         &toggle_rate,
 461                                         1);
 462                 }
 463
 464                 /* Store the last attempted link rate for this link */
 465                 link->vendor_specific_lttpr_link_rate_wa = rate;
 466         }
 467 }
 468
 469 static void vendor_specific_lttpr_wa_three(
 470         struct dc_link *link,
 471         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX])
 472 {
 473         const uint8_t vendor_lttpr_write_data_vs[3] = {0x0, 0x53, 0x63};
 474         const uint8_t vendor_lttpr_write_data_pe[3] = {0x0, 0x54, 0x63};
 475         const uint8_t offset = dp_convert_to_count(
 476                         link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
 477         uint32_t vendor_lttpr_write_address = 0xF004F;
 478         uint32_t vendor_lttpr_read_address = 0xF0053;
 479         uint8_t dprx_vs = 0;
 480         uint8_t dprx_pe = 0;
 481         uint8_t lane;
 482
 483         if (offset != 0xFF) {
 484                 vendor_lttpr_write_address +=
 485                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 486                 vendor_lttpr_read_address +=
 487                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 488         }
 489
 490         /* W/A to read lane settings requested by DPRX */
 491         core_link_write_dpcd(
 492                         link,
 493                         vendor_lttpr_write_address,
 494                         &vendor_lttpr_write_data_vs[0],
 495                         sizeof(vendor_lttpr_write_data_vs));
 496         core_link_read_dpcd(
 497                         link,
 498                         vendor_lttpr_read_address,
 499                         &dprx_vs,
 500                         1);
 501         core_link_write_dpcd(
 502                         link,
 503                         vendor_lttpr_write_address,
 504                         &vendor_lttpr_write_data_pe[0],
 505                         sizeof(vendor_lttpr_write_data_pe));
 506         core_link_read_dpcd(
 507                         link,
 508                         vendor_lttpr_read_address,
 509                         &dprx_pe,
 510                         1);
 511
 512         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
 513                 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_LANE = (dprx_vs >> (2 * lane)) & 0x3;
 514                 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_LANE = (dprx_pe >> (2 * lane)) & 0x3;
 515         }
 516 }
 517
 518 static void vendor_specific_lttpr_wa_four(
 519         struct dc_link *link,
 520         bool apply_wa)
 521 {
 522         const uint8_t vendor_lttpr_write_data_one[4] = {0x1, 0x55, 0x63, 0x8};
 523         const uint8_t vendor_lttpr_write_data_two[4] = {0x1, 0x55, 0x63, 0x0};
 524         const uint8_t offset = dp_convert_to_count(
 525                         link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
 526         uint32_t vendor_lttpr_write_address = 0xF004F;
 527 #if defined(CONFIG_DRM_AMD_DC_DP2_0)
 528         uint8_t sink_status = 0;
 529         uint8_t i;
 530 #endif
 531
 532         if (offset != 0xFF)
 533                 vendor_lttpr_write_address +=
 534                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 535
 536         /* W/A to pass through DPCD write of TPS=0 to DPRX */
 537         if (apply_wa) {
 538                 core_link_write_dpcd(
 539                                 link,
 540                                 vendor_lttpr_write_address,
 541                                 &vendor_lttpr_write_data_one[0],
 542                                 sizeof(vendor_lttpr_write_data_one));
 543         }
 544
 545         /* clear training pattern set */
 546         dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
 547
 548         if (apply_wa) {
 549                 core_link_write_dpcd(
 550                                 link,
 551                                 vendor_lttpr_write_address,
 552                                 &vendor_lttpr_write_data_two[0],
 553                                 sizeof(vendor_lttpr_write_data_two));
 554         }
 555
 556 #if defined(CONFIG_DRM_AMD_DC_DP2_0)
 557         /* poll for intra-hop disable */
 558         for (i = 0; i < 10; i++) {
 559                 if ((core_link_read_dpcd(link, DP_SINK_STATUS, &sink_status, 1) == DC_OK) &&
 560                                 (sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION) == 0)
 561                         break;
 562                 udelay(1000);
 563         }
 564 #endif
 565 }
 566
 567 enum dc_status dpcd_set_link_settings(
 568         struct dc_link *link,
 569         const struct link_training_settings *lt_settings)
 570 {
 571         uint8_t rate;
 572         enum dc_status status;
 573
 574         union down_spread_ctrl downspread = {0};
 575         union lane_count_set lane_count_set = {0};
 576
 577         downspread.raw = (uint8_t)
 578         (lt_settings->link_settings.link_spread);
 579
 580         lane_count_set.bits.LANE_COUNT_SET =
 581         lt_settings->link_settings.lane_count;
 582
 583         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
 584         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 585
 586
 587         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
 588                         lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
 589                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 590                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 591         }
 592
 593         status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 594                 &downspread.raw, sizeof(downspread));
 595
 596         status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 597                 &lane_count_set.raw, 1);
 598
 599         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
 600                         lt_settings->link_settings.use_link_rate_set == true) {
 601                 rate = 0;
 602                 /* WA for some MUX chips that will power down with eDP and lose supported
 603                  * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
 604                  * MUX chip gets link rate set back before link training.
 605                  */
 606                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 607                         uint8_t supported_link_rates[16];
 608
 609                         core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
 610                                         supported_link_rates, sizeof(supported_link_rates));
 611                 }
 612                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 613                 status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
 614                                 &lt_settings->link_settings.link_rate_set, 1);
 615         } else {
 616 #if defined(CONFIG_DRM_AMD_DC_DCN)
 617                 rate = get_dpcd_link_rate(&lt_settings->link_settings);
 618 #else
 619                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 620 #endif
 621                 if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
 622                                         (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
 623                                         link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
 624                         vendor_specific_lttpr_wa_one_start(link);
 625
 626                 if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
 627                                         (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN))
 628                         vendor_specific_lttpr_wa_one_two(link, rate);
 629
 630                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 631         }
 632
 633         if (rate) {
 634                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 635                         __func__,
 636                         DP_LINK_BW_SET,
 637                         lt_settings->link_settings.link_rate,
 638                         DP_LANE_COUNT_SET,
 639                         lt_settings->link_settings.lane_count,
 640                         lt_settings->enhanced_framing,
 641                         DP_DOWNSPREAD_CTRL,
 642                         lt_settings->link_settings.link_spread);
 643         } else {
 644                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 645                         __func__,
 646                         DP_LINK_RATE_SET,
 647                         lt_settings->link_settings.link_rate_set,
 648                         DP_LANE_COUNT_SET,
 649                         lt_settings->link_settings.lane_count,
 650                         lt_settings->enhanced_framing,
 651                         DP_DOWNSPREAD_CTRL,
 652                         lt_settings->link_settings.link_spread);
 653         }
 654
 655         return status;
 656 }
 657
 658 uint8_t dc_dp_initialize_scrambling_data_symbols(
 659         struct dc_link *link,
 660         enum dc_dp_training_pattern pattern)
 661 {
 662         uint8_t disable_scrabled_data_symbols = 0;
 663
 664         switch (pattern) {
 665         case DP_TRAINING_PATTERN_SEQUENCE_1:
 666         case DP_TRAINING_PATTERN_SEQUENCE_2:
 667         case DP_TRAINING_PATTERN_SEQUENCE_3:
 668                 disable_scrabled_data_symbols = 1;
 669                 break;
 670         case DP_TRAINING_PATTERN_SEQUENCE_4:
 671 #if defined(CONFIG_DRM_AMD_DC_DCN)
 672         case DP_128b_132b_TPS1:
 673         case DP_128b_132b_TPS2:
 674 #endif
 675                 disable_scrabled_data_symbols = 0;
 676                 break;
 677         default:
 678                 ASSERT(0);
 679                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 680                         __func__, pattern);
 681                 break;
 682         }
 683         return disable_scrabled_data_symbols;
 684 }
 685
 686 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 687 {
 688         return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
 689 }
 690
 691 static void dpcd_set_lt_pattern_and_lane_settings(
 692         struct dc_link *link,
 693         const struct link_training_settings *lt_settings,
 694         enum dc_dp_training_pattern pattern,
 695         uint32_t offset)
 696 {
 697         uint32_t dpcd_base_lt_offset;
 698
 699         uint8_t dpcd_lt_buffer[5] = {0};
 700         union dpcd_training_pattern dpcd_pattern = { 0 };
 701         uint32_t size_in_bytes;
 702         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 703         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
 704
 705         if (is_repeater(link, offset))
 706                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
 707                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 708
 709         /*****************************************************************
 710         * DpcdAddress_TrainingPatternSet
 711         *****************************************************************/
 712         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 713                 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
 714
 715         dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
 716                 dc_dp_initialize_scrambling_data_symbols(link, pattern);
 717
 718         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
 719                 = dpcd_pattern.raw;
 720
 721         if (is_repeater(link, offset)) {
 722                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
 723                         __func__,
 724                         offset,
 725                         dpcd_base_lt_offset,
 726                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 727         } else {
 728                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
 729                         __func__,
 730                         dpcd_base_lt_offset,
 731                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 732         }
 733
 734         /* concatenate everything into one buffer*/
 735         size_in_bytes = lt_settings->link_settings.lane_count *
 736                         sizeof(lt_settings->dpcd_lane_settings[0]);
 737
 738          // 0x00103 - 0x00102
 739         memmove(
 740                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
 741                 lt_settings->dpcd_lane_settings,
 742                 size_in_bytes);
 743
 744         if (is_repeater(link, offset)) {
 745 #if defined(CONFIG_DRM_AMD_DC_DCN)
 746                 if (dp_get_link_encoding_format(&lt_settings->link_settings) ==
 747                                 DP_128b_132b_ENCODING)
 748                         DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 749                                         " 0x%X TX_FFE_PRESET_VALUE = %x\n",
 750                                         __func__,
 751                                         offset,
 752                                         dpcd_base_lt_offset,
 753                                         lt_settings->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
 754                 else if (dp_get_link_encoding_format(&lt_settings->link_settings) ==
 755                                 DP_8b_10b_ENCODING)
 756 #endif
 757                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 758                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 759                         __func__,
 760                         offset,
 761                         dpcd_base_lt_offset,
 762                         lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
 763                         lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
 764                         lt_settings->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
 765                         lt_settings->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
 766         } else {
 767 #if defined(CONFIG_DRM_AMD_DC_DCN)
 768                 if (dp_get_link_encoding_format(&lt_settings->link_settings) ==
 769                                 DP_128b_132b_ENCODING)
 770                         DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X TX_FFE_PRESET_VALUE = %x\n",
 771                                         __func__,
 772                                         dpcd_base_lt_offset,
 773                                         lt_settings->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
 774                 else if (dp_get_link_encoding_format(&lt_settings->link_settings) ==
 775                                 DP_8b_10b_ENCODING)
 776 #endif
 777                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 778                         __func__,
 779                         dpcd_base_lt_offset,
 780                         lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
 781                         lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
 782                         lt_settings->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
 783                         lt_settings->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
 784         }
 785         if (edp_workaround) {
 786                 /* for eDP write in 2 parts because the 5-byte burst is
 787                 * causing issues on some eDP panels (EPR#366724)
 788                 */
 789                 core_link_write_dpcd(
 790                         link,
 791                         DP_TRAINING_PATTERN_SET,
 792                         &dpcd_pattern.raw,
 793                         sizeof(dpcd_pattern.raw));
 794
 795                 core_link_write_dpcd(
 796                         link,
 797                         DP_TRAINING_LANE0_SET,
 798                         (uint8_t *)(lt_settings->dpcd_lane_settings),
 799                         size_in_bytes);
 800
 801 #if defined(CONFIG_DRM_AMD_DC_DCN)
 802         } else if (dp_get_link_encoding_format(&lt_settings->link_settings) ==
 803                         DP_128b_132b_ENCODING) {
 804                 core_link_write_dpcd(
 805                                 link,
 806                                 dpcd_base_lt_offset,
 807                                 dpcd_lt_buffer,
 808                                 sizeof(dpcd_lt_buffer));
 809 #endif
 810                 } else
 811                 /* write it all in (1 + number-of-lanes)-byte burst*/
 812                         core_link_write_dpcd(
 813                                 link,
 814                                 dpcd_base_lt_offset,
 815                                 dpcd_lt_buffer,
 816                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 817 }
 818
 819 bool dp_is_cr_done(enum dc_lane_count ln_count,
 820         union lane_status *dpcd_lane_status)
 821 {
 822         uint32_t lane;
 823         /*LANEx_CR_DONE bits All 1's?*/
 824         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 825                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 826                         return false;
 827         }
 828         return true;
 829 }
 830
 831 bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
 832                 union lane_status *dpcd_lane_status)
 833 {
 834         bool done = true;
 835         uint32_t lane;
 836         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 837                 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 838                         done = false;
 839         return done;
 840 }
 841
 842 bool dp_is_symbol_locked(enum dc_lane_count ln_count,
 843                 union lane_status *dpcd_lane_status)
 844 {
 845         bool locked = true;
 846         uint32_t lane;
 847         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 848                 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
 849                         locked = false;
 850         return locked;
 851 }
 852
 853 bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
 854 {
 855         return align_status.bits.INTERLANE_ALIGN_DONE == 1;
 856 }
 857
 858 void dp_hw_to_dpcd_lane_settings(
 859                 const struct link_training_settings *lt_settings,
 860                 const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
 861                 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])
 862 {
 863         uint8_t lane = 0;
 864
 865         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
 866                 if (dp_get_link_encoding_format(&lt_settings->link_settings) ==
 867                                 DP_8b_10b_ENCODING) {
 868                         dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET =
 869                                         (uint8_t)(hw_lane_settings[lane].VOLTAGE_SWING);
 870                         dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET =
 871                                         (uint8_t)(hw_lane_settings[lane].PRE_EMPHASIS);
 872                         dpcd_lane_settings[lane].bits.MAX_SWING_REACHED =
 873                                         (hw_lane_settings[lane].VOLTAGE_SWING ==
 874                                                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 875                         dpcd_lane_settings[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 876                                         (hw_lane_settings[lane].PRE_EMPHASIS ==
 877                                                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 878                 }
 879 #if defined(CONFIG_DRM_AMD_DC_DCN)
 880                 else if (dp_get_link_encoding_format(&lt_settings->link_settings) ==
 881                                 DP_128b_132b_ENCODING) {
 882                         dpcd_lane_settings[lane].tx_ffe.PRESET_VALUE =
 883                                         hw_lane_settings[lane].FFE_PRESET.settings.level;
 884                 }
 885 #endif
 886         }
 887 }
 888
 889 void dp_decide_lane_settings(
 890                 const struct link_training_settings *lt_settings,
 891                 const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
 892                 struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
 893                 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])
 894 {
 895         uint32_t lane;
 896
 897         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
 898                 if (dp_get_link_encoding_format(&lt_settings->link_settings) ==
 899                                 DP_8b_10b_ENCODING) {
 900                         hw_lane_settings[lane].VOLTAGE_SWING =
 901                                         (enum dc_voltage_swing)(ln_adjust[lane].bits.
 902                                                         VOLTAGE_SWING_LANE);
 903                         hw_lane_settings[lane].PRE_EMPHASIS =
 904                                         (enum dc_pre_emphasis)(ln_adjust[lane].bits.
 905                                                         PRE_EMPHASIS_LANE);
 906                 }
 907 #if defined(CONFIG_DRM_AMD_DC_DCN)
 908                 else if (dp_get_link_encoding_format(&lt_settings->link_settings) ==
 909                                 DP_128b_132b_ENCODING) {
 910                         hw_lane_settings[lane].FFE_PRESET.raw =
 911                                         ln_adjust[lane].tx_ffe.PRESET_VALUE;
 912                 }
 913 #endif
 914         }
 915         dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings);
 916
 917         if (lt_settings->disallow_per_lane_settings) {
 918                 /* we find the maximum of the requested settings across all lanes*/
 919                 /* and set this maximum for all lanes*/
 920                 maximize_lane_settings(lt_settings, hw_lane_settings);
 921                 override_lane_settings(lt_settings, hw_lane_settings);
 922
 923                 if (lt_settings->always_match_dpcd_with_hw_lane_settings)
 924                         dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings);
 925         }
 926
 927 }
 928
 929 static uint8_t get_nibble_at_index(const uint8_t *buf,
 930         uint32_t index)
 931 {
 932         uint8_t nibble;
 933         nibble = buf[index / 2];
 934
 935         if (index % 2)
 936                 nibble >>= 4;
 937         else
 938                 nibble &= 0x0F;
 939
 940         return nibble;
 941 }
 942
 943 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 944         enum dc_voltage_swing voltage)
 945 {
 946         enum dc_pre_emphasis pre_emphasis;
 947         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 948
 949         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 950                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 951
 952         return pre_emphasis;
 953
 954 }
 955
 956 static void maximize_lane_settings(const struct link_training_settings *lt_settings,
 957                 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
 958 {
 959         uint32_t lane;
 960         struct dc_lane_settings max_requested;
 961
 962         max_requested.VOLTAGE_SWING = lane_settings[0].VOLTAGE_SWING;
 963         max_requested.PRE_EMPHASIS = lane_settings[0].PRE_EMPHASIS;
 964 #if defined(CONFIG_DRM_AMD_DC_DCN)
 965         max_requested.FFE_PRESET = lane_settings[0].FFE_PRESET;
 966 #endif
 967
 968         /* Determine what the maximum of the requested settings are*/
 969         for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) {
 970                 if (lane_settings[lane].VOLTAGE_SWING > max_requested.VOLTAGE_SWING)
 971                         max_requested.VOLTAGE_SWING = lane_settings[lane].VOLTAGE_SWING;
 972
 973                 if (lane_settings[lane].PRE_EMPHASIS > max_requested.PRE_EMPHASIS)
 974                         max_requested.PRE_EMPHASIS = lane_settings[lane].PRE_EMPHASIS;
 975 #if defined(CONFIG_DRM_AMD_DC_DCN)
 976                 if (lane_settings[lane].FFE_PRESET.settings.level >
 977                                 max_requested.FFE_PRESET.settings.level)
 978                         max_requested.FFE_PRESET.settings.level =
 979                                         lane_settings[lane].FFE_PRESET.settings.level;
 980 #endif
 981         }
 982
 983         /* make sure the requested settings are
 984          * not higher than maximum settings*/
 985         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 986                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 987
 988         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 989                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 990 #if defined(CONFIG_DRM_AMD_DC_DCN)
 991         if (max_requested.FFE_PRESET.settings.level > DP_FFE_PRESET_MAX_LEVEL)
 992                 max_requested.FFE_PRESET.settings.level = DP_FFE_PRESET_MAX_LEVEL;
 993 #endif
 994
 995         /* make sure the pre-emphasis matches the voltage swing*/
 996         if (max_requested.PRE_EMPHASIS >
 997                 get_max_pre_emphasis_for_voltage_swing(
 998                         max_requested.VOLTAGE_SWING))
 999                 max_requested.PRE_EMPHASIS =
1000                 get_max_pre_emphasis_for_voltage_swing(
1001                         max_requested.VOLTAGE_SWING);
1002
1003         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1004                 lane_settings[lane].VOLTAGE_SWING = max_requested.VOLTAGE_SWING;
1005                 lane_settings[lane].PRE_EMPHASIS = max_requested.PRE_EMPHASIS;
1006 #if defined(CONFIG_DRM_AMD_DC_DCN)
1007                 lane_settings[lane].FFE_PRESET = max_requested.FFE_PRESET;
1008 #endif
1009         }
1010 }
1011
1012 static void override_lane_settings(const struct link_training_settings *lt_settings,
1013                 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
1014 {
1015         uint32_t lane;
1016
1017         if (lt_settings->voltage_swing == NULL &&
1018             lt_settings->pre_emphasis == NULL &&
1019 #if defined(CONFIG_DRM_AMD_DC_DCN)
1020             lt_settings->ffe_preset == NULL &&
1021 #endif
1022             lt_settings->post_cursor2 == NULL)
1023
1024                 return;
1025
1026         for (lane = 1; lane < LANE_COUNT_DP_MAX; lane++) {
1027                 if (lt_settings->voltage_swing)
1028                         lane_settings[lane].VOLTAGE_SWING = *lt_settings->voltage_swing;
1029                 if (lt_settings->pre_emphasis)
1030                         lane_settings[lane].PRE_EMPHASIS = *lt_settings->pre_emphasis;
1031                 if (lt_settings->post_cursor2)
1032                         lane_settings[lane].POST_CURSOR2 = *lt_settings->post_cursor2;
1033 #if defined(CONFIG_DRM_AMD_DC_DCN)
1034                 if (lt_settings->ffe_preset)
1035                         lane_settings[lane].FFE_PRESET = *lt_settings->ffe_preset;
1036 #endif
1037         }
1038 }
1039
1040 enum dc_status dp_get_lane_status_and_lane_adjust(
1041         struct dc_link *link,
1042         const struct link_training_settings *link_training_setting,
1043         union lane_status ln_status[LANE_COUNT_DP_MAX],
1044         union lane_align_status_updated *ln_align,
1045         union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
1046         uint32_t offset)
1047 {
1048         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
1049         uint8_t lane_adjust_offset = 4;
1050         unsigned int lane01_adjust_address;
1051         uint8_t dpcd_buf[6] = {0};
1052         uint32_t lane;
1053         enum dc_status status;
1054
1055         if (is_repeater(link, offset)) {
1056                 lane01_status_address =
1057                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
1058                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1059                 lane_adjust_offset = 3;
1060         }
1061
1062         status = core_link_read_dpcd(
1063                 link,
1064                 lane01_status_address,
1065                 (uint8_t *)(dpcd_buf),
1066                 sizeof(dpcd_buf));
1067
1068         for (lane = 0; lane <
1069                 (uint32_t)(link_training_setting->link_settings.lane_count);
1070                 lane++) {
1071
1072                 ln_status[lane].raw =
1073                         get_nibble_at_index(&dpcd_buf[0], lane);
1074                 ln_adjust[lane].raw =
1075                         get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
1076         }
1077
1078         ln_align->raw = dpcd_buf[2];
1079
1080         if (is_repeater(link, offset)) {
1081                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
1082                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
1083                         __func__,
1084                         offset,
1085                         lane01_status_address, dpcd_buf[0],
1086                         lane01_status_address + 1, dpcd_buf[1]);
1087         } else {
1088                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
1089                         __func__,
1090                         lane01_status_address, dpcd_buf[0],
1091                         lane01_status_address + 1, dpcd_buf[1]);
1092         }
1093         lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
1094
1095         if (is_repeater(link, offset))
1096                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
1097                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1098
1099         if (is_repeater(link, offset)) {
1100                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
1101                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
1102                                         __func__,
1103                                         offset,
1104                                         lane01_adjust_address,
1105                                         dpcd_buf[lane_adjust_offset],
1106                                         lane01_adjust_address + 1,
1107                                         dpcd_buf[lane_adjust_offset + 1]);
1108         } else {
1109                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
1110                         __func__,
1111                         lane01_adjust_address,
1112                         dpcd_buf[lane_adjust_offset],
1113                         lane01_adjust_address + 1,
1114                         dpcd_buf[lane_adjust_offset + 1]);
1115         }
1116
1117         return status;
1118 }
1119
1120 enum dc_status dpcd_set_lane_settings(
1121         struct dc_link *link,
1122         const struct link_training_settings *link_training_setting,
1123         uint32_t offset)
1124 {
1125         unsigned int lane0_set_address;
1126         enum dc_status status;
1127
1128         lane0_set_address = DP_TRAINING_LANE0_SET;
1129
1130         if (is_repeater(link, offset))
1131                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
1132                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1133
1134         status = core_link_write_dpcd(link,
1135                 lane0_set_address,
1136                 (uint8_t *)(link_training_setting->dpcd_lane_settings),
1137                 link_training_setting->link_settings.lane_count);
1138
1139         if (is_repeater(link, offset)) {
1140 #if defined(CONFIG_DRM_AMD_DC_DCN)
1141                 if (dp_get_link_encoding_format(&link_training_setting->link_settings) ==
1142                                 DP_128b_132b_ENCODING)
1143                         DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
1144                                         " 0x%X TX_FFE_PRESET_VALUE = %x\n",
1145                                         __func__,
1146                                         offset,
1147                                         lane0_set_address,
1148                                         link_training_setting->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
1149                 else if (dp_get_link_encoding_format(&link_training_setting->link_settings) ==
1150                                 DP_8b_10b_ENCODING)
1151 #endif
1152                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
1153                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
1154                         __func__,
1155                         offset,
1156                         lane0_set_address,
1157                         link_training_setting->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1158                         link_training_setting->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1159                         link_training_setting->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1160                         link_training_setting->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1161
1162         } else {
1163 #if defined(CONFIG_DRM_AMD_DC_DCN)
1164                 if (dp_get_link_encoding_format(&link_training_setting->link_settings) ==
1165                                 DP_128b_132b_ENCODING)
1166                         DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X TX_FFE_PRESET_VALUE = %x\n",
1167                                         __func__,
1168                                         lane0_set_address,
1169                                         link_training_setting->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
1170                 else if (dp_get_link_encoding_format(&link_training_setting->link_settings) ==
1171                                 DP_8b_10b_ENCODING)
1172 #endif
1173                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
1174                         __func__,
1175                         lane0_set_address,
1176                         link_training_setting->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1177                         link_training_setting->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1178                         link_training_setting->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1179                         link_training_setting->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1180         }
1181
1182         return status;
1183 }
1184
1185 bool dp_is_max_vs_reached(
1186         const struct link_training_settings *lt_settings)
1187 {
1188         uint32_t lane;
1189         for (lane = 0; lane <
1190                 (uint32_t)(lt_settings->link_settings.lane_count);
1191                 lane++) {
1192                 if (lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET
1193                         == VOLTAGE_SWING_MAX_LEVEL)
1194                         return true;
1195         }
1196         return false;
1197
1198 }
1199
1200 static bool perform_post_lt_adj_req_sequence(
1201         struct dc_link *link,
1202         struct link_training_settings *lt_settings)
1203 {
1204         enum dc_lane_count lane_count =
1205         lt_settings->link_settings.lane_count;
1206
1207         uint32_t adj_req_count;
1208         uint32_t adj_req_timer;
1209         bool req_drv_setting_changed;
1210         uint32_t lane;
1211
1212         req_drv_setting_changed = false;
1213         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
1214         adj_req_count++) {
1215
1216                 req_drv_setting_changed = false;
1217
1218                 for (adj_req_timer = 0;
1219                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
1220                         adj_req_timer++) {
1221
1222                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1223                         union lane_align_status_updated
1224                                 dpcd_lane_status_updated;
1225                         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
1226
1227                         dp_get_lane_status_and_lane_adjust(
1228                                 link,
1229                                 lt_settings,
1230                                 dpcd_lane_status,
1231                                 &dpcd_lane_status_updated,
1232                                 dpcd_lane_adjust,
1233                                 DPRX);
1234
1235                         if (dpcd_lane_status_updated.bits.
1236                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
1237                                 return true;
1238
1239                         if (!dp_is_cr_done(lane_count, dpcd_lane_status))
1240                                 return false;
1241
1242                         if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
1243                                         !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
1244                                         !dp_is_interlane_aligned(dpcd_lane_status_updated))
1245                                 return false;
1246
1247                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
1248
1249                                 if (lt_settings->
1250                                 dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET !=
1251                                 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_LANE ||
1252                                 lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET !=
1253                                 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_LANE) {
1254
1255                                         req_drv_setting_changed = true;
1256                                         break;
1257                                 }
1258                         }
1259
1260                         if (req_drv_setting_changed) {
1261                                 dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
1262                                                 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
1263
1264                                 dc_link_dp_set_drive_settings(link,
1265                                                 lt_settings);
1266                                 break;
1267                         }
1268
1269                         msleep(1);
1270                 }
1271
1272                 if (!req_drv_setting_changed) {
1273                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
1274                                 __func__);
1275
1276                         ASSERT(0);
1277                         return true;
1278                 }
1279         }
1280         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
1281                 __func__);
1282
1283         ASSERT(0);
1284         return true;
1285
1286 }
1287
1288 /* Only used for channel equalization */
1289 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
1290 {
1291         unsigned int aux_rd_interval_us = 400;
1292
1293         switch (dpcd_aux_read_interval) {
1294         case 0x01:
1295                 aux_rd_interval_us = 4000;
1296                 break;
1297         case 0x02:
1298                 aux_rd_interval_us = 8000;
1299                 break;
1300         case 0x03:
1301                 aux_rd_interval_us = 12000;
1302                 break;
1303         case 0x04:
1304                 aux_rd_interval_us = 16000;
1305                 break;
1306 #if defined(CONFIG_DRM_AMD_DC_DCN)
1307         case 0x05:
1308                 aux_rd_interval_us = 32000;
1309                 break;
1310         case 0x06:
1311                 aux_rd_interval_us = 64000;
1312                 break;
1313 #endif
1314         default:
1315                 break;
1316         }
1317
1318         return aux_rd_interval_us;
1319 }
1320
1321 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
1322                                         union lane_status *dpcd_lane_status)
1323 {
1324         enum link_training_result result = LINK_TRAINING_SUCCESS;
1325
1326         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
1327                 result = LINK_TRAINING_CR_FAIL_LANE0;
1328         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
1329                 result = LINK_TRAINING_CR_FAIL_LANE1;
1330         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
1331                 result = LINK_TRAINING_CR_FAIL_LANE23;
1332         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
1333                 result = LINK_TRAINING_CR_FAIL_LANE23;
1334         return result;
1335 }
1336
1337 static enum link_training_result perform_channel_equalization_sequence(
1338         struct dc_link *link,
1339         struct link_training_settings *lt_settings,
1340         uint32_t offset)
1341 {
1342         enum dc_dp_training_pattern tr_pattern;
1343         uint32_t retries_ch_eq;
1344         uint32_t wait_time_microsec;
1345         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1346         union lane_align_status_updated dpcd_lane_status_updated = {0};
1347         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
1348         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
1349
1350         /* Note: also check that TPS4 is a supported feature*/
1351         tr_pattern = lt_settings->pattern_for_eq;
1352
1353 #if defined(CONFIG_DRM_AMD_DC_DCN)
1354         if (is_repeater(link, offset) && dp_get_link_encoding_format(&lt_settings->link_settings) == DP_8b_10b_ENCODING)
1355                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
1356 #else
1357         if (is_repeater(link, offset))
1358                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
1359 #endif
1360
1361         dp_set_hw_training_pattern(link, tr_pattern, offset);
1362
1363         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
1364                 retries_ch_eq++) {
1365
1366                 dp_set_hw_lane_settings(link, lt_settings, offset);
1367
1368                 /* 2. update DPCD*/
1369                 if (!retries_ch_eq)
1370                         /* EPR #361076 - write as a 5-byte burst,
1371                          * but only for the 1-st iteration
1372                          */
1373
1374                         dpcd_set_lt_pattern_and_lane_settings(
1375                                 link,
1376                                 lt_settings,
1377                                 tr_pattern, offset);
1378                 else
1379                         dpcd_set_lane_settings(link, lt_settings, offset);
1380
1381                 /* 3. wait for receiver to lock-on*/
1382                 wait_time_microsec = lt_settings->eq_pattern_time;
1383
1384                 if (is_repeater(link, offset))
1385                         wait_time_microsec =
1386                                         dp_translate_training_aux_read_interval(
1387                                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
1388
1389                 if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
1390                                 (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
1391                                 link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
1392                         wait_time_microsec = 16000;
1393                 }
1394
1395                 dp_wait_for_training_aux_rd_interval(
1396                                 link,
1397                                 wait_time_microsec);
1398
1399                 /* 4. Read lane status and requested
1400                  * drive settings as set by the sink*/
1401
1402                 dp_get_lane_status_and_lane_adjust(
1403                         link,
1404                         lt_settings,
1405                         dpcd_lane_status,
1406                         &dpcd_lane_status_updated,
1407                         dpcd_lane_adjust,
1408                         offset);
1409
1410                 /* 5. check CR done*/
1411                 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
1412                         return LINK_TRAINING_EQ_FAIL_CR;
1413
1414                 /* 6. check CHEQ done*/
1415                 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
1416                                 dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
1417                                 dp_is_interlane_aligned(dpcd_lane_status_updated))
1418                         return LINK_TRAINING_SUCCESS;
1419
1420                 /* 7. update VS/PE/PC2 in lt_settings*/
1421                 dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
1422                                 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
1423         }
1424
1425         return LINK_TRAINING_EQ_FAIL_EQ;
1426
1427 }
1428
1429 static void start_clock_recovery_pattern_early(struct dc_link *link,
1430                 struct link_training_settings *lt_settings,
1431                 uint32_t offset)
1432 {
1433         DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1434                         __func__);
1435         dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1436         dp_set_hw_lane_settings(link, lt_settings, offset);
1437         udelay(400);
1438 }
1439
1440 static enum link_training_result perform_clock_recovery_sequence(
1441         struct dc_link *link,
1442         struct link_training_settings *lt_settings,
1443         uint32_t offset)
1444 {
1445         uint32_t retries_cr;
1446         uint32_t retry_count;
1447         uint32_t wait_time_microsec;
1448         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1449         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1450         union lane_align_status_updated dpcd_lane_status_updated;
1451         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
1452
1453         retries_cr = 0;
1454         retry_count = 0;
1455
1456         if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1457                 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1458
1459         /* najeeb - The synaptics MST hub can put the LT in
1460         * infinite loop by switching the VS
1461         */
1462         /* between level 0 and level 1 continuously, here
1463         * we try for CR lock for LinkTrainingMaxCRRetry count*/
1464         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1465                 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1466
1467                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1468                 memset(&dpcd_lane_status_updated, '\0',
1469                 sizeof(dpcd_lane_status_updated));
1470
1471                 /* 1. call HWSS to set lane settings*/
1472                 dp_set_hw_lane_settings(
1473                                 link,
1474                                 lt_settings,
1475                                 offset);
1476
1477                 /* 2. update DPCD of the receiver*/
1478                 if (!retry_count)
1479                         /* EPR #361076 - write as a 5-byte burst,
1480                          * but only for the 1-st iteration.*/
1481                         dpcd_set_lt_pattern_and_lane_settings(
1482                                         link,
1483                                         lt_settings,
1484                                         lt_settings->pattern_for_cr,
1485                                         offset);
1486                 else
1487                         dpcd_set_lane_settings(
1488                                         link,
1489                                         lt_settings,
1490                                         offset);
1491
1492                 /* 3. wait receiver to lock-on*/
1493                 wait_time_microsec = lt_settings->cr_pattern_time;
1494
1495                 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1496                         wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1497
1498                 if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
1499                                 (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)) {
1500                         wait_time_microsec = 16000;
1501                 }
1502
1503                 dp_wait_for_training_aux_rd_interval(
1504                                 link,
1505                                 wait_time_microsec);
1506
1507                 /* 4. Read lane status and requested drive
1508                 * settings as set by the sink
1509                 */
1510                 dp_get_lane_status_and_lane_adjust(
1511                                 link,
1512                                 lt_settings,
1513                                 dpcd_lane_status,
1514                                 &dpcd_lane_status_updated,
1515                                 dpcd_lane_adjust,
1516                                 offset);
1517
1518                 if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
1519                                 (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
1520                                 link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
1521                         vendor_specific_lttpr_wa_one_end(link, retry_count);
1522                         vendor_specific_lttpr_wa_three(link, dpcd_lane_adjust);
1523                 }
1524
1525                 /* 5. check CR done*/
1526                 if (dp_is_cr_done(lane_count, dpcd_lane_status))
1527                         return LINK_TRAINING_SUCCESS;
1528
1529                 /* 6. max VS reached*/
1530 #if defined(CONFIG_DRM_AMD_DC_DCN)
1531                 if ((dp_get_link_encoding_format(&lt_settings->link_settings) ==
1532                                 DP_8b_10b_ENCODING) &&
1533                                 dp_is_max_vs_reached(lt_settings))
1534                         break;
1535 #else
1536                 if (dp_is_max_vs_reached(lt_settings))
1537                         break;
1538 #endif
1539
1540                 /* 7. same lane settings*/
1541                 /* Note: settings are the same for all lanes,
1542                  * so comparing first lane is sufficient*/
1543                 if ((dp_get_link_encoding_format(&lt_settings->link_settings) == DP_8b_10b_ENCODING) &&
1544                                 lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET ==
1545                                                 dpcd_lane_adjust[0].bits.VOLTAGE_SWING_LANE)
1546                         retries_cr++;
1547 #if defined(CONFIG_DRM_AMD_DC_DCN)
1548                 else if ((dp_get_link_encoding_format(&lt_settings->link_settings) == DP_128b_132b_ENCODING) &&
1549                                 lt_settings->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE ==
1550                                                 dpcd_lane_adjust[0].tx_ffe.PRESET_VALUE)
1551                         retries_cr++;
1552 #endif
1553                 else
1554                         retries_cr = 0;
1555
1556                 /* 8. update VS/PE/PC2 in lt_settings*/
1557                 dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
1558                                 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
1559                 retry_count++;
1560         }
1561
1562         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1563                 ASSERT(0);
1564                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1565                         __func__,
1566                         LINK_TRAINING_MAX_CR_RETRY);
1567
1568         }
1569
1570         return dp_get_cr_failure(lane_count, dpcd_lane_status);
1571 }
1572
1573 static inline enum link_training_result dp_transition_to_video_idle(
1574         struct dc_link *link,
1575         struct link_training_settings *lt_settings,
1576         enum link_training_result status)
1577 {
1578         union lane_count_set lane_count_set = {0};
1579
1580         /* 4. mainlink output idle pattern*/
1581         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1582
1583         /*
1584          * 5. post training adjust if required
1585          * If the upstream DPTX and downstream DPRX both support TPS4,
1586          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1587          */
1588         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1589 #if defined(CONFIG_DRM_AMD_DC_DCN)
1590                         lt_settings->pattern_for_eq >= DP_TRAINING_PATTERN_SEQUENCE_4) {
1591 #else
1592                         lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) {
1593 #endif
1594                 /* delay 5ms after Main Link output idle pattern and then check
1595                  * DPCD 0202h.
1596                  */
1597                 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1598                         msleep(5);
1599                         status = dp_check_link_loss_status(link, lt_settings);
1600                 }
1601                 return status;
1602         }
1603
1604         if (status == LINK_TRAINING_SUCCESS &&
1605                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1606                 status = LINK_TRAINING_LQA_FAIL;
1607
1608         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1609         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1610         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1611
1612         core_link_write_dpcd(
1613                 link,
1614                 DP_LANE_COUNT_SET,
1615                 &lane_count_set.raw,
1616                 sizeof(lane_count_set));
1617
1618         return status;
1619 }
1620
1621 enum link_training_result dp_check_link_loss_status(
1622         struct dc_link *link,
1623         const struct link_training_settings *link_training_setting)
1624 {
1625         enum link_training_result status = LINK_TRAINING_SUCCESS;
1626         union lane_status lane_status;
1627         uint8_t dpcd_buf[6] = {0};
1628         uint32_t lane;
1629
1630         core_link_read_dpcd(
1631                         link,
1632                         DP_SINK_COUNT,
1633                         (uint8_t *)(dpcd_buf),
1634                         sizeof(dpcd_buf));
1635
1636         /*parse lane status*/
1637         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1638                 /*
1639                  * check lanes status
1640                  */
1641                 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1642
1643                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1644                         !lane_status.bits.CR_DONE_0 ||
1645                         !lane_status.bits.SYMBOL_LOCKED_0) {
1646                         /* if one of the channel equalization, clock
1647                          * recovery or symbol lock is dropped
1648                          * consider it as (link has been
1649                          * dropped) dp sink status has changed
1650                          */
1651                         status = LINK_TRAINING_LINK_LOSS;
1652                         break;
1653                 }
1654         }
1655
1656         return status;
1657 }
1658
1659 static inline void decide_8b_10b_training_settings(
1660          struct dc_link *link,
1661         const struct dc_link_settings *link_setting,
1662         struct link_training_settings *lt_settings)
1663 {
1664         memset(lt_settings, '\0', sizeof(struct link_training_settings));
1665
1666         /* Initialize link settings */
1667         lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1668         lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1669         lt_settings->link_settings.link_rate = link_setting->link_rate;
1670         lt_settings->link_settings.lane_count = link_setting->lane_count;
1671         /* TODO hard coded to SS for now
1672          * lt_settings.link_settings.link_spread =
1673          * dal_display_path_is_ss_supported(
1674          * path_mode->display_path) ?
1675          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1676          * LINK_SPREAD_DISABLED;
1677          */
1678         lt_settings->link_settings.link_spread = link->dp_ss_off ?
1679                         LINK_SPREAD_DISABLED : LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1680         lt_settings->lttpr_mode = link->lttpr_mode;
1681         lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1682         lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1683         lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1684         lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1685         lt_settings->enhanced_framing = 1;
1686         lt_settings->should_set_fec_ready = true;
1687         lt_settings->disallow_per_lane_settings = true;
1688         lt_settings->always_match_dpcd_with_hw_lane_settings = true;
1689         dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
1690 }
1691
1692 #if defined(CONFIG_DRM_AMD_DC_DCN)
1693 static inline void decide_128b_132b_training_settings(struct dc_link *link,
1694                 const struct dc_link_settings *link_settings,
1695                 struct link_training_settings *lt_settings)
1696 {
1697         memset(lt_settings, 0, sizeof(*lt_settings));
1698
1699         lt_settings->link_settings = *link_settings;
1700         /* TODO: should decide link spread when populating link_settings */
1701         lt_settings->link_settings.link_spread = link->dp_ss_off ? LINK_SPREAD_DISABLED :
1702                         LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1703
1704         lt_settings->pattern_for_cr = decide_cr_training_pattern(link_settings);
1705         lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_settings);
1706         lt_settings->eq_pattern_time = 2500;
1707         lt_settings->eq_wait_time_limit = 400000;
1708         lt_settings->eq_loop_count_limit = 20;
1709         lt_settings->pattern_for_cds = DP_128b_132b_TPS2_CDS;
1710         lt_settings->cds_pattern_time = 2500;
1711         lt_settings->cds_wait_time_limit = (dp_convert_to_count(
1712                         link->dpcd_caps.lttpr_caps.phy_repeater_cnt) + 1) * 20000;
1713         lt_settings->lttpr_mode = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) ?
1714                         LTTPR_MODE_NON_TRANSPARENT : LTTPR_MODE_TRANSPARENT;
1715         lt_settings->disallow_per_lane_settings = true;
1716         dp_hw_to_dpcd_lane_settings(lt_settings,
1717                         lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
1718 }
1719 #endif
1720
1721 void dp_decide_training_settings(
1722                 struct dc_link *link,
1723                 const struct dc_link_settings *link_settings,
1724                 struct link_training_settings *lt_settings)
1725 {
1726         if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
1727                 decide_8b_10b_training_settings(link, link_settings, lt_settings);
1728 #if defined(CONFIG_DRM_AMD_DC_DCN)
1729         else if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING)
1730                 decide_128b_132b_training_settings(link, link_settings, lt_settings);
1731 #endif
1732 }
1733
1734 static void override_training_settings(
1735                 struct dc_link *link,
1736                 const struct dc_link_training_overrides *overrides,
1737                 struct link_training_settings *lt_settings)
1738 {
1739         uint32_t lane;
1740
1741         /* Override link spread */
1742         if (!link->dp_ss_off && overrides->downspread != NULL)
1743                 lt_settings->link_settings.link_spread = *overrides->downspread ?
1744                                 LINK_SPREAD_05_DOWNSPREAD_30KHZ
1745                                 : LINK_SPREAD_DISABLED;
1746
1747         /* Override lane settings */
1748         if (overrides->voltage_swing != NULL)
1749                 lt_settings->voltage_swing = overrides->voltage_swing;
1750         if (overrides->pre_emphasis != NULL)
1751                 lt_settings->pre_emphasis = overrides->pre_emphasis;
1752         if (overrides->post_cursor2 != NULL)
1753                 lt_settings->post_cursor2 = overrides->post_cursor2;
1754 #if defined(CONFIG_DRM_AMD_DC_DCN)
1755         if (overrides->ffe_preset != NULL)
1756                 lt_settings->ffe_preset = overrides->ffe_preset;
1757 #endif
1758         /* Override HW lane settings with BIOS forced values if present */
1759         if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN &&
1760                         link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
1761                 lt_settings->voltage_swing = &link->bios_forced_drive_settings.VOLTAGE_SWING;
1762                 lt_settings->pre_emphasis = &link->bios_forced_drive_settings.PRE_EMPHASIS;
1763                 lt_settings->always_match_dpcd_with_hw_lane_settings = false;
1764         }
1765         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1766                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1767                         lt_settings->voltage_swing != NULL ?
1768                         *lt_settings->voltage_swing :
1769                         VOLTAGE_SWING_LEVEL0;
1770                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1771                         lt_settings->pre_emphasis != NULL ?
1772                         *lt_settings->pre_emphasis
1773                         : PRE_EMPHASIS_DISABLED;
1774                 lt_settings->lane_settings[lane].POST_CURSOR2 =
1775                         lt_settings->post_cursor2 != NULL ?
1776                         *lt_settings->post_cursor2
1777                         : POST_CURSOR2_DISABLED;
1778         }
1779
1780         dp_hw_to_dpcd_lane_settings(lt_settings,
1781                         lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
1782
1783         /* Initialize training timings */
1784         if (overrides->cr_pattern_time != NULL)
1785                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1786
1787         if (overrides->eq_pattern_time != NULL)
1788                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1789
1790         if (overrides->pattern_for_cr != NULL)
1791                 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1792         if (overrides->pattern_for_eq != NULL)
1793                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1794
1795         if (overrides->enhanced_framing != NULL)
1796                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1797
1798         if (link->preferred_training_settings.fec_enable != NULL)
1799                 lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
1800 }
1801
1802 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
1803 {
1804         switch (lttpr_repeater_count) {
1805         case 0x80: // 1 lttpr repeater
1806                 return 1;
1807         case 0x40: // 2 lttpr repeaters
1808                 return 2;
1809         case 0x20: // 3 lttpr repeaters
1810                 return 3;
1811         case 0x10: // 4 lttpr repeaters
1812                 return 4;
1813         case 0x08: // 5 lttpr repeaters
1814                 return 5;
1815         case 0x04: // 6 lttpr repeaters
1816                 return 6;
1817         case 0x02: // 7 lttpr repeaters
1818                 return 7;
1819         case 0x01: // 8 lttpr repeaters
1820                 return 8;
1821         default:
1822                 break;
1823         }
1824         return 0; // invalid value
1825 }
1826
1827 static enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
1828 {
1829         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1830
1831         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1832         return core_link_write_dpcd(link,
1833                         DP_PHY_REPEATER_MODE,
1834                         (uint8_t *)&repeater_mode,
1835                         sizeof(repeater_mode));
1836 }
1837
1838 static enum dc_status configure_lttpr_mode_non_transparent(
1839                 struct dc_link *link,
1840                 const struct link_training_settings *lt_settings)
1841 {
1842         /* aux timeout is already set to extended */
1843         /* RESET/SET lttpr mode to enable non transparent mode */
1844         uint8_t repeater_cnt;
1845         uint32_t aux_interval_address;
1846         uint8_t repeater_id;
1847         enum dc_status result = DC_ERROR_UNEXPECTED;
1848         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1849
1850         enum dp_link_encoding encoding = dp_get_link_encoding_format(&lt_settings->link_settings);
1851
1852         if (encoding == DP_8b_10b_ENCODING) {
1853                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1854                 result = core_link_write_dpcd(link,
1855                                 DP_PHY_REPEATER_MODE,
1856                                 (uint8_t *)&repeater_mode,
1857                                 sizeof(repeater_mode));
1858
1859         }
1860
1861         if (result == DC_OK) {
1862                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1863         }
1864
1865         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1866
1867                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1868
1869                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1870                 result = core_link_write_dpcd(link,
1871                                 DP_PHY_REPEATER_MODE,
1872                                 (uint8_t *)&repeater_mode,
1873                                 sizeof(repeater_mode));
1874
1875                 if (result == DC_OK) {
1876                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1877                 }
1878
1879                 if (encoding == DP_8b_10b_ENCODING) {
1880                         repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1881
1882                         /* Driver does not need to train the first hop. Skip DPCD read and clear
1883                          * AUX_RD_INTERVAL for DPTX-to-DPIA hop.
1884                          */
1885                         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1886                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[--repeater_cnt] = 0;
1887
1888                         for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1889                                 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1890                                                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1891                                 core_link_read_dpcd(
1892                                         link,
1893                                         aux_interval_address,
1894                                         (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1895                                         sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1896                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1897                         }
1898                 }
1899         }
1900
1901         return result;
1902 }
1903
1904 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1905 {
1906         union dpcd_training_pattern dpcd_pattern = {0};
1907
1908         const uint32_t dpcd_base_lt_offset =
1909                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1910                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1911         /* Set training not in progress*/
1912         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1913
1914         core_link_write_dpcd(
1915                 link,
1916                 dpcd_base_lt_offset,
1917                 &dpcd_pattern.raw,
1918                 1);
1919
1920         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1921                 __func__,
1922                 offset,
1923                 dpcd_base_lt_offset,
1924                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1925 }
1926
1927 static void print_status_message(
1928         struct dc_link *link,
1929         const struct link_training_settings *lt_settings,
1930         enum link_training_result status)
1931 {
1932         char *link_rate = "Unknown";
1933         char *lt_result = "Unknown";
1934         char *lt_spread = "Disabled";
1935
1936         switch (lt_settings->link_settings.link_rate) {
1937         case LINK_RATE_LOW:
1938                 link_rate = "RBR";
1939                 break;
1940         case LINK_RATE_RATE_2:
1941                 link_rate = "R2";
1942                 break;
1943         case LINK_RATE_RATE_3:
1944                 link_rate = "R3";
1945                 break;
1946         case LINK_RATE_HIGH:
1947                 link_rate = "HBR";
1948                 break;
1949         case LINK_RATE_RBR2:
1950                 link_rate = "RBR2";
1951                 break;
1952         case LINK_RATE_RATE_6:
1953                 link_rate = "R6";
1954                 break;
1955         case LINK_RATE_HIGH2:
1956                 link_rate = "HBR2";
1957                 break;
1958         case LINK_RATE_HIGH3:
1959                 link_rate = "HBR3";
1960                 break;
1961 #if defined(CONFIG_DRM_AMD_DC_DCN)
1962         case LINK_RATE_UHBR10:
1963                 link_rate = "UHBR10";
1964                 break;
1965         case LINK_RATE_UHBR13_5:
1966                 link_rate = "UHBR13.5";
1967                 break;
1968         case LINK_RATE_UHBR20:
1969                 link_rate = "UHBR20";
1970                 break;
1971 #endif
1972         default:
1973                 break;
1974         }
1975
1976         switch (status) {
1977         case LINK_TRAINING_SUCCESS:
1978                 lt_result = "pass";
1979                 break;
1980         case LINK_TRAINING_CR_FAIL_LANE0:
1981                 lt_result = "CR failed lane0";
1982                 break;
1983         case LINK_TRAINING_CR_FAIL_LANE1:
1984                 lt_result = "CR failed lane1";
1985                 break;
1986         case LINK_TRAINING_CR_FAIL_LANE23:
1987                 lt_result = "CR failed lane23";
1988                 break;
1989         case LINK_TRAINING_EQ_FAIL_CR:
1990                 lt_result = "CR failed in EQ";
1991                 break;
1992         case LINK_TRAINING_EQ_FAIL_EQ:
1993                 lt_result = "EQ failed";
1994                 break;
1995         case LINK_TRAINING_LQA_FAIL:
1996                 lt_result = "LQA failed";
1997                 break;
1998         case LINK_TRAINING_LINK_LOSS:
1999                 lt_result = "Link loss";
2000                 break;
2001 #if defined(CONFIG_DRM_AMD_DC_DCN)
2002         case DP_128b_132b_LT_FAILED:
2003                 lt_result = "LT_FAILED received";
2004                 break;
2005         case DP_128b_132b_MAX_LOOP_COUNT_REACHED:
2006                 lt_result = "max loop count reached";
2007                 break;
2008         case DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT:
2009                 lt_result = "channel EQ timeout";
2010                 break;
2011         case DP_128b_132b_CDS_DONE_TIMEOUT:
2012                 lt_result = "CDS timeout";
2013                 break;
2014 #endif
2015         default:
2016                 break;
2017         }
2018
2019         switch (lt_settings->link_settings.link_spread) {
2020         case LINK_SPREAD_DISABLED:
2021                 lt_spread = "Disabled";
2022                 break;
2023         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
2024                 lt_spread = "0.5% 30KHz";
2025                 break;
2026         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
2027                 lt_spread = "0.5% 33KHz";
2028                 break;
2029         default:
2030                 break;
2031         }
2032
2033         /* Connectivity log: link training */
2034 #if defined(CONFIG_DRM_AMD_DC_DCN)
2035         /* TODO - DP2.0 Log: add connectivity log for FFE PRESET */
2036 #endif
2037         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
2038                                 link_rate,
2039                                 lt_settings->link_settings.lane_count,
2040                                 lt_result,
2041                                 lt_settings->lane_settings[0].VOLTAGE_SWING,
2042                                 lt_settings->lane_settings[0].PRE_EMPHASIS,
2043                                 lt_spread);
2044 }
2045
2046 void dc_link_dp_set_drive_settings(
2047         struct dc_link *link,
2048         struct link_training_settings *lt_settings)
2049 {
2050         /* program ASIC PHY settings*/
2051         dp_set_hw_lane_settings(link, lt_settings, DPRX);
2052
2053         dp_hw_to_dpcd_lane_settings(lt_settings,
2054                         lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
2055
2056         /* Notify DP sink the PHY settings from source */
2057         dpcd_set_lane_settings(link, lt_settings, DPRX);
2058 }
2059
2060 bool dc_link_dp_perform_link_training_skip_aux(
2061         struct dc_link *link,
2062         const struct dc_link_settings *link_setting)
2063 {
2064         struct link_training_settings lt_settings = {0};
2065
2066         dp_decide_training_settings(
2067                         link,
2068                         link_setting,
2069                         &lt_settings);
2070         override_training_settings(
2071                         link,
2072                         &link->preferred_training_settings,
2073                         &lt_settings);
2074
2075         /* 1. Perform_clock_recovery_sequence. */
2076
2077         /* transmit training pattern for clock recovery */
2078         dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
2079
2080         /* call HWSS to set lane settings*/
2081         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
2082
2083         /* wait receiver to lock-on*/
2084         dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
2085
2086         /* 2. Perform_channel_equalization_sequence. */
2087
2088         /* transmit training pattern for channel equalization. */
2089         dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
2090
2091         /* call HWSS to set lane settings*/
2092         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
2093
2094         /* wait receiver to lock-on. */
2095         dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
2096
2097         /* 3. Perform_link_training_int. */
2098
2099         /* Mainlink output idle pattern. */
2100         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
2101
2102         print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
2103
2104         return true;
2105 }
2106
2107 enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
2108 {
2109         enum dc_status status = DC_OK;
2110
2111         if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT)
2112                 status = configure_lttpr_mode_transparent(link);
2113
2114         else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
2115                 status = configure_lttpr_mode_non_transparent(link, lt_settings);
2116
2117         return status;
2118 }
2119
2120 static void dpcd_exit_training_mode(struct dc_link *link)
2121 {
2122 #if defined(CONFIG_DRM_AMD_DC_DCN)
2123         uint8_t sink_status = 0;
2124         uint8_t i;
2125 #endif
2126
2127         /* clear training pattern set */
2128         dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
2129
2130 #if defined(CONFIG_DRM_AMD_DC_DCN)
2131         /* poll for intra-hop disable */
2132         for (i = 0; i < 10; i++) {
2133                 if ((core_link_read_dpcd(link, DP_SINK_STATUS, &sink_status, 1) == DC_OK) &&
2134                                 (sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION) == 0)
2135                         break;
2136                 udelay(1000);
2137         }
2138 #endif
2139 }
2140
2141 enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
2142                 struct link_training_settings *lt_settings)
2143 {
2144         enum dp_link_encoding encoding =
2145                         dp_get_link_encoding_format(
2146                                         &lt_settings->link_settings);
2147         enum dc_status status;
2148
2149         status = core_link_write_dpcd(
2150                         link,
2151                         DP_MAIN_LINK_CHANNEL_CODING_SET,
2152                         (uint8_t *) &encoding,
2153                         1);
2154         DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
2155                                         __func__,
2156                                         DP_MAIN_LINK_CHANNEL_CODING_SET,
2157                                         encoding);
2158
2159         return status;
2160 }
2161
2162 #if defined(CONFIG_DRM_AMD_DC_DCN)
2163 static void dpcd_128b_132b_get_aux_rd_interval(struct dc_link *link,
2164                 uint32_t *interval_in_us)
2165 {
2166         union dp_128b_132b_training_aux_rd_interval dpcd_interval;
2167         uint32_t interval_unit = 0;
2168
2169         dpcd_interval.raw = 0;
2170         core_link_read_dpcd(link, DP_128b_132b_TRAINING_AUX_RD_INTERVAL,
2171                         &dpcd_interval.raw, sizeof(dpcd_interval.raw));
2172         interval_unit = dpcd_interval.bits.UNIT ? 1 : 2; /* 0b = 2 ms, 1b = 1 ms */
2173         /* (128b/132b_TRAINING_AUX_RD_INTERVAL value + 1) *
2174          * INTERVAL_UNIT. The maximum is 256 ms
2175          */
2176         *interval_in_us = (dpcd_interval.bits.VALUE + 1) * interval_unit * 1000;
2177 }
2178
2179 static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
2180                 struct dc_link *link,
2181                 struct link_training_settings *lt_settings)
2182 {
2183         uint8_t loop_count;
2184         uint32_t aux_rd_interval = 0;
2185         uint32_t wait_time = 0;
2186         union lane_align_status_updated dpcd_lane_status_updated = {0};
2187         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
2188         enum link_training_result status = LINK_TRAINING_SUCCESS;
2189         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
2190
2191         /* Transmit 128b/132b_TPS1 over Main-Link */
2192         dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, DPRX);
2193         /* Set TRAINING_PATTERN_SET to 01h */
2194         dpcd_set_training_pattern(link, lt_settings->pattern_for_cr);
2195
2196         /* Adjust TX_FFE_PRESET_VALUE and Transmit 128b/132b_TPS2 over Main-Link */
2197         dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval);
2198         dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
2199                         &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
2200         dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
2201                         lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
2202         dp_set_hw_lane_settings(link, lt_settings, DPRX);
2203         dp_set_hw_training_pattern(link, lt_settings->pattern_for_eq, DPRX);
2204
2205         /* Set loop counter to start from 1 */
2206         loop_count = 1;
2207
2208         /* Set TRAINING_PATTERN_SET to 02h and TX_FFE_PRESET_VALUE in one AUX transaction */
2209         dpcd_set_lt_pattern_and_lane_settings(link, lt_settings,
2210                         lt_settings->pattern_for_eq, DPRX);
2211
2212         /* poll for channel EQ done */
2213         while (status == LINK_TRAINING_SUCCESS) {
2214                 dp_wait_for_training_aux_rd_interval(link, aux_rd_interval);
2215                 wait_time += aux_rd_interval;
2216                 dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
2217                                 &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
2218                 dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
2219                         lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
2220                 dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval);
2221                 if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count,
2222                                 dpcd_lane_status)) {
2223                         /* pass */
2224                         break;
2225                 } else if (loop_count >= lt_settings->eq_loop_count_limit) {
2226                         status = DP_128b_132b_MAX_LOOP_COUNT_REACHED;
2227                 } else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
2228                         status = DP_128b_132b_LT_FAILED;
2229                 } else {
2230                         dp_set_hw_lane_settings(link, lt_settings, DPRX);
2231                         dpcd_set_lane_settings(link, lt_settings, DPRX);
2232                 }
2233                 loop_count++;
2234         }
2235
2236         /* poll for EQ interlane align done */
2237         while (status == LINK_TRAINING_SUCCESS) {
2238                 if (dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) {
2239                         /* pass */
2240                         break;
2241                 } else if (wait_time >= lt_settings->eq_wait_time_limit) {
2242                         status = DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT;
2243                 } else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
2244                         status = DP_128b_132b_LT_FAILED;
2245                 } else {
2246                         dp_wait_for_training_aux_rd_interval(link,
2247                                         lt_settings->eq_pattern_time);
2248                         wait_time += lt_settings->eq_pattern_time;
2249                         dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
2250                                         &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
2251                 }
2252         }
2253
2254         return status;
2255 }
2256
2257 static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
2258                 struct dc_link *link,
2259                 struct link_training_settings *lt_settings)
2260 {
2261         /* Assumption: assume hardware has transmitted eq pattern */
2262         enum link_training_result status = LINK_TRAINING_SUCCESS;
2263         union lane_align_status_updated dpcd_lane_status_updated = {0};
2264         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
2265         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
2266         uint32_t wait_time = 0;
2267
2268         /* initiate CDS done sequence */
2269         dpcd_set_training_pattern(link, lt_settings->pattern_for_cds);
2270
2271         /* poll for CDS interlane align done and symbol lock */
2272         while (status == LINK_TRAINING_SUCCESS) {
2273                 dp_wait_for_training_aux_rd_interval(link,
2274                                 lt_settings->cds_pattern_time);
2275                 wait_time += lt_settings->cds_pattern_time;
2276                 dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
2277                                                 &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
2278                 if (dp_is_symbol_locked(lt_settings->link_settings.lane_count, dpcd_lane_status) &&
2279                                 dpcd_lane_status_updated.bits.CDS_INTERLANE_ALIGN_DONE_128b_132b) {
2280                         /* pass */
2281                         break;
2282                 } else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
2283                         status = DP_128b_132b_LT_FAILED;
2284                 } else if (wait_time >= lt_settings->cds_wait_time_limit) {
2285                         status = DP_128b_132b_CDS_DONE_TIMEOUT;
2286                 }
2287         }
2288
2289         return status;
2290 }
2291 #endif
2292
2293 static enum link_training_result dp_perform_8b_10b_link_training(
2294                 struct dc_link *link,
2295                 struct link_training_settings *lt_settings)
2296 {
2297         enum link_training_result status = LINK_TRAINING_SUCCESS;
2298
2299         uint8_t repeater_cnt;
2300         uint8_t repeater_id;
2301         uint8_t lane = 0;
2302
2303         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
2304                 start_clock_recovery_pattern_early(link, lt_settings, DPRX);
2305
2306         /* 1. set link rate, lane count and spread. */
2307         dpcd_set_link_settings(link, lt_settings);
2308
2309         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
2310
2311                 /* 2. perform link training (set link training done
2312                  *  to false is done as well)
2313                  */
2314                 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
2315
2316                 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
2317                                 repeater_id--) {
2318                         status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);
2319
2320                         if (status != LINK_TRAINING_SUCCESS)
2321                                 break;
2322
2323                         status = perform_channel_equalization_sequence(link,
2324                                         lt_settings,
2325                                         repeater_id);
2326
2327                         if (status != LINK_TRAINING_SUCCESS)
2328                                 break;
2329
2330                         repeater_training_done(link, repeater_id);
2331                 }
2332
2333                 for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
2334                         lt_settings->dpcd_lane_settings[lane].raw = 0;
2335         }
2336
2337         if (status == LINK_TRAINING_SUCCESS) {
2338                 status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
2339         if (status == LINK_TRAINING_SUCCESS) {
2340                 status = perform_channel_equalization_sequence(link,
2341                                         lt_settings,
2342                                         DPRX);
2343                 }
2344         }
2345
2346         return status;
2347 }
2348
2349 #if defined(CONFIG_DRM_AMD_DC_DCN)
2350 static enum link_training_result dp_perform_128b_132b_link_training(
2351                 struct dc_link *link,
2352                 struct link_training_settings *lt_settings)
2353 {
2354         enum link_training_result result = LINK_TRAINING_SUCCESS;
2355
2356         /* TODO - DP2.0 Link: remove legacy_dp2_lt logic */
2357         if (link->dc->debug.legacy_dp2_lt) {
2358                 struct link_training_settings legacy_settings;
2359
2360                 decide_8b_10b_training_settings(link,
2361                                 &lt_settings->link_settings,
2362                                 &legacy_settings);
2363                 return dp_perform_8b_10b_link_training(link, &legacy_settings);
2364         }
2365
2366         dpcd_set_link_settings(link, lt_settings);
2367
2368         if (result == LINK_TRAINING_SUCCESS)
2369                 result = dp_perform_128b_132b_channel_eq_done_sequence(link, lt_settings);
2370
2371         if (result == LINK_TRAINING_SUCCESS)
2372                 result = dp_perform_128b_132b_cds_done_sequence(link, lt_settings);
2373
2374         return result;
2375 }
2376 #endif
2377
2378 enum link_training_result dc_link_dp_perform_link_training(
2379         struct dc_link *link,
2380         const struct dc_link_settings *link_settings,
2381         bool skip_video_pattern)
2382 {
2383         enum link_training_result status = LINK_TRAINING_SUCCESS;
2384         struct link_training_settings lt_settings = {0};
2385         enum dp_link_encoding encoding =
2386                         dp_get_link_encoding_format(link_settings);
2387
2388         /* decide training settings */
2389         dp_decide_training_settings(
2390                         link,
2391                         link_settings,
2392                         &lt_settings);
2393         override_training_settings(
2394                         link,
2395                         &link->preferred_training_settings,
2396                         &lt_settings);
2397
2398         /* reset previous training states */
2399         if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
2400                         (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
2401                         link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
2402                 link->apply_vendor_specific_lttpr_link_rate_wa = true;
2403                 vendor_specific_lttpr_wa_four(link, true);
2404         } else {
2405                 dpcd_exit_training_mode(link);
2406         }
2407
2408         /* configure link prior to entering training mode */
2409         dpcd_configure_lttpr_mode(link, &lt_settings);
2410         dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
2411         dpcd_configure_channel_coding(link, &lt_settings);
2412
2413         /* enter training mode:
2414          * Per DP specs starting from here, DPTX device shall not issue
2415          * Non-LT AUX transactions inside training mode.
2416          */
2417         if (encoding == DP_8b_10b_ENCODING)
2418                 status = dp_perform_8b_10b_link_training(link, &lt_settings);
2419 #if defined(CONFIG_DRM_AMD_DC_DCN)
2420         else if (encoding == DP_128b_132b_ENCODING)
2421                 status = dp_perform_128b_132b_link_training(link, &lt_settings);
2422 #endif
2423         else
2424                 ASSERT(0);
2425
2426         /* exit training mode */
2427         if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
2428                         (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
2429                         link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
2430                 link->apply_vendor_specific_lttpr_link_rate_wa = false;
2431                 vendor_specific_lttpr_wa_four(link, (status != LINK_TRAINING_SUCCESS));
2432         } else {
2433                 dpcd_exit_training_mode(link);
2434         }
2435
2436         /* switch to video idle */
2437         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
2438                 status = dp_transition_to_video_idle(link,
2439                                 &lt_settings,
2440                                 status);
2441
2442         /* dump debug data */
2443         print_status_message(link, &lt_settings, status);
2444         if (status != LINK_TRAINING_SUCCESS)
2445                 link->ctx->dc->debug_data.ltFailCount++;
2446         return status;
2447 }
2448
2449 bool perform_link_training_with_retries(
2450         const struct dc_link_settings *link_setting,
2451         bool skip_video_pattern,
2452         int attempts,
2453         struct pipe_ctx *pipe_ctx,
2454         enum signal_type signal,
2455         bool do_fallback)
2456 {
2457         int j;
2458         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
2459         struct dc_stream_state *stream = pipe_ctx->stream;
2460         struct dc_link *link = stream->link;
2461         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
2462         struct link_encoder *link_enc;
2463         enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
2464         struct dc_link_settings current_setting = *link_setting;
2465
2466         /* Dynamically assigned link encoders associated with stream rather than
2467          * link.
2468          */
2469         if (link->is_dig_mapping_flexible && link->dc->res_pool->funcs->link_encs_assign)
2470                 link_enc = link_enc_cfg_get_link_enc_used_by_stream(link->ctx->dc, pipe_ctx->stream);
2471         else
2472                 link_enc = link->link_enc;
2473
2474         /* We need to do this before the link training to ensure the idle pattern in SST
2475          * mode will be sent right after the link training
2476          */
2477         if (dp_get_link_encoding_format(&current_setting) == DP_8b_10b_ENCODING) {
2478                 link_enc->funcs->connect_dig_be_to_fe(link_enc,
2479                                                         pipe_ctx->stream_res.stream_enc->id, true);
2480                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE);
2481         }
2482
2483         for (j = 0; j < attempts; ++j) {
2484
2485                 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
2486                         __func__, (unsigned int)j + 1, attempts);
2487
2488                 dp_enable_link_phy(
2489                         link,
2490                         signal,
2491                         pipe_ctx->clock_source->id,
2492                         &current_setting);
2493
2494                 if (stream->sink_patches.dppowerup_delay > 0) {
2495                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
2496
2497                         msleep(delay_dp_power_up_in_ms);
2498                 }
2499
2500 #ifdef CONFIG_DRM_AMD_DC_HDCP
2501                 if (panel_mode == DP_PANEL_MODE_EDP) {
2502                         struct cp_psp *cp_psp = &stream->ctx->cp_psp;
2503
2504                         if (cp_psp && cp_psp->funcs.enable_assr)
2505                                 /* ASSR is bound to fail with unsigned PSP
2506                                  * verstage used during devlopment phase.
2507                                  * Report and continue with eDP panel mode to
2508                                  * perform eDP link training with right settings
2509                                  */
2510                                 cp_psp->funcs.enable_assr(cp_psp->handle, link);
2511                 }
2512 #endif
2513
2514                 dp_set_panel_mode(link, panel_mode);
2515
2516                 if (link->aux_access_disabled) {
2517                         dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
2518                         return true;
2519                 } else {
2520                         /** @todo Consolidate USB4 DP and DPx.x training. */
2521                         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
2522                                 status = dc_link_dpia_perform_link_training(link,
2523                                                                             &current_setting,
2524                                                                             skip_video_pattern);
2525
2526                                 /* Transmit idle pattern once training successful. */
2527                                 if (status == LINK_TRAINING_SUCCESS)
2528                                         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE,
2529                                                                NULL, 0);
2530                         } else {
2531                                 status = dc_link_dp_perform_link_training(link,
2532                                                                           &current_setting,
2533                                                                           skip_video_pattern);
2534                         }
2535
2536                         if (status == LINK_TRAINING_SUCCESS)
2537                                 return true;
2538                 }
2539
2540                 /* latest link training still fail, skip delay and keep PHY on
2541                  */
2542                 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
2543                         break;
2544
2545                 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
2546                         __func__, (unsigned int)j + 1, attempts);
2547
2548                 dp_disable_link_phy(link, signal);
2549
2550                 /* Abort link training if failure due to sink being unplugged. */
2551                 if (status == LINK_TRAINING_ABORT) {
2552                         enum dc_connection_type type = dc_connection_none;
2553
2554                         dc_link_detect_sink(link, &type);
2555                         if (type == dc_connection_none)
2556                                 break;
2557                 } else if (do_fallback) {
2558                         uint32_t req_bw;
2559                         uint32_t link_bw;
2560
2561                         decide_fallback_link_setting(*link_setting, &current_setting, status);
2562                         /* Fail link training if reduced link bandwidth no longer meets
2563                          * stream requirements.
2564                          */
2565                         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2566                         link_bw = dc_link_bandwidth_kbps(link, &current_setting);
2567                         if (req_bw > link_bw)
2568                                 break;
2569                 }
2570
2571                 msleep(delay_between_attempts);
2572
2573                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
2574         }
2575
2576         return false;
2577 }
2578
2579 static enum clock_source_id get_clock_source_id(struct dc_link *link)
2580 {
2581         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
2582         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
2583
2584         if (dp_cs != NULL) {
2585                 dp_cs_id = dp_cs->id;
2586         } else {
2587                 /*
2588                  * dp clock source is not initialized for some reason.
2589                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
2590                  */
2591                 ASSERT(dp_cs);
2592         }
2593
2594         return dp_cs_id;
2595 }
2596
2597 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
2598 {
2599         if (mst_enable == false &&
2600                 link->type == dc_connection_mst_branch) {
2601                 /* Disable MST on link. Use only local sink. */
2602                 dp_disable_link_phy_mst(link, link->connector_signal);
2603
2604                 link->type = dc_connection_single;
2605                 link->local_sink = link->remote_sinks[0];
2606                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
2607                 dc_sink_retain(link->local_sink);
2608                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
2609         } else if (mst_enable == true &&
2610                         link->type == dc_connection_single &&
2611                         link->remote_sinks[0] != NULL) {
2612                 /* Re-enable MST on link. */
2613                 dp_disable_link_phy(link, link->connector_signal);
2614                 dp_enable_mst_on_sink(link, true);
2615
2616                 link->type = dc_connection_mst_branch;
2617                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
2618         }
2619 }
2620
2621 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
2622 {
2623         /* Begin Sync LT. During this time,
2624          * DPCD:600h must not be powered down.
2625          */
2626         link->sync_lt_in_progress = true;
2627
2628         /*Clear any existing preferred settings.*/
2629         memset(&link->preferred_training_settings, 0,
2630                 sizeof(struct dc_link_training_overrides));
2631         memset(&link->preferred_link_setting, 0,
2632                 sizeof(struct dc_link_settings));
2633
2634         return true;
2635 }
2636
2637 enum link_training_result dc_link_dp_sync_lt_attempt(
2638     struct dc_link *link,
2639     struct dc_link_settings *link_settings,
2640     struct dc_link_training_overrides *lt_overrides)
2641 {
2642         struct link_training_settings lt_settings = {0};
2643         enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
2644         enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
2645         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2646         bool fec_enable = false;
2647
2648         dp_decide_training_settings(
2649                         link,
2650                         link_settings,
2651                         &lt_settings);
2652         override_training_settings(
2653                         link,
2654                         lt_overrides,
2655                         &lt_settings);
2656         /* Setup MST Mode */
2657         if (lt_overrides->mst_enable)
2658                 set_dp_mst_mode(link, *lt_overrides->mst_enable);
2659
2660         /* Disable link */
2661         dp_disable_link_phy(link, link->connector_signal);
2662
2663         /* Enable link */
2664         dp_cs_id = get_clock_source_id(link);
2665         dp_enable_link_phy(link, link->connector_signal,
2666                 dp_cs_id, link_settings);
2667
2668         /* Set FEC enable */
2669 #if defined(CONFIG_DRM_AMD_DC_DCN)
2670         if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
2671 #endif
2672                 fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
2673                 dp_set_fec_ready(link, fec_enable);
2674 #if defined(CONFIG_DRM_AMD_DC_DCN)
2675         }
2676 #endif
2677
2678         if (lt_overrides->alternate_scrambler_reset) {
2679                 if (*lt_overrides->alternate_scrambler_reset)
2680                         panel_mode = DP_PANEL_MODE_EDP;
2681                 else
2682                         panel_mode = DP_PANEL_MODE_DEFAULT;
2683         } else
2684                 panel_mode = dp_get_panel_mode(link);
2685
2686         dp_set_panel_mode(link, panel_mode);
2687
2688         /* Attempt to train with given link training settings */
2689         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
2690                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
2691
2692         /* Set link rate, lane count and spread. */
2693         dpcd_set_link_settings(link, &lt_settings);
2694
2695         /* 2. perform link training (set link training done
2696          *  to false is done as well)
2697          */
2698         lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
2699         if (lt_status == LINK_TRAINING_SUCCESS) {
2700                 lt_status = perform_channel_equalization_sequence(link,
2701                                                 &lt_settings,
2702                                                 DPRX);
2703         }
2704
2705         /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
2706         /* 4. print status message*/
2707         print_status_message(link, &lt_settings, lt_status);
2708
2709         return lt_status;
2710 }
2711
2712 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
2713 {
2714         /* If input parameter is set, shut down phy.
2715          * Still shouldn't turn off dp_receiver (DPCD:600h)
2716          */
2717         if (link_down == true) {
2718 #if defined(CONFIG_DRM_AMD_DC_DCN)
2719                 struct dc_link_settings link_settings = link->cur_link_settings;
2720 #endif
2721                 dp_disable_link_phy(link, link->connector_signal);
2722 #if defined(CONFIG_DRM_AMD_DC_DCN)
2723                 if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING)
2724 #endif
2725                         dp_set_fec_ready(link, false);
2726         }
2727
2728         link->sync_lt_in_progress = false;
2729         return true;
2730 }
2731
2732 #if defined(CONFIG_DRM_AMD_DC_DCN)
2733 static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link)
2734 {
2735         enum dc_link_rate lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
2736
2737         if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20)
2738                 lttpr_max_link_rate = LINK_RATE_UHBR20;
2739         else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
2740                 lttpr_max_link_rate = LINK_RATE_UHBR13_5;
2741         else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR10)
2742                 lttpr_max_link_rate = LINK_RATE_UHBR10;
2743
2744         return lttpr_max_link_rate;
2745 }
2746 #endif
2747
2748 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2749 {
2750         struct link_encoder *link_enc = NULL;
2751
2752         if (!max_link_enc_cap) {
2753                 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2754                 return false;
2755         }
2756
2757         /* Links supporting dynamically assigned link encoder will be assigned next
2758          * available encoder if one not already assigned.
2759          */
2760         if (link->is_dig_mapping_flexible &&
2761                         link->dc->res_pool->funcs->link_encs_assign) {
2762                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
2763                 if (link_enc == NULL)
2764                         link_enc = link_enc_cfg_get_next_avail_link_enc(link->ctx->dc);
2765         } else
2766                 link_enc = link->link_enc;
2767         ASSERT(link_enc);
2768
2769         if (link_enc && link_enc->funcs->get_max_link_cap) {
2770                 link_enc->funcs->get_max_link_cap(link_enc, max_link_enc_cap);
2771                 return true;
2772         }
2773
2774         DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2775         max_link_enc_cap->lane_count = 1;
2776         max_link_enc_cap->link_rate = 6;
2777         return false;
2778 }
2779
2780 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
2781 {
2782         struct dc_link_settings max_link_cap = {0};
2783 #if defined(CONFIG_DRM_AMD_DC_DCN)
2784         enum dc_link_rate lttpr_max_link_rate;
2785 #endif
2786         struct link_encoder *link_enc = NULL;
2787
2788         /* Links supporting dynamically assigned link encoder will be assigned next
2789          * available encoder if one not already assigned.
2790          */
2791         if (link->is_dig_mapping_flexible &&
2792                         link->dc->res_pool->funcs->link_encs_assign) {
2793                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
2794                 if (link_enc == NULL)
2795                         link_enc = link_enc_cfg_get_next_avail_link_enc(link->ctx->dc);
2796         } else
2797                 link_enc = link->link_enc;
2798         ASSERT(link_enc);
2799
2800         /* get max link encoder capability */
2801         if (link_enc)
2802                 link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap);
2803 #if defined(CONFIG_DRM_AMD_DC_DCN)
2804         if (max_link_cap.link_rate >= LINK_RATE_UHBR10 &&
2805                         !link->hpo_dp_link_enc)
2806                 max_link_cap.link_rate = LINK_RATE_HIGH3;
2807 #endif
2808
2809         /* Lower link settings based on sink's link cap */
2810         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2811                 max_link_cap.lane_count =
2812                                 link->reported_link_cap.lane_count;
2813         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2814                 max_link_cap.link_rate =
2815                                 link->reported_link_cap.link_rate;
2816         if (link->reported_link_cap.link_spread <
2817                         max_link_cap.link_spread)
2818                 max_link_cap.link_spread =
2819                                 link->reported_link_cap.link_spread;
2820         /*
2821          * account for lttpr repeaters cap
2822          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2823          */
2824         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
2825                 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2826                         max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2827
2828 #if defined(CONFIG_DRM_AMD_DC_DCN)
2829                 lttpr_max_link_rate = get_lttpr_max_link_rate(link);
2830
2831                 if (lttpr_max_link_rate < max_link_cap.link_rate)
2832                         max_link_cap.link_rate = lttpr_max_link_rate;
2833 #else
2834                 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
2835                         max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
2836 #endif
2837
2838                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
2839                                                 __func__,
2840                                                 max_link_cap.lane_count,
2841                                                 max_link_cap.link_rate);
2842         }
2843         return max_link_cap;
2844 }
2845
2846 static enum dc_status read_hpd_rx_irq_data(
2847         struct dc_link *link,
2848         union hpd_irq_data *irq_data)
2849 {
2850         static enum dc_status retval;
2851
2852         /* The HW reads 16 bytes from 200h on HPD,
2853          * but if we get an AUX_DEFER, the HW cannot retry
2854          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
2855          * fail, so we now explicitly read 6 bytes which is
2856          * the req from the above mentioned test cases.
2857          *
2858          * For DP 1.4 we need to read those from 2002h range.
2859          */
2860         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
2861                 retval = core_link_read_dpcd(
2862                         link,
2863                         DP_SINK_COUNT,
2864                         irq_data->raw,
2865                         sizeof(union hpd_irq_data));
2866         else {
2867                 /* Read 14 bytes in a single read and then copy only the required fields.
2868                  * This is more efficient than doing it in two separate AUX reads. */
2869
2870                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
2871
2872                 retval = core_link_read_dpcd(
2873                         link,
2874                         DP_SINK_COUNT_ESI,
2875                         tmp,
2876                         sizeof(tmp));
2877
2878                 if (retval != DC_OK)
2879                         return retval;
2880
2881                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
2882                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
2883                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
2884                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
2885                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
2886                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
2887         }
2888
2889         return retval;
2890 }
2891
2892 bool hpd_rx_irq_check_link_loss_status(
2893         struct dc_link *link,
2894         union hpd_irq_data *hpd_irq_dpcd_data)
2895 {
2896         uint8_t irq_reg_rx_power_state = 0;
2897         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2898         union lane_status lane_status;
2899         uint32_t lane;
2900         bool sink_status_changed;
2901         bool return_code;
2902
2903         sink_status_changed = false;
2904         return_code = false;
2905
2906         if (link->cur_link_settings.lane_count == 0)
2907                 return return_code;
2908
2909         /*1. Check that Link Status changed, before re-training.*/
2910
2911         /*parse lane status*/
2912         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2913                 /* check status of lanes 0,1
2914                  * changed DpcdAddress_Lane01Status (0x202)
2915                  */
2916                 lane_status.raw = get_nibble_at_index(
2917                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2918                         lane);
2919
2920                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2921                         !lane_status.bits.CR_DONE_0 ||
2922                         !lane_status.bits.SYMBOL_LOCKED_0) {
2923                         /* if one of the channel equalization, clock
2924                          * recovery or symbol lock is dropped
2925                          * consider it as (link has been
2926                          * dropped) dp sink status has changed
2927                          */
2928                         sink_status_changed = true;
2929                         break;
2930                 }
2931         }
2932
2933         /* Check interlane align.*/
2934         if (sink_status_changed ||
2935                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2936
2937                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2938
2939                 return_code = true;
2940
2941                 /*2. Check that we can handle interrupt: Not in FS DOS,
2942                  *  Not in "Display Timeout" state, Link is trained.
2943                  */
2944                 dpcd_result = core_link_read_dpcd(link,
2945                         DP_SET_POWER,
2946                         &irq_reg_rx_power_state,
2947                         sizeof(irq_reg_rx_power_state));
2948
2949                 if (dpcd_result != DC_OK) {
2950                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2951                                 __func__);
2952                 } else {
2953                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2954                                 return_code = false;
2955                 }
2956         }
2957
2958         return return_code;
2959 }
2960
2961 bool dp_verify_link_cap(
2962         struct dc_link *link,
2963         struct dc_link_settings *known_limit_link_setting,
2964         int *fail_count)
2965 {
2966         struct dc_link_settings max_link_cap = {0};
2967         struct dc_link_settings cur_link_setting = {0};
2968         struct dc_link_settings *cur = &cur_link_setting;
2969         struct dc_link_settings initial_link_settings = {0};
2970         bool success;
2971         bool skip_link_training;
2972         bool skip_video_pattern;
2973         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2974         enum link_training_result status;
2975         union hpd_irq_data irq_data;
2976
2977         /* link training starts with the maximum common settings
2978          * supported by both sink and ASIC.
2979          */
2980         max_link_cap = get_max_link_cap(link);
2981         initial_link_settings = get_common_supported_link_settings(
2982                         *known_limit_link_setting,
2983                         max_link_cap);
2984
2985         /* Accept reported capabilities if link supports flexible encoder mapping or encoder already in use. */
2986         if (link->dc->debug.skip_detection_link_training ||
2987                         link->is_dig_mapping_flexible) {
2988                 /* TODO - should we check link encoder's max link caps here?
2989                  * How do we know which link encoder to check from?
2990                  */
2991                 link->verified_link_cap = *known_limit_link_setting;
2992                 return true;
2993         } else if (link->link_enc && link->dc->res_pool->funcs->link_encs_assign &&
2994                         !link_enc_cfg_is_link_enc_avail(link->ctx->dc, link->link_enc->preferred_engine, link)) {
2995                 link->verified_link_cap = initial_link_settings;
2996                 return true;
2997         }
2998
2999         memset(&irq_data, 0, sizeof(irq_data));
3000         success = false;
3001         skip_link_training = false;
3002
3003         /* Grant extended timeout request */
3004         if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
3005                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
3006
3007                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
3008         }
3009
3010 #if defined(CONFIG_DRM_AMD_DC_DCN)
3011         if (dp_get_link_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING)
3012                 reset_dp_hpo_stream_encoders_for_link(link);
3013 #endif
3014         /* TODO implement override and monitor patch later */
3015
3016         /* try to train the link from high to low to
3017          * find the physical link capability
3018          */
3019         /* disable PHY done possible by BIOS, will be done by driver itself */
3020         dp_disable_link_phy(link, link->connector_signal);
3021
3022         dp_cs_id = get_clock_source_id(link);
3023
3024         cur_link_setting = initial_link_settings;
3025
3026         /* Temporary Renoir-specific workaround for SWDEV-215184;
3027          * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
3028          * so add extra cycle of enabling and disabling the PHY before first link training.
3029          */
3030         if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C &&
3031                         link->dc->debug.usbc_combo_phy_reset_wa) {
3032                 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
3033                 dp_disable_link_phy(link, link->connector_signal);
3034         }
3035
3036         do {
3037                 skip_video_pattern = true;
3038
3039                 if (cur->link_rate == LINK_RATE_LOW)
3040                         skip_video_pattern = false;
3041
3042                 dp_enable_link_phy(
3043                                 link,
3044                                 link->connector_signal,
3045                                 dp_cs_id,
3046                                 cur);
3047
3048
3049                 if (skip_link_training)
3050                         success = true;
3051                 else {
3052                         status = dc_link_dp_perform_link_training(
3053                                                         link,
3054                                                         cur,
3055                                                         skip_video_pattern);
3056                         if (status == LINK_TRAINING_SUCCESS)
3057                                 success = true;
3058                         else
3059                                 (*fail_count)++;
3060                 }
3061
3062                 if (success) {
3063                         link->verified_link_cap = *cur;
3064                         udelay(1000);
3065                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
3066                                 if (hpd_rx_irq_check_link_loss_status(
3067                                                 link,
3068                                                 &irq_data))
3069                                         (*fail_count)++;
3070                 }
3071                 /* always disable the link before trying another
3072                  * setting or before returning we'll enable it later
3073                  * based on the actual mode we're driving
3074                  */
3075                 dp_disable_link_phy(link, link->connector_signal);
3076         } while (!success && decide_fallback_link_setting(
3077                         initial_link_settings, cur, status));
3078
3079         /* Link Training failed for all Link Settings
3080          *  (Lane Count is still unknown)
3081          */
3082         if (!success) {
3083                 /* If all LT fails for all settings,
3084                  * set verified = failed safe (1 lane low)
3085                  */
3086                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
3087                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
3088
3089                 link->verified_link_cap.link_spread =
3090                 LINK_SPREAD_DISABLED;
3091         }
3092
3093
3094         return success;
3095 }
3096
3097 bool dp_verify_link_cap_with_retries(
3098         struct dc_link *link,
3099         struct dc_link_settings *known_limit_link_setting,
3100         int attempts)
3101 {
3102         int i = 0;
3103         bool success = false;
3104
3105         for (i = 0; i < attempts; i++) {
3106                 int fail_count = 0;
3107                 enum dc_connection_type type = dc_connection_none;
3108
3109                 memset(&link->verified_link_cap, 0,
3110                                 sizeof(struct dc_link_settings));
3111                 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
3112                         link->verified_link_cap.lane_count = LANE_COUNT_ONE;
3113                         link->verified_link_cap.link_rate = LINK_RATE_LOW;
3114                         link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
3115                         break;
3116                 } else if (dp_verify_link_cap(link,
3117                                 known_limit_link_setting,
3118                                 &fail_count) && fail_count == 0) {
3119                         success = true;
3120                         break;
3121                 }
3122                 msleep(10);
3123         }
3124         return success;
3125 }
3126
3127 bool dp_verify_mst_link_cap(
3128         struct dc_link *link)
3129 {
3130         struct dc_link_settings max_link_cap = {0};
3131
3132         if (dp_get_link_encoding_format(&link->reported_link_cap) ==
3133                         DP_8b_10b_ENCODING) {
3134                 max_link_cap = get_max_link_cap(link);
3135                 link->verified_link_cap = get_common_supported_link_settings(
3136                                 link->reported_link_cap,
3137                                 max_link_cap);
3138         }
3139 #if defined(CONFIG_DRM_AMD_DC_DCN)
3140         else if (dp_get_link_encoding_format(&link->reported_link_cap) ==
3141                         DP_128b_132b_ENCODING) {
3142                 dp_verify_link_cap_with_retries(link,
3143                                 &link->reported_link_cap,
3144                                 LINK_TRAINING_MAX_VERIFY_RETRY);
3145         }
3146 #endif
3147         return true;
3148 }
3149
3150 static struct dc_link_settings get_common_supported_link_settings(
3151                 struct dc_link_settings link_setting_a,
3152                 struct dc_link_settings link_setting_b)
3153 {
3154         struct dc_link_settings link_settings = {0};
3155
3156         link_settings.lane_count =
3157                 (link_setting_a.lane_count <=
3158                         link_setting_b.lane_count) ?
3159                         link_setting_a.lane_count :
3160                         link_setting_b.lane_count;
3161         link_settings.link_rate =
3162                 (link_setting_a.link_rate <=
3163                         link_setting_b.link_rate) ?
3164                         link_setting_a.link_rate :
3165                         link_setting_b.link_rate;
3166         link_settings.link_spread = LINK_SPREAD_DISABLED;
3167
3168         /* in DP compliance test, DPR-120 may have
3169          * a random value in its MAX_LINK_BW dpcd field.
3170          * We map it to the maximum supported link rate that
3171          * is smaller than MAX_LINK_BW in this case.
3172          */
3173 #if defined(CONFIG_DRM_AMD_DC_DCN)
3174         if (link_settings.link_rate > LINK_RATE_UHBR20) {
3175                 link_settings.link_rate = LINK_RATE_UHBR20;
3176         } else if (link_settings.link_rate < LINK_RATE_UHBR20 &&
3177                         link_settings.link_rate > LINK_RATE_UHBR13_5) {
3178                 link_settings.link_rate = LINK_RATE_UHBR13_5;
3179         } else if (link_settings.link_rate < LINK_RATE_UHBR10 &&
3180                         link_settings.link_rate > LINK_RATE_HIGH3) {
3181 #else
3182         if (link_settings.link_rate > LINK_RATE_HIGH3) {
3183 #endif
3184                 link_settings.link_rate = LINK_RATE_HIGH3;
3185         } else if (link_settings.link_rate < LINK_RATE_HIGH3
3186                         && link_settings.link_rate > LINK_RATE_HIGH2) {
3187                 link_settings.link_rate = LINK_RATE_HIGH2;
3188         } else if (link_settings.link_rate < LINK_RATE_HIGH2
3189                         && link_settings.link_rate > LINK_RATE_HIGH) {
3190                 link_settings.link_rate = LINK_RATE_HIGH;
3191         } else if (link_settings.link_rate < LINK_RATE_HIGH
3192                         && link_settings.link_rate > LINK_RATE_LOW) {
3193                 link_settings.link_rate = LINK_RATE_LOW;
3194         } else if (link_settings.link_rate < LINK_RATE_LOW) {
3195                 link_settings.link_rate = LINK_RATE_UNKNOWN;
3196         }
3197
3198         return link_settings;
3199 }
3200
3201 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
3202 {
3203         return lane_count <= LANE_COUNT_ONE;
3204 }
3205
3206 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
3207 {
3208         return link_rate <= LINK_RATE_LOW;
3209 }
3210
3211 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
3212 {
3213         switch (lane_count) {
3214         case LANE_COUNT_FOUR:
3215                 return LANE_COUNT_TWO;
3216         case LANE_COUNT_TWO:
3217                 return LANE_COUNT_ONE;
3218         case LANE_COUNT_ONE:
3219                 return LANE_COUNT_UNKNOWN;
3220         default:
3221                 return LANE_COUNT_UNKNOWN;
3222         }
3223 }
3224
3225 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
3226 {
3227         switch (link_rate) {
3228 #if defined(CONFIG_DRM_AMD_DC_DCN)
3229         case LINK_RATE_UHBR20:
3230                 return LINK_RATE_UHBR13_5;
3231         case LINK_RATE_UHBR13_5:
3232                 return LINK_RATE_UHBR10;
3233         case LINK_RATE_UHBR10:
3234                 return LINK_RATE_HIGH3;
3235 #endif
3236         case LINK_RATE_HIGH3:
3237                 return LINK_RATE_HIGH2;
3238         case LINK_RATE_HIGH2:
3239                 return LINK_RATE_HIGH;
3240         case LINK_RATE_HIGH:
3241                 return LINK_RATE_LOW;
3242         case LINK_RATE_LOW:
3243                 return LINK_RATE_UNKNOWN;
3244         default:
3245                 return LINK_RATE_UNKNOWN;
3246         }
3247 }
3248
3249 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
3250 {
3251         switch (lane_count) {
3252         case LANE_COUNT_ONE:
3253                 return LANE_COUNT_TWO;
3254         case LANE_COUNT_TWO:
3255                 return LANE_COUNT_FOUR;
3256         default:
3257                 return LANE_COUNT_UNKNOWN;
3258         }
3259 }
3260
3261 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
3262 {
3263         switch (link_rate) {
3264         case LINK_RATE_LOW:
3265                 return LINK_RATE_HIGH;
3266         case LINK_RATE_HIGH:
3267                 return LINK_RATE_HIGH2;
3268         case LINK_RATE_HIGH2:
3269                 return LINK_RATE_HIGH3;
3270 #if defined(CONFIG_DRM_AMD_DC_DCN)
3271         case LINK_RATE_HIGH3:
3272                 return LINK_RATE_UHBR10;
3273         case LINK_RATE_UHBR10:
3274                 return LINK_RATE_UHBR13_5;
3275         case LINK_RATE_UHBR13_5:
3276                 return LINK_RATE_UHBR20;
3277 #endif
3278         default:
3279                 return LINK_RATE_UNKNOWN;
3280         }
3281 }
3282
3283 #if defined(CONFIG_DRM_AMD_DC_DCN)
3284 static bool decide_fallback_link_setting_max_bw_policy(
3285                 const struct dc_link_settings *max,
3286                 struct dc_link_settings *cur)
3287 {
3288         uint8_t cur_idx = 0, next_idx;
3289         bool found = false;
3290
3291         while (cur_idx < ARRAY_SIZE(dp_lt_fallbacks))
3292                 /* find current index */
3293                 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count &&
3294                                 dp_lt_fallbacks[cur_idx].link_rate == cur->link_rate)
3295                         break;
3296                 else
3297                         cur_idx++;
3298
3299         next_idx = cur_idx + 1;
3300
3301         while (next_idx < ARRAY_SIZE(dp_lt_fallbacks))
3302                 /* find next index */
3303                 if (dp_lt_fallbacks[next_idx].lane_count <= max->lane_count &&
3304                                 dp_lt_fallbacks[next_idx].link_rate <= max->link_rate)
3305                         break;
3306                 else
3307                         next_idx++;
3308
3309         if (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) {
3310                 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count;
3311                 cur->link_rate = dp_lt_fallbacks[next_idx].link_rate;
3312                 found = true;
3313         }
3314
3315         return found;
3316 }
3317 #endif
3318
3319 /*
3320  * function: set link rate and lane count fallback based
3321  * on current link setting and last link training result
3322  * return value:
3323  *                      true - link setting could be set
3324  *                      false - has reached minimum setting
3325  *                                      and no further fallback could be done
3326  */
3327 static bool decide_fallback_link_setting(
3328                 struct dc_link_settings initial_link_settings,
3329                 struct dc_link_settings *current_link_setting,
3330                 enum link_training_result training_result)
3331 {
3332         if (!current_link_setting)
3333                 return false;
3334 #if defined(CONFIG_DRM_AMD_DC_DCN)
3335         if (dp_get_link_encoding_format(&initial_link_settings) == DP_128b_132b_ENCODING)
3336                 return decide_fallback_link_setting_max_bw_policy(&initial_link_settings,
3337                                 current_link_setting);
3338 #endif
3339
3340         switch (training_result) {
3341         case LINK_TRAINING_CR_FAIL_LANE0:
3342         case LINK_TRAINING_CR_FAIL_LANE1:
3343         case LINK_TRAINING_CR_FAIL_LANE23:
3344         case LINK_TRAINING_LQA_FAIL:
3345         {
3346                 if (!reached_minimum_link_rate
3347                                 (current_link_setting->link_rate)) {
3348                         current_link_setting->link_rate =
3349                                 reduce_link_rate(
3350                                         current_link_setting->link_rate);
3351                 } else if (!reached_minimum_lane_count
3352                                 (current_link_setting->lane_count)) {
3353                         current_link_setting->link_rate =
3354                                 initial_link_settings.link_rate;
3355                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
3356                                 return false;
3357                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
3358                                 current_link_setting->lane_count =
3359                                                 LANE_COUNT_ONE;
3360                         else if (training_result ==
3361                                         LINK_TRAINING_CR_FAIL_LANE23)
3362                                 current_link_setting->lane_count =
3363                                                 LANE_COUNT_TWO;
3364                         else
3365                                 current_link_setting->lane_count =
3366                                         reduce_lane_count(
3367                                         current_link_setting->lane_count);
3368                 } else {
3369                         return false;
3370                 }
3371                 break;
3372         }
3373         case LINK_TRAINING_EQ_FAIL_EQ:
3374         {
3375                 if (!reached_minimum_lane_count
3376                                 (current_link_setting->lane_count)) {
3377                         current_link_setting->lane_count =
3378                                 reduce_lane_count(
3379                                         current_link_setting->lane_count);
3380                 } else if (!reached_minimum_link_rate
3381                                 (current_link_setting->link_rate)) {
3382                         current_link_setting->link_rate =
3383                                 reduce_link_rate(
3384                                         current_link_setting->link_rate);
3385                 } else {
3386                         return false;
3387                 }
3388                 break;
3389         }
3390         case LINK_TRAINING_EQ_FAIL_CR:
3391         {
3392                 if (!reached_minimum_link_rate
3393                                 (current_link_setting->link_rate)) {
3394                         current_link_setting->link_rate =
3395                                 reduce_link_rate(
3396                                         current_link_setting->link_rate);
3397                 } else {
3398                         return false;
3399                 }
3400                 break;
3401         }
3402         default:
3403                 return false;
3404         }
3405         return true;
3406 }
3407
3408 bool dp_validate_mode_timing(
3409         struct dc_link *link,
3410         const struct dc_crtc_timing *timing)
3411 {
3412         uint32_t req_bw;
3413         uint32_t max_bw;
3414
3415         const struct dc_link_settings *link_setting;
3416
3417         /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
3418         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
3419                         !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
3420                         dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
3421                 return false;
3422
3423         /*always DP fail safe mode*/
3424         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
3425                 timing->h_addressable == (uint32_t) 640 &&
3426                 timing->v_addressable == (uint32_t) 480)
3427                 return true;
3428
3429         link_setting = dc_link_get_link_cap(link);
3430
3431         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
3432         /*if (flags.DYNAMIC_VALIDATION == 1 &&
3433                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
3434                 link_setting = &link->verified_link_cap;
3435         */
3436
3437         req_bw = dc_bandwidth_in_kbps_from_timing(timing);
3438         max_bw = dc_link_bandwidth_kbps(link, link_setting);
3439
3440         if (req_bw <= max_bw) {
3441                 /* remember the biggest mode here, during
3442                  * initial link training (to get
3443                  * verified_link_cap), LS sends event about
3444                  * cannot train at reported cap to upper
3445                  * layer and upper layer will re-enumerate modes.
3446                  * this is not necessary if the lower
3447                  * verified_link_cap is enough to drive
3448                  * all the modes */
3449
3450                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
3451                 /* if (flags.DYNAMIC_VALIDATION == 1)
3452                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
3453                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
3454                 return true;
3455         } else
3456                 return false;
3457 }
3458
3459 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
3460 {
3461         struct dc_link_settings initial_link_setting = {
3462                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
3463         struct dc_link_settings current_link_setting =
3464                         initial_link_setting;
3465         uint32_t link_bw;
3466
3467         if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
3468                 return false;
3469
3470         /* search for the minimum link setting that:
3471          * 1. is supported according to the link training result
3472          * 2. could support the b/w requested by the timing
3473          */
3474         while (current_link_setting.link_rate <=
3475                         link->verified_link_cap.link_rate) {
3476                 link_bw = dc_link_bandwidth_kbps(
3477                                 link,
3478                                 &current_link_setting);
3479                 if (req_bw <= link_bw) {
3480                         *link_setting = current_link_setting;
3481                         return true;
3482                 }
3483
3484                 if (current_link_setting.lane_count <
3485                                 link->verified_link_cap.lane_count) {
3486                         current_link_setting.lane_count =
3487                                         increase_lane_count(
3488                                                         current_link_setting.lane_count);
3489                 } else {
3490                         current_link_setting.link_rate =
3491                                         increase_link_rate(
3492                                                         current_link_setting.link_rate);
3493                         current_link_setting.lane_count =
3494                                         initial_link_setting.lane_count;
3495                 }
3496         }
3497
3498         return false;
3499 }
3500
3501 bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
3502 {
3503         struct dc_link_settings initial_link_setting;
3504         struct dc_link_settings current_link_setting;
3505         uint32_t link_bw;
3506
3507         /*
3508          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
3509          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
3510          */
3511         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
3512                         link->dpcd_caps.edp_supported_link_rates_count == 0) {
3513                 *link_setting = link->verified_link_cap;
3514                 return true;
3515         }
3516
3517         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
3518         initial_link_setting.lane_count = LANE_COUNT_ONE;
3519         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
3520         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
3521         initial_link_setting.use_link_rate_set = true;
3522         initial_link_setting.link_rate_set = 0;
3523         current_link_setting = initial_link_setting;
3524
3525         /* search for the minimum link setting that:
3526          * 1. is supported according to the link training result
3527          * 2. could support the b/w requested by the timing
3528          */
3529         while (current_link_setting.link_rate <=
3530                         link->verified_link_cap.link_rate) {
3531                 link_bw = dc_link_bandwidth_kbps(
3532                                 link,
3533                                 &current_link_setting);
3534                 if (req_bw <= link_bw) {
3535                         *link_setting = current_link_setting;
3536                         return true;
3537                 }
3538
3539                 if (current_link_setting.lane_count <
3540                                 link->verified_link_cap.lane_count) {
3541                         current_link_setting.lane_count =
3542                                         increase_lane_count(
3543                                                         current_link_setting.lane_count);
3544                 } else {
3545                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
3546                                 current_link_setting.link_rate_set++;
3547                                 current_link_setting.link_rate =
3548                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
3549                                 current_link_setting.lane_count =
3550                                                                         initial_link_setting.lane_count;
3551                         } else
3552                                 break;
3553                 }
3554         }
3555         return false;
3556 }
3557
3558 static bool decide_edp_link_settings_with_dsc(struct dc_link *link,
3559                 struct dc_link_settings *link_setting,
3560                 uint32_t req_bw,
3561                 enum dc_link_rate max_link_rate)
3562 {
3563         struct dc_link_settings initial_link_setting;
3564         struct dc_link_settings current_link_setting;
3565         uint32_t link_bw;
3566
3567         unsigned int policy = 0;
3568
3569         policy = link->ctx->dc->debug.force_dsc_edp_policy;
3570         if (max_link_rate == LINK_RATE_UNKNOWN)
3571                 max_link_rate = link->verified_link_cap.link_rate;
3572         /*
3573          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
3574          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
3575          */
3576         if ((link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
3577                         link->dpcd_caps.edp_supported_link_rates_count == 0)) {
3578                 /* for DSC enabled case, we search for minimum lane count */
3579                 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
3580                 initial_link_setting.lane_count = LANE_COUNT_ONE;
3581                 initial_link_setting.link_rate = LINK_RATE_LOW;
3582                 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
3583                 initial_link_setting.use_link_rate_set = false;
3584                 initial_link_setting.link_rate_set = 0;
3585                 current_link_setting = initial_link_setting;
3586                 if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
3587                         return false;
3588
3589                 /* search for the minimum link setting that:
3590                  * 1. is supported according to the link training result
3591                  * 2. could support the b/w requested by the timing
3592                  */
3593                 while (current_link_setting.link_rate <=
3594                                 max_link_rate) {
3595                         link_bw = dc_link_bandwidth_kbps(
3596                                         link,
3597                                         &current_link_setting);
3598                         if (req_bw <= link_bw) {
3599                                 *link_setting = current_link_setting;
3600                                 return true;
3601                         }
3602                         if (policy) {
3603                                 /* minimize lane */
3604                                 if (current_link_setting.link_rate < max_link_rate) {
3605                                         current_link_setting.link_rate =
3606                                                         increase_link_rate(
3607                                                                         current_link_setting.link_rate);
3608                                 } else {
3609                                         if (current_link_setting.lane_count <
3610                                                                         link->verified_link_cap.lane_count) {
3611                                                 current_link_setting.lane_count =
3612                                                                 increase_lane_count(
3613                                                                                 current_link_setting.lane_count);
3614                                                 current_link_setting.link_rate = initial_link_setting.link_rate;
3615                                         } else
3616                                                 break;
3617                                 }
3618                         } else {
3619                                 /* minimize link rate */
3620                                 if (current_link_setting.lane_count <
3621                                                 link->verified_link_cap.lane_count) {
3622                                         current_link_setting.lane_count =
3623                                                         increase_lane_count(
3624                                                                         current_link_setting.lane_count);
3625                                 } else {
3626                                         current_link_setting.link_rate =
3627                                                         increase_link_rate(
3628                                                                         current_link_setting.link_rate);
3629                                         current_link_setting.lane_count =
3630                                                         initial_link_setting.lane_count;
3631                                 }
3632                         }
3633                 }
3634                 return false;
3635         }
3636
3637         /* if optimize edp link is supported */
3638         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
3639         initial_link_setting.lane_count = LANE_COUNT_ONE;
3640         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
3641         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
3642         initial_link_setting.use_link_rate_set = true;
3643         initial_link_setting.link_rate_set = 0;
3644         current_link_setting = initial_link_setting;
3645
3646         /* search for the minimum link setting that:
3647          * 1. is supported according to the link training result
3648          * 2. could support the b/w requested by the timing
3649          */
3650         while (current_link_setting.link_rate <=
3651                         max_link_rate) {
3652                 link_bw = dc_link_bandwidth_kbps(
3653                                 link,
3654                                 &current_link_setting);
3655                 if (req_bw <= link_bw) {
3656                         *link_setting = current_link_setting;
3657                         return true;
3658                 }
3659                 if (policy) {
3660                         /* minimize lane */
3661                         if (current_link_setting.link_rate_set <
3662                                         link->dpcd_caps.edp_supported_link_rates_count
3663                                         && current_link_setting.link_rate < max_link_rate) {
3664                                 current_link_setting.link_rate_set++;
3665                                 current_link_setting.link_rate =
3666                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
3667                         } else {
3668                                 if (current_link_setting.lane_count < link->verified_link_cap.lane_count) {
3669                                         current_link_setting.lane_count =
3670                                                         increase_lane_count(
3671                                                                         current_link_setting.lane_count);
3672                                         current_link_setting.link_rate_set = initial_link_setting.link_rate_set;
3673                                         current_link_setting.link_rate =
3674                                                 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
3675                                 } else
3676                                         break;
3677                         }
3678                 } else {
3679                         /* minimize link rate */
3680                         if (current_link_setting.lane_count <
3681                                         link->verified_link_cap.lane_count) {
3682                                 current_link_setting.lane_count =
3683                                                 increase_lane_count(
3684                                                                 current_link_setting.lane_count);
3685                         } else {
3686                                 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
3687                                         current_link_setting.link_rate_set++;
3688                                         current_link_setting.link_rate =
3689                                                 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
3690                                         current_link_setting.lane_count =
3691                                                 initial_link_setting.lane_count;
3692                                 } else
3693                                         break;
3694                         }
3695                 }
3696         }
3697         return false;
3698 }
3699
3700 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
3701 {
3702         *link_setting = link->verified_link_cap;
3703         return true;
3704 }
3705
3706 void decide_link_settings(struct dc_stream_state *stream,
3707         struct dc_link_settings *link_setting)
3708 {
3709         struct dc_link *link;
3710         uint32_t req_bw;
3711
3712         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
3713
3714         link = stream->link;
3715
3716         /* if preferred is specified through AMDDP, use it, if it's enough
3717          * to drive the mode
3718          */
3719         if (link->preferred_link_setting.lane_count !=
3720                         LANE_COUNT_UNKNOWN &&
3721                         link->preferred_link_setting.link_rate !=
3722                                         LINK_RATE_UNKNOWN) {
3723                 *link_setting =  link->preferred_link_setting;
3724                 return;
3725         }
3726
3727         /* MST doesn't perform link training for now
3728          * TODO: add MST specific link training routine
3729          */
3730         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3731                 if (decide_mst_link_settings(link, link_setting))
3732                         return;
3733         } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
3734                 /* enable edp link optimization for DSC eDP case */
3735                 if (stream->timing.flags.DSC) {
3736                         enum dc_link_rate max_link_rate = LINK_RATE_UNKNOWN;
3737
3738                         if (link->ctx->dc->debug.force_dsc_edp_policy) {
3739                                 /* calculate link max link rate cap*/
3740                                 struct dc_link_settings tmp_link_setting;
3741                                 struct dc_crtc_timing tmp_timing = stream->timing;
3742                                 uint32_t orig_req_bw;
3743
3744                                 tmp_link_setting.link_rate = LINK_RATE_UNKNOWN;
3745                                 tmp_timing.flags.DSC = 0;
3746                                 orig_req_bw = dc_bandwidth_in_kbps_from_timing(&tmp_timing);
3747                                 decide_edp_link_settings(link, &tmp_link_setting, orig_req_bw);
3748                                 max_link_rate = tmp_link_setting.link_rate;
3749                         }
3750                         if (decide_edp_link_settings_with_dsc(link, link_setting, req_bw, max_link_rate))
3751                                 return;
3752                 } else if (decide_edp_link_settings(link, link_setting, req_bw))
3753                         return;
3754         } else if (decide_dp_link_settings(link, link_setting, req_bw))
3755                 return;
3756
3757         BREAK_TO_DEBUGGER();
3758         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
3759
3760         *link_setting = link->verified_link_cap;
3761 }
3762
3763 /*************************Short Pulse IRQ***************************/
3764 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link)
3765 {
3766         /*
3767          * Don't handle RX IRQ unless one of following is met:
3768          * 1) The link is established (cur_link_settings != unknown)
3769          * 2) We know we're dealing with a branch device, SST or MST
3770          */
3771
3772         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
3773                 is_dp_branch_device(link))
3774                 return true;
3775
3776         return false;
3777 }
3778
3779 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
3780 {
3781         union dpcd_psr_configuration psr_configuration;
3782
3783         if (!link->psr_settings.psr_feature_enabled)
3784                 return false;
3785
3786         dm_helpers_dp_read_dpcd(
3787                 link->ctx,
3788                 link,
3789                 368,/*DpcdAddress_PSR_Enable_Cfg*/
3790                 &psr_configuration.raw,
3791                 sizeof(psr_configuration.raw));
3792
3793
3794         if (psr_configuration.bits.ENABLE) {
3795                 unsigned char dpcdbuf[3] = {0};
3796                 union psr_error_status psr_error_status;
3797                 union psr_sink_psr_status psr_sink_psr_status;
3798
3799                 dm_helpers_dp_read_dpcd(
3800                         link->ctx,
3801                         link,
3802                         0x2006, /*DpcdAddress_PSR_Error_Status*/
3803                         (unsigned char *) dpcdbuf,
3804                         sizeof(dpcdbuf));
3805
3806                 /*DPCD 2006h   ERROR STATUS*/
3807                 psr_error_status.raw = dpcdbuf[0];
3808                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
3809                 psr_sink_psr_status.raw = dpcdbuf[2];
3810
3811                 if (psr_error_status.bits.LINK_CRC_ERROR ||
3812                                 psr_error_status.bits.RFB_STORAGE_ERROR ||
3813                                 psr_error_status.bits.VSC_SDP_ERROR) {
3814                         bool allow_active;
3815
3816                         /* Acknowledge and clear error bits */
3817                         dm_helpers_dp_write_dpcd(
3818                                 link->ctx,
3819                                 link,
3820                                 8198,/*DpcdAddress_PSR_Error_Status*/
3821                                 &psr_error_status.raw,
3822                                 sizeof(psr_error_status.raw));
3823
3824                         /* PSR error, disable and re-enable PSR */
3825                         allow_active = false;
3826                         dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL);
3827                         allow_active = true;
3828                         dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL);
3829
3830                         return true;
3831                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
3832                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
3833                         /* No error is detect, PSR is active.
3834                          * We should return with IRQ_HPD handled without
3835                          * checking for loss of sync since PSR would have
3836                          * powered down main link.
3837                          */
3838                         return true;
3839                 }
3840         }
3841         return false;
3842 }
3843
3844 static void dp_test_send_link_training(struct dc_link *link)
3845 {
3846         struct dc_link_settings link_settings = {0};
3847
3848         core_link_read_dpcd(
3849                         link,
3850                         DP_TEST_LANE_COUNT,
3851                         (unsigned char *)(&link_settings.lane_count),
3852                         1);
3853         core_link_read_dpcd(
3854                         link,
3855                         DP_TEST_LINK_RATE,
3856                         (unsigned char *)(&link_settings.link_rate),
3857                         1);
3858
3859         /* Set preferred link settings */
3860         link->verified_link_cap.lane_count = link_settings.lane_count;
3861         link->verified_link_cap.link_rate = link_settings.link_rate;
3862
3863         dp_retrain_link_dp_test(link, &link_settings, false);
3864 }
3865
3866 /* TODO Raven hbr2 compliance eye output is unstable
3867  * (toggling on and off) with debugger break
3868  * This caueses intermittent PHY automation failure
3869  * Need to look into the root cause */
3870 static void dp_test_send_phy_test_pattern(struct dc_link *link)
3871 {
3872         union phy_test_pattern dpcd_test_pattern;
3873         union lane_adjust dpcd_lane_adjustment[2];
3874         unsigned char dpcd_post_cursor_2_adjustment = 0;
3875 #if defined(CONFIG_DRM_AMD_DC_DCN)
3876         unsigned char test_pattern_buffer[
3877                         (DP_TEST_264BIT_CUSTOM_PATTERN_263_256 -
3878                         DP_TEST_264BIT_CUSTOM_PATTERN_7_0)+1] = {0};
3879 #else
3880         unsigned char test_pattern_buffer[
3881                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
3882                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
3883 #endif
3884         unsigned int test_pattern_size = 0;
3885         enum dp_test_pattern test_pattern;
3886         union lane_adjust dpcd_lane_adjust;
3887         unsigned int lane;
3888         struct link_training_settings link_training_settings;
3889
3890         dpcd_test_pattern.raw = 0;
3891         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
3892         memset(&link_training_settings, 0, sizeof(link_training_settings));
3893
3894         /* get phy test pattern and pattern parameters from DP receiver */
3895         core_link_read_dpcd(
3896                         link,
3897                         DP_PHY_TEST_PATTERN,
3898                         &dpcd_test_pattern.raw,
3899                         sizeof(dpcd_test_pattern));
3900         core_link_read_dpcd(
3901                         link,
3902                         DP_ADJUST_REQUEST_LANE0_1,
3903                         &dpcd_lane_adjustment[0].raw,
3904                         sizeof(dpcd_lane_adjustment));
3905
3906         /*get post cursor 2 parameters
3907          * For DP 1.1a or eariler, this DPCD register's value is 0
3908          * For DP 1.2 or later:
3909          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
3910          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
3911          */
3912         core_link_read_dpcd(
3913                         link,
3914                         DP_ADJUST_REQUEST_POST_CURSOR2,
3915                         &dpcd_post_cursor_2_adjustment,
3916                         sizeof(dpcd_post_cursor_2_adjustment));
3917
3918         /* translate request */
3919         switch (dpcd_test_pattern.bits.PATTERN) {
3920         case PHY_TEST_PATTERN_D10_2:
3921                 test_pattern = DP_TEST_PATTERN_D102;
3922                 break;
3923         case PHY_TEST_PATTERN_SYMBOL_ERROR:
3924                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
3925                 break;
3926         case PHY_TEST_PATTERN_PRBS7:
3927                 test_pattern = DP_TEST_PATTERN_PRBS7;
3928                 break;
3929         case PHY_TEST_PATTERN_80BIT_CUSTOM:
3930                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
3931                 break;
3932         case PHY_TEST_PATTERN_CP2520_1:
3933                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
3934                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
3935                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
3936                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
3937                 break;
3938         case PHY_TEST_PATTERN_CP2520_2:
3939                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
3940                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
3941                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
3942                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
3943                 break;
3944         case PHY_TEST_PATTERN_CP2520_3:
3945                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
3946                 break;
3947 #if defined(CONFIG_DRM_AMD_DC_DCN)
3948         case PHY_TEST_PATTERN_128b_132b_TPS1:
3949                 test_pattern = DP_TEST_PATTERN_128b_132b_TPS1;
3950                 break;
3951         case PHY_TEST_PATTERN_128b_132b_TPS2:
3952                 test_pattern = DP_TEST_PATTERN_128b_132b_TPS2;
3953                 break;
3954         case PHY_TEST_PATTERN_PRBS9:
3955                 test_pattern = DP_TEST_PATTERN_PRBS9;
3956                 break;
3957         case PHY_TEST_PATTERN_PRBS11:
3958                 test_pattern = DP_TEST_PATTERN_PRBS11;
3959                 break;
3960         case PHY_TEST_PATTERN_PRBS15:
3961                 test_pattern = DP_TEST_PATTERN_PRBS15;
3962                 break;
3963         case PHY_TEST_PATTERN_PRBS23:
3964                 test_pattern = DP_TEST_PATTERN_PRBS23;
3965                 break;
3966         case PHY_TEST_PATTERN_PRBS31:
3967                 test_pattern = DP_TEST_PATTERN_PRBS31;
3968                 break;
3969         case PHY_TEST_PATTERN_264BIT_CUSTOM:
3970                 test_pattern = DP_TEST_PATTERN_264BIT_CUSTOM;
3971                 break;
3972         case PHY_TEST_PATTERN_SQUARE_PULSE:
3973                 test_pattern = DP_TEST_PATTERN_SQUARE_PULSE;
3974                 break;
3975 #endif
3976         default:
3977                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
3978         break;
3979         }
3980
3981         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
3982                 test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
3983                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1;
3984                 core_link_read_dpcd(
3985                                 link,
3986                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
3987                                 test_pattern_buffer,
3988                                 test_pattern_size);
3989         }
3990
3991 #if defined(CONFIG_DRM_AMD_DC_DCN)
3992         if (test_pattern == DP_TEST_PATTERN_SQUARE_PULSE) {
3993                 test_pattern_size = 1; // Square pattern data is 1 byte (DP spec)
3994                 core_link_read_dpcd(
3995                                 link,
3996                                 DP_PHY_SQUARE_PATTERN,
3997                                 test_pattern_buffer,
3998                                 test_pattern_size);
3999         }
4000
4001         if (test_pattern == DP_TEST_PATTERN_264BIT_CUSTOM) {
4002                 test_pattern_size = (DP_TEST_264BIT_CUSTOM_PATTERN_263_256-
4003                                 DP_TEST_264BIT_CUSTOM_PATTERN_7_0) + 1;
4004                 core_link_read_dpcd(
4005                                 link,
4006                                 DP_TEST_264BIT_CUSTOM_PATTERN_7_0,
4007                                 test_pattern_buffer,
4008                                 test_pattern_size);
4009         }
4010 #endif
4011
4012         /* prepare link training settings */
4013         link_training_settings.link_settings = link->cur_link_settings;
4014
4015         for (lane = 0; lane <
4016                 (unsigned int)(link->cur_link_settings.lane_count);
4017                 lane++) {
4018                 dpcd_lane_adjust.raw =
4019                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
4020                 if (dp_get_link_encoding_format(&link->cur_link_settings) ==
4021                                 DP_8b_10b_ENCODING) {
4022                         link_training_settings.hw_lane_settings[lane].VOLTAGE_SWING =
4023                                 (enum dc_voltage_swing)
4024                                 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
4025                         link_training_settings.hw_lane_settings[lane].PRE_EMPHASIS =
4026                                 (enum dc_pre_emphasis)
4027                                 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
4028                         link_training_settings.hw_lane_settings[lane].POST_CURSOR2 =
4029                                 (enum dc_post_cursor2)
4030                                 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
4031                 }
4032 #if defined(CONFIG_DRM_AMD_DC_DCN)
4033                 else if (dp_get_link_encoding_format(&link->cur_link_settings) ==
4034                                 DP_128b_132b_ENCODING) {
4035                         link_training_settings.hw_lane_settings[lane].FFE_PRESET.raw =
4036                                         dpcd_lane_adjust.tx_ffe.PRESET_VALUE;
4037                 }
4038 #endif
4039         }
4040
4041         dp_hw_to_dpcd_lane_settings(&link_training_settings,
4042                         link_training_settings.hw_lane_settings,
4043                         link_training_settings.dpcd_lane_settings);
4044         /*Usage: Measure DP physical lane signal
4045          * by DP SI test equipment automatically.
4046          * PHY test pattern request is generated by equipment via HPD interrupt.
4047          * HPD needs to be active all the time. HPD should be active
4048          * all the time. Do not touch it.
4049          * forward request to DS
4050          */
4051         dc_link_dp_set_test_pattern(
4052                 link,
4053                 test_pattern,
4054                 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
4055                 &link_training_settings,
4056                 test_pattern_buffer,
4057                 test_pattern_size);
4058 }
4059
4060 static void dp_test_send_link_test_pattern(struct dc_link *link)
4061 {
4062         union link_test_pattern dpcd_test_pattern;
4063         union test_misc dpcd_test_params;
4064         enum dp_test_pattern test_pattern;
4065         enum dp_test_pattern_color_space test_pattern_color_space =
4066                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
4067         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
4068         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4069         struct pipe_ctx *pipe_ctx = NULL;
4070         int i;
4071
4072         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
4073         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
4074
4075         for (i = 0; i < MAX_PIPES; i++) {
4076                 if (pipes[i].stream == NULL)
4077                         continue;
4078
4079                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4080                         pipe_ctx = &pipes[i];
4081                         break;
4082                 }
4083         }
4084
4085         if (pipe_ctx == NULL)
4086                 return;
4087
4088         /* get link test pattern and pattern parameters */
4089         core_link_read_dpcd(
4090                         link,
4091                         DP_TEST_PATTERN,
4092                         &dpcd_test_pattern.raw,
4093                         sizeof(dpcd_test_pattern));
4094         core_link_read_dpcd(
4095                         link,
4096                         DP_TEST_MISC0,
4097                         &dpcd_test_params.raw,
4098                         sizeof(dpcd_test_params));
4099
4100         switch (dpcd_test_pattern.bits.PATTERN) {
4101         case LINK_TEST_PATTERN_COLOR_RAMP:
4102                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
4103         break;
4104         case LINK_TEST_PATTERN_VERTICAL_BARS:
4105                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
4106         break; /* black and white */
4107         case LINK_TEST_PATTERN_COLOR_SQUARES:
4108                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
4109                                 TEST_DYN_RANGE_VESA ?
4110                                 DP_TEST_PATTERN_COLOR_SQUARES :
4111                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
4112         break;
4113         default:
4114                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
4115         break;
4116         }
4117
4118         if (dpcd_test_params.bits.CLR_FORMAT == 0)
4119                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
4120         else
4121                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
4122                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
4123                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
4124
4125         switch (dpcd_test_params.bits.BPC) {
4126         case 0: // 6 bits
4127                 requestColorDepth = COLOR_DEPTH_666;
4128                 break;
4129         case 1: // 8 bits
4130                 requestColorDepth = COLOR_DEPTH_888;
4131                 break;
4132         case 2: // 10 bits
4133                 requestColorDepth = COLOR_DEPTH_101010;
4134                 break;
4135         case 3: // 12 bits
4136                 requestColorDepth = COLOR_DEPTH_121212;
4137                 break;
4138         default:
4139                 break;
4140         }
4141
4142         switch (dpcd_test_params.bits.CLR_FORMAT) {
4143         case 0:
4144                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
4145                 break;
4146         case 1:
4147                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
4148                 break;
4149         case 2:
4150                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
4151                 break;
4152         default:
4153                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
4154                 break;
4155         }
4156
4157
4158         if (requestColorDepth != COLOR_DEPTH_UNDEFINED
4159                         && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
4160                 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
4161                                 __func__,
4162                                 pipe_ctx->stream->timing.display_color_depth,
4163                                 requestColorDepth);
4164                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
4165         }
4166
4167         dp_update_dsc_config(pipe_ctx);
4168
4169         dc_link_dp_set_test_pattern(
4170                         link,
4171                         test_pattern,
4172                         test_pattern_color_space,
4173                         NULL,
4174                         NULL,
4175                         0);
4176 }
4177
4178 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
4179 {
4180         union audio_test_mode            dpcd_test_mode = {0};
4181         struct audio_test_pattern_type   dpcd_pattern_type = {0};
4182         union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
4183         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
4184
4185         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4186         struct pipe_ctx *pipe_ctx = &pipes[0];
4187         unsigned int channel_count;
4188         unsigned int channel = 0;
4189         unsigned int modes = 0;
4190         unsigned int sampling_rate_in_hz = 0;
4191
4192         // get audio test mode and test pattern parameters
4193         core_link_read_dpcd(
4194                 link,
4195                 DP_TEST_AUDIO_MODE,
4196                 &dpcd_test_mode.raw,
4197                 sizeof(dpcd_test_mode));
4198
4199         core_link_read_dpcd(
4200                 link,
4201                 DP_TEST_AUDIO_PATTERN_TYPE,
4202                 &dpcd_pattern_type.value,
4203                 sizeof(dpcd_pattern_type));
4204
4205         channel_count = dpcd_test_mode.bits.channel_count + 1;
4206
4207         // read pattern periods for requested channels when sawTooth pattern is requested
4208         if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
4209                         dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
4210
4211                 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
4212                                 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
4213                 // read period for each channel
4214                 for (channel = 0; channel < channel_count; channel++) {
4215                         core_link_read_dpcd(
4216                                                         link,
4217                                                         DP_TEST_AUDIO_PERIOD_CH1 + channel,
4218                                                         &dpcd_pattern_period[channel].raw,
4219                                                         sizeof(dpcd_pattern_period[channel]));
4220                 }
4221         }
4222
4223         // translate sampling rate
4224         switch (dpcd_test_mode.bits.sampling_rate) {
4225         case AUDIO_SAMPLING_RATE_32KHZ:
4226                 sampling_rate_in_hz = 32000;
4227                 break;
4228         case AUDIO_SAMPLING_RATE_44_1KHZ:
4229                 sampling_rate_in_hz = 44100;
4230                 break;
4231         case AUDIO_SAMPLING_RATE_48KHZ:
4232                 sampling_rate_in_hz = 48000;
4233                 break;
4234         case AUDIO_SAMPLING_RATE_88_2KHZ:
4235                 sampling_rate_in_hz = 88200;
4236                 break;
4237         case AUDIO_SAMPLING_RATE_96KHZ:
4238                 sampling_rate_in_hz = 96000;
4239                 break;
4240         case AUDIO_SAMPLING_RATE_176_4KHZ:
4241                 sampling_rate_in_hz = 176400;
4242                 break;
4243         case AUDIO_SAMPLING_RATE_192KHZ:
4244                 sampling_rate_in_hz = 192000;
4245                 break;
4246         default:
4247                 sampling_rate_in_hz = 0;
4248                 break;
4249         }
4250
4251         link->audio_test_data.flags.test_requested = 1;
4252         link->audio_test_data.flags.disable_video = disable_video;
4253         link->audio_test_data.sampling_rate = sampling_rate_in_hz;
4254         link->audio_test_data.channel_count = channel_count;
4255         link->audio_test_data.pattern_type = test_pattern;
4256
4257         if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
4258                 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
4259                         link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
4260                 }
4261         }
4262 }
4263
4264 void dc_link_dp_handle_automated_test(struct dc_link *link)
4265 {
4266         union test_request test_request;
4267         union test_response test_response;
4268
4269         memset(&test_request, 0, sizeof(test_request));
4270         memset(&test_response, 0, sizeof(test_response));
4271
4272         core_link_read_dpcd(
4273                 link,
4274                 DP_TEST_REQUEST,
4275                 &test_request.raw,
4276                 sizeof(union test_request));
4277         if (test_request.bits.LINK_TRAINING) {
4278                 /* ACK first to let DP RX test box monitor LT sequence */
4279                 test_response.bits.ACK = 1;
4280                 core_link_write_dpcd(
4281                         link,
4282                         DP_TEST_RESPONSE,
4283                         &test_response.raw,
4284                         sizeof(test_response));
4285                 dp_test_send_link_training(link);
4286                 /* no acknowledge request is needed again */
4287                 test_response.bits.ACK = 0;
4288         }
4289         if (test_request.bits.LINK_TEST_PATTRN) {
4290                 dp_test_send_link_test_pattern(link);
4291                 test_response.bits.ACK = 1;
4292         }
4293
4294         if (test_request.bits.AUDIO_TEST_PATTERN) {
4295                 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
4296                 test_response.bits.ACK = 1;
4297         }
4298
4299         if (test_request.bits.PHY_TEST_PATTERN) {
4300                 dp_test_send_phy_test_pattern(link);
4301                 test_response.bits.ACK = 1;
4302         }
4303
4304         /* send request acknowledgment */
4305         if (test_response.bits.ACK)
4306                 core_link_write_dpcd(
4307                         link,
4308                         DP_TEST_RESPONSE,
4309                         &test_response.raw,
4310                         sizeof(test_response));
4311 }
4312
4313 void dc_link_dp_handle_link_loss(struct dc_link *link)
4314 {
4315         int i;
4316         struct pipe_ctx *pipe_ctx;
4317
4318         for (i = 0; i < MAX_PIPES; i++) {
4319                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
4320                 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
4321                         break;
4322         }
4323
4324         if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
4325                 return;
4326
4327         for (i = 0; i < MAX_PIPES; i++) {
4328                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
4329                 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
4330                                 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) {
4331                         core_link_disable_stream(pipe_ctx);
4332                 }
4333         }
4334
4335         for (i = 0; i < MAX_PIPES; i++) {
4336                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
4337                 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
4338                                 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) {
4339                         core_link_enable_stream(link->dc->current_state, pipe_ctx);
4340                 }
4341         }
4342 }
4343
4344 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss,
4345                                                         bool defer_handling, bool *has_left_work)
4346 {
4347         union hpd_irq_data hpd_irq_dpcd_data = {0};
4348         union device_service_irq device_service_clear = {0};
4349         enum dc_status result;
4350         bool status = false;
4351
4352         if (out_link_loss)
4353                 *out_link_loss = false;
4354
4355         if (has_left_work)
4356                 *has_left_work = false;
4357         /* For use cases related to down stream connection status change,
4358          * PSR and device auto test, refer to function handle_sst_hpd_irq
4359          * in DAL2.1*/
4360
4361         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
4362                 __func__, link->link_index);
4363
4364
4365          /* All the "handle_hpd_irq_xxx()" methods
4366                  * should be called only after
4367                  * dal_dpsst_ls_read_hpd_irq_data
4368                  * Order of calls is important too
4369                  */
4370         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
4371         if (out_hpd_irq_dpcd_data)
4372                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
4373
4374         if (result != DC_OK) {
4375                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
4376                         __func__);
4377                 return false;
4378         }
4379
4380         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
4381                 device_service_clear.bits.AUTOMATED_TEST = 1;
4382                 core_link_write_dpcd(
4383                         link,
4384                         DP_DEVICE_SERVICE_IRQ_VECTOR,
4385                         &device_service_clear.raw,
4386                         sizeof(device_service_clear.raw));
4387                 device_service_clear.raw = 0;
4388                 if (defer_handling && has_left_work)
4389                         *has_left_work = true;
4390                 else
4391                         dc_link_dp_handle_automated_test(link);
4392                 return false;
4393         }
4394
4395         if (!dc_link_dp_allow_hpd_rx_irq(link)) {
4396                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
4397                         __func__, link->link_index);
4398                 return false;
4399         }
4400
4401         if (handle_hpd_irq_psr_sink(link))
4402                 /* PSR-related error was detected and handled */
4403                 return true;
4404
4405         /* If PSR-related error handled, Main link may be off,
4406          * so do not handle as a normal sink status change interrupt.
4407          */
4408
4409         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY) {
4410                 if (defer_handling && has_left_work)
4411                         *has_left_work = true;
4412                 return true;
4413         }
4414
4415         /* check if we have MST msg and return since we poll for it */
4416         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
4417                 if (defer_handling && has_left_work)
4418                         *has_left_work = true;
4419                 return false;
4420         }
4421
4422         /* For now we only handle 'Downstream port status' case.
4423          * If we got sink count changed it means
4424          * Downstream port status changed,
4425          * then DM should call DC to do the detection.
4426          * NOTE: Do not handle link loss on eDP since it is internal link*/
4427         if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
4428                 hpd_rx_irq_check_link_loss_status(
4429                         link,
4430                         &hpd_irq_dpcd_data)) {
4431                 /* Connectivity log: link loss */
4432                 CONN_DATA_LINK_LOSS(link,
4433                                         hpd_irq_dpcd_data.raw,
4434                                         sizeof(hpd_irq_dpcd_data),
4435                                         "Status: ");
4436
4437                 if (defer_handling && has_left_work)
4438                         *has_left_work = true;
4439                 else
4440                         dc_link_dp_handle_link_loss(link);
4441
4442                 status = false;
4443                 if (out_link_loss)
4444                         *out_link_loss = true;
4445         }
4446
4447         if (link->type == dc_connection_sst_branch &&
4448                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
4449                         != link->dpcd_sink_count)
4450                 status = true;
4451
4452         /* reasons for HPD RX:
4453          * 1. Link Loss - ie Re-train the Link
4454          * 2. MST sideband message
4455          * 3. Automated Test - ie. Internal Commit
4456          * 4. CP (copy protection) - (not interesting for DM???)
4457          * 5. DRR
4458          * 6. Downstream Port status changed
4459          * -ie. Detect - this the only one
4460          * which is interesting for DM because
4461          * it must call dc_link_detect.
4462          */
4463         return status;
4464 }
4465
4466 /*query dpcd for version and mst cap addresses*/
4467 bool is_mst_supported(struct dc_link *link)
4468 {
4469         bool mst          = false;
4470         enum dc_status st = DC_OK;
4471         union dpcd_rev rev;
4472         union mstm_cap cap;
4473
4474         if (link->preferred_training_settings.mst_enable &&
4475                 *link->preferred_training_settings.mst_enable == false) {
4476                 return false;
4477         }
4478
4479         rev.raw  = 0;
4480         cap.raw  = 0;
4481
4482         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
4483                         sizeof(rev));
4484
4485         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
4486
4487                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
4488                                 &cap.raw, sizeof(cap));
4489                 if (st == DC_OK && cap.bits.MST_CAP == 1)
4490                         mst = true;
4491         }
4492         return mst;
4493
4494 }
4495
4496 bool is_dp_active_dongle(const struct dc_link *link)
4497 {
4498         return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
4499                                 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
4500 }
4501
4502 bool is_dp_branch_device(const struct dc_link *link)
4503 {
4504         return link->dpcd_caps.is_branch_dev;
4505 }
4506
4507 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
4508 {
4509         switch (bpc) {
4510         case DOWN_STREAM_MAX_8BPC:
4511                 return 8;
4512         case DOWN_STREAM_MAX_10BPC:
4513                 return 10;
4514         case DOWN_STREAM_MAX_12BPC:
4515                 return 12;
4516         case DOWN_STREAM_MAX_16BPC:
4517                 return 16;
4518         default:
4519                 break;
4520         }
4521
4522         return -1;
4523 }
4524
4525 #if defined(CONFIG_DRM_AMD_DC_DCN)
4526 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)
4527 {
4528         switch (bw) {
4529         case 0b001:
4530                 return 9000000;
4531         case 0b010:
4532                 return 18000000;
4533         case 0b011:
4534                 return 24000000;
4535         case 0b100:
4536                 return 32000000;
4537         case 0b101:
4538                 return 40000000;
4539         case 0b110:
4540                 return 48000000;
4541         }
4542
4543         return 0;
4544 }
4545
4546 /**
4547  * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw.
4548  */
4549 static uint32_t intersect_frl_link_bw_support(
4550         const uint32_t max_supported_frl_bw_in_kbps,
4551         const union hdmi_encoded_link_bw hdmi_encoded_link_bw)
4552 {
4553         uint32_t supported_bw_in_kbps = max_supported_frl_bw_in_kbps;
4554
4555         // HDMI_ENCODED_LINK_BW bits are only valid if HDMI Link Configuration bit is 1 (FRL mode)
4556         if (hdmi_encoded_link_bw.bits.FRL_MODE) {
4557                 if (hdmi_encoded_link_bw.bits.BW_48Gbps)
4558                         supported_bw_in_kbps = 48000000;
4559                 else if (hdmi_encoded_link_bw.bits.BW_40Gbps)
4560                         supported_bw_in_kbps = 40000000;
4561                 else if (hdmi_encoded_link_bw.bits.BW_32Gbps)
4562                         supported_bw_in_kbps = 32000000;
4563                 else if (hdmi_encoded_link_bw.bits.BW_24Gbps)
4564                         supported_bw_in_kbps = 24000000;
4565                 else if (hdmi_encoded_link_bw.bits.BW_18Gbps)
4566                         supported_bw_in_kbps = 18000000;
4567                 else if (hdmi_encoded_link_bw.bits.BW_9Gbps)
4568                         supported_bw_in_kbps = 9000000;
4569         }
4570
4571         return supported_bw_in_kbps;
4572 }
4573 #endif
4574
4575 static void read_dp_device_vendor_id(struct dc_link *link)
4576 {
4577         struct dp_device_vendor_id dp_id;
4578
4579         /* read IEEE branch device id */
4580         core_link_read_dpcd(
4581                 link,
4582                 DP_BRANCH_OUI,
4583                 (uint8_t *)&dp_id,
4584                 sizeof(dp_id));
4585
4586         link->dpcd_caps.branch_dev_id =
4587                 (dp_id.ieee_oui[0] << 16) +
4588                 (dp_id.ieee_oui[1] << 8) +
4589                 dp_id.ieee_oui[2];
4590
4591         memmove(
4592                 link->dpcd_caps.branch_dev_name,
4593                 dp_id.ieee_device_id,
4594                 sizeof(dp_id.ieee_device_id));
4595 }
4596
4597
4598
4599 static void get_active_converter_info(
4600         uint8_t data, struct dc_link *link)
4601 {
4602         union dp_downstream_port_present ds_port = { .byte = data };
4603         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
4604
4605         /* decode converter info*/
4606         if (!ds_port.fields.PORT_PRESENT) {
4607                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
4608                 ddc_service_set_dongle_type(link->ddc,
4609                                 link->dpcd_caps.dongle_type);
4610                 link->dpcd_caps.is_branch_dev = false;
4611                 return;
4612         }
4613
4614         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
4615         link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
4616
4617         switch (ds_port.fields.PORT_TYPE) {
4618         case DOWNSTREAM_VGA:
4619                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
4620                 break;
4621         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
4622                 /* At this point we don't know is it DVI or HDMI or DP++,
4623                  * assume DVI.*/
4624                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
4625                 break;
4626         default:
4627                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
4628                 break;
4629         }
4630
4631         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
4632                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
4633                 union dwnstream_port_caps_byte0 *port_caps =
4634                         (union dwnstream_port_caps_byte0 *)det_caps;
4635                 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
4636                                 det_caps, sizeof(det_caps)) == DC_OK) {
4637
4638                         switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
4639                         /*Handle DP case as DONGLE_NONE*/
4640                         case DOWN_STREAM_DETAILED_DP:
4641                                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
4642                                 break;
4643                         case DOWN_STREAM_DETAILED_VGA:
4644                                 link->dpcd_caps.dongle_type =
4645                                         DISPLAY_DONGLE_DP_VGA_CONVERTER;
4646                                 break;
4647                         case DOWN_STREAM_DETAILED_DVI:
4648                                 link->dpcd_caps.dongle_type =
4649                                         DISPLAY_DONGLE_DP_DVI_CONVERTER;
4650                                 break;
4651                         case DOWN_STREAM_DETAILED_HDMI:
4652                         case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
4653                                 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
4654                                 link->dpcd_caps.dongle_type =
4655                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER;
4656
4657                                 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
4658                                 if (ds_port.fields.DETAILED_CAPS) {
4659
4660                                         union dwnstream_port_caps_byte3_hdmi
4661                                                 hdmi_caps = {.raw = det_caps[3] };
4662                                         union dwnstream_port_caps_byte2
4663                                                 hdmi_color_caps = {.raw = det_caps[2] };
4664                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
4665                                                 det_caps[1] * 2500;
4666
4667                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
4668                                                 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
4669                                         /*YCBCR capability only for HDMI case*/
4670                                         if (port_caps->bits.DWN_STRM_PORTX_TYPE
4671                                                         == DOWN_STREAM_DETAILED_HDMI) {
4672                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
4673                                                                 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
4674                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
4675                                                                 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
4676                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
4677                                                                 hdmi_caps.bits.YCrCr422_CONVERSION;
4678                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
4679                                                                 hdmi_caps.bits.YCrCr420_CONVERSION;
4680                                         }
4681
4682                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
4683                                                 translate_dpcd_max_bpc(
4684                                                         hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
4685
4686 #if defined(CONFIG_DRM_AMD_DC_DCN)
4687                                         if (link->dc->caps.hdmi_frl_pcon_support) {
4688                                                 union hdmi_encoded_link_bw hdmi_encoded_link_bw;
4689
4690                                                 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps =
4691                                                                 dc_link_bw_kbps_from_raw_frl_link_rate_data(
4692                                                                                 hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT);
4693
4694                                                 // Intersect reported max link bw support with the supported link rate post FRL link training
4695                                                 if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS,
4696                                                                 &hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) {
4697                                                         link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support(
4698                                                                         link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps,
4699                                                                         hdmi_encoded_link_bw);
4700                                                 }
4701
4702                                                 if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0)
4703                                                         link->dpcd_caps.dongle_caps.extendedCapValid = true;
4704                                         }
4705 #endif
4706
4707                                         if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
4708                                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
4709                                 }
4710
4711                                 break;
4712                         }
4713                 }
4714         }
4715
4716         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
4717
4718         {
4719                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
4720
4721                 core_link_read_dpcd(
4722                         link,
4723                         DP_BRANCH_REVISION_START,
4724                         (uint8_t *)&dp_hw_fw_revision,
4725                         sizeof(dp_hw_fw_revision));
4726
4727                 link->dpcd_caps.branch_hw_revision =
4728                         dp_hw_fw_revision.ieee_hw_rev;
4729
4730                 memmove(
4731                         link->dpcd_caps.branch_fw_revision,
4732                         dp_hw_fw_revision.ieee_fw_rev,
4733                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
4734         }
4735 #if defined(CONFIG_DRM_AMD_DC_DCN)
4736         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
4737                         link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
4738                 union dp_dfp_cap_ext dfp_cap_ext;
4739                 memset(&dfp_cap_ext, '\0', sizeof (dfp_cap_ext));
4740                 core_link_read_dpcd(
4741                                 link,
4742                                 DP_DFP_CAPABILITY_EXTENSION_SUPPORT,
4743                                 dfp_cap_ext.raw,
4744                                 sizeof(dfp_cap_ext.raw));
4745                 link->dpcd_caps.dongle_caps.dfp_cap_ext.supported = dfp_cap_ext.fields.supported;
4746                 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps =
4747                                 dfp_cap_ext.fields.max_pixel_rate_in_mps[0] +
4748                                 (dfp_cap_ext.fields.max_pixel_rate_in_mps[1] << 8);
4749                 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width =
4750                                 dfp_cap_ext.fields.max_video_h_active_width[0] +
4751                                 (dfp_cap_ext.fields.max_video_h_active_width[1] << 8);
4752                 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height =
4753                                 dfp_cap_ext.fields.max_video_v_active_height[0] +
4754                                 (dfp_cap_ext.fields.max_video_v_active_height[1] << 8);
4755                 link->dpcd_caps.dongle_caps.dfp_cap_ext.encoding_format_caps =
4756                                 dfp_cap_ext.fields.encoding_format_caps;
4757                 link->dpcd_caps.dongle_caps.dfp_cap_ext.rgb_color_depth_caps =
4758                                 dfp_cap_ext.fields.rgb_color_depth_caps;
4759                 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr444_color_depth_caps =
4760                                 dfp_cap_ext.fields.ycbcr444_color_depth_caps;
4761                 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr422_color_depth_caps =
4762                                 dfp_cap_ext.fields.ycbcr422_color_depth_caps;
4763                 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr420_color_depth_caps =
4764                                 dfp_cap_ext.fields.ycbcr420_color_depth_caps;
4765                 DC_LOG_DP2("DFP capability extension is read at link %d", link->link_index);
4766                 DC_LOG_DP2("\tdfp_cap_ext.supported = %s", link->dpcd_caps.dongle_caps.dfp_cap_ext.supported ? "true" : "false");
4767                 DC_LOG_DP2("\tdfp_cap_ext.max_pixel_rate_in_mps = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps);
4768                 DC_LOG_DP2("\tdfp_cap_ext.max_video_h_active_width = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width);
4769                 DC_LOG_DP2("\tdfp_cap_ext.max_video_v_active_height = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height);
4770         }
4771 #endif
4772 }
4773
4774 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
4775                 int length)
4776 {
4777         int retry = 0;
4778
4779         if (!link->dpcd_caps.dpcd_rev.raw) {
4780                 do {
4781                         dp_receiver_power_ctrl(link, true);
4782                         core_link_read_dpcd(link, DP_DPCD_REV,
4783                                                         dpcd_data, length);
4784                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
4785                                 DP_DPCD_REV -
4786                                 DP_DPCD_REV];
4787                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
4788         }
4789
4790         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
4791                 switch (link->dpcd_caps.branch_dev_id) {
4792                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
4793                  * all internal circuits including AUX communication preventing
4794                  * reading DPCD table and EDID (spec violation).
4795                  * Encoder will skip DP RX power down on disable_output to
4796                  * keep receiver powered all the time.*/
4797                 case DP_BRANCH_DEVICE_ID_0010FA:
4798                 case DP_BRANCH_DEVICE_ID_0080E1:
4799                 case DP_BRANCH_DEVICE_ID_00E04C:
4800                         link->wa_flags.dp_keep_receiver_powered = true;
4801                         break;
4802
4803                 /* TODO: May need work around for other dongles. */
4804                 default:
4805                         link->wa_flags.dp_keep_receiver_powered = false;
4806                         break;
4807                 }
4808         } else
4809                 link->wa_flags.dp_keep_receiver_powered = false;
4810 }
4811
4812 /* Read additional sink caps defined in source specific DPCD area
4813  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
4814  */
4815 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
4816 {
4817         uint8_t dpcd_data;
4818
4819         if (!link)
4820                 return false;
4821
4822         if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
4823                 return false;
4824
4825         link->dpcd_sink_ext_caps.raw = dpcd_data;
4826         return true;
4827 }
4828
4829 bool dp_retrieve_lttpr_cap(struct dc_link *link)
4830 {
4831 #if defined(CONFIG_DRM_AMD_DC_DCN)
4832         uint8_t lttpr_dpcd_data[8];
4833         bool allow_lttpr_non_transparent_mode = 0;
4834 #else
4835         uint8_t lttpr_dpcd_data[6];
4836 #endif
4837         bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable;
4838         bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
4839         enum dc_status status = DC_ERROR_UNEXPECTED;
4840         bool is_lttpr_present = false;
4841
4842         memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
4843
4844 #if defined(CONFIG_DRM_AMD_DC_DCN)
4845         if ((link->dc->config.allow_lttpr_non_transparent_mode.bits.DP2_0 &&
4846                         link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)) {
4847                 allow_lttpr_non_transparent_mode = 1;
4848         } else if (link->dc->config.allow_lttpr_non_transparent_mode.bits.DP1_4A &&
4849                         !link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
4850                 allow_lttpr_non_transparent_mode = 1;
4851         }
4852 #endif
4853
4854         /*
4855          * Logic to determine LTTPR mode
4856          */
4857         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
4858         if (vbios_lttpr_enable && vbios_lttpr_interop)
4859                 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
4860         else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
4861 #if defined(CONFIG_DRM_AMD_DC_DCN)
4862                 if (allow_lttpr_non_transparent_mode)
4863 #else
4864                 if (link->dc->config.allow_lttpr_non_transparent_mode)
4865 #endif
4866                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
4867                 else
4868                         link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
4869         } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
4870 #if defined(CONFIG_DRM_AMD_DC_DCN)
4871                 if (!allow_lttpr_non_transparent_mode || !link->dc->caps.extended_aux_timeout_support)
4872 #else
4873                 if (!link->dc->config.allow_lttpr_non_transparent_mode
4874                         || !link->dc->caps.extended_aux_timeout_support)
4875 #endif
4876                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
4877                 else
4878                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
4879         }
4880 #if defined(CONFIG_DRM_AMD_DC_DCN)
4881         /* Check DP tunnel LTTPR mode debug option. */
4882         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
4883             link->dc->debug.dpia_debug.bits.force_non_lttpr)
4884                 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
4885 #endif
4886
4887         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
4888                 /* By reading LTTPR capability, RX assumes that we will enable
4889                  * LTTPR extended aux timeout if LTTPR is present.
4890                  */
4891                 status = core_link_read_dpcd(
4892                                 link,
4893                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
4894                                 lttpr_dpcd_data,
4895                                 sizeof(lttpr_dpcd_data));
4896                 if (status != DC_OK) {
4897                         DC_LOG_DP2("%s: Read LTTPR caps data failed.\n", __func__);
4898                         return false;
4899                 }
4900
4901                 link->dpcd_caps.lttpr_caps.revision.raw =
4902                                 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
4903                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
4904
4905                 link->dpcd_caps.lttpr_caps.max_link_rate =
4906                                 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
4907                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
4908
4909                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
4910                                 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
4911                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
4912
4913                 link->dpcd_caps.lttpr_caps.max_lane_count =
4914                                 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
4915                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
4916
4917                 link->dpcd_caps.lttpr_caps.mode =
4918                                 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
4919                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
4920
4921                 link->dpcd_caps.lttpr_caps.max_ext_timeout =
4922                                 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
4923                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
4924
4925 #if defined(CONFIG_DRM_AMD_DC_DCN)
4926                 link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw =
4927                                 lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
4928                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
4929
4930                 link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
4931                                 lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES -
4932                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
4933 #endif
4934
4935                 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
4936                 is_lttpr_present = (dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
4937                                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt < 0xff &&
4938                                 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
4939                                 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
4940                                 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
4941                 if (is_lttpr_present) {
4942                         CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
4943                         configure_lttpr_mode_transparent(link);
4944                 } else
4945                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
4946         }
4947         return is_lttpr_present;
4948 }
4949
4950 static bool retrieve_link_cap(struct dc_link *link)
4951 {
4952         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
4953          * which means size 16 will be good for both of those DPCD register block reads
4954          */
4955         uint8_t dpcd_data[16];
4956         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
4957          */
4958         uint8_t dpcd_dprx_data = '\0';
4959         uint8_t dpcd_power_state = '\0';
4960
4961         struct dp_device_vendor_id sink_id;
4962         union down_stream_port_count down_strm_port_count;
4963         union edp_configuration_cap edp_config_cap;
4964         union dp_downstream_port_present ds_port = { 0 };
4965         enum dc_status status = DC_ERROR_UNEXPECTED;
4966         uint32_t read_dpcd_retry_cnt = 3;
4967         int i;
4968         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
4969         const uint32_t post_oui_delay = 30; // 30ms
4970         bool is_lttpr_present = false;
4971
4972         memset(dpcd_data, '\0', sizeof(dpcd_data));
4973         memset(&down_strm_port_count,
4974                 '\0', sizeof(union down_stream_port_count));
4975         memset(&edp_config_cap, '\0',
4976                 sizeof(union edp_configuration_cap));
4977
4978         /* if extended timeout is supported in hardware,
4979          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
4980          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
4981          */
4982         dc_link_aux_try_to_configure_timeout(link->ddc,
4983                         LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
4984
4985         is_lttpr_present = dp_retrieve_lttpr_cap(link);
4986         /* Read DP tunneling information. */
4987         status = dpcd_get_tunneling_device_data(link);
4988
4989         status = core_link_read_dpcd(link, DP_SET_POWER,
4990                         &dpcd_power_state, sizeof(dpcd_power_state));
4991
4992         /* Delay 1 ms if AUX CH is in power down state. Based on spec
4993          * section 2.3.1.2, if AUX CH may be powered down due to
4994          * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
4995          * signal and may need up to 1 ms before being able to reply.
4996          */
4997         if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
4998                 udelay(1000);
4999
5000         dpcd_set_source_specific_data(link);
5001         /* Sink may need to configure internals based on vendor, so allow some
5002          * time before proceeding with possibly vendor specific transactions
5003          */
5004         msleep(post_oui_delay);
5005
5006         for (i = 0; i < read_dpcd_retry_cnt; i++) {
5007                 status = core_link_read_dpcd(
5008                                 link,
5009                                 DP_DPCD_REV,
5010                                 dpcd_data,
5011                                 sizeof(dpcd_data));
5012                 if (status == DC_OK)
5013                         break;
5014         }
5015
5016         if (status != DC_OK) {
5017                 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
5018                 return false;
5019         }
5020
5021         if (!is_lttpr_present)
5022                 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
5023
5024         {
5025                 union training_aux_rd_interval aux_rd_interval;
5026
5027                 aux_rd_interval.raw =
5028                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
5029
5030                 link->dpcd_caps.ext_receiver_cap_field_present =
5031                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
5032
5033                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
5034                         uint8_t ext_cap_data[16];
5035
5036                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
5037                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
5038                                 status = core_link_read_dpcd(
5039                                 link,
5040                                 DP_DP13_DPCD_REV,
5041                                 ext_cap_data,
5042                                 sizeof(ext_cap_data));
5043                                 if (status == DC_OK) {
5044                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
5045                                         break;
5046                                 }
5047                         }
5048                         if (status != DC_OK)
5049                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
5050                 }
5051         }
5052
5053         link->dpcd_caps.dpcd_rev.raw =
5054                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
5055
5056         if (link->dpcd_caps.ext_receiver_cap_field_present) {
5057                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
5058                         status = core_link_read_dpcd(
5059                                         link,
5060                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
5061                                         &dpcd_dprx_data,
5062                                         sizeof(dpcd_dprx_data));
5063                         if (status == DC_OK)
5064                                 break;
5065                 }
5066
5067                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
5068
5069                 if (status != DC_OK)
5070                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
5071         }
5072
5073         else {
5074                 link->dpcd_caps.dprx_feature.raw = 0;
5075         }
5076
5077
5078         /* Error condition checking...
5079          * It is impossible for Sink to report Max Lane Count = 0.
5080          * It is possible for Sink to report Max Link Rate = 0, if it is
5081          * an eDP device that is reporting specialized link rates in the
5082          * SUPPORTED_LINK_RATE table.
5083          */
5084         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
5085                 return false;
5086
5087         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
5088                                  DP_DPCD_REV];
5089
5090         read_dp_device_vendor_id(link);
5091
5092         get_active_converter_info(ds_port.byte, link);
5093
5094         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
5095
5096         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
5097                                  DP_DPCD_REV];
5098
5099         link->dpcd_caps.allow_invalid_MSA_timing_param =
5100                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
5101
5102         link->dpcd_caps.max_ln_count.raw = dpcd_data[
5103                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
5104
5105         link->dpcd_caps.max_down_spread.raw = dpcd_data[
5106                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
5107
5108         link->reported_link_cap.lane_count =
5109                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
5110         link->reported_link_cap.link_rate = dpcd_data[
5111                 DP_MAX_LINK_RATE - DP_DPCD_REV];
5112         link->reported_link_cap.link_spread =
5113                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
5114                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
5115
5116         edp_config_cap.raw = dpcd_data[
5117                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
5118         link->dpcd_caps.panel_mode_edp =
5119                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
5120         link->dpcd_caps.dpcd_display_control_capable =
5121                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
5122
5123         link->test_pattern_enabled = false;
5124         link->compliance_test_state.raw = 0;
5125
5126         /* read sink count */
5127         core_link_read_dpcd(link,
5128                         DP_SINK_COUNT,
5129                         &link->dpcd_caps.sink_count.raw,
5130                         sizeof(link->dpcd_caps.sink_count.raw));
5131
5132         /* read sink ieee oui */
5133         core_link_read_dpcd(link,
5134                         DP_SINK_OUI,
5135                         (uint8_t *)(&sink_id),
5136                         sizeof(sink_id));
5137
5138         link->dpcd_caps.sink_dev_id =
5139                         (sink_id.ieee_oui[0] << 16) +
5140                         (sink_id.ieee_oui[1] << 8) +
5141                         (sink_id.ieee_oui[2]);
5142
5143         memmove(
5144                 link->dpcd_caps.sink_dev_id_str,
5145                 sink_id.ieee_device_id,
5146                 sizeof(sink_id.ieee_device_id));
5147
5148         /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
5149         {
5150                 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
5151
5152                 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
5153                     !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
5154                             sizeof(str_mbp_2017))) {
5155                         link->reported_link_cap.link_rate = 0x0c;
5156                 }
5157         }
5158
5159         core_link_read_dpcd(
5160                 link,
5161                 DP_SINK_HW_REVISION_START,
5162                 (uint8_t *)&dp_hw_fw_revision,
5163                 sizeof(dp_hw_fw_revision));
5164
5165         link->dpcd_caps.sink_hw_revision =
5166                 dp_hw_fw_revision.ieee_hw_rev;
5167
5168         memmove(
5169                 link->dpcd_caps.sink_fw_revision,
5170                 dp_hw_fw_revision.ieee_fw_rev,
5171                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
5172
5173         memset(&link->dpcd_caps.dsc_caps, '\0',
5174                         sizeof(link->dpcd_caps.dsc_caps));
5175         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
5176         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
5177         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
5178                 status = core_link_read_dpcd(
5179                                 link,
5180                                 DP_FEC_CAPABILITY,
5181                                 &link->dpcd_caps.fec_cap.raw,
5182                                 sizeof(link->dpcd_caps.fec_cap.raw));
5183                 status = core_link_read_dpcd(
5184                                 link,
5185                                 DP_DSC_SUPPORT,
5186                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5187                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
5188 #if defined(CONFIG_DRM_AMD_DC_DCN)
5189                 if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
5190                         status = core_link_read_dpcd(
5191                                         link,
5192                                         DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
5193                                         link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5194                                         sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
5195                         DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index);
5196                         DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x",
5197                                         link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_0);
5198                         DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_1 = 0x%02x",
5199                                         link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_1);
5200                         DC_LOG_DSC("\tBRANCH_MAX_LINE_WIDTH 0x%02x",
5201                                         link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_MAX_LINE_WIDTH);
5202                 }
5203 #else
5204                 status = core_link_read_dpcd(
5205                                 link,
5206                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
5207                                 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5208                                 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
5209 #endif
5210         }
5211
5212         if (!dpcd_read_sink_ext_caps(link))
5213                 link->dpcd_sink_ext_caps.raw = 0;
5214
5215 #if defined(CONFIG_DRM_AMD_DC_DCN)
5216         link->dpcd_caps.channel_coding_cap.raw = dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_CAP - DP_DPCD_REV];
5217
5218         if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
5219                 DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index);
5220
5221                 core_link_read_dpcd(link,
5222                                 DP_128b_132b_SUPPORTED_LINK_RATES,
5223                                 &link->dpcd_caps.dp_128b_132b_supported_link_rates.raw,
5224                                 sizeof(link->dpcd_caps.dp_128b_132b_supported_link_rates.raw));
5225                 if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR20)
5226                         link->reported_link_cap.link_rate = LINK_RATE_UHBR20;
5227                 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)
5228                         link->reported_link_cap.link_rate = LINK_RATE_UHBR13_5;
5229                 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR10)
5230                         link->reported_link_cap.link_rate = LINK_RATE_UHBR10;
5231                 else
5232                         dm_error("%s: Invalid RX 128b_132b_supported_link_rates\n", __func__);
5233                 DC_LOG_DP2("128b/132b supported link rates is read at link %d", link->link_index);
5234                 DC_LOG_DP2("\tmax 128b/132b link rate support is %d.%d GHz",
5235                                 link->reported_link_cap.link_rate / 100,
5236                                 link->reported_link_cap.link_rate % 100);
5237
5238                 core_link_read_dpcd(link,
5239                                 DP_SINK_VIDEO_FALLBACK_FORMATS,
5240                                 &link->dpcd_caps.fallback_formats.raw,
5241                                 sizeof(link->dpcd_caps.fallback_formats.raw));
5242                 DC_LOG_DP2("sink video fallback format is read at link %d", link->link_index);
5243                 if (link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support)
5244                         DC_LOG_DP2("\t1920x1080@60Hz 24bpp fallback format supported");
5245                 if (link->dpcd_caps.fallback_formats.bits.dp_1280x720_60Hz_24bpp_support)
5246                         DC_LOG_DP2("\t1280x720@60Hz 24bpp fallback format supported");
5247                 if (link->dpcd_caps.fallback_formats.bits.dp_1024x768_60Hz_24bpp_support)
5248                         DC_LOG_DP2("\t1024x768@60Hz 24bpp fallback format supported");
5249                 if (link->dpcd_caps.fallback_formats.raw == 0) {
5250                         DC_LOG_DP2("\tno supported fallback formats, assume 1920x1080@60Hz 24bpp is supported");
5251                         link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support = 1;
5252                 }
5253
5254                 core_link_read_dpcd(link,
5255                                 DP_FEC_CAPABILITY_1,
5256                                 &link->dpcd_caps.fec_cap1.raw,
5257                                 sizeof(link->dpcd_caps.fec_cap1.raw));
5258                 DC_LOG_DP2("FEC CAPABILITY 1 is read at link %d", link->link_index);
5259                 if (link->dpcd_caps.fec_cap1.bits.AGGREGATED_ERROR_COUNTERS_CAPABLE)
5260                         DC_LOG_DP2("\tFEC aggregated error counters are supported");
5261         }
5262 #endif
5263
5264         /* Connectivity log: detection */
5265         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
5266
5267         return true;
5268 }
5269
5270 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
5271 {
5272         uint8_t dpcd_data[16];
5273         uint32_t read_dpcd_retry_cnt = 3;
5274         enum dc_status status = DC_ERROR_UNEXPECTED;
5275         union dp_downstream_port_present ds_port = { 0 };
5276         union down_stream_port_count down_strm_port_count;
5277         union edp_configuration_cap edp_config_cap;
5278
5279         int i;
5280
5281         for (i = 0; i < read_dpcd_retry_cnt; i++) {
5282                 status = core_link_read_dpcd(
5283                                 link,
5284                                 DP_DPCD_REV,
5285                                 dpcd_data,
5286                                 sizeof(dpcd_data));
5287                 if (status == DC_OK)
5288                         break;
5289         }
5290
5291         link->dpcd_caps.dpcd_rev.raw =
5292                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
5293
5294         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
5295                 return false;
5296
5297         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
5298                         DP_DPCD_REV];
5299
5300         get_active_converter_info(ds_port.byte, link);
5301
5302         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
5303                         DP_DPCD_REV];
5304
5305         link->dpcd_caps.allow_invalid_MSA_timing_param =
5306                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
5307
5308         link->dpcd_caps.max_ln_count.raw = dpcd_data[
5309                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
5310
5311         link->dpcd_caps.max_down_spread.raw = dpcd_data[
5312                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
5313
5314         link->reported_link_cap.lane_count =
5315                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
5316         link->reported_link_cap.link_rate = dpcd_data[
5317                 DP_MAX_LINK_RATE - DP_DPCD_REV];
5318         link->reported_link_cap.link_spread =
5319                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
5320                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
5321
5322         edp_config_cap.raw = dpcd_data[
5323                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
5324         link->dpcd_caps.panel_mode_edp =
5325                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
5326         link->dpcd_caps.dpcd_display_control_capable =
5327                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
5328
5329         return true;
5330 }
5331
5332 bool detect_dp_sink_caps(struct dc_link *link)
5333 {
5334         return retrieve_link_cap(link);
5335
5336         /* dc init_hw has power encoder using default
5337          * signal for connector. For native DP, no
5338          * need to power up encoder again. If not native
5339          * DP, hw_init may need check signal or power up
5340          * encoder here.
5341          */
5342         /* TODO save sink caps in link->sink */
5343 }
5344
5345 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
5346 {
5347         enum dc_link_rate link_rate;
5348         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
5349         switch (link_rate_in_khz) {
5350         case 1620000:
5351                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
5352                 break;
5353         case 2160000:
5354                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
5355                 break;
5356         case 2430000:
5357                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
5358                 break;
5359         case 2700000:
5360                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
5361                 break;
5362         case 3240000:
5363                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
5364                 break;
5365         case 4320000:
5366                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
5367                 break;
5368         case 5400000:
5369                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
5370                 break;
5371         case 8100000:
5372                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
5373                 break;
5374         default:
5375                 link_rate = LINK_RATE_UNKNOWN;
5376                 break;
5377         }
5378         return link_rate;
5379 }
5380
5381 void detect_edp_sink_caps(struct dc_link *link)
5382 {
5383         uint8_t supported_link_rates[16];
5384         uint32_t entry;
5385         uint32_t link_rate_in_khz;
5386         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
5387         uint8_t backlight_adj_cap;
5388
5389         retrieve_link_cap(link);
5390         link->dpcd_caps.edp_supported_link_rates_count = 0;
5391         memset(supported_link_rates, 0, sizeof(supported_link_rates));
5392
5393         /*
5394          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
5395          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
5396          */
5397         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
5398                         (link->dc->debug.optimize_edp_link_rate ||
5399                         link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
5400                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
5401                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
5402                                                         supported_link_rates, sizeof(supported_link_rates));
5403
5404                 for (entry = 0; entry < 16; entry += 2) {
5405                         // DPCD register reports per-lane link rate = 16-bit link rate capability
5406                         // value X 200 kHz. Need multiplier to find link rate in kHz.
5407                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
5408                                                                                 supported_link_rates[entry]) * 200;
5409
5410                         if (link_rate_in_khz != 0) {
5411                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
5412                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
5413                                 link->dpcd_caps.edp_supported_link_rates_count++;
5414
5415                                 if (link->reported_link_cap.link_rate < link_rate)
5416                                         link->reported_link_cap.link_rate = link_rate;
5417                         }
5418                 }
5419         }
5420         link->verified_link_cap = link->reported_link_cap;
5421
5422         core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
5423                                                 &backlight_adj_cap, sizeof(backlight_adj_cap));
5424
5425         link->dpcd_caps.dynamic_backlight_capable_edp =
5426                                 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
5427
5428         dc_link_set_default_brightness_aux(link);
5429 }
5430
5431 void dc_link_dp_enable_hpd(const struct dc_link *link)
5432 {
5433         struct link_encoder *encoder = link->link_enc;
5434
5435         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
5436                 encoder->funcs->enable_hpd(encoder);
5437 }
5438
5439 void dc_link_dp_disable_hpd(const struct dc_link *link)
5440 {
5441         struct link_encoder *encoder = link->link_enc;
5442
5443         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
5444                 encoder->funcs->disable_hpd(encoder);
5445 }
5446
5447 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
5448 {
5449         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
5450                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
5451                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
5452                 return true;
5453         else
5454                 return false;
5455 }
5456
5457 static void set_crtc_test_pattern(struct dc_link *link,
5458                                 struct pipe_ctx *pipe_ctx,
5459                                 enum dp_test_pattern test_pattern,
5460                                 enum dp_test_pattern_color_space test_pattern_color_space)
5461 {
5462         enum controller_dp_test_pattern controller_test_pattern;
5463         enum dc_color_depth color_depth = pipe_ctx->
5464                 stream->timing.display_color_depth;
5465         struct bit_depth_reduction_params params;
5466         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
5467         int width = pipe_ctx->stream->timing.h_addressable +
5468                 pipe_ctx->stream->timing.h_border_left +
5469                 pipe_ctx->stream->timing.h_border_right;
5470         int height = pipe_ctx->stream->timing.v_addressable +
5471                 pipe_ctx->stream->timing.v_border_bottom +
5472                 pipe_ctx->stream->timing.v_border_top;
5473
5474         memset(&params, 0, sizeof(params));
5475
5476         switch (test_pattern) {
5477         case DP_TEST_PATTERN_COLOR_SQUARES:
5478                 controller_test_pattern =
5479                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
5480         break;
5481         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
5482                 controller_test_pattern =
5483                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
5484         break;
5485         case DP_TEST_PATTERN_VERTICAL_BARS:
5486                 controller_test_pattern =
5487                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
5488         break;
5489         case DP_TEST_PATTERN_HORIZONTAL_BARS:
5490                 controller_test_pattern =
5491                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
5492         break;
5493         case DP_TEST_PATTERN_COLOR_RAMP:
5494                 controller_test_pattern =
5495                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
5496         break;
5497         default:
5498                 controller_test_pattern =
5499                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
5500         break;
5501         }
5502
5503         switch (test_pattern) {
5504         case DP_TEST_PATTERN_COLOR_SQUARES:
5505         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
5506         case DP_TEST_PATTERN_VERTICAL_BARS:
5507         case DP_TEST_PATTERN_HORIZONTAL_BARS:
5508         case DP_TEST_PATTERN_COLOR_RAMP:
5509         {
5510                 /* disable bit depth reduction */
5511                 pipe_ctx->stream->bit_depth_params = params;
5512                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
5513                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
5514                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
5515                                 controller_test_pattern, color_depth);
5516                 else if (link->dc->hwss.set_disp_pattern_generator) {
5517                         struct pipe_ctx *odm_pipe;
5518                         enum controller_dp_color_space controller_color_space;
5519                         int opp_cnt = 1;
5520                         int offset = 0;
5521                         int dpg_width = width;
5522
5523                         switch (test_pattern_color_space) {
5524                         case DP_TEST_PATTERN_COLOR_SPACE_RGB:
5525                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
5526                                 break;
5527                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
5528                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
5529                                 break;
5530                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
5531                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
5532                                 break;
5533                         case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
5534                         default:
5535                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
5536                                 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
5537                                 ASSERT(0);
5538                                 break;
5539                         }
5540
5541                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
5542                                 opp_cnt++;
5543                         dpg_width = width / opp_cnt;
5544                         offset = dpg_width;
5545
5546                         link->dc->hwss.set_disp_pattern_generator(link->dc,
5547                                         pipe_ctx,
5548                                         controller_test_pattern,
5549                                         controller_color_space,
5550                                         color_depth,
5551                                         NULL,
5552                                         dpg_width,
5553                                         height,
5554                                         0);
5555
5556                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
5557                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
5558
5559                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
5560                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
5561                                                 odm_pipe,
5562                                                 controller_test_pattern,
5563                                                 controller_color_space,
5564                                                 color_depth,
5565                                                 NULL,
5566                                                 dpg_width,
5567                                                 height,
5568                                                 offset);
5569                                 offset += offset;
5570                         }
5571                 }
5572         }
5573         break;
5574         case DP_TEST_PATTERN_VIDEO_MODE:
5575         {
5576                 /* restore bitdepth reduction */
5577                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
5578                 pipe_ctx->stream->bit_depth_params = params;
5579                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
5580                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
5581                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
5582                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
5583                                 color_depth);
5584                 else if (link->dc->hwss.set_disp_pattern_generator) {
5585                         struct pipe_ctx *odm_pipe;
5586                         int opp_cnt = 1;
5587                         int dpg_width = width;
5588
5589                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
5590                                 opp_cnt++;
5591
5592                         dpg_width = width / opp_cnt;
5593                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
5594                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
5595
5596                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
5597                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
5598                                                 odm_pipe,
5599                                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
5600                                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
5601                                                 color_depth,
5602                                                 NULL,
5603                                                 dpg_width,
5604                                                 height,
5605                                                 0);
5606                         }
5607                         link->dc->hwss.set_disp_pattern_generator(link->dc,
5608                                         pipe_ctx,
5609                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
5610                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
5611                                         color_depth,
5612                                         NULL,
5613                                         dpg_width,
5614                                         height,
5615                                         0);
5616                 }
5617         }
5618         break;
5619
5620         default:
5621         break;
5622         }
5623 }
5624
5625 bool dc_link_dp_set_test_pattern(
5626         struct dc_link *link,
5627         enum dp_test_pattern test_pattern,
5628         enum dp_test_pattern_color_space test_pattern_color_space,
5629         const struct link_training_settings *p_link_settings,
5630         const unsigned char *p_custom_pattern,
5631         unsigned int cust_pattern_size)
5632 {
5633         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
5634         struct pipe_ctx *pipe_ctx = NULL;
5635         unsigned int lane;
5636         unsigned int i;
5637         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
5638         union dpcd_training_pattern training_pattern;
5639         enum dpcd_phy_test_patterns pattern;
5640
5641         memset(&training_pattern, 0, sizeof(training_pattern));
5642
5643         for (i = 0; i < MAX_PIPES; i++) {
5644                 if (pipes[i].stream == NULL)
5645                         continue;
5646
5647                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
5648                         pipe_ctx = &pipes[i];
5649                         break;
5650                 }
5651         }
5652
5653         if (pipe_ctx == NULL)
5654                 return false;
5655
5656         /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
5657         if (link->test_pattern_enabled && test_pattern ==
5658                         DP_TEST_PATTERN_VIDEO_MODE) {
5659                 /* Set CRTC Test Pattern */
5660                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
5661                 dp_set_hw_test_pattern(link, test_pattern,
5662                                 (uint8_t *)p_custom_pattern,
5663                                 (uint32_t)cust_pattern_size);
5664
5665                 /* Unblank Stream */
5666                 link->dc->hwss.unblank_stream(
5667                         pipe_ctx,
5668                         &link->verified_link_cap);
5669                 /* TODO:m_pHwss->MuteAudioEndpoint
5670                  * (pPathMode->pDisplayPath, false);
5671                  */
5672
5673                 /* Reset Test Pattern state */
5674                 link->test_pattern_enabled = false;
5675
5676                 return true;
5677         }
5678
5679         /* Check for PHY Test Patterns */
5680         if (is_dp_phy_pattern(test_pattern)) {
5681                 /* Set DPCD Lane Settings before running test pattern */
5682                 if (p_link_settings != NULL) {
5683                         dp_set_hw_lane_settings(link, p_link_settings, DPRX);
5684                         dpcd_set_lane_settings(link, p_link_settings, DPRX);
5685                 }
5686
5687                 /* Blank stream if running test pattern */
5688                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
5689                         /*TODO:
5690                          * m_pHwss->
5691                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
5692                          */
5693                         /* Blank stream */
5694                         pipes->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
5695                 }
5696
5697                 dp_set_hw_test_pattern(link, test_pattern,
5698                                 (uint8_t *)p_custom_pattern,
5699                                 (uint32_t)cust_pattern_size);
5700
5701                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
5702                         /* Set Test Pattern state */
5703                         link->test_pattern_enabled = true;
5704                         if (p_link_settings != NULL)
5705                                 dpcd_set_link_settings(link,
5706                                                 p_link_settings);
5707                 }
5708
5709                 switch (test_pattern) {
5710                 case DP_TEST_PATTERN_VIDEO_MODE:
5711                         pattern = PHY_TEST_PATTERN_NONE;
5712                         break;
5713                 case DP_TEST_PATTERN_D102:
5714                         pattern = PHY_TEST_PATTERN_D10_2;
5715                         break;
5716                 case DP_TEST_PATTERN_SYMBOL_ERROR:
5717                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
5718                         break;
5719                 case DP_TEST_PATTERN_PRBS7:
5720                         pattern = PHY_TEST_PATTERN_PRBS7;
5721                         break;
5722                 case DP_TEST_PATTERN_80BIT_CUSTOM:
5723                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
5724                         break;
5725                 case DP_TEST_PATTERN_CP2520_1:
5726                         pattern = PHY_TEST_PATTERN_CP2520_1;
5727                         break;
5728                 case DP_TEST_PATTERN_CP2520_2:
5729                         pattern = PHY_TEST_PATTERN_CP2520_2;
5730                         break;
5731                 case DP_TEST_PATTERN_CP2520_3:
5732                         pattern = PHY_TEST_PATTERN_CP2520_3;
5733                         break;
5734 #if defined(CONFIG_DRM_AMD_DC_DCN)
5735                 case DP_TEST_PATTERN_128b_132b_TPS1:
5736                         pattern = PHY_TEST_PATTERN_128b_132b_TPS1;
5737                         break;
5738                 case DP_TEST_PATTERN_128b_132b_TPS2:
5739                         pattern = PHY_TEST_PATTERN_128b_132b_TPS2;
5740                         break;
5741                 case DP_TEST_PATTERN_PRBS9:
5742                         pattern = PHY_TEST_PATTERN_PRBS9;
5743                         break;
5744                 case DP_TEST_PATTERN_PRBS11:
5745                         pattern = PHY_TEST_PATTERN_PRBS11;
5746                         break;
5747                 case DP_TEST_PATTERN_PRBS15:
5748                         pattern = PHY_TEST_PATTERN_PRBS15;
5749                         break;
5750                 case DP_TEST_PATTERN_PRBS23:
5751                         pattern = PHY_TEST_PATTERN_PRBS23;
5752                         break;
5753                 case DP_TEST_PATTERN_PRBS31:
5754                         pattern = PHY_TEST_PATTERN_PRBS31;
5755                         break;
5756                 case DP_TEST_PATTERN_264BIT_CUSTOM:
5757                         pattern = PHY_TEST_PATTERN_264BIT_CUSTOM;
5758                         break;
5759                 case DP_TEST_PATTERN_SQUARE_PULSE:
5760                         pattern = PHY_TEST_PATTERN_SQUARE_PULSE;
5761                         break;
5762 #endif
5763                 default:
5764                         return false;
5765                 }
5766
5767                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
5768                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
5769                         return false;
5770
5771                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
5772 #if defined(CONFIG_DRM_AMD_DC_DCN)
5773                         if (test_pattern == DP_TEST_PATTERN_SQUARE_PULSE)
5774                                 core_link_write_dpcd(link,
5775                                                 DP_LINK_SQUARE_PATTERN,
5776                                                 p_custom_pattern,
5777                                                 1);
5778
5779 #endif
5780                         /* tell receiver that we are sending qualification
5781                          * pattern DP 1.2 or later - DP receiver's link quality
5782                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
5783                          * register (0x10B~0x10E)\
5784                          */
5785                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
5786                                 link_qual_pattern[lane] =
5787                                                 (unsigned char)(pattern);
5788
5789                         core_link_write_dpcd(link,
5790                                         DP_LINK_QUAL_LANE0_SET,
5791                                         link_qual_pattern,
5792                                         sizeof(link_qual_pattern));
5793                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
5794                            link->dpcd_caps.dpcd_rev.raw == 0) {
5795                         /* tell receiver that we are sending qualification
5796                          * pattern DP 1.1a or earlier - DP receiver's link
5797                          * quality pattern is set using
5798                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
5799                          * register (0x102). We will use v_1.3 when we are
5800                          * setting test pattern for DP 1.1.
5801                          */
5802                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
5803                                             &training_pattern.raw,
5804                                             sizeof(training_pattern));
5805                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
5806                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
5807                                              &training_pattern.raw,
5808                                              sizeof(training_pattern));
5809                 }
5810         } else {
5811                 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
5812
5813                 switch (test_pattern_color_space) {
5814                 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
5815                         color_space = COLOR_SPACE_SRGB;
5816                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
5817                                 color_space = COLOR_SPACE_SRGB_LIMITED;
5818                         break;
5819
5820                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
5821                         color_space = COLOR_SPACE_YCBCR601;
5822                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
5823                                 color_space = COLOR_SPACE_YCBCR601_LIMITED;
5824                         break;
5825                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
5826                         color_space = COLOR_SPACE_YCBCR709;
5827                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
5828                                 color_space = COLOR_SPACE_YCBCR709_LIMITED;
5829                         break;
5830                 default:
5831                         break;
5832                 }
5833
5834                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
5835                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
5836                                 union dmub_hw_lock_flags hw_locks = { 0 };
5837                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
5838
5839                                 hw_locks.bits.lock_dig = 1;
5840                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
5841
5842                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
5843                                                         true,
5844                                                         &hw_locks,
5845                                                         &inst_flags);
5846                         } else
5847                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
5848                                                 pipe_ctx->stream_res.tg);
5849                 }
5850
5851                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
5852                 /* update MSA to requested color space */
5853                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
5854                                 &pipe_ctx->stream->timing,
5855                                 color_space,
5856                                 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
5857                                 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
5858
5859                 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
5860                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
5861                                 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
5862                         else
5863                                 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
5864                         resource_build_info_frame(pipe_ctx);
5865                         link->dc->hwss.update_info_frame(pipe_ctx);
5866                 }
5867
5868                 /* CRTC Patterns */
5869                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
5870                 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
5871                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
5872                                 CRTC_STATE_VACTIVE);
5873                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
5874                                 CRTC_STATE_VBLANK);
5875                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
5876                                 CRTC_STATE_VACTIVE);
5877
5878                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
5879                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
5880                                 union dmub_hw_lock_flags hw_locks = { 0 };
5881                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
5882
5883                                 hw_locks.bits.lock_dig = 1;
5884                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
5885
5886                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
5887                                                         false,
5888                                                         &hw_locks,
5889                                                         &inst_flags);
5890                         } else
5891                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
5892                                                 pipe_ctx->stream_res.tg);
5893                 }
5894
5895                 /* Set Test Pattern state */
5896                 link->test_pattern_enabled = true;
5897         }
5898
5899         return true;
5900 }
5901
5902 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
5903 {
5904         unsigned char mstmCntl;
5905
5906         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
5907         if (enable)
5908                 mstmCntl |= DP_MST_EN;
5909         else
5910                 mstmCntl &= (~DP_MST_EN);
5911
5912         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
5913 }
5914
5915 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
5916 {
5917         union dpcd_edp_config edp_config_set;
5918         bool panel_mode_edp = false;
5919
5920         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
5921
5922         if (panel_mode != DP_PANEL_MODE_DEFAULT) {
5923
5924                 switch (panel_mode) {
5925                 case DP_PANEL_MODE_EDP:
5926                 case DP_PANEL_MODE_SPECIAL:
5927                         panel_mode_edp = true;
5928                         break;
5929
5930                 default:
5931                                 break;
5932                 }
5933
5934                 /*set edp panel mode in receiver*/
5935                 core_link_read_dpcd(
5936                         link,
5937                         DP_EDP_CONFIGURATION_SET,
5938                         &edp_config_set.raw,
5939                         sizeof(edp_config_set.raw));
5940
5941                 if (edp_config_set.bits.PANEL_MODE_EDP
5942                         != panel_mode_edp) {
5943                         enum dc_status result;
5944
5945                         edp_config_set.bits.PANEL_MODE_EDP =
5946                         panel_mode_edp;
5947                         result = core_link_write_dpcd(
5948                                 link,
5949                                 DP_EDP_CONFIGURATION_SET,
5950                                 &edp_config_set.raw,
5951                                 sizeof(edp_config_set.raw));
5952
5953                         ASSERT(result == DC_OK);
5954                 }
5955         }
5956         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
5957                  "eDP panel mode enabled: %d \n",
5958                  link->link_index,
5959                  link->dpcd_caps.panel_mode_edp,
5960                  panel_mode_edp);
5961 }
5962
5963 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
5964 {
5965         /* We need to explicitly check that connector
5966          * is not DP. Some Travis_VGA get reported
5967          * by video bios as DP.
5968          */
5969         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
5970
5971                 switch (link->dpcd_caps.branch_dev_id) {
5972                 case DP_BRANCH_DEVICE_ID_0022B9:
5973                         /* alternate scrambler reset is required for Travis
5974                          * for the case when external chip does not
5975                          * provide sink device id, alternate scrambler
5976                          * scheme will  be overriden later by querying
5977                          * Encoder features
5978                          */
5979                         if (strncmp(
5980                                 link->dpcd_caps.branch_dev_name,
5981                                 DP_VGA_LVDS_CONVERTER_ID_2,
5982                                 sizeof(
5983                                 link->dpcd_caps.
5984                                 branch_dev_name)) == 0) {
5985                                         return DP_PANEL_MODE_SPECIAL;
5986                         }
5987                         break;
5988                 case DP_BRANCH_DEVICE_ID_00001A:
5989                         /* alternate scrambler reset is required for Travis
5990                          * for the case when external chip does not provide
5991                          * sink device id, alternate scrambler scheme will
5992                          * be overriden later by querying Encoder feature
5993                          */
5994                         if (strncmp(link->dpcd_caps.branch_dev_name,
5995                                 DP_VGA_LVDS_CONVERTER_ID_3,
5996                                 sizeof(
5997                                 link->dpcd_caps.
5998                                 branch_dev_name)) == 0) {
5999                                         return DP_PANEL_MODE_SPECIAL;
6000                         }
6001                         break;
6002                 default:
6003                         break;
6004                 }
6005         }
6006
6007         if (link->dpcd_caps.panel_mode_edp &&
6008                 (link->connector_signal == SIGNAL_TYPE_EDP ||
6009                  (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
6010                   link->is_internal_display))) {
6011                 return DP_PANEL_MODE_EDP;
6012         }
6013
6014         return DP_PANEL_MODE_DEFAULT;
6015 }
6016
6017 enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
6018 {
6019         /* FEC has to be "set ready" before the link training.
6020          * The policy is to always train with FEC
6021          * if the sink supports it and leave it enabled on link.
6022          * If FEC is not supported, disable it.
6023          */
6024         struct link_encoder *link_enc = NULL;
6025         enum dc_status status = DC_OK;
6026         uint8_t fec_config = 0;
6027
6028         /* Access link encoder based on whether it is statically
6029          * or dynamically assigned to a link.
6030          */
6031         if (link->is_dig_mapping_flexible &&
6032                         link->dc->res_pool->funcs->link_encs_assign)
6033                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
6034         else
6035                 link_enc = link->link_enc;
6036         ASSERT(link_enc);
6037
6038         if (!dc_link_should_enable_fec(link))
6039                 return status;
6040
6041         if (link_enc->funcs->fec_set_ready &&
6042                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
6043                 if (ready) {
6044                         fec_config = 1;
6045                         status = core_link_write_dpcd(link,
6046                                         DP_FEC_CONFIGURATION,
6047                                         &fec_config,
6048                                         sizeof(fec_config));
6049                         if (status == DC_OK) {
6050                                 link_enc->funcs->fec_set_ready(link_enc, true);
6051                                 link->fec_state = dc_link_fec_ready;
6052                         } else {
6053                                 link_enc->funcs->fec_set_ready(link_enc, false);
6054                                 link->fec_state = dc_link_fec_not_ready;
6055                                 dm_error("dpcd write failed to set fec_ready");
6056                         }
6057                 } else if (link->fec_state == dc_link_fec_ready) {
6058                         fec_config = 0;
6059                         status = core_link_write_dpcd(link,
6060                                         DP_FEC_CONFIGURATION,
6061                                         &fec_config,
6062                                         sizeof(fec_config));
6063                         link_enc->funcs->fec_set_ready(link_enc, false);
6064                         link->fec_state = dc_link_fec_not_ready;
6065                 }
6066         }
6067
6068         return status;
6069 }
6070
6071 void dp_set_fec_enable(struct dc_link *link, bool enable)
6072 {
6073         struct link_encoder *link_enc = NULL;
6074
6075         /* Access link encoder based on whether it is statically
6076          * or dynamically assigned to a link.
6077          */
6078         if (link->is_dig_mapping_flexible &&
6079                         link->dc->res_pool->funcs->link_encs_assign)
6080                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
6081         else
6082                 link_enc = link->link_enc;
6083         ASSERT(link_enc);
6084
6085         if (!dc_link_should_enable_fec(link))
6086                 return;
6087
6088         if (link_enc->funcs->fec_set_enable &&
6089                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
6090                 if (link->fec_state == dc_link_fec_ready && enable) {
6091                         /* Accord to DP spec, FEC enable sequence can first
6092                          * be transmitted anytime after 1000 LL codes have
6093                          * been transmitted on the link after link training
6094                          * completion. Using 1 lane RBR should have the maximum
6095                          * time for transmitting 1000 LL codes which is 6.173 us.
6096                          * So use 7 microseconds delay instead.
6097                          */
6098                         udelay(7);
6099                         link_enc->funcs->fec_set_enable(link_enc, true);
6100                         link->fec_state = dc_link_fec_enabled;
6101                 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
6102                         link_enc->funcs->fec_set_enable(link_enc, false);
6103                         link->fec_state = dc_link_fec_ready;
6104                 }
6105         }
6106 }
6107
6108 void dpcd_set_source_specific_data(struct dc_link *link)
6109 {
6110         if (!link->dc->vendor_signature.is_valid) {
6111                 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
6112                 struct dpcd_amd_signature amd_signature = {0};
6113                 struct dpcd_amd_device_id amd_device_id = {0};
6114
6115                 amd_device_id.device_id_byte1 =
6116                                 (uint8_t)(link->ctx->asic_id.chip_id);
6117                 amd_device_id.device_id_byte2 =
6118                                 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
6119                 amd_device_id.dce_version =
6120                                 (uint8_t)(link->ctx->dce_version);
6121                 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
6122                 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
6123
6124                 core_link_read_dpcd(link, DP_SOURCE_OUI,
6125                                 (uint8_t *)(&amd_signature),
6126                                 sizeof(amd_signature));
6127
6128                 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
6129                         (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
6130                         (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
6131
6132                         amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
6133                         amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
6134                         amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
6135
6136                         core_link_write_dpcd(link, DP_SOURCE_OUI,
6137                                 (uint8_t *)(&amd_signature),
6138                                 sizeof(amd_signature));
6139                 }
6140
6141                 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
6142                                 (uint8_t *)(&amd_device_id),
6143                                 sizeof(amd_device_id));
6144
6145                 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
6146                         link->dc->caps.min_horizontal_blanking_period != 0) {
6147
6148                         uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
6149
6150                         if (link->preferred_link_setting.dpcd_source_device_specific_field_support) {
6151                                 result_write_min_hblank = core_link_write_dpcd(link,
6152                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
6153                                         sizeof(hblank_size));
6154
6155                                 if (result_write_min_hblank == DC_ERROR_UNEXPECTED)
6156                                         link->preferred_link_setting.dpcd_source_device_specific_field_support = false;
6157                         } else {
6158                                 DC_LOG_DC("Sink device does not support 00340h DPCD write. Skipping on purpose.\n");
6159                         }
6160                 }
6161
6162                 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
6163                                                         WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
6164                                                         "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
6165                                                         result_write_min_hblank,
6166                                                         link->link_index,
6167                                                         link->ctx->dce_version,
6168                                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
6169                                                         link->dc->caps.min_horizontal_blanking_period,
6170                                                         link->dpcd_caps.branch_dev_id,
6171                                                         link->dpcd_caps.branch_dev_name[0],
6172                                                         link->dpcd_caps.branch_dev_name[1],
6173                                                         link->dpcd_caps.branch_dev_name[2],
6174                                                         link->dpcd_caps.branch_dev_name[3],
6175                                                         link->dpcd_caps.branch_dev_name[4],
6176                                                         link->dpcd_caps.branch_dev_name[5]);
6177         } else {
6178                 core_link_write_dpcd(link, DP_SOURCE_OUI,
6179                                 link->dc->vendor_signature.data.raw,
6180                                 sizeof(link->dc->vendor_signature.data.raw));
6181         }
6182 }
6183
6184 bool dc_link_set_backlight_level_nits(struct dc_link *link,
6185                 bool isHDR,
6186                 uint32_t backlight_millinits,
6187                 uint32_t transition_time_in_ms)
6188 {
6189         struct dpcd_source_backlight_set dpcd_backlight_set;
6190         uint8_t backlight_control = isHDR ? 1 : 0;
6191
6192         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
6193                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
6194                 return false;
6195
6196         // OLEDs have no PWM, they can only use AUX
6197         if (link->dpcd_sink_ext_caps.bits.oled == 1)
6198                 backlight_control = 1;
6199
6200         *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
6201         *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
6202
6203
6204         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
6205                         (uint8_t *)(&dpcd_backlight_set),
6206                         sizeof(dpcd_backlight_set)) != DC_OK)
6207                 return false;
6208
6209         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
6210                         &backlight_control, 1) != DC_OK)
6211                 return false;
6212
6213         return true;
6214 }
6215
6216 bool dc_link_get_backlight_level_nits(struct dc_link *link,
6217                 uint32_t *backlight_millinits_avg,
6218                 uint32_t *backlight_millinits_peak)
6219 {
6220         union dpcd_source_backlight_get dpcd_backlight_get;
6221
6222         memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
6223
6224         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
6225                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
6226                 return false;
6227
6228         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
6229                         dpcd_backlight_get.raw,
6230                         sizeof(union dpcd_source_backlight_get)) != DC_OK)
6231                 return false;
6232
6233         *backlight_millinits_avg =
6234                 dpcd_backlight_get.bytes.backlight_millinits_avg;
6235         *backlight_millinits_peak =
6236                 dpcd_backlight_get.bytes.backlight_millinits_peak;
6237
6238         /* On non-supported panels dpcd_read usually succeeds with 0 returned */
6239         if (*backlight_millinits_avg == 0 ||
6240                         *backlight_millinits_avg > *backlight_millinits_peak)
6241                 return false;
6242
6243         return true;
6244 }
6245
6246 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
6247 {
6248         uint8_t backlight_enable = enable ? 1 : 0;
6249
6250         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
6251                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
6252                 return false;
6253
6254         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
6255                 &backlight_enable, 1) != DC_OK)
6256                 return false;
6257
6258         return true;
6259 }
6260
6261 // we read default from 0x320 because we expect BIOS wrote it there
6262 // regular get_backlight_nit reads from panel set at 0x326
6263 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
6264 {
6265         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
6266                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
6267                 return false;
6268
6269         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
6270                 (uint8_t *) backlight_millinits,
6271                 sizeof(uint32_t)) != DC_OK)
6272                 return false;
6273
6274         return true;
6275 }
6276
6277 bool dc_link_set_default_brightness_aux(struct dc_link *link)
6278 {
6279         uint32_t default_backlight;
6280
6281         if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {
6282                 if (!dc_link_read_default_bl_aux(link, &default_backlight))
6283                         default_backlight = 150000;
6284                 // if < 5 nits or > 5000, it might be wrong readback
6285                 if (default_backlight < 5000 || default_backlight > 5000000)
6286                         default_backlight = 150000; //
6287
6288                 return dc_link_set_backlight_level_nits(link, true,
6289                                 default_backlight, 0);
6290         }
6291         return false;
6292 }
6293
6294 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
6295 {
6296         struct dc_link_settings link_setting;
6297         uint8_t link_bw_set;
6298         uint8_t link_rate_set;
6299         uint32_t req_bw;
6300         union lane_count_set lane_count_set = {0};
6301
6302         ASSERT(link || crtc_timing); // invalid input
6303
6304         if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
6305                         !link->dc->debug.optimize_edp_link_rate)
6306                 return false;
6307
6308
6309         // Read DPCD 00100h to find if standard link rates are set
6310         core_link_read_dpcd(link, DP_LINK_BW_SET,
6311                                 &link_bw_set, sizeof(link_bw_set));
6312
6313         if (link_bw_set) {
6314                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
6315                 return true;
6316         }
6317
6318         // Read DPCD 00115h to find the edp link rate set used
6319         core_link_read_dpcd(link, DP_LINK_RATE_SET,
6320                             &link_rate_set, sizeof(link_rate_set));
6321
6322         // Read DPCD 00101h to find out the number of lanes currently set
6323         core_link_read_dpcd(link, DP_LANE_COUNT_SET,
6324                                 &lane_count_set.raw, sizeof(lane_count_set));
6325
6326         req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
6327
6328         if (!crtc_timing->flags.DSC)
6329                 decide_edp_link_settings(link, &link_setting, req_bw);
6330         else
6331                 decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN);
6332
6333         if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
6334                         lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
6335                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
6336                 return true;
6337         }
6338
6339         DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
6340         return false;
6341 }
6342
6343 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
6344 {
6345         if ((link_settings->link_rate >= LINK_RATE_LOW) &&
6346                         (link_settings->link_rate <= LINK_RATE_HIGH3))
6347                 return DP_8b_10b_ENCODING;
6348 #if defined(CONFIG_DRM_AMD_DC_DCN)
6349         else if ((link_settings->link_rate >= LINK_RATE_UHBR10) &&
6350                         (link_settings->link_rate <= LINK_RATE_UHBR20))
6351                 return DP_128b_132b_ENCODING;
6352 #endif
6353         return DP_UNKNOWN_ENCODING;
6354 }
6355
6356 #if defined(CONFIG_DRM_AMD_DC_DCN)
6357 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(const struct dc_link *link)
6358 {
6359         struct dc_link_settings link_settings = {0};
6360
6361         if (!dc_is_dp_signal(link->connector_signal))
6362                 return DP_UNKNOWN_ENCODING;
6363
6364         if (link->preferred_link_setting.lane_count !=
6365                         LANE_COUNT_UNKNOWN &&
6366                         link->preferred_link_setting.link_rate !=
6367                                         LINK_RATE_UNKNOWN) {
6368                 link_settings = link->preferred_link_setting;
6369         } else {
6370                 decide_mst_link_settings(link, &link_settings);
6371         }
6372
6373         return dp_get_link_encoding_format(&link_settings);
6374 }
6375
6376 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST)
6377 static void get_lane_status(
6378         struct dc_link *link,
6379         uint32_t lane_count,
6380         union lane_status *status,
6381         union lane_align_status_updated *status_updated)
6382 {
6383         unsigned int lane;
6384         uint8_t dpcd_buf[3] = {0};
6385
6386         if (status == NULL || status_updated == NULL) {
6387                 return;
6388         }
6389
6390         core_link_read_dpcd(
6391                         link,
6392                         DP_LANE0_1_STATUS,
6393                         dpcd_buf,
6394                         sizeof(dpcd_buf));
6395
6396         for (lane = 0; lane < lane_count; lane++) {
6397                 status[lane].raw = get_nibble_at_index(&dpcd_buf[0], lane);
6398         }
6399
6400         status_updated->raw = dpcd_buf[2];
6401 }
6402
6403 bool dpcd_write_128b_132b_sst_payload_allocation_table(
6404                 const struct dc_stream_state *stream,
6405                 struct dc_link *link,
6406                 struct link_mst_stream_allocation_table *proposed_table,
6407                 bool allocate)
6408 {
6409         const uint8_t vc_id = 1; /// VC ID always 1 for SST
6410         const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST
6411         bool result = false;
6412         uint8_t req_slot_count = 0;
6413         struct fixed31_32 avg_time_slots_per_mtp = { 0 };
6414         union payload_table_update_status update_status = { 0 };
6415         const uint32_t max_retries = 30;
6416         uint32_t retries = 0;
6417
6418         if (allocate)   {
6419                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
6420                 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
6421         } else {
6422                 /// Leave req_slot_count = 0 if allocate is false.
6423         }
6424
6425         /// Write DPCD 2C0 = 1 to start updating
6426         update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1;
6427         core_link_write_dpcd(
6428                         link,
6429                         DP_PAYLOAD_TABLE_UPDATE_STATUS,
6430                         &update_status.raw,
6431                         1);
6432
6433         /// Program the changes in DPCD 1C0 - 1C2
6434         ASSERT(vc_id == 1);
6435         core_link_write_dpcd(
6436                         link,
6437                         DP_PAYLOAD_ALLOCATE_SET,
6438                         &vc_id,
6439                         1);
6440
6441         ASSERT(start_time_slot == 0);
6442         core_link_write_dpcd(
6443                         link,
6444                         DP_PAYLOAD_ALLOCATE_START_TIME_SLOT,
6445                         &start_time_slot,
6446                         1);
6447
6448         ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); /// Validation should filter out modes that exceed link BW
6449         core_link_write_dpcd(
6450                         link,
6451                         DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT,
6452                         &req_slot_count,
6453                         1);
6454
6455         /// Poll till DPCD 2C0 read 1
6456         /// Try for at least 150ms (30 retries, with 5ms delay after each attempt)
6457
6458         while (retries < max_retries) {
6459                 if (core_link_read_dpcd(
6460                                 link,
6461                                 DP_PAYLOAD_TABLE_UPDATE_STATUS,
6462                                 &update_status.raw,
6463                                 1) == DC_OK) {
6464                         if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) {
6465                                 DC_LOG_DP2("SST Update Payload: downstream payload table updated.");
6466                                 result = true;
6467                                 break;
6468                         }
6469                 } else {
6470                         union dpcd_rev dpcdRev;
6471
6472                         if (core_link_read_dpcd(
6473                                         link,
6474                                         DP_DPCD_REV,
6475                                         &dpcdRev.raw,
6476                                         1) != DC_OK) {
6477                                 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision "
6478                                                 "of sink while polling payload table "
6479                                                 "updated status bit.");
6480                                 break;
6481                         }
6482                 }
6483                 retries++;
6484                 udelay(5000);
6485         }
6486
6487         if (!result && retries == max_retries) {
6488                 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, "
6489                                 "continue on. Something is wrong with the branch.");
6490                 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch
6491         }
6492
6493         proposed_table->stream_count = 1; /// Always 1 stream for SST
6494         proposed_table->stream_allocations[0].slot_count = req_slot_count;
6495         proposed_table->stream_allocations[0].vcp_id = vc_id;
6496
6497         return result;
6498 }
6499
6500 bool dpcd_poll_for_allocation_change_trigger(struct dc_link *link)
6501 {
6502         /*
6503          * wait for ACT handled
6504          */
6505         int i;
6506         const int act_retries = 30;
6507         enum act_return_status result = ACT_FAILED;
6508         union payload_table_update_status update_status = {0};
6509         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
6510         union lane_align_status_updated lane_status_updated;
6511
6512         for (i = 0; i < act_retries; i++) {
6513                 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated);
6514
6515                 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) ||
6516                                 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) ||
6517                                 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) ||
6518                                 !dp_is_interlane_aligned(lane_status_updated)) {
6519                         DC_LOG_ERROR("SST Update Payload: Link loss occurred while "
6520                                         "polling for ACT handled.");
6521                         result = ACT_LINK_LOST;
6522                         break;
6523                 }
6524                 core_link_read_dpcd(
6525                                 link,
6526                                 DP_PAYLOAD_TABLE_UPDATE_STATUS,
6527                                 &update_status.raw,
6528                                 1);
6529
6530                 if (update_status.bits.ACT_HANDLED == 1) {
6531                         DC_LOG_DP2("SST Update Payload: ACT handled by downstream.");
6532                         result = ACT_SUCCESS;
6533                         break;
6534                 }
6535
6536                 udelay(5000);
6537         }
6538
6539         if (result == ACT_FAILED) {
6540                 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, "
6541                                 "continue on. Something is wrong with the branch.");
6542         }
6543
6544         return (result == ACT_SUCCESS);
6545 }
6546
6547 struct fixed31_32 calculate_sst_avg_time_slots_per_mtp(
6548                 const struct dc_stream_state *stream,
6549                 const struct dc_link *link)
6550 {
6551         struct fixed31_32 link_bw_effective =
6552                         dc_fixpt_from_int(
6553                                         dc_link_bandwidth_kbps(link, &link->cur_link_settings));
6554         struct fixed31_32 timeslot_bw_effective =
6555                         dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT);
6556         struct fixed31_32 timing_bw =
6557                         dc_fixpt_from_int(
6558                                         dc_bandwidth_in_kbps_from_timing(&stream->timing));
6559         struct fixed31_32 avg_time_slots_per_mtp =
6560                         dc_fixpt_div(timing_bw, timeslot_bw_effective);
6561
6562         return avg_time_slots_per_mtp;
6563 }
6564
6565 bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx)
6566 {
6567         return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
6568                         pipe_ctx->stream->link->hpo_dp_link_enc &&
6569                         dc_is_dp_signal(pipe_ctx->stream->signal));
6570 }
6571 #endif
6572
6573 void edp_panel_backlight_power_on(struct dc_link *link)
6574 {
6575         if (link->connector_signal != SIGNAL_TYPE_EDP)
6576                 return;
6577
6578         link->dc->hwss.edp_power_control(link, true);
6579         link->dc->hwss.edp_wait_for_hpd_ready(link, true);
6580         if (link->dc->hwss.edp_backlight_control)
6581                 link->dc->hwss.edp_backlight_control(link, true);
6582 }