1 /* Copyright 2015 Advanced Micro Devices, Inc. */
2 #include "dm_services.h"
4 #include "dc_link_dp.h"
5 #include "dm_helpers.h"
10 #include "inc/core_types.h"
11 #include "link_hwss.h"
12 #include "dc_link_ddc.h"
13 #include "core_status.h"
14 #include "dpcd_defs.h"
15 #include "dc_dmub_srv.h"
16 #include "dce/dmub_hw_lock_mgr.h"
17 #include "inc/link_enc_cfg.h"
20 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
22 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
26 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
28 #include "link_dpcd.h"
30 /* maximum pre emphasis level allowed for each voltage swing level*/
31 static const enum dc_pre_emphasis
32 voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
35 PRE_EMPHASIS_DISABLED };
38 POST_LT_ADJ_REQ_LIMIT = 6,
39 POST_LT_ADJ_REQ_TIMEOUT = 200
42 static bool decide_fallback_link_setting(
43 struct dc_link_settings initial_link_settings,
44 struct dc_link_settings *current_link_setting,
45 enum link_training_result training_result);
46 static struct dc_link_settings get_common_supported_link_settings(
47 struct dc_link_settings link_setting_a,
48 struct dc_link_settings link_setting_b);
50 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
51 const struct dc_link_settings *link_settings)
53 union training_aux_rd_interval training_rd_interval;
54 uint32_t wait_in_micro_secs = 100;
56 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
59 DP_TRAINING_AUX_RD_INTERVAL,
60 (uint8_t *)&training_rd_interval,
61 sizeof(training_rd_interval));
62 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
63 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
64 return wait_in_micro_secs;
67 static uint32_t get_eq_training_aux_rd_interval(
69 const struct dc_link_settings *link_settings)
71 union training_aux_rd_interval training_rd_interval;
72 uint32_t wait_in_micro_secs = 400;
74 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
75 /* overwrite the delay if rev > 1.1*/
76 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
77 /* DP 1.2 or later - retrieve delay through
78 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
81 DP_TRAINING_AUX_RD_INTERVAL,
82 (uint8_t *)&training_rd_interval,
83 sizeof(training_rd_interval));
85 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
86 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
89 return wait_in_micro_secs;
92 void dp_wait_for_training_aux_rd_interval(
94 uint32_t wait_in_micro_secs)
96 udelay(wait_in_micro_secs);
98 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
103 enum dpcd_training_patterns
104 dc_dp_training_pattern_to_dpcd_training_pattern(
105 struct dc_link *link,
106 enum dc_dp_training_pattern pattern)
108 enum dpcd_training_patterns dpcd_tr_pattern =
109 DPCD_TRAINING_PATTERN_VIDEOIDLE;
112 case DP_TRAINING_PATTERN_SEQUENCE_1:
113 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
115 case DP_TRAINING_PATTERN_SEQUENCE_2:
116 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
118 case DP_TRAINING_PATTERN_SEQUENCE_3:
119 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
121 case DP_TRAINING_PATTERN_SEQUENCE_4:
122 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
124 case DP_TRAINING_PATTERN_VIDEOIDLE:
125 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
129 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
134 return dpcd_tr_pattern;
137 static void dpcd_set_training_pattern(
138 struct dc_link *link,
139 enum dc_dp_training_pattern training_pattern)
141 union dpcd_training_pattern dpcd_pattern = { {0} };
143 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
144 dc_dp_training_pattern_to_dpcd_training_pattern(
145 link, training_pattern);
147 core_link_write_dpcd(
149 DP_TRAINING_PATTERN_SET,
153 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
155 DP_TRAINING_PATTERN_SET,
156 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
159 static enum dc_dp_training_pattern decide_cr_training_pattern(
160 const struct dc_link_settings *link_settings)
162 return DP_TRAINING_PATTERN_SEQUENCE_1;
165 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
166 const struct dc_link_settings *link_settings)
168 struct link_encoder *link_enc;
169 enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
170 struct encoder_feature_support *features;
171 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
173 /* Access link encoder capability based on whether it is statically
174 * or dynamically assigned to a link.
176 if (link->is_dig_mapping_flexible &&
177 link->dc->res_pool->funcs->link_encs_assign)
178 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
180 link_enc = link->link_enc;
182 features = &link_enc->features;
184 if (features->flags.bits.IS_TPS3_CAPABLE)
185 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
187 if (features->flags.bits.IS_TPS4_CAPABLE)
188 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
190 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
191 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
192 return DP_TRAINING_PATTERN_SEQUENCE_4;
194 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
195 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
196 return DP_TRAINING_PATTERN_SEQUENCE_3;
198 return DP_TRAINING_PATTERN_SEQUENCE_2;
201 enum dc_status dpcd_set_link_settings(
202 struct dc_link *link,
203 const struct link_training_settings *lt_settings)
206 enum dc_status status;
208 union down_spread_ctrl downspread = { {0} };
209 union lane_count_set lane_count_set = { {0} };
211 downspread.raw = (uint8_t)
212 (lt_settings->link_settings.link_spread);
214 lane_count_set.bits.LANE_COUNT_SET =
215 lt_settings->link_settings.lane_count;
217 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
218 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
221 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
222 lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
223 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
224 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
227 status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
228 &downspread.raw, sizeof(downspread));
230 status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
231 &lane_count_set.raw, 1);
233 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
234 lt_settings->link_settings.use_link_rate_set == true) {
236 /* WA for some MUX chips that will power down with eDP and lose supported
237 * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
238 * MUX chip gets link rate set back before link training.
240 if (link->connector_signal == SIGNAL_TYPE_EDP) {
241 uint8_t supported_link_rates[16];
243 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
244 supported_link_rates, sizeof(supported_link_rates));
246 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
247 status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
248 <_settings->link_settings.link_rate_set, 1);
250 rate = (uint8_t) (lt_settings->link_settings.link_rate);
251 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
255 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
258 lt_settings->link_settings.link_rate,
260 lt_settings->link_settings.lane_count,
261 lt_settings->enhanced_framing,
263 lt_settings->link_settings.link_spread);
265 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
268 lt_settings->link_settings.link_rate_set,
270 lt_settings->link_settings.lane_count,
271 lt_settings->enhanced_framing,
273 lt_settings->link_settings.link_spread);
279 uint8_t dc_dp_initialize_scrambling_data_symbols(
280 struct dc_link *link,
281 enum dc_dp_training_pattern pattern)
283 uint8_t disable_scrabled_data_symbols = 0;
286 case DP_TRAINING_PATTERN_SEQUENCE_1:
287 case DP_TRAINING_PATTERN_SEQUENCE_2:
288 case DP_TRAINING_PATTERN_SEQUENCE_3:
289 disable_scrabled_data_symbols = 1;
291 case DP_TRAINING_PATTERN_SEQUENCE_4:
292 disable_scrabled_data_symbols = 0;
296 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
300 return disable_scrabled_data_symbols;
303 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
305 return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
308 static void dpcd_set_lt_pattern_and_lane_settings(
309 struct dc_link *link,
310 const struct link_training_settings *lt_settings,
311 enum dc_dp_training_pattern pattern,
314 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
316 uint32_t dpcd_base_lt_offset;
318 uint8_t dpcd_lt_buffer[5] = {0};
319 union dpcd_training_pattern dpcd_pattern = { {0} };
321 uint32_t size_in_bytes;
322 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
323 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
325 if (is_repeater(link, offset))
326 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
327 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
329 /*****************************************************************
330 * DpcdAddress_TrainingPatternSet
331 *****************************************************************/
332 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
333 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
335 dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
336 dc_dp_initialize_scrambling_data_symbols(link, pattern);
338 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
341 if (is_repeater(link, offset)) {
342 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
346 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
348 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
351 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
353 /*****************************************************************
354 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
355 *****************************************************************/
356 for (lane = 0; lane <
357 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
359 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
360 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
361 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
362 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
364 dpcd_lane[lane].bits.MAX_SWING_REACHED =
365 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
366 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
367 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
368 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
369 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
372 /* concatenate everything into one buffer*/
374 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
378 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
382 if (is_repeater(link, offset)) {
383 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
384 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
388 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
389 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
390 dpcd_lane[0].bits.MAX_SWING_REACHED,
391 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
393 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
396 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
397 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
398 dpcd_lane[0].bits.MAX_SWING_REACHED,
399 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
401 if (edp_workaround) {
402 /* for eDP write in 2 parts because the 5-byte burst is
403 * causing issues on some eDP panels (EPR#366724)
405 core_link_write_dpcd(
407 DP_TRAINING_PATTERN_SET,
409 sizeof(dpcd_pattern.raw));
411 core_link_write_dpcd(
413 DP_TRAINING_LANE0_SET,
414 (uint8_t *)(dpcd_lane),
418 /* write it all in (1 + number-of-lanes)-byte burst*/
419 core_link_write_dpcd(
423 size_in_bytes + sizeof(dpcd_pattern.raw));
425 link->cur_lane_setting = lt_settings->lane_settings[0];
428 bool dp_is_cr_done(enum dc_lane_count ln_count,
429 union lane_status *dpcd_lane_status)
432 /*LANEx_CR_DONE bits All 1's?*/
433 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
434 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
440 bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
441 union lane_status *dpcd_lane_status)
445 for (lane = 0; lane < (uint32_t)(ln_count); lane++)
446 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
451 bool dp_is_symbol_locked(enum dc_lane_count ln_count,
452 union lane_status *dpcd_lane_status)
456 for (lane = 0; lane < (uint32_t)(ln_count); lane++)
457 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
462 bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
464 return align_status.bits.INTERLANE_ALIGN_DONE == 1;
467 void dp_update_drive_settings(
468 struct link_training_settings *dest,
469 struct link_training_settings src)
472 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
473 if (dest->voltage_swing == NULL)
474 dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
476 dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
478 if (dest->pre_emphasis == NULL)
479 dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
481 dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
483 if (dest->post_cursor2 == NULL)
484 dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
486 dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
490 static uint8_t get_nibble_at_index(const uint8_t *buf,
494 nibble = buf[index / 2];
504 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
505 enum dc_voltage_swing voltage)
507 enum dc_pre_emphasis pre_emphasis;
508 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
510 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
511 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
517 static void find_max_drive_settings(
518 const struct link_training_settings *link_training_setting,
519 struct link_training_settings *max_lt_setting)
522 struct dc_lane_settings max_requested;
524 max_requested.VOLTAGE_SWING =
525 link_training_setting->
526 lane_settings[0].VOLTAGE_SWING;
527 max_requested.PRE_EMPHASIS =
528 link_training_setting->
529 lane_settings[0].PRE_EMPHASIS;
530 /*max_requested.postCursor2 =
531 * link_training_setting->laneSettings[0].postCursor2;*/
533 /* Determine what the maximum of the requested settings are*/
534 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
536 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
537 max_requested.VOLTAGE_SWING)
539 max_requested.VOLTAGE_SWING =
540 link_training_setting->
541 lane_settings[lane].VOLTAGE_SWING;
543 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
544 max_requested.PRE_EMPHASIS)
545 max_requested.PRE_EMPHASIS =
546 link_training_setting->
547 lane_settings[lane].PRE_EMPHASIS;
550 if (link_training_setting->laneSettings[lane].postCursor2 >
551 max_requested.postCursor2)
553 max_requested.postCursor2 =
554 link_training_setting->laneSettings[lane].postCursor2;
559 /* make sure the requested settings are
560 * not higher than maximum settings*/
561 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
562 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
564 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
565 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
567 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
568 max_requested.postCursor2 = PostCursor2_MaxLevel;
571 /* make sure the pre-emphasis matches the voltage swing*/
572 if (max_requested.PRE_EMPHASIS >
573 get_max_pre_emphasis_for_voltage_swing(
574 max_requested.VOLTAGE_SWING))
575 max_requested.PRE_EMPHASIS =
576 get_max_pre_emphasis_for_voltage_swing(
577 max_requested.VOLTAGE_SWING);
580 * Post Cursor2 levels are completely independent from
581 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
582 * can only be applied to each allowable combination of voltage
583 * swing and pre-emphasis levels */
584 /* if ( max_requested.postCursor2 >
585 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
586 * max_requested.postCursor2 =
587 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
590 max_lt_setting->link_settings.link_rate =
591 link_training_setting->link_settings.link_rate;
592 max_lt_setting->link_settings.lane_count =
593 link_training_setting->link_settings.lane_count;
594 max_lt_setting->link_settings.link_spread =
595 link_training_setting->link_settings.link_spread;
597 for (lane = 0; lane <
598 link_training_setting->link_settings.lane_count;
600 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
601 max_requested.VOLTAGE_SWING;
602 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
603 max_requested.PRE_EMPHASIS;
604 /*max_lt_setting->laneSettings[lane].postCursor2 =
605 * max_requested.postCursor2;
611 enum dc_status dp_get_lane_status_and_drive_settings(
612 struct dc_link *link,
613 const struct link_training_settings *link_training_setting,
614 union lane_status *ln_status,
615 union lane_align_status_updated *ln_status_updated,
616 struct link_training_settings *req_settings,
619 unsigned int lane01_status_address = DP_LANE0_1_STATUS;
620 uint8_t lane_adjust_offset = 4;
621 unsigned int lane01_adjust_address;
622 uint8_t dpcd_buf[6] = {0};
623 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
624 struct link_training_settings request_settings = { {0} };
626 enum dc_status status;
628 memset(req_settings, '\0', sizeof(struct link_training_settings));
630 if (is_repeater(link, offset)) {
631 lane01_status_address =
632 DP_LANE0_1_STATUS_PHY_REPEATER1 +
633 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
634 lane_adjust_offset = 3;
637 status = core_link_read_dpcd(
639 lane01_status_address,
640 (uint8_t *)(dpcd_buf),
643 for (lane = 0; lane <
644 (uint32_t)(link_training_setting->link_settings.lane_count);
647 ln_status[lane].raw =
648 get_nibble_at_index(&dpcd_buf[0], lane);
649 dpcd_lane_adjust[lane].raw =
650 get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
653 ln_status_updated->raw = dpcd_buf[2];
655 if (is_repeater(link, offset)) {
656 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
657 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
660 lane01_status_address, dpcd_buf[0],
661 lane01_status_address + 1, dpcd_buf[1]);
663 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
665 lane01_status_address, dpcd_buf[0],
666 lane01_status_address + 1, dpcd_buf[1]);
668 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
670 if (is_repeater(link, offset))
671 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
672 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
674 if (is_repeater(link, offset)) {
675 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
676 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
679 lane01_adjust_address,
680 dpcd_buf[lane_adjust_offset],
681 lane01_adjust_address + 1,
682 dpcd_buf[lane_adjust_offset + 1]);
684 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
686 lane01_adjust_address,
687 dpcd_buf[lane_adjust_offset],
688 lane01_adjust_address + 1,
689 dpcd_buf[lane_adjust_offset + 1]);
692 /*copy to req_settings*/
693 request_settings.link_settings.lane_count =
694 link_training_setting->link_settings.lane_count;
695 request_settings.link_settings.link_rate =
696 link_training_setting->link_settings.link_rate;
697 request_settings.link_settings.link_spread =
698 link_training_setting->link_settings.link_spread;
700 for (lane = 0; lane <
701 (uint32_t)(link_training_setting->link_settings.lane_count);
704 request_settings.lane_settings[lane].VOLTAGE_SWING =
705 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
707 request_settings.lane_settings[lane].PRE_EMPHASIS =
708 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
712 /*Note: for postcursor2, read adjusted
713 * postcursor2 settings from*/
714 /*DpcdAddress_AdjustRequestPostCursor2 =
715 *0x020C (not implemented yet)*/
717 /* we find the maximum of the requested settings across all lanes*/
718 /* and set this maximum for all lanes*/
719 find_max_drive_settings(&request_settings, req_settings);
721 /* if post cursor 2 is needed in the future,
722 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
728 enum dc_status dpcd_set_lane_settings(
729 struct dc_link *link,
730 const struct link_training_settings *link_training_setting,
733 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
735 unsigned int lane0_set_address;
736 enum dc_status status;
738 lane0_set_address = DP_TRAINING_LANE0_SET;
740 if (is_repeater(link, offset))
741 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
742 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
744 for (lane = 0; lane <
745 (uint32_t)(link_training_setting->
746 link_settings.lane_count);
748 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
749 (uint8_t)(link_training_setting->
750 lane_settings[lane].VOLTAGE_SWING);
751 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
752 (uint8_t)(link_training_setting->
753 lane_settings[lane].PRE_EMPHASIS);
754 dpcd_lane[lane].bits.MAX_SWING_REACHED =
755 (link_training_setting->
756 lane_settings[lane].VOLTAGE_SWING ==
757 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
758 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
759 (link_training_setting->
760 lane_settings[lane].PRE_EMPHASIS ==
761 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
764 status = core_link_write_dpcd(link,
766 (uint8_t *)(dpcd_lane),
767 link_training_setting->link_settings.lane_count);
770 if (LTSettings.link.rate == LinkRate_High2)
772 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
773 for ( uint32_t lane = 0;
774 lane < lane_count_DPMax; lane++)
776 dpcd_lane2[lane].bits.post_cursor2_set =
777 static_cast<unsigned char>(
778 LTSettings.laneSettings[lane].postCursor2);
779 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
781 m_pDpcdAccessSrv->WriteDpcdData(
782 DpcdAddress_Lane0Set2,
783 reinterpret_cast<unsigned char*>(dpcd_lane2),
784 LTSettings.link.lanes);
788 if (is_repeater(link, offset)) {
789 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
790 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
794 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
795 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
796 dpcd_lane[0].bits.MAX_SWING_REACHED,
797 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
800 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
803 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
804 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
805 dpcd_lane[0].bits.MAX_SWING_REACHED,
806 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
808 link->cur_lane_setting = link_training_setting->lane_settings[0];
813 bool dp_is_max_vs_reached(
814 const struct link_training_settings *lt_settings)
817 for (lane = 0; lane <
818 (uint32_t)(lt_settings->link_settings.lane_count);
820 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
821 == VOLTAGE_SWING_MAX_LEVEL)
828 static bool perform_post_lt_adj_req_sequence(
829 struct dc_link *link,
830 struct link_training_settings *lt_settings)
832 enum dc_lane_count lane_count =
833 lt_settings->link_settings.lane_count;
835 uint32_t adj_req_count;
836 uint32_t adj_req_timer;
837 bool req_drv_setting_changed;
840 req_drv_setting_changed = false;
841 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
844 req_drv_setting_changed = false;
846 for (adj_req_timer = 0;
847 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
850 struct link_training_settings req_settings;
851 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
852 union lane_align_status_updated
853 dpcd_lane_status_updated;
855 dp_get_lane_status_and_drive_settings(
859 &dpcd_lane_status_updated,
863 if (dpcd_lane_status_updated.bits.
864 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
867 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
870 if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
871 !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
872 !dp_is_interlane_aligned(dpcd_lane_status_updated))
875 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
878 lane_settings[lane].VOLTAGE_SWING !=
879 req_settings.lane_settings[lane].
881 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
882 req_settings.lane_settings[lane].PRE_EMPHASIS) {
884 req_drv_setting_changed = true;
889 if (req_drv_setting_changed) {
890 dp_update_drive_settings(
891 lt_settings, req_settings);
893 dc_link_dp_set_drive_settings(link,
901 if (!req_drv_setting_changed) {
902 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
909 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
917 /* Only used for channel equalization */
918 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
920 unsigned int aux_rd_interval_us = 400;
922 switch (dpcd_aux_read_interval) {
924 aux_rd_interval_us = 4000;
927 aux_rd_interval_us = 8000;
930 aux_rd_interval_us = 12000;
933 aux_rd_interval_us = 16000;
939 return aux_rd_interval_us;
942 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
943 union lane_status *dpcd_lane_status)
945 enum link_training_result result = LINK_TRAINING_SUCCESS;
947 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
948 result = LINK_TRAINING_CR_FAIL_LANE0;
949 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
950 result = LINK_TRAINING_CR_FAIL_LANE1;
951 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
952 result = LINK_TRAINING_CR_FAIL_LANE23;
953 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
954 result = LINK_TRAINING_CR_FAIL_LANE23;
958 static enum link_training_result perform_channel_equalization_sequence(
959 struct dc_link *link,
960 struct link_training_settings *lt_settings,
963 struct link_training_settings req_settings;
964 enum dc_dp_training_pattern tr_pattern;
965 uint32_t retries_ch_eq;
966 uint32_t wait_time_microsec;
967 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
968 union lane_align_status_updated dpcd_lane_status_updated = { {0} };
969 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
971 /* Note: also check that TPS4 is a supported feature*/
973 tr_pattern = lt_settings->pattern_for_eq;
975 if (is_repeater(link, offset))
976 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
978 dp_set_hw_training_pattern(link, tr_pattern, offset);
980 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
983 dp_set_hw_lane_settings(link, lt_settings, offset);
987 /* EPR #361076 - write as a 5-byte burst,
988 * but only for the 1-st iteration
991 dpcd_set_lt_pattern_and_lane_settings(
996 dpcd_set_lane_settings(link, lt_settings, offset);
998 /* 3. wait for receiver to lock-on*/
999 wait_time_microsec = lt_settings->eq_pattern_time;
1001 if (is_repeater(link, offset))
1002 wait_time_microsec =
1003 dp_translate_training_aux_read_interval(
1004 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
1006 dp_wait_for_training_aux_rd_interval(
1008 wait_time_microsec);
1010 /* 4. Read lane status and requested
1011 * drive settings as set by the sink*/
1013 dp_get_lane_status_and_drive_settings(
1017 &dpcd_lane_status_updated,
1021 /* 5. check CR done*/
1022 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
1023 return LINK_TRAINING_EQ_FAIL_CR;
1025 /* 6. check CHEQ done*/
1026 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
1027 dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
1028 dp_is_interlane_aligned(dpcd_lane_status_updated))
1029 return LINK_TRAINING_SUCCESS;
1031 /* 7. update VS/PE/PC2 in lt_settings*/
1032 dp_update_drive_settings(lt_settings, req_settings);
1035 return LINK_TRAINING_EQ_FAIL_EQ;
1039 static void start_clock_recovery_pattern_early(struct dc_link *link,
1040 struct link_training_settings *lt_settings,
1043 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1045 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1046 dp_set_hw_lane_settings(link, lt_settings, offset);
1050 static enum link_training_result perform_clock_recovery_sequence(
1051 struct dc_link *link,
1052 struct link_training_settings *lt_settings,
1055 uint32_t retries_cr;
1056 uint32_t retry_count;
1057 uint32_t wait_time_microsec;
1058 struct link_training_settings req_settings;
1059 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1060 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1061 union lane_align_status_updated dpcd_lane_status_updated;
1066 if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1067 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1069 /* najeeb - The synaptics MST hub can put the LT in
1070 * infinite loop by switching the VS
1072 /* between level 0 and level 1 continuously, here
1073 * we try for CR lock for LinkTrainingMaxCRRetry count*/
1074 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1075 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1077 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1078 memset(&dpcd_lane_status_updated, '\0',
1079 sizeof(dpcd_lane_status_updated));
1081 /* 1. call HWSS to set lane settings*/
1082 dp_set_hw_lane_settings(
1087 /* 2. update DPCD of the receiver*/
1089 /* EPR #361076 - write as a 5-byte burst,
1090 * but only for the 1-st iteration.*/
1091 dpcd_set_lt_pattern_and_lane_settings(
1094 lt_settings->pattern_for_cr,
1097 dpcd_set_lane_settings(
1102 /* 3. wait receiver to lock-on*/
1103 wait_time_microsec = lt_settings->cr_pattern_time;
1105 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1106 wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1108 dp_wait_for_training_aux_rd_interval(
1110 wait_time_microsec);
1112 /* 4. Read lane status and requested drive
1113 * settings as set by the sink
1115 dp_get_lane_status_and_drive_settings(
1119 &dpcd_lane_status_updated,
1123 /* 5. check CR done*/
1124 if (dp_is_cr_done(lane_count, dpcd_lane_status))
1125 return LINK_TRAINING_SUCCESS;
1127 /* 6. max VS reached*/
1128 if (dp_is_max_vs_reached(lt_settings))
1131 /* 7. same lane settings*/
1132 /* Note: settings are the same for all lanes,
1133 * so comparing first lane is sufficient*/
1134 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
1135 req_settings.lane_settings[0].VOLTAGE_SWING)
1136 && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1137 req_settings.lane_settings[0].PRE_EMPHASIS))
1142 /* 8. update VS/PE/PC2 in lt_settings*/
1143 dp_update_drive_settings(lt_settings, req_settings);
1148 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1150 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1152 LINK_TRAINING_MAX_CR_RETRY);
1156 return dp_get_cr_failure(lane_count, dpcd_lane_status);
1159 static inline enum link_training_result dp_transition_to_video_idle(
1160 struct dc_link *link,
1161 struct link_training_settings *lt_settings,
1162 enum link_training_result status)
1164 union lane_count_set lane_count_set = { {0} };
1166 /* 4. mainlink output idle pattern*/
1167 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1170 * 5. post training adjust if required
1171 * If the upstream DPTX and downstream DPRX both support TPS4,
1172 * TPS4 must be used instead of POST_LT_ADJ_REQ.
1174 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1175 lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) {
1176 /* delay 5ms after Main Link output idle pattern and then check
1179 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1181 status = dp_check_link_loss_status(link, lt_settings);
1186 if (status == LINK_TRAINING_SUCCESS &&
1187 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1188 status = LINK_TRAINING_LQA_FAIL;
1190 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1191 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1192 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1194 core_link_write_dpcd(
1197 &lane_count_set.raw,
1198 sizeof(lane_count_set));
1203 enum link_training_result dp_check_link_loss_status(
1204 struct dc_link *link,
1205 const struct link_training_settings *link_training_setting)
1207 enum link_training_result status = LINK_TRAINING_SUCCESS;
1208 union lane_status lane_status;
1209 uint8_t dpcd_buf[6] = {0};
1212 core_link_read_dpcd(
1215 (uint8_t *)(dpcd_buf),
1218 /*parse lane status*/
1219 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1221 * check lanes status
1223 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1225 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1226 !lane_status.bits.CR_DONE_0 ||
1227 !lane_status.bits.SYMBOL_LOCKED_0) {
1228 /* if one of the channel equalization, clock
1229 * recovery or symbol lock is dropped
1230 * consider it as (link has been
1231 * dropped) dp sink status has changed
1233 status = LINK_TRAINING_LINK_LOSS;
1241 static inline void decide_8b_10b_training_settings(
1242 struct dc_link *link,
1243 const struct dc_link_settings *link_setting,
1244 const struct dc_link_training_overrides *overrides,
1245 struct link_training_settings *lt_settings)
1249 memset(lt_settings, '\0', sizeof(struct link_training_settings));
1251 /* Initialize link settings */
1252 lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1253 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1255 if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1256 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1258 lt_settings->link_settings.link_rate = link_setting->link_rate;
1260 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1261 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1263 lt_settings->link_settings.lane_count = link_setting->lane_count;
1265 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1267 /* TODO hard coded to SS for now
1268 * lt_settings.link_settings.link_spread =
1269 * dal_display_path_is_ss_supported(
1270 * path_mode->display_path) ?
1271 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1272 * LINK_SPREAD_DISABLED;
1274 /* Initialize link spread */
1275 if (link->dp_ss_off)
1276 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1277 else if (overrides->downspread != NULL)
1278 lt_settings->link_settings.link_spread
1279 = *overrides->downspread
1280 ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1281 : LINK_SPREAD_DISABLED;
1283 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1285 lt_settings->lttpr_mode = link->lttpr_mode;
1287 /* Initialize lane settings overrides */
1288 if (overrides->voltage_swing != NULL)
1289 lt_settings->voltage_swing = overrides->voltage_swing;
1291 if (overrides->pre_emphasis != NULL)
1292 lt_settings->pre_emphasis = overrides->pre_emphasis;
1294 if (overrides->post_cursor2 != NULL)
1295 lt_settings->post_cursor2 = overrides->post_cursor2;
1297 /* Initialize lane settings (VS/PE/PC2) */
1298 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1299 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1300 lt_settings->voltage_swing != NULL ?
1301 *lt_settings->voltage_swing :
1302 VOLTAGE_SWING_LEVEL0;
1303 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1304 lt_settings->pre_emphasis != NULL ?
1305 *lt_settings->pre_emphasis
1306 : PRE_EMPHASIS_DISABLED;
1307 lt_settings->lane_settings[lane].POST_CURSOR2 =
1308 lt_settings->post_cursor2 != NULL ?
1309 *lt_settings->post_cursor2
1310 : POST_CURSOR2_DISABLED;
1313 /* Initialize training timings */
1314 if (overrides->cr_pattern_time != NULL)
1315 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1317 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1319 if (overrides->eq_pattern_time != NULL)
1320 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1322 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1324 if (overrides->pattern_for_cr != NULL)
1325 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1327 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1328 if (overrides->pattern_for_eq != NULL)
1329 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1331 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1333 if (overrides->enhanced_framing != NULL)
1334 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1336 lt_settings->enhanced_framing = 1;
1338 if (link->preferred_training_settings.fec_enable != NULL)
1339 lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
1341 lt_settings->should_set_fec_ready = true;
1344 void dp_decide_training_settings(
1345 struct dc_link *link,
1346 const struct dc_link_settings *link_settings,
1347 const struct dc_link_training_overrides *overrides,
1348 struct link_training_settings *lt_settings)
1350 if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
1351 decide_8b_10b_training_settings(link, link_settings, overrides, lt_settings);
1355 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
1357 switch (lttpr_repeater_count) {
1358 case 0x80: // 1 lttpr repeater
1360 case 0x40: // 2 lttpr repeaters
1362 case 0x20: // 3 lttpr repeaters
1364 case 0x10: // 4 lttpr repeaters
1366 case 0x08: // 5 lttpr repeaters
1368 case 0x04: // 6 lttpr repeaters
1370 case 0x02: // 7 lttpr repeaters
1372 case 0x01: // 8 lttpr repeaters
1377 return 0; // invalid value
1380 enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
1382 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1384 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1385 return core_link_write_dpcd(link,
1386 DP_PHY_REPEATER_MODE,
1387 (uint8_t *)&repeater_mode,
1388 sizeof(repeater_mode));
1391 enum dc_status configure_lttpr_mode_non_transparent(
1392 struct dc_link *link,
1393 const struct link_training_settings *lt_settings)
1395 /* aux timeout is already set to extended */
1396 /* RESET/SET lttpr mode to enable non transparent mode */
1397 uint8_t repeater_cnt;
1398 uint32_t aux_interval_address;
1399 uint8_t repeater_id;
1400 enum dc_status result = DC_ERROR_UNEXPECTED;
1401 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1403 enum dp_link_encoding encoding = dp_get_link_encoding_format(<_settings->link_settings);
1405 if (encoding == DP_8b_10b_ENCODING) {
1406 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1407 result = core_link_write_dpcd(link,
1408 DP_PHY_REPEATER_MODE,
1409 (uint8_t *)&repeater_mode,
1410 sizeof(repeater_mode));
1414 if (result == DC_OK) {
1415 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1418 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1420 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1422 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1423 result = core_link_write_dpcd(link,
1424 DP_PHY_REPEATER_MODE,
1425 (uint8_t *)&repeater_mode,
1426 sizeof(repeater_mode));
1428 if (result == DC_OK) {
1429 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1432 if (encoding == DP_8b_10b_ENCODING) {
1433 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1434 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1435 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1436 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1437 core_link_read_dpcd(
1439 aux_interval_address,
1440 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1441 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1442 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1450 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1452 union dpcd_training_pattern dpcd_pattern = { {0} };
1454 const uint32_t dpcd_base_lt_offset =
1455 DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1456 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1457 /* Set training not in progress*/
1458 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1460 core_link_write_dpcd(
1462 dpcd_base_lt_offset,
1466 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1469 dpcd_base_lt_offset,
1470 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1473 static void print_status_message(
1474 struct dc_link *link,
1475 const struct link_training_settings *lt_settings,
1476 enum link_training_result status)
1478 char *link_rate = "Unknown";
1479 char *lt_result = "Unknown";
1480 char *lt_spread = "Disabled";
1482 switch (lt_settings->link_settings.link_rate) {
1486 case LINK_RATE_RATE_2:
1489 case LINK_RATE_RATE_3:
1492 case LINK_RATE_HIGH:
1495 case LINK_RATE_RBR2:
1498 case LINK_RATE_RATE_6:
1501 case LINK_RATE_HIGH2:
1504 case LINK_RATE_HIGH3:
1512 case LINK_TRAINING_SUCCESS:
1515 case LINK_TRAINING_CR_FAIL_LANE0:
1516 lt_result = "CR failed lane0";
1518 case LINK_TRAINING_CR_FAIL_LANE1:
1519 lt_result = "CR failed lane1";
1521 case LINK_TRAINING_CR_FAIL_LANE23:
1522 lt_result = "CR failed lane23";
1524 case LINK_TRAINING_EQ_FAIL_CR:
1525 lt_result = "CR failed in EQ";
1527 case LINK_TRAINING_EQ_FAIL_EQ:
1528 lt_result = "EQ failed";
1530 case LINK_TRAINING_LQA_FAIL:
1531 lt_result = "LQA failed";
1533 case LINK_TRAINING_LINK_LOSS:
1534 lt_result = "Link loss";
1540 switch (lt_settings->link_settings.link_spread) {
1541 case LINK_SPREAD_DISABLED:
1542 lt_spread = "Disabled";
1544 case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1545 lt_spread = "0.5% 30KHz";
1547 case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1548 lt_spread = "0.5% 33KHz";
1554 /* Connectivity log: link training */
1555 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1557 lt_settings->link_settings.lane_count,
1559 lt_settings->lane_settings[0].VOLTAGE_SWING,
1560 lt_settings->lane_settings[0].PRE_EMPHASIS,
1564 void dc_link_dp_set_drive_settings(
1565 struct dc_link *link,
1566 struct link_training_settings *lt_settings)
1568 /* program ASIC PHY settings*/
1569 dp_set_hw_lane_settings(link, lt_settings, DPRX);
1571 /* Notify DP sink the PHY settings from source */
1572 dpcd_set_lane_settings(link, lt_settings, DPRX);
1575 bool dc_link_dp_perform_link_training_skip_aux(
1576 struct dc_link *link,
1577 const struct dc_link_settings *link_setting)
1579 struct link_training_settings lt_settings;
1581 dp_decide_training_settings(
1584 &link->preferred_training_settings,
1587 /* 1. Perform_clock_recovery_sequence. */
1589 /* transmit training pattern for clock recovery */
1590 dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1592 /* call HWSS to set lane settings*/
1593 dp_set_hw_lane_settings(link, <_settings, DPRX);
1595 /* wait receiver to lock-on*/
1596 dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1598 /* 2. Perform_channel_equalization_sequence. */
1600 /* transmit training pattern for channel equalization. */
1601 dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1603 /* call HWSS to set lane settings*/
1604 dp_set_hw_lane_settings(link, <_settings, DPRX);
1606 /* wait receiver to lock-on. */
1607 dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1609 /* 3. Perform_link_training_int. */
1611 /* Mainlink output idle pattern. */
1612 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1614 print_status_message(link, <_settings, LINK_TRAINING_SUCCESS);
1619 enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
1621 enum dc_status status = DC_OK;
1623 if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1624 status = configure_lttpr_mode_non_transparent(link, lt_settings);
1626 status = configure_lttpr_mode_transparent(link);
1631 static void dpcd_exit_training_mode(struct dc_link *link)
1634 /* clear training pattern set */
1635 dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
1638 enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
1639 struct link_training_settings *lt_settings)
1641 enum dp_link_encoding encoding =
1642 dp_get_link_encoding_format(
1643 <_settings->link_settings);
1644 enum dc_status status;
1646 status = core_link_write_dpcd(
1648 DP_MAIN_LINK_CHANNEL_CODING_SET,
1649 (uint8_t *) &encoding,
1651 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
1653 DP_MAIN_LINK_CHANNEL_CODING_SET,
1659 static enum link_training_result dp_perform_8b_10b_link_training(
1660 struct dc_link *link,
1661 struct link_training_settings *lt_settings)
1663 enum link_training_result status = LINK_TRAINING_SUCCESS;
1665 uint8_t repeater_cnt;
1666 uint8_t repeater_id;
1669 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1670 start_clock_recovery_pattern_early(link, lt_settings, DPRX);
1672 /* 1. set link rate, lane count and spread. */
1673 dpcd_set_link_settings(link, lt_settings);
1675 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1677 /* 2. perform link training (set link training done
1678 * to false is done as well)
1680 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1682 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1684 status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);
1686 if (status != LINK_TRAINING_SUCCESS)
1689 status = perform_channel_equalization_sequence(link,
1693 if (status != LINK_TRAINING_SUCCESS)
1696 repeater_training_done(link, repeater_id);
1699 for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
1700 lt_settings->lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0;
1703 if (status == LINK_TRAINING_SUCCESS) {
1704 status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
1705 if (status == LINK_TRAINING_SUCCESS) {
1706 status = perform_channel_equalization_sequence(link,
1715 enum link_training_result dc_link_dp_perform_link_training(
1716 struct dc_link *link,
1717 const struct dc_link_settings *link_settings,
1718 bool skip_video_pattern)
1720 enum link_training_result status = LINK_TRAINING_SUCCESS;
1721 struct link_training_settings lt_settings;
1722 enum dp_link_encoding encoding =
1723 dp_get_link_encoding_format(link_settings);
1725 /* decide training settings */
1726 dp_decide_training_settings(
1729 &link->preferred_training_settings,
1732 /* reset previous training states */
1733 dpcd_exit_training_mode(link);
1735 /* configure link prior to entering training mode */
1736 dpcd_configure_lttpr_mode(link, <_settings);
1737 dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
1738 dpcd_configure_channel_coding(link, <_settings);
1740 /* enter training mode:
1741 * Per DP specs starting from here, DPTX device shall not issue
1742 * Non-LT AUX transactions inside training mode.
1744 if (encoding == DP_8b_10b_ENCODING)
1745 status = dp_perform_8b_10b_link_training(link, <_settings);
1749 /* exit training mode and switch to video idle */
1750 dpcd_exit_training_mode(link);
1751 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
1752 status = dp_transition_to_video_idle(link,
1756 /* dump debug data */
1757 print_status_message(link, <_settings, status);
1758 if (status != LINK_TRAINING_SUCCESS)
1759 link->ctx->dc->debug_data.ltFailCount++;
1763 bool perform_link_training_with_retries(
1764 const struct dc_link_settings *link_setting,
1765 bool skip_video_pattern,
1767 struct pipe_ctx *pipe_ctx,
1768 enum signal_type signal,
1772 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1773 struct dc_stream_state *stream = pipe_ctx->stream;
1774 struct dc_link *link = stream->link;
1775 enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1776 struct link_encoder *link_enc;
1777 enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1778 struct dc_link_settings current_setting = *link_setting;
1780 /* Dynamically assigned link encoders associated with stream rather than
1783 if (link->dc->res_pool->funcs->link_encs_assign)
1784 link_enc = stream->link_enc;
1786 link_enc = link->link_enc;
1789 /* We need to do this before the link training to ensure the idle pattern in SST
1790 * mode will be sent right after the link training
1792 link_enc->funcs->connect_dig_be_to_fe(link_enc,
1793 pipe_ctx->stream_res.stream_enc->id, true);
1795 for (j = 0; j < attempts; ++j) {
1797 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1798 __func__, (unsigned int)j + 1, attempts);
1803 pipe_ctx->clock_source->id,
1806 if (stream->sink_patches.dppowerup_delay > 0) {
1807 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1809 msleep(delay_dp_power_up_in_ms);
1812 #ifdef CONFIG_DRM_AMD_DC_HDCP
1813 if (panel_mode == DP_PANEL_MODE_EDP) {
1814 struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1816 if (cp_psp && cp_psp->funcs.enable_assr) {
1817 if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
1818 /* since eDP implies ASSR on, change panel
1819 * mode to disable ASSR
1821 panel_mode = DP_PANEL_MODE_DEFAULT;
1824 panel_mode = DP_PANEL_MODE_DEFAULT;
1828 dp_set_panel_mode(link, panel_mode);
1830 if (link->aux_access_disabled) {
1831 dc_link_dp_perform_link_training_skip_aux(link, ¤t_setting);
1834 status = dc_link_dp_perform_link_training(
1837 skip_video_pattern);
1838 if (status == LINK_TRAINING_SUCCESS)
1842 /* latest link training still fail, skip delay and keep PHY on
1844 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
1847 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1848 __func__, (unsigned int)j + 1, attempts);
1850 dp_disable_link_phy(link, signal);
1852 /* Abort link training if failure due to sink being unplugged. */
1853 if (status == LINK_TRAINING_ABORT)
1855 else if (do_fallback) {
1856 decide_fallback_link_setting(*link_setting, ¤t_setting, status);
1857 /* Fail link training if reduced link bandwidth no longer meets
1858 * stream requirements.
1860 if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
1861 dc_link_bandwidth_kbps(link, ¤t_setting))
1865 msleep(delay_between_attempts);
1867 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1873 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1875 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1876 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1878 if (dp_cs != NULL) {
1879 dp_cs_id = dp_cs->id;
1882 * dp clock source is not initialized for some reason.
1883 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1891 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1893 if (mst_enable == false &&
1894 link->type == dc_connection_mst_branch) {
1895 /* Disable MST on link. Use only local sink. */
1896 dp_disable_link_phy_mst(link, link->connector_signal);
1898 link->type = dc_connection_single;
1899 link->local_sink = link->remote_sinks[0];
1900 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1901 dc_sink_retain(link->local_sink);
1902 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1903 } else if (mst_enable == true &&
1904 link->type == dc_connection_single &&
1905 link->remote_sinks[0] != NULL) {
1906 /* Re-enable MST on link. */
1907 dp_disable_link_phy(link, link->connector_signal);
1908 dp_enable_mst_on_sink(link, true);
1910 link->type = dc_connection_mst_branch;
1911 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1915 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1917 /* Begin Sync LT. During this time,
1918 * DPCD:600h must not be powered down.
1920 link->sync_lt_in_progress = true;
1922 /*Clear any existing preferred settings.*/
1923 memset(&link->preferred_training_settings, 0,
1924 sizeof(struct dc_link_training_overrides));
1925 memset(&link->preferred_link_setting, 0,
1926 sizeof(struct dc_link_settings));
1931 enum link_training_result dc_link_dp_sync_lt_attempt(
1932 struct dc_link *link,
1933 struct dc_link_settings *link_settings,
1934 struct dc_link_training_overrides *lt_overrides)
1936 struct link_training_settings lt_settings;
1937 enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1938 enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1939 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1940 bool fec_enable = false;
1942 dp_decide_training_settings(
1948 /* Setup MST Mode */
1949 if (lt_overrides->mst_enable)
1950 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1953 dp_disable_link_phy(link, link->connector_signal);
1956 dp_cs_id = get_clock_source_id(link);
1957 dp_enable_link_phy(link, link->connector_signal,
1958 dp_cs_id, link_settings);
1960 /* Set FEC enable */
1961 fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1962 dp_set_fec_ready(link, fec_enable);
1964 if (lt_overrides->alternate_scrambler_reset) {
1965 if (*lt_overrides->alternate_scrambler_reset)
1966 panel_mode = DP_PANEL_MODE_EDP;
1968 panel_mode = DP_PANEL_MODE_DEFAULT;
1970 panel_mode = dp_get_panel_mode(link);
1972 dp_set_panel_mode(link, panel_mode);
1974 /* Attempt to train with given link training settings */
1975 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1976 start_clock_recovery_pattern_early(link, <_settings, DPRX);
1978 /* Set link rate, lane count and spread. */
1979 dpcd_set_link_settings(link, <_settings);
1981 /* 2. perform link training (set link training done
1982 * to false is done as well)
1984 lt_status = perform_clock_recovery_sequence(link, <_settings, DPRX);
1985 if (lt_status == LINK_TRAINING_SUCCESS) {
1986 lt_status = perform_channel_equalization_sequence(link,
1991 /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1992 /* 4. print status message*/
1993 print_status_message(link, <_settings, lt_status);
1998 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
2000 /* If input parameter is set, shut down phy.
2001 * Still shouldn't turn off dp_receiver (DPCD:600h)
2003 if (link_down == true) {
2004 dp_disable_link_phy(link, link->connector_signal);
2005 dp_set_fec_ready(link, false);
2008 link->sync_lt_in_progress = false;
2012 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2014 if (!max_link_enc_cap) {
2015 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2019 if (link->link_enc->funcs->get_max_link_cap) {
2020 link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap);
2024 DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2025 max_link_enc_cap->lane_count = 1;
2026 max_link_enc_cap->link_rate = 6;
2030 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
2032 struct dc_link_settings max_link_cap = {0};
2034 /* get max link encoder capability */
2035 link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
2037 /* Lower link settings based on sink's link cap */
2038 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2039 max_link_cap.lane_count =
2040 link->reported_link_cap.lane_count;
2041 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2042 max_link_cap.link_rate =
2043 link->reported_link_cap.link_rate;
2044 if (link->reported_link_cap.link_spread <
2045 max_link_cap.link_spread)
2046 max_link_cap.link_spread =
2047 link->reported_link_cap.link_spread;
2049 * account for lttpr repeaters cap
2050 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2052 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
2053 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2054 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2056 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
2057 max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
2059 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
2061 max_link_cap.lane_count,
2062 max_link_cap.link_rate);
2064 return max_link_cap;
2067 enum dc_status read_hpd_rx_irq_data(
2068 struct dc_link *link,
2069 union hpd_irq_data *irq_data)
2071 static enum dc_status retval;
2073 /* The HW reads 16 bytes from 200h on HPD,
2074 * but if we get an AUX_DEFER, the HW cannot retry
2075 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
2076 * fail, so we now explicitly read 6 bytes which is
2077 * the req from the above mentioned test cases.
2079 * For DP 1.4 we need to read those from 2002h range.
2081 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
2082 retval = core_link_read_dpcd(
2086 sizeof(union hpd_irq_data));
2088 /* Read 14 bytes in a single read and then copy only the required fields.
2089 * This is more efficient than doing it in two separate AUX reads. */
2091 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
2093 retval = core_link_read_dpcd(
2099 if (retval != DC_OK)
2102 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
2103 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
2104 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
2105 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
2106 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
2107 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
2113 bool hpd_rx_irq_check_link_loss_status(
2114 struct dc_link *link,
2115 union hpd_irq_data *hpd_irq_dpcd_data)
2117 uint8_t irq_reg_rx_power_state = 0;
2118 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2119 union lane_status lane_status;
2121 bool sink_status_changed;
2124 sink_status_changed = false;
2125 return_code = false;
2127 if (link->cur_link_settings.lane_count == 0)
2130 /*1. Check that Link Status changed, before re-training.*/
2132 /*parse lane status*/
2133 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2134 /* check status of lanes 0,1
2135 * changed DpcdAddress_Lane01Status (0x202)
2137 lane_status.raw = get_nibble_at_index(
2138 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2141 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2142 !lane_status.bits.CR_DONE_0 ||
2143 !lane_status.bits.SYMBOL_LOCKED_0) {
2144 /* if one of the channel equalization, clock
2145 * recovery or symbol lock is dropped
2146 * consider it as (link has been
2147 * dropped) dp sink status has changed
2149 sink_status_changed = true;
2154 /* Check interlane align.*/
2155 if (sink_status_changed ||
2156 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2158 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2162 /*2. Check that we can handle interrupt: Not in FS DOS,
2163 * Not in "Display Timeout" state, Link is trained.
2165 dpcd_result = core_link_read_dpcd(link,
2167 &irq_reg_rx_power_state,
2168 sizeof(irq_reg_rx_power_state));
2170 if (dpcd_result != DC_OK) {
2171 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2174 if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2175 return_code = false;
2182 bool dp_verify_link_cap(
2183 struct dc_link *link,
2184 struct dc_link_settings *known_limit_link_setting,
2187 struct dc_link_settings max_link_cap = {0};
2188 struct dc_link_settings cur_link_setting = {0};
2189 struct dc_link_settings *cur = &cur_link_setting;
2190 struct dc_link_settings initial_link_settings = {0};
2192 bool skip_link_training;
2193 bool skip_video_pattern;
2194 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2195 enum link_training_result status;
2196 union hpd_irq_data irq_data;
2198 if (link->dc->debug.skip_detection_link_training) {
2199 link->verified_link_cap = *known_limit_link_setting;
2203 memset(&irq_data, 0, sizeof(irq_data));
2205 skip_link_training = false;
2207 max_link_cap = get_max_link_cap(link);
2209 /* Grant extended timeout request */
2210 if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
2211 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2213 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2216 /* TODO implement override and monitor patch later */
2218 /* try to train the link from high to low to
2219 * find the physical link capability
2221 /* disable PHY done possible by BIOS, will be done by driver itself */
2222 dp_disable_link_phy(link, link->connector_signal);
2224 dp_cs_id = get_clock_source_id(link);
2226 /* link training starts with the maximum common settings
2227 * supported by both sink and ASIC.
2229 initial_link_settings = get_common_supported_link_settings(
2230 *known_limit_link_setting,
2232 cur_link_setting = initial_link_settings;
2234 /* Temporary Renoir-specific workaround for SWDEV-215184;
2235 * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2236 * so add extra cycle of enabling and disabling the PHY before first link training.
2238 if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2239 link->dc->debug.usbc_combo_phy_reset_wa) {
2240 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2241 dp_disable_link_phy(link, link->connector_signal);
2245 skip_video_pattern = true;
2247 if (cur->link_rate == LINK_RATE_LOW)
2248 skip_video_pattern = false;
2252 link->connector_signal,
2257 if (skip_link_training)
2260 status = dc_link_dp_perform_link_training(
2263 skip_video_pattern);
2264 if (status == LINK_TRAINING_SUCCESS)
2271 link->verified_link_cap = *cur;
2273 if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2274 if (hpd_rx_irq_check_link_loss_status(
2279 /* always disable the link before trying another
2280 * setting or before returning we'll enable it later
2281 * based on the actual mode we're driving
2283 dp_disable_link_phy(link, link->connector_signal);
2284 } while (!success && decide_fallback_link_setting(
2285 initial_link_settings, cur, status));
2287 /* Link Training failed for all Link Settings
2288 * (Lane Count is still unknown)
2291 /* If all LT fails for all settings,
2292 * set verified = failed safe (1 lane low)
2294 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2295 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2297 link->verified_link_cap.link_spread =
2298 LINK_SPREAD_DISABLED;
2305 bool dp_verify_link_cap_with_retries(
2306 struct dc_link *link,
2307 struct dc_link_settings *known_limit_link_setting,
2311 bool success = false;
2313 for (i = 0; i < attempts; i++) {
2315 enum dc_connection_type type = dc_connection_none;
2317 memset(&link->verified_link_cap, 0,
2318 sizeof(struct dc_link_settings));
2319 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2320 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2321 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2322 link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2324 } else if (dp_verify_link_cap(link,
2325 &link->reported_link_cap,
2326 &fail_count) && fail_count == 0) {
2335 bool dp_verify_mst_link_cap(
2336 struct dc_link *link)
2338 struct dc_link_settings max_link_cap = {0};
2340 max_link_cap = get_max_link_cap(link);
2341 link->verified_link_cap = get_common_supported_link_settings(
2342 link->reported_link_cap,
2348 static struct dc_link_settings get_common_supported_link_settings(
2349 struct dc_link_settings link_setting_a,
2350 struct dc_link_settings link_setting_b)
2352 struct dc_link_settings link_settings = {0};
2354 link_settings.lane_count =
2355 (link_setting_a.lane_count <=
2356 link_setting_b.lane_count) ?
2357 link_setting_a.lane_count :
2358 link_setting_b.lane_count;
2359 link_settings.link_rate =
2360 (link_setting_a.link_rate <=
2361 link_setting_b.link_rate) ?
2362 link_setting_a.link_rate :
2363 link_setting_b.link_rate;
2364 link_settings.link_spread = LINK_SPREAD_DISABLED;
2366 /* in DP compliance test, DPR-120 may have
2367 * a random value in its MAX_LINK_BW dpcd field.
2368 * We map it to the maximum supported link rate that
2369 * is smaller than MAX_LINK_BW in this case.
2371 if (link_settings.link_rate > LINK_RATE_HIGH3) {
2372 link_settings.link_rate = LINK_RATE_HIGH3;
2373 } else if (link_settings.link_rate < LINK_RATE_HIGH3
2374 && link_settings.link_rate > LINK_RATE_HIGH2) {
2375 link_settings.link_rate = LINK_RATE_HIGH2;
2376 } else if (link_settings.link_rate < LINK_RATE_HIGH2
2377 && link_settings.link_rate > LINK_RATE_HIGH) {
2378 link_settings.link_rate = LINK_RATE_HIGH;
2379 } else if (link_settings.link_rate < LINK_RATE_HIGH
2380 && link_settings.link_rate > LINK_RATE_LOW) {
2381 link_settings.link_rate = LINK_RATE_LOW;
2382 } else if (link_settings.link_rate < LINK_RATE_LOW) {
2383 link_settings.link_rate = LINK_RATE_UNKNOWN;
2386 return link_settings;
2389 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2391 return lane_count <= LANE_COUNT_ONE;
2394 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2396 return link_rate <= LINK_RATE_LOW;
2399 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2401 switch (lane_count) {
2402 case LANE_COUNT_FOUR:
2403 return LANE_COUNT_TWO;
2404 case LANE_COUNT_TWO:
2405 return LANE_COUNT_ONE;
2406 case LANE_COUNT_ONE:
2407 return LANE_COUNT_UNKNOWN;
2409 return LANE_COUNT_UNKNOWN;
2413 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2415 switch (link_rate) {
2416 case LINK_RATE_HIGH3:
2417 return LINK_RATE_HIGH2;
2418 case LINK_RATE_HIGH2:
2419 return LINK_RATE_HIGH;
2420 case LINK_RATE_HIGH:
2421 return LINK_RATE_LOW;
2423 return LINK_RATE_UNKNOWN;
2425 return LINK_RATE_UNKNOWN;
2429 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2431 switch (lane_count) {
2432 case LANE_COUNT_ONE:
2433 return LANE_COUNT_TWO;
2434 case LANE_COUNT_TWO:
2435 return LANE_COUNT_FOUR;
2437 return LANE_COUNT_UNKNOWN;
2441 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2443 switch (link_rate) {
2445 return LINK_RATE_HIGH;
2446 case LINK_RATE_HIGH:
2447 return LINK_RATE_HIGH2;
2448 case LINK_RATE_HIGH2:
2449 return LINK_RATE_HIGH3;
2451 return LINK_RATE_UNKNOWN;
2456 * function: set link rate and lane count fallback based
2457 * on current link setting and last link training result
2459 * true - link setting could be set
2460 * false - has reached minimum setting
2461 * and no further fallback could be done
2463 static bool decide_fallback_link_setting(
2464 struct dc_link_settings initial_link_settings,
2465 struct dc_link_settings *current_link_setting,
2466 enum link_training_result training_result)
2468 if (!current_link_setting)
2471 switch (training_result) {
2472 case LINK_TRAINING_CR_FAIL_LANE0:
2473 case LINK_TRAINING_CR_FAIL_LANE1:
2474 case LINK_TRAINING_CR_FAIL_LANE23:
2475 case LINK_TRAINING_LQA_FAIL:
2477 if (!reached_minimum_link_rate
2478 (current_link_setting->link_rate)) {
2479 current_link_setting->link_rate =
2481 current_link_setting->link_rate);
2482 } else if (!reached_minimum_lane_count
2483 (current_link_setting->lane_count)) {
2484 current_link_setting->link_rate =
2485 initial_link_settings.link_rate;
2486 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2488 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2489 current_link_setting->lane_count =
2491 else if (training_result ==
2492 LINK_TRAINING_CR_FAIL_LANE23)
2493 current_link_setting->lane_count =
2496 current_link_setting->lane_count =
2498 current_link_setting->lane_count);
2504 case LINK_TRAINING_EQ_FAIL_EQ:
2506 if (!reached_minimum_lane_count
2507 (current_link_setting->lane_count)) {
2508 current_link_setting->lane_count =
2510 current_link_setting->lane_count);
2511 } else if (!reached_minimum_link_rate
2512 (current_link_setting->link_rate)) {
2513 current_link_setting->link_rate =
2515 current_link_setting->link_rate);
2521 case LINK_TRAINING_EQ_FAIL_CR:
2523 if (!reached_minimum_link_rate
2524 (current_link_setting->link_rate)) {
2525 current_link_setting->link_rate =
2527 current_link_setting->link_rate);
2539 bool dp_validate_mode_timing(
2540 struct dc_link *link,
2541 const struct dc_crtc_timing *timing)
2546 const struct dc_link_settings *link_setting;
2548 /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
2549 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
2550 !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
2551 dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
2554 /*always DP fail safe mode*/
2555 if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2556 timing->h_addressable == (uint32_t) 640 &&
2557 timing->v_addressable == (uint32_t) 480)
2560 link_setting = dc_link_get_link_cap(link);
2562 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2563 /*if (flags.DYNAMIC_VALIDATION == 1 &&
2564 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2565 link_setting = &link->verified_link_cap;
2568 req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2569 max_bw = dc_link_bandwidth_kbps(link, link_setting);
2571 if (req_bw <= max_bw) {
2572 /* remember the biggest mode here, during
2573 * initial link training (to get
2574 * verified_link_cap), LS sends event about
2575 * cannot train at reported cap to upper
2576 * layer and upper layer will re-enumerate modes.
2577 * this is not necessary if the lower
2578 * verified_link_cap is enough to drive
2581 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2582 /* if (flags.DYNAMIC_VALIDATION == 1)
2583 dpsst->max_req_bw_for_verified_linkcap = dal_max(
2584 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2590 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2592 struct dc_link_settings initial_link_setting = {
2593 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2594 struct dc_link_settings current_link_setting =
2595 initial_link_setting;
2598 if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2601 /* search for the minimum link setting that:
2602 * 1. is supported according to the link training result
2603 * 2. could support the b/w requested by the timing
2605 while (current_link_setting.link_rate <=
2606 link->verified_link_cap.link_rate) {
2607 link_bw = dc_link_bandwidth_kbps(
2609 ¤t_link_setting);
2610 if (req_bw <= link_bw) {
2611 *link_setting = current_link_setting;
2615 if (current_link_setting.lane_count <
2616 link->verified_link_cap.lane_count) {
2617 current_link_setting.lane_count =
2618 increase_lane_count(
2619 current_link_setting.lane_count);
2621 current_link_setting.link_rate =
2623 current_link_setting.link_rate);
2624 current_link_setting.lane_count =
2625 initial_link_setting.lane_count;
2632 bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2634 struct dc_link_settings initial_link_setting;
2635 struct dc_link_settings current_link_setting;
2639 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
2640 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
2642 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
2643 link->dpcd_caps.edp_supported_link_rates_count == 0) {
2644 *link_setting = link->verified_link_cap;
2648 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2649 initial_link_setting.lane_count = LANE_COUNT_ONE;
2650 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2651 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2652 initial_link_setting.use_link_rate_set = true;
2653 initial_link_setting.link_rate_set = 0;
2654 current_link_setting = initial_link_setting;
2656 /* search for the minimum link setting that:
2657 * 1. is supported according to the link training result
2658 * 2. could support the b/w requested by the timing
2660 while (current_link_setting.link_rate <=
2661 link->verified_link_cap.link_rate) {
2662 link_bw = dc_link_bandwidth_kbps(
2664 ¤t_link_setting);
2665 if (req_bw <= link_bw) {
2666 *link_setting = current_link_setting;
2670 if (current_link_setting.lane_count <
2671 link->verified_link_cap.lane_count) {
2672 current_link_setting.lane_count =
2673 increase_lane_count(
2674 current_link_setting.lane_count);
2676 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2677 current_link_setting.link_rate_set++;
2678 current_link_setting.link_rate =
2679 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2680 current_link_setting.lane_count =
2681 initial_link_setting.lane_count;
2689 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2691 *link_setting = link->verified_link_cap;
2695 void decide_link_settings(struct dc_stream_state *stream,
2696 struct dc_link_settings *link_setting)
2698 struct dc_link *link;
2701 req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2703 link = stream->link;
2705 /* if preferred is specified through AMDDP, use it, if it's enough
2708 if (link->preferred_link_setting.lane_count !=
2709 LANE_COUNT_UNKNOWN &&
2710 link->preferred_link_setting.link_rate !=
2711 LINK_RATE_UNKNOWN) {
2712 *link_setting = link->preferred_link_setting;
2716 /* MST doesn't perform link training for now
2717 * TODO: add MST specific link training routine
2719 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2720 if (decide_mst_link_settings(link, link_setting))
2722 } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2723 if (decide_edp_link_settings(link, link_setting, req_bw))
2725 } else if (decide_dp_link_settings(link, link_setting, req_bw))
2728 BREAK_TO_DEBUGGER();
2729 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2731 *link_setting = link->verified_link_cap;
2734 /*************************Short Pulse IRQ***************************/
2735 static bool allow_hpd_rx_irq(const struct dc_link *link)
2738 * Don't handle RX IRQ unless one of following is met:
2739 * 1) The link is established (cur_link_settings != unknown)
2740 * 2) We know we're dealing with a branch device, SST or MST
2743 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2744 is_dp_branch_device(link))
2750 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2752 union dpcd_psr_configuration psr_configuration;
2754 if (!link->psr_settings.psr_feature_enabled)
2757 dm_helpers_dp_read_dpcd(
2760 368,/*DpcdAddress_PSR_Enable_Cfg*/
2761 &psr_configuration.raw,
2762 sizeof(psr_configuration.raw));
2765 if (psr_configuration.bits.ENABLE) {
2766 unsigned char dpcdbuf[3] = {0};
2767 union psr_error_status psr_error_status;
2768 union psr_sink_psr_status psr_sink_psr_status;
2770 dm_helpers_dp_read_dpcd(
2773 0x2006, /*DpcdAddress_PSR_Error_Status*/
2774 (unsigned char *) dpcdbuf,
2777 /*DPCD 2006h ERROR STATUS*/
2778 psr_error_status.raw = dpcdbuf[0];
2779 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
2780 psr_sink_psr_status.raw = dpcdbuf[2];
2782 if (psr_error_status.bits.LINK_CRC_ERROR ||
2783 psr_error_status.bits.RFB_STORAGE_ERROR ||
2784 psr_error_status.bits.VSC_SDP_ERROR) {
2785 /* Acknowledge and clear error bits */
2786 dm_helpers_dp_write_dpcd(
2789 8198,/*DpcdAddress_PSR_Error_Status*/
2790 &psr_error_status.raw,
2791 sizeof(psr_error_status.raw));
2793 /* PSR error, disable and re-enable PSR */
2794 dc_link_set_psr_allow_active(link, false, true, false);
2795 dc_link_set_psr_allow_active(link, true, true, false);
2798 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2799 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2800 /* No error is detect, PSR is active.
2801 * We should return with IRQ_HPD handled without
2802 * checking for loss of sync since PSR would have
2803 * powered down main link.
2811 static void dp_test_send_link_training(struct dc_link *link)
2813 struct dc_link_settings link_settings = {0};
2815 core_link_read_dpcd(
2818 (unsigned char *)(&link_settings.lane_count),
2820 core_link_read_dpcd(
2823 (unsigned char *)(&link_settings.link_rate),
2826 /* Set preferred link settings */
2827 link->verified_link_cap.lane_count = link_settings.lane_count;
2828 link->verified_link_cap.link_rate = link_settings.link_rate;
2830 dp_retrain_link_dp_test(link, &link_settings, false);
2833 /* TODO Raven hbr2 compliance eye output is unstable
2834 * (toggling on and off) with debugger break
2835 * This caueses intermittent PHY automation failure
2836 * Need to look into the root cause */
2837 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2839 union phy_test_pattern dpcd_test_pattern;
2840 union lane_adjust dpcd_lane_adjustment[2];
2841 unsigned char dpcd_post_cursor_2_adjustment = 0;
2842 unsigned char test_pattern_buffer[
2843 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2844 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2845 unsigned int test_pattern_size = 0;
2846 enum dp_test_pattern test_pattern;
2847 struct dc_link_training_settings link_settings;
2848 union lane_adjust dpcd_lane_adjust;
2850 struct link_training_settings link_training_settings;
2853 dpcd_test_pattern.raw = 0;
2854 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2855 memset(&link_settings, 0, sizeof(link_settings));
2857 /* get phy test pattern and pattern parameters from DP receiver */
2858 core_link_read_dpcd(
2860 DP_PHY_TEST_PATTERN,
2861 &dpcd_test_pattern.raw,
2862 sizeof(dpcd_test_pattern));
2863 core_link_read_dpcd(
2865 DP_ADJUST_REQUEST_LANE0_1,
2866 &dpcd_lane_adjustment[0].raw,
2867 sizeof(dpcd_lane_adjustment));
2869 /*get post cursor 2 parameters
2870 * For DP 1.1a or eariler, this DPCD register's value is 0
2871 * For DP 1.2 or later:
2872 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2873 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2875 core_link_read_dpcd(
2877 DP_ADJUST_REQUEST_POST_CURSOR2,
2878 &dpcd_post_cursor_2_adjustment,
2879 sizeof(dpcd_post_cursor_2_adjustment));
2881 /* translate request */
2882 switch (dpcd_test_pattern.bits.PATTERN) {
2883 case PHY_TEST_PATTERN_D10_2:
2884 test_pattern = DP_TEST_PATTERN_D102;
2886 case PHY_TEST_PATTERN_SYMBOL_ERROR:
2887 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2889 case PHY_TEST_PATTERN_PRBS7:
2890 test_pattern = DP_TEST_PATTERN_PRBS7;
2892 case PHY_TEST_PATTERN_80BIT_CUSTOM:
2893 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2895 case PHY_TEST_PATTERN_CP2520_1:
2896 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2897 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2898 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2899 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2901 case PHY_TEST_PATTERN_CP2520_2:
2902 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2903 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2904 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2905 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2907 case PHY_TEST_PATTERN_CP2520_3:
2908 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2911 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2915 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
2916 test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2917 DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1;
2918 core_link_read_dpcd(
2920 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2921 test_pattern_buffer,
2925 /* prepare link training settings */
2926 link_settings.link = link->cur_link_settings;
2928 for (lane = 0; lane <
2929 (unsigned int)(link->cur_link_settings.lane_count);
2931 dpcd_lane_adjust.raw =
2932 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2933 link_settings.lane_settings[lane].VOLTAGE_SWING =
2934 (enum dc_voltage_swing)
2935 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2936 link_settings.lane_settings[lane].PRE_EMPHASIS =
2937 (enum dc_pre_emphasis)
2938 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2939 link_settings.lane_settings[lane].POST_CURSOR2 =
2940 (enum dc_post_cursor2)
2941 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2944 for (i = 0; i < 4; i++)
2945 link_training_settings.lane_settings[i] =
2946 link_settings.lane_settings[i];
2947 link_training_settings.link_settings = link_settings.link;
2948 link_training_settings.allow_invalid_msa_timing_param = false;
2949 /*Usage: Measure DP physical lane signal
2950 * by DP SI test equipment automatically.
2951 * PHY test pattern request is generated by equipment via HPD interrupt.
2952 * HPD needs to be active all the time. HPD should be active
2953 * all the time. Do not touch it.
2954 * forward request to DS
2956 dc_link_dp_set_test_pattern(
2959 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2960 &link_training_settings,
2961 test_pattern_buffer,
2965 static void dp_test_send_link_test_pattern(struct dc_link *link)
2967 union link_test_pattern dpcd_test_pattern;
2968 union test_misc dpcd_test_params;
2969 enum dp_test_pattern test_pattern;
2970 enum dp_test_pattern_color_space test_pattern_color_space =
2971 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2972 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2973 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2974 struct pipe_ctx *pipe_ctx = NULL;
2977 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2978 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2980 for (i = 0; i < MAX_PIPES; i++) {
2981 if (pipes[i].stream == NULL)
2984 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
2985 pipe_ctx = &pipes[i];
2990 if (pipe_ctx == NULL)
2993 /* get link test pattern and pattern parameters */
2994 core_link_read_dpcd(
2997 &dpcd_test_pattern.raw,
2998 sizeof(dpcd_test_pattern));
2999 core_link_read_dpcd(
3002 &dpcd_test_params.raw,
3003 sizeof(dpcd_test_params));
3005 switch (dpcd_test_pattern.bits.PATTERN) {
3006 case LINK_TEST_PATTERN_COLOR_RAMP:
3007 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
3009 case LINK_TEST_PATTERN_VERTICAL_BARS:
3010 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
3011 break; /* black and white */
3012 case LINK_TEST_PATTERN_COLOR_SQUARES:
3013 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
3014 TEST_DYN_RANGE_VESA ?
3015 DP_TEST_PATTERN_COLOR_SQUARES :
3016 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
3019 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
3023 if (dpcd_test_params.bits.CLR_FORMAT == 0)
3024 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
3026 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
3027 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
3028 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
3030 switch (dpcd_test_params.bits.BPC) {
3032 requestColorDepth = COLOR_DEPTH_666;
3035 requestColorDepth = COLOR_DEPTH_888;
3038 requestColorDepth = COLOR_DEPTH_101010;
3041 requestColorDepth = COLOR_DEPTH_121212;
3047 switch (dpcd_test_params.bits.CLR_FORMAT) {
3049 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3052 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
3055 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
3058 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3063 if (requestColorDepth != COLOR_DEPTH_UNDEFINED
3064 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
3065 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
3067 pipe_ctx->stream->timing.display_color_depth,
3069 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
3072 dp_update_dsc_config(pipe_ctx);
3074 dc_link_dp_set_test_pattern(
3077 test_pattern_color_space,
3083 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
3085 union audio_test_mode dpcd_test_mode = {0};
3086 struct audio_test_pattern_type dpcd_pattern_type = {0};
3087 union audio_test_pattern_period dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
3088 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3090 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3091 struct pipe_ctx *pipe_ctx = &pipes[0];
3092 unsigned int channel_count;
3093 unsigned int channel = 0;
3094 unsigned int modes = 0;
3095 unsigned int sampling_rate_in_hz = 0;
3097 // get audio test mode and test pattern parameters
3098 core_link_read_dpcd(
3101 &dpcd_test_mode.raw,
3102 sizeof(dpcd_test_mode));
3104 core_link_read_dpcd(
3106 DP_TEST_AUDIO_PATTERN_TYPE,
3107 &dpcd_pattern_type.value,
3108 sizeof(dpcd_pattern_type));
3110 channel_count = dpcd_test_mode.bits.channel_count + 1;
3112 // read pattern periods for requested channels when sawTooth pattern is requested
3113 if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
3114 dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
3116 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
3117 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3118 // read period for each channel
3119 for (channel = 0; channel < channel_count; channel++) {
3120 core_link_read_dpcd(
3122 DP_TEST_AUDIO_PERIOD_CH1 + channel,
3123 &dpcd_pattern_period[channel].raw,
3124 sizeof(dpcd_pattern_period[channel]));
3128 // translate sampling rate
3129 switch (dpcd_test_mode.bits.sampling_rate) {
3130 case AUDIO_SAMPLING_RATE_32KHZ:
3131 sampling_rate_in_hz = 32000;
3133 case AUDIO_SAMPLING_RATE_44_1KHZ:
3134 sampling_rate_in_hz = 44100;
3136 case AUDIO_SAMPLING_RATE_48KHZ:
3137 sampling_rate_in_hz = 48000;
3139 case AUDIO_SAMPLING_RATE_88_2KHZ:
3140 sampling_rate_in_hz = 88200;
3142 case AUDIO_SAMPLING_RATE_96KHZ:
3143 sampling_rate_in_hz = 96000;
3145 case AUDIO_SAMPLING_RATE_176_4KHZ:
3146 sampling_rate_in_hz = 176400;
3148 case AUDIO_SAMPLING_RATE_192KHZ:
3149 sampling_rate_in_hz = 192000;
3152 sampling_rate_in_hz = 0;
3156 link->audio_test_data.flags.test_requested = 1;
3157 link->audio_test_data.flags.disable_video = disable_video;
3158 link->audio_test_data.sampling_rate = sampling_rate_in_hz;
3159 link->audio_test_data.channel_count = channel_count;
3160 link->audio_test_data.pattern_type = test_pattern;
3162 if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3163 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3164 link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3169 static void handle_automated_test(struct dc_link *link)
3171 union test_request test_request;
3172 union test_response test_response;
3174 memset(&test_request, 0, sizeof(test_request));
3175 memset(&test_response, 0, sizeof(test_response));
3177 core_link_read_dpcd(
3181 sizeof(union test_request));
3182 if (test_request.bits.LINK_TRAINING) {
3183 /* ACK first to let DP RX test box monitor LT sequence */
3184 test_response.bits.ACK = 1;
3185 core_link_write_dpcd(
3189 sizeof(test_response));
3190 dp_test_send_link_training(link);
3191 /* no acknowledge request is needed again */
3192 test_response.bits.ACK = 0;
3194 if (test_request.bits.LINK_TEST_PATTRN) {
3195 dp_test_send_link_test_pattern(link);
3196 test_response.bits.ACK = 1;
3199 if (test_request.bits.AUDIO_TEST_PATTERN) {
3200 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3201 test_response.bits.ACK = 1;
3204 if (test_request.bits.PHY_TEST_PATTERN) {
3205 dp_test_send_phy_test_pattern(link);
3206 test_response.bits.ACK = 1;
3209 /* send request acknowledgment */
3210 if (test_response.bits.ACK)
3211 core_link_write_dpcd(
3215 sizeof(test_response));
3218 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
3220 union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
3221 union device_service_irq device_service_clear = { { 0 } };
3222 enum dc_status result;
3223 bool status = false;
3224 struct pipe_ctx *pipe_ctx;
3228 *out_link_loss = false;
3229 /* For use cases related to down stream connection status change,
3230 * PSR and device auto test, refer to function handle_sst_hpd_irq
3233 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
3234 __func__, link->link_index);
3237 /* All the "handle_hpd_irq_xxx()" methods
3238 * should be called only after
3239 * dal_dpsst_ls_read_hpd_irq_data
3240 * Order of calls is important too
3242 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
3243 if (out_hpd_irq_dpcd_data)
3244 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
3246 if (result != DC_OK) {
3247 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
3252 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3253 device_service_clear.bits.AUTOMATED_TEST = 1;
3254 core_link_write_dpcd(
3256 DP_DEVICE_SERVICE_IRQ_VECTOR,
3257 &device_service_clear.raw,
3258 sizeof(device_service_clear.raw));
3259 device_service_clear.raw = 0;
3260 handle_automated_test(link);
3264 if (!allow_hpd_rx_irq(link)) {
3265 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3266 __func__, link->link_index);
3270 if (handle_hpd_irq_psr_sink(link))
3271 /* PSR-related error was detected and handled */
3274 /* If PSR-related error handled, Main link may be off,
3275 * so do not handle as a normal sink status change interrupt.
3278 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3281 /* check if we have MST msg and return since we poll for it */
3282 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3285 /* For now we only handle 'Downstream port status' case.
3286 * If we got sink count changed it means
3287 * Downstream port status changed,
3288 * then DM should call DC to do the detection.
3289 * NOTE: Do not handle link loss on eDP since it is internal link*/
3290 if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3291 hpd_rx_irq_check_link_loss_status(
3293 &hpd_irq_dpcd_data)) {
3294 /* Connectivity log: link loss */
3295 CONN_DATA_LINK_LOSS(link,
3296 hpd_irq_dpcd_data.raw,
3297 sizeof(hpd_irq_dpcd_data),
3300 for (i = 0; i < MAX_PIPES; i++) {
3301 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3302 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3306 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3310 for (i = 0; i < MAX_PIPES; i++) {
3311 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3312 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3313 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3314 core_link_disable_stream(pipe_ctx);
3317 for (i = 0; i < MAX_PIPES; i++) {
3318 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3319 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3320 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3321 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3326 *out_link_loss = true;
3329 if (link->type == dc_connection_sst_branch &&
3330 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3331 != link->dpcd_sink_count)
3334 /* reasons for HPD RX:
3335 * 1. Link Loss - ie Re-train the Link
3336 * 2. MST sideband message
3337 * 3. Automated Test - ie. Internal Commit
3338 * 4. CP (copy protection) - (not interesting for DM???)
3340 * 6. Downstream Port status changed
3341 * -ie. Detect - this the only one
3342 * which is interesting for DM because
3343 * it must call dc_link_detect.
3348 /*query dpcd for version and mst cap addresses*/
3349 bool is_mst_supported(struct dc_link *link)
3352 enum dc_status st = DC_OK;
3356 if (link->preferred_training_settings.mst_enable &&
3357 *link->preferred_training_settings.mst_enable == false) {
3364 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3367 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3369 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3370 &cap.raw, sizeof(cap));
3371 if (st == DC_OK && cap.bits.MST_CAP == 1)
3378 bool is_dp_active_dongle(const struct dc_link *link)
3380 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
3381 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
3384 bool is_dp_branch_device(const struct dc_link *link)
3386 return link->dpcd_caps.is_branch_dev;
3389 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3392 case DOWN_STREAM_MAX_8BPC:
3394 case DOWN_STREAM_MAX_10BPC:
3396 case DOWN_STREAM_MAX_12BPC:
3398 case DOWN_STREAM_MAX_16BPC:
3407 static void read_dp_device_vendor_id(struct dc_link *link)
3409 struct dp_device_vendor_id dp_id;
3411 /* read IEEE branch device id */
3412 core_link_read_dpcd(
3418 link->dpcd_caps.branch_dev_id =
3419 (dp_id.ieee_oui[0] << 16) +
3420 (dp_id.ieee_oui[1] << 8) +
3424 link->dpcd_caps.branch_dev_name,
3425 dp_id.ieee_device_id,
3426 sizeof(dp_id.ieee_device_id));
3431 static void get_active_converter_info(
3432 uint8_t data, struct dc_link *link)
3434 union dp_downstream_port_present ds_port = { .byte = data };
3435 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3437 /* decode converter info*/
3438 if (!ds_port.fields.PORT_PRESENT) {
3439 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3440 ddc_service_set_dongle_type(link->ddc,
3441 link->dpcd_caps.dongle_type);
3442 link->dpcd_caps.is_branch_dev = false;
3446 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3447 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3449 switch (ds_port.fields.PORT_TYPE) {
3450 case DOWNSTREAM_VGA:
3451 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3453 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3454 /* At this point we don't know is it DVI or HDMI or DP++,
3456 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3459 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3463 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3464 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3465 union dwnstream_port_caps_byte0 *port_caps =
3466 (union dwnstream_port_caps_byte0 *)det_caps;
3467 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3468 det_caps, sizeof(det_caps)) == DC_OK) {
3470 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3471 /*Handle DP case as DONGLE_NONE*/
3472 case DOWN_STREAM_DETAILED_DP:
3473 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3475 case DOWN_STREAM_DETAILED_VGA:
3476 link->dpcd_caps.dongle_type =
3477 DISPLAY_DONGLE_DP_VGA_CONVERTER;
3479 case DOWN_STREAM_DETAILED_DVI:
3480 link->dpcd_caps.dongle_type =
3481 DISPLAY_DONGLE_DP_DVI_CONVERTER;
3483 case DOWN_STREAM_DETAILED_HDMI:
3484 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3485 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3486 link->dpcd_caps.dongle_type =
3487 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3489 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3490 if (ds_port.fields.DETAILED_CAPS) {
3492 union dwnstream_port_caps_byte3_hdmi
3493 hdmi_caps = {.raw = det_caps[3] };
3494 union dwnstream_port_caps_byte2
3495 hdmi_color_caps = {.raw = det_caps[2] };
3496 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3499 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3500 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3501 /*YCBCR capability only for HDMI case*/
3502 if (port_caps->bits.DWN_STRM_PORTX_TYPE
3503 == DOWN_STREAM_DETAILED_HDMI) {
3504 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3505 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3506 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3507 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3508 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3509 hdmi_caps.bits.YCrCr422_CONVERSION;
3510 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3511 hdmi_caps.bits.YCrCr420_CONVERSION;
3514 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3515 translate_dpcd_max_bpc(
3516 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3518 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3519 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3527 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3530 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3532 core_link_read_dpcd(
3534 DP_BRANCH_REVISION_START,
3535 (uint8_t *)&dp_hw_fw_revision,
3536 sizeof(dp_hw_fw_revision));
3538 link->dpcd_caps.branch_hw_revision =
3539 dp_hw_fw_revision.ieee_hw_rev;
3542 link->dpcd_caps.branch_fw_revision,
3543 dp_hw_fw_revision.ieee_fw_rev,
3544 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3548 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3553 if (!link->dpcd_caps.dpcd_rev.raw) {
3555 dp_receiver_power_ctrl(link, true);
3556 core_link_read_dpcd(link, DP_DPCD_REV,
3558 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3561 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3564 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3565 switch (link->dpcd_caps.branch_dev_id) {
3566 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3567 * all internal circuits including AUX communication preventing
3568 * reading DPCD table and EDID (spec violation).
3569 * Encoder will skip DP RX power down on disable_output to
3570 * keep receiver powered all the time.*/
3571 case DP_BRANCH_DEVICE_ID_0010FA:
3572 case DP_BRANCH_DEVICE_ID_0080E1:
3573 case DP_BRANCH_DEVICE_ID_00E04C:
3574 link->wa_flags.dp_keep_receiver_powered = true;
3577 /* TODO: May need work around for other dongles. */
3579 link->wa_flags.dp_keep_receiver_powered = false;
3583 link->wa_flags.dp_keep_receiver_powered = false;
3586 /* Read additional sink caps defined in source specific DPCD area
3587 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3589 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3596 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3599 link->dpcd_sink_ext_caps.raw = dpcd_data;
3603 bool dp_retrieve_lttpr_cap(struct dc_link *link)
3605 uint8_t lttpr_dpcd_data[6];
3606 bool vbios_lttpr_enable = false;
3607 bool vbios_lttpr_interop = false;
3608 struct dc_bios *bios = link->dc->ctx->dc_bios;
3609 enum dc_status status = DC_ERROR_UNEXPECTED;
3610 bool is_lttpr_present = false;
3612 memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3613 /* Query BIOS to determine if LTTPR functionality is forced on by system */
3614 if (bios->funcs->get_lttpr_caps) {
3615 enum bp_result bp_query_result;
3616 uint8_t is_vbios_lttpr_enable = 0;
3618 bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable);
3619 vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
3622 if (bios->funcs->get_lttpr_interop) {
3623 enum bp_result bp_query_result;
3624 uint8_t is_vbios_interop_enabled = 0;
3626 bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled);
3627 vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
3631 * Logic to determine LTTPR mode
3633 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3634 if (vbios_lttpr_enable && vbios_lttpr_interop)
3635 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3636 else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3637 if (link->dc->config.allow_lttpr_non_transparent_mode)
3638 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3640 link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3641 } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3642 if (!link->dc->config.allow_lttpr_non_transparent_mode
3643 || !link->dc->caps.extended_aux_timeout_support)
3644 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3646 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3649 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
3650 /* By reading LTTPR capability, RX assumes that we will enable
3651 * LTTPR extended aux timeout if LTTPR is present.
3653 status = core_link_read_dpcd(
3655 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3657 sizeof(lttpr_dpcd_data));
3658 if (status != DC_OK) {
3659 dm_error("%s: Read LTTPR caps data failed.\n", __func__);
3663 link->dpcd_caps.lttpr_caps.revision.raw =
3664 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3665 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3667 link->dpcd_caps.lttpr_caps.max_link_rate =
3668 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3669 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3671 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3672 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3673 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3675 link->dpcd_caps.lttpr_caps.max_lane_count =
3676 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3677 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3679 link->dpcd_caps.lttpr_caps.mode =
3680 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3681 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3683 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3684 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3685 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3687 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
3688 is_lttpr_present = (dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
3689 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3690 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3691 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3692 if (is_lttpr_present) {
3693 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3694 configure_lttpr_mode_transparent(link);
3696 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3698 return is_lttpr_present;
3701 static bool retrieve_link_cap(struct dc_link *link)
3703 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3704 * which means size 16 will be good for both of those DPCD register block reads
3706 uint8_t dpcd_data[16];
3707 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3709 uint8_t dpcd_dprx_data = '\0';
3710 uint8_t dpcd_power_state = '\0';
3712 struct dp_device_vendor_id sink_id;
3713 union down_stream_port_count down_strm_port_count;
3714 union edp_configuration_cap edp_config_cap;
3715 union dp_downstream_port_present ds_port = { 0 };
3716 enum dc_status status = DC_ERROR_UNEXPECTED;
3717 uint32_t read_dpcd_retry_cnt = 3;
3719 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3720 const uint32_t post_oui_delay = 30; // 30ms
3721 bool is_lttpr_present = false;
3723 memset(dpcd_data, '\0', sizeof(dpcd_data));
3724 memset(&down_strm_port_count,
3725 '\0', sizeof(union down_stream_port_count));
3726 memset(&edp_config_cap, '\0',
3727 sizeof(union edp_configuration_cap));
3729 /* if extended timeout is supported in hardware,
3730 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3731 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3733 dc_link_aux_try_to_configure_timeout(link->ddc,
3734 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3736 is_lttpr_present = dp_retrieve_lttpr_cap(link);
3738 status = core_link_read_dpcd(link, DP_SET_POWER,
3739 &dpcd_power_state, sizeof(dpcd_power_state));
3741 /* Delay 1 ms if AUX CH is in power down state. Based on spec
3742 * section 2.3.1.2, if AUX CH may be powered down due to
3743 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3744 * signal and may need up to 1 ms before being able to reply.
3746 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3749 dpcd_set_source_specific_data(link);
3750 /* Sink may need to configure internals based on vendor, so allow some
3751 * time before proceeding with possibly vendor specific transactions
3753 msleep(post_oui_delay);
3755 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3756 status = core_link_read_dpcd(
3761 if (status == DC_OK)
3765 if (status != DC_OK) {
3766 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
3770 if (!is_lttpr_present)
3771 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3774 union training_aux_rd_interval aux_rd_interval;
3776 aux_rd_interval.raw =
3777 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3779 link->dpcd_caps.ext_receiver_cap_field_present =
3780 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3782 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3783 uint8_t ext_cap_data[16];
3785 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3786 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3787 status = core_link_read_dpcd(
3791 sizeof(ext_cap_data));
3792 if (status == DC_OK) {
3793 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3797 if (status != DC_OK)
3798 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3802 link->dpcd_caps.dpcd_rev.raw =
3803 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3805 if (link->dpcd_caps.ext_receiver_cap_field_present) {
3806 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3807 status = core_link_read_dpcd(
3809 DP_DPRX_FEATURE_ENUMERATION_LIST,
3811 sizeof(dpcd_dprx_data));
3812 if (status == DC_OK)
3816 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3818 if (status != DC_OK)
3819 dm_error("%s: Read DPRX caps data failed.\n", __func__);
3823 link->dpcd_caps.dprx_feature.raw = 0;
3827 /* Error condition checking...
3828 * It is impossible for Sink to report Max Lane Count = 0.
3829 * It is possible for Sink to report Max Link Rate = 0, if it is
3830 * an eDP device that is reporting specialized link rates in the
3831 * SUPPORTED_LINK_RATE table.
3833 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3836 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3839 read_dp_device_vendor_id(link);
3841 get_active_converter_info(ds_port.byte, link);
3843 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3845 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3848 link->dpcd_caps.allow_invalid_MSA_timing_param =
3849 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3851 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3852 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3854 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3855 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3857 link->reported_link_cap.lane_count =
3858 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3859 link->reported_link_cap.link_rate = dpcd_data[
3860 DP_MAX_LINK_RATE - DP_DPCD_REV];
3861 link->reported_link_cap.link_spread =
3862 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3863 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3865 edp_config_cap.raw = dpcd_data[
3866 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3867 link->dpcd_caps.panel_mode_edp =
3868 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3869 link->dpcd_caps.dpcd_display_control_capable =
3870 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3872 link->test_pattern_enabled = false;
3873 link->compliance_test_state.raw = 0;
3875 /* read sink count */
3876 core_link_read_dpcd(link,
3878 &link->dpcd_caps.sink_count.raw,
3879 sizeof(link->dpcd_caps.sink_count.raw));
3881 /* read sink ieee oui */
3882 core_link_read_dpcd(link,
3884 (uint8_t *)(&sink_id),
3887 link->dpcd_caps.sink_dev_id =
3888 (sink_id.ieee_oui[0] << 16) +
3889 (sink_id.ieee_oui[1] << 8) +
3890 (sink_id.ieee_oui[2]);
3893 link->dpcd_caps.sink_dev_id_str,
3894 sink_id.ieee_device_id,
3895 sizeof(sink_id.ieee_device_id));
3897 /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3899 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3901 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3902 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3903 sizeof(str_mbp_2017))) {
3904 link->reported_link_cap.link_rate = 0x0c;
3908 core_link_read_dpcd(
3910 DP_SINK_HW_REVISION_START,
3911 (uint8_t *)&dp_hw_fw_revision,
3912 sizeof(dp_hw_fw_revision));
3914 link->dpcd_caps.sink_hw_revision =
3915 dp_hw_fw_revision.ieee_hw_rev;
3918 link->dpcd_caps.sink_fw_revision,
3919 dp_hw_fw_revision.ieee_fw_rev,
3920 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3922 memset(&link->dpcd_caps.dsc_caps, '\0',
3923 sizeof(link->dpcd_caps.dsc_caps));
3924 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3925 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3926 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3927 status = core_link_read_dpcd(
3930 &link->dpcd_caps.fec_cap.raw,
3931 sizeof(link->dpcd_caps.fec_cap.raw));
3932 status = core_link_read_dpcd(
3935 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3936 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3937 status = core_link_read_dpcd(
3939 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3940 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3941 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3944 if (!dpcd_read_sink_ext_caps(link))
3945 link->dpcd_sink_ext_caps.raw = 0;
3947 /* Connectivity log: detection */
3948 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3953 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3955 uint8_t dpcd_data[16];
3956 uint32_t read_dpcd_retry_cnt = 3;
3957 enum dc_status status = DC_ERROR_UNEXPECTED;
3958 union dp_downstream_port_present ds_port = { 0 };
3959 union down_stream_port_count down_strm_port_count;
3960 union edp_configuration_cap edp_config_cap;
3964 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3965 status = core_link_read_dpcd(
3970 if (status == DC_OK)
3974 link->dpcd_caps.dpcd_rev.raw =
3975 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3977 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3980 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3983 get_active_converter_info(ds_port.byte, link);
3985 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3988 link->dpcd_caps.allow_invalid_MSA_timing_param =
3989 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3991 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3992 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3994 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3995 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3997 link->reported_link_cap.lane_count =
3998 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3999 link->reported_link_cap.link_rate = dpcd_data[
4000 DP_MAX_LINK_RATE - DP_DPCD_REV];
4001 link->reported_link_cap.link_spread =
4002 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
4003 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
4005 edp_config_cap.raw = dpcd_data[
4006 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4007 link->dpcd_caps.panel_mode_edp =
4008 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
4009 link->dpcd_caps.dpcd_display_control_capable =
4010 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4015 bool detect_dp_sink_caps(struct dc_link *link)
4017 return retrieve_link_cap(link);
4019 /* dc init_hw has power encoder using default
4020 * signal for connector. For native DP, no
4021 * need to power up encoder again. If not native
4022 * DP, hw_init may need check signal or power up
4025 /* TODO save sink caps in link->sink */
4028 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
4030 enum dc_link_rate link_rate;
4031 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
4032 switch (link_rate_in_khz) {
4034 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
4037 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
4040 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
4043 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
4046 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2) - 3.24 Gbps/Lane
4049 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
4052 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2) - 5.40 Gbps/Lane
4055 link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3) - 8.10 Gbps/Lane
4058 link_rate = LINK_RATE_UNKNOWN;
4064 void detect_edp_sink_caps(struct dc_link *link)
4066 uint8_t supported_link_rates[16];
4068 uint32_t link_rate_in_khz;
4069 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
4070 uint8_t backlight_adj_cap;
4072 retrieve_link_cap(link);
4073 link->dpcd_caps.edp_supported_link_rates_count = 0;
4074 memset(supported_link_rates, 0, sizeof(supported_link_rates));
4077 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
4078 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
4080 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
4081 (link->dc->debug.optimize_edp_link_rate ||
4082 link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
4083 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
4084 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
4085 supported_link_rates, sizeof(supported_link_rates));
4087 for (entry = 0; entry < 16; entry += 2) {
4088 // DPCD register reports per-lane link rate = 16-bit link rate capability
4089 // value X 200 kHz. Need multiplier to find link rate in kHz.
4090 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
4091 supported_link_rates[entry]) * 200;
4093 if (link_rate_in_khz != 0) {
4094 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
4095 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
4096 link->dpcd_caps.edp_supported_link_rates_count++;
4098 if (link->reported_link_cap.link_rate < link_rate)
4099 link->reported_link_cap.link_rate = link_rate;
4103 link->verified_link_cap = link->reported_link_cap;
4105 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
4106 &backlight_adj_cap, sizeof(backlight_adj_cap));
4108 link->dpcd_caps.dynamic_backlight_capable_edp =
4109 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
4111 dc_link_set_default_brightness_aux(link);
4114 void dc_link_dp_enable_hpd(const struct dc_link *link)
4116 struct link_encoder *encoder = link->link_enc;
4118 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4119 encoder->funcs->enable_hpd(encoder);
4122 void dc_link_dp_disable_hpd(const struct dc_link *link)
4124 struct link_encoder *encoder = link->link_enc;
4126 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4127 encoder->funcs->disable_hpd(encoder);
4130 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
4132 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
4133 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
4134 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4140 static void set_crtc_test_pattern(struct dc_link *link,
4141 struct pipe_ctx *pipe_ctx,
4142 enum dp_test_pattern test_pattern,
4143 enum dp_test_pattern_color_space test_pattern_color_space)
4145 enum controller_dp_test_pattern controller_test_pattern;
4146 enum dc_color_depth color_depth = pipe_ctx->
4147 stream->timing.display_color_depth;
4148 struct bit_depth_reduction_params params;
4149 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
4150 int width = pipe_ctx->stream->timing.h_addressable +
4151 pipe_ctx->stream->timing.h_border_left +
4152 pipe_ctx->stream->timing.h_border_right;
4153 int height = pipe_ctx->stream->timing.v_addressable +
4154 pipe_ctx->stream->timing.v_border_bottom +
4155 pipe_ctx->stream->timing.v_border_top;
4157 memset(¶ms, 0, sizeof(params));
4159 switch (test_pattern) {
4160 case DP_TEST_PATTERN_COLOR_SQUARES:
4161 controller_test_pattern =
4162 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
4164 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4165 controller_test_pattern =
4166 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
4168 case DP_TEST_PATTERN_VERTICAL_BARS:
4169 controller_test_pattern =
4170 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
4172 case DP_TEST_PATTERN_HORIZONTAL_BARS:
4173 controller_test_pattern =
4174 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
4176 case DP_TEST_PATTERN_COLOR_RAMP:
4177 controller_test_pattern =
4178 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
4181 controller_test_pattern =
4182 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
4186 switch (test_pattern) {
4187 case DP_TEST_PATTERN_COLOR_SQUARES:
4188 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4189 case DP_TEST_PATTERN_VERTICAL_BARS:
4190 case DP_TEST_PATTERN_HORIZONTAL_BARS:
4191 case DP_TEST_PATTERN_COLOR_RAMP:
4193 /* disable bit depth reduction */
4194 pipe_ctx->stream->bit_depth_params = params;
4195 opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms);
4196 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4197 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4198 controller_test_pattern, color_depth);
4199 else if (link->dc->hwss.set_disp_pattern_generator) {
4200 struct pipe_ctx *odm_pipe;
4201 enum controller_dp_color_space controller_color_space;
4204 int dpg_width = width;
4206 switch (test_pattern_color_space) {
4207 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4208 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4210 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4211 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4213 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4214 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4216 case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4218 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4219 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4224 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4226 dpg_width = width / opp_cnt;
4229 link->dc->hwss.set_disp_pattern_generator(link->dc,
4231 controller_test_pattern,
4232 controller_color_space,
4239 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4240 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4242 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms);
4243 link->dc->hwss.set_disp_pattern_generator(link->dc,
4245 controller_test_pattern,
4246 controller_color_space,
4257 case DP_TEST_PATTERN_VIDEO_MODE:
4259 /* restore bitdepth reduction */
4260 resource_build_bit_depth_reduction_params(pipe_ctx->stream, ¶ms);
4261 pipe_ctx->stream->bit_depth_params = params;
4262 opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms);
4263 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4264 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4265 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4267 else if (link->dc->hwss.set_disp_pattern_generator) {
4268 struct pipe_ctx *odm_pipe;
4270 int dpg_width = width;
4272 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4275 dpg_width = width / opp_cnt;
4276 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4277 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4279 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms);
4280 link->dc->hwss.set_disp_pattern_generator(link->dc,
4282 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4283 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4290 link->dc->hwss.set_disp_pattern_generator(link->dc,
4292 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4293 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4308 bool dc_link_dp_set_test_pattern(
4309 struct dc_link *link,
4310 enum dp_test_pattern test_pattern,
4311 enum dp_test_pattern_color_space test_pattern_color_space,
4312 const struct link_training_settings *p_link_settings,
4313 const unsigned char *p_custom_pattern,
4314 unsigned int cust_pattern_size)
4316 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4317 struct pipe_ctx *pipe_ctx = NULL;
4320 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4321 union dpcd_training_pattern training_pattern;
4322 enum dpcd_phy_test_patterns pattern;
4324 memset(&training_pattern, 0, sizeof(training_pattern));
4326 for (i = 0; i < MAX_PIPES; i++) {
4327 if (pipes[i].stream == NULL)
4330 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4331 pipe_ctx = &pipes[i];
4336 if (pipe_ctx == NULL)
4339 /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4340 if (link->test_pattern_enabled && test_pattern ==
4341 DP_TEST_PATTERN_VIDEO_MODE) {
4342 /* Set CRTC Test Pattern */
4343 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4344 dp_set_hw_test_pattern(link, test_pattern,
4345 (uint8_t *)p_custom_pattern,
4346 (uint32_t)cust_pattern_size);
4348 /* Unblank Stream */
4349 link->dc->hwss.unblank_stream(
4351 &link->verified_link_cap);
4352 /* TODO:m_pHwss->MuteAudioEndpoint
4353 * (pPathMode->pDisplayPath, false);
4356 /* Reset Test Pattern state */
4357 link->test_pattern_enabled = false;
4362 /* Check for PHY Test Patterns */
4363 if (is_dp_phy_pattern(test_pattern)) {
4364 /* Set DPCD Lane Settings before running test pattern */
4365 if (p_link_settings != NULL) {
4366 dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4367 dpcd_set_lane_settings(link, p_link_settings, DPRX);
4370 /* Blank stream if running test pattern */
4371 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4374 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4377 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4380 dp_set_hw_test_pattern(link, test_pattern,
4381 (uint8_t *)p_custom_pattern,
4382 (uint32_t)cust_pattern_size);
4384 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4385 /* Set Test Pattern state */
4386 link->test_pattern_enabled = true;
4387 if (p_link_settings != NULL)
4388 dpcd_set_link_settings(link,
4392 switch (test_pattern) {
4393 case DP_TEST_PATTERN_VIDEO_MODE:
4394 pattern = PHY_TEST_PATTERN_NONE;
4396 case DP_TEST_PATTERN_D102:
4397 pattern = PHY_TEST_PATTERN_D10_2;
4399 case DP_TEST_PATTERN_SYMBOL_ERROR:
4400 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4402 case DP_TEST_PATTERN_PRBS7:
4403 pattern = PHY_TEST_PATTERN_PRBS7;
4405 case DP_TEST_PATTERN_80BIT_CUSTOM:
4406 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4408 case DP_TEST_PATTERN_CP2520_1:
4409 pattern = PHY_TEST_PATTERN_CP2520_1;
4411 case DP_TEST_PATTERN_CP2520_2:
4412 pattern = PHY_TEST_PATTERN_CP2520_2;
4414 case DP_TEST_PATTERN_CP2520_3:
4415 pattern = PHY_TEST_PATTERN_CP2520_3;
4421 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4422 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4425 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4426 /* tell receiver that we are sending qualification
4427 * pattern DP 1.2 or later - DP receiver's link quality
4428 * pattern is set using DPCD LINK_QUAL_LANEx_SET
4429 * register (0x10B~0x10E)\
4431 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4432 link_qual_pattern[lane] =
4433 (unsigned char)(pattern);
4435 core_link_write_dpcd(link,
4436 DP_LINK_QUAL_LANE0_SET,
4438 sizeof(link_qual_pattern));
4439 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4440 link->dpcd_caps.dpcd_rev.raw == 0) {
4441 /* tell receiver that we are sending qualification
4442 * pattern DP 1.1a or earlier - DP receiver's link
4443 * quality pattern is set using
4444 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4445 * register (0x102). We will use v_1.3 when we are
4446 * setting test pattern for DP 1.1.
4448 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4449 &training_pattern.raw,
4450 sizeof(training_pattern));
4451 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4452 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4453 &training_pattern.raw,
4454 sizeof(training_pattern));
4457 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4459 switch (test_pattern_color_space) {
4460 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4461 color_space = COLOR_SPACE_SRGB;
4462 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4463 color_space = COLOR_SPACE_SRGB_LIMITED;
4466 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4467 color_space = COLOR_SPACE_YCBCR601;
4468 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4469 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4471 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4472 color_space = COLOR_SPACE_YCBCR709;
4473 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4474 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4480 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4481 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4482 union dmub_hw_lock_flags hw_locks = { 0 };
4483 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4485 hw_locks.bits.lock_dig = 1;
4486 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4488 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4493 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4494 pipe_ctx->stream_res.tg);
4497 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4498 /* update MSA to requested color space */
4499 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4500 &pipe_ctx->stream->timing,
4502 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4503 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4505 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4506 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4507 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4509 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4510 resource_build_info_frame(pipe_ctx);
4511 link->dc->hwss.update_info_frame(pipe_ctx);
4515 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4516 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4517 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4518 CRTC_STATE_VACTIVE);
4519 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4521 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4522 CRTC_STATE_VACTIVE);
4524 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4525 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4526 union dmub_hw_lock_flags hw_locks = { 0 };
4527 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4529 hw_locks.bits.lock_dig = 1;
4530 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4532 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4537 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4538 pipe_ctx->stream_res.tg);
4541 /* Set Test Pattern state */
4542 link->test_pattern_enabled = true;
4548 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4550 unsigned char mstmCntl;
4552 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4554 mstmCntl |= DP_MST_EN;
4556 mstmCntl &= (~DP_MST_EN);
4558 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4561 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4563 union dpcd_edp_config edp_config_set;
4564 bool panel_mode_edp = false;
4566 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4568 if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4570 switch (panel_mode) {
4571 case DP_PANEL_MODE_EDP:
4572 case DP_PANEL_MODE_SPECIAL:
4573 panel_mode_edp = true;
4580 /*set edp panel mode in receiver*/
4581 core_link_read_dpcd(
4583 DP_EDP_CONFIGURATION_SET,
4584 &edp_config_set.raw,
4585 sizeof(edp_config_set.raw));
4587 if (edp_config_set.bits.PANEL_MODE_EDP
4588 != panel_mode_edp) {
4589 enum dc_status result;
4591 edp_config_set.bits.PANEL_MODE_EDP =
4593 result = core_link_write_dpcd(
4595 DP_EDP_CONFIGURATION_SET,
4596 &edp_config_set.raw,
4597 sizeof(edp_config_set.raw));
4599 ASSERT(result == DC_OK);
4602 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4603 "eDP panel mode enabled: %d \n",
4605 link->dpcd_caps.panel_mode_edp,
4609 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4611 /* We need to explicitly check that connector
4612 * is not DP. Some Travis_VGA get reported
4613 * by video bios as DP.
4615 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4617 switch (link->dpcd_caps.branch_dev_id) {
4618 case DP_BRANCH_DEVICE_ID_0022B9:
4619 /* alternate scrambler reset is required for Travis
4620 * for the case when external chip does not
4621 * provide sink device id, alternate scrambler
4622 * scheme will be overriden later by querying
4626 link->dpcd_caps.branch_dev_name,
4627 DP_VGA_LVDS_CONVERTER_ID_2,
4630 branch_dev_name)) == 0) {
4631 return DP_PANEL_MODE_SPECIAL;
4634 case DP_BRANCH_DEVICE_ID_00001A:
4635 /* alternate scrambler reset is required for Travis
4636 * for the case when external chip does not provide
4637 * sink device id, alternate scrambler scheme will
4638 * be overriden later by querying Encoder feature
4640 if (strncmp(link->dpcd_caps.branch_dev_name,
4641 DP_VGA_LVDS_CONVERTER_ID_3,
4644 branch_dev_name)) == 0) {
4645 return DP_PANEL_MODE_SPECIAL;
4653 if (link->dpcd_caps.panel_mode_edp) {
4654 return DP_PANEL_MODE_EDP;
4657 return DP_PANEL_MODE_DEFAULT;
4660 enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
4662 /* FEC has to be "set ready" before the link training.
4663 * The policy is to always train with FEC
4664 * if the sink supports it and leave it enabled on link.
4665 * If FEC is not supported, disable it.
4667 struct link_encoder *link_enc = NULL;
4668 enum dc_status status = DC_OK;
4669 uint8_t fec_config = 0;
4671 /* Access link encoder based on whether it is statically
4672 * or dynamically assigned to a link.
4674 if (link->is_dig_mapping_flexible &&
4675 link->dc->res_pool->funcs->link_encs_assign)
4676 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
4678 link_enc = link->link_enc;
4681 if (!dc_link_should_enable_fec(link))
4684 if (link_enc->funcs->fec_set_ready &&
4685 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4688 status = core_link_write_dpcd(link,
4689 DP_FEC_CONFIGURATION,
4691 sizeof(fec_config));
4692 if (status == DC_OK) {
4693 link_enc->funcs->fec_set_ready(link_enc, true);
4694 link->fec_state = dc_link_fec_ready;
4696 link_enc->funcs->fec_set_ready(link->link_enc, false);
4697 link->fec_state = dc_link_fec_not_ready;
4698 dm_error("dpcd write failed to set fec_ready");
4700 } else if (link->fec_state == dc_link_fec_ready) {
4702 status = core_link_write_dpcd(link,
4703 DP_FEC_CONFIGURATION,
4705 sizeof(fec_config));
4706 link_enc->funcs->fec_set_ready(link_enc, false);
4707 link->fec_state = dc_link_fec_not_ready;
4714 void dp_set_fec_enable(struct dc_link *link, bool enable)
4716 struct link_encoder *link_enc = NULL;
4718 /* Access link encoder based on whether it is statically
4719 * or dynamically assigned to a link.
4721 if (link->is_dig_mapping_flexible &&
4722 link->dc->res_pool->funcs->link_encs_assign)
4723 link_enc = link_enc_cfg_get_link_enc_used_by_link(
4724 link->dc->current_state, link);
4726 link_enc = link->link_enc;
4729 if (!dc_link_should_enable_fec(link))
4732 if (link_enc->funcs->fec_set_enable &&
4733 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4734 if (link->fec_state == dc_link_fec_ready && enable) {
4735 /* Accord to DP spec, FEC enable sequence can first
4736 * be transmitted anytime after 1000 LL codes have
4737 * been transmitted on the link after link training
4738 * completion. Using 1 lane RBR should have the maximum
4739 * time for transmitting 1000 LL codes which is 6.173 us.
4740 * So use 7 microseconds delay instead.
4743 link_enc->funcs->fec_set_enable(link_enc, true);
4744 link->fec_state = dc_link_fec_enabled;
4745 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4746 link_enc->funcs->fec_set_enable(link_enc, false);
4747 link->fec_state = dc_link_fec_ready;
4752 void dpcd_set_source_specific_data(struct dc_link *link)
4754 if (!link->dc->vendor_signature.is_valid) {
4755 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
4756 struct dpcd_amd_signature amd_signature = {0};
4757 struct dpcd_amd_device_id amd_device_id = {0};
4759 amd_device_id.device_id_byte1 =
4760 (uint8_t)(link->ctx->asic_id.chip_id);
4761 amd_device_id.device_id_byte2 =
4762 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4763 amd_device_id.dce_version =
4764 (uint8_t)(link->ctx->dce_version);
4765 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4766 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4768 core_link_read_dpcd(link, DP_SOURCE_OUI,
4769 (uint8_t *)(&amd_signature),
4770 sizeof(amd_signature));
4772 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4773 (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4774 (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4776 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4777 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4778 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4780 core_link_write_dpcd(link, DP_SOURCE_OUI,
4781 (uint8_t *)(&amd_signature),
4782 sizeof(amd_signature));
4785 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4786 (uint8_t *)(&amd_device_id),
4787 sizeof(amd_device_id));
4789 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4790 link->dc->caps.min_horizontal_blanking_period != 0) {
4792 uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4794 result_write_min_hblank = core_link_write_dpcd(link,
4795 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4796 sizeof(hblank_size));
4798 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4799 WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4800 "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4801 result_write_min_hblank,
4803 link->ctx->dce_version,
4804 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4805 link->dc->caps.min_horizontal_blanking_period,
4806 link->dpcd_caps.branch_dev_id,
4807 link->dpcd_caps.branch_dev_name[0],
4808 link->dpcd_caps.branch_dev_name[1],
4809 link->dpcd_caps.branch_dev_name[2],
4810 link->dpcd_caps.branch_dev_name[3],
4811 link->dpcd_caps.branch_dev_name[4],
4812 link->dpcd_caps.branch_dev_name[5]);
4814 core_link_write_dpcd(link, DP_SOURCE_OUI,
4815 link->dc->vendor_signature.data.raw,
4816 sizeof(link->dc->vendor_signature.data.raw));
4820 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4822 uint32_t backlight_millinits,
4823 uint32_t transition_time_in_ms)
4825 struct dpcd_source_backlight_set dpcd_backlight_set;
4826 uint8_t backlight_control = isHDR ? 1 : 0;
4828 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4829 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4832 // OLEDs have no PWM, they can only use AUX
4833 if (link->dpcd_sink_ext_caps.bits.oled == 1)
4834 backlight_control = 1;
4836 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4837 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4840 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4841 (uint8_t *)(&dpcd_backlight_set),
4842 sizeof(dpcd_backlight_set)) != DC_OK)
4845 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4846 &backlight_control, 1) != DC_OK)
4852 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4853 uint32_t *backlight_millinits_avg,
4854 uint32_t *backlight_millinits_peak)
4856 union dpcd_source_backlight_get dpcd_backlight_get;
4858 memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4860 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4861 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4864 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4865 dpcd_backlight_get.raw,
4866 sizeof(union dpcd_source_backlight_get)) != DC_OK)
4869 *backlight_millinits_avg =
4870 dpcd_backlight_get.bytes.backlight_millinits_avg;
4871 *backlight_millinits_peak =
4872 dpcd_backlight_get.bytes.backlight_millinits_peak;
4874 /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4875 if (*backlight_millinits_avg == 0 ||
4876 *backlight_millinits_avg > *backlight_millinits_peak)
4882 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4884 uint8_t backlight_enable = enable ? 1 : 0;
4886 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4887 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4890 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4891 &backlight_enable, 1) != DC_OK)
4897 // we read default from 0x320 because we expect BIOS wrote it there
4898 // regular get_backlight_nit reads from panel set at 0x326
4899 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4901 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4902 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4905 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4906 (uint8_t *) backlight_millinits,
4907 sizeof(uint32_t)) != DC_OK)
4913 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4915 uint32_t default_backlight;
4918 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4919 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4920 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4921 default_backlight = 150000;
4922 // if < 5 nits or > 5000, it might be wrong readback
4923 if (default_backlight < 5000 || default_backlight > 5000000)
4924 default_backlight = 150000; //
4926 return dc_link_set_backlight_level_nits(link, true,
4927 default_backlight, 0);
4932 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4934 struct dc_link_settings link_setting;
4935 uint8_t link_bw_set;
4936 uint8_t link_rate_set;
4938 union lane_count_set lane_count_set = { {0} };
4940 ASSERT(link || crtc_timing); // invalid input
4942 if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4943 !link->dc->debug.optimize_edp_link_rate)
4947 // Read DPCD 00100h to find if standard link rates are set
4948 core_link_read_dpcd(link, DP_LINK_BW_SET,
4949 &link_bw_set, sizeof(link_bw_set));
4952 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
4956 // Read DPCD 00115h to find the edp link rate set used
4957 core_link_read_dpcd(link, DP_LINK_RATE_SET,
4958 &link_rate_set, sizeof(link_rate_set));
4960 // Read DPCD 00101h to find out the number of lanes currently set
4961 core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4962 &lane_count_set.raw, sizeof(lane_count_set));
4964 req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4966 decide_edp_link_settings(link, &link_setting, req_bw);
4968 if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
4969 lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4970 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
4974 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
4978 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
4980 if ((link_settings->link_rate >= LINK_RATE_LOW) &&
4981 (link_settings->link_rate <= LINK_RATE_HIGH3))
4982 return DP_8b_10b_ENCODING;
4983 return DP_UNKNOWN_ENCODING;