1 /* Copyright 2015 Advanced Micro Devices, Inc. */
2 #include "dm_services.h"
4 #include "dc_link_dp.h"
5 #include "dm_helpers.h"
10 #include "inc/core_types.h"
11 #include "link_hwss.h"
12 #include "dc_link_ddc.h"
13 #include "core_status.h"
14 #include "dpcd_defs.h"
15 #include "dc_dmub_srv.h"
16 #include "dce/dmub_hw_lock_mgr.h"
22 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
24 /* maximum pre emphasis level allowed for each voltage swing level*/
25 static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
29 PRE_EMPHASIS_DISABLED };
32 POST_LT_ADJ_REQ_LIMIT = 6,
33 POST_LT_ADJ_REQ_TIMEOUT = 200
37 LINK_TRAINING_MAX_RETRY_COUNT = 5,
38 /* to avoid infinite loop where-in the receiver
39 * switches between different VS
41 LINK_TRAINING_MAX_CR_RETRY = 100
44 static bool decide_fallback_link_setting(
45 struct dc_link_settings initial_link_settings,
46 struct dc_link_settings *current_link_setting,
47 enum link_training_result training_result);
48 static struct dc_link_settings get_common_supported_link_settings(
49 struct dc_link_settings link_setting_a,
50 struct dc_link_settings link_setting_b);
52 static uint32_t get_training_aux_rd_interval(
54 uint32_t default_wait_in_micro_secs)
56 union training_aux_rd_interval training_rd_interval;
58 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
60 /* overwrite the delay if rev > 1.1*/
61 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
62 /* DP 1.2 or later - retrieve delay through
63 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
66 DP_TRAINING_AUX_RD_INTERVAL,
67 (uint8_t *)&training_rd_interval,
68 sizeof(training_rd_interval));
70 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
71 default_wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
74 return default_wait_in_micro_secs;
77 static void wait_for_training_aux_rd_interval(
79 uint32_t wait_in_micro_secs)
81 udelay(wait_in_micro_secs);
83 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
88 static void dpcd_set_training_pattern(
90 union dpcd_training_pattern dpcd_pattern)
94 DP_TRAINING_PATTERN_SET,
98 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
100 DP_TRAINING_PATTERN_SET,
101 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
104 static enum dc_dp_training_pattern get_supported_tp(struct dc_link *link)
106 enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
107 struct encoder_feature_support *features = &link->link_enc->features;
108 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
110 if (features->flags.bits.IS_TPS3_CAPABLE)
111 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
113 if (features->flags.bits.IS_TPS4_CAPABLE)
114 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
116 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
117 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
118 return DP_TRAINING_PATTERN_SEQUENCE_4;
120 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
121 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
122 return DP_TRAINING_PATTERN_SEQUENCE_3;
124 return DP_TRAINING_PATTERN_SEQUENCE_2;
127 static void dpcd_set_link_settings(
128 struct dc_link *link,
129 const struct link_training_settings *lt_settings)
133 union down_spread_ctrl downspread = { {0} };
134 union lane_count_set lane_count_set = { {0} };
135 enum dc_dp_training_pattern dp_tr_pattern;
137 downspread.raw = (uint8_t)
138 (lt_settings->link_settings.link_spread);
140 lane_count_set.bits.LANE_COUNT_SET =
141 lt_settings->link_settings.lane_count;
143 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
144 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
146 dp_tr_pattern = get_supported_tp(link);
148 if (dp_tr_pattern != DP_TRAINING_PATTERN_SEQUENCE_4) {
149 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
150 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
153 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
154 &downspread.raw, sizeof(downspread));
156 core_link_write_dpcd(link, DP_LANE_COUNT_SET,
157 &lane_count_set.raw, 1);
159 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
160 lt_settings->link_settings.use_link_rate_set == true) {
162 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
163 core_link_write_dpcd(link, DP_LINK_RATE_SET,
164 <_settings->link_settings.link_rate_set, 1);
166 rate = (uint8_t) (lt_settings->link_settings.link_rate);
167 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
171 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
174 lt_settings->link_settings.link_rate,
176 lt_settings->link_settings.lane_count,
177 lt_settings->enhanced_framing,
179 lt_settings->link_settings.link_spread);
181 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
184 lt_settings->link_settings.link_rate_set,
186 lt_settings->link_settings.lane_count,
187 lt_settings->enhanced_framing,
189 lt_settings->link_settings.link_spread);
193 static enum dpcd_training_patterns
194 dc_dp_training_pattern_to_dpcd_training_pattern(
195 struct dc_link *link,
196 enum dc_dp_training_pattern pattern)
198 enum dpcd_training_patterns dpcd_tr_pattern =
199 DPCD_TRAINING_PATTERN_VIDEOIDLE;
202 case DP_TRAINING_PATTERN_SEQUENCE_1:
203 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
205 case DP_TRAINING_PATTERN_SEQUENCE_2:
206 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
208 case DP_TRAINING_PATTERN_SEQUENCE_3:
209 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
211 case DP_TRAINING_PATTERN_SEQUENCE_4:
212 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
216 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
221 return dpcd_tr_pattern;
224 static uint8_t dc_dp_initialize_scrambling_data_symbols(
225 struct dc_link *link,
226 enum dc_dp_training_pattern pattern)
228 uint8_t disable_scrabled_data_symbols = 0;
231 case DP_TRAINING_PATTERN_SEQUENCE_1:
232 case DP_TRAINING_PATTERN_SEQUENCE_2:
233 case DP_TRAINING_PATTERN_SEQUENCE_3:
234 disable_scrabled_data_symbols = 1;
236 case DP_TRAINING_PATTERN_SEQUENCE_4:
237 disable_scrabled_data_symbols = 0;
241 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
245 return disable_scrabled_data_symbols;
248 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
250 return (link->lttpr_non_transparent_mode && offset != 0);
253 static void dpcd_set_lt_pattern_and_lane_settings(
254 struct dc_link *link,
255 const struct link_training_settings *lt_settings,
256 enum dc_dp_training_pattern pattern,
259 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
261 uint32_t dpcd_base_lt_offset;
263 uint8_t dpcd_lt_buffer[5] = {0};
264 union dpcd_training_pattern dpcd_pattern = { {0} };
266 uint32_t size_in_bytes;
267 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
268 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
270 if (is_repeater(link, offset))
271 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
272 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
274 /*****************************************************************
275 * DpcdAddress_TrainingPatternSet
276 *****************************************************************/
277 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
278 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
280 dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
281 dc_dp_initialize_scrambling_data_symbols(link, pattern);
283 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
286 if (is_repeater(link, offset)) {
287 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
291 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
293 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
296 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
298 /*****************************************************************
299 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
300 *****************************************************************/
301 for (lane = 0; lane <
302 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
304 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
305 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
306 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
307 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
309 dpcd_lane[lane].bits.MAX_SWING_REACHED =
310 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
311 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
312 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
313 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
314 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
317 /* concatenate everything into one buffer*/
319 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
323 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
327 if (is_repeater(link, offset)) {
328 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
329 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
333 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
334 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
335 dpcd_lane[0].bits.MAX_SWING_REACHED,
336 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
338 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
341 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
342 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
343 dpcd_lane[0].bits.MAX_SWING_REACHED,
344 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
346 if (edp_workaround) {
347 /* for eDP write in 2 parts because the 5-byte burst is
348 * causing issues on some eDP panels (EPR#366724)
350 core_link_write_dpcd(
352 DP_TRAINING_PATTERN_SET,
354 sizeof(dpcd_pattern.raw));
356 core_link_write_dpcd(
358 DP_TRAINING_LANE0_SET,
359 (uint8_t *)(dpcd_lane),
363 /* write it all in (1 + number-of-lanes)-byte burst*/
364 core_link_write_dpcd(
368 size_in_bytes + sizeof(dpcd_pattern.raw));
370 link->cur_lane_setting = lt_settings->lane_settings[0];
373 static bool is_cr_done(enum dc_lane_count ln_count,
374 union lane_status *dpcd_lane_status)
378 /*LANEx_CR_DONE bits All 1's?*/
379 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
380 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
387 static bool is_ch_eq_done(enum dc_lane_count ln_count,
388 union lane_status *dpcd_lane_status,
389 union lane_align_status_updated *lane_status_updated)
393 if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
396 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
397 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
398 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
406 static void update_drive_settings(
407 struct link_training_settings *dest,
408 struct link_training_settings src)
411 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
412 if (dest->voltage_swing == NULL)
413 dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
415 dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
417 if (dest->pre_emphasis == NULL)
418 dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
420 dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
422 if (dest->post_cursor2 == NULL)
423 dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
425 dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
429 static uint8_t get_nibble_at_index(const uint8_t *buf,
433 nibble = buf[index / 2];
443 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
444 enum dc_voltage_swing voltage)
446 enum dc_pre_emphasis pre_emphasis;
447 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
449 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
450 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
456 static void find_max_drive_settings(
457 const struct link_training_settings *link_training_setting,
458 struct link_training_settings *max_lt_setting)
461 struct dc_lane_settings max_requested;
463 max_requested.VOLTAGE_SWING =
464 link_training_setting->
465 lane_settings[0].VOLTAGE_SWING;
466 max_requested.PRE_EMPHASIS =
467 link_training_setting->
468 lane_settings[0].PRE_EMPHASIS;
469 /*max_requested.postCursor2 =
470 * link_training_setting->laneSettings[0].postCursor2;*/
472 /* Determine what the maximum of the requested settings are*/
473 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
475 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
476 max_requested.VOLTAGE_SWING)
478 max_requested.VOLTAGE_SWING =
479 link_training_setting->
480 lane_settings[lane].VOLTAGE_SWING;
482 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
483 max_requested.PRE_EMPHASIS)
484 max_requested.PRE_EMPHASIS =
485 link_training_setting->
486 lane_settings[lane].PRE_EMPHASIS;
489 if (link_training_setting->laneSettings[lane].postCursor2 >
490 max_requested.postCursor2)
492 max_requested.postCursor2 =
493 link_training_setting->laneSettings[lane].postCursor2;
498 /* make sure the requested settings are
499 * not higher than maximum settings*/
500 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
501 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
503 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
504 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
506 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
507 max_requested.postCursor2 = PostCursor2_MaxLevel;
510 /* make sure the pre-emphasis matches the voltage swing*/
511 if (max_requested.PRE_EMPHASIS >
512 get_max_pre_emphasis_for_voltage_swing(
513 max_requested.VOLTAGE_SWING))
514 max_requested.PRE_EMPHASIS =
515 get_max_pre_emphasis_for_voltage_swing(
516 max_requested.VOLTAGE_SWING);
519 * Post Cursor2 levels are completely independent from
520 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
521 * can only be applied to each allowable combination of voltage
522 * swing and pre-emphasis levels */
523 /* if ( max_requested.postCursor2 >
524 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
525 * max_requested.postCursor2 =
526 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
529 max_lt_setting->link_settings.link_rate =
530 link_training_setting->link_settings.link_rate;
531 max_lt_setting->link_settings.lane_count =
532 link_training_setting->link_settings.lane_count;
533 max_lt_setting->link_settings.link_spread =
534 link_training_setting->link_settings.link_spread;
536 for (lane = 0; lane <
537 link_training_setting->link_settings.lane_count;
539 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
540 max_requested.VOLTAGE_SWING;
541 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
542 max_requested.PRE_EMPHASIS;
543 /*max_lt_setting->laneSettings[lane].postCursor2 =
544 * max_requested.postCursor2;
550 static void get_lane_status_and_drive_settings(
551 struct dc_link *link,
552 const struct link_training_settings *link_training_setting,
553 union lane_status *ln_status,
554 union lane_align_status_updated *ln_status_updated,
555 struct link_training_settings *req_settings,
558 unsigned int lane01_status_address = DP_LANE0_1_STATUS;
559 uint8_t lane_adjust_offset = 4;
560 unsigned int lane01_adjust_address;
561 uint8_t dpcd_buf[6] = {0};
562 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
563 struct link_training_settings request_settings = { {0} };
566 memset(req_settings, '\0', sizeof(struct link_training_settings));
568 if (is_repeater(link, offset)) {
569 lane01_status_address =
570 DP_LANE0_1_STATUS_PHY_REPEATER1 +
571 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
572 lane_adjust_offset = 3;
577 lane01_status_address,
578 (uint8_t *)(dpcd_buf),
581 for (lane = 0; lane <
582 (uint32_t)(link_training_setting->link_settings.lane_count);
585 ln_status[lane].raw =
586 get_nibble_at_index(&dpcd_buf[0], lane);
587 dpcd_lane_adjust[lane].raw =
588 get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
591 ln_status_updated->raw = dpcd_buf[2];
593 if (is_repeater(link, offset)) {
594 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
595 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
598 lane01_status_address, dpcd_buf[0],
599 lane01_status_address + 1, dpcd_buf[1]);
601 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
603 lane01_status_address, dpcd_buf[0],
604 lane01_status_address + 1, dpcd_buf[1]);
606 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
608 if (is_repeater(link, offset))
609 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
610 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
612 if (is_repeater(link, offset)) {
613 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
614 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
617 lane01_adjust_address,
618 dpcd_buf[lane_adjust_offset],
619 lane01_adjust_address + 1,
620 dpcd_buf[lane_adjust_offset + 1]);
622 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
624 lane01_adjust_address,
625 dpcd_buf[lane_adjust_offset],
626 lane01_adjust_address + 1,
627 dpcd_buf[lane_adjust_offset + 1]);
630 /*copy to req_settings*/
631 request_settings.link_settings.lane_count =
632 link_training_setting->link_settings.lane_count;
633 request_settings.link_settings.link_rate =
634 link_training_setting->link_settings.link_rate;
635 request_settings.link_settings.link_spread =
636 link_training_setting->link_settings.link_spread;
638 for (lane = 0; lane <
639 (uint32_t)(link_training_setting->link_settings.lane_count);
642 request_settings.lane_settings[lane].VOLTAGE_SWING =
643 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
645 request_settings.lane_settings[lane].PRE_EMPHASIS =
646 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
650 /*Note: for postcursor2, read adjusted
651 * postcursor2 settings from*/
652 /*DpcdAddress_AdjustRequestPostCursor2 =
653 *0x020C (not implemented yet)*/
655 /* we find the maximum of the requested settings across all lanes*/
656 /* and set this maximum for all lanes*/
657 find_max_drive_settings(&request_settings, req_settings);
659 /* if post cursor 2 is needed in the future,
660 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
665 static void dpcd_set_lane_settings(
666 struct dc_link *link,
667 const struct link_training_settings *link_training_setting,
670 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
672 unsigned int lane0_set_address;
674 lane0_set_address = DP_TRAINING_LANE0_SET;
676 if (is_repeater(link, offset))
677 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
678 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
680 for (lane = 0; lane <
681 (uint32_t)(link_training_setting->
682 link_settings.lane_count);
684 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
685 (uint8_t)(link_training_setting->
686 lane_settings[lane].VOLTAGE_SWING);
687 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
688 (uint8_t)(link_training_setting->
689 lane_settings[lane].PRE_EMPHASIS);
690 dpcd_lane[lane].bits.MAX_SWING_REACHED =
691 (link_training_setting->
692 lane_settings[lane].VOLTAGE_SWING ==
693 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
694 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
695 (link_training_setting->
696 lane_settings[lane].PRE_EMPHASIS ==
697 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
700 core_link_write_dpcd(link,
702 (uint8_t *)(dpcd_lane),
703 link_training_setting->link_settings.lane_count);
706 if (LTSettings.link.rate == LinkRate_High2)
708 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
709 for ( uint32_t lane = 0;
710 lane < lane_count_DPMax; lane++)
712 dpcd_lane2[lane].bits.post_cursor2_set =
713 static_cast<unsigned char>(
714 LTSettings.laneSettings[lane].postCursor2);
715 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
717 m_pDpcdAccessSrv->WriteDpcdData(
718 DpcdAddress_Lane0Set2,
719 reinterpret_cast<unsigned char*>(dpcd_lane2),
720 LTSettings.link.lanes);
724 if (is_repeater(link, offset)) {
725 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
726 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
730 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
731 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
732 dpcd_lane[0].bits.MAX_SWING_REACHED,
733 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
736 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
739 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
740 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
741 dpcd_lane[0].bits.MAX_SWING_REACHED,
742 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
744 link->cur_lane_setting = link_training_setting->lane_settings[0];
748 static bool is_max_vs_reached(
749 const struct link_training_settings *lt_settings)
752 for (lane = 0; lane <
753 (uint32_t)(lt_settings->link_settings.lane_count);
755 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
756 == VOLTAGE_SWING_MAX_LEVEL)
763 static bool perform_post_lt_adj_req_sequence(
764 struct dc_link *link,
765 struct link_training_settings *lt_settings)
767 enum dc_lane_count lane_count =
768 lt_settings->link_settings.lane_count;
770 uint32_t adj_req_count;
771 uint32_t adj_req_timer;
772 bool req_drv_setting_changed;
775 req_drv_setting_changed = false;
776 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
779 req_drv_setting_changed = false;
781 for (adj_req_timer = 0;
782 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
785 struct link_training_settings req_settings;
786 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
787 union lane_align_status_updated
788 dpcd_lane_status_updated;
790 get_lane_status_and_drive_settings(
794 &dpcd_lane_status_updated,
798 if (dpcd_lane_status_updated.bits.
799 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
802 if (!is_cr_done(lane_count, dpcd_lane_status))
808 &dpcd_lane_status_updated))
811 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
814 lane_settings[lane].VOLTAGE_SWING !=
815 req_settings.lane_settings[lane].
817 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
818 req_settings.lane_settings[lane].PRE_EMPHASIS) {
820 req_drv_setting_changed = true;
825 if (req_drv_setting_changed) {
826 update_drive_settings(
827 lt_settings, req_settings);
829 dc_link_dp_set_drive_settings(link,
837 if (!req_drv_setting_changed) {
838 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
845 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
853 /* Only used for channel equalization */
854 static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
856 unsigned int aux_rd_interval_us = 400;
858 switch (dpcd_aux_read_interval) {
860 aux_rd_interval_us = 400;
863 aux_rd_interval_us = 4000;
866 aux_rd_interval_us = 8000;
869 aux_rd_interval_us = 16000;
875 return aux_rd_interval_us;
878 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
879 union lane_status *dpcd_lane_status)
881 enum link_training_result result = LINK_TRAINING_SUCCESS;
883 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
884 result = LINK_TRAINING_CR_FAIL_LANE0;
885 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
886 result = LINK_TRAINING_CR_FAIL_LANE1;
887 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
888 result = LINK_TRAINING_CR_FAIL_LANE23;
889 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
890 result = LINK_TRAINING_CR_FAIL_LANE23;
894 static enum link_training_result perform_channel_equalization_sequence(
895 struct dc_link *link,
896 struct link_training_settings *lt_settings,
899 struct link_training_settings req_settings;
900 enum dc_dp_training_pattern tr_pattern;
901 uint32_t retries_ch_eq;
902 uint32_t wait_time_microsec;
903 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
904 union lane_align_status_updated dpcd_lane_status_updated = { {0} };
905 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
907 /* Note: also check that TPS4 is a supported feature*/
909 tr_pattern = lt_settings->pattern_for_eq;
911 if (is_repeater(link, offset))
912 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
914 dp_set_hw_training_pattern(link, tr_pattern, offset);
916 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
919 dp_set_hw_lane_settings(link, lt_settings, offset);
923 /* EPR #361076 - write as a 5-byte burst,
924 * but only for the 1-st iteration
927 dpcd_set_lt_pattern_and_lane_settings(
932 dpcd_set_lane_settings(link, lt_settings, offset);
934 /* 3. wait for receiver to lock-on*/
935 wait_time_microsec = lt_settings->eq_pattern_time;
937 if (is_repeater(link, offset))
939 translate_training_aux_read_interval(
940 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
942 wait_for_training_aux_rd_interval(
946 /* 4. Read lane status and requested
947 * drive settings as set by the sink*/
949 get_lane_status_and_drive_settings(
953 &dpcd_lane_status_updated,
957 /* 5. check CR done*/
958 if (!is_cr_done(lane_count, dpcd_lane_status))
959 return LINK_TRAINING_EQ_FAIL_CR;
961 /* 6. check CHEQ done*/
962 if (is_ch_eq_done(lane_count,
964 &dpcd_lane_status_updated))
965 return LINK_TRAINING_SUCCESS;
967 /* 7. update VS/PE/PC2 in lt_settings*/
968 update_drive_settings(lt_settings, req_settings);
971 return LINK_TRAINING_EQ_FAIL_EQ;
974 #define TRAINING_AUX_RD_INTERVAL 100 //us
976 static void start_clock_recovery_pattern_early(struct dc_link *link,
977 struct link_training_settings *lt_settings,
980 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
982 dp_set_hw_training_pattern(link, DP_TRAINING_PATTERN_SEQUENCE_1, offset);
983 dp_set_hw_lane_settings(link, lt_settings, offset);
987 static enum link_training_result perform_clock_recovery_sequence(
988 struct dc_link *link,
989 struct link_training_settings *lt_settings,
993 uint32_t retry_count;
994 uint32_t wait_time_microsec;
995 struct link_training_settings req_settings;
996 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
997 enum dc_dp_training_pattern tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_1;
998 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
999 union lane_align_status_updated dpcd_lane_status_updated;
1004 if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1005 dp_set_hw_training_pattern(link, tr_pattern, offset);
1007 /* najeeb - The synaptics MST hub can put the LT in
1008 * infinite loop by switching the VS
1010 /* between level 0 and level 1 continuously, here
1011 * we try for CR lock for LinkTrainingMaxCRRetry count*/
1012 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1013 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1015 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1016 memset(&dpcd_lane_status_updated, '\0',
1017 sizeof(dpcd_lane_status_updated));
1019 /* 1. call HWSS to set lane settings*/
1020 dp_set_hw_lane_settings(
1025 /* 2. update DPCD of the receiver*/
1027 /* EPR #361076 - write as a 5-byte burst,
1028 * but only for the 1-st iteration.*/
1029 dpcd_set_lt_pattern_and_lane_settings(
1035 dpcd_set_lane_settings(
1040 /* 3. wait receiver to lock-on*/
1041 wait_time_microsec = lt_settings->cr_pattern_time;
1043 if (link->lttpr_non_transparent_mode)
1044 wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1046 wait_for_training_aux_rd_interval(
1048 wait_time_microsec);
1050 /* 4. Read lane status and requested drive
1051 * settings as set by the sink
1053 get_lane_status_and_drive_settings(
1057 &dpcd_lane_status_updated,
1061 /* 5. check CR done*/
1062 if (is_cr_done(lane_count, dpcd_lane_status))
1063 return LINK_TRAINING_SUCCESS;
1065 /* 6. max VS reached*/
1066 if (is_max_vs_reached(lt_settings))
1069 /* 7. same voltage*/
1070 /* Note: VS same for all lanes,
1071 * so comparing first lane is sufficient*/
1072 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
1073 req_settings.lane_settings[0].VOLTAGE_SWING)
1078 /* 8. update VS/PE/PC2 in lt_settings*/
1079 update_drive_settings(lt_settings, req_settings);
1084 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1086 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1088 LINK_TRAINING_MAX_CR_RETRY);
1092 return get_cr_failure(lane_count, dpcd_lane_status);
1095 static inline enum link_training_result perform_link_training_int(
1096 struct dc_link *link,
1097 struct link_training_settings *lt_settings,
1098 enum link_training_result status)
1100 union lane_count_set lane_count_set = { {0} };
1101 union dpcd_training_pattern dpcd_pattern = { {0} };
1103 /* 3. set training not in progress*/
1104 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1105 dpcd_set_training_pattern(link, dpcd_pattern);
1107 /* 4. mainlink output idle pattern*/
1108 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1111 * 5. post training adjust if required
1112 * If the upstream DPTX and downstream DPRX both support TPS4,
1113 * TPS4 must be used instead of POST_LT_ADJ_REQ.
1115 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1116 get_supported_tp(link) == DP_TRAINING_PATTERN_SEQUENCE_4)
1119 if (status == LINK_TRAINING_SUCCESS &&
1120 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1121 status = LINK_TRAINING_LQA_FAIL;
1123 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1124 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1125 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1127 core_link_write_dpcd(
1130 &lane_count_set.raw,
1131 sizeof(lane_count_set));
1136 static enum link_training_result check_link_loss_status(
1137 struct dc_link *link,
1138 const struct link_training_settings *link_training_setting)
1140 enum link_training_result status = LINK_TRAINING_SUCCESS;
1141 union lane_status lane_status;
1142 uint8_t dpcd_buf[6] = {0};
1145 core_link_read_dpcd(
1148 (uint8_t *)(dpcd_buf),
1151 /*parse lane status*/
1152 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1154 * check lanes status
1156 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1158 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1159 !lane_status.bits.CR_DONE_0 ||
1160 !lane_status.bits.SYMBOL_LOCKED_0) {
1161 /* if one of the channel equalization, clock
1162 * recovery or symbol lock is dropped
1163 * consider it as (link has been
1164 * dropped) dp sink status has changed
1166 status = LINK_TRAINING_LINK_LOSS;
1174 static void initialize_training_settings(
1175 struct dc_link *link,
1176 const struct dc_link_settings *link_setting,
1177 const struct dc_link_training_overrides *overrides,
1178 struct link_training_settings *lt_settings)
1182 memset(lt_settings, '\0', sizeof(struct link_training_settings));
1184 /* Initialize link settings */
1185 lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1186 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1188 if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1189 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1191 lt_settings->link_settings.link_rate = link_setting->link_rate;
1193 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1194 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1196 lt_settings->link_settings.lane_count = link_setting->lane_count;
1198 /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1200 /* TODO hard coded to SS for now
1201 * lt_settings.link_settings.link_spread =
1202 * dal_display_path_is_ss_supported(
1203 * path_mode->display_path) ?
1204 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1205 * LINK_SPREAD_DISABLED;
1207 /* Initialize link spread */
1208 if (link->dp_ss_off)
1209 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1210 else if (overrides->downspread != NULL)
1211 lt_settings->link_settings.link_spread
1212 = *overrides->downspread
1213 ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1214 : LINK_SPREAD_DISABLED;
1216 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1218 /* Initialize lane settings overrides */
1219 if (overrides->voltage_swing != NULL)
1220 lt_settings->voltage_swing = overrides->voltage_swing;
1222 if (overrides->pre_emphasis != NULL)
1223 lt_settings->pre_emphasis = overrides->pre_emphasis;
1225 if (overrides->post_cursor2 != NULL)
1226 lt_settings->post_cursor2 = overrides->post_cursor2;
1228 /* Initialize lane settings (VS/PE/PC2) */
1229 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1230 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1231 lt_settings->voltage_swing != NULL ?
1232 *lt_settings->voltage_swing :
1233 VOLTAGE_SWING_LEVEL0;
1234 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1235 lt_settings->pre_emphasis != NULL ?
1236 *lt_settings->pre_emphasis
1237 : PRE_EMPHASIS_DISABLED;
1238 lt_settings->lane_settings[lane].POST_CURSOR2 =
1239 lt_settings->post_cursor2 != NULL ?
1240 *lt_settings->post_cursor2
1241 : POST_CURSOR2_DISABLED;
1244 /* Initialize training timings */
1245 if (overrides->cr_pattern_time != NULL)
1246 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1248 lt_settings->cr_pattern_time = get_training_aux_rd_interval(link, 100);
1250 if (overrides->eq_pattern_time != NULL)
1251 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1253 lt_settings->eq_pattern_time = get_training_aux_rd_interval(link, 400);
1255 if (overrides->pattern_for_eq != NULL)
1256 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1258 lt_settings->pattern_for_eq = get_supported_tp(link);
1260 if (overrides->enhanced_framing != NULL)
1261 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1263 lt_settings->enhanced_framing = 1;
1266 static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
1268 switch (lttpr_repeater_count) {
1269 case 0x80: // 1 lttpr repeater
1271 case 0x40: // 2 lttpr repeaters
1273 case 0x20: // 3 lttpr repeaters
1275 case 0x10: // 4 lttpr repeaters
1277 case 0x08: // 5 lttpr repeaters
1279 case 0x04: // 6 lttpr repeaters
1281 case 0x02: // 7 lttpr repeaters
1283 case 0x01: // 8 lttpr repeaters
1288 return 0; // invalid value
1291 static void configure_lttpr_mode(struct dc_link *link)
1293 /* aux timeout is already set to extended */
1294 /* RESET/SET lttpr mode to enable non transparent mode */
1295 uint8_t repeater_cnt;
1296 uint32_t aux_interval_address;
1297 uint8_t repeater_id;
1298 enum dc_status result = DC_ERROR_UNEXPECTED;
1299 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1301 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1302 result = core_link_write_dpcd(link,
1303 DP_PHY_REPEATER_MODE,
1304 (uint8_t *)&repeater_mode,
1305 sizeof(repeater_mode));
1307 if (result == DC_OK) {
1308 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1311 if (link->lttpr_non_transparent_mode) {
1313 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1315 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1316 result = core_link_write_dpcd(link,
1317 DP_PHY_REPEATER_MODE,
1318 (uint8_t *)&repeater_mode,
1319 sizeof(repeater_mode));
1321 if (result == DC_OK) {
1322 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1325 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1326 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1327 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1328 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1329 core_link_read_dpcd(
1331 aux_interval_address,
1332 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1333 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1334 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1339 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1341 union dpcd_training_pattern dpcd_pattern = { {0} };
1343 const uint32_t dpcd_base_lt_offset =
1344 DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1345 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1346 /* Set training not in progress*/
1347 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1349 core_link_write_dpcd(
1351 dpcd_base_lt_offset,
1355 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1358 dpcd_base_lt_offset,
1359 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1362 static void print_status_message(
1363 struct dc_link *link,
1364 const struct link_training_settings *lt_settings,
1365 enum link_training_result status)
1367 char *link_rate = "Unknown";
1368 char *lt_result = "Unknown";
1369 char *lt_spread = "Disabled";
1371 switch (lt_settings->link_settings.link_rate) {
1375 case LINK_RATE_HIGH:
1378 case LINK_RATE_HIGH2:
1381 case LINK_RATE_RBR2:
1384 case LINK_RATE_HIGH3:
1392 case LINK_TRAINING_SUCCESS:
1395 case LINK_TRAINING_CR_FAIL_LANE0:
1396 lt_result = "CR failed lane0";
1398 case LINK_TRAINING_CR_FAIL_LANE1:
1399 lt_result = "CR failed lane1";
1401 case LINK_TRAINING_CR_FAIL_LANE23:
1402 lt_result = "CR failed lane23";
1404 case LINK_TRAINING_EQ_FAIL_CR:
1405 lt_result = "CR failed in EQ";
1407 case LINK_TRAINING_EQ_FAIL_EQ:
1408 lt_result = "EQ failed";
1410 case LINK_TRAINING_LQA_FAIL:
1411 lt_result = "LQA failed";
1413 case LINK_TRAINING_LINK_LOSS:
1414 lt_result = "Link loss";
1420 switch (lt_settings->link_settings.link_spread) {
1421 case LINK_SPREAD_DISABLED:
1422 lt_spread = "Disabled";
1424 case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1425 lt_spread = "0.5% 30KHz";
1427 case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1428 lt_spread = "0.5% 33KHz";
1434 /* Connectivity log: link training */
1435 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1437 lt_settings->link_settings.lane_count,
1439 lt_settings->lane_settings[0].VOLTAGE_SWING,
1440 lt_settings->lane_settings[0].PRE_EMPHASIS,
1444 void dc_link_dp_set_drive_settings(
1445 struct dc_link *link,
1446 struct link_training_settings *lt_settings)
1448 /* program ASIC PHY settings*/
1449 dp_set_hw_lane_settings(link, lt_settings, DPRX);
1451 /* Notify DP sink the PHY settings from source */
1452 dpcd_set_lane_settings(link, lt_settings, DPRX);
1455 bool dc_link_dp_perform_link_training_skip_aux(
1456 struct dc_link *link,
1457 const struct dc_link_settings *link_setting)
1459 struct link_training_settings lt_settings;
1460 enum dc_dp_training_pattern pattern_for_cr = DP_TRAINING_PATTERN_SEQUENCE_1;
1462 initialize_training_settings(
1465 &link->preferred_training_settings,
1468 /* 1. Perform_clock_recovery_sequence. */
1470 /* transmit training pattern for clock recovery */
1471 dp_set_hw_training_pattern(link, pattern_for_cr, DPRX);
1473 /* call HWSS to set lane settings*/
1474 dp_set_hw_lane_settings(link, <_settings, DPRX);
1476 /* wait receiver to lock-on*/
1477 wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1479 /* 2. Perform_channel_equalization_sequence. */
1481 /* transmit training pattern for channel equalization. */
1482 dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1484 /* call HWSS to set lane settings*/
1485 dp_set_hw_lane_settings(link, <_settings, DPRX);
1487 /* wait receiver to lock-on. */
1488 wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1490 /* 3. Perform_link_training_int. */
1492 /* Mainlink output idle pattern. */
1493 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1495 print_status_message(link, <_settings, LINK_TRAINING_SUCCESS);
1500 enum link_training_result dc_link_dp_perform_link_training(
1501 struct dc_link *link,
1502 const struct dc_link_settings *link_setting,
1503 bool skip_video_pattern)
1505 enum link_training_result status = LINK_TRAINING_SUCCESS;
1506 struct link_training_settings lt_settings;
1509 uint8_t repeater_cnt;
1510 uint8_t repeater_id;
1512 initialize_training_settings(
1515 &link->preferred_training_settings,
1518 /* Configure lttpr mode */
1519 if (link->lttpr_non_transparent_mode)
1520 configure_lttpr_mode(link);
1522 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1523 start_clock_recovery_pattern_early(link, <_settings, DPRX);
1525 /* 1. set link rate, lane count and spread. */
1526 dpcd_set_link_settings(link, <_settings);
1528 if (link->preferred_training_settings.fec_enable != NULL)
1529 fec_enable = *link->preferred_training_settings.fec_enable;
1533 dp_set_fec_ready(link, fec_enable);
1535 if (link->lttpr_non_transparent_mode) {
1537 /* 2. perform link training (set link training done
1538 * to false is done as well)
1540 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1542 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1544 status = perform_clock_recovery_sequence(link, <_settings, repeater_id);
1546 if (status != LINK_TRAINING_SUCCESS)
1549 status = perform_channel_equalization_sequence(link,
1553 if (status != LINK_TRAINING_SUCCESS)
1556 repeater_training_done(link, repeater_id);
1560 if (status == LINK_TRAINING_SUCCESS) {
1561 status = perform_clock_recovery_sequence(link, <_settings, DPRX);
1562 if (status == LINK_TRAINING_SUCCESS) {
1563 status = perform_channel_equalization_sequence(link,
1569 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
1570 status = perform_link_training_int(link,
1575 /* delay 5ms after Main Link output idle pattern and then check
1578 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1580 status = check_link_loss_status(link, <_settings);
1583 /* 6. print status message*/
1584 print_status_message(link, <_settings, status);
1586 if (status != LINK_TRAINING_SUCCESS)
1587 link->ctx->dc->debug_data.ltFailCount++;
1592 bool perform_link_training_with_retries(
1593 const struct dc_link_settings *link_setting,
1594 bool skip_video_pattern,
1596 struct pipe_ctx *pipe_ctx,
1597 enum signal_type signal)
1600 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1601 struct dc_stream_state *stream = pipe_ctx->stream;
1602 struct dc_link *link = stream->link;
1603 enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1605 /* We need to do this before the link training to ensure the idle pattern in SST
1606 * mode will be sent right after the link training
1608 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
1609 pipe_ctx->stream_res.stream_enc->id, true);
1611 for (j = 0; j < attempts; ++j) {
1616 pipe_ctx->clock_source->id,
1619 if (stream->sink_patches.dppowerup_delay > 0) {
1620 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1622 msleep(delay_dp_power_up_in_ms);
1625 dp_set_panel_mode(link, panel_mode);
1627 if (link->aux_access_disabled) {
1628 dc_link_dp_perform_link_training_skip_aux(link, link_setting);
1630 } else if (dc_link_dp_perform_link_training(
1633 skip_video_pattern) == LINK_TRAINING_SUCCESS)
1636 /* latest link training still fail, skip delay and keep PHY on
1638 if (j == (attempts - 1))
1641 dp_disable_link_phy(link, signal);
1643 msleep(delay_between_attempts);
1645 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1651 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1653 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1654 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1656 if (dp_cs != NULL) {
1657 dp_cs_id = dp_cs->id;
1660 * dp clock source is not initialized for some reason.
1661 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1669 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1671 if (mst_enable == false &&
1672 link->type == dc_connection_mst_branch) {
1673 /* Disable MST on link. Use only local sink. */
1674 dp_disable_link_phy_mst(link, link->connector_signal);
1676 link->type = dc_connection_single;
1677 link->local_sink = link->remote_sinks[0];
1678 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1679 } else if (mst_enable == true &&
1680 link->type == dc_connection_single &&
1681 link->remote_sinks[0] != NULL) {
1682 /* Re-enable MST on link. */
1683 dp_disable_link_phy(link, link->connector_signal);
1684 dp_enable_mst_on_sink(link, true);
1686 link->type = dc_connection_mst_branch;
1687 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1691 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1693 /* Begin Sync LT. During this time,
1694 * DPCD:600h must not be powered down.
1696 link->sync_lt_in_progress = true;
1698 /*Clear any existing preferred settings.*/
1699 memset(&link->preferred_training_settings, 0,
1700 sizeof(struct dc_link_training_overrides));
1701 memset(&link->preferred_link_setting, 0,
1702 sizeof(struct dc_link_settings));
1707 enum link_training_result dc_link_dp_sync_lt_attempt(
1708 struct dc_link *link,
1709 struct dc_link_settings *link_settings,
1710 struct dc_link_training_overrides *lt_overrides)
1712 struct link_training_settings lt_settings;
1713 enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1714 enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1715 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1716 bool fec_enable = false;
1718 initialize_training_settings(
1724 /* Setup MST Mode */
1725 if (lt_overrides->mst_enable)
1726 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1729 dp_disable_link_phy(link, link->connector_signal);
1732 dp_cs_id = get_clock_source_id(link);
1733 dp_enable_link_phy(link, link->connector_signal,
1734 dp_cs_id, link_settings);
1736 /* Set FEC enable */
1737 fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1738 dp_set_fec_ready(link, fec_enable);
1740 if (lt_overrides->alternate_scrambler_reset) {
1741 if (*lt_overrides->alternate_scrambler_reset)
1742 panel_mode = DP_PANEL_MODE_EDP;
1744 panel_mode = DP_PANEL_MODE_DEFAULT;
1746 panel_mode = dp_get_panel_mode(link);
1748 dp_set_panel_mode(link, panel_mode);
1750 /* Attempt to train with given link training settings */
1751 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1752 start_clock_recovery_pattern_early(link, <_settings, DPRX);
1754 /* Set link rate, lane count and spread. */
1755 dpcd_set_link_settings(link, <_settings);
1757 /* 2. perform link training (set link training done
1758 * to false is done as well)
1760 lt_status = perform_clock_recovery_sequence(link, <_settings, DPRX);
1761 if (lt_status == LINK_TRAINING_SUCCESS) {
1762 lt_status = perform_channel_equalization_sequence(link,
1767 /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1768 /* 4. print status message*/
1769 print_status_message(link, <_settings, lt_status);
1774 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1776 /* If input parameter is set, shut down phy.
1777 * Still shouldn't turn off dp_receiver (DPCD:600h)
1779 if (link_down == true) {
1780 dp_disable_link_phy(link, link->connector_signal);
1781 dp_set_fec_ready(link, false);
1784 link->sync_lt_in_progress = false;
1788 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1790 struct dc_link_settings max_link_cap = {0};
1792 /* get max link encoder capability */
1793 link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
1795 /* Lower link settings based on sink's link cap */
1796 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1797 max_link_cap.lane_count =
1798 link->reported_link_cap.lane_count;
1799 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
1800 max_link_cap.link_rate =
1801 link->reported_link_cap.link_rate;
1802 if (link->reported_link_cap.link_spread <
1803 max_link_cap.link_spread)
1804 max_link_cap.link_spread =
1805 link->reported_link_cap.link_spread;
1807 * account for lttpr repeaters cap
1808 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
1810 if (link->lttpr_non_transparent_mode) {
1811 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
1812 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
1814 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
1815 max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
1817 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
1819 max_link_cap.lane_count,
1820 max_link_cap.link_rate);
1822 return max_link_cap;
1825 static enum dc_status read_hpd_rx_irq_data(
1826 struct dc_link *link,
1827 union hpd_irq_data *irq_data)
1829 static enum dc_status retval;
1831 /* The HW reads 16 bytes from 200h on HPD,
1832 * but if we get an AUX_DEFER, the HW cannot retry
1833 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1834 * fail, so we now explicitly read 6 bytes which is
1835 * the req from the above mentioned test cases.
1837 * For DP 1.4 we need to read those from 2002h range.
1839 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1840 retval = core_link_read_dpcd(
1844 sizeof(union hpd_irq_data));
1846 /* Read 14 bytes in a single read and then copy only the required fields.
1847 * This is more efficient than doing it in two separate AUX reads. */
1849 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1851 retval = core_link_read_dpcd(
1857 if (retval != DC_OK)
1860 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1861 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1862 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1863 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1864 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1865 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1871 static bool hpd_rx_irq_check_link_loss_status(
1872 struct dc_link *link,
1873 union hpd_irq_data *hpd_irq_dpcd_data)
1875 uint8_t irq_reg_rx_power_state = 0;
1876 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1877 union lane_status lane_status;
1879 bool sink_status_changed;
1882 sink_status_changed = false;
1883 return_code = false;
1885 if (link->cur_link_settings.lane_count == 0)
1888 /*1. Check that Link Status changed, before re-training.*/
1890 /*parse lane status*/
1891 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1892 /* check status of lanes 0,1
1893 * changed DpcdAddress_Lane01Status (0x202)
1895 lane_status.raw = get_nibble_at_index(
1896 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1899 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1900 !lane_status.bits.CR_DONE_0 ||
1901 !lane_status.bits.SYMBOL_LOCKED_0) {
1902 /* if one of the channel equalization, clock
1903 * recovery or symbol lock is dropped
1904 * consider it as (link has been
1905 * dropped) dp sink status has changed
1907 sink_status_changed = true;
1912 /* Check interlane align.*/
1913 if (sink_status_changed ||
1914 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
1916 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
1920 /*2. Check that we can handle interrupt: Not in FS DOS,
1921 * Not in "Display Timeout" state, Link is trained.
1923 dpcd_result = core_link_read_dpcd(link,
1925 &irq_reg_rx_power_state,
1926 sizeof(irq_reg_rx_power_state));
1928 if (dpcd_result != DC_OK) {
1929 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1932 if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1933 return_code = false;
1940 bool dp_verify_link_cap(
1941 struct dc_link *link,
1942 struct dc_link_settings *known_limit_link_setting,
1945 struct dc_link_settings max_link_cap = {0};
1946 struct dc_link_settings cur_link_setting = {0};
1947 struct dc_link_settings *cur = &cur_link_setting;
1948 struct dc_link_settings initial_link_settings = {0};
1950 bool skip_link_training;
1951 bool skip_video_pattern;
1952 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1953 enum link_training_result status;
1954 union hpd_irq_data irq_data;
1956 if (link->dc->debug.skip_detection_link_training) {
1957 link->verified_link_cap = *known_limit_link_setting;
1961 memset(&irq_data, 0, sizeof(irq_data));
1963 skip_link_training = false;
1965 max_link_cap = get_max_link_cap(link);
1967 /* Grant extended timeout request */
1968 if (link->lttpr_non_transparent_mode && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
1969 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
1971 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
1974 /* TODO implement override and monitor patch later */
1976 /* try to train the link from high to low to
1977 * find the physical link capability
1979 /* disable PHY done possible by BIOS, will be done by driver itself */
1980 dp_disable_link_phy(link, link->connector_signal);
1982 dp_cs_id = get_clock_source_id(link);
1984 /* link training starts with the maximum common settings
1985 * supported by both sink and ASIC.
1987 initial_link_settings = get_common_supported_link_settings(
1988 *known_limit_link_setting,
1990 cur_link_setting = initial_link_settings;
1992 /* Temporary Renoir-specific workaround for SWDEV-215184;
1993 * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
1994 * so add extra cycle of enabling and disabling the PHY before first link training.
1996 if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
1997 link->dc->debug.usbc_combo_phy_reset_wa) {
1998 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
1999 dp_disable_link_phy(link, link->connector_signal);
2003 skip_video_pattern = true;
2005 if (cur->link_rate == LINK_RATE_LOW)
2006 skip_video_pattern = false;
2010 link->connector_signal,
2015 if (skip_link_training)
2018 status = dc_link_dp_perform_link_training(
2021 skip_video_pattern);
2022 if (status == LINK_TRAINING_SUCCESS)
2029 link->verified_link_cap = *cur;
2031 if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2032 if (hpd_rx_irq_check_link_loss_status(
2037 /* always disable the link before trying another
2038 * setting or before returning we'll enable it later
2039 * based on the actual mode we're driving
2041 dp_disable_link_phy(link, link->connector_signal);
2042 } while (!success && decide_fallback_link_setting(
2043 initial_link_settings, cur, status));
2045 /* Link Training failed for all Link Settings
2046 * (Lane Count is still unknown)
2049 /* If all LT fails for all settings,
2050 * set verified = failed safe (1 lane low)
2052 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2053 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2055 link->verified_link_cap.link_spread =
2056 LINK_SPREAD_DISABLED;
2063 bool dp_verify_link_cap_with_retries(
2064 struct dc_link *link,
2065 struct dc_link_settings *known_limit_link_setting,
2069 bool success = false;
2071 for (i = 0; i < attempts; i++) {
2073 enum dc_connection_type type = dc_connection_none;
2075 memset(&link->verified_link_cap, 0,
2076 sizeof(struct dc_link_settings));
2077 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2078 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2079 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2080 link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2082 } else if (dp_verify_link_cap(link,
2083 &link->reported_link_cap,
2084 &fail_count) && fail_count == 0) {
2093 bool dp_verify_mst_link_cap(
2094 struct dc_link *link)
2096 struct dc_link_settings max_link_cap = {0};
2098 max_link_cap = get_max_link_cap(link);
2099 link->verified_link_cap = get_common_supported_link_settings(
2100 link->reported_link_cap,
2106 static struct dc_link_settings get_common_supported_link_settings(
2107 struct dc_link_settings link_setting_a,
2108 struct dc_link_settings link_setting_b)
2110 struct dc_link_settings link_settings = {0};
2112 link_settings.lane_count =
2113 (link_setting_a.lane_count <=
2114 link_setting_b.lane_count) ?
2115 link_setting_a.lane_count :
2116 link_setting_b.lane_count;
2117 link_settings.link_rate =
2118 (link_setting_a.link_rate <=
2119 link_setting_b.link_rate) ?
2120 link_setting_a.link_rate :
2121 link_setting_b.link_rate;
2122 link_settings.link_spread = LINK_SPREAD_DISABLED;
2124 /* in DP compliance test, DPR-120 may have
2125 * a random value in its MAX_LINK_BW dpcd field.
2126 * We map it to the maximum supported link rate that
2127 * is smaller than MAX_LINK_BW in this case.
2129 if (link_settings.link_rate > LINK_RATE_HIGH3) {
2130 link_settings.link_rate = LINK_RATE_HIGH3;
2131 } else if (link_settings.link_rate < LINK_RATE_HIGH3
2132 && link_settings.link_rate > LINK_RATE_HIGH2) {
2133 link_settings.link_rate = LINK_RATE_HIGH2;
2134 } else if (link_settings.link_rate < LINK_RATE_HIGH2
2135 && link_settings.link_rate > LINK_RATE_HIGH) {
2136 link_settings.link_rate = LINK_RATE_HIGH;
2137 } else if (link_settings.link_rate < LINK_RATE_HIGH
2138 && link_settings.link_rate > LINK_RATE_LOW) {
2139 link_settings.link_rate = LINK_RATE_LOW;
2140 } else if (link_settings.link_rate < LINK_RATE_LOW) {
2141 link_settings.link_rate = LINK_RATE_UNKNOWN;
2144 return link_settings;
2147 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2149 return lane_count <= LANE_COUNT_ONE;
2152 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2154 return link_rate <= LINK_RATE_LOW;
2157 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2159 switch (lane_count) {
2160 case LANE_COUNT_FOUR:
2161 return LANE_COUNT_TWO;
2162 case LANE_COUNT_TWO:
2163 return LANE_COUNT_ONE;
2164 case LANE_COUNT_ONE:
2165 return LANE_COUNT_UNKNOWN;
2167 return LANE_COUNT_UNKNOWN;
2171 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2173 switch (link_rate) {
2174 case LINK_RATE_HIGH3:
2175 return LINK_RATE_HIGH2;
2176 case LINK_RATE_HIGH2:
2177 return LINK_RATE_HIGH;
2178 case LINK_RATE_HIGH:
2179 return LINK_RATE_LOW;
2181 return LINK_RATE_UNKNOWN;
2183 return LINK_RATE_UNKNOWN;
2187 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2189 switch (lane_count) {
2190 case LANE_COUNT_ONE:
2191 return LANE_COUNT_TWO;
2192 case LANE_COUNT_TWO:
2193 return LANE_COUNT_FOUR;
2195 return LANE_COUNT_UNKNOWN;
2199 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2201 switch (link_rate) {
2203 return LINK_RATE_HIGH;
2204 case LINK_RATE_HIGH:
2205 return LINK_RATE_HIGH2;
2206 case LINK_RATE_HIGH2:
2207 return LINK_RATE_HIGH3;
2209 return LINK_RATE_UNKNOWN;
2214 * function: set link rate and lane count fallback based
2215 * on current link setting and last link training result
2217 * true - link setting could be set
2218 * false - has reached minimum setting
2219 * and no further fallback could be done
2221 static bool decide_fallback_link_setting(
2222 struct dc_link_settings initial_link_settings,
2223 struct dc_link_settings *current_link_setting,
2224 enum link_training_result training_result)
2226 if (!current_link_setting)
2229 switch (training_result) {
2230 case LINK_TRAINING_CR_FAIL_LANE0:
2231 case LINK_TRAINING_CR_FAIL_LANE1:
2232 case LINK_TRAINING_CR_FAIL_LANE23:
2233 case LINK_TRAINING_LQA_FAIL:
2235 if (!reached_minimum_link_rate
2236 (current_link_setting->link_rate)) {
2237 current_link_setting->link_rate =
2239 current_link_setting->link_rate);
2240 } else if (!reached_minimum_lane_count
2241 (current_link_setting->lane_count)) {
2242 current_link_setting->link_rate =
2243 initial_link_settings.link_rate;
2244 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2246 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2247 current_link_setting->lane_count =
2249 else if (training_result ==
2250 LINK_TRAINING_CR_FAIL_LANE23)
2251 current_link_setting->lane_count =
2254 current_link_setting->lane_count =
2256 current_link_setting->lane_count);
2262 case LINK_TRAINING_EQ_FAIL_EQ:
2264 if (!reached_minimum_lane_count
2265 (current_link_setting->lane_count)) {
2266 current_link_setting->lane_count =
2268 current_link_setting->lane_count);
2269 } else if (!reached_minimum_link_rate
2270 (current_link_setting->link_rate)) {
2271 current_link_setting->link_rate =
2273 current_link_setting->link_rate);
2279 case LINK_TRAINING_EQ_FAIL_CR:
2281 if (!reached_minimum_link_rate
2282 (current_link_setting->link_rate)) {
2283 current_link_setting->link_rate =
2285 current_link_setting->link_rate);
2297 bool dp_validate_mode_timing(
2298 struct dc_link *link,
2299 const struct dc_crtc_timing *timing)
2304 const struct dc_link_settings *link_setting;
2306 /*always DP fail safe mode*/
2307 if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2308 timing->h_addressable == (uint32_t) 640 &&
2309 timing->v_addressable == (uint32_t) 480)
2312 link_setting = dc_link_get_link_cap(link);
2314 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2315 /*if (flags.DYNAMIC_VALIDATION == 1 &&
2316 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2317 link_setting = &link->verified_link_cap;
2320 req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2321 max_bw = dc_link_bandwidth_kbps(link, link_setting);
2323 if (req_bw <= max_bw) {
2324 /* remember the biggest mode here, during
2325 * initial link training (to get
2326 * verified_link_cap), LS sends event about
2327 * cannot train at reported cap to upper
2328 * layer and upper layer will re-enumerate modes.
2329 * this is not necessary if the lower
2330 * verified_link_cap is enough to drive
2333 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2334 /* if (flags.DYNAMIC_VALIDATION == 1)
2335 dpsst->max_req_bw_for_verified_linkcap = dal_max(
2336 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2342 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2344 struct dc_link_settings initial_link_setting = {
2345 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2346 struct dc_link_settings current_link_setting =
2347 initial_link_setting;
2350 /* search for the minimum link setting that:
2351 * 1. is supported according to the link training result
2352 * 2. could support the b/w requested by the timing
2354 while (current_link_setting.link_rate <=
2355 link->verified_link_cap.link_rate) {
2356 link_bw = dc_link_bandwidth_kbps(
2358 ¤t_link_setting);
2359 if (req_bw <= link_bw) {
2360 *link_setting = current_link_setting;
2364 if (current_link_setting.lane_count <
2365 link->verified_link_cap.lane_count) {
2366 current_link_setting.lane_count =
2367 increase_lane_count(
2368 current_link_setting.lane_count);
2370 current_link_setting.link_rate =
2372 current_link_setting.link_rate);
2373 current_link_setting.lane_count =
2374 initial_link_setting.lane_count;
2381 static bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2383 struct dc_link_settings initial_link_setting;
2384 struct dc_link_settings current_link_setting;
2387 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
2388 link->dpcd_caps.edp_supported_link_rates_count == 0) {
2389 *link_setting = link->verified_link_cap;
2393 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2394 initial_link_setting.lane_count = LANE_COUNT_ONE;
2395 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2396 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2397 initial_link_setting.use_link_rate_set = true;
2398 initial_link_setting.link_rate_set = 0;
2399 current_link_setting = initial_link_setting;
2401 /* search for the minimum link setting that:
2402 * 1. is supported according to the link training result
2403 * 2. could support the b/w requested by the timing
2405 while (current_link_setting.link_rate <=
2406 link->verified_link_cap.link_rate) {
2407 link_bw = dc_link_bandwidth_kbps(
2409 ¤t_link_setting);
2410 if (req_bw <= link_bw) {
2411 *link_setting = current_link_setting;
2415 if (current_link_setting.lane_count <
2416 link->verified_link_cap.lane_count) {
2417 current_link_setting.lane_count =
2418 increase_lane_count(
2419 current_link_setting.lane_count);
2421 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2422 current_link_setting.link_rate_set++;
2423 current_link_setting.link_rate =
2424 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2425 current_link_setting.lane_count =
2426 initial_link_setting.lane_count;
2434 void decide_link_settings(struct dc_stream_state *stream,
2435 struct dc_link_settings *link_setting)
2437 struct dc_link *link;
2440 req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2442 link = stream->link;
2444 /* if preferred is specified through AMDDP, use it, if it's enough
2447 if (link->preferred_link_setting.lane_count !=
2448 LANE_COUNT_UNKNOWN &&
2449 link->preferred_link_setting.link_rate !=
2450 LINK_RATE_UNKNOWN) {
2451 *link_setting = link->preferred_link_setting;
2455 /* MST doesn't perform link training for now
2456 * TODO: add MST specific link training routine
2458 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2459 *link_setting = link->verified_link_cap;
2463 if (link->connector_signal == SIGNAL_TYPE_EDP) {
2464 if (decide_edp_link_settings(link, link_setting, req_bw))
2466 } else if (decide_dp_link_settings(link, link_setting, req_bw))
2469 BREAK_TO_DEBUGGER();
2470 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2472 *link_setting = link->verified_link_cap;
2475 /*************************Short Pulse IRQ***************************/
2476 static bool allow_hpd_rx_irq(const struct dc_link *link)
2479 * Don't handle RX IRQ unless one of following is met:
2480 * 1) The link is established (cur_link_settings != unknown)
2481 * 2) We kicked off MST detection
2482 * 3) We know we're dealing with an active dongle
2485 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2486 (link->type == dc_connection_mst_branch) ||
2487 is_dp_active_dongle(link))
2493 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2495 union dpcd_psr_configuration psr_configuration;
2497 if (!link->psr_settings.psr_feature_enabled)
2500 dm_helpers_dp_read_dpcd(
2503 368,/*DpcdAddress_PSR_Enable_Cfg*/
2504 &psr_configuration.raw,
2505 sizeof(psr_configuration.raw));
2508 if (psr_configuration.bits.ENABLE) {
2509 unsigned char dpcdbuf[3] = {0};
2510 union psr_error_status psr_error_status;
2511 union psr_sink_psr_status psr_sink_psr_status;
2513 dm_helpers_dp_read_dpcd(
2516 0x2006, /*DpcdAddress_PSR_Error_Status*/
2517 (unsigned char *) dpcdbuf,
2520 /*DPCD 2006h ERROR STATUS*/
2521 psr_error_status.raw = dpcdbuf[0];
2522 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
2523 psr_sink_psr_status.raw = dpcdbuf[2];
2525 if (psr_error_status.bits.LINK_CRC_ERROR ||
2526 psr_error_status.bits.RFB_STORAGE_ERROR) {
2527 /* Acknowledge and clear error bits */
2528 dm_helpers_dp_write_dpcd(
2531 8198,/*DpcdAddress_PSR_Error_Status*/
2532 &psr_error_status.raw,
2533 sizeof(psr_error_status.raw));
2535 /* PSR error, disable and re-enable PSR */
2536 dc_link_set_psr_allow_active(link, false, true);
2537 dc_link_set_psr_allow_active(link, true, true);
2540 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2541 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2542 /* No error is detect, PSR is active.
2543 * We should return with IRQ_HPD handled without
2544 * checking for loss of sync since PSR would have
2545 * powered down main link.
2553 static void dp_test_send_link_training(struct dc_link *link)
2555 struct dc_link_settings link_settings = {0};
2557 core_link_read_dpcd(
2560 (unsigned char *)(&link_settings.lane_count),
2562 core_link_read_dpcd(
2565 (unsigned char *)(&link_settings.link_rate),
2568 /* Set preferred link settings */
2569 link->verified_link_cap.lane_count = link_settings.lane_count;
2570 link->verified_link_cap.link_rate = link_settings.link_rate;
2572 dp_retrain_link_dp_test(link, &link_settings, false);
2575 /* TODO Raven hbr2 compliance eye output is unstable
2576 * (toggling on and off) with debugger break
2577 * This caueses intermittent PHY automation failure
2578 * Need to look into the root cause */
2579 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2581 union phy_test_pattern dpcd_test_pattern;
2582 union lane_adjust dpcd_lane_adjustment[2];
2583 unsigned char dpcd_post_cursor_2_adjustment = 0;
2584 unsigned char test_80_bit_pattern[
2585 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2586 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2587 enum dp_test_pattern test_pattern;
2588 struct dc_link_training_settings link_settings;
2589 union lane_adjust dpcd_lane_adjust;
2591 struct link_training_settings link_training_settings;
2594 dpcd_test_pattern.raw = 0;
2595 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2596 memset(&link_settings, 0, sizeof(link_settings));
2598 /* get phy test pattern and pattern parameters from DP receiver */
2599 core_link_read_dpcd(
2601 DP_PHY_TEST_PATTERN,
2602 &dpcd_test_pattern.raw,
2603 sizeof(dpcd_test_pattern));
2604 core_link_read_dpcd(
2606 DP_ADJUST_REQUEST_LANE0_1,
2607 &dpcd_lane_adjustment[0].raw,
2608 sizeof(dpcd_lane_adjustment));
2610 /*get post cursor 2 parameters
2611 * For DP 1.1a or eariler, this DPCD register's value is 0
2612 * For DP 1.2 or later:
2613 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2614 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2616 core_link_read_dpcd(
2618 DP_ADJUST_REQUEST_POST_CURSOR2,
2619 &dpcd_post_cursor_2_adjustment,
2620 sizeof(dpcd_post_cursor_2_adjustment));
2622 /* translate request */
2623 switch (dpcd_test_pattern.bits.PATTERN) {
2624 case PHY_TEST_PATTERN_D10_2:
2625 test_pattern = DP_TEST_PATTERN_D102;
2627 case PHY_TEST_PATTERN_SYMBOL_ERROR:
2628 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2630 case PHY_TEST_PATTERN_PRBS7:
2631 test_pattern = DP_TEST_PATTERN_PRBS7;
2633 case PHY_TEST_PATTERN_80BIT_CUSTOM:
2634 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2636 case PHY_TEST_PATTERN_CP2520_1:
2637 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2638 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2639 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2640 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2642 case PHY_TEST_PATTERN_CP2520_2:
2643 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2644 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2645 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2646 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2648 case PHY_TEST_PATTERN_CP2520_3:
2649 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2652 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2656 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
2657 core_link_read_dpcd(
2659 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2660 test_80_bit_pattern,
2661 sizeof(test_80_bit_pattern));
2663 /* prepare link training settings */
2664 link_settings.link = link->cur_link_settings;
2666 for (lane = 0; lane <
2667 (unsigned int)(link->cur_link_settings.lane_count);
2669 dpcd_lane_adjust.raw =
2670 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2671 link_settings.lane_settings[lane].VOLTAGE_SWING =
2672 (enum dc_voltage_swing)
2673 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2674 link_settings.lane_settings[lane].PRE_EMPHASIS =
2675 (enum dc_pre_emphasis)
2676 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2677 link_settings.lane_settings[lane].POST_CURSOR2 =
2678 (enum dc_post_cursor2)
2679 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2682 for (i = 0; i < 4; i++)
2683 link_training_settings.lane_settings[i] =
2684 link_settings.lane_settings[i];
2685 link_training_settings.link_settings = link_settings.link;
2686 link_training_settings.allow_invalid_msa_timing_param = false;
2687 /*Usage: Measure DP physical lane signal
2688 * by DP SI test equipment automatically.
2689 * PHY test pattern request is generated by equipment via HPD interrupt.
2690 * HPD needs to be active all the time. HPD should be active
2691 * all the time. Do not touch it.
2692 * forward request to DS
2694 dc_link_dp_set_test_pattern(
2697 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2698 &link_training_settings,
2699 test_80_bit_pattern,
2700 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2701 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
2704 static void dp_test_send_link_test_pattern(struct dc_link *link)
2706 union link_test_pattern dpcd_test_pattern;
2707 union test_misc dpcd_test_params;
2708 enum dp_test_pattern test_pattern;
2709 enum dp_test_pattern_color_space test_pattern_color_space =
2710 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2712 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2713 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2715 /* get link test pattern and pattern parameters */
2716 core_link_read_dpcd(
2719 &dpcd_test_pattern.raw,
2720 sizeof(dpcd_test_pattern));
2721 core_link_read_dpcd(
2724 &dpcd_test_params.raw,
2725 sizeof(dpcd_test_params));
2727 switch (dpcd_test_pattern.bits.PATTERN) {
2728 case LINK_TEST_PATTERN_COLOR_RAMP:
2729 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2731 case LINK_TEST_PATTERN_VERTICAL_BARS:
2732 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2733 break; /* black and white */
2734 case LINK_TEST_PATTERN_COLOR_SQUARES:
2735 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2736 TEST_DYN_RANGE_VESA ?
2737 DP_TEST_PATTERN_COLOR_SQUARES :
2738 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2741 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2745 if (dpcd_test_params.bits.CLR_FORMAT == 0)
2746 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
2748 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
2749 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
2750 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2752 dc_link_dp_set_test_pattern(
2755 test_pattern_color_space,
2761 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
2763 union audio_test_mode dpcd_test_mode = {0};
2764 struct audio_test_pattern_type dpcd_pattern_type = {0};
2765 union audio_test_pattern_period dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
2766 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2768 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2769 struct pipe_ctx *pipe_ctx = &pipes[0];
2770 unsigned int channel_count;
2771 unsigned int channel = 0;
2772 unsigned int modes = 0;
2773 unsigned int sampling_rate_in_hz = 0;
2775 // get audio test mode and test pattern parameters
2776 core_link_read_dpcd(
2779 &dpcd_test_mode.raw,
2780 sizeof(dpcd_test_mode));
2782 core_link_read_dpcd(
2784 DP_TEST_AUDIO_PATTERN_TYPE,
2785 &dpcd_pattern_type.value,
2786 sizeof(dpcd_pattern_type));
2788 channel_count = dpcd_test_mode.bits.channel_count + 1;
2790 // read pattern periods for requested channels when sawTooth pattern is requested
2791 if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
2792 dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
2794 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
2795 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2796 // read period for each channel
2797 for (channel = 0; channel < channel_count; channel++) {
2798 core_link_read_dpcd(
2800 DP_TEST_AUDIO_PERIOD_CH1 + channel,
2801 &dpcd_pattern_period[channel].raw,
2802 sizeof(dpcd_pattern_period[channel]));
2806 // translate sampling rate
2807 switch (dpcd_test_mode.bits.sampling_rate) {
2808 case AUDIO_SAMPLING_RATE_32KHZ:
2809 sampling_rate_in_hz = 32000;
2811 case AUDIO_SAMPLING_RATE_44_1KHZ:
2812 sampling_rate_in_hz = 44100;
2814 case AUDIO_SAMPLING_RATE_48KHZ:
2815 sampling_rate_in_hz = 48000;
2817 case AUDIO_SAMPLING_RATE_88_2KHZ:
2818 sampling_rate_in_hz = 88200;
2820 case AUDIO_SAMPLING_RATE_96KHZ:
2821 sampling_rate_in_hz = 96000;
2823 case AUDIO_SAMPLING_RATE_176_4KHZ:
2824 sampling_rate_in_hz = 176400;
2826 case AUDIO_SAMPLING_RATE_192KHZ:
2827 sampling_rate_in_hz = 192000;
2830 sampling_rate_in_hz = 0;
2834 link->audio_test_data.flags.test_requested = 1;
2835 link->audio_test_data.flags.disable_video = disable_video;
2836 link->audio_test_data.sampling_rate = sampling_rate_in_hz;
2837 link->audio_test_data.channel_count = channel_count;
2838 link->audio_test_data.pattern_type = test_pattern;
2840 if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
2841 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
2842 link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
2847 static void handle_automated_test(struct dc_link *link)
2849 union test_request test_request;
2850 union test_response test_response;
2852 memset(&test_request, 0, sizeof(test_request));
2853 memset(&test_response, 0, sizeof(test_response));
2855 core_link_read_dpcd(
2859 sizeof(union test_request));
2860 if (test_request.bits.LINK_TRAINING) {
2861 /* ACK first to let DP RX test box monitor LT sequence */
2862 test_response.bits.ACK = 1;
2863 core_link_write_dpcd(
2867 sizeof(test_response));
2868 dp_test_send_link_training(link);
2869 /* no acknowledge request is needed again */
2870 test_response.bits.ACK = 0;
2872 if (test_request.bits.LINK_TEST_PATTRN) {
2873 dp_test_send_link_test_pattern(link);
2874 test_response.bits.ACK = 1;
2877 if (test_request.bits.AUDIO_TEST_PATTERN) {
2878 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
2879 test_response.bits.ACK = 1;
2882 if (test_request.bits.PHY_TEST_PATTERN) {
2883 dp_test_send_phy_test_pattern(link);
2884 test_response.bits.ACK = 1;
2887 /* send request acknowledgment */
2888 if (test_response.bits.ACK)
2889 core_link_write_dpcd(
2893 sizeof(test_response));
2896 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
2898 union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
2899 union device_service_irq device_service_clear = { { 0 } };
2900 enum dc_status result;
2901 bool status = false;
2902 struct pipe_ctx *pipe_ctx;
2906 *out_link_loss = false;
2907 /* For use cases related to down stream connection status change,
2908 * PSR and device auto test, refer to function handle_sst_hpd_irq
2911 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
2912 __func__, link->link_index);
2915 /* All the "handle_hpd_irq_xxx()" methods
2916 * should be called only after
2917 * dal_dpsst_ls_read_hpd_irq_data
2918 * Order of calls is important too
2920 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
2921 if (out_hpd_irq_dpcd_data)
2922 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
2924 if (result != DC_OK) {
2925 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
2930 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2931 device_service_clear.bits.AUTOMATED_TEST = 1;
2932 core_link_write_dpcd(
2934 DP_DEVICE_SERVICE_IRQ_VECTOR,
2935 &device_service_clear.raw,
2936 sizeof(device_service_clear.raw));
2937 device_service_clear.raw = 0;
2938 handle_automated_test(link);
2942 if (!allow_hpd_rx_irq(link)) {
2943 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
2944 __func__, link->link_index);
2948 if (handle_hpd_irq_psr_sink(link))
2949 /* PSR-related error was detected and handled */
2952 /* If PSR-related error handled, Main link may be off,
2953 * so do not handle as a normal sink status change interrupt.
2956 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
2959 /* check if we have MST msg and return since we poll for it */
2960 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
2963 /* For now we only handle 'Downstream port status' case.
2964 * If we got sink count changed it means
2965 * Downstream port status changed,
2966 * then DM should call DC to do the detection.
2967 * NOTE: Do not handle link loss on eDP since it is internal link*/
2968 if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
2969 hpd_rx_irq_check_link_loss_status(
2971 &hpd_irq_dpcd_data)) {
2972 /* Connectivity log: link loss */
2973 CONN_DATA_LINK_LOSS(link,
2974 hpd_irq_dpcd_data.raw,
2975 sizeof(hpd_irq_dpcd_data),
2978 for (i = 0; i < MAX_PIPES; i++) {
2979 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2980 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2984 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
2988 for (i = 0; i < MAX_PIPES; i++) {
2989 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2990 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
2991 pipe_ctx->stream->link == link)
2992 core_link_disable_stream(pipe_ctx);
2995 for (i = 0; i < MAX_PIPES; i++) {
2996 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2997 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
2998 pipe_ctx->stream->link == link)
2999 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3004 *out_link_loss = true;
3007 if (link->type == dc_connection_active_dongle &&
3008 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3009 != link->dpcd_sink_count)
3012 /* reasons for HPD RX:
3013 * 1. Link Loss - ie Re-train the Link
3014 * 2. MST sideband message
3015 * 3. Automated Test - ie. Internal Commit
3016 * 4. CP (copy protection) - (not interesting for DM???)
3018 * 6. Downstream Port status changed
3019 * -ie. Detect - this the only one
3020 * which is interesting for DM because
3021 * it must call dc_link_detect.
3026 /*query dpcd for version and mst cap addresses*/
3027 bool is_mst_supported(struct dc_link *link)
3030 enum dc_status st = DC_OK;
3034 if (link->preferred_training_settings.mst_enable &&
3035 *link->preferred_training_settings.mst_enable == false) {
3042 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3045 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3047 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3048 &cap.raw, sizeof(cap));
3049 if (st == DC_OK && cap.bits.MST_CAP == 1)
3056 bool is_dp_active_dongle(const struct dc_link *link)
3058 return link->dpcd_caps.is_branch_dev;
3061 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3064 case DOWN_STREAM_MAX_8BPC:
3066 case DOWN_STREAM_MAX_10BPC:
3068 case DOWN_STREAM_MAX_12BPC:
3070 case DOWN_STREAM_MAX_16BPC:
3079 static void read_dp_device_vendor_id(struct dc_link *link)
3081 struct dp_device_vendor_id dp_id;
3083 /* read IEEE branch device id */
3084 core_link_read_dpcd(
3090 link->dpcd_caps.branch_dev_id =
3091 (dp_id.ieee_oui[0] << 16) +
3092 (dp_id.ieee_oui[1] << 8) +
3096 link->dpcd_caps.branch_dev_name,
3097 dp_id.ieee_device_id,
3098 sizeof(dp_id.ieee_device_id));
3103 static void get_active_converter_info(
3104 uint8_t data, struct dc_link *link)
3106 union dp_downstream_port_present ds_port = { .byte = data };
3107 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3109 /* decode converter info*/
3110 if (!ds_port.fields.PORT_PRESENT) {
3111 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3112 ddc_service_set_dongle_type(link->ddc,
3113 link->dpcd_caps.dongle_type);
3114 link->dpcd_caps.is_branch_dev = false;
3118 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3119 if (ds_port.fields.PORT_TYPE == DOWNSTREAM_DP) {
3120 link->dpcd_caps.is_branch_dev = false;
3124 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3127 switch (ds_port.fields.PORT_TYPE) {
3128 case DOWNSTREAM_VGA:
3129 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3131 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3132 /* At this point we don't know is it DVI or HDMI or DP++,
3134 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3137 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3141 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3142 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3143 union dwnstream_port_caps_byte0 *port_caps =
3144 (union dwnstream_port_caps_byte0 *)det_caps;
3145 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3146 det_caps, sizeof(det_caps)) == DC_OK) {
3148 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3149 /*Handle DP case as DONGLE_NONE*/
3150 case DOWN_STREAM_DETAILED_DP:
3151 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3153 case DOWN_STREAM_DETAILED_VGA:
3154 link->dpcd_caps.dongle_type =
3155 DISPLAY_DONGLE_DP_VGA_CONVERTER;
3157 case DOWN_STREAM_DETAILED_DVI:
3158 link->dpcd_caps.dongle_type =
3159 DISPLAY_DONGLE_DP_DVI_CONVERTER;
3161 case DOWN_STREAM_DETAILED_HDMI:
3162 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3163 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3164 link->dpcd_caps.dongle_type =
3165 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3167 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3168 if (ds_port.fields.DETAILED_CAPS) {
3170 union dwnstream_port_caps_byte3_hdmi
3171 hdmi_caps = {.raw = det_caps[3] };
3172 union dwnstream_port_caps_byte2
3173 hdmi_color_caps = {.raw = det_caps[2] };
3174 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3177 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3178 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3179 /*YCBCR capability only for HDMI case*/
3180 if (port_caps->bits.DWN_STRM_PORTX_TYPE
3181 == DOWN_STREAM_DETAILED_HDMI) {
3182 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3183 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3184 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3185 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3186 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3187 hdmi_caps.bits.YCrCr422_CONVERSION;
3188 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3189 hdmi_caps.bits.YCrCr420_CONVERSION;
3192 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3193 translate_dpcd_max_bpc(
3194 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3196 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3197 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3205 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3208 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3210 core_link_read_dpcd(
3212 DP_BRANCH_REVISION_START,
3213 (uint8_t *)&dp_hw_fw_revision,
3214 sizeof(dp_hw_fw_revision));
3216 link->dpcd_caps.branch_hw_revision =
3217 dp_hw_fw_revision.ieee_hw_rev;
3220 link->dpcd_caps.branch_fw_revision,
3221 dp_hw_fw_revision.ieee_fw_rev,
3222 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3226 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3231 if (!link->dpcd_caps.dpcd_rev.raw) {
3233 dp_receiver_power_ctrl(link, true);
3234 core_link_read_dpcd(link, DP_DPCD_REV,
3236 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3239 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3242 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3243 switch (link->dpcd_caps.branch_dev_id) {
3244 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3245 * all internal circuits including AUX communication preventing
3246 * reading DPCD table and EDID (spec violation).
3247 * Encoder will skip DP RX power down on disable_output to
3248 * keep receiver powered all the time.*/
3249 case DP_BRANCH_DEVICE_ID_0010FA:
3250 case DP_BRANCH_DEVICE_ID_0080E1:
3251 case DP_BRANCH_DEVICE_ID_00E04C:
3252 link->wa_flags.dp_keep_receiver_powered = true;
3255 /* TODO: May need work around for other dongles. */
3257 link->wa_flags.dp_keep_receiver_powered = false;
3261 link->wa_flags.dp_keep_receiver_powered = false;
3264 /* Read additional sink caps defined in source specific DPCD area
3265 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3267 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3274 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3277 link->dpcd_sink_ext_caps.raw = dpcd_data;
3281 static bool retrieve_link_cap(struct dc_link *link)
3283 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3284 * which means size 16 will be good for both of those DPCD register block reads
3286 uint8_t dpcd_data[16];
3287 uint8_t lttpr_dpcd_data[6];
3289 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3291 uint8_t dpcd_dprx_data = '\0';
3292 uint8_t dpcd_power_state = '\0';
3294 struct dp_device_vendor_id sink_id;
3295 union down_stream_port_count down_strm_port_count;
3296 union edp_configuration_cap edp_config_cap;
3297 union dp_downstream_port_present ds_port = { 0 };
3298 enum dc_status status = DC_ERROR_UNEXPECTED;
3299 uint32_t read_dpcd_retry_cnt = 3;
3301 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3302 bool is_lttpr_present = false;
3303 const uint32_t post_oui_delay = 30; // 30ms
3305 memset(dpcd_data, '\0', sizeof(dpcd_data));
3306 memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3307 memset(&down_strm_port_count,
3308 '\0', sizeof(union down_stream_port_count));
3309 memset(&edp_config_cap, '\0',
3310 sizeof(union edp_configuration_cap));
3312 /* if extended timeout is supported in hardware,
3313 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3314 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3316 dc_link_aux_try_to_configure_timeout(link->ddc,
3317 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3319 status = core_link_read_dpcd(link, DP_SET_POWER,
3320 &dpcd_power_state, sizeof(dpcd_power_state));
3322 /* Delay 1 ms if AUX CH is in power down state. Based on spec
3323 * section 2.3.1.2, if AUX CH may be powered down due to
3324 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3325 * signal and may need up to 1 ms before being able to reply.
3327 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3330 dpcd_set_source_specific_data(link);
3331 /* Sink may need to configure internals based on vendor, so allow some
3332 * time before proceeding with possibly vendor specific transactions
3334 msleep(post_oui_delay);
3336 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3337 status = core_link_read_dpcd(
3342 if (status == DC_OK)
3346 if (status != DC_OK) {
3347 dm_error("%s: Read dpcd data failed.\n", __func__);
3351 if (link->dc->caps.extended_aux_timeout_support &&
3352 link->dc->config.allow_lttpr_non_transparent_mode) {
3353 /* By reading LTTPR capability, RX assumes that we will enable
3354 * LTTPR non transparent if LTTPR is present.
3355 * Therefore, only query LTTPR capability when both LTTPR
3356 * extended aux timeout and
3357 * non transparent mode is supported by hardware
3359 status = core_link_read_dpcd(
3361 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3363 sizeof(lttpr_dpcd_data));
3365 link->dpcd_caps.lttpr_caps.revision.raw =
3366 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3367 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3369 link->dpcd_caps.lttpr_caps.max_link_rate =
3370 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3371 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3373 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3374 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3375 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3377 link->dpcd_caps.lttpr_caps.max_lane_count =
3378 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3379 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3381 link->dpcd_caps.lttpr_caps.mode =
3382 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3383 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3385 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3386 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3387 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3389 is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3390 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3391 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3392 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3393 if (is_lttpr_present)
3394 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3397 /* decide lttpr non transparent mode */
3398 link->lttpr_non_transparent_mode = is_lttpr_present;
3400 if (!is_lttpr_present)
3401 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3405 union training_aux_rd_interval aux_rd_interval;
3407 aux_rd_interval.raw =
3408 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3410 link->dpcd_caps.ext_receiver_cap_field_present =
3411 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3413 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3414 uint8_t ext_cap_data[16];
3416 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3417 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3418 status = core_link_read_dpcd(
3422 sizeof(ext_cap_data));
3423 if (status == DC_OK) {
3424 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3428 if (status != DC_OK)
3429 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3433 link->dpcd_caps.dpcd_rev.raw =
3434 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3436 if (link->dpcd_caps.ext_receiver_cap_field_present) {
3437 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3438 status = core_link_read_dpcd(
3440 DP_DPRX_FEATURE_ENUMERATION_LIST,
3442 sizeof(dpcd_dprx_data));
3443 if (status == DC_OK)
3447 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3449 if (status != DC_OK)
3450 dm_error("%s: Read DPRX caps data failed.\n", __func__);
3454 link->dpcd_caps.dprx_feature.raw = 0;
3458 /* Error condition checking...
3459 * It is impossible for Sink to report Max Lane Count = 0.
3460 * It is possible for Sink to report Max Link Rate = 0, if it is
3461 * an eDP device that is reporting specialized link rates in the
3462 * SUPPORTED_LINK_RATE table.
3464 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3467 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3470 read_dp_device_vendor_id(link);
3472 get_active_converter_info(ds_port.byte, link);
3474 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3476 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3479 link->dpcd_caps.allow_invalid_MSA_timing_param =
3480 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3482 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3483 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3485 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3486 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3488 link->reported_link_cap.lane_count =
3489 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3490 link->reported_link_cap.link_rate = dpcd_data[
3491 DP_MAX_LINK_RATE - DP_DPCD_REV];
3492 link->reported_link_cap.link_spread =
3493 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3494 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3496 edp_config_cap.raw = dpcd_data[
3497 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3498 link->dpcd_caps.panel_mode_edp =
3499 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3500 link->dpcd_caps.dpcd_display_control_capable =
3501 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3503 link->test_pattern_enabled = false;
3504 link->compliance_test_state.raw = 0;
3506 /* read sink count */
3507 core_link_read_dpcd(link,
3509 &link->dpcd_caps.sink_count.raw,
3510 sizeof(link->dpcd_caps.sink_count.raw));
3512 /* read sink ieee oui */
3513 core_link_read_dpcd(link,
3515 (uint8_t *)(&sink_id),
3518 link->dpcd_caps.sink_dev_id =
3519 (sink_id.ieee_oui[0] << 16) +
3520 (sink_id.ieee_oui[1] << 8) +
3521 (sink_id.ieee_oui[2]);
3524 link->dpcd_caps.sink_dev_id_str,
3525 sink_id.ieee_device_id,
3526 sizeof(sink_id.ieee_device_id));
3528 /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3530 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3532 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3533 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3534 sizeof(str_mbp_2017))) {
3535 link->reported_link_cap.link_rate = 0x0c;
3539 core_link_read_dpcd(
3541 DP_SINK_HW_REVISION_START,
3542 (uint8_t *)&dp_hw_fw_revision,
3543 sizeof(dp_hw_fw_revision));
3545 link->dpcd_caps.sink_hw_revision =
3546 dp_hw_fw_revision.ieee_hw_rev;
3549 link->dpcd_caps.sink_fw_revision,
3550 dp_hw_fw_revision.ieee_fw_rev,
3551 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3553 memset(&link->dpcd_caps.dsc_caps, '\0',
3554 sizeof(link->dpcd_caps.dsc_caps));
3555 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3556 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3557 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3558 status = core_link_read_dpcd(
3561 &link->dpcd_caps.fec_cap.raw,
3562 sizeof(link->dpcd_caps.fec_cap.raw));
3563 status = core_link_read_dpcd(
3566 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3567 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3568 status = core_link_read_dpcd(
3570 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3571 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3572 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3575 if (!dpcd_read_sink_ext_caps(link))
3576 link->dpcd_sink_ext_caps.raw = 0;
3578 /* Connectivity log: detection */
3579 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3584 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3586 uint8_t dpcd_data[16];
3587 uint32_t read_dpcd_retry_cnt = 3;
3588 enum dc_status status = DC_ERROR_UNEXPECTED;
3589 union dp_downstream_port_present ds_port = { 0 };
3590 union down_stream_port_count down_strm_port_count;
3591 union edp_configuration_cap edp_config_cap;
3595 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3596 status = core_link_read_dpcd(
3601 if (status == DC_OK)
3605 link->dpcd_caps.dpcd_rev.raw =
3606 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3608 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3611 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3614 get_active_converter_info(ds_port.byte, link);
3616 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3619 link->dpcd_caps.allow_invalid_MSA_timing_param =
3620 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3622 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3623 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3625 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3626 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3628 link->reported_link_cap.lane_count =
3629 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3630 link->reported_link_cap.link_rate = dpcd_data[
3631 DP_MAX_LINK_RATE - DP_DPCD_REV];
3632 link->reported_link_cap.link_spread =
3633 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3634 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3636 edp_config_cap.raw = dpcd_data[
3637 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3638 link->dpcd_caps.panel_mode_edp =
3639 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3640 link->dpcd_caps.dpcd_display_control_capable =
3641 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3646 bool detect_dp_sink_caps(struct dc_link *link)
3648 return retrieve_link_cap(link);
3650 /* dc init_hw has power encoder using default
3651 * signal for connector. For native DP, no
3652 * need to power up encoder again. If not native
3653 * DP, hw_init may need check signal or power up
3656 /* TODO save sink caps in link->sink */
3659 enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
3661 enum dc_link_rate link_rate;
3662 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
3663 switch (link_rate_in_khz) {
3665 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
3668 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
3671 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
3674 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
3677 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2) - 3.24 Gbps/Lane
3680 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
3683 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2) - 5.40 Gbps/Lane
3686 link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3) - 8.10 Gbps/Lane
3689 link_rate = LINK_RATE_UNKNOWN;
3695 void detect_edp_sink_caps(struct dc_link *link)
3697 uint8_t supported_link_rates[16];
3699 uint32_t link_rate_in_khz;
3700 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
3702 retrieve_link_cap(link);
3703 link->dpcd_caps.edp_supported_link_rates_count = 0;
3704 memset(supported_link_rates, 0, sizeof(supported_link_rates));
3706 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
3707 (link->dc->config.optimize_edp_link_rate ||
3708 link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
3709 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
3710 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
3711 supported_link_rates, sizeof(supported_link_rates));
3713 for (entry = 0; entry < 16; entry += 2) {
3714 // DPCD register reports per-lane link rate = 16-bit link rate capability
3715 // value X 200 kHz. Need multiplier to find link rate in kHz.
3716 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3717 supported_link_rates[entry]) * 200;
3719 if (link_rate_in_khz != 0) {
3720 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
3721 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
3722 link->dpcd_caps.edp_supported_link_rates_count++;
3724 if (link->reported_link_cap.link_rate < link_rate)
3725 link->reported_link_cap.link_rate = link_rate;
3729 link->verified_link_cap = link->reported_link_cap;
3731 dc_link_set_default_brightness_aux(link);
3734 void dc_link_dp_enable_hpd(const struct dc_link *link)
3736 struct link_encoder *encoder = link->link_enc;
3738 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3739 encoder->funcs->enable_hpd(encoder);
3742 void dc_link_dp_disable_hpd(const struct dc_link *link)
3744 struct link_encoder *encoder = link->link_enc;
3746 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3747 encoder->funcs->disable_hpd(encoder);
3750 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
3752 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
3753 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
3754 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
3760 static void set_crtc_test_pattern(struct dc_link *link,
3761 struct pipe_ctx *pipe_ctx,
3762 enum dp_test_pattern test_pattern,
3763 enum dp_test_pattern_color_space test_pattern_color_space)
3765 enum controller_dp_test_pattern controller_test_pattern;
3766 enum dc_color_depth color_depth = pipe_ctx->
3767 stream->timing.display_color_depth;
3768 struct bit_depth_reduction_params params;
3769 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
3770 int width = pipe_ctx->stream->timing.h_addressable +
3771 pipe_ctx->stream->timing.h_border_left +
3772 pipe_ctx->stream->timing.h_border_right;
3773 int height = pipe_ctx->stream->timing.v_addressable +
3774 pipe_ctx->stream->timing.v_border_bottom +
3775 pipe_ctx->stream->timing.v_border_top;
3777 memset(¶ms, 0, sizeof(params));
3779 switch (test_pattern) {
3780 case DP_TEST_PATTERN_COLOR_SQUARES:
3781 controller_test_pattern =
3782 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
3784 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3785 controller_test_pattern =
3786 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
3788 case DP_TEST_PATTERN_VERTICAL_BARS:
3789 controller_test_pattern =
3790 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
3792 case DP_TEST_PATTERN_HORIZONTAL_BARS:
3793 controller_test_pattern =
3794 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
3796 case DP_TEST_PATTERN_COLOR_RAMP:
3797 controller_test_pattern =
3798 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
3801 controller_test_pattern =
3802 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
3806 switch (test_pattern) {
3807 case DP_TEST_PATTERN_COLOR_SQUARES:
3808 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3809 case DP_TEST_PATTERN_VERTICAL_BARS:
3810 case DP_TEST_PATTERN_HORIZONTAL_BARS:
3811 case DP_TEST_PATTERN_COLOR_RAMP:
3813 /* disable bit depth reduction */
3814 pipe_ctx->stream->bit_depth_params = params;
3815 opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms);
3816 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3817 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3818 controller_test_pattern, color_depth);
3819 else if (opp->funcs->opp_set_disp_pattern_generator) {
3820 struct pipe_ctx *odm_pipe;
3821 enum controller_dp_color_space controller_color_space;
3824 int dpg_width = width;
3826 switch (test_pattern_color_space) {
3827 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
3828 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
3830 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
3831 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
3833 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
3834 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
3836 case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
3838 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
3839 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
3844 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3846 dpg_width = width / opp_cnt;
3849 opp->funcs->opp_set_disp_pattern_generator(opp,
3850 controller_test_pattern,
3851 controller_color_space,
3858 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3859 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
3860 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms);
3861 odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
3862 controller_test_pattern,
3863 controller_color_space,
3874 case DP_TEST_PATTERN_VIDEO_MODE:
3876 /* restore bitdepth reduction */
3877 resource_build_bit_depth_reduction_params(pipe_ctx->stream, ¶ms);
3878 pipe_ctx->stream->bit_depth_params = params;
3879 opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms);
3880 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3881 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3882 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3884 else if (opp->funcs->opp_set_disp_pattern_generator) {
3885 struct pipe_ctx *odm_pipe;
3887 int dpg_width = width;
3889 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3892 dpg_width = width / opp_cnt;
3893 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3894 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
3896 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms);
3897 odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
3898 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3899 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
3906 opp->funcs->opp_set_disp_pattern_generator(opp,
3907 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3908 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
3923 bool dc_link_dp_set_test_pattern(
3924 struct dc_link *link,
3925 enum dp_test_pattern test_pattern,
3926 enum dp_test_pattern_color_space test_pattern_color_space,
3927 const struct link_training_settings *p_link_settings,
3928 const unsigned char *p_custom_pattern,
3929 unsigned int cust_pattern_size)
3931 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3932 struct pipe_ctx *pipe_ctx = &pipes[0];
3935 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
3936 union dpcd_training_pattern training_pattern;
3937 enum dpcd_phy_test_patterns pattern;
3939 memset(&training_pattern, 0, sizeof(training_pattern));
3941 for (i = 0; i < MAX_PIPES; i++) {
3942 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
3943 pipe_ctx = &pipes[i];
3948 /* Reset CRTC Test Pattern if it is currently running and request
3949 * is VideoMode Reset DP Phy Test Pattern if it is currently running
3950 * and request is VideoMode
3952 if (link->test_pattern_enabled && test_pattern ==
3953 DP_TEST_PATTERN_VIDEO_MODE) {
3954 /* Set CRTC Test Pattern */
3955 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
3956 dp_set_hw_test_pattern(link, test_pattern,
3957 (uint8_t *)p_custom_pattern,
3958 (uint32_t)cust_pattern_size);
3960 /* Unblank Stream */
3961 link->dc->hwss.unblank_stream(
3963 &link->verified_link_cap);
3964 /* TODO:m_pHwss->MuteAudioEndpoint
3965 * (pPathMode->pDisplayPath, false);
3968 /* Reset Test Pattern state */
3969 link->test_pattern_enabled = false;
3974 /* Check for PHY Test Patterns */
3975 if (is_dp_phy_pattern(test_pattern)) {
3976 /* Set DPCD Lane Settings before running test pattern */
3977 if (p_link_settings != NULL) {
3978 dp_set_hw_lane_settings(link, p_link_settings, DPRX);
3979 dpcd_set_lane_settings(link, p_link_settings, DPRX);
3982 /* Blank stream if running test pattern */
3983 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
3986 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
3989 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
3992 dp_set_hw_test_pattern(link, test_pattern,
3993 (uint8_t *)p_custom_pattern,
3994 (uint32_t)cust_pattern_size);
3996 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
3997 /* Set Test Pattern state */
3998 link->test_pattern_enabled = true;
3999 if (p_link_settings != NULL)
4000 dpcd_set_link_settings(link,
4004 switch (test_pattern) {
4005 case DP_TEST_PATTERN_VIDEO_MODE:
4006 pattern = PHY_TEST_PATTERN_NONE;
4008 case DP_TEST_PATTERN_D102:
4009 pattern = PHY_TEST_PATTERN_D10_2;
4011 case DP_TEST_PATTERN_SYMBOL_ERROR:
4012 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4014 case DP_TEST_PATTERN_PRBS7:
4015 pattern = PHY_TEST_PATTERN_PRBS7;
4017 case DP_TEST_PATTERN_80BIT_CUSTOM:
4018 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4020 case DP_TEST_PATTERN_CP2520_1:
4021 pattern = PHY_TEST_PATTERN_CP2520_1;
4023 case DP_TEST_PATTERN_CP2520_2:
4024 pattern = PHY_TEST_PATTERN_CP2520_2;
4026 case DP_TEST_PATTERN_CP2520_3:
4027 pattern = PHY_TEST_PATTERN_CP2520_3;
4033 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4034 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4037 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4038 /* tell receiver that we are sending qualification
4039 * pattern DP 1.2 or later - DP receiver's link quality
4040 * pattern is set using DPCD LINK_QUAL_LANEx_SET
4041 * register (0x10B~0x10E)\
4043 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4044 link_qual_pattern[lane] =
4045 (unsigned char)(pattern);
4047 core_link_write_dpcd(link,
4048 DP_LINK_QUAL_LANE0_SET,
4050 sizeof(link_qual_pattern));
4051 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4052 link->dpcd_caps.dpcd_rev.raw == 0) {
4053 /* tell receiver that we are sending qualification
4054 * pattern DP 1.1a or earlier - DP receiver's link
4055 * quality pattern is set using
4056 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4057 * register (0x102). We will use v_1.3 when we are
4058 * setting test pattern for DP 1.1.
4060 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4061 &training_pattern.raw,
4062 sizeof(training_pattern));
4063 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4064 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4065 &training_pattern.raw,
4066 sizeof(training_pattern));
4069 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4071 switch (test_pattern_color_space) {
4072 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4073 color_space = COLOR_SPACE_SRGB;
4074 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4075 color_space = COLOR_SPACE_SRGB_LIMITED;
4078 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4079 color_space = COLOR_SPACE_YCBCR601;
4080 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4081 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4083 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4084 color_space = COLOR_SPACE_YCBCR709;
4085 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4086 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4092 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4093 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4094 union dmub_hw_lock_flags hw_locks = { 0 };
4095 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4097 hw_locks.bits.lock_dig = 1;
4098 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4100 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4105 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4106 pipe_ctx->stream_res.tg);
4109 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4110 /* update MSA to requested color space */
4111 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4112 &pipe_ctx->stream->timing,
4114 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4115 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4117 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4118 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4119 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4121 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4122 resource_build_info_frame(pipe_ctx);
4123 link->dc->hwss.update_info_frame(pipe_ctx);
4127 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4128 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4129 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4130 CRTC_STATE_VACTIVE);
4131 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4133 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4134 CRTC_STATE_VACTIVE);
4136 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4137 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4138 union dmub_hw_lock_flags hw_locks = { 0 };
4139 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4141 hw_locks.bits.lock_dig = 1;
4142 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4144 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4149 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4150 pipe_ctx->stream_res.tg);
4153 /* Set Test Pattern state */
4154 link->test_pattern_enabled = true;
4160 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4162 unsigned char mstmCntl;
4164 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4166 mstmCntl |= DP_MST_EN;
4168 mstmCntl &= (~DP_MST_EN);
4170 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4173 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4175 union dpcd_edp_config edp_config_set;
4176 bool panel_mode_edp = false;
4178 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4180 if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4182 switch (panel_mode) {
4183 case DP_PANEL_MODE_EDP:
4184 case DP_PANEL_MODE_SPECIAL:
4185 panel_mode_edp = true;
4192 /*set edp panel mode in receiver*/
4193 core_link_read_dpcd(
4195 DP_EDP_CONFIGURATION_SET,
4196 &edp_config_set.raw,
4197 sizeof(edp_config_set.raw));
4199 if (edp_config_set.bits.PANEL_MODE_EDP
4200 != panel_mode_edp) {
4201 enum ddc_result result = DDC_RESULT_UNKNOWN;
4203 edp_config_set.bits.PANEL_MODE_EDP =
4205 result = core_link_write_dpcd(
4207 DP_EDP_CONFIGURATION_SET,
4208 &edp_config_set.raw,
4209 sizeof(edp_config_set.raw));
4211 ASSERT(result == DDC_RESULT_SUCESSFULL);
4214 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4215 "eDP panel mode enabled: %d \n",
4217 link->dpcd_caps.panel_mode_edp,
4221 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4223 /* We need to explicitly check that connector
4224 * is not DP. Some Travis_VGA get reported
4225 * by video bios as DP.
4227 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4229 switch (link->dpcd_caps.branch_dev_id) {
4230 case DP_BRANCH_DEVICE_ID_0022B9:
4231 /* alternate scrambler reset is required for Travis
4232 * for the case when external chip does not
4233 * provide sink device id, alternate scrambler
4234 * scheme will be overriden later by querying
4238 link->dpcd_caps.branch_dev_name,
4239 DP_VGA_LVDS_CONVERTER_ID_2,
4242 branch_dev_name)) == 0) {
4243 return DP_PANEL_MODE_SPECIAL;
4246 case DP_BRANCH_DEVICE_ID_00001A:
4247 /* alternate scrambler reset is required for Travis
4248 * for the case when external chip does not provide
4249 * sink device id, alternate scrambler scheme will
4250 * be overriden later by querying Encoder feature
4252 if (strncmp(link->dpcd_caps.branch_dev_name,
4253 DP_VGA_LVDS_CONVERTER_ID_3,
4256 branch_dev_name)) == 0) {
4257 return DP_PANEL_MODE_SPECIAL;
4265 if (link->dpcd_caps.panel_mode_edp) {
4266 return DP_PANEL_MODE_EDP;
4269 return DP_PANEL_MODE_DEFAULT;
4272 void dp_set_fec_ready(struct dc_link *link, bool ready)
4274 /* FEC has to be "set ready" before the link training.
4275 * The policy is to always train with FEC
4276 * if the sink supports it and leave it enabled on link.
4277 * If FEC is not supported, disable it.
4279 struct link_encoder *link_enc = link->link_enc;
4280 uint8_t fec_config = 0;
4282 if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
4285 if (link_enc->funcs->fec_set_ready &&
4286 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4289 if (core_link_write_dpcd(link,
4290 DP_FEC_CONFIGURATION,
4292 sizeof(fec_config)) == DC_OK) {
4293 link_enc->funcs->fec_set_ready(link_enc, true);
4294 link->fec_state = dc_link_fec_ready;
4296 link->link_enc->funcs->fec_set_ready(link->link_enc, false);
4297 link->fec_state = dc_link_fec_not_ready;
4298 dm_error("dpcd write failed to set fec_ready");
4300 } else if (link->fec_state == dc_link_fec_ready) {
4302 core_link_write_dpcd(link,
4303 DP_FEC_CONFIGURATION,
4305 sizeof(fec_config));
4306 link->link_enc->funcs->fec_set_ready(
4307 link->link_enc, false);
4308 link->fec_state = dc_link_fec_not_ready;
4313 void dp_set_fec_enable(struct dc_link *link, bool enable)
4315 struct link_encoder *link_enc = link->link_enc;
4317 if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
4320 if (link_enc->funcs->fec_set_enable &&
4321 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4322 if (link->fec_state == dc_link_fec_ready && enable) {
4323 /* Accord to DP spec, FEC enable sequence can first
4324 * be transmitted anytime after 1000 LL codes have
4325 * been transmitted on the link after link training
4326 * completion. Using 1 lane RBR should have the maximum
4327 * time for transmitting 1000 LL codes which is 6.173 us.
4328 * So use 7 microseconds delay instead.
4331 link_enc->funcs->fec_set_enable(link_enc, true);
4332 link->fec_state = dc_link_fec_enabled;
4333 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4334 link_enc->funcs->fec_set_enable(link_enc, false);
4335 link->fec_state = dc_link_fec_ready;
4340 void dpcd_set_source_specific_data(struct dc_link *link)
4345 ret = core_link_read_dpcd(link, DP_DOWN_STREAM_PORT_COUNT, &dspc,
4349 DC_LOG_ERROR("Error in DP aux read transaction,"
4350 " not writing source specific data\n");
4354 /* Return if OUI unsupported */
4355 if (!(dspc & DP_OUI_SUPPORT))
4358 if (!link->dc->vendor_signature.is_valid) {
4359 struct dpcd_amd_signature amd_signature;
4360 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4361 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4362 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4363 amd_signature.device_id_byte1 =
4364 (uint8_t)(link->ctx->asic_id.chip_id);
4365 amd_signature.device_id_byte2 =
4366 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4367 memset(&amd_signature.zero, 0, 4);
4368 amd_signature.dce_version =
4369 (uint8_t)(link->ctx->dce_version);
4370 amd_signature.dal_version_byte1 = 0x0; // needed? where to get?
4371 amd_signature.dal_version_byte2 = 0x0; // needed? where to get?
4373 core_link_write_dpcd(link, DP_SOURCE_OUI,
4374 (uint8_t *)(&amd_signature),
4375 sizeof(amd_signature));
4378 core_link_write_dpcd(link, DP_SOURCE_OUI,
4379 link->dc->vendor_signature.data.raw,
4380 sizeof(link->dc->vendor_signature.data.raw));
4384 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4386 uint32_t backlight_millinits,
4387 uint32_t transition_time_in_ms)
4389 struct dpcd_source_backlight_set dpcd_backlight_set;
4390 uint8_t backlight_control = isHDR ? 1 : 0;
4392 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4393 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4396 // OLEDs have no PWM, they can only use AUX
4397 if (link->dpcd_sink_ext_caps.bits.oled == 1)
4398 backlight_control = 1;
4400 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4401 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4404 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4405 (uint8_t *)(&dpcd_backlight_set),
4406 sizeof(dpcd_backlight_set)) != DC_OK)
4409 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4410 &backlight_control, 1) != DC_OK)
4416 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4417 uint32_t *backlight_millinits_avg,
4418 uint32_t *backlight_millinits_peak)
4420 union dpcd_source_backlight_get dpcd_backlight_get;
4422 memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4424 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4425 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4428 if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4429 dpcd_backlight_get.raw,
4430 sizeof(union dpcd_source_backlight_get)))
4433 *backlight_millinits_avg =
4434 dpcd_backlight_get.bytes.backlight_millinits_avg;
4435 *backlight_millinits_peak =
4436 dpcd_backlight_get.bytes.backlight_millinits_peak;
4438 /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4439 if (*backlight_millinits_avg == 0 ||
4440 *backlight_millinits_avg > *backlight_millinits_peak)
4446 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4448 uint8_t backlight_enable = enable ? 1 : 0;
4450 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4451 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4454 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4455 &backlight_enable, 1) != DC_OK)
4461 // we read default from 0x320 because we expect BIOS wrote it there
4462 // regular get_backlight_nit reads from panel set at 0x326
4463 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4465 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4466 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4469 if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4470 (uint8_t *) backlight_millinits,
4477 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4479 uint32_t default_backlight;
4482 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4483 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4484 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4485 default_backlight = 150000;
4486 // if < 5 nits or > 5000, it might be wrong readback
4487 if (default_backlight < 5000 || default_backlight > 5000000)
4488 default_backlight = 150000; //
4490 return dc_link_set_backlight_level_nits(link, true,
4491 default_backlight, 0);