drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2 #include "dm_services.h"
   3 #include "dc.h"
   4 #include "dc_link_dp.h"
   5 #include "dm_helpers.h"
   6 #include "opp.h"
   7 #include "dsc.h"
   8 #include "resource.h"
   9
  10 #include "inc/core_types.h"
  11 #include "link_hwss.h"
  12 #include "dc_link_ddc.h"
  13 #include "core_status.h"
  14 #include "dpcd_defs.h"
  15 #include "dc_dmub_srv.h"
  16 #include "dce/dmub_hw_lock_mgr.h"
  17 #include "inc/link_enc_cfg.h"
  18
  19 /*Travis*/
  20 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
  21 /*Nutmeg*/
  22 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
  23
  24 #define DC_LOGGER \
  25         link->ctx->logger
  26 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
  27
  28         /* maximum pre emphasis level allowed for each voltage swing level*/
  29         static const enum dc_pre_emphasis
  30         voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
  31                                             PRE_EMPHASIS_LEVEL2,
  32                                             PRE_EMPHASIS_LEVEL1,
  33                                             PRE_EMPHASIS_DISABLED };
  34
  35 enum {
  36         POST_LT_ADJ_REQ_LIMIT = 6,
  37         POST_LT_ADJ_REQ_TIMEOUT = 200
  38 };
  39
  40 static bool decide_fallback_link_setting(
  41                 struct dc_link_settings initial_link_settings,
  42                 struct dc_link_settings *current_link_setting,
  43                 enum link_training_result training_result);
  44 static struct dc_link_settings get_common_supported_link_settings(
  45                 struct dc_link_settings link_setting_a,
  46                 struct dc_link_settings link_setting_b);
  47
  48 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
  49                 const struct dc_link_settings *link_settings)
  50 {
  51         union training_aux_rd_interval training_rd_interval;
  52         uint32_t wait_in_micro_secs = 100;
  53
  54         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  55         core_link_read_dpcd(
  56                         link,
  57                         DP_TRAINING_AUX_RD_INTERVAL,
  58                         (uint8_t *)&training_rd_interval,
  59                         sizeof(training_rd_interval));
  60         if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  61                 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  62         return wait_in_micro_secs;
  63 }
  64
  65 static uint32_t get_eq_training_aux_rd_interval(
  66         struct dc_link *link,
  67         const struct dc_link_settings *link_settings)
  68 {
  69         union training_aux_rd_interval training_rd_interval;
  70         uint32_t wait_in_micro_secs = 400;
  71
  72         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  73         /* overwrite the delay if rev > 1.1*/
  74         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  75                 /* DP 1.2 or later - retrieve delay through
  76                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
  77                 core_link_read_dpcd(
  78                         link,
  79                         DP_TRAINING_AUX_RD_INTERVAL,
  80                         (uint8_t *)&training_rd_interval,
  81                         sizeof(training_rd_interval));
  82
  83                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  84                         wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  85         }
  86
  87         return wait_in_micro_secs;
  88 }
  89
  90 void dp_wait_for_training_aux_rd_interval(
  91         struct dc_link *link,
  92         uint32_t wait_in_micro_secs)
  93 {
  94         udelay(wait_in_micro_secs);
  95
  96         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
  97                 __func__,
  98                 wait_in_micro_secs);
  99 }
 100
 101 enum dpcd_training_patterns
 102         dc_dp_training_pattern_to_dpcd_training_pattern(
 103         struct dc_link *link,
 104         enum dc_dp_training_pattern pattern)
 105 {
 106         enum dpcd_training_patterns dpcd_tr_pattern =
 107         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 108
 109         switch (pattern) {
 110         case DP_TRAINING_PATTERN_SEQUENCE_1:
 111                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 112                 break;
 113         case DP_TRAINING_PATTERN_SEQUENCE_2:
 114                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 115                 break;
 116         case DP_TRAINING_PATTERN_SEQUENCE_3:
 117                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 118                 break;
 119         case DP_TRAINING_PATTERN_SEQUENCE_4:
 120                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 121                 break;
 122         case DP_TRAINING_PATTERN_VIDEOIDLE:
 123                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
 124                 break;
 125         default:
 126                 ASSERT(0);
 127                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 128                         __func__, pattern);
 129                 break;
 130         }
 131
 132         return dpcd_tr_pattern;
 133 }
 134
 135 static void dpcd_set_training_pattern(
 136         struct dc_link *link,
 137         enum dc_dp_training_pattern training_pattern)
 138 {
 139         union dpcd_training_pattern dpcd_pattern = { {0} };
 140
 141         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 142                         dc_dp_training_pattern_to_dpcd_training_pattern(
 143                                         link, training_pattern);
 144
 145         core_link_write_dpcd(
 146                 link,
 147                 DP_TRAINING_PATTERN_SET,
 148                 &dpcd_pattern.raw,
 149                 1);
 150
 151         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
 152                 __func__,
 153                 DP_TRAINING_PATTERN_SET,
 154                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 155 }
 156
 157 static enum dc_dp_training_pattern decide_cr_training_pattern(
 158                 const struct dc_link_settings *link_settings)
 159 {
 160         return DP_TRAINING_PATTERN_SEQUENCE_1;
 161 }
 162
 163 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
 164                 const struct dc_link_settings *link_settings)
 165 {
 166         struct link_encoder *link_enc;
 167         enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
 168         struct encoder_feature_support *features;
 169         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 170
 171         /* Access link encoder capability based on whether it is statically
 172          * or dynamically assigned to a link.
 173          */
 174         if (link->is_dig_mapping_flexible &&
 175                         link->dc->res_pool->funcs->link_encs_assign)
 176                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
 177         else
 178                 link_enc = link->link_enc;
 179         ASSERT(link_enc);
 180         features = &link_enc->features;
 181
 182         if (features->flags.bits.IS_TPS3_CAPABLE)
 183                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 184
 185         if (features->flags.bits.IS_TPS4_CAPABLE)
 186                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
 187
 188         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 189                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
 190                 return DP_TRAINING_PATTERN_SEQUENCE_4;
 191
 192         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 193                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
 194                 return DP_TRAINING_PATTERN_SEQUENCE_3;
 195
 196         return DP_TRAINING_PATTERN_SEQUENCE_2;
 197 }
 198
 199 enum dc_status dpcd_set_link_settings(
 200         struct dc_link *link,
 201         const struct link_training_settings *lt_settings)
 202 {
 203         uint8_t rate;
 204         enum dc_status status;
 205
 206         union down_spread_ctrl downspread = { {0} };
 207         union lane_count_set lane_count_set = { {0} };
 208
 209         downspread.raw = (uint8_t)
 210         (lt_settings->link_settings.link_spread);
 211
 212         lane_count_set.bits.LANE_COUNT_SET =
 213         lt_settings->link_settings.lane_count;
 214
 215         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
 216         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 217
 218
 219         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
 220                         lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
 221                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 222                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 223         }
 224
 225         status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 226                 &downspread.raw, sizeof(downspread));
 227
 228         status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 229                 &lane_count_set.raw, 1);
 230
 231         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 232                         lt_settings->link_settings.use_link_rate_set == true) {
 233                 rate = 0;
 234                 /* WA for some MUX chips that will power down with eDP and lose supported
 235                  * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
 236                  * MUX chip gets link rate set back before link training.
 237                  */
 238                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 239                         uint8_t supported_link_rates[16];
 240
 241                         core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
 242                                         supported_link_rates, sizeof(supported_link_rates));
 243                 }
 244                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 245                 status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
 246                                 &lt_settings->link_settings.link_rate_set, 1);
 247         } else {
 248                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 249                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 250         }
 251
 252         if (rate) {
 253                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 254                         __func__,
 255                         DP_LINK_BW_SET,
 256                         lt_settings->link_settings.link_rate,
 257                         DP_LANE_COUNT_SET,
 258                         lt_settings->link_settings.lane_count,
 259                         lt_settings->enhanced_framing,
 260                         DP_DOWNSPREAD_CTRL,
 261                         lt_settings->link_settings.link_spread);
 262         } else {
 263                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 264                         __func__,
 265                         DP_LINK_RATE_SET,
 266                         lt_settings->link_settings.link_rate_set,
 267                         DP_LANE_COUNT_SET,
 268                         lt_settings->link_settings.lane_count,
 269                         lt_settings->enhanced_framing,
 270                         DP_DOWNSPREAD_CTRL,
 271                         lt_settings->link_settings.link_spread);
 272         }
 273
 274         return status;
 275 }
 276
 277 uint8_t dc_dp_initialize_scrambling_data_symbols(
 278         struct dc_link *link,
 279         enum dc_dp_training_pattern pattern)
 280 {
 281         uint8_t disable_scrabled_data_symbols = 0;
 282
 283         switch (pattern) {
 284         case DP_TRAINING_PATTERN_SEQUENCE_1:
 285         case DP_TRAINING_PATTERN_SEQUENCE_2:
 286         case DP_TRAINING_PATTERN_SEQUENCE_3:
 287                 disable_scrabled_data_symbols = 1;
 288                 break;
 289         case DP_TRAINING_PATTERN_SEQUENCE_4:
 290                 disable_scrabled_data_symbols = 0;
 291                 break;
 292         default:
 293                 ASSERT(0);
 294                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 295                         __func__, pattern);
 296                 break;
 297         }
 298         return disable_scrabled_data_symbols;
 299 }
 300
 301 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 302 {
 303         return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
 304 }
 305
 306 static void dpcd_set_lt_pattern_and_lane_settings(
 307         struct dc_link *link,
 308         const struct link_training_settings *lt_settings,
 309         enum dc_dp_training_pattern pattern,
 310         uint32_t offset)
 311 {
 312         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
 313
 314         uint32_t dpcd_base_lt_offset;
 315
 316         uint8_t dpcd_lt_buffer[5] = {0};
 317         union dpcd_training_pattern dpcd_pattern = { {0} };
 318         uint32_t lane;
 319         uint32_t size_in_bytes;
 320         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 321         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
 322
 323         if (is_repeater(link, offset))
 324                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
 325                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 326
 327         /*****************************************************************
 328         * DpcdAddress_TrainingPatternSet
 329         *****************************************************************/
 330         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 331                 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
 332
 333         dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
 334                 dc_dp_initialize_scrambling_data_symbols(link, pattern);
 335
 336         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
 337                 = dpcd_pattern.raw;
 338
 339         if (is_repeater(link, offset)) {
 340                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
 341                         __func__,
 342                         offset,
 343                         dpcd_base_lt_offset,
 344                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 345         } else {
 346                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
 347                         __func__,
 348                         dpcd_base_lt_offset,
 349                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 350         }
 351         /*****************************************************************
 352         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 353         *****************************************************************/
 354         for (lane = 0; lane <
 355                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 356
 357                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 358                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 359                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 360                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 361
 362                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 363                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 364                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 365                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 366                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 367                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 368         }
 369
 370         /* concatenate everything into one buffer*/
 371
 372         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 373
 374          // 0x00103 - 0x00102
 375         memmove(
 376                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
 377                 dpcd_lane,
 378                 size_in_bytes);
 379
 380         if (is_repeater(link, offset)) {
 381                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 382                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 383                         __func__,
 384                         offset,
 385                         dpcd_base_lt_offset,
 386                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 387                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 388                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 389                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 390         } else {
 391                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 392                         __func__,
 393                         dpcd_base_lt_offset,
 394                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 395                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 396                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 397                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 398         }
 399         if (edp_workaround) {
 400                 /* for eDP write in 2 parts because the 5-byte burst is
 401                 * causing issues on some eDP panels (EPR#366724)
 402                 */
 403                 core_link_write_dpcd(
 404                         link,
 405                         DP_TRAINING_PATTERN_SET,
 406                         &dpcd_pattern.raw,
 407                         sizeof(dpcd_pattern.raw));
 408
 409                 core_link_write_dpcd(
 410                         link,
 411                         DP_TRAINING_LANE0_SET,
 412                         (uint8_t *)(dpcd_lane),
 413                         size_in_bytes);
 414
 415                 } else
 416                 /* write it all in (1 + number-of-lanes)-byte burst*/
 417                         core_link_write_dpcd(
 418                                 link,
 419                                 dpcd_base_lt_offset,
 420                                 dpcd_lt_buffer,
 421                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 422
 423         link->cur_lane_setting = lt_settings->lane_settings[0];
 424 }
 425
 426 bool dp_is_cr_done(enum dc_lane_count ln_count,
 427         union lane_status *dpcd_lane_status)
 428 {
 429         uint32_t lane;
 430         /*LANEx_CR_DONE bits All 1's?*/
 431         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 432                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 433                         return false;
 434         }
 435         return true;
 436 }
 437
 438 bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
 439                 union lane_status *dpcd_lane_status)
 440 {
 441         bool done = true;
 442         uint32_t lane;
 443         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 444                 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 445                         done = false;
 446         return done;
 447 }
 448
 449 bool dp_is_symbol_locked(enum dc_lane_count ln_count,
 450                 union lane_status *dpcd_lane_status)
 451 {
 452         bool locked = true;
 453         uint32_t lane;
 454         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 455                 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
 456                         locked = false;
 457         return locked;
 458 }
 459
 460 bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
 461 {
 462         return align_status.bits.INTERLANE_ALIGN_DONE == 1;
 463 }
 464
 465 void dp_update_drive_settings(
 466                 struct link_training_settings *dest,
 467                 struct link_training_settings src)
 468 {
 469         uint32_t lane;
 470         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 471                 if (dest->voltage_swing == NULL)
 472                         dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
 473                 else
 474                         dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
 475
 476                 if (dest->pre_emphasis == NULL)
 477                         dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
 478                 else
 479                         dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
 480
 481                 if (dest->post_cursor2 == NULL)
 482                         dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
 483                 else
 484                         dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
 485         }
 486 }
 487
 488 static uint8_t get_nibble_at_index(const uint8_t *buf,
 489         uint32_t index)
 490 {
 491         uint8_t nibble;
 492         nibble = buf[index / 2];
 493
 494         if (index % 2)
 495                 nibble >>= 4;
 496         else
 497                 nibble &= 0x0F;
 498
 499         return nibble;
 500 }
 501
 502 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 503         enum dc_voltage_swing voltage)
 504 {
 505         enum dc_pre_emphasis pre_emphasis;
 506         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 507
 508         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 509                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 510
 511         return pre_emphasis;
 512
 513 }
 514
 515 static void find_max_drive_settings(
 516         const struct link_training_settings *link_training_setting,
 517         struct link_training_settings *max_lt_setting)
 518 {
 519         uint32_t lane;
 520         struct dc_lane_settings max_requested;
 521
 522         max_requested.VOLTAGE_SWING =
 523                 link_training_setting->
 524                 lane_settings[0].VOLTAGE_SWING;
 525         max_requested.PRE_EMPHASIS =
 526                 link_training_setting->
 527                 lane_settings[0].PRE_EMPHASIS;
 528         /*max_requested.postCursor2 =
 529          * link_training_setting->laneSettings[0].postCursor2;*/
 530
 531         /* Determine what the maximum of the requested settings are*/
 532         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 533                         lane++) {
 534                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 535                         max_requested.VOLTAGE_SWING)
 536
 537                         max_requested.VOLTAGE_SWING =
 538                         link_training_setting->
 539                         lane_settings[lane].VOLTAGE_SWING;
 540
 541                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 542                                 max_requested.PRE_EMPHASIS)
 543                         max_requested.PRE_EMPHASIS =
 544                         link_training_setting->
 545                         lane_settings[lane].PRE_EMPHASIS;
 546
 547                 /*
 548                 if (link_training_setting->laneSettings[lane].postCursor2 >
 549                  max_requested.postCursor2)
 550                 {
 551                 max_requested.postCursor2 =
 552                 link_training_setting->laneSettings[lane].postCursor2;
 553                 }
 554                 */
 555         }
 556
 557         /* make sure the requested settings are
 558          * not higher than maximum settings*/
 559         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 560                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 561
 562         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 563                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 564         /*
 565         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 566         max_requested.postCursor2 = PostCursor2_MaxLevel;
 567         */
 568
 569         /* make sure the pre-emphasis matches the voltage swing*/
 570         if (max_requested.PRE_EMPHASIS >
 571                 get_max_pre_emphasis_for_voltage_swing(
 572                         max_requested.VOLTAGE_SWING))
 573                 max_requested.PRE_EMPHASIS =
 574                 get_max_pre_emphasis_for_voltage_swing(
 575                         max_requested.VOLTAGE_SWING);
 576
 577         /*
 578          * Post Cursor2 levels are completely independent from
 579          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 580          * can only be applied to each allowable combination of voltage
 581          * swing and pre-emphasis levels */
 582          /* if ( max_requested.postCursor2 >
 583           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 584           *  max_requested.postCursor2 =
 585           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 586           */
 587
 588         max_lt_setting->link_settings.link_rate =
 589                 link_training_setting->link_settings.link_rate;
 590         max_lt_setting->link_settings.lane_count =
 591         link_training_setting->link_settings.lane_count;
 592         max_lt_setting->link_settings.link_spread =
 593                 link_training_setting->link_settings.link_spread;
 594
 595         for (lane = 0; lane <
 596                 link_training_setting->link_settings.lane_count;
 597                 lane++) {
 598                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 599                         max_requested.VOLTAGE_SWING;
 600                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 601                         max_requested.PRE_EMPHASIS;
 602                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 603                  * max_requested.postCursor2;
 604                  */
 605         }
 606
 607 }
 608
 609 enum dc_status dp_get_lane_status_and_drive_settings(
 610         struct dc_link *link,
 611         const struct link_training_settings *link_training_setting,
 612         union lane_status *ln_status,
 613         union lane_align_status_updated *ln_status_updated,
 614         struct link_training_settings *req_settings,
 615         uint32_t offset)
 616 {
 617         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
 618         uint8_t lane_adjust_offset = 4;
 619         unsigned int lane01_adjust_address;
 620         uint8_t dpcd_buf[6] = {0};
 621         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 622         struct link_training_settings request_settings = { {0} };
 623         uint32_t lane;
 624         enum dc_status status;
 625
 626         memset(req_settings, '\0', sizeof(struct link_training_settings));
 627
 628         if (is_repeater(link, offset)) {
 629                 lane01_status_address =
 630                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
 631                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 632                 lane_adjust_offset = 3;
 633         }
 634
 635         status = core_link_read_dpcd(
 636                 link,
 637                 lane01_status_address,
 638                 (uint8_t *)(dpcd_buf),
 639                 sizeof(dpcd_buf));
 640
 641         for (lane = 0; lane <
 642                 (uint32_t)(link_training_setting->link_settings.lane_count);
 643                 lane++) {
 644
 645                 ln_status[lane].raw =
 646                         get_nibble_at_index(&dpcd_buf[0], lane);
 647                 dpcd_lane_adjust[lane].raw =
 648                         get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
 649         }
 650
 651         ln_status_updated->raw = dpcd_buf[2];
 652
 653         if (is_repeater(link, offset)) {
 654                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 655                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 656                         __func__,
 657                         offset,
 658                         lane01_status_address, dpcd_buf[0],
 659                         lane01_status_address + 1, dpcd_buf[1]);
 660         } else {
 661                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 662                         __func__,
 663                         lane01_status_address, dpcd_buf[0],
 664                         lane01_status_address + 1, dpcd_buf[1]);
 665         }
 666         lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
 667
 668         if (is_repeater(link, offset))
 669                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
 670                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 671
 672         if (is_repeater(link, offset)) {
 673                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 674                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 675                                         __func__,
 676                                         offset,
 677                                         lane01_adjust_address,
 678                                         dpcd_buf[lane_adjust_offset],
 679                                         lane01_adjust_address + 1,
 680                                         dpcd_buf[lane_adjust_offset + 1]);
 681         } else {
 682                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 683                         __func__,
 684                         lane01_adjust_address,
 685                         dpcd_buf[lane_adjust_offset],
 686                         lane01_adjust_address + 1,
 687                         dpcd_buf[lane_adjust_offset + 1]);
 688         }
 689
 690         /*copy to req_settings*/
 691         request_settings.link_settings.lane_count =
 692                 link_training_setting->link_settings.lane_count;
 693         request_settings.link_settings.link_rate =
 694                 link_training_setting->link_settings.link_rate;
 695         request_settings.link_settings.link_spread =
 696                 link_training_setting->link_settings.link_spread;
 697
 698         for (lane = 0; lane <
 699                 (uint32_t)(link_training_setting->link_settings.lane_count);
 700                 lane++) {
 701
 702                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 703                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 704                                 VOLTAGE_SWING_LANE);
 705                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 706                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 707                                 PRE_EMPHASIS_LANE);
 708         }
 709
 710         /*Note: for postcursor2, read adjusted
 711          * postcursor2 settings from*/
 712         /*DpcdAddress_AdjustRequestPostCursor2 =
 713          *0x020C (not implemented yet)*/
 714
 715         /* we find the maximum of the requested settings across all lanes*/
 716         /* and set this maximum for all lanes*/
 717         find_max_drive_settings(&request_settings, req_settings);
 718
 719         /* if post cursor 2 is needed in the future,
 720          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 721          */
 722
 723         return status;
 724 }
 725
 726 enum dc_status dpcd_set_lane_settings(
 727         struct dc_link *link,
 728         const struct link_training_settings *link_training_setting,
 729         uint32_t offset)
 730 {
 731         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 732         uint32_t lane;
 733         unsigned int lane0_set_address;
 734         enum dc_status status;
 735
 736         lane0_set_address = DP_TRAINING_LANE0_SET;
 737
 738         if (is_repeater(link, offset))
 739                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
 740                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 741
 742         for (lane = 0; lane <
 743                 (uint32_t)(link_training_setting->
 744                 link_settings.lane_count);
 745                 lane++) {
 746                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 747                         (uint8_t)(link_training_setting->
 748                         lane_settings[lane].VOLTAGE_SWING);
 749                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 750                         (uint8_t)(link_training_setting->
 751                         lane_settings[lane].PRE_EMPHASIS);
 752                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 753                         (link_training_setting->
 754                         lane_settings[lane].VOLTAGE_SWING ==
 755                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 756                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 757                         (link_training_setting->
 758                         lane_settings[lane].PRE_EMPHASIS ==
 759                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 760         }
 761
 762         status = core_link_write_dpcd(link,
 763                 lane0_set_address,
 764                 (uint8_t *)(dpcd_lane),
 765                 link_training_setting->link_settings.lane_count);
 766
 767         /*
 768         if (LTSettings.link.rate == LinkRate_High2)
 769         {
 770                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 771                 for ( uint32_t lane = 0;
 772                 lane < lane_count_DPMax; lane++)
 773                 {
 774                         dpcd_lane2[lane].bits.post_cursor2_set =
 775                         static_cast<unsigned char>(
 776                         LTSettings.laneSettings[lane].postCursor2);
 777                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 778                 }
 779                 m_pDpcdAccessSrv->WriteDpcdData(
 780                 DpcdAddress_Lane0Set2,
 781                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 782                 LTSettings.link.lanes);
 783         }
 784         */
 785
 786         if (is_repeater(link, offset)) {
 787                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
 788                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 789                         __func__,
 790                         offset,
 791                         lane0_set_address,
 792                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 793                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 794                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 795                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 796
 797         } else {
 798                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 799                         __func__,
 800                         lane0_set_address,
 801                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 802                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 803                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 804                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 805         }
 806         link->cur_lane_setting = link_training_setting->lane_settings[0];
 807
 808         return status;
 809 }
 810
 811 bool dp_is_max_vs_reached(
 812         const struct link_training_settings *lt_settings)
 813 {
 814         uint32_t lane;
 815         for (lane = 0; lane <
 816                 (uint32_t)(lt_settings->link_settings.lane_count);
 817                 lane++) {
 818                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 819                         == VOLTAGE_SWING_MAX_LEVEL)
 820                         return true;
 821         }
 822         return false;
 823
 824 }
 825
 826 static bool perform_post_lt_adj_req_sequence(
 827         struct dc_link *link,
 828         struct link_training_settings *lt_settings)
 829 {
 830         enum dc_lane_count lane_count =
 831         lt_settings->link_settings.lane_count;
 832
 833         uint32_t adj_req_count;
 834         uint32_t adj_req_timer;
 835         bool req_drv_setting_changed;
 836         uint32_t lane;
 837
 838         req_drv_setting_changed = false;
 839         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 840         adj_req_count++) {
 841
 842                 req_drv_setting_changed = false;
 843
 844                 for (adj_req_timer = 0;
 845                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 846                         adj_req_timer++) {
 847
 848                         struct link_training_settings req_settings;
 849                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 850                         union lane_align_status_updated
 851                                 dpcd_lane_status_updated;
 852
 853                         dp_get_lane_status_and_drive_settings(
 854                                 link,
 855                                 lt_settings,
 856                                 dpcd_lane_status,
 857                                 &dpcd_lane_status_updated,
 858                                 &req_settings,
 859                                 DPRX);
 860
 861                         if (dpcd_lane_status_updated.bits.
 862                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 863                                 return true;
 864
 865                         if (!dp_is_cr_done(lane_count, dpcd_lane_status))
 866                                 return false;
 867
 868                         if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
 869                                         !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
 870                                         !dp_is_interlane_aligned(dpcd_lane_status_updated))
 871                                 return false;
 872
 873                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 874
 875                                 if (lt_settings->
 876                                 lane_settings[lane].VOLTAGE_SWING !=
 877                                 req_settings.lane_settings[lane].
 878                                 VOLTAGE_SWING ||
 879                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 880                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 881
 882                                         req_drv_setting_changed = true;
 883                                         break;
 884                                 }
 885                         }
 886
 887                         if (req_drv_setting_changed) {
 888                                 dp_update_drive_settings(
 889                                         lt_settings, req_settings);
 890
 891                                 dc_link_dp_set_drive_settings(link,
 892                                                 lt_settings);
 893                                 break;
 894                         }
 895
 896                         msleep(1);
 897                 }
 898
 899                 if (!req_drv_setting_changed) {
 900                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 901                                 __func__);
 902
 903                         ASSERT(0);
 904                         return true;
 905                 }
 906         }
 907         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 908                 __func__);
 909
 910         ASSERT(0);
 911         return true;
 912
 913 }
 914
 915 /* Only used for channel equalization */
 916 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 917 {
 918         unsigned int aux_rd_interval_us = 400;
 919
 920         switch (dpcd_aux_read_interval) {
 921         case 0x01:
 922                 aux_rd_interval_us = 4000;
 923                 break;
 924         case 0x02:
 925                 aux_rd_interval_us = 8000;
 926                 break;
 927         case 0x03:
 928                 aux_rd_interval_us = 12000;
 929                 break;
 930         case 0x04:
 931                 aux_rd_interval_us = 16000;
 932                 break;
 933         default:
 934                 break;
 935         }
 936
 937         return aux_rd_interval_us;
 938 }
 939
 940 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
 941                                         union lane_status *dpcd_lane_status)
 942 {
 943         enum link_training_result result = LINK_TRAINING_SUCCESS;
 944
 945         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 946                 result = LINK_TRAINING_CR_FAIL_LANE0;
 947         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 948                 result = LINK_TRAINING_CR_FAIL_LANE1;
 949         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 950                 result = LINK_TRAINING_CR_FAIL_LANE23;
 951         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 952                 result = LINK_TRAINING_CR_FAIL_LANE23;
 953         return result;
 954 }
 955
 956 static enum link_training_result perform_channel_equalization_sequence(
 957         struct dc_link *link,
 958         struct link_training_settings *lt_settings,
 959         uint32_t offset)
 960 {
 961         struct link_training_settings req_settings;
 962         enum dc_dp_training_pattern tr_pattern;
 963         uint32_t retries_ch_eq;
 964         uint32_t wait_time_microsec;
 965         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 966         union lane_align_status_updated dpcd_lane_status_updated = { {0} };
 967         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 968
 969         /* Note: also check that TPS4 is a supported feature*/
 970
 971         tr_pattern = lt_settings->pattern_for_eq;
 972
 973         if (is_repeater(link, offset))
 974                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 975
 976         dp_set_hw_training_pattern(link, tr_pattern, offset);
 977
 978         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 979                 retries_ch_eq++) {
 980
 981                 dp_set_hw_lane_settings(link, lt_settings, offset);
 982
 983                 /* 2. update DPCD*/
 984                 if (!retries_ch_eq)
 985                         /* EPR #361076 - write as a 5-byte burst,
 986                          * but only for the 1-st iteration
 987                          */
 988
 989                         dpcd_set_lt_pattern_and_lane_settings(
 990                                 link,
 991                                 lt_settings,
 992                                 tr_pattern, offset);
 993                 else
 994                         dpcd_set_lane_settings(link, lt_settings, offset);
 995
 996                 /* 3. wait for receiver to lock-on*/
 997                 wait_time_microsec = lt_settings->eq_pattern_time;
 998
 999                 if (is_repeater(link, offset))
1000                         wait_time_microsec =
1001                                         dp_translate_training_aux_read_interval(
1002                                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
1003
1004                 dp_wait_for_training_aux_rd_interval(
1005                                 link,
1006                                 wait_time_microsec);
1007
1008                 /* 4. Read lane status and requested
1009                  * drive settings as set by the sink*/
1010
1011                 dp_get_lane_status_and_drive_settings(
1012                         link,
1013                         lt_settings,
1014                         dpcd_lane_status,
1015                         &dpcd_lane_status_updated,
1016                         &req_settings,
1017                         offset);
1018
1019                 /* 5. check CR done*/
1020                 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
1021                         return LINK_TRAINING_EQ_FAIL_CR;
1022
1023                 /* 6. check CHEQ done*/
1024                 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
1025                                 dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
1026                                 dp_is_interlane_aligned(dpcd_lane_status_updated))
1027                         return LINK_TRAINING_SUCCESS;
1028
1029                 /* 7. update VS/PE/PC2 in lt_settings*/
1030                 dp_update_drive_settings(lt_settings, req_settings);
1031         }
1032
1033         return LINK_TRAINING_EQ_FAIL_EQ;
1034
1035 }
1036
1037 static void start_clock_recovery_pattern_early(struct dc_link *link,
1038                 struct link_training_settings *lt_settings,
1039                 uint32_t offset)
1040 {
1041         DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1042                         __func__);
1043         dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1044         dp_set_hw_lane_settings(link, lt_settings, offset);
1045         udelay(400);
1046 }
1047
1048 static enum link_training_result perform_clock_recovery_sequence(
1049         struct dc_link *link,
1050         struct link_training_settings *lt_settings,
1051         uint32_t offset)
1052 {
1053         uint32_t retries_cr;
1054         uint32_t retry_count;
1055         uint32_t wait_time_microsec;
1056         struct link_training_settings req_settings;
1057         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1058         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1059         union lane_align_status_updated dpcd_lane_status_updated;
1060
1061         retries_cr = 0;
1062         retry_count = 0;
1063
1064         if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1065                 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1066
1067         /* najeeb - The synaptics MST hub can put the LT in
1068         * infinite loop by switching the VS
1069         */
1070         /* between level 0 and level 1 continuously, here
1071         * we try for CR lock for LinkTrainingMaxCRRetry count*/
1072         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1073                 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1074
1075                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1076                 memset(&dpcd_lane_status_updated, '\0',
1077                 sizeof(dpcd_lane_status_updated));
1078
1079                 /* 1. call HWSS to set lane settings*/
1080                 dp_set_hw_lane_settings(
1081                                 link,
1082                                 lt_settings,
1083                                 offset);
1084
1085                 /* 2. update DPCD of the receiver*/
1086                 if (!retry_count)
1087                         /* EPR #361076 - write as a 5-byte burst,
1088                          * but only for the 1-st iteration.*/
1089                         dpcd_set_lt_pattern_and_lane_settings(
1090                                         link,
1091                                         lt_settings,
1092                                         lt_settings->pattern_for_cr,
1093                                         offset);
1094                 else
1095                         dpcd_set_lane_settings(
1096                                         link,
1097                                         lt_settings,
1098                                         offset);
1099
1100                 /* 3. wait receiver to lock-on*/
1101                 wait_time_microsec = lt_settings->cr_pattern_time;
1102
1103                 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1104                         wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1105
1106                 dp_wait_for_training_aux_rd_interval(
1107                                 link,
1108                                 wait_time_microsec);
1109
1110                 /* 4. Read lane status and requested drive
1111                 * settings as set by the sink
1112                 */
1113                 dp_get_lane_status_and_drive_settings(
1114                                 link,
1115                                 lt_settings,
1116                                 dpcd_lane_status,
1117                                 &dpcd_lane_status_updated,
1118                                 &req_settings,
1119                                 offset);
1120
1121                 /* 5. check CR done*/
1122                 if (dp_is_cr_done(lane_count, dpcd_lane_status))
1123                         return LINK_TRAINING_SUCCESS;
1124
1125                 /* 6. max VS reached*/
1126                 if (dp_is_max_vs_reached(lt_settings))
1127                         break;
1128
1129                 /* 7. same lane settings*/
1130                 /* Note: settings are the same for all lanes,
1131                  * so comparing first lane is sufficient*/
1132                 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
1133                         req_settings.lane_settings[0].VOLTAGE_SWING)
1134                         && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1135                                 req_settings.lane_settings[0].PRE_EMPHASIS))
1136                         retries_cr++;
1137                 else
1138                         retries_cr = 0;
1139
1140                 /* 8. update VS/PE/PC2 in lt_settings*/
1141                 dp_update_drive_settings(lt_settings, req_settings);
1142
1143                 retry_count++;
1144         }
1145
1146         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1147                 ASSERT(0);
1148                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1149                         __func__,
1150                         LINK_TRAINING_MAX_CR_RETRY);
1151
1152         }
1153
1154         return dp_get_cr_failure(lane_count, dpcd_lane_status);
1155 }
1156
1157 static inline enum link_training_result dp_transition_to_video_idle(
1158         struct dc_link *link,
1159         struct link_training_settings *lt_settings,
1160         enum link_training_result status)
1161 {
1162         union lane_count_set lane_count_set = { {0} };
1163
1164         /* 4. mainlink output idle pattern*/
1165         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1166
1167         /*
1168          * 5. post training adjust if required
1169          * If the upstream DPTX and downstream DPRX both support TPS4,
1170          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1171          */
1172         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1173                         lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) {
1174                 /* delay 5ms after Main Link output idle pattern and then check
1175                  * DPCD 0202h.
1176                  */
1177                 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1178                         msleep(5);
1179                         status = dp_check_link_loss_status(link, lt_settings);
1180                 }
1181                 return status;
1182         }
1183
1184         if (status == LINK_TRAINING_SUCCESS &&
1185                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1186                 status = LINK_TRAINING_LQA_FAIL;
1187
1188         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1189         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1190         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1191
1192         core_link_write_dpcd(
1193                 link,
1194                 DP_LANE_COUNT_SET,
1195                 &lane_count_set.raw,
1196                 sizeof(lane_count_set));
1197
1198         return status;
1199 }
1200
1201 enum link_training_result dp_check_link_loss_status(
1202         struct dc_link *link,
1203         const struct link_training_settings *link_training_setting)
1204 {
1205         enum link_training_result status = LINK_TRAINING_SUCCESS;
1206         union lane_status lane_status;
1207         uint8_t dpcd_buf[6] = {0};
1208         uint32_t lane;
1209
1210         core_link_read_dpcd(
1211                         link,
1212                         DP_SINK_COUNT,
1213                         (uint8_t *)(dpcd_buf),
1214                         sizeof(dpcd_buf));
1215
1216         /*parse lane status*/
1217         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1218                 /*
1219                  * check lanes status
1220                  */
1221                 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1222
1223                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1224                         !lane_status.bits.CR_DONE_0 ||
1225                         !lane_status.bits.SYMBOL_LOCKED_0) {
1226                         /* if one of the channel equalization, clock
1227                          * recovery or symbol lock is dropped
1228                          * consider it as (link has been
1229                          * dropped) dp sink status has changed
1230                          */
1231                         status = LINK_TRAINING_LINK_LOSS;
1232                         break;
1233                 }
1234         }
1235
1236         return status;
1237 }
1238
1239 static inline void decide_8b_10b_training_settings(
1240          struct dc_link *link,
1241         const struct dc_link_settings *link_setting,
1242         const struct dc_link_training_overrides *overrides,
1243         struct link_training_settings *lt_settings)
1244 {
1245         uint32_t lane;
1246
1247         memset(lt_settings, '\0', sizeof(struct link_training_settings));
1248
1249         /* Initialize link settings */
1250         lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1251         lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1252
1253         if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1254                 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1255         else
1256                 lt_settings->link_settings.link_rate = link_setting->link_rate;
1257
1258         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1259                 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1260         else
1261                 lt_settings->link_settings.lane_count = link_setting->lane_count;
1262
1263         /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1264
1265         /* TODO hard coded to SS for now
1266          * lt_settings.link_settings.link_spread =
1267          * dal_display_path_is_ss_supported(
1268          * path_mode->display_path) ?
1269          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1270          * LINK_SPREAD_DISABLED;
1271          */
1272         /* Initialize link spread */
1273         if (link->dp_ss_off)
1274                 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1275         else if (overrides->downspread != NULL)
1276                 lt_settings->link_settings.link_spread
1277                         = *overrides->downspread
1278                         ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1279                         : LINK_SPREAD_DISABLED;
1280         else
1281                 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1282
1283         lt_settings->lttpr_mode = link->lttpr_mode;
1284
1285         /* Initialize lane settings overrides */
1286         if (overrides->voltage_swing != NULL)
1287                 lt_settings->voltage_swing = overrides->voltage_swing;
1288
1289         if (overrides->pre_emphasis != NULL)
1290                 lt_settings->pre_emphasis = overrides->pre_emphasis;
1291
1292         if (overrides->post_cursor2 != NULL)
1293                 lt_settings->post_cursor2 = overrides->post_cursor2;
1294
1295         /* Initialize lane settings (VS/PE/PC2) */
1296         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1297                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1298                         lt_settings->voltage_swing != NULL ?
1299                         *lt_settings->voltage_swing :
1300                         VOLTAGE_SWING_LEVEL0;
1301                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1302                         lt_settings->pre_emphasis != NULL ?
1303                         *lt_settings->pre_emphasis
1304                         : PRE_EMPHASIS_DISABLED;
1305                 lt_settings->lane_settings[lane].POST_CURSOR2 =
1306                         lt_settings->post_cursor2 != NULL ?
1307                         *lt_settings->post_cursor2
1308                         : POST_CURSOR2_DISABLED;
1309         }
1310
1311         /* Initialize training timings */
1312         if (overrides->cr_pattern_time != NULL)
1313                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1314         else
1315                 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1316
1317         if (overrides->eq_pattern_time != NULL)
1318                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1319         else
1320                 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1321
1322         if (overrides->pattern_for_cr != NULL)
1323                 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1324         else
1325                 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1326         if (overrides->pattern_for_eq != NULL)
1327                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1328         else
1329                 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1330
1331         if (overrides->enhanced_framing != NULL)
1332                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1333         else
1334                 lt_settings->enhanced_framing = 1;
1335
1336         if (link->preferred_training_settings.fec_enable != NULL)
1337                 lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
1338         else
1339                 lt_settings->should_set_fec_ready = true;
1340 }
1341
1342 void dp_decide_training_settings(
1343                 struct dc_link *link,
1344                 const struct dc_link_settings *link_settings,
1345                 const struct dc_link_training_overrides *overrides,
1346                 struct link_training_settings *lt_settings)
1347 {
1348         if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
1349                 decide_8b_10b_training_settings(link, link_settings, overrides, lt_settings);
1350 }
1351
1352
1353 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
1354 {
1355         switch (lttpr_repeater_count) {
1356         case 0x80: // 1 lttpr repeater
1357                 return 1;
1358         case 0x40: // 2 lttpr repeaters
1359                 return 2;
1360         case 0x20: // 3 lttpr repeaters
1361                 return 3;
1362         case 0x10: // 4 lttpr repeaters
1363                 return 4;
1364         case 0x08: // 5 lttpr repeaters
1365                 return 5;
1366         case 0x04: // 6 lttpr repeaters
1367                 return 6;
1368         case 0x02: // 7 lttpr repeaters
1369                 return 7;
1370         case 0x01: // 8 lttpr repeaters
1371                 return 8;
1372         default:
1373                 break;
1374         }
1375         return 0; // invalid value
1376 }
1377
1378 enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
1379 {
1380         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1381
1382         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1383         return core_link_write_dpcd(link,
1384                         DP_PHY_REPEATER_MODE,
1385                         (uint8_t *)&repeater_mode,
1386                         sizeof(repeater_mode));
1387 }
1388
1389 enum dc_status configure_lttpr_mode_non_transparent(
1390                 struct dc_link *link,
1391                 const struct link_training_settings *lt_settings)
1392 {
1393         /* aux timeout is already set to extended */
1394         /* RESET/SET lttpr mode to enable non transparent mode */
1395         uint8_t repeater_cnt;
1396         uint32_t aux_interval_address;
1397         uint8_t repeater_id;
1398         enum dc_status result = DC_ERROR_UNEXPECTED;
1399         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1400
1401         enum dp_link_encoding encoding = dp_get_link_encoding_format(&lt_settings->link_settings);
1402
1403         if (encoding == DP_8b_10b_ENCODING) {
1404                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1405                 result = core_link_write_dpcd(link,
1406                                 DP_PHY_REPEATER_MODE,
1407                                 (uint8_t *)&repeater_mode,
1408                                 sizeof(repeater_mode));
1409
1410         }
1411
1412         if (result == DC_OK) {
1413                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1414         }
1415
1416         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1417
1418                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1419
1420                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1421                 result = core_link_write_dpcd(link,
1422                                 DP_PHY_REPEATER_MODE,
1423                                 (uint8_t *)&repeater_mode,
1424                                 sizeof(repeater_mode));
1425
1426                 if (result == DC_OK) {
1427                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1428                 }
1429
1430                 if (encoding == DP_8b_10b_ENCODING) {
1431                         repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1432                         for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1433                                 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1434                                                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1435                                 core_link_read_dpcd(
1436                                         link,
1437                                         aux_interval_address,
1438                                         (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1439                                         sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1440                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1441                         }
1442                 }
1443         }
1444
1445         return result;
1446 }
1447
1448 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1449 {
1450         union dpcd_training_pattern dpcd_pattern = { {0} };
1451
1452         const uint32_t dpcd_base_lt_offset =
1453                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1454                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1455         /* Set training not in progress*/
1456         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1457
1458         core_link_write_dpcd(
1459                 link,
1460                 dpcd_base_lt_offset,
1461                 &dpcd_pattern.raw,
1462                 1);
1463
1464         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1465                 __func__,
1466                 offset,
1467                 dpcd_base_lt_offset,
1468                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1469 }
1470
1471 static void print_status_message(
1472         struct dc_link *link,
1473         const struct link_training_settings *lt_settings,
1474         enum link_training_result status)
1475 {
1476         char *link_rate = "Unknown";
1477         char *lt_result = "Unknown";
1478         char *lt_spread = "Disabled";
1479
1480         switch (lt_settings->link_settings.link_rate) {
1481         case LINK_RATE_LOW:
1482                 link_rate = "RBR";
1483                 break;
1484         case LINK_RATE_RATE_2:
1485                 link_rate = "R2";
1486                 break;
1487         case LINK_RATE_RATE_3:
1488                 link_rate = "R3";
1489                 break;
1490         case LINK_RATE_HIGH:
1491                 link_rate = "HBR";
1492                 break;
1493         case LINK_RATE_RBR2:
1494                 link_rate = "RBR2";
1495                 break;
1496         case LINK_RATE_RATE_6:
1497                 link_rate = "R6";
1498                 break;
1499         case LINK_RATE_HIGH2:
1500                 link_rate = "HBR2";
1501                 break;
1502         case LINK_RATE_HIGH3:
1503                 link_rate = "HBR3";
1504                 break;
1505         default:
1506                 break;
1507         }
1508
1509         switch (status) {
1510         case LINK_TRAINING_SUCCESS:
1511                 lt_result = "pass";
1512                 break;
1513         case LINK_TRAINING_CR_FAIL_LANE0:
1514                 lt_result = "CR failed lane0";
1515                 break;
1516         case LINK_TRAINING_CR_FAIL_LANE1:
1517                 lt_result = "CR failed lane1";
1518                 break;
1519         case LINK_TRAINING_CR_FAIL_LANE23:
1520                 lt_result = "CR failed lane23";
1521                 break;
1522         case LINK_TRAINING_EQ_FAIL_CR:
1523                 lt_result = "CR failed in EQ";
1524                 break;
1525         case LINK_TRAINING_EQ_FAIL_EQ:
1526                 lt_result = "EQ failed";
1527                 break;
1528         case LINK_TRAINING_LQA_FAIL:
1529                 lt_result = "LQA failed";
1530                 break;
1531         case LINK_TRAINING_LINK_LOSS:
1532                 lt_result = "Link loss";
1533                 break;
1534         default:
1535                 break;
1536         }
1537
1538         switch (lt_settings->link_settings.link_spread) {
1539         case LINK_SPREAD_DISABLED:
1540                 lt_spread = "Disabled";
1541                 break;
1542         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1543                 lt_spread = "0.5% 30KHz";
1544                 break;
1545         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1546                 lt_spread = "0.5% 33KHz";
1547                 break;
1548         default:
1549                 break;
1550         }
1551
1552         /* Connectivity log: link training */
1553         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1554                                 link_rate,
1555                                 lt_settings->link_settings.lane_count,
1556                                 lt_result,
1557                                 lt_settings->lane_settings[0].VOLTAGE_SWING,
1558                                 lt_settings->lane_settings[0].PRE_EMPHASIS,
1559                                 lt_spread);
1560 }
1561
1562 void dc_link_dp_set_drive_settings(
1563         struct dc_link *link,
1564         struct link_training_settings *lt_settings)
1565 {
1566         /* program ASIC PHY settings*/
1567         dp_set_hw_lane_settings(link, lt_settings, DPRX);
1568
1569         /* Notify DP sink the PHY settings from source */
1570         dpcd_set_lane_settings(link, lt_settings, DPRX);
1571 }
1572
1573 bool dc_link_dp_perform_link_training_skip_aux(
1574         struct dc_link *link,
1575         const struct dc_link_settings *link_setting)
1576 {
1577         struct link_training_settings lt_settings;
1578
1579         dp_decide_training_settings(
1580                         link,
1581                         link_setting,
1582                         &link->preferred_training_settings,
1583                         &lt_settings);
1584
1585         /* 1. Perform_clock_recovery_sequence. */
1586
1587         /* transmit training pattern for clock recovery */
1588         dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1589
1590         /* call HWSS to set lane settings*/
1591         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1592
1593         /* wait receiver to lock-on*/
1594         dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1595
1596         /* 2. Perform_channel_equalization_sequence. */
1597
1598         /* transmit training pattern for channel equalization. */
1599         dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1600
1601         /* call HWSS to set lane settings*/
1602         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1603
1604         /* wait receiver to lock-on. */
1605         dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1606
1607         /* 3. Perform_link_training_int. */
1608
1609         /* Mainlink output idle pattern. */
1610         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1611
1612         print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1613
1614         return true;
1615 }
1616
1617 enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
1618 {
1619         enum dc_status status = DC_OK;
1620
1621         if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1622                 status = configure_lttpr_mode_non_transparent(link, lt_settings);
1623         else
1624                 status = configure_lttpr_mode_transparent(link);
1625
1626         return status;
1627 }
1628
1629 static void dpcd_exit_training_mode(struct dc_link *link)
1630 {
1631
1632         /* clear training pattern set */
1633         dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
1634 }
1635
1636 enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
1637                 struct link_training_settings *lt_settings)
1638 {
1639         enum dp_link_encoding encoding =
1640                         dp_get_link_encoding_format(
1641                                         &lt_settings->link_settings);
1642         enum dc_status status;
1643
1644         status = core_link_write_dpcd(
1645                         link,
1646                         DP_MAIN_LINK_CHANNEL_CODING_SET,
1647                         (uint8_t *) &encoding,
1648                         1);
1649         DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
1650                                         __func__,
1651                                         DP_MAIN_LINK_CHANNEL_CODING_SET,
1652                                         encoding);
1653
1654         return status;
1655 }
1656
1657 static enum link_training_result dp_perform_8b_10b_link_training(
1658                 struct dc_link *link,
1659                 struct link_training_settings *lt_settings)
1660 {
1661         enum link_training_result status = LINK_TRAINING_SUCCESS;
1662
1663         uint8_t repeater_cnt;
1664         uint8_t repeater_id;
1665
1666         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1667                 start_clock_recovery_pattern_early(link, lt_settings, DPRX);
1668
1669         /* 1. set link rate, lane count and spread. */
1670         dpcd_set_link_settings(link, lt_settings);
1671
1672         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1673
1674                 /* 2. perform link training (set link training done
1675                  *  to false is done as well)
1676                  */
1677                 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1678
1679                 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1680                                 repeater_id--) {
1681                         status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);
1682
1683                         if (status != LINK_TRAINING_SUCCESS)
1684                                 break;
1685
1686                         status = perform_channel_equalization_sequence(link,
1687                                         lt_settings,
1688                                         repeater_id);
1689
1690                         if (status != LINK_TRAINING_SUCCESS)
1691                                 break;
1692
1693                         repeater_training_done(link, repeater_id);
1694                 }
1695         }
1696
1697         if (status == LINK_TRAINING_SUCCESS) {
1698                 status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
1699         if (status == LINK_TRAINING_SUCCESS) {
1700                 status = perform_channel_equalization_sequence(link,
1701                                         lt_settings,
1702                                         DPRX);
1703                 }
1704         }
1705
1706         return status;
1707 }
1708
1709 enum link_training_result dc_link_dp_perform_link_training(
1710         struct dc_link *link,
1711         const struct dc_link_settings *link_settings,
1712         bool skip_video_pattern)
1713 {
1714         enum link_training_result status = LINK_TRAINING_SUCCESS;
1715         struct link_training_settings lt_settings;
1716         enum dp_link_encoding encoding =
1717                         dp_get_link_encoding_format(link_settings);
1718
1719         /* decide training settings */
1720         dp_decide_training_settings(
1721                         link,
1722                         link_settings,
1723                         &link->preferred_training_settings,
1724                         &lt_settings);
1725
1726         /* reset previous training states */
1727         dpcd_exit_training_mode(link);
1728
1729         /* configure link prior to entering training mode */
1730         dpcd_configure_lttpr_mode(link, &lt_settings);
1731         dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
1732         dpcd_configure_channel_coding(link, &lt_settings);
1733
1734         /* enter training mode:
1735          * Per DP specs starting from here, DPTX device shall not issue
1736          * Non-LT AUX transactions inside training mode.
1737          */
1738         if (encoding == DP_8b_10b_ENCODING)
1739                 status = dp_perform_8b_10b_link_training(link, &lt_settings);
1740         else
1741                 ASSERT(0);
1742
1743         /* exit training mode and switch to video idle */
1744         dpcd_exit_training_mode(link);
1745         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
1746                 status = dp_transition_to_video_idle(link,
1747                                 &lt_settings,
1748                                 status);
1749
1750         /* dump debug data */
1751         print_status_message(link, &lt_settings, status);
1752         if (status != LINK_TRAINING_SUCCESS)
1753                 link->ctx->dc->debug_data.ltFailCount++;
1754         return status;
1755 }
1756
1757 static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
1758 {
1759         struct dc_link *link = stream->link;
1760         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1761 #ifdef CONFIG_DRM_AMD_DC_HDCP
1762         struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1763 #endif
1764
1765         /* ASSR must be supported on the panel */
1766         if (panel_mode == DP_PANEL_MODE_DEFAULT)
1767                 return panel_mode;
1768
1769         /* eDP or internal DP only */
1770         if (link->connector_signal != SIGNAL_TYPE_EDP &&
1771                 !(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1772                  link->is_internal_display))
1773                 return DP_PANEL_MODE_DEFAULT;
1774
1775 #ifdef CONFIG_DRM_AMD_DC_HDCP
1776         if (cp_psp && cp_psp->funcs.enable_assr) {
1777                 if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
1778                         /* since eDP implies ASSR on, change panel
1779                          * mode to disable ASSR
1780                          */
1781                         panel_mode = DP_PANEL_MODE_DEFAULT;
1782                 }
1783         } else
1784                 panel_mode = DP_PANEL_MODE_DEFAULT;
1785
1786 #else
1787         /* turn off ASSR if the implementation is not compiled in */
1788         panel_mode = DP_PANEL_MODE_DEFAULT;
1789 #endif
1790         return panel_mode;
1791 }
1792
1793 bool perform_link_training_with_retries(
1794         const struct dc_link_settings *link_setting,
1795         bool skip_video_pattern,
1796         int attempts,
1797         struct pipe_ctx *pipe_ctx,
1798         enum signal_type signal,
1799         bool do_fallback)
1800 {
1801         uint8_t j;
1802         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1803         struct dc_stream_state *stream = pipe_ctx->stream;
1804         struct dc_link *link = stream->link;
1805         enum dp_panel_mode panel_mode;
1806         struct link_encoder *link_enc;
1807         enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1808         struct dc_link_settings current_setting = *link_setting;
1809
1810         /* Dynamically assigned link encoders associated with stream rather than
1811          * link.
1812          */
1813         if (link->dc->res_pool->funcs->link_encs_assign)
1814                 link_enc = stream->link_enc;
1815         else
1816                 link_enc = link->link_enc;
1817         ASSERT(link_enc);
1818
1819         /* We need to do this before the link training to ensure the idle pattern in SST
1820          * mode will be sent right after the link training
1821          */
1822         link_enc->funcs->connect_dig_be_to_fe(link_enc,
1823                                                         pipe_ctx->stream_res.stream_enc->id, true);
1824
1825         for (j = 0; j < attempts; ++j) {
1826
1827                 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1828                         __func__, (unsigned int)j + 1, attempts);
1829
1830                 dp_enable_link_phy(
1831                         link,
1832                         signal,
1833                         pipe_ctx->clock_source->id,
1834                         &current_setting);
1835
1836                 if (stream->sink_patches.dppowerup_delay > 0) {
1837                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1838
1839                         msleep(delay_dp_power_up_in_ms);
1840                 }
1841
1842                 panel_mode = try_enable_assr(stream);
1843                 dp_set_panel_mode(link, panel_mode);
1844                 DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
1845                          link->link_index,
1846                          panel_mode != DP_PANEL_MODE_DEFAULT);
1847
1848                 if (link->aux_access_disabled) {
1849                         dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
1850                         return true;
1851                 } else {
1852                                 status = dc_link_dp_perform_link_training(
1853                                                                                 link,
1854                                                                                 &current_setting,
1855                                                                                 skip_video_pattern);
1856                         if (status == LINK_TRAINING_SUCCESS)
1857                                 return true;
1858                 }
1859
1860                 /* latest link training still fail, skip delay and keep PHY on
1861                  */
1862                 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
1863                         break;
1864
1865                 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1866                         __func__, (unsigned int)j + 1, attempts);
1867
1868                 dp_disable_link_phy(link, signal);
1869
1870                 /* Abort link training if failure due to sink being unplugged. */
1871                 if (status == LINK_TRAINING_ABORT)
1872                         break;
1873                 else if (do_fallback) {
1874                         decide_fallback_link_setting(*link_setting, &current_setting, status);
1875                         /* Fail link training if reduced link bandwidth no longer meets
1876                          * stream requirements.
1877                          */
1878                         if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
1879                                         dc_link_bandwidth_kbps(link, &current_setting))
1880                                 break;
1881                 }
1882
1883                 msleep(delay_between_attempts);
1884
1885                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1886         }
1887
1888         return false;
1889 }
1890
1891 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1892 {
1893         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1894         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1895
1896         if (dp_cs != NULL) {
1897                 dp_cs_id = dp_cs->id;
1898         } else {
1899                 /*
1900                  * dp clock source is not initialized for some reason.
1901                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1902                  */
1903                 ASSERT(dp_cs);
1904         }
1905
1906         return dp_cs_id;
1907 }
1908
1909 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1910 {
1911         if (mst_enable == false &&
1912                 link->type == dc_connection_mst_branch) {
1913                 /* Disable MST on link. Use only local sink. */
1914                 dp_disable_link_phy_mst(link, link->connector_signal);
1915
1916                 link->type = dc_connection_single;
1917                 link->local_sink = link->remote_sinks[0];
1918                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1919                 dc_sink_retain(link->local_sink);
1920                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1921         } else if (mst_enable == true &&
1922                         link->type == dc_connection_single &&
1923                         link->remote_sinks[0] != NULL) {
1924                 /* Re-enable MST on link. */
1925                 dp_disable_link_phy(link, link->connector_signal);
1926                 dp_enable_mst_on_sink(link, true);
1927
1928                 link->type = dc_connection_mst_branch;
1929                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1930         }
1931 }
1932
1933 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1934 {
1935         /* Begin Sync LT. During this time,
1936          * DPCD:600h must not be powered down.
1937          */
1938         link->sync_lt_in_progress = true;
1939
1940         /*Clear any existing preferred settings.*/
1941         memset(&link->preferred_training_settings, 0,
1942                 sizeof(struct dc_link_training_overrides));
1943         memset(&link->preferred_link_setting, 0,
1944                 sizeof(struct dc_link_settings));
1945
1946         return true;
1947 }
1948
1949 enum link_training_result dc_link_dp_sync_lt_attempt(
1950     struct dc_link *link,
1951     struct dc_link_settings *link_settings,
1952     struct dc_link_training_overrides *lt_overrides)
1953 {
1954         struct link_training_settings lt_settings;
1955         enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1956         enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1957         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1958         bool fec_enable = false;
1959
1960         dp_decide_training_settings(
1961                 link,
1962                 link_settings,
1963                 lt_overrides,
1964                 &lt_settings);
1965
1966         /* Setup MST Mode */
1967         if (lt_overrides->mst_enable)
1968                 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1969
1970         /* Disable link */
1971         dp_disable_link_phy(link, link->connector_signal);
1972
1973         /* Enable link */
1974         dp_cs_id = get_clock_source_id(link);
1975         dp_enable_link_phy(link, link->connector_signal,
1976                 dp_cs_id, link_settings);
1977
1978         /* Set FEC enable */
1979         fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1980         dp_set_fec_ready(link, fec_enable);
1981
1982         if (lt_overrides->alternate_scrambler_reset) {
1983                 if (*lt_overrides->alternate_scrambler_reset)
1984                         panel_mode = DP_PANEL_MODE_EDP;
1985                 else
1986                         panel_mode = DP_PANEL_MODE_DEFAULT;
1987         } else
1988                 panel_mode = dp_get_panel_mode(link);
1989
1990         dp_set_panel_mode(link, panel_mode);
1991
1992         /* Attempt to train with given link training settings */
1993         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1994                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1995
1996         /* Set link rate, lane count and spread. */
1997         dpcd_set_link_settings(link, &lt_settings);
1998
1999         /* 2. perform link training (set link training done
2000          *  to false is done as well)
2001          */
2002         lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
2003         if (lt_status == LINK_TRAINING_SUCCESS) {
2004                 lt_status = perform_channel_equalization_sequence(link,
2005                                                 &lt_settings,
2006                                                 DPRX);
2007         }
2008
2009         /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
2010         /* 4. print status message*/
2011         print_status_message(link, &lt_settings, lt_status);
2012
2013         return lt_status;
2014 }
2015
2016 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
2017 {
2018         /* If input parameter is set, shut down phy.
2019          * Still shouldn't turn off dp_receiver (DPCD:600h)
2020          */
2021         if (link_down == true) {
2022                 dp_disable_link_phy(link, link->connector_signal);
2023                 dp_set_fec_ready(link, false);
2024         }
2025
2026         link->sync_lt_in_progress = false;
2027         return true;
2028 }
2029
2030 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2031 {
2032         if (!max_link_enc_cap) {
2033                 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2034                 return false;
2035         }
2036
2037         if (link->link_enc->funcs->get_max_link_cap) {
2038                 link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap);
2039                 return true;
2040         }
2041
2042         DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2043         max_link_enc_cap->lane_count = 1;
2044         max_link_enc_cap->link_rate = 6;
2045         return false;
2046 }
2047
2048 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
2049 {
2050         struct dc_link_settings max_link_cap = {0};
2051
2052         /* get max link encoder capability */
2053         link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
2054
2055         /* Lower link settings based on sink's link cap */
2056         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2057                 max_link_cap.lane_count =
2058                                 link->reported_link_cap.lane_count;
2059         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2060                 max_link_cap.link_rate =
2061                                 link->reported_link_cap.link_rate;
2062         if (link->reported_link_cap.link_spread <
2063                         max_link_cap.link_spread)
2064                 max_link_cap.link_spread =
2065                                 link->reported_link_cap.link_spread;
2066         /*
2067          * account for lttpr repeaters cap
2068          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2069          */
2070         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
2071                 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2072                         max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2073
2074                 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
2075                         max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
2076
2077                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
2078                                                 __func__,
2079                                                 max_link_cap.lane_count,
2080                                                 max_link_cap.link_rate);
2081         }
2082         return max_link_cap;
2083 }
2084
2085 enum dc_status read_hpd_rx_irq_data(
2086         struct dc_link *link,
2087         union hpd_irq_data *irq_data)
2088 {
2089         static enum dc_status retval;
2090
2091         /* The HW reads 16 bytes from 200h on HPD,
2092          * but if we get an AUX_DEFER, the HW cannot retry
2093          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
2094          * fail, so we now explicitly read 6 bytes which is
2095          * the req from the above mentioned test cases.
2096          *
2097          * For DP 1.4 we need to read those from 2002h range.
2098          */
2099         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
2100                 retval = core_link_read_dpcd(
2101                         link,
2102                         DP_SINK_COUNT,
2103                         irq_data->raw,
2104                         sizeof(union hpd_irq_data));
2105         else {
2106                 /* Read 14 bytes in a single read and then copy only the required fields.
2107                  * This is more efficient than doing it in two separate AUX reads. */
2108
2109                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
2110
2111                 retval = core_link_read_dpcd(
2112                         link,
2113                         DP_SINK_COUNT_ESI,
2114                         tmp,
2115                         sizeof(tmp));
2116
2117                 if (retval != DC_OK)
2118                         return retval;
2119
2120                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
2121                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
2122                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
2123                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
2124                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
2125                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
2126         }
2127
2128         return retval;
2129 }
2130
2131 bool hpd_rx_irq_check_link_loss_status(
2132         struct dc_link *link,
2133         union hpd_irq_data *hpd_irq_dpcd_data)
2134 {
2135         uint8_t irq_reg_rx_power_state = 0;
2136         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2137         union lane_status lane_status;
2138         uint32_t lane;
2139         bool sink_status_changed;
2140         bool return_code;
2141
2142         sink_status_changed = false;
2143         return_code = false;
2144
2145         if (link->cur_link_settings.lane_count == 0)
2146                 return return_code;
2147
2148         /*1. Check that Link Status changed, before re-training.*/
2149
2150         /*parse lane status*/
2151         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2152                 /* check status of lanes 0,1
2153                  * changed DpcdAddress_Lane01Status (0x202)
2154                  */
2155                 lane_status.raw = get_nibble_at_index(
2156                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2157                         lane);
2158
2159                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2160                         !lane_status.bits.CR_DONE_0 ||
2161                         !lane_status.bits.SYMBOL_LOCKED_0) {
2162                         /* if one of the channel equalization, clock
2163                          * recovery or symbol lock is dropped
2164                          * consider it as (link has been
2165                          * dropped) dp sink status has changed
2166                          */
2167                         sink_status_changed = true;
2168                         break;
2169                 }
2170         }
2171
2172         /* Check interlane align.*/
2173         if (sink_status_changed ||
2174                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2175
2176                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2177
2178                 return_code = true;
2179
2180                 /*2. Check that we can handle interrupt: Not in FS DOS,
2181                  *  Not in "Display Timeout" state, Link is trained.
2182                  */
2183                 dpcd_result = core_link_read_dpcd(link,
2184                         DP_SET_POWER,
2185                         &irq_reg_rx_power_state,
2186                         sizeof(irq_reg_rx_power_state));
2187
2188                 if (dpcd_result != DC_OK) {
2189                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2190                                 __func__);
2191                 } else {
2192                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2193                                 return_code = false;
2194                 }
2195         }
2196
2197         return return_code;
2198 }
2199
2200 bool dp_verify_link_cap(
2201         struct dc_link *link,
2202         struct dc_link_settings *known_limit_link_setting,
2203         int *fail_count)
2204 {
2205         struct dc_link_settings max_link_cap = {0};
2206         struct dc_link_settings cur_link_setting = {0};
2207         struct dc_link_settings *cur = &cur_link_setting;
2208         struct dc_link_settings initial_link_settings = {0};
2209         bool success;
2210         bool skip_link_training;
2211         bool skip_video_pattern;
2212         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2213         enum link_training_result status;
2214         union hpd_irq_data irq_data;
2215
2216         if (link->dc->debug.skip_detection_link_training) {
2217                 link->verified_link_cap = *known_limit_link_setting;
2218                 return true;
2219         }
2220
2221         memset(&irq_data, 0, sizeof(irq_data));
2222         success = false;
2223         skip_link_training = false;
2224
2225         max_link_cap = get_max_link_cap(link);
2226
2227         /* Grant extended timeout request */
2228         if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
2229                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2230
2231                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2232         }
2233
2234         /* TODO implement override and monitor patch later */
2235
2236         /* try to train the link from high to low to
2237          * find the physical link capability
2238          */
2239         /* disable PHY done possible by BIOS, will be done by driver itself */
2240         dp_disable_link_phy(link, link->connector_signal);
2241
2242         dp_cs_id = get_clock_source_id(link);
2243
2244         /* link training starts with the maximum common settings
2245          * supported by both sink and ASIC.
2246          */
2247         initial_link_settings = get_common_supported_link_settings(
2248                         *known_limit_link_setting,
2249                         max_link_cap);
2250         cur_link_setting = initial_link_settings;
2251
2252         /* Temporary Renoir-specific workaround for SWDEV-215184;
2253          * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2254          * so add extra cycle of enabling and disabling the PHY before first link training.
2255          */
2256         if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2257                         link->dc->debug.usbc_combo_phy_reset_wa) {
2258                 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2259                 dp_disable_link_phy(link, link->connector_signal);
2260         }
2261
2262         do {
2263                 skip_video_pattern = true;
2264
2265                 if (cur->link_rate == LINK_RATE_LOW)
2266                         skip_video_pattern = false;
2267
2268                 dp_enable_link_phy(
2269                                 link,
2270                                 link->connector_signal,
2271                                 dp_cs_id,
2272                                 cur);
2273
2274
2275                 if (skip_link_training)
2276                         success = true;
2277                 else {
2278                         status = dc_link_dp_perform_link_training(
2279                                                         link,
2280                                                         cur,
2281                                                         skip_video_pattern);
2282                         if (status == LINK_TRAINING_SUCCESS)
2283                                 success = true;
2284                         else
2285                                 (*fail_count)++;
2286                 }
2287
2288                 if (success) {
2289                         link->verified_link_cap = *cur;
2290                         udelay(1000);
2291                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2292                                 if (hpd_rx_irq_check_link_loss_status(
2293                                                 link,
2294                                                 &irq_data))
2295                                         (*fail_count)++;
2296                 }
2297                 /* always disable the link before trying another
2298                  * setting or before returning we'll enable it later
2299                  * based on the actual mode we're driving
2300                  */
2301                 dp_disable_link_phy(link, link->connector_signal);
2302         } while (!success && decide_fallback_link_setting(
2303                         initial_link_settings, cur, status));
2304
2305         /* Link Training failed for all Link Settings
2306          *  (Lane Count is still unknown)
2307          */
2308         if (!success) {
2309                 /* If all LT fails for all settings,
2310                  * set verified = failed safe (1 lane low)
2311                  */
2312                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2313                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2314
2315                 link->verified_link_cap.link_spread =
2316                 LINK_SPREAD_DISABLED;
2317         }
2318
2319
2320         return success;
2321 }
2322
2323 bool dp_verify_link_cap_with_retries(
2324         struct dc_link *link,
2325         struct dc_link_settings *known_limit_link_setting,
2326         int attempts)
2327 {
2328         uint8_t i = 0;
2329         bool success = false;
2330
2331         for (i = 0; i < attempts; i++) {
2332                 int fail_count = 0;
2333                 enum dc_connection_type type = dc_connection_none;
2334
2335                 memset(&link->verified_link_cap, 0,
2336                                 sizeof(struct dc_link_settings));
2337                 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2338                         link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2339                         link->verified_link_cap.link_rate = LINK_RATE_LOW;
2340                         link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2341                         break;
2342                 } else if (dp_verify_link_cap(link,
2343                                 &link->reported_link_cap,
2344                                 &fail_count) && fail_count == 0) {
2345                         success = true;
2346                         break;
2347                 }
2348                 msleep(10);
2349         }
2350         return success;
2351 }
2352
2353 bool dp_verify_mst_link_cap(
2354         struct dc_link *link)
2355 {
2356         struct dc_link_settings max_link_cap = {0};
2357
2358         max_link_cap = get_max_link_cap(link);
2359         link->verified_link_cap = get_common_supported_link_settings(
2360                 link->reported_link_cap,
2361                 max_link_cap);
2362
2363         return true;
2364 }
2365
2366 static struct dc_link_settings get_common_supported_link_settings(
2367                 struct dc_link_settings link_setting_a,
2368                 struct dc_link_settings link_setting_b)
2369 {
2370         struct dc_link_settings link_settings = {0};
2371
2372         link_settings.lane_count =
2373                 (link_setting_a.lane_count <=
2374                         link_setting_b.lane_count) ?
2375                         link_setting_a.lane_count :
2376                         link_setting_b.lane_count;
2377         link_settings.link_rate =
2378                 (link_setting_a.link_rate <=
2379                         link_setting_b.link_rate) ?
2380                         link_setting_a.link_rate :
2381                         link_setting_b.link_rate;
2382         link_settings.link_spread = LINK_SPREAD_DISABLED;
2383
2384         /* in DP compliance test, DPR-120 may have
2385          * a random value in its MAX_LINK_BW dpcd field.
2386          * We map it to the maximum supported link rate that
2387          * is smaller than MAX_LINK_BW in this case.
2388          */
2389         if (link_settings.link_rate > LINK_RATE_HIGH3) {
2390                 link_settings.link_rate = LINK_RATE_HIGH3;
2391         } else if (link_settings.link_rate < LINK_RATE_HIGH3
2392                         && link_settings.link_rate > LINK_RATE_HIGH2) {
2393                 link_settings.link_rate = LINK_RATE_HIGH2;
2394         } else if (link_settings.link_rate < LINK_RATE_HIGH2
2395                         && link_settings.link_rate > LINK_RATE_HIGH) {
2396                 link_settings.link_rate = LINK_RATE_HIGH;
2397         } else if (link_settings.link_rate < LINK_RATE_HIGH
2398                         && link_settings.link_rate > LINK_RATE_LOW) {
2399                 link_settings.link_rate = LINK_RATE_LOW;
2400         } else if (link_settings.link_rate < LINK_RATE_LOW) {
2401                 link_settings.link_rate = LINK_RATE_UNKNOWN;
2402         }
2403
2404         return link_settings;
2405 }
2406
2407 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2408 {
2409         return lane_count <= LANE_COUNT_ONE;
2410 }
2411
2412 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2413 {
2414         return link_rate <= LINK_RATE_LOW;
2415 }
2416
2417 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2418 {
2419         switch (lane_count) {
2420         case LANE_COUNT_FOUR:
2421                 return LANE_COUNT_TWO;
2422         case LANE_COUNT_TWO:
2423                 return LANE_COUNT_ONE;
2424         case LANE_COUNT_ONE:
2425                 return LANE_COUNT_UNKNOWN;
2426         default:
2427                 return LANE_COUNT_UNKNOWN;
2428         }
2429 }
2430
2431 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2432 {
2433         switch (link_rate) {
2434         case LINK_RATE_HIGH3:
2435                 return LINK_RATE_HIGH2;
2436         case LINK_RATE_HIGH2:
2437                 return LINK_RATE_HIGH;
2438         case LINK_RATE_HIGH:
2439                 return LINK_RATE_LOW;
2440         case LINK_RATE_LOW:
2441                 return LINK_RATE_UNKNOWN;
2442         default:
2443                 return LINK_RATE_UNKNOWN;
2444         }
2445 }
2446
2447 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2448 {
2449         switch (lane_count) {
2450         case LANE_COUNT_ONE:
2451                 return LANE_COUNT_TWO;
2452         case LANE_COUNT_TWO:
2453                 return LANE_COUNT_FOUR;
2454         default:
2455                 return LANE_COUNT_UNKNOWN;
2456         }
2457 }
2458
2459 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2460 {
2461         switch (link_rate) {
2462         case LINK_RATE_LOW:
2463                 return LINK_RATE_HIGH;
2464         case LINK_RATE_HIGH:
2465                 return LINK_RATE_HIGH2;
2466         case LINK_RATE_HIGH2:
2467                 return LINK_RATE_HIGH3;
2468         default:
2469                 return LINK_RATE_UNKNOWN;
2470         }
2471 }
2472
2473 /*
2474  * function: set link rate and lane count fallback based
2475  * on current link setting and last link training result
2476  * return value:
2477  *                      true - link setting could be set
2478  *                      false - has reached minimum setting
2479  *                                      and no further fallback could be done
2480  */
2481 static bool decide_fallback_link_setting(
2482                 struct dc_link_settings initial_link_settings,
2483                 struct dc_link_settings *current_link_setting,
2484                 enum link_training_result training_result)
2485 {
2486         if (!current_link_setting)
2487                 return false;
2488
2489         switch (training_result) {
2490         case LINK_TRAINING_CR_FAIL_LANE0:
2491         case LINK_TRAINING_CR_FAIL_LANE1:
2492         case LINK_TRAINING_CR_FAIL_LANE23:
2493         case LINK_TRAINING_LQA_FAIL:
2494         {
2495                 if (!reached_minimum_link_rate
2496                                 (current_link_setting->link_rate)) {
2497                         current_link_setting->link_rate =
2498                                 reduce_link_rate(
2499                                         current_link_setting->link_rate);
2500                 } else if (!reached_minimum_lane_count
2501                                 (current_link_setting->lane_count)) {
2502                         current_link_setting->link_rate =
2503                                 initial_link_settings.link_rate;
2504                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2505                                 return false;
2506                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2507                                 current_link_setting->lane_count =
2508                                                 LANE_COUNT_ONE;
2509                         else if (training_result ==
2510                                         LINK_TRAINING_CR_FAIL_LANE23)
2511                                 current_link_setting->lane_count =
2512                                                 LANE_COUNT_TWO;
2513                         else
2514                                 current_link_setting->lane_count =
2515                                         reduce_lane_count(
2516                                         current_link_setting->lane_count);
2517                 } else {
2518                         return false;
2519                 }
2520                 break;
2521         }
2522         case LINK_TRAINING_EQ_FAIL_EQ:
2523         {
2524                 if (!reached_minimum_lane_count
2525                                 (current_link_setting->lane_count)) {
2526                         current_link_setting->lane_count =
2527                                 reduce_lane_count(
2528                                         current_link_setting->lane_count);
2529                 } else if (!reached_minimum_link_rate
2530                                 (current_link_setting->link_rate)) {
2531                         current_link_setting->link_rate =
2532                                 reduce_link_rate(
2533                                         current_link_setting->link_rate);
2534                 } else {
2535                         return false;
2536                 }
2537                 break;
2538         }
2539         case LINK_TRAINING_EQ_FAIL_CR:
2540         {
2541                 if (!reached_minimum_link_rate
2542                                 (current_link_setting->link_rate)) {
2543                         current_link_setting->link_rate =
2544                                 reduce_link_rate(
2545                                         current_link_setting->link_rate);
2546                 } else {
2547                         return false;
2548                 }
2549                 break;
2550         }
2551         default:
2552                 return false;
2553         }
2554         return true;
2555 }
2556
2557 bool dp_validate_mode_timing(
2558         struct dc_link *link,
2559         const struct dc_crtc_timing *timing)
2560 {
2561         uint32_t req_bw;
2562         uint32_t max_bw;
2563
2564         const struct dc_link_settings *link_setting;
2565
2566         /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
2567         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
2568                         !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
2569                         dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
2570                 return false;
2571
2572         /*always DP fail safe mode*/
2573         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2574                 timing->h_addressable == (uint32_t) 640 &&
2575                 timing->v_addressable == (uint32_t) 480)
2576                 return true;
2577
2578         link_setting = dc_link_get_link_cap(link);
2579
2580         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2581         /*if (flags.DYNAMIC_VALIDATION == 1 &&
2582                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2583                 link_setting = &link->verified_link_cap;
2584         */
2585
2586         req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2587         max_bw = dc_link_bandwidth_kbps(link, link_setting);
2588
2589         if (req_bw <= max_bw) {
2590                 /* remember the biggest mode here, during
2591                  * initial link training (to get
2592                  * verified_link_cap), LS sends event about
2593                  * cannot train at reported cap to upper
2594                  * layer and upper layer will re-enumerate modes.
2595                  * this is not necessary if the lower
2596                  * verified_link_cap is enough to drive
2597                  * all the modes */
2598
2599                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2600                 /* if (flags.DYNAMIC_VALIDATION == 1)
2601                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
2602                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2603                 return true;
2604         } else
2605                 return false;
2606 }
2607
2608 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2609 {
2610         struct dc_link_settings initial_link_setting = {
2611                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2612         struct dc_link_settings current_link_setting =
2613                         initial_link_setting;
2614         uint32_t link_bw;
2615
2616         if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2617                 return false;
2618
2619         /* search for the minimum link setting that:
2620          * 1. is supported according to the link training result
2621          * 2. could support the b/w requested by the timing
2622          */
2623         while (current_link_setting.link_rate <=
2624                         link->verified_link_cap.link_rate) {
2625                 link_bw = dc_link_bandwidth_kbps(
2626                                 link,
2627                                 &current_link_setting);
2628                 if (req_bw <= link_bw) {
2629                         *link_setting = current_link_setting;
2630                         return true;
2631                 }
2632
2633                 if (current_link_setting.lane_count <
2634                                 link->verified_link_cap.lane_count) {
2635                         current_link_setting.lane_count =
2636                                         increase_lane_count(
2637                                                         current_link_setting.lane_count);
2638                 } else {
2639                         current_link_setting.link_rate =
2640                                         increase_link_rate(
2641                                                         current_link_setting.link_rate);
2642                         current_link_setting.lane_count =
2643                                         initial_link_setting.lane_count;
2644                 }
2645         }
2646
2647         return false;
2648 }
2649
2650 bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2651 {
2652         struct dc_link_settings initial_link_setting;
2653         struct dc_link_settings current_link_setting;
2654         uint32_t link_bw;
2655
2656         /*
2657          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
2658          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
2659          */
2660         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
2661                         link->dpcd_caps.edp_supported_link_rates_count == 0) {
2662                 *link_setting = link->verified_link_cap;
2663                 return true;
2664         }
2665
2666         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2667         initial_link_setting.lane_count = LANE_COUNT_ONE;
2668         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2669         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2670         initial_link_setting.use_link_rate_set = true;
2671         initial_link_setting.link_rate_set = 0;
2672         current_link_setting = initial_link_setting;
2673
2674         /* search for the minimum link setting that:
2675          * 1. is supported according to the link training result
2676          * 2. could support the b/w requested by the timing
2677          */
2678         while (current_link_setting.link_rate <=
2679                         link->verified_link_cap.link_rate) {
2680                 link_bw = dc_link_bandwidth_kbps(
2681                                 link,
2682                                 &current_link_setting);
2683                 if (req_bw <= link_bw) {
2684                         *link_setting = current_link_setting;
2685                         return true;
2686                 }
2687
2688                 if (current_link_setting.lane_count <
2689                                 link->verified_link_cap.lane_count) {
2690                         current_link_setting.lane_count =
2691                                         increase_lane_count(
2692                                                         current_link_setting.lane_count);
2693                 } else {
2694                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2695                                 current_link_setting.link_rate_set++;
2696                                 current_link_setting.link_rate =
2697                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2698                                 current_link_setting.lane_count =
2699                                                                         initial_link_setting.lane_count;
2700                         } else
2701                                 break;
2702                 }
2703         }
2704         return false;
2705 }
2706
2707 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2708 {
2709         *link_setting = link->verified_link_cap;
2710         return true;
2711 }
2712
2713 void decide_link_settings(struct dc_stream_state *stream,
2714         struct dc_link_settings *link_setting)
2715 {
2716         struct dc_link *link;
2717         uint32_t req_bw;
2718
2719         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2720
2721         link = stream->link;
2722
2723         /* if preferred is specified through AMDDP, use it, if it's enough
2724          * to drive the mode
2725          */
2726         if (link->preferred_link_setting.lane_count !=
2727                         LANE_COUNT_UNKNOWN &&
2728                         link->preferred_link_setting.link_rate !=
2729                                         LINK_RATE_UNKNOWN) {
2730                 *link_setting =  link->preferred_link_setting;
2731                 return;
2732         }
2733
2734         /* MST doesn't perform link training for now
2735          * TODO: add MST specific link training routine
2736          */
2737         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2738                 if (decide_mst_link_settings(link, link_setting))
2739                         return;
2740         } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2741                 if (decide_edp_link_settings(link, link_setting, req_bw))
2742                         return;
2743         } else if (decide_dp_link_settings(link, link_setting, req_bw))
2744                 return;
2745
2746         BREAK_TO_DEBUGGER();
2747         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2748
2749         *link_setting = link->verified_link_cap;
2750 }
2751
2752 /*************************Short Pulse IRQ***************************/
2753 static bool allow_hpd_rx_irq(const struct dc_link *link)
2754 {
2755         /*
2756          * Don't handle RX IRQ unless one of following is met:
2757          * 1) The link is established (cur_link_settings != unknown)
2758          * 2) We know we're dealing with a branch device, SST or MST
2759          */
2760
2761         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2762                 is_dp_branch_device(link))
2763                 return true;
2764
2765         return false;
2766 }
2767
2768 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2769 {
2770         union dpcd_psr_configuration psr_configuration;
2771
2772         if (!link->psr_settings.psr_feature_enabled)
2773                 return false;
2774
2775         dm_helpers_dp_read_dpcd(
2776                 link->ctx,
2777                 link,
2778                 368,/*DpcdAddress_PSR_Enable_Cfg*/
2779                 &psr_configuration.raw,
2780                 sizeof(psr_configuration.raw));
2781
2782
2783         if (psr_configuration.bits.ENABLE) {
2784                 unsigned char dpcdbuf[3] = {0};
2785                 union psr_error_status psr_error_status;
2786                 union psr_sink_psr_status psr_sink_psr_status;
2787
2788                 dm_helpers_dp_read_dpcd(
2789                         link->ctx,
2790                         link,
2791                         0x2006, /*DpcdAddress_PSR_Error_Status*/
2792                         (unsigned char *) dpcdbuf,
2793                         sizeof(dpcdbuf));
2794
2795                 /*DPCD 2006h   ERROR STATUS*/
2796                 psr_error_status.raw = dpcdbuf[0];
2797                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
2798                 psr_sink_psr_status.raw = dpcdbuf[2];
2799
2800                 if (psr_error_status.bits.LINK_CRC_ERROR ||
2801                                 psr_error_status.bits.RFB_STORAGE_ERROR ||
2802                                 psr_error_status.bits.VSC_SDP_ERROR) {
2803                         /* Acknowledge and clear error bits */
2804                         dm_helpers_dp_write_dpcd(
2805                                 link->ctx,
2806                                 link,
2807                                 8198,/*DpcdAddress_PSR_Error_Status*/
2808                                 &psr_error_status.raw,
2809                                 sizeof(psr_error_status.raw));
2810
2811                         /* PSR error, disable and re-enable PSR */
2812                         dc_link_set_psr_allow_active(link, false, true, false);
2813                         dc_link_set_psr_allow_active(link, true, true, false);
2814
2815                         return true;
2816                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2817                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2818                         /* No error is detect, PSR is active.
2819                          * We should return with IRQ_HPD handled without
2820                          * checking for loss of sync since PSR would have
2821                          * powered down main link.
2822                          */
2823                         return true;
2824                 }
2825         }
2826         return false;
2827 }
2828
2829 static void dp_test_send_link_training(struct dc_link *link)
2830 {
2831         struct dc_link_settings link_settings = {0};
2832
2833         core_link_read_dpcd(
2834                         link,
2835                         DP_TEST_LANE_COUNT,
2836                         (unsigned char *)(&link_settings.lane_count),
2837                         1);
2838         core_link_read_dpcd(
2839                         link,
2840                         DP_TEST_LINK_RATE,
2841                         (unsigned char *)(&link_settings.link_rate),
2842                         1);
2843
2844         /* Set preferred link settings */
2845         link->verified_link_cap.lane_count = link_settings.lane_count;
2846         link->verified_link_cap.link_rate = link_settings.link_rate;
2847
2848         dp_retrain_link_dp_test(link, &link_settings, false);
2849 }
2850
2851 /* TODO Raven hbr2 compliance eye output is unstable
2852  * (toggling on and off) with debugger break
2853  * This caueses intermittent PHY automation failure
2854  * Need to look into the root cause */
2855 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2856 {
2857         union phy_test_pattern dpcd_test_pattern;
2858         union lane_adjust dpcd_lane_adjustment[2];
2859         unsigned char dpcd_post_cursor_2_adjustment = 0;
2860         unsigned char test_pattern_buffer[
2861                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2862                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2863         unsigned int test_pattern_size = 0;
2864         enum dp_test_pattern test_pattern;
2865         struct dc_link_training_settings link_settings;
2866         union lane_adjust dpcd_lane_adjust;
2867         unsigned int lane;
2868         struct link_training_settings link_training_settings;
2869         int i = 0;
2870
2871         dpcd_test_pattern.raw = 0;
2872         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2873         memset(&link_settings, 0, sizeof(link_settings));
2874
2875         /* get phy test pattern and pattern parameters from DP receiver */
2876         core_link_read_dpcd(
2877                         link,
2878                         DP_PHY_TEST_PATTERN,
2879                         &dpcd_test_pattern.raw,
2880                         sizeof(dpcd_test_pattern));
2881         core_link_read_dpcd(
2882                         link,
2883                         DP_ADJUST_REQUEST_LANE0_1,
2884                         &dpcd_lane_adjustment[0].raw,
2885                         sizeof(dpcd_lane_adjustment));
2886
2887         /*get post cursor 2 parameters
2888          * For DP 1.1a or eariler, this DPCD register's value is 0
2889          * For DP 1.2 or later:
2890          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2891          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2892          */
2893         core_link_read_dpcd(
2894                         link,
2895                         DP_ADJUST_REQUEST_POST_CURSOR2,
2896                         &dpcd_post_cursor_2_adjustment,
2897                         sizeof(dpcd_post_cursor_2_adjustment));
2898
2899         /* translate request */
2900         switch (dpcd_test_pattern.bits.PATTERN) {
2901         case PHY_TEST_PATTERN_D10_2:
2902                 test_pattern = DP_TEST_PATTERN_D102;
2903                 break;
2904         case PHY_TEST_PATTERN_SYMBOL_ERROR:
2905                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2906                 break;
2907         case PHY_TEST_PATTERN_PRBS7:
2908                 test_pattern = DP_TEST_PATTERN_PRBS7;
2909                 break;
2910         case PHY_TEST_PATTERN_80BIT_CUSTOM:
2911                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2912                 break;
2913         case PHY_TEST_PATTERN_CP2520_1:
2914                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2915                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2916                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2917                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2918                 break;
2919         case PHY_TEST_PATTERN_CP2520_2:
2920                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2921                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2922                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2923                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2924                 break;
2925         case PHY_TEST_PATTERN_CP2520_3:
2926                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2927                 break;
2928         default:
2929                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2930         break;
2931         }
2932
2933         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
2934                 test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2935                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1;
2936                 core_link_read_dpcd(
2937                                 link,
2938                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2939                                 test_pattern_buffer,
2940                                 test_pattern_size);
2941         }
2942
2943         /* prepare link training settings */
2944         link_settings.link = link->cur_link_settings;
2945
2946         for (lane = 0; lane <
2947                 (unsigned int)(link->cur_link_settings.lane_count);
2948                 lane++) {
2949                 dpcd_lane_adjust.raw =
2950                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2951                 link_settings.lane_settings[lane].VOLTAGE_SWING =
2952                         (enum dc_voltage_swing)
2953                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2954                 link_settings.lane_settings[lane].PRE_EMPHASIS =
2955                         (enum dc_pre_emphasis)
2956                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2957                 link_settings.lane_settings[lane].POST_CURSOR2 =
2958                         (enum dc_post_cursor2)
2959                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2960         }
2961
2962         for (i = 0; i < 4; i++)
2963                 link_training_settings.lane_settings[i] =
2964                                 link_settings.lane_settings[i];
2965         link_training_settings.link_settings = link_settings.link;
2966         link_training_settings.allow_invalid_msa_timing_param = false;
2967         /*Usage: Measure DP physical lane signal
2968          * by DP SI test equipment automatically.
2969          * PHY test pattern request is generated by equipment via HPD interrupt.
2970          * HPD needs to be active all the time. HPD should be active
2971          * all the time. Do not touch it.
2972          * forward request to DS
2973          */
2974         dc_link_dp_set_test_pattern(
2975                 link,
2976                 test_pattern,
2977                 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2978                 &link_training_settings,
2979                 test_pattern_buffer,
2980                 test_pattern_size);
2981 }
2982
2983 static void dp_test_send_link_test_pattern(struct dc_link *link)
2984 {
2985         union link_test_pattern dpcd_test_pattern;
2986         union test_misc dpcd_test_params;
2987         enum dp_test_pattern test_pattern;
2988         enum dp_test_pattern_color_space test_pattern_color_space =
2989                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2990         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2991         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2992         struct pipe_ctx *pipe_ctx = NULL;
2993         int i;
2994
2995         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2996         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2997
2998         for (i = 0; i < MAX_PIPES; i++) {
2999                 if (pipes[i].stream == NULL)
3000                         continue;
3001
3002                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
3003                         pipe_ctx = &pipes[i];
3004                         break;
3005                 }
3006         }
3007
3008         if (pipe_ctx == NULL)
3009                 return;
3010
3011         /* get link test pattern and pattern parameters */
3012         core_link_read_dpcd(
3013                         link,
3014                         DP_TEST_PATTERN,
3015                         &dpcd_test_pattern.raw,
3016                         sizeof(dpcd_test_pattern));
3017         core_link_read_dpcd(
3018                         link,
3019                         DP_TEST_MISC0,
3020                         &dpcd_test_params.raw,
3021                         sizeof(dpcd_test_params));
3022
3023         switch (dpcd_test_pattern.bits.PATTERN) {
3024         case LINK_TEST_PATTERN_COLOR_RAMP:
3025                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
3026         break;
3027         case LINK_TEST_PATTERN_VERTICAL_BARS:
3028                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
3029         break; /* black and white */
3030         case LINK_TEST_PATTERN_COLOR_SQUARES:
3031                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
3032                                 TEST_DYN_RANGE_VESA ?
3033                                 DP_TEST_PATTERN_COLOR_SQUARES :
3034                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
3035         break;
3036         default:
3037                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
3038         break;
3039         }
3040
3041         if (dpcd_test_params.bits.CLR_FORMAT == 0)
3042                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
3043         else
3044                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
3045                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
3046                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
3047
3048         switch (dpcd_test_params.bits.BPC) {
3049         case 0: // 6 bits
3050                 requestColorDepth = COLOR_DEPTH_666;
3051                 break;
3052         case 1: // 8 bits
3053                 requestColorDepth = COLOR_DEPTH_888;
3054                 break;
3055         case 2: // 10 bits
3056                 requestColorDepth = COLOR_DEPTH_101010;
3057                 break;
3058         case 3: // 12 bits
3059                 requestColorDepth = COLOR_DEPTH_121212;
3060                 break;
3061         default:
3062                 break;
3063         }
3064
3065         switch (dpcd_test_params.bits.CLR_FORMAT) {
3066         case 0:
3067                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3068                 break;
3069         case 1:
3070                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
3071                 break;
3072         case 2:
3073                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
3074                 break;
3075         default:
3076                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3077                 break;
3078         }
3079
3080
3081         if (requestColorDepth != COLOR_DEPTH_UNDEFINED
3082                         && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
3083                 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
3084                                 __func__,
3085                                 pipe_ctx->stream->timing.display_color_depth,
3086                                 requestColorDepth);
3087                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
3088         }
3089
3090         dp_update_dsc_config(pipe_ctx);
3091
3092         dc_link_dp_set_test_pattern(
3093                         link,
3094                         test_pattern,
3095                         test_pattern_color_space,
3096                         NULL,
3097                         NULL,
3098                         0);
3099 }
3100
3101 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
3102 {
3103         union audio_test_mode            dpcd_test_mode = {0};
3104         struct audio_test_pattern_type   dpcd_pattern_type = {0};
3105         union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
3106         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3107
3108         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3109         struct pipe_ctx *pipe_ctx = &pipes[0];
3110         unsigned int channel_count;
3111         unsigned int channel = 0;
3112         unsigned int modes = 0;
3113         unsigned int sampling_rate_in_hz = 0;
3114
3115         // get audio test mode and test pattern parameters
3116         core_link_read_dpcd(
3117                 link,
3118                 DP_TEST_AUDIO_MODE,
3119                 &dpcd_test_mode.raw,
3120                 sizeof(dpcd_test_mode));
3121
3122         core_link_read_dpcd(
3123                 link,
3124                 DP_TEST_AUDIO_PATTERN_TYPE,
3125                 &dpcd_pattern_type.value,
3126                 sizeof(dpcd_pattern_type));
3127
3128         channel_count = dpcd_test_mode.bits.channel_count + 1;
3129
3130         // read pattern periods for requested channels when sawTooth pattern is requested
3131         if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
3132                         dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
3133
3134                 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
3135                                 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3136                 // read period for each channel
3137                 for (channel = 0; channel < channel_count; channel++) {
3138                         core_link_read_dpcd(
3139                                                         link,
3140                                                         DP_TEST_AUDIO_PERIOD_CH1 + channel,
3141                                                         &dpcd_pattern_period[channel].raw,
3142                                                         sizeof(dpcd_pattern_period[channel]));
3143                 }
3144         }
3145
3146         // translate sampling rate
3147         switch (dpcd_test_mode.bits.sampling_rate) {
3148         case AUDIO_SAMPLING_RATE_32KHZ:
3149                 sampling_rate_in_hz = 32000;
3150                 break;
3151         case AUDIO_SAMPLING_RATE_44_1KHZ:
3152                 sampling_rate_in_hz = 44100;
3153                 break;
3154         case AUDIO_SAMPLING_RATE_48KHZ:
3155                 sampling_rate_in_hz = 48000;
3156                 break;
3157         case AUDIO_SAMPLING_RATE_88_2KHZ:
3158                 sampling_rate_in_hz = 88200;
3159                 break;
3160         case AUDIO_SAMPLING_RATE_96KHZ:
3161                 sampling_rate_in_hz = 96000;
3162                 break;
3163         case AUDIO_SAMPLING_RATE_176_4KHZ:
3164                 sampling_rate_in_hz = 176400;
3165                 break;
3166         case AUDIO_SAMPLING_RATE_192KHZ:
3167                 sampling_rate_in_hz = 192000;
3168                 break;
3169         default:
3170                 sampling_rate_in_hz = 0;
3171                 break;
3172         }
3173
3174         link->audio_test_data.flags.test_requested = 1;
3175         link->audio_test_data.flags.disable_video = disable_video;
3176         link->audio_test_data.sampling_rate = sampling_rate_in_hz;
3177         link->audio_test_data.channel_count = channel_count;
3178         link->audio_test_data.pattern_type = test_pattern;
3179
3180         if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3181                 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3182                         link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3183                 }
3184         }
3185 }
3186
3187 static void handle_automated_test(struct dc_link *link)
3188 {
3189         union test_request test_request;
3190         union test_response test_response;
3191
3192         memset(&test_request, 0, sizeof(test_request));
3193         memset(&test_response, 0, sizeof(test_response));
3194
3195         core_link_read_dpcd(
3196                 link,
3197                 DP_TEST_REQUEST,
3198                 &test_request.raw,
3199                 sizeof(union test_request));
3200         if (test_request.bits.LINK_TRAINING) {
3201                 /* ACK first to let DP RX test box monitor LT sequence */
3202                 test_response.bits.ACK = 1;
3203                 core_link_write_dpcd(
3204                         link,
3205                         DP_TEST_RESPONSE,
3206                         &test_response.raw,
3207                         sizeof(test_response));
3208                 dp_test_send_link_training(link);
3209                 /* no acknowledge request is needed again */
3210                 test_response.bits.ACK = 0;
3211         }
3212         if (test_request.bits.LINK_TEST_PATTRN) {
3213                 dp_test_send_link_test_pattern(link);
3214                 test_response.bits.ACK = 1;
3215         }
3216
3217         if (test_request.bits.AUDIO_TEST_PATTERN) {
3218                 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3219                 test_response.bits.ACK = 1;
3220         }
3221
3222         if (test_request.bits.PHY_TEST_PATTERN) {
3223                 dp_test_send_phy_test_pattern(link);
3224                 test_response.bits.ACK = 1;
3225         }
3226
3227         /* send request acknowledgment */
3228         if (test_response.bits.ACK)
3229                 core_link_write_dpcd(
3230                         link,
3231                         DP_TEST_RESPONSE,
3232                         &test_response.raw,
3233                         sizeof(test_response));
3234 }
3235
3236 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
3237 {
3238         union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
3239         union device_service_irq device_service_clear = { { 0 } };
3240         enum dc_status result;
3241         bool status = false;
3242         struct pipe_ctx *pipe_ctx;
3243         int i;
3244
3245         if (out_link_loss)
3246                 *out_link_loss = false;
3247         /* For use cases related to down stream connection status change,
3248          * PSR and device auto test, refer to function handle_sst_hpd_irq
3249          * in DAL2.1*/
3250
3251         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
3252                 __func__, link->link_index);
3253
3254
3255          /* All the "handle_hpd_irq_xxx()" methods
3256                  * should be called only after
3257                  * dal_dpsst_ls_read_hpd_irq_data
3258                  * Order of calls is important too
3259                  */
3260         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
3261         if (out_hpd_irq_dpcd_data)
3262                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
3263
3264         if (result != DC_OK) {
3265                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
3266                         __func__);
3267                 return false;
3268         }
3269
3270         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3271                 device_service_clear.bits.AUTOMATED_TEST = 1;
3272                 core_link_write_dpcd(
3273                         link,
3274                         DP_DEVICE_SERVICE_IRQ_VECTOR,
3275                         &device_service_clear.raw,
3276                         sizeof(device_service_clear.raw));
3277                 device_service_clear.raw = 0;
3278                 handle_automated_test(link);
3279                 return false;
3280         }
3281
3282         if (!allow_hpd_rx_irq(link)) {
3283                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3284                         __func__, link->link_index);
3285                 return false;
3286         }
3287
3288         if (handle_hpd_irq_psr_sink(link))
3289                 /* PSR-related error was detected and handled */
3290                 return true;
3291
3292         /* If PSR-related error handled, Main link may be off,
3293          * so do not handle as a normal sink status change interrupt.
3294          */
3295
3296         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3297                 return true;
3298
3299         /* check if we have MST msg and return since we poll for it */
3300         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3301                 return false;
3302
3303         /* For now we only handle 'Downstream port status' case.
3304          * If we got sink count changed it means
3305          * Downstream port status changed,
3306          * then DM should call DC to do the detection.
3307          * NOTE: Do not handle link loss on eDP since it is internal link*/
3308         if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3309                 hpd_rx_irq_check_link_loss_status(
3310                         link,
3311                         &hpd_irq_dpcd_data)) {
3312                 /* Connectivity log: link loss */
3313                 CONN_DATA_LINK_LOSS(link,
3314                                         hpd_irq_dpcd_data.raw,
3315                                         sizeof(hpd_irq_dpcd_data),
3316                                         "Status: ");
3317
3318                 for (i = 0; i < MAX_PIPES; i++) {
3319                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3320                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3321                                 break;
3322                 }
3323
3324                 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3325                         return false;
3326
3327
3328                 for (i = 0; i < MAX_PIPES; i++) {
3329                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3330                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3331                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3332                                 core_link_disable_stream(pipe_ctx);
3333                 }
3334
3335                 for (i = 0; i < MAX_PIPES; i++) {
3336                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3337                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3338                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3339                                 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3340                 }
3341
3342                 status = false;
3343                 if (out_link_loss)
3344                         *out_link_loss = true;
3345         }
3346
3347         if (link->type == dc_connection_sst_branch &&
3348                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3349                         != link->dpcd_sink_count)
3350                 status = true;
3351
3352         /* reasons for HPD RX:
3353          * 1. Link Loss - ie Re-train the Link
3354          * 2. MST sideband message
3355          * 3. Automated Test - ie. Internal Commit
3356          * 4. CP (copy protection) - (not interesting for DM???)
3357          * 5. DRR
3358          * 6. Downstream Port status changed
3359          * -ie. Detect - this the only one
3360          * which is interesting for DM because
3361          * it must call dc_link_detect.
3362          */
3363         return status;
3364 }
3365
3366 /*query dpcd for version and mst cap addresses*/
3367 bool is_mst_supported(struct dc_link *link)
3368 {
3369         bool mst          = false;
3370         enum dc_status st = DC_OK;
3371         union dpcd_rev rev;
3372         union mstm_cap cap;
3373
3374         if (link->preferred_training_settings.mst_enable &&
3375                 *link->preferred_training_settings.mst_enable == false) {
3376                 return false;
3377         }
3378
3379         rev.raw  = 0;
3380         cap.raw  = 0;
3381
3382         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3383                         sizeof(rev));
3384
3385         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3386
3387                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3388                                 &cap.raw, sizeof(cap));
3389                 if (st == DC_OK && cap.bits.MST_CAP == 1)
3390                         mst = true;
3391         }
3392         return mst;
3393
3394 }
3395
3396 bool is_dp_active_dongle(const struct dc_link *link)
3397 {
3398         return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
3399                                 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
3400 }
3401
3402 bool is_dp_branch_device(const struct dc_link *link)
3403 {
3404         return link->dpcd_caps.is_branch_dev;
3405 }
3406
3407 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3408 {
3409         switch (bpc) {
3410         case DOWN_STREAM_MAX_8BPC:
3411                 return 8;
3412         case DOWN_STREAM_MAX_10BPC:
3413                 return 10;
3414         case DOWN_STREAM_MAX_12BPC:
3415                 return 12;
3416         case DOWN_STREAM_MAX_16BPC:
3417                 return 16;
3418         default:
3419                 break;
3420         }
3421
3422         return -1;
3423 }
3424
3425 static void read_dp_device_vendor_id(struct dc_link *link)
3426 {
3427         struct dp_device_vendor_id dp_id;
3428
3429         /* read IEEE branch device id */
3430         core_link_read_dpcd(
3431                 link,
3432                 DP_BRANCH_OUI,
3433                 (uint8_t *)&dp_id,
3434                 sizeof(dp_id));
3435
3436         link->dpcd_caps.branch_dev_id =
3437                 (dp_id.ieee_oui[0] << 16) +
3438                 (dp_id.ieee_oui[1] << 8) +
3439                 dp_id.ieee_oui[2];
3440
3441         memmove(
3442                 link->dpcd_caps.branch_dev_name,
3443                 dp_id.ieee_device_id,
3444                 sizeof(dp_id.ieee_device_id));
3445 }
3446
3447
3448
3449 static void get_active_converter_info(
3450         uint8_t data, struct dc_link *link)
3451 {
3452         union dp_downstream_port_present ds_port = { .byte = data };
3453         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3454
3455         /* decode converter info*/
3456         if (!ds_port.fields.PORT_PRESENT) {
3457                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3458                 ddc_service_set_dongle_type(link->ddc,
3459                                 link->dpcd_caps.dongle_type);
3460                 link->dpcd_caps.is_branch_dev = false;
3461                 return;
3462         }
3463
3464         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3465         link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3466
3467         switch (ds_port.fields.PORT_TYPE) {
3468         case DOWNSTREAM_VGA:
3469                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3470                 break;
3471         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3472                 /* At this point we don't know is it DVI or HDMI or DP++,
3473                  * assume DVI.*/
3474                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3475                 break;
3476         default:
3477                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3478                 break;
3479         }
3480
3481         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3482                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3483                 union dwnstream_port_caps_byte0 *port_caps =
3484                         (union dwnstream_port_caps_byte0 *)det_caps;
3485                 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3486                                 det_caps, sizeof(det_caps)) == DC_OK) {
3487
3488                         switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3489                         /*Handle DP case as DONGLE_NONE*/
3490                         case DOWN_STREAM_DETAILED_DP:
3491                                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3492                                 break;
3493                         case DOWN_STREAM_DETAILED_VGA:
3494                                 link->dpcd_caps.dongle_type =
3495                                         DISPLAY_DONGLE_DP_VGA_CONVERTER;
3496                                 break;
3497                         case DOWN_STREAM_DETAILED_DVI:
3498                                 link->dpcd_caps.dongle_type =
3499                                         DISPLAY_DONGLE_DP_DVI_CONVERTER;
3500                                 break;
3501                         case DOWN_STREAM_DETAILED_HDMI:
3502                         case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3503                                 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3504                                 link->dpcd_caps.dongle_type =
3505                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3506
3507                                 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3508                                 if (ds_port.fields.DETAILED_CAPS) {
3509
3510                                         union dwnstream_port_caps_byte3_hdmi
3511                                                 hdmi_caps = {.raw = det_caps[3] };
3512                                         union dwnstream_port_caps_byte2
3513                                                 hdmi_color_caps = {.raw = det_caps[2] };
3514                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3515                                                 det_caps[1] * 2500;
3516
3517                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3518                                                 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3519                                         /*YCBCR capability only for HDMI case*/
3520                                         if (port_caps->bits.DWN_STRM_PORTX_TYPE
3521                                                         == DOWN_STREAM_DETAILED_HDMI) {
3522                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3523                                                                 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3524                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3525                                                                 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3526                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3527                                                                 hdmi_caps.bits.YCrCr422_CONVERSION;
3528                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3529                                                                 hdmi_caps.bits.YCrCr420_CONVERSION;
3530                                         }
3531
3532                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3533                                                 translate_dpcd_max_bpc(
3534                                                         hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3535
3536                                         if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3537                                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3538                                 }
3539
3540                                 break;
3541                         }
3542                 }
3543         }
3544
3545         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3546
3547         {
3548                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3549
3550                 core_link_read_dpcd(
3551                         link,
3552                         DP_BRANCH_REVISION_START,
3553                         (uint8_t *)&dp_hw_fw_revision,
3554                         sizeof(dp_hw_fw_revision));
3555
3556                 link->dpcd_caps.branch_hw_revision =
3557                         dp_hw_fw_revision.ieee_hw_rev;
3558
3559                 memmove(
3560                         link->dpcd_caps.branch_fw_revision,
3561                         dp_hw_fw_revision.ieee_fw_rev,
3562                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
3563         }
3564 }
3565
3566 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3567                 int length)
3568 {
3569         int retry = 0;
3570
3571         if (!link->dpcd_caps.dpcd_rev.raw) {
3572                 do {
3573                         dp_receiver_power_ctrl(link, true);
3574                         core_link_read_dpcd(link, DP_DPCD_REV,
3575                                                         dpcd_data, length);
3576                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3577                                 DP_DPCD_REV -
3578                                 DP_DPCD_REV];
3579                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3580         }
3581
3582         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3583                 switch (link->dpcd_caps.branch_dev_id) {
3584                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3585                  * all internal circuits including AUX communication preventing
3586                  * reading DPCD table and EDID (spec violation).
3587                  * Encoder will skip DP RX power down on disable_output to
3588                  * keep receiver powered all the time.*/
3589                 case DP_BRANCH_DEVICE_ID_0010FA:
3590                 case DP_BRANCH_DEVICE_ID_0080E1:
3591                 case DP_BRANCH_DEVICE_ID_00E04C:
3592                         link->wa_flags.dp_keep_receiver_powered = true;
3593                         break;
3594
3595                 /* TODO: May need work around for other dongles. */
3596                 default:
3597                         link->wa_flags.dp_keep_receiver_powered = false;
3598                         break;
3599                 }
3600         } else
3601                 link->wa_flags.dp_keep_receiver_powered = false;
3602 }
3603
3604 /* Read additional sink caps defined in source specific DPCD area
3605  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3606  */
3607 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3608 {
3609         uint8_t dpcd_data;
3610
3611         if (!link)
3612                 return false;
3613
3614         if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3615                 return false;
3616
3617         link->dpcd_sink_ext_caps.raw = dpcd_data;
3618         return true;
3619 }
3620
3621 bool dp_retrieve_lttpr_cap(struct dc_link *link)
3622 {
3623         uint8_t lttpr_dpcd_data[6];
3624         bool vbios_lttpr_enable = false;
3625         bool vbios_lttpr_interop = false;
3626         struct dc_bios *bios = link->dc->ctx->dc_bios;
3627         enum dc_status status = DC_ERROR_UNEXPECTED;
3628         bool is_lttpr_present = false;
3629
3630         memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3631         /* Query BIOS to determine if LTTPR functionality is forced on by system */
3632         if (bios->funcs->get_lttpr_caps) {
3633                 enum bp_result bp_query_result;
3634                 uint8_t is_vbios_lttpr_enable = 0;
3635
3636                 bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable);
3637                 vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
3638         }
3639
3640         if (bios->funcs->get_lttpr_interop) {
3641                 enum bp_result bp_query_result;
3642                 uint8_t is_vbios_interop_enabled = 0;
3643
3644                 bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled);
3645                 vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
3646         }
3647
3648         /*
3649          * Logic to determine LTTPR mode
3650          */
3651         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3652         if (vbios_lttpr_enable && vbios_lttpr_interop)
3653                 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3654         else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3655                 if (link->dc->config.allow_lttpr_non_transparent_mode)
3656                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3657                 else
3658                         link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3659         } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3660                 if (!link->dc->config.allow_lttpr_non_transparent_mode
3661                         || !link->dc->caps.extended_aux_timeout_support)
3662                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3663                 else
3664                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3665         }
3666
3667         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
3668                 /* By reading LTTPR capability, RX assumes that we will enable
3669                  * LTTPR extended aux timeout if LTTPR is present.
3670                  */
3671                 status = core_link_read_dpcd(
3672                                 link,
3673                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3674                                 lttpr_dpcd_data,
3675                                 sizeof(lttpr_dpcd_data));
3676
3677                 link->dpcd_caps.lttpr_caps.revision.raw =
3678                                 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3679                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3680
3681                 link->dpcd_caps.lttpr_caps.max_link_rate =
3682                                 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3683                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3684
3685                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3686                                 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3687                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3688
3689                 link->dpcd_caps.lttpr_caps.max_lane_count =
3690                                 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3691                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3692
3693                 link->dpcd_caps.lttpr_caps.mode =
3694                                 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3695                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3696
3697                 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3698                                 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3699                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3700
3701                 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
3702                 is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3703                                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt < 0xff &&
3704                                 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3705                                 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3706                                 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3707                 if (is_lttpr_present) {
3708                         CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3709                         configure_lttpr_mode_transparent(link);
3710                 } else
3711                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3712         }
3713         return is_lttpr_present;
3714 }
3715
3716 static bool retrieve_link_cap(struct dc_link *link)
3717 {
3718         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3719          * which means size 16 will be good for both of those DPCD register block reads
3720          */
3721         uint8_t dpcd_data[16];
3722         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3723          */
3724         uint8_t dpcd_dprx_data = '\0';
3725         uint8_t dpcd_power_state = '\0';
3726
3727         struct dp_device_vendor_id sink_id;
3728         union down_stream_port_count down_strm_port_count;
3729         union edp_configuration_cap edp_config_cap;
3730         union dp_downstream_port_present ds_port = { 0 };
3731         enum dc_status status = DC_ERROR_UNEXPECTED;
3732         uint32_t read_dpcd_retry_cnt = 3;
3733         int i;
3734         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3735         const uint32_t post_oui_delay = 30; // 30ms
3736         bool is_lttpr_present = false;
3737
3738         memset(dpcd_data, '\0', sizeof(dpcd_data));
3739         memset(&down_strm_port_count,
3740                 '\0', sizeof(union down_stream_port_count));
3741         memset(&edp_config_cap, '\0',
3742                 sizeof(union edp_configuration_cap));
3743
3744         /* if extended timeout is supported in hardware,
3745          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3746          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3747          */
3748         dc_link_aux_try_to_configure_timeout(link->ddc,
3749                         LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3750
3751         is_lttpr_present = dp_retrieve_lttpr_cap(link);
3752         if (!is_lttpr_present)
3753                 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3754
3755
3756         status = core_link_read_dpcd(link, DP_SET_POWER,
3757                         &dpcd_power_state, sizeof(dpcd_power_state));
3758
3759         /* Delay 1 ms if AUX CH is in power down state. Based on spec
3760          * section 2.3.1.2, if AUX CH may be powered down due to
3761          * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3762          * signal and may need up to 1 ms before being able to reply.
3763          */
3764         if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3765                 udelay(1000);
3766
3767         dpcd_set_source_specific_data(link);
3768         /* Sink may need to configure internals based on vendor, so allow some
3769          * time before proceeding with possibly vendor specific transactions
3770          */
3771         msleep(post_oui_delay);
3772
3773         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3774                 status = core_link_read_dpcd(
3775                                 link,
3776                                 DP_DPCD_REV,
3777                                 dpcd_data,
3778                                 sizeof(dpcd_data));
3779                 if (status == DC_OK)
3780                         break;
3781         }
3782
3783
3784         if (status != DC_OK) {
3785                 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
3786                 return false;
3787         }
3788
3789         {
3790                 union training_aux_rd_interval aux_rd_interval;
3791
3792                 aux_rd_interval.raw =
3793                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3794
3795                 link->dpcd_caps.ext_receiver_cap_field_present =
3796                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3797
3798                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3799                         uint8_t ext_cap_data[16];
3800
3801                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3802                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3803                                 status = core_link_read_dpcd(
3804                                 link,
3805                                 DP_DP13_DPCD_REV,
3806                                 ext_cap_data,
3807                                 sizeof(ext_cap_data));
3808                                 if (status == DC_OK) {
3809                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3810                                         break;
3811                                 }
3812                         }
3813                         if (status != DC_OK)
3814                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3815                 }
3816         }
3817
3818         link->dpcd_caps.dpcd_rev.raw =
3819                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3820
3821         if (link->dpcd_caps.ext_receiver_cap_field_present) {
3822                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3823                         status = core_link_read_dpcd(
3824                                         link,
3825                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3826                                         &dpcd_dprx_data,
3827                                         sizeof(dpcd_dprx_data));
3828                         if (status == DC_OK)
3829                                 break;
3830                 }
3831
3832                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3833
3834                 if (status != DC_OK)
3835                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
3836         }
3837
3838         else {
3839                 link->dpcd_caps.dprx_feature.raw = 0;
3840         }
3841
3842
3843         /* Error condition checking...
3844          * It is impossible for Sink to report Max Lane Count = 0.
3845          * It is possible for Sink to report Max Link Rate = 0, if it is
3846          * an eDP device that is reporting specialized link rates in the
3847          * SUPPORTED_LINK_RATE table.
3848          */
3849         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3850                 return false;
3851
3852         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3853                                  DP_DPCD_REV];
3854
3855         read_dp_device_vendor_id(link);
3856
3857         get_active_converter_info(ds_port.byte, link);
3858
3859         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3860
3861         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3862                                  DP_DPCD_REV];
3863
3864         link->dpcd_caps.allow_invalid_MSA_timing_param =
3865                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3866
3867         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3868                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3869
3870         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3871                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3872
3873         link->reported_link_cap.lane_count =
3874                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3875         link->reported_link_cap.link_rate = dpcd_data[
3876                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3877         link->reported_link_cap.link_spread =
3878                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3879                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3880
3881         edp_config_cap.raw = dpcd_data[
3882                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3883         link->dpcd_caps.panel_mode_edp =
3884                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3885         link->dpcd_caps.dpcd_display_control_capable =
3886                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3887
3888         link->test_pattern_enabled = false;
3889         link->compliance_test_state.raw = 0;
3890
3891         /* read sink count */
3892         core_link_read_dpcd(link,
3893                         DP_SINK_COUNT,
3894                         &link->dpcd_caps.sink_count.raw,
3895                         sizeof(link->dpcd_caps.sink_count.raw));
3896
3897         /* read sink ieee oui */
3898         core_link_read_dpcd(link,
3899                         DP_SINK_OUI,
3900                         (uint8_t *)(&sink_id),
3901                         sizeof(sink_id));
3902
3903         link->dpcd_caps.sink_dev_id =
3904                         (sink_id.ieee_oui[0] << 16) +
3905                         (sink_id.ieee_oui[1] << 8) +
3906                         (sink_id.ieee_oui[2]);
3907
3908         memmove(
3909                 link->dpcd_caps.sink_dev_id_str,
3910                 sink_id.ieee_device_id,
3911                 sizeof(sink_id.ieee_device_id));
3912
3913         /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3914         {
3915                 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3916
3917                 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3918                     !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3919                             sizeof(str_mbp_2017))) {
3920                         link->reported_link_cap.link_rate = 0x0c;
3921                 }
3922         }
3923
3924         core_link_read_dpcd(
3925                 link,
3926                 DP_SINK_HW_REVISION_START,
3927                 (uint8_t *)&dp_hw_fw_revision,
3928                 sizeof(dp_hw_fw_revision));
3929
3930         link->dpcd_caps.sink_hw_revision =
3931                 dp_hw_fw_revision.ieee_hw_rev;
3932
3933         memmove(
3934                 link->dpcd_caps.sink_fw_revision,
3935                 dp_hw_fw_revision.ieee_fw_rev,
3936                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3937
3938         memset(&link->dpcd_caps.dsc_caps, '\0',
3939                         sizeof(link->dpcd_caps.dsc_caps));
3940         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3941         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3942         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3943                 status = core_link_read_dpcd(
3944                                 link,
3945                                 DP_FEC_CAPABILITY,
3946                                 &link->dpcd_caps.fec_cap.raw,
3947                                 sizeof(link->dpcd_caps.fec_cap.raw));
3948                 status = core_link_read_dpcd(
3949                                 link,
3950                                 DP_DSC_SUPPORT,
3951                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3952                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3953                 status = core_link_read_dpcd(
3954                                 link,
3955                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3956                                 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3957                                 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3958         }
3959
3960         if (!dpcd_read_sink_ext_caps(link))
3961                 link->dpcd_sink_ext_caps.raw = 0;
3962
3963         /* Connectivity log: detection */
3964         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3965
3966         return true;
3967 }
3968
3969 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3970 {
3971         uint8_t dpcd_data[16];
3972         uint32_t read_dpcd_retry_cnt = 3;
3973         enum dc_status status = DC_ERROR_UNEXPECTED;
3974         union dp_downstream_port_present ds_port = { 0 };
3975         union down_stream_port_count down_strm_port_count;
3976         union edp_configuration_cap edp_config_cap;
3977
3978         int i;
3979
3980         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3981                 status = core_link_read_dpcd(
3982                                 link,
3983                                 DP_DPCD_REV,
3984                                 dpcd_data,
3985                                 sizeof(dpcd_data));
3986                 if (status == DC_OK)
3987                         break;
3988         }
3989
3990         link->dpcd_caps.dpcd_rev.raw =
3991                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3992
3993         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3994                 return false;
3995
3996         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3997                         DP_DPCD_REV];
3998
3999         get_active_converter_info(ds_port.byte, link);
4000
4001         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
4002                         DP_DPCD_REV];
4003
4004         link->dpcd_caps.allow_invalid_MSA_timing_param =
4005                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
4006
4007         link->dpcd_caps.max_ln_count.raw = dpcd_data[
4008                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
4009
4010         link->dpcd_caps.max_down_spread.raw = dpcd_data[
4011                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
4012
4013         link->reported_link_cap.lane_count =
4014                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
4015         link->reported_link_cap.link_rate = dpcd_data[
4016                 DP_MAX_LINK_RATE - DP_DPCD_REV];
4017         link->reported_link_cap.link_spread =
4018                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
4019                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
4020
4021         edp_config_cap.raw = dpcd_data[
4022                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4023         link->dpcd_caps.panel_mode_edp =
4024                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
4025         link->dpcd_caps.dpcd_display_control_capable =
4026                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4027
4028         return true;
4029 }
4030
4031 bool detect_dp_sink_caps(struct dc_link *link)
4032 {
4033         return retrieve_link_cap(link);
4034
4035         /* dc init_hw has power encoder using default
4036          * signal for connector. For native DP, no
4037          * need to power up encoder again. If not native
4038          * DP, hw_init may need check signal or power up
4039          * encoder here.
4040          */
4041         /* TODO save sink caps in link->sink */
4042 }
4043
4044 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
4045 {
4046         enum dc_link_rate link_rate;
4047         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
4048         switch (link_rate_in_khz) {
4049         case 1620000:
4050                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
4051                 break;
4052         case 2160000:
4053                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
4054                 break;
4055         case 2430000:
4056                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
4057                 break;
4058         case 2700000:
4059                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
4060                 break;
4061         case 3240000:
4062                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
4063                 break;
4064         case 4320000:
4065                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
4066                 break;
4067         case 5400000:
4068                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
4069                 break;
4070         case 8100000:
4071                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
4072                 break;
4073         default:
4074                 link_rate = LINK_RATE_UNKNOWN;
4075                 break;
4076         }
4077         return link_rate;
4078 }
4079
4080 void detect_edp_sink_caps(struct dc_link *link)
4081 {
4082         uint8_t supported_link_rates[16];
4083         uint32_t entry;
4084         uint32_t link_rate_in_khz;
4085         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
4086         uint8_t backlight_adj_cap;
4087
4088         retrieve_link_cap(link);
4089         link->dpcd_caps.edp_supported_link_rates_count = 0;
4090         memset(supported_link_rates, 0, sizeof(supported_link_rates));
4091
4092         /*
4093          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
4094          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
4095          */
4096         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
4097                         (link->dc->debug.optimize_edp_link_rate ||
4098                         link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
4099                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
4100                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
4101                                                         supported_link_rates, sizeof(supported_link_rates));
4102
4103                 for (entry = 0; entry < 16; entry += 2) {
4104                         // DPCD register reports per-lane link rate = 16-bit link rate capability
4105                         // value X 200 kHz. Need multiplier to find link rate in kHz.
4106                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
4107                                                                                 supported_link_rates[entry]) * 200;
4108
4109                         if (link_rate_in_khz != 0) {
4110                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
4111                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
4112                                 link->dpcd_caps.edp_supported_link_rates_count++;
4113
4114                                 if (link->reported_link_cap.link_rate < link_rate)
4115                                         link->reported_link_cap.link_rate = link_rate;
4116                         }
4117                 }
4118         }
4119         link->verified_link_cap = link->reported_link_cap;
4120
4121         core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
4122                                                 &backlight_adj_cap, sizeof(backlight_adj_cap));
4123
4124         link->dpcd_caps.dynamic_backlight_capable_edp =
4125                                 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
4126
4127         dc_link_set_default_brightness_aux(link);
4128 }
4129
4130 void dc_link_dp_enable_hpd(const struct dc_link *link)
4131 {
4132         struct link_encoder *encoder = link->link_enc;
4133
4134         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4135                 encoder->funcs->enable_hpd(encoder);
4136 }
4137
4138 void dc_link_dp_disable_hpd(const struct dc_link *link)
4139 {
4140         struct link_encoder *encoder = link->link_enc;
4141
4142         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4143                 encoder->funcs->disable_hpd(encoder);
4144 }
4145
4146 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
4147 {
4148         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
4149                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
4150                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4151                 return true;
4152         else
4153                 return false;
4154 }
4155
4156 static void set_crtc_test_pattern(struct dc_link *link,
4157                                 struct pipe_ctx *pipe_ctx,
4158                                 enum dp_test_pattern test_pattern,
4159                                 enum dp_test_pattern_color_space test_pattern_color_space)
4160 {
4161         enum controller_dp_test_pattern controller_test_pattern;
4162         enum dc_color_depth color_depth = pipe_ctx->
4163                 stream->timing.display_color_depth;
4164         struct bit_depth_reduction_params params;
4165         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
4166         int width = pipe_ctx->stream->timing.h_addressable +
4167                 pipe_ctx->stream->timing.h_border_left +
4168                 pipe_ctx->stream->timing.h_border_right;
4169         int height = pipe_ctx->stream->timing.v_addressable +
4170                 pipe_ctx->stream->timing.v_border_bottom +
4171                 pipe_ctx->stream->timing.v_border_top;
4172
4173         memset(&params, 0, sizeof(params));
4174
4175         switch (test_pattern) {
4176         case DP_TEST_PATTERN_COLOR_SQUARES:
4177                 controller_test_pattern =
4178                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
4179         break;
4180         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4181                 controller_test_pattern =
4182                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
4183         break;
4184         case DP_TEST_PATTERN_VERTICAL_BARS:
4185                 controller_test_pattern =
4186                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
4187         break;
4188         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4189                 controller_test_pattern =
4190                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
4191         break;
4192         case DP_TEST_PATTERN_COLOR_RAMP:
4193                 controller_test_pattern =
4194                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
4195         break;
4196         default:
4197                 controller_test_pattern =
4198                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
4199         break;
4200         }
4201
4202         switch (test_pattern) {
4203         case DP_TEST_PATTERN_COLOR_SQUARES:
4204         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4205         case DP_TEST_PATTERN_VERTICAL_BARS:
4206         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4207         case DP_TEST_PATTERN_COLOR_RAMP:
4208         {
4209                 /* disable bit depth reduction */
4210                 pipe_ctx->stream->bit_depth_params = params;
4211                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4212                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4213                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4214                                 controller_test_pattern, color_depth);
4215                 else if (link->dc->hwss.set_disp_pattern_generator) {
4216                         struct pipe_ctx *odm_pipe;
4217                         enum controller_dp_color_space controller_color_space;
4218                         int opp_cnt = 1;
4219                         int offset = 0;
4220                         int dpg_width = width;
4221
4222                         switch (test_pattern_color_space) {
4223                         case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4224                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4225                                 break;
4226                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4227                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4228                                 break;
4229                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4230                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4231                                 break;
4232                         case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4233                         default:
4234                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4235                                 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4236                                 ASSERT(0);
4237                                 break;
4238                         }
4239
4240                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4241                                 opp_cnt++;
4242                         dpg_width = width / opp_cnt;
4243                         offset = dpg_width;
4244
4245                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4246                                         pipe_ctx,
4247                                         controller_test_pattern,
4248                                         controller_color_space,
4249                                         color_depth,
4250                                         NULL,
4251                                         dpg_width,
4252                                         height,
4253                                         0);
4254
4255                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4256                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4257
4258                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4259                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4260                                                 odm_pipe,
4261                                                 controller_test_pattern,
4262                                                 controller_color_space,
4263                                                 color_depth,
4264                                                 NULL,
4265                                                 dpg_width,
4266                                                 height,
4267                                                 offset);
4268                                 offset += offset;
4269                         }
4270                 }
4271         }
4272         break;
4273         case DP_TEST_PATTERN_VIDEO_MODE:
4274         {
4275                 /* restore bitdepth reduction */
4276                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4277                 pipe_ctx->stream->bit_depth_params = params;
4278                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4279                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4280                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4281                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4282                                 color_depth);
4283                 else if (link->dc->hwss.set_disp_pattern_generator) {
4284                         struct pipe_ctx *odm_pipe;
4285                         int opp_cnt = 1;
4286                         int dpg_width = width;
4287
4288                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4289                                 opp_cnt++;
4290
4291                         dpg_width = width / opp_cnt;
4292                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4293                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4294
4295                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4296                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4297                                                 odm_pipe,
4298                                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4299                                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4300                                                 color_depth,
4301                                                 NULL,
4302                                                 dpg_width,
4303                                                 height,
4304                                                 0);
4305                         }
4306                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4307                                         pipe_ctx,
4308                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4309                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4310                                         color_depth,
4311                                         NULL,
4312                                         dpg_width,
4313                                         height,
4314                                         0);
4315                 }
4316         }
4317         break;
4318
4319         default:
4320         break;
4321         }
4322 }
4323
4324 bool dc_link_dp_set_test_pattern(
4325         struct dc_link *link,
4326         enum dp_test_pattern test_pattern,
4327         enum dp_test_pattern_color_space test_pattern_color_space,
4328         const struct link_training_settings *p_link_settings,
4329         const unsigned char *p_custom_pattern,
4330         unsigned int cust_pattern_size)
4331 {
4332         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4333         struct pipe_ctx *pipe_ctx = NULL;
4334         unsigned int lane;
4335         unsigned int i;
4336         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4337         union dpcd_training_pattern training_pattern;
4338         enum dpcd_phy_test_patterns pattern;
4339
4340         memset(&training_pattern, 0, sizeof(training_pattern));
4341
4342         for (i = 0; i < MAX_PIPES; i++) {
4343                 if (pipes[i].stream == NULL)
4344                         continue;
4345
4346                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4347                         pipe_ctx = &pipes[i];
4348                         break;
4349                 }
4350         }
4351
4352         if (pipe_ctx == NULL)
4353                 return false;
4354
4355         /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4356         if (link->test_pattern_enabled && test_pattern ==
4357                         DP_TEST_PATTERN_VIDEO_MODE) {
4358                 /* Set CRTC Test Pattern */
4359                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4360                 dp_set_hw_test_pattern(link, test_pattern,
4361                                 (uint8_t *)p_custom_pattern,
4362                                 (uint32_t)cust_pattern_size);
4363
4364                 /* Unblank Stream */
4365                 link->dc->hwss.unblank_stream(
4366                         pipe_ctx,
4367                         &link->verified_link_cap);
4368                 /* TODO:m_pHwss->MuteAudioEndpoint
4369                  * (pPathMode->pDisplayPath, false);
4370                  */
4371
4372                 /* Reset Test Pattern state */
4373                 link->test_pattern_enabled = false;
4374
4375                 return true;
4376         }
4377
4378         /* Check for PHY Test Patterns */
4379         if (is_dp_phy_pattern(test_pattern)) {
4380                 /* Set DPCD Lane Settings before running test pattern */
4381                 if (p_link_settings != NULL) {
4382                         dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4383                         dpcd_set_lane_settings(link, p_link_settings, DPRX);
4384                 }
4385
4386                 /* Blank stream if running test pattern */
4387                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4388                         /*TODO:
4389                          * m_pHwss->
4390                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4391                          */
4392                         /* Blank stream */
4393                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4394                 }
4395
4396                 dp_set_hw_test_pattern(link, test_pattern,
4397                                 (uint8_t *)p_custom_pattern,
4398                                 (uint32_t)cust_pattern_size);
4399
4400                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4401                         /* Set Test Pattern state */
4402                         link->test_pattern_enabled = true;
4403                         if (p_link_settings != NULL)
4404                                 dpcd_set_link_settings(link,
4405                                                 p_link_settings);
4406                 }
4407
4408                 switch (test_pattern) {
4409                 case DP_TEST_PATTERN_VIDEO_MODE:
4410                         pattern = PHY_TEST_PATTERN_NONE;
4411                         break;
4412                 case DP_TEST_PATTERN_D102:
4413                         pattern = PHY_TEST_PATTERN_D10_2;
4414                         break;
4415                 case DP_TEST_PATTERN_SYMBOL_ERROR:
4416                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4417                         break;
4418                 case DP_TEST_PATTERN_PRBS7:
4419                         pattern = PHY_TEST_PATTERN_PRBS7;
4420                         break;
4421                 case DP_TEST_PATTERN_80BIT_CUSTOM:
4422                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4423                         break;
4424                 case DP_TEST_PATTERN_CP2520_1:
4425                         pattern = PHY_TEST_PATTERN_CP2520_1;
4426                         break;
4427                 case DP_TEST_PATTERN_CP2520_2:
4428                         pattern = PHY_TEST_PATTERN_CP2520_2;
4429                         break;
4430                 case DP_TEST_PATTERN_CP2520_3:
4431                         pattern = PHY_TEST_PATTERN_CP2520_3;
4432                         break;
4433                 default:
4434                         return false;
4435                 }
4436
4437                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4438                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4439                         return false;
4440
4441                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4442                         /* tell receiver that we are sending qualification
4443                          * pattern DP 1.2 or later - DP receiver's link quality
4444                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
4445                          * register (0x10B~0x10E)\
4446                          */
4447                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4448                                 link_qual_pattern[lane] =
4449                                                 (unsigned char)(pattern);
4450
4451                         core_link_write_dpcd(link,
4452                                         DP_LINK_QUAL_LANE0_SET,
4453                                         link_qual_pattern,
4454                                         sizeof(link_qual_pattern));
4455                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4456                            link->dpcd_caps.dpcd_rev.raw == 0) {
4457                         /* tell receiver that we are sending qualification
4458                          * pattern DP 1.1a or earlier - DP receiver's link
4459                          * quality pattern is set using
4460                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4461                          * register (0x102). We will use v_1.3 when we are
4462                          * setting test pattern for DP 1.1.
4463                          */
4464                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4465                                             &training_pattern.raw,
4466                                             sizeof(training_pattern));
4467                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4468                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4469                                              &training_pattern.raw,
4470                                              sizeof(training_pattern));
4471                 }
4472         } else {
4473                 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4474
4475                 switch (test_pattern_color_space) {
4476                 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4477                         color_space = COLOR_SPACE_SRGB;
4478                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4479                                 color_space = COLOR_SPACE_SRGB_LIMITED;
4480                         break;
4481
4482                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4483                         color_space = COLOR_SPACE_YCBCR601;
4484                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4485                                 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4486                         break;
4487                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4488                         color_space = COLOR_SPACE_YCBCR709;
4489                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4490                                 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4491                         break;
4492                 default:
4493                         break;
4494                 }
4495
4496                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4497                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4498                                 union dmub_hw_lock_flags hw_locks = { 0 };
4499                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4500
4501                                 hw_locks.bits.lock_dig = 1;
4502                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4503
4504                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4505                                                         true,
4506                                                         &hw_locks,
4507                                                         &inst_flags);
4508                         } else
4509                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4510                                                 pipe_ctx->stream_res.tg);
4511                 }
4512
4513                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4514                 /* update MSA to requested color space */
4515                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4516                                 &pipe_ctx->stream->timing,
4517                                 color_space,
4518                                 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4519                                 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4520
4521                 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4522                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4523                                 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4524                         else
4525                                 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4526                         resource_build_info_frame(pipe_ctx);
4527                         link->dc->hwss.update_info_frame(pipe_ctx);
4528                 }
4529
4530                 /* CRTC Patterns */
4531                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4532                 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4533                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4534                                 CRTC_STATE_VACTIVE);
4535                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4536                                 CRTC_STATE_VBLANK);
4537                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4538                                 CRTC_STATE_VACTIVE);
4539
4540                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4541                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4542                                 union dmub_hw_lock_flags hw_locks = { 0 };
4543                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4544
4545                                 hw_locks.bits.lock_dig = 1;
4546                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4547
4548                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4549                                                         false,
4550                                                         &hw_locks,
4551                                                         &inst_flags);
4552                         } else
4553                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4554                                                 pipe_ctx->stream_res.tg);
4555                 }
4556
4557                 /* Set Test Pattern state */
4558                 link->test_pattern_enabled = true;
4559         }
4560
4561         return true;
4562 }
4563
4564 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4565 {
4566         unsigned char mstmCntl;
4567
4568         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4569         if (enable)
4570                 mstmCntl |= DP_MST_EN;
4571         else
4572                 mstmCntl &= (~DP_MST_EN);
4573
4574         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4575 }
4576
4577 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4578 {
4579         union dpcd_edp_config edp_config_set;
4580         bool panel_mode_edp = false;
4581
4582         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4583
4584         if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4585
4586                 switch (panel_mode) {
4587                 case DP_PANEL_MODE_EDP:
4588                 case DP_PANEL_MODE_SPECIAL:
4589                         panel_mode_edp = true;
4590                         break;
4591
4592                 default:
4593                                 break;
4594                 }
4595
4596                 /*set edp panel mode in receiver*/
4597                 core_link_read_dpcd(
4598                         link,
4599                         DP_EDP_CONFIGURATION_SET,
4600                         &edp_config_set.raw,
4601                         sizeof(edp_config_set.raw));
4602
4603                 if (edp_config_set.bits.PANEL_MODE_EDP
4604                         != panel_mode_edp) {
4605                         enum dc_status result;
4606
4607                         edp_config_set.bits.PANEL_MODE_EDP =
4608                         panel_mode_edp;
4609                         result = core_link_write_dpcd(
4610                                 link,
4611                                 DP_EDP_CONFIGURATION_SET,
4612                                 &edp_config_set.raw,
4613                                 sizeof(edp_config_set.raw));
4614
4615                         ASSERT(result == DC_OK);
4616                 }
4617         }
4618         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4619                  "eDP panel mode enabled: %d \n",
4620                  link->link_index,
4621                  link->dpcd_caps.panel_mode_edp,
4622                  panel_mode_edp);
4623 }
4624
4625 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4626 {
4627         /* We need to explicitly check that connector
4628          * is not DP. Some Travis_VGA get reported
4629          * by video bios as DP.
4630          */
4631         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4632
4633                 switch (link->dpcd_caps.branch_dev_id) {
4634                 case DP_BRANCH_DEVICE_ID_0022B9:
4635                         /* alternate scrambler reset is required for Travis
4636                          * for the case when external chip does not
4637                          * provide sink device id, alternate scrambler
4638                          * scheme will  be overriden later by querying
4639                          * Encoder features
4640                          */
4641                         if (strncmp(
4642                                 link->dpcd_caps.branch_dev_name,
4643                                 DP_VGA_LVDS_CONVERTER_ID_2,
4644                                 sizeof(
4645                                 link->dpcd_caps.
4646                                 branch_dev_name)) == 0) {
4647                                         return DP_PANEL_MODE_SPECIAL;
4648                         }
4649                         break;
4650                 case DP_BRANCH_DEVICE_ID_00001A:
4651                         /* alternate scrambler reset is required for Travis
4652                          * for the case when external chip does not provide
4653                          * sink device id, alternate scrambler scheme will
4654                          * be overriden later by querying Encoder feature
4655                          */
4656                         if (strncmp(link->dpcd_caps.branch_dev_name,
4657                                 DP_VGA_LVDS_CONVERTER_ID_3,
4658                                 sizeof(
4659                                 link->dpcd_caps.
4660                                 branch_dev_name)) == 0) {
4661                                         return DP_PANEL_MODE_SPECIAL;
4662                         }
4663                         break;
4664                 default:
4665                         break;
4666                 }
4667         }
4668
4669         if (link->dpcd_caps.panel_mode_edp) {
4670                 return DP_PANEL_MODE_EDP;
4671         }
4672
4673         return DP_PANEL_MODE_DEFAULT;
4674 }
4675
4676 enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
4677 {
4678         /* FEC has to be "set ready" before the link training.
4679          * The policy is to always train with FEC
4680          * if the sink supports it and leave it enabled on link.
4681          * If FEC is not supported, disable it.
4682          */
4683         struct link_encoder *link_enc = NULL;
4684         enum dc_status status = DC_OK;
4685         uint8_t fec_config = 0;
4686
4687         /* Access link encoder based on whether it is statically
4688          * or dynamically assigned to a link.
4689          */
4690         if (link->is_dig_mapping_flexible &&
4691                         link->dc->res_pool->funcs->link_encs_assign)
4692                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
4693         else
4694                 link_enc = link->link_enc;
4695         ASSERT(link_enc);
4696
4697         if (!dc_link_should_enable_fec(link))
4698                 return status;
4699
4700         if (link_enc->funcs->fec_set_ready &&
4701                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4702                 if (ready) {
4703                         fec_config = 1;
4704                         status = core_link_write_dpcd(link,
4705                                         DP_FEC_CONFIGURATION,
4706                                         &fec_config,
4707                                         sizeof(fec_config));
4708                         if (status == DC_OK) {
4709                                 link_enc->funcs->fec_set_ready(link_enc, true);
4710                                 link->fec_state = dc_link_fec_ready;
4711                         } else {
4712                                 link_enc->funcs->fec_set_ready(link->link_enc, false);
4713                                 link->fec_state = dc_link_fec_not_ready;
4714                                 dm_error("dpcd write failed to set fec_ready");
4715                         }
4716                 } else if (link->fec_state == dc_link_fec_ready) {
4717                         fec_config = 0;
4718                         status = core_link_write_dpcd(link,
4719                                         DP_FEC_CONFIGURATION,
4720                                         &fec_config,
4721                                         sizeof(fec_config));
4722                         link_enc->funcs->fec_set_ready(link_enc, false);
4723                         link->fec_state = dc_link_fec_not_ready;
4724                 }
4725         }
4726
4727         return status;
4728 }
4729
4730 void dp_set_fec_enable(struct dc_link *link, bool enable)
4731 {
4732         struct link_encoder *link_enc = NULL;
4733
4734         /* Access link encoder based on whether it is statically
4735          * or dynamically assigned to a link.
4736          */
4737         if (link->is_dig_mapping_flexible &&
4738                         link->dc->res_pool->funcs->link_encs_assign)
4739                 link_enc = link_enc_cfg_get_link_enc_used_by_link(
4740                                 link->dc->current_state, link);
4741         else
4742                 link_enc = link->link_enc;
4743         ASSERT(link_enc);
4744
4745         if (!dc_link_should_enable_fec(link))
4746                 return;
4747
4748         if (link_enc->funcs->fec_set_enable &&
4749                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4750                 if (link->fec_state == dc_link_fec_ready && enable) {
4751                         /* Accord to DP spec, FEC enable sequence can first
4752                          * be transmitted anytime after 1000 LL codes have
4753                          * been transmitted on the link after link training
4754                          * completion. Using 1 lane RBR should have the maximum
4755                          * time for transmitting 1000 LL codes which is 6.173 us.
4756                          * So use 7 microseconds delay instead.
4757                          */
4758                         udelay(7);
4759                         link_enc->funcs->fec_set_enable(link_enc, true);
4760                         link->fec_state = dc_link_fec_enabled;
4761                 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4762                         link_enc->funcs->fec_set_enable(link_enc, false);
4763                         link->fec_state = dc_link_fec_ready;
4764                 }
4765         }
4766 }
4767
4768 void dpcd_set_source_specific_data(struct dc_link *link)
4769 {
4770         if (!link->dc->vendor_signature.is_valid) {
4771                 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
4772                 struct dpcd_amd_signature amd_signature = {0};
4773                 struct dpcd_amd_device_id amd_device_id = {0};
4774
4775                 amd_device_id.device_id_byte1 =
4776                                 (uint8_t)(link->ctx->asic_id.chip_id);
4777                 amd_device_id.device_id_byte2 =
4778                                 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4779                 amd_device_id.dce_version =
4780                                 (uint8_t)(link->ctx->dce_version);
4781                 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4782                 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4783
4784                 core_link_read_dpcd(link, DP_SOURCE_OUI,
4785                                 (uint8_t *)(&amd_signature),
4786                                 sizeof(amd_signature));
4787
4788                 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4789                         (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4790                         (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4791
4792                         amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4793                         amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4794                         amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4795
4796                         core_link_write_dpcd(link, DP_SOURCE_OUI,
4797                                 (uint8_t *)(&amd_signature),
4798                                 sizeof(amd_signature));
4799                 }
4800
4801                 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4802                                 (uint8_t *)(&amd_device_id),
4803                                 sizeof(amd_device_id));
4804
4805                 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4806                         link->dc->caps.min_horizontal_blanking_period != 0) {
4807
4808                         uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4809
4810                         result_write_min_hblank = core_link_write_dpcd(link,
4811                                 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4812                                 sizeof(hblank_size));
4813                 }
4814                 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4815                                                         WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4816                                                         "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4817                                                         result_write_min_hblank,
4818                                                         link->link_index,
4819                                                         link->ctx->dce_version,
4820                                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4821                                                         link->dc->caps.min_horizontal_blanking_period,
4822                                                         link->dpcd_caps.branch_dev_id,
4823                                                         link->dpcd_caps.branch_dev_name[0],
4824                                                         link->dpcd_caps.branch_dev_name[1],
4825                                                         link->dpcd_caps.branch_dev_name[2],
4826                                                         link->dpcd_caps.branch_dev_name[3],
4827                                                         link->dpcd_caps.branch_dev_name[4],
4828                                                         link->dpcd_caps.branch_dev_name[5]);
4829         } else {
4830                 core_link_write_dpcd(link, DP_SOURCE_OUI,
4831                                 link->dc->vendor_signature.data.raw,
4832                                 sizeof(link->dc->vendor_signature.data.raw));
4833         }
4834 }
4835
4836 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4837                 bool isHDR,
4838                 uint32_t backlight_millinits,
4839                 uint32_t transition_time_in_ms)
4840 {
4841         struct dpcd_source_backlight_set dpcd_backlight_set;
4842         uint8_t backlight_control = isHDR ? 1 : 0;
4843
4844         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4845                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4846                 return false;
4847
4848         // OLEDs have no PWM, they can only use AUX
4849         if (link->dpcd_sink_ext_caps.bits.oled == 1)
4850                 backlight_control = 1;
4851
4852         *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4853         *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4854
4855
4856         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4857                         (uint8_t *)(&dpcd_backlight_set),
4858                         sizeof(dpcd_backlight_set)) != DC_OK)
4859                 return false;
4860
4861         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4862                         &backlight_control, 1) != DC_OK)
4863                 return false;
4864
4865         return true;
4866 }
4867
4868 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4869                 uint32_t *backlight_millinits_avg,
4870                 uint32_t *backlight_millinits_peak)
4871 {
4872         union dpcd_source_backlight_get dpcd_backlight_get;
4873
4874         memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4875
4876         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4877                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4878                 return false;
4879
4880         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4881                         dpcd_backlight_get.raw,
4882                         sizeof(union dpcd_source_backlight_get)) != DC_OK)
4883                 return false;
4884
4885         *backlight_millinits_avg =
4886                 dpcd_backlight_get.bytes.backlight_millinits_avg;
4887         *backlight_millinits_peak =
4888                 dpcd_backlight_get.bytes.backlight_millinits_peak;
4889
4890         /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4891         if (*backlight_millinits_avg == 0 ||
4892                         *backlight_millinits_avg > *backlight_millinits_peak)
4893                 return false;
4894
4895         return true;
4896 }
4897
4898 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4899 {
4900         uint8_t backlight_enable = enable ? 1 : 0;
4901
4902         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4903                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4904                 return false;
4905
4906         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4907                 &backlight_enable, 1) != DC_OK)
4908                 return false;
4909
4910         return true;
4911 }
4912
4913 // we read default from 0x320 because we expect BIOS wrote it there
4914 // regular get_backlight_nit reads from panel set at 0x326
4915 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4916 {
4917         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4918                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4919                 return false;
4920
4921         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4922                 (uint8_t *) backlight_millinits,
4923                 sizeof(uint32_t)) != DC_OK)
4924                 return false;
4925
4926         return true;
4927 }
4928
4929 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4930 {
4931         uint32_t default_backlight;
4932
4933         if (link &&
4934                 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4935                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4936                 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4937                         default_backlight = 150000;
4938                 // if < 5 nits or > 5000, it might be wrong readback
4939                 if (default_backlight < 5000 || default_backlight > 5000000)
4940                         default_backlight = 150000; //
4941
4942                 return dc_link_set_backlight_level_nits(link, true,
4943                                 default_backlight, 0);
4944         }
4945         return false;
4946 }
4947
4948 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4949 {
4950         struct dc_link_settings link_setting;
4951         uint8_t link_bw_set;
4952         uint8_t link_rate_set;
4953         uint32_t req_bw;
4954         union lane_count_set lane_count_set = { {0} };
4955
4956         ASSERT(link || crtc_timing); // invalid input
4957
4958         if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4959                         !link->dc->debug.optimize_edp_link_rate)
4960                 return false;
4961
4962
4963         // Read DPCD 00100h to find if standard link rates are set
4964         core_link_read_dpcd(link, DP_LINK_BW_SET,
4965                                 &link_bw_set, sizeof(link_bw_set));
4966
4967         if (link_bw_set) {
4968                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
4969                 return true;
4970         }
4971
4972         // Read DPCD 00115h to find the edp link rate set used
4973         core_link_read_dpcd(link, DP_LINK_RATE_SET,
4974                             &link_rate_set, sizeof(link_rate_set));
4975
4976         // Read DPCD 00101h to find out the number of lanes currently set
4977         core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4978                                 &lane_count_set.raw, sizeof(lane_count_set));
4979
4980         req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4981
4982         decide_edp_link_settings(link, &link_setting, req_bw);
4983
4984         if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
4985                         lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4986                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
4987                 return true;
4988         }
4989
4990         DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
4991         return false;
4992 }
4993
4994 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
4995 {
4996         if ((link_settings->link_rate >= LINK_RATE_LOW) &&
4997                         (link_settings->link_rate <= LINK_RATE_HIGH3))
4998                 return DP_8b_10b_ENCODING;
4999         return DP_UNKNOWN_ENCODING;
5000 }
5001