1 /* Copyright 2015 Advanced Micro Devices, Inc. */
2 #include "dm_services.h"
4 #include "dc_link_dp.h"
5 #include "dm_helpers.h"
10 #include "inc/core_types.h"
11 #include "link_hwss.h"
12 #include "dc_link_ddc.h"
13 #include "core_status.h"
14 #include "dpcd_defs.h"
15 #include "dc_dmub_srv.h"
16 #include "dce/dmub_hw_lock_mgr.h"
17 #include "inc/link_enc_cfg.h"
20 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
22 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
26 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
28 #include "link_dpcd.h"
30 /* maximum pre emphasis level allowed for each voltage swing level*/
31 static const enum dc_pre_emphasis
32 voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
35 PRE_EMPHASIS_DISABLED };
38 POST_LT_ADJ_REQ_LIMIT = 6,
39 POST_LT_ADJ_REQ_TIMEOUT = 200
42 static bool decide_fallback_link_setting(
43 struct dc_link_settings initial_link_settings,
44 struct dc_link_settings *current_link_setting,
45 enum link_training_result training_result);
46 static struct dc_link_settings get_common_supported_link_settings(
47 struct dc_link_settings link_setting_a,
48 struct dc_link_settings link_setting_b);
50 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
51 const struct dc_link_settings *link_settings)
53 union training_aux_rd_interval training_rd_interval;
54 uint32_t wait_in_micro_secs = 100;
56 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
59 DP_TRAINING_AUX_RD_INTERVAL,
60 (uint8_t *)&training_rd_interval,
61 sizeof(training_rd_interval));
62 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
63 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
64 return wait_in_micro_secs;
67 static uint32_t get_eq_training_aux_rd_interval(
69 const struct dc_link_settings *link_settings)
71 union training_aux_rd_interval training_rd_interval;
72 uint32_t wait_in_micro_secs = 400;
74 memset(&training_rd_interval, 0, sizeof(training_rd_interval));
75 /* overwrite the delay if rev > 1.1*/
76 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
77 /* DP 1.2 or later - retrieve delay through
78 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
81 DP_TRAINING_AUX_RD_INTERVAL,
82 (uint8_t *)&training_rd_interval,
83 sizeof(training_rd_interval));
85 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
86 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
89 return wait_in_micro_secs;
92 void dp_wait_for_training_aux_rd_interval(
94 uint32_t wait_in_micro_secs)
96 udelay(wait_in_micro_secs);
98 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
103 enum dpcd_training_patterns
104 dc_dp_training_pattern_to_dpcd_training_pattern(
105 struct dc_link *link,
106 enum dc_dp_training_pattern pattern)
108 enum dpcd_training_patterns dpcd_tr_pattern =
109 DPCD_TRAINING_PATTERN_VIDEOIDLE;
112 case DP_TRAINING_PATTERN_SEQUENCE_1:
113 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
115 case DP_TRAINING_PATTERN_SEQUENCE_2:
116 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
118 case DP_TRAINING_PATTERN_SEQUENCE_3:
119 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
121 case DP_TRAINING_PATTERN_SEQUENCE_4:
122 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
124 case DP_TRAINING_PATTERN_VIDEOIDLE:
125 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
129 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
134 return dpcd_tr_pattern;
137 static void dpcd_set_training_pattern(
138 struct dc_link *link,
139 enum dc_dp_training_pattern training_pattern)
141 union dpcd_training_pattern dpcd_pattern = { {0} };
143 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
144 dc_dp_training_pattern_to_dpcd_training_pattern(
145 link, training_pattern);
147 core_link_write_dpcd(
149 DP_TRAINING_PATTERN_SET,
153 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
155 DP_TRAINING_PATTERN_SET,
156 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
159 static enum dc_dp_training_pattern decide_cr_training_pattern(
160 const struct dc_link_settings *link_settings)
162 return DP_TRAINING_PATTERN_SEQUENCE_1;
165 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
166 const struct dc_link_settings *link_settings)
168 struct link_encoder *link_enc;
169 enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
170 struct encoder_feature_support *features;
171 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
173 /* Access link encoder capability based on whether it is statically
174 * or dynamically assigned to a link.
176 if (link->is_dig_mapping_flexible &&
177 link->dc->res_pool->funcs->link_encs_assign)
178 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
180 link_enc = link->link_enc;
182 features = &link_enc->features;
184 if (features->flags.bits.IS_TPS3_CAPABLE)
185 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
187 if (features->flags.bits.IS_TPS4_CAPABLE)
188 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
190 if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
191 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
192 return DP_TRAINING_PATTERN_SEQUENCE_4;
194 if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
195 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
196 return DP_TRAINING_PATTERN_SEQUENCE_3;
198 return DP_TRAINING_PATTERN_SEQUENCE_2;
201 enum dc_status dpcd_set_link_settings(
202 struct dc_link *link,
203 const struct link_training_settings *lt_settings)
206 enum dc_status status;
208 union down_spread_ctrl downspread = { {0} };
209 union lane_count_set lane_count_set = { {0} };
211 downspread.raw = (uint8_t)
212 (lt_settings->link_settings.link_spread);
214 lane_count_set.bits.LANE_COUNT_SET =
215 lt_settings->link_settings.lane_count;
217 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
218 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
221 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
222 lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
223 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
224 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
227 status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
228 &downspread.raw, sizeof(downspread));
230 status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
231 &lane_count_set.raw, 1);
233 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
234 lt_settings->link_settings.use_link_rate_set == true) {
236 /* WA for some MUX chips that will power down with eDP and lose supported
237 * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
238 * MUX chip gets link rate set back before link training.
240 if (link->connector_signal == SIGNAL_TYPE_EDP) {
241 uint8_t supported_link_rates[16];
243 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
244 supported_link_rates, sizeof(supported_link_rates));
246 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
247 status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
248 <_settings->link_settings.link_rate_set, 1);
250 rate = (uint8_t) (lt_settings->link_settings.link_rate);
251 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
255 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
258 lt_settings->link_settings.link_rate,
260 lt_settings->link_settings.lane_count,
261 lt_settings->enhanced_framing,
263 lt_settings->link_settings.link_spread);
265 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
268 lt_settings->link_settings.link_rate_set,
270 lt_settings->link_settings.lane_count,
271 lt_settings->enhanced_framing,
273 lt_settings->link_settings.link_spread);
279 uint8_t dc_dp_initialize_scrambling_data_symbols(
280 struct dc_link *link,
281 enum dc_dp_training_pattern pattern)
283 uint8_t disable_scrabled_data_symbols = 0;
286 case DP_TRAINING_PATTERN_SEQUENCE_1:
287 case DP_TRAINING_PATTERN_SEQUENCE_2:
288 case DP_TRAINING_PATTERN_SEQUENCE_3:
289 disable_scrabled_data_symbols = 1;
291 case DP_TRAINING_PATTERN_SEQUENCE_4:
292 disable_scrabled_data_symbols = 0;
296 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
300 return disable_scrabled_data_symbols;
303 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
305 return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
308 static void dpcd_set_lt_pattern_and_lane_settings(
309 struct dc_link *link,
310 const struct link_training_settings *lt_settings,
311 enum dc_dp_training_pattern pattern,
314 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
316 uint32_t dpcd_base_lt_offset;
318 uint8_t dpcd_lt_buffer[5] = {0};
319 union dpcd_training_pattern dpcd_pattern = { {0} };
321 uint32_t size_in_bytes;
322 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
323 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
325 if (is_repeater(link, offset))
326 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
327 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
329 /*****************************************************************
330 * DpcdAddress_TrainingPatternSet
331 *****************************************************************/
332 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
333 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
335 dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
336 dc_dp_initialize_scrambling_data_symbols(link, pattern);
338 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
341 if (is_repeater(link, offset)) {
342 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
346 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
348 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
351 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
353 /*****************************************************************
354 * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
355 *****************************************************************/
356 for (lane = 0; lane <
357 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
359 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
360 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
361 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
362 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
364 dpcd_lane[lane].bits.MAX_SWING_REACHED =
365 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
366 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
367 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
368 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
369 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
372 /* concatenate everything into one buffer*/
374 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
378 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
382 if (is_repeater(link, offset)) {
383 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
384 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
388 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
389 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
390 dpcd_lane[0].bits.MAX_SWING_REACHED,
391 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
393 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
396 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
397 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
398 dpcd_lane[0].bits.MAX_SWING_REACHED,
399 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
401 if (edp_workaround) {
402 /* for eDP write in 2 parts because the 5-byte burst is
403 * causing issues on some eDP panels (EPR#366724)
405 core_link_write_dpcd(
407 DP_TRAINING_PATTERN_SET,
409 sizeof(dpcd_pattern.raw));
411 core_link_write_dpcd(
413 DP_TRAINING_LANE0_SET,
414 (uint8_t *)(dpcd_lane),
418 /* write it all in (1 + number-of-lanes)-byte burst*/
419 core_link_write_dpcd(
423 size_in_bytes + sizeof(dpcd_pattern.raw));
425 link->cur_lane_setting = lt_settings->lane_settings[0];
428 bool dp_is_cr_done(enum dc_lane_count ln_count,
429 union lane_status *dpcd_lane_status)
432 /*LANEx_CR_DONE bits All 1's?*/
433 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
434 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
440 bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
441 union lane_status *dpcd_lane_status)
445 for (lane = 0; lane < (uint32_t)(ln_count); lane++)
446 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
451 bool dp_is_symbol_locked(enum dc_lane_count ln_count,
452 union lane_status *dpcd_lane_status)
456 for (lane = 0; lane < (uint32_t)(ln_count); lane++)
457 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
462 bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
464 return align_status.bits.INTERLANE_ALIGN_DONE == 1;
467 void dp_update_drive_settings(
468 struct link_training_settings *dest,
469 struct link_training_settings src)
472 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
473 if (dest->voltage_swing == NULL)
474 dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
476 dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
478 if (dest->pre_emphasis == NULL)
479 dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
481 dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
483 if (dest->post_cursor2 == NULL)
484 dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
486 dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
490 static uint8_t get_nibble_at_index(const uint8_t *buf,
494 nibble = buf[index / 2];
504 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
505 enum dc_voltage_swing voltage)
507 enum dc_pre_emphasis pre_emphasis;
508 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
510 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
511 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
517 static void find_max_drive_settings(
518 const struct link_training_settings *link_training_setting,
519 struct link_training_settings *max_lt_setting)
522 struct dc_lane_settings max_requested;
524 max_requested.VOLTAGE_SWING =
525 link_training_setting->
526 lane_settings[0].VOLTAGE_SWING;
527 max_requested.PRE_EMPHASIS =
528 link_training_setting->
529 lane_settings[0].PRE_EMPHASIS;
530 /*max_requested.postCursor2 =
531 * link_training_setting->laneSettings[0].postCursor2;*/
533 /* Determine what the maximum of the requested settings are*/
534 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
536 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
537 max_requested.VOLTAGE_SWING)
539 max_requested.VOLTAGE_SWING =
540 link_training_setting->
541 lane_settings[lane].VOLTAGE_SWING;
543 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
544 max_requested.PRE_EMPHASIS)
545 max_requested.PRE_EMPHASIS =
546 link_training_setting->
547 lane_settings[lane].PRE_EMPHASIS;
550 if (link_training_setting->laneSettings[lane].postCursor2 >
551 max_requested.postCursor2)
553 max_requested.postCursor2 =
554 link_training_setting->laneSettings[lane].postCursor2;
559 /* make sure the requested settings are
560 * not higher than maximum settings*/
561 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
562 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
564 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
565 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
567 if (max_requested.postCursor2 > PostCursor2_MaxLevel)
568 max_requested.postCursor2 = PostCursor2_MaxLevel;
571 /* make sure the pre-emphasis matches the voltage swing*/
572 if (max_requested.PRE_EMPHASIS >
573 get_max_pre_emphasis_for_voltage_swing(
574 max_requested.VOLTAGE_SWING))
575 max_requested.PRE_EMPHASIS =
576 get_max_pre_emphasis_for_voltage_swing(
577 max_requested.VOLTAGE_SWING);
580 * Post Cursor2 levels are completely independent from
581 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
582 * can only be applied to each allowable combination of voltage
583 * swing and pre-emphasis levels */
584 /* if ( max_requested.postCursor2 >
585 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
586 * max_requested.postCursor2 =
587 * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
590 max_lt_setting->link_settings.link_rate =
591 link_training_setting->link_settings.link_rate;
592 max_lt_setting->link_settings.lane_count =
593 link_training_setting->link_settings.lane_count;
594 max_lt_setting->link_settings.link_spread =
595 link_training_setting->link_settings.link_spread;
597 for (lane = 0; lane <
598 link_training_setting->link_settings.lane_count;
600 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
601 max_requested.VOLTAGE_SWING;
602 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
603 max_requested.PRE_EMPHASIS;
604 /*max_lt_setting->laneSettings[lane].postCursor2 =
605 * max_requested.postCursor2;
611 enum dc_status dp_get_lane_status_and_drive_settings(
612 struct dc_link *link,
613 const struct link_training_settings *link_training_setting,
614 union lane_status *ln_status,
615 union lane_align_status_updated *ln_status_updated,
616 struct link_training_settings *req_settings,
619 unsigned int lane01_status_address = DP_LANE0_1_STATUS;
620 uint8_t lane_adjust_offset = 4;
621 unsigned int lane01_adjust_address;
622 uint8_t dpcd_buf[6] = {0};
623 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
624 struct link_training_settings request_settings = { {0} };
626 enum dc_status status;
628 memset(req_settings, '\0', sizeof(struct link_training_settings));
630 if (is_repeater(link, offset)) {
631 lane01_status_address =
632 DP_LANE0_1_STATUS_PHY_REPEATER1 +
633 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
634 lane_adjust_offset = 3;
637 status = core_link_read_dpcd(
639 lane01_status_address,
640 (uint8_t *)(dpcd_buf),
643 for (lane = 0; lane <
644 (uint32_t)(link_training_setting->link_settings.lane_count);
647 ln_status[lane].raw =
648 get_nibble_at_index(&dpcd_buf[0], lane);
649 dpcd_lane_adjust[lane].raw =
650 get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
653 ln_status_updated->raw = dpcd_buf[2];
655 if (is_repeater(link, offset)) {
656 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
657 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
660 lane01_status_address, dpcd_buf[0],
661 lane01_status_address + 1, dpcd_buf[1]);
663 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
665 lane01_status_address, dpcd_buf[0],
666 lane01_status_address + 1, dpcd_buf[1]);
668 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
670 if (is_repeater(link, offset))
671 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
672 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
674 if (is_repeater(link, offset)) {
675 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
676 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
679 lane01_adjust_address,
680 dpcd_buf[lane_adjust_offset],
681 lane01_adjust_address + 1,
682 dpcd_buf[lane_adjust_offset + 1]);
684 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
686 lane01_adjust_address,
687 dpcd_buf[lane_adjust_offset],
688 lane01_adjust_address + 1,
689 dpcd_buf[lane_adjust_offset + 1]);
692 /*copy to req_settings*/
693 request_settings.link_settings.lane_count =
694 link_training_setting->link_settings.lane_count;
695 request_settings.link_settings.link_rate =
696 link_training_setting->link_settings.link_rate;
697 request_settings.link_settings.link_spread =
698 link_training_setting->link_settings.link_spread;
700 for (lane = 0; lane <
701 (uint32_t)(link_training_setting->link_settings.lane_count);
704 request_settings.lane_settings[lane].VOLTAGE_SWING =
705 (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
707 request_settings.lane_settings[lane].PRE_EMPHASIS =
708 (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
712 /*Note: for postcursor2, read adjusted
713 * postcursor2 settings from*/
714 /*DpcdAddress_AdjustRequestPostCursor2 =
715 *0x020C (not implemented yet)*/
717 /* we find the maximum of the requested settings across all lanes*/
718 /* and set this maximum for all lanes*/
719 find_max_drive_settings(&request_settings, req_settings);
721 /* if post cursor 2 is needed in the future,
722 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
728 enum dc_status dpcd_set_lane_settings(
729 struct dc_link *link,
730 const struct link_training_settings *link_training_setting,
733 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
735 unsigned int lane0_set_address;
736 enum dc_status status;
738 lane0_set_address = DP_TRAINING_LANE0_SET;
740 if (is_repeater(link, offset))
741 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
742 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
744 for (lane = 0; lane <
745 (uint32_t)(link_training_setting->
746 link_settings.lane_count);
748 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
749 (uint8_t)(link_training_setting->
750 lane_settings[lane].VOLTAGE_SWING);
751 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
752 (uint8_t)(link_training_setting->
753 lane_settings[lane].PRE_EMPHASIS);
754 dpcd_lane[lane].bits.MAX_SWING_REACHED =
755 (link_training_setting->
756 lane_settings[lane].VOLTAGE_SWING ==
757 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
758 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
759 (link_training_setting->
760 lane_settings[lane].PRE_EMPHASIS ==
761 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
764 status = core_link_write_dpcd(link,
766 (uint8_t *)(dpcd_lane),
767 link_training_setting->link_settings.lane_count);
770 if (LTSettings.link.rate == LinkRate_High2)
772 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
773 for ( uint32_t lane = 0;
774 lane < lane_count_DPMax; lane++)
776 dpcd_lane2[lane].bits.post_cursor2_set =
777 static_cast<unsigned char>(
778 LTSettings.laneSettings[lane].postCursor2);
779 dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
781 m_pDpcdAccessSrv->WriteDpcdData(
782 DpcdAddress_Lane0Set2,
783 reinterpret_cast<unsigned char*>(dpcd_lane2),
784 LTSettings.link.lanes);
788 if (is_repeater(link, offset)) {
789 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
790 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
794 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
795 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
796 dpcd_lane[0].bits.MAX_SWING_REACHED,
797 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
800 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
803 dpcd_lane[0].bits.VOLTAGE_SWING_SET,
804 dpcd_lane[0].bits.PRE_EMPHASIS_SET,
805 dpcd_lane[0].bits.MAX_SWING_REACHED,
806 dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
808 link->cur_lane_setting = link_training_setting->lane_settings[0];
813 bool dp_is_max_vs_reached(
814 const struct link_training_settings *lt_settings)
817 for (lane = 0; lane <
818 (uint32_t)(lt_settings->link_settings.lane_count);
820 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
821 == VOLTAGE_SWING_MAX_LEVEL)
828 static bool perform_post_lt_adj_req_sequence(
829 struct dc_link *link,
830 struct link_training_settings *lt_settings)
832 enum dc_lane_count lane_count =
833 lt_settings->link_settings.lane_count;
835 uint32_t adj_req_count;
836 uint32_t adj_req_timer;
837 bool req_drv_setting_changed;
840 req_drv_setting_changed = false;
841 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
844 req_drv_setting_changed = false;
846 for (adj_req_timer = 0;
847 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
850 struct link_training_settings req_settings;
851 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
852 union lane_align_status_updated
853 dpcd_lane_status_updated;
855 dp_get_lane_status_and_drive_settings(
859 &dpcd_lane_status_updated,
863 if (dpcd_lane_status_updated.bits.
864 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
867 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
870 if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
871 !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
872 !dp_is_interlane_aligned(dpcd_lane_status_updated))
875 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
878 lane_settings[lane].VOLTAGE_SWING !=
879 req_settings.lane_settings[lane].
881 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
882 req_settings.lane_settings[lane].PRE_EMPHASIS) {
884 req_drv_setting_changed = true;
889 if (req_drv_setting_changed) {
890 dp_update_drive_settings(
891 lt_settings, req_settings);
893 dc_link_dp_set_drive_settings(link,
901 if (!req_drv_setting_changed) {
902 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
909 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
917 /* Only used for channel equalization */
918 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
920 unsigned int aux_rd_interval_us = 400;
922 switch (dpcd_aux_read_interval) {
924 aux_rd_interval_us = 4000;
927 aux_rd_interval_us = 8000;
930 aux_rd_interval_us = 12000;
933 aux_rd_interval_us = 16000;
939 return aux_rd_interval_us;
942 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
943 union lane_status *dpcd_lane_status)
945 enum link_training_result result = LINK_TRAINING_SUCCESS;
947 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
948 result = LINK_TRAINING_CR_FAIL_LANE0;
949 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
950 result = LINK_TRAINING_CR_FAIL_LANE1;
951 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
952 result = LINK_TRAINING_CR_FAIL_LANE23;
953 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
954 result = LINK_TRAINING_CR_FAIL_LANE23;
958 static enum link_training_result perform_channel_equalization_sequence(
959 struct dc_link *link,
960 struct link_training_settings *lt_settings,
963 struct link_training_settings req_settings;
964 enum dc_dp_training_pattern tr_pattern;
965 uint32_t retries_ch_eq;
966 uint32_t wait_time_microsec;
967 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
968 union lane_align_status_updated dpcd_lane_status_updated = { {0} };
969 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
971 /* Note: also check that TPS4 is a supported feature*/
973 tr_pattern = lt_settings->pattern_for_eq;
975 if (is_repeater(link, offset))
976 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
978 dp_set_hw_training_pattern(link, tr_pattern, offset);
980 for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
983 dp_set_hw_lane_settings(link, lt_settings, offset);
987 /* EPR #361076 - write as a 5-byte burst,
988 * but only for the 1-st iteration
991 dpcd_set_lt_pattern_and_lane_settings(
996 dpcd_set_lane_settings(link, lt_settings, offset);
998 /* 3. wait for receiver to lock-on*/
999 wait_time_microsec = lt_settings->eq_pattern_time;
1001 if (is_repeater(link, offset))
1002 wait_time_microsec =
1003 dp_translate_training_aux_read_interval(
1004 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
1006 dp_wait_for_training_aux_rd_interval(
1008 wait_time_microsec);
1010 /* 4. Read lane status and requested
1011 * drive settings as set by the sink*/
1013 dp_get_lane_status_and_drive_settings(
1017 &dpcd_lane_status_updated,
1021 /* 5. check CR done*/
1022 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
1023 return LINK_TRAINING_EQ_FAIL_CR;
1025 /* 6. check CHEQ done*/
1026 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
1027 dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
1028 dp_is_interlane_aligned(dpcd_lane_status_updated))
1029 return LINK_TRAINING_SUCCESS;
1031 /* 7. update VS/PE/PC2 in lt_settings*/
1032 dp_update_drive_settings(lt_settings, req_settings);
1035 return LINK_TRAINING_EQ_FAIL_EQ;
1039 static void start_clock_recovery_pattern_early(struct dc_link *link,
1040 struct link_training_settings *lt_settings,
1043 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1045 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1046 dp_set_hw_lane_settings(link, lt_settings, offset);
1050 static enum link_training_result perform_clock_recovery_sequence(
1051 struct dc_link *link,
1052 struct link_training_settings *lt_settings,
1055 uint32_t retries_cr;
1056 uint32_t retry_count;
1057 uint32_t wait_time_microsec;
1058 struct link_training_settings req_settings;
1059 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1060 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1061 union lane_align_status_updated dpcd_lane_status_updated;
1066 if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1067 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1069 /* najeeb - The synaptics MST hub can put the LT in
1070 * infinite loop by switching the VS
1072 /* between level 0 and level 1 continuously, here
1073 * we try for CR lock for LinkTrainingMaxCRRetry count*/
1074 while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1075 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1077 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1078 memset(&dpcd_lane_status_updated, '\0',
1079 sizeof(dpcd_lane_status_updated));
1081 /* 1. call HWSS to set lane settings*/
1082 dp_set_hw_lane_settings(
1087 /* 2. update DPCD of the receiver*/
1089 /* EPR #361076 - write as a 5-byte burst,
1090 * but only for the 1-st iteration.*/
1091 dpcd_set_lt_pattern_and_lane_settings(
1094 lt_settings->pattern_for_cr,
1097 dpcd_set_lane_settings(
1102 /* 3. wait receiver to lock-on*/
1103 wait_time_microsec = lt_settings->cr_pattern_time;
1105 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1106 wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1108 dp_wait_for_training_aux_rd_interval(
1110 wait_time_microsec);
1112 /* 4. Read lane status and requested drive
1113 * settings as set by the sink
1115 dp_get_lane_status_and_drive_settings(
1119 &dpcd_lane_status_updated,
1123 /* 5. check CR done*/
1124 if (dp_is_cr_done(lane_count, dpcd_lane_status))
1125 return LINK_TRAINING_SUCCESS;
1127 /* 6. max VS reached*/
1128 if (dp_is_max_vs_reached(lt_settings))
1131 /* 7. same lane settings*/
1132 /* Note: settings are the same for all lanes,
1133 * so comparing first lane is sufficient*/
1134 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
1135 req_settings.lane_settings[0].VOLTAGE_SWING)
1136 && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1137 req_settings.lane_settings[0].PRE_EMPHASIS))
1142 /* 8. update VS/PE/PC2 in lt_settings*/
1143 dp_update_drive_settings(lt_settings, req_settings);
1148 if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1150 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1152 LINK_TRAINING_MAX_CR_RETRY);
1156 return dp_get_cr_failure(lane_count, dpcd_lane_status);
1159 static inline enum link_training_result dp_transition_to_video_idle(
1160 struct dc_link *link,
1161 struct link_training_settings *lt_settings,
1162 enum link_training_result status)
1164 union lane_count_set lane_count_set = { {0} };
1166 /* 4. mainlink output idle pattern*/
1167 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1170 * 5. post training adjust if required
1171 * If the upstream DPTX and downstream DPRX both support TPS4,
1172 * TPS4 must be used instead of POST_LT_ADJ_REQ.
1174 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1175 lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) {
1176 /* delay 5ms after Main Link output idle pattern and then check
1179 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1181 status = dp_check_link_loss_status(link, lt_settings);
1186 if (status == LINK_TRAINING_SUCCESS &&
1187 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1188 status = LINK_TRAINING_LQA_FAIL;
1190 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1191 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1192 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1194 core_link_write_dpcd(
1197 &lane_count_set.raw,
1198 sizeof(lane_count_set));
1203 enum link_training_result dp_check_link_loss_status(
1204 struct dc_link *link,
1205 const struct link_training_settings *link_training_setting)
1207 enum link_training_result status = LINK_TRAINING_SUCCESS;
1208 union lane_status lane_status;
1209 uint8_t dpcd_buf[6] = {0};
1212 core_link_read_dpcd(
1215 (uint8_t *)(dpcd_buf),
1218 /*parse lane status*/
1219 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1221 * check lanes status
1223 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1225 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1226 !lane_status.bits.CR_DONE_0 ||
1227 !lane_status.bits.SYMBOL_LOCKED_0) {
1228 /* if one of the channel equalization, clock
1229 * recovery or symbol lock is dropped
1230 * consider it as (link has been
1231 * dropped) dp sink status has changed
1233 status = LINK_TRAINING_LINK_LOSS;
1241 static inline void decide_8b_10b_training_settings(
1242 struct dc_link *link,
1243 const struct dc_link_settings *link_setting,
1244 struct link_training_settings *lt_settings)
1246 memset(lt_settings, '\0', sizeof(struct link_training_settings));
1248 /* Initialize link settings */
1249 lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1250 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1251 lt_settings->link_settings.link_rate = link_setting->link_rate;
1252 lt_settings->link_settings.lane_count = link_setting->lane_count;
1253 /* TODO hard coded to SS for now
1254 * lt_settings.link_settings.link_spread =
1255 * dal_display_path_is_ss_supported(
1256 * path_mode->display_path) ?
1257 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1258 * LINK_SPREAD_DISABLED;
1260 lt_settings->link_settings.link_spread = link->dp_ss_off ?
1261 LINK_SPREAD_DISABLED : LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1262 lt_settings->lttpr_mode = link->lttpr_mode;
1263 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1264 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1265 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1266 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1267 lt_settings->enhanced_framing = 1;
1268 lt_settings->should_set_fec_ready = true;
1271 void dp_decide_training_settings(
1272 struct dc_link *link,
1273 const struct dc_link_settings *link_settings,
1274 struct link_training_settings *lt_settings)
1276 if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
1277 decide_8b_10b_training_settings(link, link_settings, lt_settings);
1280 static void override_training_settings(
1281 struct dc_link *link,
1282 const struct dc_link_training_overrides *overrides,
1283 struct link_training_settings *lt_settings)
1287 /* Override link settings */
1288 if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1289 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1290 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1291 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1293 /* Override link spread */
1294 if (!link->dp_ss_off && overrides->downspread != NULL)
1295 lt_settings->link_settings.link_spread = *overrides->downspread ?
1296 LINK_SPREAD_05_DOWNSPREAD_30KHZ
1297 : LINK_SPREAD_DISABLED;
1299 /* Override lane settings */
1300 if (overrides->voltage_swing != NULL)
1301 lt_settings->voltage_swing = overrides->voltage_swing;
1302 if (overrides->pre_emphasis != NULL)
1303 lt_settings->pre_emphasis = overrides->pre_emphasis;
1304 if (overrides->post_cursor2 != NULL)
1305 lt_settings->post_cursor2 = overrides->post_cursor2;
1306 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1307 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1308 lt_settings->voltage_swing != NULL ?
1309 *lt_settings->voltage_swing :
1310 VOLTAGE_SWING_LEVEL0;
1311 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1312 lt_settings->pre_emphasis != NULL ?
1313 *lt_settings->pre_emphasis
1314 : PRE_EMPHASIS_DISABLED;
1315 lt_settings->lane_settings[lane].POST_CURSOR2 =
1316 lt_settings->post_cursor2 != NULL ?
1317 *lt_settings->post_cursor2
1318 : POST_CURSOR2_DISABLED;
1321 /* Initialize training timings */
1322 if (overrides->cr_pattern_time != NULL)
1323 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1325 if (overrides->eq_pattern_time != NULL)
1326 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1328 if (overrides->pattern_for_cr != NULL)
1329 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1330 if (overrides->pattern_for_eq != NULL)
1331 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1333 if (overrides->enhanced_framing != NULL)
1334 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1336 if (link->preferred_training_settings.fec_enable != NULL)
1337 lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
1340 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
1342 switch (lttpr_repeater_count) {
1343 case 0x80: // 1 lttpr repeater
1345 case 0x40: // 2 lttpr repeaters
1347 case 0x20: // 3 lttpr repeaters
1349 case 0x10: // 4 lttpr repeaters
1351 case 0x08: // 5 lttpr repeaters
1353 case 0x04: // 6 lttpr repeaters
1355 case 0x02: // 7 lttpr repeaters
1357 case 0x01: // 8 lttpr repeaters
1362 return 0; // invalid value
1365 enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
1367 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1369 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1370 return core_link_write_dpcd(link,
1371 DP_PHY_REPEATER_MODE,
1372 (uint8_t *)&repeater_mode,
1373 sizeof(repeater_mode));
1376 enum dc_status configure_lttpr_mode_non_transparent(
1377 struct dc_link *link,
1378 const struct link_training_settings *lt_settings)
1380 /* aux timeout is already set to extended */
1381 /* RESET/SET lttpr mode to enable non transparent mode */
1382 uint8_t repeater_cnt;
1383 uint32_t aux_interval_address;
1384 uint8_t repeater_id;
1385 enum dc_status result = DC_ERROR_UNEXPECTED;
1386 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1388 enum dp_link_encoding encoding = dp_get_link_encoding_format(<_settings->link_settings);
1390 if (encoding == DP_8b_10b_ENCODING) {
1391 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1392 result = core_link_write_dpcd(link,
1393 DP_PHY_REPEATER_MODE,
1394 (uint8_t *)&repeater_mode,
1395 sizeof(repeater_mode));
1399 if (result == DC_OK) {
1400 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1403 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1405 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1407 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1408 result = core_link_write_dpcd(link,
1409 DP_PHY_REPEATER_MODE,
1410 (uint8_t *)&repeater_mode,
1411 sizeof(repeater_mode));
1413 if (result == DC_OK) {
1414 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1417 if (encoding == DP_8b_10b_ENCODING) {
1418 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1419 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1420 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1421 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1422 core_link_read_dpcd(
1424 aux_interval_address,
1425 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1426 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1427 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1435 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1437 union dpcd_training_pattern dpcd_pattern = { {0} };
1439 const uint32_t dpcd_base_lt_offset =
1440 DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1441 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1442 /* Set training not in progress*/
1443 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1445 core_link_write_dpcd(
1447 dpcd_base_lt_offset,
1451 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1454 dpcd_base_lt_offset,
1455 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1458 static void print_status_message(
1459 struct dc_link *link,
1460 const struct link_training_settings *lt_settings,
1461 enum link_training_result status)
1463 char *link_rate = "Unknown";
1464 char *lt_result = "Unknown";
1465 char *lt_spread = "Disabled";
1467 switch (lt_settings->link_settings.link_rate) {
1471 case LINK_RATE_RATE_2:
1474 case LINK_RATE_RATE_3:
1477 case LINK_RATE_HIGH:
1480 case LINK_RATE_RBR2:
1483 case LINK_RATE_RATE_6:
1486 case LINK_RATE_HIGH2:
1489 case LINK_RATE_HIGH3:
1497 case LINK_TRAINING_SUCCESS:
1500 case LINK_TRAINING_CR_FAIL_LANE0:
1501 lt_result = "CR failed lane0";
1503 case LINK_TRAINING_CR_FAIL_LANE1:
1504 lt_result = "CR failed lane1";
1506 case LINK_TRAINING_CR_FAIL_LANE23:
1507 lt_result = "CR failed lane23";
1509 case LINK_TRAINING_EQ_FAIL_CR:
1510 lt_result = "CR failed in EQ";
1512 case LINK_TRAINING_EQ_FAIL_EQ:
1513 lt_result = "EQ failed";
1515 case LINK_TRAINING_LQA_FAIL:
1516 lt_result = "LQA failed";
1518 case LINK_TRAINING_LINK_LOSS:
1519 lt_result = "Link loss";
1525 switch (lt_settings->link_settings.link_spread) {
1526 case LINK_SPREAD_DISABLED:
1527 lt_spread = "Disabled";
1529 case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1530 lt_spread = "0.5% 30KHz";
1532 case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1533 lt_spread = "0.5% 33KHz";
1539 /* Connectivity log: link training */
1540 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1542 lt_settings->link_settings.lane_count,
1544 lt_settings->lane_settings[0].VOLTAGE_SWING,
1545 lt_settings->lane_settings[0].PRE_EMPHASIS,
1549 void dc_link_dp_set_drive_settings(
1550 struct dc_link *link,
1551 struct link_training_settings *lt_settings)
1553 /* program ASIC PHY settings*/
1554 dp_set_hw_lane_settings(link, lt_settings, DPRX);
1556 /* Notify DP sink the PHY settings from source */
1557 dpcd_set_lane_settings(link, lt_settings, DPRX);
1560 bool dc_link_dp_perform_link_training_skip_aux(
1561 struct dc_link *link,
1562 const struct dc_link_settings *link_setting)
1564 struct link_training_settings lt_settings = {0};
1566 dp_decide_training_settings(
1570 override_training_settings(
1572 &link->preferred_training_settings,
1575 /* 1. Perform_clock_recovery_sequence. */
1577 /* transmit training pattern for clock recovery */
1578 dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1580 /* call HWSS to set lane settings*/
1581 dp_set_hw_lane_settings(link, <_settings, DPRX);
1583 /* wait receiver to lock-on*/
1584 dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1586 /* 2. Perform_channel_equalization_sequence. */
1588 /* transmit training pattern for channel equalization. */
1589 dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1591 /* call HWSS to set lane settings*/
1592 dp_set_hw_lane_settings(link, <_settings, DPRX);
1594 /* wait receiver to lock-on. */
1595 dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1597 /* 3. Perform_link_training_int. */
1599 /* Mainlink output idle pattern. */
1600 dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1602 print_status_message(link, <_settings, LINK_TRAINING_SUCCESS);
1607 enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
1609 enum dc_status status = DC_OK;
1611 if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT)
1612 status = configure_lttpr_mode_transparent(link);
1614 else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1615 status = configure_lttpr_mode_non_transparent(link, lt_settings);
1620 static void dpcd_exit_training_mode(struct dc_link *link)
1623 /* clear training pattern set */
1624 dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
1627 enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
1628 struct link_training_settings *lt_settings)
1630 enum dp_link_encoding encoding =
1631 dp_get_link_encoding_format(
1632 <_settings->link_settings);
1633 enum dc_status status;
1635 status = core_link_write_dpcd(
1637 DP_MAIN_LINK_CHANNEL_CODING_SET,
1638 (uint8_t *) &encoding,
1640 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
1642 DP_MAIN_LINK_CHANNEL_CODING_SET,
1648 static enum link_training_result dp_perform_8b_10b_link_training(
1649 struct dc_link *link,
1650 struct link_training_settings *lt_settings)
1652 enum link_training_result status = LINK_TRAINING_SUCCESS;
1654 uint8_t repeater_cnt;
1655 uint8_t repeater_id;
1658 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1659 start_clock_recovery_pattern_early(link, lt_settings, DPRX);
1661 /* 1. set link rate, lane count and spread. */
1662 dpcd_set_link_settings(link, lt_settings);
1664 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1666 /* 2. perform link training (set link training done
1667 * to false is done as well)
1669 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1671 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1673 status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);
1675 if (status != LINK_TRAINING_SUCCESS)
1678 status = perform_channel_equalization_sequence(link,
1682 if (status != LINK_TRAINING_SUCCESS)
1685 repeater_training_done(link, repeater_id);
1688 for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
1689 lt_settings->lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0;
1692 if (status == LINK_TRAINING_SUCCESS) {
1693 status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
1694 if (status == LINK_TRAINING_SUCCESS) {
1695 status = perform_channel_equalization_sequence(link,
1704 enum link_training_result dc_link_dp_perform_link_training(
1705 struct dc_link *link,
1706 const struct dc_link_settings *link_settings,
1707 bool skip_video_pattern)
1709 enum link_training_result status = LINK_TRAINING_SUCCESS;
1710 struct link_training_settings lt_settings = {0};
1711 enum dp_link_encoding encoding =
1712 dp_get_link_encoding_format(link_settings);
1714 /* decide training settings */
1715 dp_decide_training_settings(
1719 override_training_settings(
1721 &link->preferred_training_settings,
1724 /* reset previous training states */
1725 dpcd_exit_training_mode(link);
1727 /* configure link prior to entering training mode */
1728 dpcd_configure_lttpr_mode(link, <_settings);
1729 dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
1730 dpcd_configure_channel_coding(link, <_settings);
1732 /* enter training mode:
1733 * Per DP specs starting from here, DPTX device shall not issue
1734 * Non-LT AUX transactions inside training mode.
1736 if (encoding == DP_8b_10b_ENCODING)
1737 status = dp_perform_8b_10b_link_training(link, <_settings);
1741 /* exit training mode and switch to video idle */
1742 dpcd_exit_training_mode(link);
1743 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
1744 status = dp_transition_to_video_idle(link,
1748 /* dump debug data */
1749 print_status_message(link, <_settings, status);
1750 if (status != LINK_TRAINING_SUCCESS)
1751 link->ctx->dc->debug_data.ltFailCount++;
1755 bool perform_link_training_with_retries(
1756 const struct dc_link_settings *link_setting,
1757 bool skip_video_pattern,
1759 struct pipe_ctx *pipe_ctx,
1760 enum signal_type signal,
1764 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1765 struct dc_stream_state *stream = pipe_ctx->stream;
1766 struct dc_link *link = stream->link;
1767 enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1768 struct link_encoder *link_enc;
1769 enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1770 struct dc_link_settings current_setting = *link_setting;
1772 /* Dynamically assigned link encoders associated with stream rather than
1775 if (link->dc->res_pool->funcs->link_encs_assign)
1776 link_enc = stream->link_enc;
1778 link_enc = link->link_enc;
1780 /* We need to do this before the link training to ensure the idle pattern in SST
1781 * mode will be sent right after the link training
1783 link_enc->funcs->connect_dig_be_to_fe(link_enc,
1784 pipe_ctx->stream_res.stream_enc->id, true);
1786 for (j = 0; j < attempts; ++j) {
1788 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1789 __func__, (unsigned int)j + 1, attempts);
1794 pipe_ctx->clock_source->id,
1797 if (stream->sink_patches.dppowerup_delay > 0) {
1798 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1800 msleep(delay_dp_power_up_in_ms);
1803 #ifdef CONFIG_DRM_AMD_DC_HDCP
1804 if (panel_mode == DP_PANEL_MODE_EDP) {
1805 struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1807 if (cp_psp && cp_psp->funcs.enable_assr) {
1808 if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
1809 /* since eDP implies ASSR on, change panel
1810 * mode to disable ASSR
1812 panel_mode = DP_PANEL_MODE_DEFAULT;
1818 dp_set_panel_mode(link, panel_mode);
1820 if (link->aux_access_disabled) {
1821 dc_link_dp_perform_link_training_skip_aux(link, ¤t_setting);
1824 status = dc_link_dp_perform_link_training(
1827 skip_video_pattern);
1828 if (status == LINK_TRAINING_SUCCESS)
1832 /* latest link training still fail, skip delay and keep PHY on
1834 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
1837 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1838 __func__, (unsigned int)j + 1, attempts);
1840 dp_disable_link_phy(link, signal);
1842 /* Abort link training if failure due to sink being unplugged. */
1843 if (status == LINK_TRAINING_ABORT)
1845 else if (do_fallback) {
1846 decide_fallback_link_setting(*link_setting, ¤t_setting, status);
1847 /* Fail link training if reduced link bandwidth no longer meets
1848 * stream requirements.
1850 if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
1851 dc_link_bandwidth_kbps(link, ¤t_setting))
1855 msleep(delay_between_attempts);
1857 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1863 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1865 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1866 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1868 if (dp_cs != NULL) {
1869 dp_cs_id = dp_cs->id;
1872 * dp clock source is not initialized for some reason.
1873 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1881 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1883 if (mst_enable == false &&
1884 link->type == dc_connection_mst_branch) {
1885 /* Disable MST on link. Use only local sink. */
1886 dp_disable_link_phy_mst(link, link->connector_signal);
1888 link->type = dc_connection_single;
1889 link->local_sink = link->remote_sinks[0];
1890 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1891 dc_sink_retain(link->local_sink);
1892 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1893 } else if (mst_enable == true &&
1894 link->type == dc_connection_single &&
1895 link->remote_sinks[0] != NULL) {
1896 /* Re-enable MST on link. */
1897 dp_disable_link_phy(link, link->connector_signal);
1898 dp_enable_mst_on_sink(link, true);
1900 link->type = dc_connection_mst_branch;
1901 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1905 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1907 /* Begin Sync LT. During this time,
1908 * DPCD:600h must not be powered down.
1910 link->sync_lt_in_progress = true;
1912 /*Clear any existing preferred settings.*/
1913 memset(&link->preferred_training_settings, 0,
1914 sizeof(struct dc_link_training_overrides));
1915 memset(&link->preferred_link_setting, 0,
1916 sizeof(struct dc_link_settings));
1921 enum link_training_result dc_link_dp_sync_lt_attempt(
1922 struct dc_link *link,
1923 struct dc_link_settings *link_settings,
1924 struct dc_link_training_overrides *lt_overrides)
1926 struct link_training_settings lt_settings = {0};
1927 enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1928 enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1929 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1930 bool fec_enable = false;
1932 dp_decide_training_settings(
1936 override_training_settings(
1940 /* Setup MST Mode */
1941 if (lt_overrides->mst_enable)
1942 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1945 dp_disable_link_phy(link, link->connector_signal);
1948 dp_cs_id = get_clock_source_id(link);
1949 dp_enable_link_phy(link, link->connector_signal,
1950 dp_cs_id, link_settings);
1952 /* Set FEC enable */
1953 fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1954 dp_set_fec_ready(link, fec_enable);
1956 if (lt_overrides->alternate_scrambler_reset) {
1957 if (*lt_overrides->alternate_scrambler_reset)
1958 panel_mode = DP_PANEL_MODE_EDP;
1960 panel_mode = DP_PANEL_MODE_DEFAULT;
1962 panel_mode = dp_get_panel_mode(link);
1964 dp_set_panel_mode(link, panel_mode);
1966 /* Attempt to train with given link training settings */
1967 if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1968 start_clock_recovery_pattern_early(link, <_settings, DPRX);
1970 /* Set link rate, lane count and spread. */
1971 dpcd_set_link_settings(link, <_settings);
1973 /* 2. perform link training (set link training done
1974 * to false is done as well)
1976 lt_status = perform_clock_recovery_sequence(link, <_settings, DPRX);
1977 if (lt_status == LINK_TRAINING_SUCCESS) {
1978 lt_status = perform_channel_equalization_sequence(link,
1983 /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1984 /* 4. print status message*/
1985 print_status_message(link, <_settings, lt_status);
1990 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1992 /* If input parameter is set, shut down phy.
1993 * Still shouldn't turn off dp_receiver (DPCD:600h)
1995 if (link_down == true) {
1996 dp_disable_link_phy(link, link->connector_signal);
1997 dp_set_fec_ready(link, false);
2000 link->sync_lt_in_progress = false;
2004 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2006 if (!max_link_enc_cap) {
2007 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2011 if (link->link_enc->funcs->get_max_link_cap) {
2012 link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap);
2016 DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2017 max_link_enc_cap->lane_count = 1;
2018 max_link_enc_cap->link_rate = 6;
2022 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
2024 struct dc_link_settings max_link_cap = {0};
2026 /* get max link encoder capability */
2027 link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
2029 /* Lower link settings based on sink's link cap */
2030 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2031 max_link_cap.lane_count =
2032 link->reported_link_cap.lane_count;
2033 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2034 max_link_cap.link_rate =
2035 link->reported_link_cap.link_rate;
2036 if (link->reported_link_cap.link_spread <
2037 max_link_cap.link_spread)
2038 max_link_cap.link_spread =
2039 link->reported_link_cap.link_spread;
2041 * account for lttpr repeaters cap
2042 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2044 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
2045 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2046 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2048 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
2049 max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
2051 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
2053 max_link_cap.lane_count,
2054 max_link_cap.link_rate);
2056 return max_link_cap;
2059 enum dc_status read_hpd_rx_irq_data(
2060 struct dc_link *link,
2061 union hpd_irq_data *irq_data)
2063 static enum dc_status retval;
2065 /* The HW reads 16 bytes from 200h on HPD,
2066 * but if we get an AUX_DEFER, the HW cannot retry
2067 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
2068 * fail, so we now explicitly read 6 bytes which is
2069 * the req from the above mentioned test cases.
2071 * For DP 1.4 we need to read those from 2002h range.
2073 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
2074 retval = core_link_read_dpcd(
2078 sizeof(union hpd_irq_data));
2080 /* Read 14 bytes in a single read and then copy only the required fields.
2081 * This is more efficient than doing it in two separate AUX reads. */
2083 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
2085 retval = core_link_read_dpcd(
2091 if (retval != DC_OK)
2094 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
2095 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
2096 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
2097 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
2098 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
2099 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
2105 bool hpd_rx_irq_check_link_loss_status(
2106 struct dc_link *link,
2107 union hpd_irq_data *hpd_irq_dpcd_data)
2109 uint8_t irq_reg_rx_power_state = 0;
2110 enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2111 union lane_status lane_status;
2113 bool sink_status_changed;
2116 sink_status_changed = false;
2117 return_code = false;
2119 if (link->cur_link_settings.lane_count == 0)
2122 /*1. Check that Link Status changed, before re-training.*/
2124 /*parse lane status*/
2125 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2126 /* check status of lanes 0,1
2127 * changed DpcdAddress_Lane01Status (0x202)
2129 lane_status.raw = get_nibble_at_index(
2130 &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2133 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2134 !lane_status.bits.CR_DONE_0 ||
2135 !lane_status.bits.SYMBOL_LOCKED_0) {
2136 /* if one of the channel equalization, clock
2137 * recovery or symbol lock is dropped
2138 * consider it as (link has been
2139 * dropped) dp sink status has changed
2141 sink_status_changed = true;
2146 /* Check interlane align.*/
2147 if (sink_status_changed ||
2148 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2150 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2154 /*2. Check that we can handle interrupt: Not in FS DOS,
2155 * Not in "Display Timeout" state, Link is trained.
2157 dpcd_result = core_link_read_dpcd(link,
2159 &irq_reg_rx_power_state,
2160 sizeof(irq_reg_rx_power_state));
2162 if (dpcd_result != DC_OK) {
2163 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2166 if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2167 return_code = false;
2174 bool dp_verify_link_cap(
2175 struct dc_link *link,
2176 struct dc_link_settings *known_limit_link_setting,
2179 struct dc_link_settings max_link_cap = {0};
2180 struct dc_link_settings cur_link_setting = {0};
2181 struct dc_link_settings *cur = &cur_link_setting;
2182 struct dc_link_settings initial_link_settings = {0};
2184 bool skip_link_training;
2185 bool skip_video_pattern;
2186 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2187 enum link_training_result status;
2188 union hpd_irq_data irq_data;
2190 if (link->dc->debug.skip_detection_link_training) {
2191 link->verified_link_cap = *known_limit_link_setting;
2195 memset(&irq_data, 0, sizeof(irq_data));
2197 skip_link_training = false;
2199 max_link_cap = get_max_link_cap(link);
2201 /* Grant extended timeout request */
2202 if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
2203 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2205 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2208 /* TODO implement override and monitor patch later */
2210 /* try to train the link from high to low to
2211 * find the physical link capability
2213 /* disable PHY done possible by BIOS, will be done by driver itself */
2214 dp_disable_link_phy(link, link->connector_signal);
2216 dp_cs_id = get_clock_source_id(link);
2218 /* link training starts with the maximum common settings
2219 * supported by both sink and ASIC.
2221 initial_link_settings = get_common_supported_link_settings(
2222 *known_limit_link_setting,
2224 cur_link_setting = initial_link_settings;
2226 /* Temporary Renoir-specific workaround for SWDEV-215184;
2227 * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2228 * so add extra cycle of enabling and disabling the PHY before first link training.
2230 if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2231 link->dc->debug.usbc_combo_phy_reset_wa) {
2232 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2233 dp_disable_link_phy(link, link->connector_signal);
2237 skip_video_pattern = true;
2239 if (cur->link_rate == LINK_RATE_LOW)
2240 skip_video_pattern = false;
2244 link->connector_signal,
2249 if (skip_link_training)
2252 status = dc_link_dp_perform_link_training(
2255 skip_video_pattern);
2256 if (status == LINK_TRAINING_SUCCESS)
2263 link->verified_link_cap = *cur;
2265 if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2266 if (hpd_rx_irq_check_link_loss_status(
2271 /* always disable the link before trying another
2272 * setting or before returning we'll enable it later
2273 * based on the actual mode we're driving
2275 dp_disable_link_phy(link, link->connector_signal);
2276 } while (!success && decide_fallback_link_setting(
2277 initial_link_settings, cur, status));
2279 /* Link Training failed for all Link Settings
2280 * (Lane Count is still unknown)
2283 /* If all LT fails for all settings,
2284 * set verified = failed safe (1 lane low)
2286 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2287 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2289 link->verified_link_cap.link_spread =
2290 LINK_SPREAD_DISABLED;
2297 bool dp_verify_link_cap_with_retries(
2298 struct dc_link *link,
2299 struct dc_link_settings *known_limit_link_setting,
2303 bool success = false;
2305 for (i = 0; i < attempts; i++) {
2307 enum dc_connection_type type = dc_connection_none;
2309 memset(&link->verified_link_cap, 0,
2310 sizeof(struct dc_link_settings));
2311 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2312 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2313 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2314 link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2316 } else if (dp_verify_link_cap(link,
2317 &link->reported_link_cap,
2318 &fail_count) && fail_count == 0) {
2327 bool dp_verify_mst_link_cap(
2328 struct dc_link *link)
2330 struct dc_link_settings max_link_cap = {0};
2332 max_link_cap = get_max_link_cap(link);
2333 link->verified_link_cap = get_common_supported_link_settings(
2334 link->reported_link_cap,
2340 static struct dc_link_settings get_common_supported_link_settings(
2341 struct dc_link_settings link_setting_a,
2342 struct dc_link_settings link_setting_b)
2344 struct dc_link_settings link_settings = {0};
2346 link_settings.lane_count =
2347 (link_setting_a.lane_count <=
2348 link_setting_b.lane_count) ?
2349 link_setting_a.lane_count :
2350 link_setting_b.lane_count;
2351 link_settings.link_rate =
2352 (link_setting_a.link_rate <=
2353 link_setting_b.link_rate) ?
2354 link_setting_a.link_rate :
2355 link_setting_b.link_rate;
2356 link_settings.link_spread = LINK_SPREAD_DISABLED;
2358 /* in DP compliance test, DPR-120 may have
2359 * a random value in its MAX_LINK_BW dpcd field.
2360 * We map it to the maximum supported link rate that
2361 * is smaller than MAX_LINK_BW in this case.
2363 if (link_settings.link_rate > LINK_RATE_HIGH3) {
2364 link_settings.link_rate = LINK_RATE_HIGH3;
2365 } else if (link_settings.link_rate < LINK_RATE_HIGH3
2366 && link_settings.link_rate > LINK_RATE_HIGH2) {
2367 link_settings.link_rate = LINK_RATE_HIGH2;
2368 } else if (link_settings.link_rate < LINK_RATE_HIGH2
2369 && link_settings.link_rate > LINK_RATE_HIGH) {
2370 link_settings.link_rate = LINK_RATE_HIGH;
2371 } else if (link_settings.link_rate < LINK_RATE_HIGH
2372 && link_settings.link_rate > LINK_RATE_LOW) {
2373 link_settings.link_rate = LINK_RATE_LOW;
2374 } else if (link_settings.link_rate < LINK_RATE_LOW) {
2375 link_settings.link_rate = LINK_RATE_UNKNOWN;
2378 return link_settings;
2381 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2383 return lane_count <= LANE_COUNT_ONE;
2386 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2388 return link_rate <= LINK_RATE_LOW;
2391 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2393 switch (lane_count) {
2394 case LANE_COUNT_FOUR:
2395 return LANE_COUNT_TWO;
2396 case LANE_COUNT_TWO:
2397 return LANE_COUNT_ONE;
2398 case LANE_COUNT_ONE:
2399 return LANE_COUNT_UNKNOWN;
2401 return LANE_COUNT_UNKNOWN;
2405 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2407 switch (link_rate) {
2408 case LINK_RATE_HIGH3:
2409 return LINK_RATE_HIGH2;
2410 case LINK_RATE_HIGH2:
2411 return LINK_RATE_HIGH;
2412 case LINK_RATE_HIGH:
2413 return LINK_RATE_LOW;
2415 return LINK_RATE_UNKNOWN;
2417 return LINK_RATE_UNKNOWN;
2421 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2423 switch (lane_count) {
2424 case LANE_COUNT_ONE:
2425 return LANE_COUNT_TWO;
2426 case LANE_COUNT_TWO:
2427 return LANE_COUNT_FOUR;
2429 return LANE_COUNT_UNKNOWN;
2433 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2435 switch (link_rate) {
2437 return LINK_RATE_HIGH;
2438 case LINK_RATE_HIGH:
2439 return LINK_RATE_HIGH2;
2440 case LINK_RATE_HIGH2:
2441 return LINK_RATE_HIGH3;
2443 return LINK_RATE_UNKNOWN;
2448 * function: set link rate and lane count fallback based
2449 * on current link setting and last link training result
2451 * true - link setting could be set
2452 * false - has reached minimum setting
2453 * and no further fallback could be done
2455 static bool decide_fallback_link_setting(
2456 struct dc_link_settings initial_link_settings,
2457 struct dc_link_settings *current_link_setting,
2458 enum link_training_result training_result)
2460 if (!current_link_setting)
2463 switch (training_result) {
2464 case LINK_TRAINING_CR_FAIL_LANE0:
2465 case LINK_TRAINING_CR_FAIL_LANE1:
2466 case LINK_TRAINING_CR_FAIL_LANE23:
2467 case LINK_TRAINING_LQA_FAIL:
2469 if (!reached_minimum_link_rate
2470 (current_link_setting->link_rate)) {
2471 current_link_setting->link_rate =
2473 current_link_setting->link_rate);
2474 } else if (!reached_minimum_lane_count
2475 (current_link_setting->lane_count)) {
2476 current_link_setting->link_rate =
2477 initial_link_settings.link_rate;
2478 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2480 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2481 current_link_setting->lane_count =
2483 else if (training_result ==
2484 LINK_TRAINING_CR_FAIL_LANE23)
2485 current_link_setting->lane_count =
2488 current_link_setting->lane_count =
2490 current_link_setting->lane_count);
2496 case LINK_TRAINING_EQ_FAIL_EQ:
2498 if (!reached_minimum_lane_count
2499 (current_link_setting->lane_count)) {
2500 current_link_setting->lane_count =
2502 current_link_setting->lane_count);
2503 } else if (!reached_minimum_link_rate
2504 (current_link_setting->link_rate)) {
2505 current_link_setting->link_rate =
2507 current_link_setting->link_rate);
2513 case LINK_TRAINING_EQ_FAIL_CR:
2515 if (!reached_minimum_link_rate
2516 (current_link_setting->link_rate)) {
2517 current_link_setting->link_rate =
2519 current_link_setting->link_rate);
2531 bool dp_validate_mode_timing(
2532 struct dc_link *link,
2533 const struct dc_crtc_timing *timing)
2538 const struct dc_link_settings *link_setting;
2540 /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
2541 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
2542 !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
2543 dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
2546 /*always DP fail safe mode*/
2547 if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2548 timing->h_addressable == (uint32_t) 640 &&
2549 timing->v_addressable == (uint32_t) 480)
2552 link_setting = dc_link_get_link_cap(link);
2554 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2555 /*if (flags.DYNAMIC_VALIDATION == 1 &&
2556 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2557 link_setting = &link->verified_link_cap;
2560 req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2561 max_bw = dc_link_bandwidth_kbps(link, link_setting);
2563 if (req_bw <= max_bw) {
2564 /* remember the biggest mode here, during
2565 * initial link training (to get
2566 * verified_link_cap), LS sends event about
2567 * cannot train at reported cap to upper
2568 * layer and upper layer will re-enumerate modes.
2569 * this is not necessary if the lower
2570 * verified_link_cap is enough to drive
2573 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2574 /* if (flags.DYNAMIC_VALIDATION == 1)
2575 dpsst->max_req_bw_for_verified_linkcap = dal_max(
2576 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2582 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2584 struct dc_link_settings initial_link_setting = {
2585 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2586 struct dc_link_settings current_link_setting =
2587 initial_link_setting;
2590 if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2593 /* search for the minimum link setting that:
2594 * 1. is supported according to the link training result
2595 * 2. could support the b/w requested by the timing
2597 while (current_link_setting.link_rate <=
2598 link->verified_link_cap.link_rate) {
2599 link_bw = dc_link_bandwidth_kbps(
2601 ¤t_link_setting);
2602 if (req_bw <= link_bw) {
2603 *link_setting = current_link_setting;
2607 if (current_link_setting.lane_count <
2608 link->verified_link_cap.lane_count) {
2609 current_link_setting.lane_count =
2610 increase_lane_count(
2611 current_link_setting.lane_count);
2613 current_link_setting.link_rate =
2615 current_link_setting.link_rate);
2616 current_link_setting.lane_count =
2617 initial_link_setting.lane_count;
2624 bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2626 struct dc_link_settings initial_link_setting;
2627 struct dc_link_settings current_link_setting;
2631 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
2632 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
2634 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
2635 link->dpcd_caps.edp_supported_link_rates_count == 0) {
2636 *link_setting = link->verified_link_cap;
2640 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2641 initial_link_setting.lane_count = LANE_COUNT_ONE;
2642 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2643 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2644 initial_link_setting.use_link_rate_set = true;
2645 initial_link_setting.link_rate_set = 0;
2646 current_link_setting = initial_link_setting;
2648 /* search for the minimum link setting that:
2649 * 1. is supported according to the link training result
2650 * 2. could support the b/w requested by the timing
2652 while (current_link_setting.link_rate <=
2653 link->verified_link_cap.link_rate) {
2654 link_bw = dc_link_bandwidth_kbps(
2656 ¤t_link_setting);
2657 if (req_bw <= link_bw) {
2658 *link_setting = current_link_setting;
2662 if (current_link_setting.lane_count <
2663 link->verified_link_cap.lane_count) {
2664 current_link_setting.lane_count =
2665 increase_lane_count(
2666 current_link_setting.lane_count);
2668 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2669 current_link_setting.link_rate_set++;
2670 current_link_setting.link_rate =
2671 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2672 current_link_setting.lane_count =
2673 initial_link_setting.lane_count;
2681 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2683 *link_setting = link->verified_link_cap;
2687 void decide_link_settings(struct dc_stream_state *stream,
2688 struct dc_link_settings *link_setting)
2690 struct dc_link *link;
2693 req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2695 link = stream->link;
2697 /* if preferred is specified through AMDDP, use it, if it's enough
2700 if (link->preferred_link_setting.lane_count !=
2701 LANE_COUNT_UNKNOWN &&
2702 link->preferred_link_setting.link_rate !=
2703 LINK_RATE_UNKNOWN) {
2704 *link_setting = link->preferred_link_setting;
2708 /* MST doesn't perform link training for now
2709 * TODO: add MST specific link training routine
2711 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2712 if (decide_mst_link_settings(link, link_setting))
2714 } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2715 if (decide_edp_link_settings(link, link_setting, req_bw))
2717 } else if (decide_dp_link_settings(link, link_setting, req_bw))
2720 BREAK_TO_DEBUGGER();
2721 ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2723 *link_setting = link->verified_link_cap;
2726 /*************************Short Pulse IRQ***************************/
2727 static bool allow_hpd_rx_irq(const struct dc_link *link)
2730 * Don't handle RX IRQ unless one of following is met:
2731 * 1) The link is established (cur_link_settings != unknown)
2732 * 2) We know we're dealing with a branch device, SST or MST
2735 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2736 is_dp_branch_device(link))
2742 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2744 union dpcd_psr_configuration psr_configuration;
2746 if (!link->psr_settings.psr_feature_enabled)
2749 dm_helpers_dp_read_dpcd(
2752 368,/*DpcdAddress_PSR_Enable_Cfg*/
2753 &psr_configuration.raw,
2754 sizeof(psr_configuration.raw));
2757 if (psr_configuration.bits.ENABLE) {
2758 unsigned char dpcdbuf[3] = {0};
2759 union psr_error_status psr_error_status;
2760 union psr_sink_psr_status psr_sink_psr_status;
2762 dm_helpers_dp_read_dpcd(
2765 0x2006, /*DpcdAddress_PSR_Error_Status*/
2766 (unsigned char *) dpcdbuf,
2769 /*DPCD 2006h ERROR STATUS*/
2770 psr_error_status.raw = dpcdbuf[0];
2771 /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
2772 psr_sink_psr_status.raw = dpcdbuf[2];
2774 if (psr_error_status.bits.LINK_CRC_ERROR ||
2775 psr_error_status.bits.RFB_STORAGE_ERROR ||
2776 psr_error_status.bits.VSC_SDP_ERROR) {
2777 /* Acknowledge and clear error bits */
2778 dm_helpers_dp_write_dpcd(
2781 8198,/*DpcdAddress_PSR_Error_Status*/
2782 &psr_error_status.raw,
2783 sizeof(psr_error_status.raw));
2785 /* PSR error, disable and re-enable PSR */
2786 dc_link_set_psr_allow_active(link, false, true, false);
2787 dc_link_set_psr_allow_active(link, true, true, false);
2790 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2791 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2792 /* No error is detect, PSR is active.
2793 * We should return with IRQ_HPD handled without
2794 * checking for loss of sync since PSR would have
2795 * powered down main link.
2803 static void dp_test_send_link_training(struct dc_link *link)
2805 struct dc_link_settings link_settings = {0};
2807 core_link_read_dpcd(
2810 (unsigned char *)(&link_settings.lane_count),
2812 core_link_read_dpcd(
2815 (unsigned char *)(&link_settings.link_rate),
2818 /* Set preferred link settings */
2819 link->verified_link_cap.lane_count = link_settings.lane_count;
2820 link->verified_link_cap.link_rate = link_settings.link_rate;
2822 dp_retrain_link_dp_test(link, &link_settings, false);
2825 /* TODO Raven hbr2 compliance eye output is unstable
2826 * (toggling on and off) with debugger break
2827 * This caueses intermittent PHY automation failure
2828 * Need to look into the root cause */
2829 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2831 union phy_test_pattern dpcd_test_pattern;
2832 union lane_adjust dpcd_lane_adjustment[2];
2833 unsigned char dpcd_post_cursor_2_adjustment = 0;
2834 unsigned char test_pattern_buffer[
2835 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2836 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2837 unsigned int test_pattern_size = 0;
2838 enum dp_test_pattern test_pattern;
2839 struct dc_link_training_settings link_settings;
2840 union lane_adjust dpcd_lane_adjust;
2842 struct link_training_settings link_training_settings;
2845 dpcd_test_pattern.raw = 0;
2846 memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2847 memset(&link_settings, 0, sizeof(link_settings));
2849 /* get phy test pattern and pattern parameters from DP receiver */
2850 core_link_read_dpcd(
2852 DP_PHY_TEST_PATTERN,
2853 &dpcd_test_pattern.raw,
2854 sizeof(dpcd_test_pattern));
2855 core_link_read_dpcd(
2857 DP_ADJUST_REQUEST_LANE0_1,
2858 &dpcd_lane_adjustment[0].raw,
2859 sizeof(dpcd_lane_adjustment));
2861 /*get post cursor 2 parameters
2862 * For DP 1.1a or eariler, this DPCD register's value is 0
2863 * For DP 1.2 or later:
2864 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2865 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2867 core_link_read_dpcd(
2869 DP_ADJUST_REQUEST_POST_CURSOR2,
2870 &dpcd_post_cursor_2_adjustment,
2871 sizeof(dpcd_post_cursor_2_adjustment));
2873 /* translate request */
2874 switch (dpcd_test_pattern.bits.PATTERN) {
2875 case PHY_TEST_PATTERN_D10_2:
2876 test_pattern = DP_TEST_PATTERN_D102;
2878 case PHY_TEST_PATTERN_SYMBOL_ERROR:
2879 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2881 case PHY_TEST_PATTERN_PRBS7:
2882 test_pattern = DP_TEST_PATTERN_PRBS7;
2884 case PHY_TEST_PATTERN_80BIT_CUSTOM:
2885 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2887 case PHY_TEST_PATTERN_CP2520_1:
2888 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2889 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2890 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2891 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2893 case PHY_TEST_PATTERN_CP2520_2:
2894 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2895 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2896 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2897 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2899 case PHY_TEST_PATTERN_CP2520_3:
2900 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2903 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2907 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
2908 test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2909 DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1;
2910 core_link_read_dpcd(
2912 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2913 test_pattern_buffer,
2917 /* prepare link training settings */
2918 link_settings.link = link->cur_link_settings;
2920 for (lane = 0; lane <
2921 (unsigned int)(link->cur_link_settings.lane_count);
2923 dpcd_lane_adjust.raw =
2924 get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2925 link_settings.lane_settings[lane].VOLTAGE_SWING =
2926 (enum dc_voltage_swing)
2927 (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2928 link_settings.lane_settings[lane].PRE_EMPHASIS =
2929 (enum dc_pre_emphasis)
2930 (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2931 link_settings.lane_settings[lane].POST_CURSOR2 =
2932 (enum dc_post_cursor2)
2933 ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2936 for (i = 0; i < 4; i++)
2937 link_training_settings.lane_settings[i] =
2938 link_settings.lane_settings[i];
2939 link_training_settings.link_settings = link_settings.link;
2940 link_training_settings.allow_invalid_msa_timing_param = false;
2941 /*Usage: Measure DP physical lane signal
2942 * by DP SI test equipment automatically.
2943 * PHY test pattern request is generated by equipment via HPD interrupt.
2944 * HPD needs to be active all the time. HPD should be active
2945 * all the time. Do not touch it.
2946 * forward request to DS
2948 dc_link_dp_set_test_pattern(
2951 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2952 &link_training_settings,
2953 test_pattern_buffer,
2957 static void dp_test_send_link_test_pattern(struct dc_link *link)
2959 union link_test_pattern dpcd_test_pattern;
2960 union test_misc dpcd_test_params;
2961 enum dp_test_pattern test_pattern;
2962 enum dp_test_pattern_color_space test_pattern_color_space =
2963 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2964 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2965 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2966 struct pipe_ctx *pipe_ctx = NULL;
2969 memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2970 memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2972 for (i = 0; i < MAX_PIPES; i++) {
2973 if (pipes[i].stream == NULL)
2976 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
2977 pipe_ctx = &pipes[i];
2982 if (pipe_ctx == NULL)
2985 /* get link test pattern and pattern parameters */
2986 core_link_read_dpcd(
2989 &dpcd_test_pattern.raw,
2990 sizeof(dpcd_test_pattern));
2991 core_link_read_dpcd(
2994 &dpcd_test_params.raw,
2995 sizeof(dpcd_test_params));
2997 switch (dpcd_test_pattern.bits.PATTERN) {
2998 case LINK_TEST_PATTERN_COLOR_RAMP:
2999 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
3001 case LINK_TEST_PATTERN_VERTICAL_BARS:
3002 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
3003 break; /* black and white */
3004 case LINK_TEST_PATTERN_COLOR_SQUARES:
3005 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
3006 TEST_DYN_RANGE_VESA ?
3007 DP_TEST_PATTERN_COLOR_SQUARES :
3008 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
3011 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
3015 if (dpcd_test_params.bits.CLR_FORMAT == 0)
3016 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
3018 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
3019 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
3020 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
3022 switch (dpcd_test_params.bits.BPC) {
3024 requestColorDepth = COLOR_DEPTH_666;
3027 requestColorDepth = COLOR_DEPTH_888;
3030 requestColorDepth = COLOR_DEPTH_101010;
3033 requestColorDepth = COLOR_DEPTH_121212;
3039 switch (dpcd_test_params.bits.CLR_FORMAT) {
3041 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3044 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
3047 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
3050 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3055 if (requestColorDepth != COLOR_DEPTH_UNDEFINED
3056 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
3057 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
3059 pipe_ctx->stream->timing.display_color_depth,
3061 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
3064 dp_update_dsc_config(pipe_ctx);
3066 dc_link_dp_set_test_pattern(
3069 test_pattern_color_space,
3075 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
3077 union audio_test_mode dpcd_test_mode = {0};
3078 struct audio_test_pattern_type dpcd_pattern_type = {0};
3079 union audio_test_pattern_period dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
3080 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3082 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3083 struct pipe_ctx *pipe_ctx = &pipes[0];
3084 unsigned int channel_count;
3085 unsigned int channel = 0;
3086 unsigned int modes = 0;
3087 unsigned int sampling_rate_in_hz = 0;
3089 // get audio test mode and test pattern parameters
3090 core_link_read_dpcd(
3093 &dpcd_test_mode.raw,
3094 sizeof(dpcd_test_mode));
3096 core_link_read_dpcd(
3098 DP_TEST_AUDIO_PATTERN_TYPE,
3099 &dpcd_pattern_type.value,
3100 sizeof(dpcd_pattern_type));
3102 channel_count = dpcd_test_mode.bits.channel_count + 1;
3104 // read pattern periods for requested channels when sawTooth pattern is requested
3105 if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
3106 dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
3108 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
3109 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3110 // read period for each channel
3111 for (channel = 0; channel < channel_count; channel++) {
3112 core_link_read_dpcd(
3114 DP_TEST_AUDIO_PERIOD_CH1 + channel,
3115 &dpcd_pattern_period[channel].raw,
3116 sizeof(dpcd_pattern_period[channel]));
3120 // translate sampling rate
3121 switch (dpcd_test_mode.bits.sampling_rate) {
3122 case AUDIO_SAMPLING_RATE_32KHZ:
3123 sampling_rate_in_hz = 32000;
3125 case AUDIO_SAMPLING_RATE_44_1KHZ:
3126 sampling_rate_in_hz = 44100;
3128 case AUDIO_SAMPLING_RATE_48KHZ:
3129 sampling_rate_in_hz = 48000;
3131 case AUDIO_SAMPLING_RATE_88_2KHZ:
3132 sampling_rate_in_hz = 88200;
3134 case AUDIO_SAMPLING_RATE_96KHZ:
3135 sampling_rate_in_hz = 96000;
3137 case AUDIO_SAMPLING_RATE_176_4KHZ:
3138 sampling_rate_in_hz = 176400;
3140 case AUDIO_SAMPLING_RATE_192KHZ:
3141 sampling_rate_in_hz = 192000;
3144 sampling_rate_in_hz = 0;
3148 link->audio_test_data.flags.test_requested = 1;
3149 link->audio_test_data.flags.disable_video = disable_video;
3150 link->audio_test_data.sampling_rate = sampling_rate_in_hz;
3151 link->audio_test_data.channel_count = channel_count;
3152 link->audio_test_data.pattern_type = test_pattern;
3154 if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3155 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3156 link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3161 static void handle_automated_test(struct dc_link *link)
3163 union test_request test_request;
3164 union test_response test_response;
3166 memset(&test_request, 0, sizeof(test_request));
3167 memset(&test_response, 0, sizeof(test_response));
3169 core_link_read_dpcd(
3173 sizeof(union test_request));
3174 if (test_request.bits.LINK_TRAINING) {
3175 /* ACK first to let DP RX test box monitor LT sequence */
3176 test_response.bits.ACK = 1;
3177 core_link_write_dpcd(
3181 sizeof(test_response));
3182 dp_test_send_link_training(link);
3183 /* no acknowledge request is needed again */
3184 test_response.bits.ACK = 0;
3186 if (test_request.bits.LINK_TEST_PATTRN) {
3187 dp_test_send_link_test_pattern(link);
3188 test_response.bits.ACK = 1;
3191 if (test_request.bits.AUDIO_TEST_PATTERN) {
3192 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3193 test_response.bits.ACK = 1;
3196 if (test_request.bits.PHY_TEST_PATTERN) {
3197 dp_test_send_phy_test_pattern(link);
3198 test_response.bits.ACK = 1;
3201 /* send request acknowledgment */
3202 if (test_response.bits.ACK)
3203 core_link_write_dpcd(
3207 sizeof(test_response));
3210 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
3212 union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
3213 union device_service_irq device_service_clear = { { 0 } };
3214 enum dc_status result;
3215 bool status = false;
3216 struct pipe_ctx *pipe_ctx;
3220 *out_link_loss = false;
3221 /* For use cases related to down stream connection status change,
3222 * PSR and device auto test, refer to function handle_sst_hpd_irq
3225 DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
3226 __func__, link->link_index);
3229 /* All the "handle_hpd_irq_xxx()" methods
3230 * should be called only after
3231 * dal_dpsst_ls_read_hpd_irq_data
3232 * Order of calls is important too
3234 result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
3235 if (out_hpd_irq_dpcd_data)
3236 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
3238 if (result != DC_OK) {
3239 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
3244 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3245 device_service_clear.bits.AUTOMATED_TEST = 1;
3246 core_link_write_dpcd(
3248 DP_DEVICE_SERVICE_IRQ_VECTOR,
3249 &device_service_clear.raw,
3250 sizeof(device_service_clear.raw));
3251 device_service_clear.raw = 0;
3252 handle_automated_test(link);
3256 if (!allow_hpd_rx_irq(link)) {
3257 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3258 __func__, link->link_index);
3262 if (handle_hpd_irq_psr_sink(link))
3263 /* PSR-related error was detected and handled */
3266 /* If PSR-related error handled, Main link may be off,
3267 * so do not handle as a normal sink status change interrupt.
3270 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3273 /* check if we have MST msg and return since we poll for it */
3274 if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3277 /* For now we only handle 'Downstream port status' case.
3278 * If we got sink count changed it means
3279 * Downstream port status changed,
3280 * then DM should call DC to do the detection.
3281 * NOTE: Do not handle link loss on eDP since it is internal link*/
3282 if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3283 hpd_rx_irq_check_link_loss_status(
3285 &hpd_irq_dpcd_data)) {
3286 /* Connectivity log: link loss */
3287 CONN_DATA_LINK_LOSS(link,
3288 hpd_irq_dpcd_data.raw,
3289 sizeof(hpd_irq_dpcd_data),
3292 for (i = 0; i < MAX_PIPES; i++) {
3293 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3294 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3298 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3302 for (i = 0; i < MAX_PIPES; i++) {
3303 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3304 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3305 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3306 core_link_disable_stream(pipe_ctx);
3309 for (i = 0; i < MAX_PIPES; i++) {
3310 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3311 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3312 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3313 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3318 *out_link_loss = true;
3321 if (link->type == dc_connection_sst_branch &&
3322 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3323 != link->dpcd_sink_count)
3326 /* reasons for HPD RX:
3327 * 1. Link Loss - ie Re-train the Link
3328 * 2. MST sideband message
3329 * 3. Automated Test - ie. Internal Commit
3330 * 4. CP (copy protection) - (not interesting for DM???)
3332 * 6. Downstream Port status changed
3333 * -ie. Detect - this the only one
3334 * which is interesting for DM because
3335 * it must call dc_link_detect.
3340 /*query dpcd for version and mst cap addresses*/
3341 bool is_mst_supported(struct dc_link *link)
3344 enum dc_status st = DC_OK;
3348 if (link->preferred_training_settings.mst_enable &&
3349 *link->preferred_training_settings.mst_enable == false) {
3356 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3359 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3361 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3362 &cap.raw, sizeof(cap));
3363 if (st == DC_OK && cap.bits.MST_CAP == 1)
3370 bool is_dp_active_dongle(const struct dc_link *link)
3372 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
3373 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
3376 bool is_dp_branch_device(const struct dc_link *link)
3378 return link->dpcd_caps.is_branch_dev;
3381 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3384 case DOWN_STREAM_MAX_8BPC:
3386 case DOWN_STREAM_MAX_10BPC:
3388 case DOWN_STREAM_MAX_12BPC:
3390 case DOWN_STREAM_MAX_16BPC:
3399 static void read_dp_device_vendor_id(struct dc_link *link)
3401 struct dp_device_vendor_id dp_id;
3403 /* read IEEE branch device id */
3404 core_link_read_dpcd(
3410 link->dpcd_caps.branch_dev_id =
3411 (dp_id.ieee_oui[0] << 16) +
3412 (dp_id.ieee_oui[1] << 8) +
3416 link->dpcd_caps.branch_dev_name,
3417 dp_id.ieee_device_id,
3418 sizeof(dp_id.ieee_device_id));
3423 static void get_active_converter_info(
3424 uint8_t data, struct dc_link *link)
3426 union dp_downstream_port_present ds_port = { .byte = data };
3427 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3429 /* decode converter info*/
3430 if (!ds_port.fields.PORT_PRESENT) {
3431 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3432 ddc_service_set_dongle_type(link->ddc,
3433 link->dpcd_caps.dongle_type);
3434 link->dpcd_caps.is_branch_dev = false;
3438 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3439 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3441 switch (ds_port.fields.PORT_TYPE) {
3442 case DOWNSTREAM_VGA:
3443 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3445 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3446 /* At this point we don't know is it DVI or HDMI or DP++,
3448 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3451 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3455 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3456 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3457 union dwnstream_port_caps_byte0 *port_caps =
3458 (union dwnstream_port_caps_byte0 *)det_caps;
3459 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3460 det_caps, sizeof(det_caps)) == DC_OK) {
3462 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3463 /*Handle DP case as DONGLE_NONE*/
3464 case DOWN_STREAM_DETAILED_DP:
3465 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3467 case DOWN_STREAM_DETAILED_VGA:
3468 link->dpcd_caps.dongle_type =
3469 DISPLAY_DONGLE_DP_VGA_CONVERTER;
3471 case DOWN_STREAM_DETAILED_DVI:
3472 link->dpcd_caps.dongle_type =
3473 DISPLAY_DONGLE_DP_DVI_CONVERTER;
3475 case DOWN_STREAM_DETAILED_HDMI:
3476 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3477 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3478 link->dpcd_caps.dongle_type =
3479 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3481 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3482 if (ds_port.fields.DETAILED_CAPS) {
3484 union dwnstream_port_caps_byte3_hdmi
3485 hdmi_caps = {.raw = det_caps[3] };
3486 union dwnstream_port_caps_byte2
3487 hdmi_color_caps = {.raw = det_caps[2] };
3488 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3491 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3492 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3493 /*YCBCR capability only for HDMI case*/
3494 if (port_caps->bits.DWN_STRM_PORTX_TYPE
3495 == DOWN_STREAM_DETAILED_HDMI) {
3496 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3497 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3498 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3499 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3500 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3501 hdmi_caps.bits.YCrCr422_CONVERSION;
3502 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3503 hdmi_caps.bits.YCrCr420_CONVERSION;
3506 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3507 translate_dpcd_max_bpc(
3508 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3510 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3511 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3519 ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3522 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3524 core_link_read_dpcd(
3526 DP_BRANCH_REVISION_START,
3527 (uint8_t *)&dp_hw_fw_revision,
3528 sizeof(dp_hw_fw_revision));
3530 link->dpcd_caps.branch_hw_revision =
3531 dp_hw_fw_revision.ieee_hw_rev;
3534 link->dpcd_caps.branch_fw_revision,
3535 dp_hw_fw_revision.ieee_fw_rev,
3536 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3540 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3545 if (!link->dpcd_caps.dpcd_rev.raw) {
3547 dp_receiver_power_ctrl(link, true);
3548 core_link_read_dpcd(link, DP_DPCD_REV,
3550 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3553 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3556 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3557 switch (link->dpcd_caps.branch_dev_id) {
3558 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3559 * all internal circuits including AUX communication preventing
3560 * reading DPCD table and EDID (spec violation).
3561 * Encoder will skip DP RX power down on disable_output to
3562 * keep receiver powered all the time.*/
3563 case DP_BRANCH_DEVICE_ID_0010FA:
3564 case DP_BRANCH_DEVICE_ID_0080E1:
3565 case DP_BRANCH_DEVICE_ID_00E04C:
3566 link->wa_flags.dp_keep_receiver_powered = true;
3569 /* TODO: May need work around for other dongles. */
3571 link->wa_flags.dp_keep_receiver_powered = false;
3575 link->wa_flags.dp_keep_receiver_powered = false;
3578 /* Read additional sink caps defined in source specific DPCD area
3579 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3581 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3588 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3591 link->dpcd_sink_ext_caps.raw = dpcd_data;
3595 bool dp_retrieve_lttpr_cap(struct dc_link *link)
3597 uint8_t lttpr_dpcd_data[6];
3598 bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable;
3599 bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
3600 enum dc_status status = DC_ERROR_UNEXPECTED;
3601 bool is_lttpr_present = false;
3603 memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3606 * Logic to determine LTTPR mode
3608 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3609 if (vbios_lttpr_enable && vbios_lttpr_interop)
3610 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3611 else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3612 if (link->dc->config.allow_lttpr_non_transparent_mode)
3613 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3615 link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3616 } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3617 if (!link->dc->config.allow_lttpr_non_transparent_mode
3618 || !link->dc->caps.extended_aux_timeout_support)
3619 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3621 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3624 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
3625 /* By reading LTTPR capability, RX assumes that we will enable
3626 * LTTPR extended aux timeout if LTTPR is present.
3628 status = core_link_read_dpcd(
3630 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3632 sizeof(lttpr_dpcd_data));
3633 if (status != DC_OK) {
3634 dm_error("%s: Read LTTPR caps data failed.\n", __func__);
3638 link->dpcd_caps.lttpr_caps.revision.raw =
3639 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3640 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3642 link->dpcd_caps.lttpr_caps.max_link_rate =
3643 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3644 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3646 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3647 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3648 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3650 link->dpcd_caps.lttpr_caps.max_lane_count =
3651 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3652 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3654 link->dpcd_caps.lttpr_caps.mode =
3655 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3656 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3658 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3659 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3660 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3662 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
3663 is_lttpr_present = (dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
3664 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3665 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3666 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3667 if (is_lttpr_present) {
3668 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3669 configure_lttpr_mode_transparent(link);
3671 link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3673 return is_lttpr_present;
3676 static bool retrieve_link_cap(struct dc_link *link)
3678 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3679 * which means size 16 will be good for both of those DPCD register block reads
3681 uint8_t dpcd_data[16];
3682 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3684 uint8_t dpcd_dprx_data = '\0';
3685 uint8_t dpcd_power_state = '\0';
3687 struct dp_device_vendor_id sink_id;
3688 union down_stream_port_count down_strm_port_count;
3689 union edp_configuration_cap edp_config_cap;
3690 union dp_downstream_port_present ds_port = { 0 };
3691 enum dc_status status = DC_ERROR_UNEXPECTED;
3692 uint32_t read_dpcd_retry_cnt = 3;
3694 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3695 const uint32_t post_oui_delay = 30; // 30ms
3696 bool is_lttpr_present = false;
3698 memset(dpcd_data, '\0', sizeof(dpcd_data));
3699 memset(&down_strm_port_count,
3700 '\0', sizeof(union down_stream_port_count));
3701 memset(&edp_config_cap, '\0',
3702 sizeof(union edp_configuration_cap));
3704 /* if extended timeout is supported in hardware,
3705 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3706 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3708 dc_link_aux_try_to_configure_timeout(link->ddc,
3709 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3711 is_lttpr_present = dp_retrieve_lttpr_cap(link);
3713 status = core_link_read_dpcd(link, DP_SET_POWER,
3714 &dpcd_power_state, sizeof(dpcd_power_state));
3716 /* Delay 1 ms if AUX CH is in power down state. Based on spec
3717 * section 2.3.1.2, if AUX CH may be powered down due to
3718 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3719 * signal and may need up to 1 ms before being able to reply.
3721 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3724 dpcd_set_source_specific_data(link);
3725 /* Sink may need to configure internals based on vendor, so allow some
3726 * time before proceeding with possibly vendor specific transactions
3728 msleep(post_oui_delay);
3730 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3731 status = core_link_read_dpcd(
3736 if (status == DC_OK)
3740 if (status != DC_OK) {
3741 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
3745 if (!is_lttpr_present)
3746 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3749 union training_aux_rd_interval aux_rd_interval;
3751 aux_rd_interval.raw =
3752 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3754 link->dpcd_caps.ext_receiver_cap_field_present =
3755 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3757 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3758 uint8_t ext_cap_data[16];
3760 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3761 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3762 status = core_link_read_dpcd(
3766 sizeof(ext_cap_data));
3767 if (status == DC_OK) {
3768 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3772 if (status != DC_OK)
3773 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3777 link->dpcd_caps.dpcd_rev.raw =
3778 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3780 if (link->dpcd_caps.ext_receiver_cap_field_present) {
3781 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3782 status = core_link_read_dpcd(
3784 DP_DPRX_FEATURE_ENUMERATION_LIST,
3786 sizeof(dpcd_dprx_data));
3787 if (status == DC_OK)
3791 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3793 if (status != DC_OK)
3794 dm_error("%s: Read DPRX caps data failed.\n", __func__);
3798 link->dpcd_caps.dprx_feature.raw = 0;
3802 /* Error condition checking...
3803 * It is impossible for Sink to report Max Lane Count = 0.
3804 * It is possible for Sink to report Max Link Rate = 0, if it is
3805 * an eDP device that is reporting specialized link rates in the
3806 * SUPPORTED_LINK_RATE table.
3808 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3811 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3814 read_dp_device_vendor_id(link);
3816 get_active_converter_info(ds_port.byte, link);
3818 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3820 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3823 link->dpcd_caps.allow_invalid_MSA_timing_param =
3824 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3826 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3827 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3829 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3830 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3832 link->reported_link_cap.lane_count =
3833 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3834 link->reported_link_cap.link_rate = dpcd_data[
3835 DP_MAX_LINK_RATE - DP_DPCD_REV];
3836 link->reported_link_cap.link_spread =
3837 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3838 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3840 edp_config_cap.raw = dpcd_data[
3841 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3842 link->dpcd_caps.panel_mode_edp =
3843 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3844 link->dpcd_caps.dpcd_display_control_capable =
3845 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3847 link->test_pattern_enabled = false;
3848 link->compliance_test_state.raw = 0;
3850 /* read sink count */
3851 core_link_read_dpcd(link,
3853 &link->dpcd_caps.sink_count.raw,
3854 sizeof(link->dpcd_caps.sink_count.raw));
3856 /* read sink ieee oui */
3857 core_link_read_dpcd(link,
3859 (uint8_t *)(&sink_id),
3862 link->dpcd_caps.sink_dev_id =
3863 (sink_id.ieee_oui[0] << 16) +
3864 (sink_id.ieee_oui[1] << 8) +
3865 (sink_id.ieee_oui[2]);
3868 link->dpcd_caps.sink_dev_id_str,
3869 sink_id.ieee_device_id,
3870 sizeof(sink_id.ieee_device_id));
3872 /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3874 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3876 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3877 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3878 sizeof(str_mbp_2017))) {
3879 link->reported_link_cap.link_rate = 0x0c;
3883 core_link_read_dpcd(
3885 DP_SINK_HW_REVISION_START,
3886 (uint8_t *)&dp_hw_fw_revision,
3887 sizeof(dp_hw_fw_revision));
3889 link->dpcd_caps.sink_hw_revision =
3890 dp_hw_fw_revision.ieee_hw_rev;
3893 link->dpcd_caps.sink_fw_revision,
3894 dp_hw_fw_revision.ieee_fw_rev,
3895 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3897 memset(&link->dpcd_caps.dsc_caps, '\0',
3898 sizeof(link->dpcd_caps.dsc_caps));
3899 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3900 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3901 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3902 status = core_link_read_dpcd(
3905 &link->dpcd_caps.fec_cap.raw,
3906 sizeof(link->dpcd_caps.fec_cap.raw));
3907 status = core_link_read_dpcd(
3910 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3911 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3912 status = core_link_read_dpcd(
3914 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3915 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3916 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3919 if (!dpcd_read_sink_ext_caps(link))
3920 link->dpcd_sink_ext_caps.raw = 0;
3922 /* Connectivity log: detection */
3923 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3928 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3930 uint8_t dpcd_data[16];
3931 uint32_t read_dpcd_retry_cnt = 3;
3932 enum dc_status status = DC_ERROR_UNEXPECTED;
3933 union dp_downstream_port_present ds_port = { 0 };
3934 union down_stream_port_count down_strm_port_count;
3935 union edp_configuration_cap edp_config_cap;
3939 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3940 status = core_link_read_dpcd(
3945 if (status == DC_OK)
3949 link->dpcd_caps.dpcd_rev.raw =
3950 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3952 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3955 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3958 get_active_converter_info(ds_port.byte, link);
3960 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3963 link->dpcd_caps.allow_invalid_MSA_timing_param =
3964 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3966 link->dpcd_caps.max_ln_count.raw = dpcd_data[
3967 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3969 link->dpcd_caps.max_down_spread.raw = dpcd_data[
3970 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3972 link->reported_link_cap.lane_count =
3973 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3974 link->reported_link_cap.link_rate = dpcd_data[
3975 DP_MAX_LINK_RATE - DP_DPCD_REV];
3976 link->reported_link_cap.link_spread =
3977 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3978 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3980 edp_config_cap.raw = dpcd_data[
3981 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3982 link->dpcd_caps.panel_mode_edp =
3983 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3984 link->dpcd_caps.dpcd_display_control_capable =
3985 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3990 bool detect_dp_sink_caps(struct dc_link *link)
3992 return retrieve_link_cap(link);
3994 /* dc init_hw has power encoder using default
3995 * signal for connector. For native DP, no
3996 * need to power up encoder again. If not native
3997 * DP, hw_init may need check signal or power up
4000 /* TODO save sink caps in link->sink */
4003 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
4005 enum dc_link_rate link_rate;
4006 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
4007 switch (link_rate_in_khz) {
4009 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
4012 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
4015 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
4018 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
4021 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2) - 3.24 Gbps/Lane
4024 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
4027 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2) - 5.40 Gbps/Lane
4030 link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3) - 8.10 Gbps/Lane
4033 link_rate = LINK_RATE_UNKNOWN;
4039 void detect_edp_sink_caps(struct dc_link *link)
4041 uint8_t supported_link_rates[16];
4043 uint32_t link_rate_in_khz;
4044 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
4045 uint8_t backlight_adj_cap;
4047 retrieve_link_cap(link);
4048 link->dpcd_caps.edp_supported_link_rates_count = 0;
4049 memset(supported_link_rates, 0, sizeof(supported_link_rates));
4052 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
4053 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
4055 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
4056 (link->dc->debug.optimize_edp_link_rate ||
4057 link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
4058 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
4059 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
4060 supported_link_rates, sizeof(supported_link_rates));
4062 for (entry = 0; entry < 16; entry += 2) {
4063 // DPCD register reports per-lane link rate = 16-bit link rate capability
4064 // value X 200 kHz. Need multiplier to find link rate in kHz.
4065 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
4066 supported_link_rates[entry]) * 200;
4068 if (link_rate_in_khz != 0) {
4069 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
4070 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
4071 link->dpcd_caps.edp_supported_link_rates_count++;
4073 if (link->reported_link_cap.link_rate < link_rate)
4074 link->reported_link_cap.link_rate = link_rate;
4078 link->verified_link_cap = link->reported_link_cap;
4080 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
4081 &backlight_adj_cap, sizeof(backlight_adj_cap));
4083 link->dpcd_caps.dynamic_backlight_capable_edp =
4084 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
4086 dc_link_set_default_brightness_aux(link);
4089 void dc_link_dp_enable_hpd(const struct dc_link *link)
4091 struct link_encoder *encoder = link->link_enc;
4093 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4094 encoder->funcs->enable_hpd(encoder);
4097 void dc_link_dp_disable_hpd(const struct dc_link *link)
4099 struct link_encoder *encoder = link->link_enc;
4101 if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4102 encoder->funcs->disable_hpd(encoder);
4105 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
4107 if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
4108 test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
4109 test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4115 static void set_crtc_test_pattern(struct dc_link *link,
4116 struct pipe_ctx *pipe_ctx,
4117 enum dp_test_pattern test_pattern,
4118 enum dp_test_pattern_color_space test_pattern_color_space)
4120 enum controller_dp_test_pattern controller_test_pattern;
4121 enum dc_color_depth color_depth = pipe_ctx->
4122 stream->timing.display_color_depth;
4123 struct bit_depth_reduction_params params;
4124 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
4125 int width = pipe_ctx->stream->timing.h_addressable +
4126 pipe_ctx->stream->timing.h_border_left +
4127 pipe_ctx->stream->timing.h_border_right;
4128 int height = pipe_ctx->stream->timing.v_addressable +
4129 pipe_ctx->stream->timing.v_border_bottom +
4130 pipe_ctx->stream->timing.v_border_top;
4132 memset(¶ms, 0, sizeof(params));
4134 switch (test_pattern) {
4135 case DP_TEST_PATTERN_COLOR_SQUARES:
4136 controller_test_pattern =
4137 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
4139 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4140 controller_test_pattern =
4141 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
4143 case DP_TEST_PATTERN_VERTICAL_BARS:
4144 controller_test_pattern =
4145 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
4147 case DP_TEST_PATTERN_HORIZONTAL_BARS:
4148 controller_test_pattern =
4149 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
4151 case DP_TEST_PATTERN_COLOR_RAMP:
4152 controller_test_pattern =
4153 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
4156 controller_test_pattern =
4157 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
4161 switch (test_pattern) {
4162 case DP_TEST_PATTERN_COLOR_SQUARES:
4163 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4164 case DP_TEST_PATTERN_VERTICAL_BARS:
4165 case DP_TEST_PATTERN_HORIZONTAL_BARS:
4166 case DP_TEST_PATTERN_COLOR_RAMP:
4168 /* disable bit depth reduction */
4169 pipe_ctx->stream->bit_depth_params = params;
4170 opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms);
4171 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4172 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4173 controller_test_pattern, color_depth);
4174 else if (link->dc->hwss.set_disp_pattern_generator) {
4175 struct pipe_ctx *odm_pipe;
4176 enum controller_dp_color_space controller_color_space;
4179 int dpg_width = width;
4181 switch (test_pattern_color_space) {
4182 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4183 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4185 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4186 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4188 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4189 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4191 case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4193 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4194 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4199 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4201 dpg_width = width / opp_cnt;
4204 link->dc->hwss.set_disp_pattern_generator(link->dc,
4206 controller_test_pattern,
4207 controller_color_space,
4214 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4215 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4217 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms);
4218 link->dc->hwss.set_disp_pattern_generator(link->dc,
4220 controller_test_pattern,
4221 controller_color_space,
4232 case DP_TEST_PATTERN_VIDEO_MODE:
4234 /* restore bitdepth reduction */
4235 resource_build_bit_depth_reduction_params(pipe_ctx->stream, ¶ms);
4236 pipe_ctx->stream->bit_depth_params = params;
4237 opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms);
4238 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4239 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4240 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4242 else if (link->dc->hwss.set_disp_pattern_generator) {
4243 struct pipe_ctx *odm_pipe;
4245 int dpg_width = width;
4247 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4250 dpg_width = width / opp_cnt;
4251 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4252 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4254 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms);
4255 link->dc->hwss.set_disp_pattern_generator(link->dc,
4257 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4258 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4265 link->dc->hwss.set_disp_pattern_generator(link->dc,
4267 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4268 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4283 bool dc_link_dp_set_test_pattern(
4284 struct dc_link *link,
4285 enum dp_test_pattern test_pattern,
4286 enum dp_test_pattern_color_space test_pattern_color_space,
4287 const struct link_training_settings *p_link_settings,
4288 const unsigned char *p_custom_pattern,
4289 unsigned int cust_pattern_size)
4291 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4292 struct pipe_ctx *pipe_ctx = NULL;
4295 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4296 union dpcd_training_pattern training_pattern;
4297 enum dpcd_phy_test_patterns pattern;
4299 memset(&training_pattern, 0, sizeof(training_pattern));
4301 for (i = 0; i < MAX_PIPES; i++) {
4302 if (pipes[i].stream == NULL)
4305 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4306 pipe_ctx = &pipes[i];
4311 if (pipe_ctx == NULL)
4314 /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4315 if (link->test_pattern_enabled && test_pattern ==
4316 DP_TEST_PATTERN_VIDEO_MODE) {
4317 /* Set CRTC Test Pattern */
4318 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4319 dp_set_hw_test_pattern(link, test_pattern,
4320 (uint8_t *)p_custom_pattern,
4321 (uint32_t)cust_pattern_size);
4323 /* Unblank Stream */
4324 link->dc->hwss.unblank_stream(
4326 &link->verified_link_cap);
4327 /* TODO:m_pHwss->MuteAudioEndpoint
4328 * (pPathMode->pDisplayPath, false);
4331 /* Reset Test Pattern state */
4332 link->test_pattern_enabled = false;
4337 /* Check for PHY Test Patterns */
4338 if (is_dp_phy_pattern(test_pattern)) {
4339 /* Set DPCD Lane Settings before running test pattern */
4340 if (p_link_settings != NULL) {
4341 dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4342 dpcd_set_lane_settings(link, p_link_settings, DPRX);
4345 /* Blank stream if running test pattern */
4346 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4349 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4352 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4355 dp_set_hw_test_pattern(link, test_pattern,
4356 (uint8_t *)p_custom_pattern,
4357 (uint32_t)cust_pattern_size);
4359 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4360 /* Set Test Pattern state */
4361 link->test_pattern_enabled = true;
4362 if (p_link_settings != NULL)
4363 dpcd_set_link_settings(link,
4367 switch (test_pattern) {
4368 case DP_TEST_PATTERN_VIDEO_MODE:
4369 pattern = PHY_TEST_PATTERN_NONE;
4371 case DP_TEST_PATTERN_D102:
4372 pattern = PHY_TEST_PATTERN_D10_2;
4374 case DP_TEST_PATTERN_SYMBOL_ERROR:
4375 pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4377 case DP_TEST_PATTERN_PRBS7:
4378 pattern = PHY_TEST_PATTERN_PRBS7;
4380 case DP_TEST_PATTERN_80BIT_CUSTOM:
4381 pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4383 case DP_TEST_PATTERN_CP2520_1:
4384 pattern = PHY_TEST_PATTERN_CP2520_1;
4386 case DP_TEST_PATTERN_CP2520_2:
4387 pattern = PHY_TEST_PATTERN_CP2520_2;
4389 case DP_TEST_PATTERN_CP2520_3:
4390 pattern = PHY_TEST_PATTERN_CP2520_3;
4396 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4397 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4400 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4401 /* tell receiver that we are sending qualification
4402 * pattern DP 1.2 or later - DP receiver's link quality
4403 * pattern is set using DPCD LINK_QUAL_LANEx_SET
4404 * register (0x10B~0x10E)\
4406 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4407 link_qual_pattern[lane] =
4408 (unsigned char)(pattern);
4410 core_link_write_dpcd(link,
4411 DP_LINK_QUAL_LANE0_SET,
4413 sizeof(link_qual_pattern));
4414 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4415 link->dpcd_caps.dpcd_rev.raw == 0) {
4416 /* tell receiver that we are sending qualification
4417 * pattern DP 1.1a or earlier - DP receiver's link
4418 * quality pattern is set using
4419 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4420 * register (0x102). We will use v_1.3 when we are
4421 * setting test pattern for DP 1.1.
4423 core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4424 &training_pattern.raw,
4425 sizeof(training_pattern));
4426 training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4427 core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4428 &training_pattern.raw,
4429 sizeof(training_pattern));
4432 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4434 switch (test_pattern_color_space) {
4435 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4436 color_space = COLOR_SPACE_SRGB;
4437 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4438 color_space = COLOR_SPACE_SRGB_LIMITED;
4441 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4442 color_space = COLOR_SPACE_YCBCR601;
4443 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4444 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4446 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4447 color_space = COLOR_SPACE_YCBCR709;
4448 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4449 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4455 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4456 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4457 union dmub_hw_lock_flags hw_locks = { 0 };
4458 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4460 hw_locks.bits.lock_dig = 1;
4461 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4463 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4468 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4469 pipe_ctx->stream_res.tg);
4472 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4473 /* update MSA to requested color space */
4474 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4475 &pipe_ctx->stream->timing,
4477 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4478 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4480 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4481 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4482 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4484 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4485 resource_build_info_frame(pipe_ctx);
4486 link->dc->hwss.update_info_frame(pipe_ctx);
4490 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4491 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4492 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4493 CRTC_STATE_VACTIVE);
4494 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4496 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4497 CRTC_STATE_VACTIVE);
4499 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4500 if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4501 union dmub_hw_lock_flags hw_locks = { 0 };
4502 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4504 hw_locks.bits.lock_dig = 1;
4505 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4507 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4512 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4513 pipe_ctx->stream_res.tg);
4516 /* Set Test Pattern state */
4517 link->test_pattern_enabled = true;
4523 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4525 unsigned char mstmCntl;
4527 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4529 mstmCntl |= DP_MST_EN;
4531 mstmCntl &= (~DP_MST_EN);
4533 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4536 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4538 union dpcd_edp_config edp_config_set;
4539 bool panel_mode_edp = false;
4541 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4543 if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4545 switch (panel_mode) {
4546 case DP_PANEL_MODE_EDP:
4547 case DP_PANEL_MODE_SPECIAL:
4548 panel_mode_edp = true;
4555 /*set edp panel mode in receiver*/
4556 core_link_read_dpcd(
4558 DP_EDP_CONFIGURATION_SET,
4559 &edp_config_set.raw,
4560 sizeof(edp_config_set.raw));
4562 if (edp_config_set.bits.PANEL_MODE_EDP
4563 != panel_mode_edp) {
4564 enum dc_status result;
4566 edp_config_set.bits.PANEL_MODE_EDP =
4568 result = core_link_write_dpcd(
4570 DP_EDP_CONFIGURATION_SET,
4571 &edp_config_set.raw,
4572 sizeof(edp_config_set.raw));
4574 ASSERT(result == DC_OK);
4577 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4578 "eDP panel mode enabled: %d \n",
4580 link->dpcd_caps.panel_mode_edp,
4584 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4586 /* We need to explicitly check that connector
4587 * is not DP. Some Travis_VGA get reported
4588 * by video bios as DP.
4590 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4592 switch (link->dpcd_caps.branch_dev_id) {
4593 case DP_BRANCH_DEVICE_ID_0022B9:
4594 /* alternate scrambler reset is required for Travis
4595 * for the case when external chip does not
4596 * provide sink device id, alternate scrambler
4597 * scheme will be overriden later by querying
4601 link->dpcd_caps.branch_dev_name,
4602 DP_VGA_LVDS_CONVERTER_ID_2,
4605 branch_dev_name)) == 0) {
4606 return DP_PANEL_MODE_SPECIAL;
4609 case DP_BRANCH_DEVICE_ID_00001A:
4610 /* alternate scrambler reset is required for Travis
4611 * for the case when external chip does not provide
4612 * sink device id, alternate scrambler scheme will
4613 * be overriden later by querying Encoder feature
4615 if (strncmp(link->dpcd_caps.branch_dev_name,
4616 DP_VGA_LVDS_CONVERTER_ID_3,
4619 branch_dev_name)) == 0) {
4620 return DP_PANEL_MODE_SPECIAL;
4628 if (link->dpcd_caps.panel_mode_edp &&
4629 (link->connector_signal == SIGNAL_TYPE_EDP ||
4630 (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
4631 link->is_internal_display))) {
4632 return DP_PANEL_MODE_EDP;
4635 return DP_PANEL_MODE_DEFAULT;
4638 enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
4640 /* FEC has to be "set ready" before the link training.
4641 * The policy is to always train with FEC
4642 * if the sink supports it and leave it enabled on link.
4643 * If FEC is not supported, disable it.
4645 struct link_encoder *link_enc = NULL;
4646 enum dc_status status = DC_OK;
4647 uint8_t fec_config = 0;
4649 /* Access link encoder based on whether it is statically
4650 * or dynamically assigned to a link.
4652 if (link->is_dig_mapping_flexible &&
4653 link->dc->res_pool->funcs->link_encs_assign)
4654 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
4656 link_enc = link->link_enc;
4659 if (!dc_link_should_enable_fec(link))
4662 if (link_enc->funcs->fec_set_ready &&
4663 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4666 status = core_link_write_dpcd(link,
4667 DP_FEC_CONFIGURATION,
4669 sizeof(fec_config));
4670 if (status == DC_OK) {
4671 link_enc->funcs->fec_set_ready(link_enc, true);
4672 link->fec_state = dc_link_fec_ready;
4674 link_enc->funcs->fec_set_ready(link->link_enc, false);
4675 link->fec_state = dc_link_fec_not_ready;
4676 dm_error("dpcd write failed to set fec_ready");
4678 } else if (link->fec_state == dc_link_fec_ready) {
4680 status = core_link_write_dpcd(link,
4681 DP_FEC_CONFIGURATION,
4683 sizeof(fec_config));
4684 link_enc->funcs->fec_set_ready(link_enc, false);
4685 link->fec_state = dc_link_fec_not_ready;
4692 void dp_set_fec_enable(struct dc_link *link, bool enable)
4694 struct link_encoder *link_enc = NULL;
4696 /* Access link encoder based on whether it is statically
4697 * or dynamically assigned to a link.
4699 if (link->is_dig_mapping_flexible &&
4700 link->dc->res_pool->funcs->link_encs_assign)
4701 link_enc = link_enc_cfg_get_link_enc_used_by_link(
4702 link->dc->current_state, link);
4704 link_enc = link->link_enc;
4707 if (!dc_link_should_enable_fec(link))
4710 if (link_enc->funcs->fec_set_enable &&
4711 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4712 if (link->fec_state == dc_link_fec_ready && enable) {
4713 /* Accord to DP spec, FEC enable sequence can first
4714 * be transmitted anytime after 1000 LL codes have
4715 * been transmitted on the link after link training
4716 * completion. Using 1 lane RBR should have the maximum
4717 * time for transmitting 1000 LL codes which is 6.173 us.
4718 * So use 7 microseconds delay instead.
4721 link_enc->funcs->fec_set_enable(link_enc, true);
4722 link->fec_state = dc_link_fec_enabled;
4723 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4724 link_enc->funcs->fec_set_enable(link_enc, false);
4725 link->fec_state = dc_link_fec_ready;
4730 void dpcd_set_source_specific_data(struct dc_link *link)
4732 if (!link->dc->vendor_signature.is_valid) {
4733 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
4734 struct dpcd_amd_signature amd_signature = {0};
4735 struct dpcd_amd_device_id amd_device_id = {0};
4737 amd_device_id.device_id_byte1 =
4738 (uint8_t)(link->ctx->asic_id.chip_id);
4739 amd_device_id.device_id_byte2 =
4740 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4741 amd_device_id.dce_version =
4742 (uint8_t)(link->ctx->dce_version);
4743 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4744 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4746 core_link_read_dpcd(link, DP_SOURCE_OUI,
4747 (uint8_t *)(&amd_signature),
4748 sizeof(amd_signature));
4750 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4751 (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4752 (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4754 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4755 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4756 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4758 core_link_write_dpcd(link, DP_SOURCE_OUI,
4759 (uint8_t *)(&amd_signature),
4760 sizeof(amd_signature));
4763 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4764 (uint8_t *)(&amd_device_id),
4765 sizeof(amd_device_id));
4767 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4768 link->dc->caps.min_horizontal_blanking_period != 0) {
4770 uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4772 if (link->preferred_link_setting.dpcd_source_device_specific_field_support) {
4773 result_write_min_hblank = core_link_write_dpcd(link,
4774 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4775 sizeof(hblank_size));
4777 if (result_write_min_hblank == DC_ERROR_UNEXPECTED)
4778 link->preferred_link_setting.dpcd_source_device_specific_field_support = false;
4780 DC_LOG_DC("Sink device does not support 00340h DPCD write. Skipping on purpose.\n");
4784 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4785 WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4786 "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4787 result_write_min_hblank,
4789 link->ctx->dce_version,
4790 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4791 link->dc->caps.min_horizontal_blanking_period,
4792 link->dpcd_caps.branch_dev_id,
4793 link->dpcd_caps.branch_dev_name[0],
4794 link->dpcd_caps.branch_dev_name[1],
4795 link->dpcd_caps.branch_dev_name[2],
4796 link->dpcd_caps.branch_dev_name[3],
4797 link->dpcd_caps.branch_dev_name[4],
4798 link->dpcd_caps.branch_dev_name[5]);
4800 core_link_write_dpcd(link, DP_SOURCE_OUI,
4801 link->dc->vendor_signature.data.raw,
4802 sizeof(link->dc->vendor_signature.data.raw));
4806 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4808 uint32_t backlight_millinits,
4809 uint32_t transition_time_in_ms)
4811 struct dpcd_source_backlight_set dpcd_backlight_set;
4812 uint8_t backlight_control = isHDR ? 1 : 0;
4814 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4815 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4818 // OLEDs have no PWM, they can only use AUX
4819 if (link->dpcd_sink_ext_caps.bits.oled == 1)
4820 backlight_control = 1;
4822 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4823 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4826 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4827 (uint8_t *)(&dpcd_backlight_set),
4828 sizeof(dpcd_backlight_set)) != DC_OK)
4831 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4832 &backlight_control, 1) != DC_OK)
4838 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4839 uint32_t *backlight_millinits_avg,
4840 uint32_t *backlight_millinits_peak)
4842 union dpcd_source_backlight_get dpcd_backlight_get;
4844 memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4846 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4847 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4850 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4851 dpcd_backlight_get.raw,
4852 sizeof(union dpcd_source_backlight_get)) != DC_OK)
4855 *backlight_millinits_avg =
4856 dpcd_backlight_get.bytes.backlight_millinits_avg;
4857 *backlight_millinits_peak =
4858 dpcd_backlight_get.bytes.backlight_millinits_peak;
4860 /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4861 if (*backlight_millinits_avg == 0 ||
4862 *backlight_millinits_avg > *backlight_millinits_peak)
4868 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4870 uint8_t backlight_enable = enable ? 1 : 0;
4872 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4873 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4876 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4877 &backlight_enable, 1) != DC_OK)
4883 // we read default from 0x320 because we expect BIOS wrote it there
4884 // regular get_backlight_nit reads from panel set at 0x326
4885 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4887 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4888 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4891 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4892 (uint8_t *) backlight_millinits,
4893 sizeof(uint32_t)) != DC_OK)
4899 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4901 uint32_t default_backlight;
4903 if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {
4904 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4905 default_backlight = 150000;
4906 // if < 5 nits or > 5000, it might be wrong readback
4907 if (default_backlight < 5000 || default_backlight > 5000000)
4908 default_backlight = 150000; //
4910 return dc_link_set_backlight_level_nits(link, true,
4911 default_backlight, 0);
4916 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4918 struct dc_link_settings link_setting;
4919 uint8_t link_bw_set;
4920 uint8_t link_rate_set;
4922 union lane_count_set lane_count_set = { {0} };
4924 ASSERT(link || crtc_timing); // invalid input
4926 if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4927 !link->dc->debug.optimize_edp_link_rate)
4931 // Read DPCD 00100h to find if standard link rates are set
4932 core_link_read_dpcd(link, DP_LINK_BW_SET,
4933 &link_bw_set, sizeof(link_bw_set));
4936 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
4940 // Read DPCD 00115h to find the edp link rate set used
4941 core_link_read_dpcd(link, DP_LINK_RATE_SET,
4942 &link_rate_set, sizeof(link_rate_set));
4944 // Read DPCD 00101h to find out the number of lanes currently set
4945 core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4946 &lane_count_set.raw, sizeof(lane_count_set));
4948 req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4950 decide_edp_link_settings(link, &link_setting, req_bw);
4952 if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
4953 lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4954 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
4958 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
4962 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
4964 if ((link_settings->link_rate >= LINK_RATE_LOW) &&
4965 (link_settings->link_rate <= LINK_RATE_HIGH3))
4966 return DP_8b_10b_ENCODING;
4967 return DP_UNKNOWN_ENCODING;