drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dm_helpers.h"
  28 #include "gpio_service_interface.h"
  29 #include "include/ddc_service_types.h"
  30 #include "include/grph_object_id.h"
  31 #include "include/dpcd_defs.h"
  32 #include "include/logger_interface.h"
  33 #include "include/vector.h"
  34 #include "core_types.h"
  35 #include "dc_link_ddc.h"
  36 #include "dce/dce_aux.h"
  37 #include "dmub/inc/dmub_cmd.h"
  38
  39 #define DC_LOGGER_INIT(logger)
  40
  41 static const uint8_t DP_VGA_DONGLE_BRANCH_DEV_NAME[] = "DpVga";
  42 /* DP to Dual link DVI converter */
  43 static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
  44 static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
  45
  46 #define AUX_POWER_UP_WA_DELAY 500
  47 #define I2C_OVER_AUX_DEFER_WA_DELAY 70
  48 #define DPVGA_DONGLE_AUX_DEFER_WA_DELAY 40
  49 #define I2C_OVER_AUX_DEFER_WA_DELAY_1MS 1
  50
  51 /* CV smart dongle slave address for retrieving supported HDTV modes*/
  52 #define CV_SMART_DONGLE_ADDRESS 0x20
  53 /* DVI-HDMI dongle slave address for retrieving dongle signature*/
  54 #define DVI_HDMI_DONGLE_ADDRESS 0x68
  55 struct dvi_hdmi_dongle_signature_data {
  56         int8_t vendor[3];/* "AMD" */
  57         uint8_t version[2];
  58         uint8_t size;
  59         int8_t id[11];/* "6140063500G"*/
  60 };
  61 /* DP-HDMI dongle slave address for retrieving dongle signature*/
  62 #define DP_HDMI_DONGLE_ADDRESS 0x40
  63 static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
  64 #define DP_HDMI_DONGLE_SIGNATURE_EOT 0x04
  65
  66 struct dp_hdmi_dongle_signature_data {
  67         int8_t id[15];/* "DP-HDMI ADAPTOR"*/
  68         uint8_t eot;/* end of transmition '\x4' */
  69 };
  70
  71 /* SCDC Address defines (HDMI 2.0)*/
  72 #define HDMI_SCDC_WRITE_UPDATE_0_ARRAY 3
  73 #define HDMI_SCDC_ADDRESS  0x54
  74 #define HDMI_SCDC_SINK_VERSION 0x01
  75 #define HDMI_SCDC_SOURCE_VERSION 0x02
  76 #define HDMI_SCDC_UPDATE_0 0x10
  77 #define HDMI_SCDC_TMDS_CONFIG 0x20
  78 #define HDMI_SCDC_SCRAMBLER_STATUS 0x21
  79 #define HDMI_SCDC_CONFIG_0 0x30
  80 #define HDMI_SCDC_STATUS_FLAGS 0x40
  81 #define HDMI_SCDC_ERR_DETECT 0x50
  82 #define HDMI_SCDC_TEST_CONFIG 0xC0
  83
  84 union hdmi_scdc_update_read_data {
  85         uint8_t byte[2];
  86         struct {
  87                 uint8_t STATUS_UPDATE:1;
  88                 uint8_t CED_UPDATE:1;
  89                 uint8_t RR_TEST:1;
  90                 uint8_t RESERVED:5;
  91                 uint8_t RESERVED2:8;
  92         } fields;
  93 };
  94
  95 union hdmi_scdc_status_flags_data {
  96         uint8_t byte[2];
  97         struct {
  98                 uint8_t CLOCK_DETECTED:1;
  99                 uint8_t CH0_LOCKED:1;
 100                 uint8_t CH1_LOCKED:1;
 101                 uint8_t CH2_LOCKED:1;
 102                 uint8_t RESERVED:4;
 103                 uint8_t RESERVED2:8;
 104                 uint8_t RESERVED3:8;
 105
 106         } fields;
 107 };
 108
 109 union hdmi_scdc_ced_data {
 110         uint8_t byte[7];
 111         struct {
 112                 uint8_t CH0_8LOW:8;
 113                 uint8_t CH0_7HIGH:7;
 114                 uint8_t CH0_VALID:1;
 115                 uint8_t CH1_8LOW:8;
 116                 uint8_t CH1_7HIGH:7;
 117                 uint8_t CH1_VALID:1;
 118                 uint8_t CH2_8LOW:8;
 119                 uint8_t CH2_7HIGH:7;
 120                 uint8_t CH2_VALID:1;
 121                 uint8_t CHECKSUM:8;
 122                 uint8_t RESERVED:8;
 123                 uint8_t RESERVED2:8;
 124                 uint8_t RESERVED3:8;
 125                 uint8_t RESERVED4:4;
 126         } fields;
 127 };
 128
 129 struct i2c_payloads {
 130         struct vector payloads;
 131 };
 132
 133 struct aux_payloads {
 134         struct vector payloads;
 135 };
 136
 137 static bool dal_ddc_i2c_payloads_create(
 138                 struct dc_context *ctx,
 139                 struct i2c_payloads *payloads,
 140                 uint32_t count)
 141 {
 142         if (dal_vector_construct(
 143                 &payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
 144                 return true;
 145
 146         return false;
 147 }
 148
 149 static struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p)
 150 {
 151         return (struct i2c_payload *)p->payloads.container;
 152 }
 153
 154 static uint32_t dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p)
 155 {
 156         return p->payloads.count;
 157 }
 158
 159 #define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
 160
 161 void dal_ddc_i2c_payloads_add(
 162         struct i2c_payloads *payloads,
 163         uint32_t address,
 164         uint32_t len,
 165         uint8_t *data,
 166         bool write)
 167 {
 168         uint32_t payload_size = EDID_SEGMENT_SIZE;
 169         uint32_t pos;
 170
 171         for (pos = 0; pos < len; pos += payload_size) {
 172                 struct i2c_payload payload = {
 173                         .write = write,
 174                         .address = address,
 175                         .length = DDC_MIN(payload_size, len - pos),
 176                         .data = data + pos };
 177                 dal_vector_append(&payloads->payloads, &payload);
 178         }
 179
 180 }
 181
 182 static void ddc_service_construct(
 183         struct ddc_service *ddc_service,
 184         struct ddc_service_init_data *init_data)
 185 {
 186         enum connector_id connector_id =
 187                 dal_graphics_object_id_get_connector_id(init_data->id);
 188
 189         struct gpio_service *gpio_service = init_data->ctx->gpio_service;
 190         struct graphics_object_i2c_info i2c_info;
 191         struct gpio_ddc_hw_info hw_info;
 192         struct dc_bios *dcb = init_data->ctx->dc_bios;
 193
 194         ddc_service->link = init_data->link;
 195         ddc_service->ctx = init_data->ctx;
 196
 197         if (init_data->is_dpia_link ||
 198             dcb->funcs->get_i2c_info(dcb, init_data->id, &i2c_info) != BP_RESULT_OK) {
 199                 ddc_service->ddc_pin = NULL;
 200         } else {
 201                 DC_LOGGER_INIT(ddc_service->ctx->logger);
 202                 DC_LOG_DC("BIOS object table - i2c_line: %d", i2c_info.i2c_line);
 203                 DC_LOG_DC("BIOS object table - i2c_engine_id: %d", i2c_info.i2c_engine_id);
 204
 205                 hw_info.ddc_channel = i2c_info.i2c_line;
 206                 if (ddc_service->link != NULL)
 207                         hw_info.hw_supported = i2c_info.i2c_hw_assist;
 208                 else
 209                         hw_info.hw_supported = false;
 210
 211                 ddc_service->ddc_pin = dal_gpio_create_ddc(
 212                         gpio_service,
 213                         i2c_info.gpio_info.clk_a_register_index,
 214                         1 << i2c_info.gpio_info.clk_a_shift,
 215                         &hw_info);
 216         }
 217
 218         ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
 219         ddc_service->flags.FORCE_READ_REPEATED_START = false;
 220         ddc_service->flags.EDID_STRESS_READ = false;
 221
 222         ddc_service->flags.IS_INTERNAL_DISPLAY =
 223                 connector_id == CONNECTOR_ID_EDP ||
 224                 connector_id == CONNECTOR_ID_LVDS;
 225
 226         ddc_service->wa.raw = 0;
 227 }
 228
 229 struct ddc_service *dal_ddc_service_create(
 230         struct ddc_service_init_data *init_data)
 231 {
 232         struct ddc_service *ddc_service;
 233
 234         ddc_service = kzalloc(sizeof(struct ddc_service), GFP_KERNEL);
 235
 236         if (!ddc_service)
 237                 return NULL;
 238
 239         ddc_service_construct(ddc_service, init_data);
 240         return ddc_service;
 241 }
 242
 243 static void ddc_service_destruct(struct ddc_service *ddc)
 244 {
 245         if (ddc->ddc_pin)
 246                 dal_gpio_destroy_ddc(&ddc->ddc_pin);
 247 }
 248
 249 void dal_ddc_service_destroy(struct ddc_service **ddc)
 250 {
 251         if (!ddc || !*ddc) {
 252                 BREAK_TO_DEBUGGER();
 253                 return;
 254         }
 255         ddc_service_destruct(*ddc);
 256         kfree(*ddc);
 257         *ddc = NULL;
 258 }
 259
 260 enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc)
 261 {
 262         return DDC_SERVICE_TYPE_CONNECTOR;
 263 }
 264
 265 void dal_ddc_service_set_transaction_type(
 266         struct ddc_service *ddc,
 267         enum ddc_transaction_type type)
 268 {
 269         ddc->transaction_type = type;
 270 }
 271
 272 bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc)
 273 {
 274         switch (ddc->transaction_type) {
 275         case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
 276         case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
 277         case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER:
 278                 return true;
 279         default:
 280                 break;
 281         }
 282         return false;
 283 }
 284
 285 void ddc_service_set_dongle_type(struct ddc_service *ddc,
 286                 enum display_dongle_type dongle_type)
 287 {
 288         ddc->dongle_type = dongle_type;
 289 }
 290
 291 static uint32_t defer_delay_converter_wa(
 292         struct ddc_service *ddc,
 293         uint32_t defer_delay)
 294 {
 295         struct dc_link *link = ddc->link;
 296
 297         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER &&
 298                 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
 299                 (link->dpcd_caps.branch_fw_revision[0] < 0x01 ||
 300                                 (link->dpcd_caps.branch_fw_revision[0] == 0x01 &&
 301                                 link->dpcd_caps.branch_fw_revision[1] < 0x40)) &&
 302                 !memcmp(link->dpcd_caps.branch_dev_name,
 303                     DP_VGA_DONGLE_BRANCH_DEV_NAME,
 304                         sizeof(link->dpcd_caps.branch_dev_name)))
 305
 306                 return defer_delay > DPVGA_DONGLE_AUX_DEFER_WA_DELAY ?
 307                         defer_delay : DPVGA_DONGLE_AUX_DEFER_WA_DELAY;
 308
 309         if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
 310             !memcmp(link->dpcd_caps.branch_dev_name,
 311                     DP_DVI_CONVERTER_ID_4,
 312                     sizeof(link->dpcd_caps.branch_dev_name)))
 313                 return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
 314                         defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;
 315         if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 &&
 316             !memcmp(link->dpcd_caps.branch_dev_name,
 317                     DP_DVI_CONVERTER_ID_5,
 318                     sizeof(link->dpcd_caps.branch_dev_name)))
 319                 return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY_1MS ?
 320                         I2C_OVER_AUX_DEFER_WA_DELAY_1MS : defer_delay;
 321
 322         return defer_delay;
 323 }
 324
 325 #define DP_TRANSLATOR_DELAY 5
 326
 327 uint32_t get_defer_delay(struct ddc_service *ddc)
 328 {
 329         uint32_t defer_delay = 0;
 330
 331         switch (ddc->transaction_type) {
 332         case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
 333                 if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||
 334                         (DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||
 335                         (DISPLAY_DONGLE_DP_HDMI_CONVERTER ==
 336                                 ddc->dongle_type)) {
 337
 338                         defer_delay = DP_TRANSLATOR_DELAY;
 339
 340                         defer_delay =
 341                                 defer_delay_converter_wa(ddc, defer_delay);
 342
 343                 } else /*sink has a delay different from an Active Converter*/
 344                         defer_delay = 0;
 345                 break;
 346         case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
 347                 defer_delay = DP_TRANSLATOR_DELAY;
 348                 break;
 349         default:
 350                 break;
 351         }
 352         return defer_delay;
 353 }
 354
 355 static bool i2c_read(
 356         struct ddc_service *ddc,
 357         uint32_t address,
 358         uint8_t *buffer,
 359         uint32_t len)
 360 {
 361         uint8_t offs_data = 0;
 362         struct i2c_payload payloads[2] = {
 363                 {
 364                 .write = true,
 365                 .address = address,
 366                 .length = 1,
 367                 .data = &offs_data },
 368                 {
 369                 .write = false,
 370                 .address = address,
 371                 .length = len,
 372                 .data = buffer } };
 373
 374         struct i2c_command command = {
 375                 .payloads = payloads,
 376                 .number_of_payloads = 2,
 377                 .engine = DDC_I2C_COMMAND_ENGINE,
 378                 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
 379
 380         return dm_helpers_submit_i2c(
 381                         ddc->ctx,
 382                         ddc->link,
 383                         &command);
 384 }
 385
 386 void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 387         struct ddc_service *ddc,
 388         struct display_sink_capability *sink_cap)
 389 {
 390         uint8_t i;
 391         bool is_valid_hdmi_signature;
 392         enum display_dongle_type *dongle = &sink_cap->dongle_type;
 393         uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
 394         bool is_type2_dongle = false;
 395         int retry_count = 2;
 396         struct dp_hdmi_dongle_signature_data *dongle_signature;
 397
 398         /* Assume we have no valid DP passive dongle connected */
 399         *dongle = DISPLAY_DONGLE_NONE;
 400         sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
 401
 402         /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
 403         if (!i2c_read(
 404                 ddc,
 405                 DP_HDMI_DONGLE_ADDRESS,
 406                 type2_dongle_buf,
 407                 sizeof(type2_dongle_buf))) {
 408                 /* Passive HDMI dongles can sometimes fail here without retrying*/
 409                 while (retry_count > 0) {
 410                         if (i2c_read(ddc,
 411                                 DP_HDMI_DONGLE_ADDRESS,
 412                                 type2_dongle_buf,
 413                                 sizeof(type2_dongle_buf)))
 414                                 break;
 415                         retry_count--;
 416                 }
 417                 if (retry_count == 0) {
 418                         *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
 419                         sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
 420
 421                         CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
 422                                         "DP-DVI passive dongle %dMhz: ",
 423                                         DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
 424                         return;
 425                 }
 426         }
 427
 428         /* Check if Type 2 dongle.*/
 429         if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
 430                 is_type2_dongle = true;
 431
 432         dongle_signature =
 433                 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
 434
 435         is_valid_hdmi_signature = true;
 436
 437         /* Check EOT */
 438         if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
 439                 is_valid_hdmi_signature = false;
 440         }
 441
 442         /* Check signature */
 443         for (i = 0; i < sizeof(dongle_signature->id); ++i) {
 444                 /* If its not the right signature,
 445                  * skip mismatch in subversion byte.*/
 446                 if (dongle_signature->id[i] !=
 447                         dp_hdmi_dongle_signature_str[i] && i != 3) {
 448
 449                         if (is_type2_dongle) {
 450                                 is_valid_hdmi_signature = false;
 451                                 break;
 452                         }
 453
 454                 }
 455         }
 456
 457         if (is_type2_dongle) {
 458                 uint32_t max_tmds_clk =
 459                         type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
 460
 461                 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
 462
 463                 if (0 == max_tmds_clk ||
 464                                 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
 465                                 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
 466                         *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
 467
 468                         CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
 469                                         sizeof(type2_dongle_buf),
 470                                         "DP-DVI passive dongle %dMhz: ",
 471                                         DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
 472                 } else {
 473                         if (is_valid_hdmi_signature == true) {
 474                                 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
 475
 476                                 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
 477                                                 sizeof(type2_dongle_buf),
 478                                                 "Type 2 DP-HDMI passive dongle %dMhz: ",
 479                                                 max_tmds_clk);
 480                         } else {
 481                                 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
 482
 483                                 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
 484                                                 sizeof(type2_dongle_buf),
 485                                                 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ",
 486                                                 max_tmds_clk);
 487
 488                         }
 489
 490                         /* Multiply by 1000 to convert to kHz. */
 491                         sink_cap->max_hdmi_pixel_clock =
 492                                 max_tmds_clk * 1000;
 493                 }
 494                 sink_cap->is_dongle_type_one = false;
 495
 496         } else {
 497                 if (is_valid_hdmi_signature == true) {
 498                         *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
 499
 500                         CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
 501                                         sizeof(type2_dongle_buf),
 502                                         "Type 1 DP-HDMI passive dongle %dMhz: ",
 503                                         sink_cap->max_hdmi_pixel_clock / 1000);
 504                 } else {
 505                         *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
 506
 507                         CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
 508                                         sizeof(type2_dongle_buf),
 509                                         "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ",
 510                                         sink_cap->max_hdmi_pixel_clock / 1000);
 511                 }
 512                 sink_cap->is_dongle_type_one = true;
 513         }
 514
 515         return;
 516 }
 517
 518 enum {
 519         DP_SINK_CAP_SIZE =
 520                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
 521 };
 522
 523 bool dal_ddc_service_query_ddc_data(
 524         struct ddc_service *ddc,
 525         uint32_t address,
 526         uint8_t *write_buf,
 527         uint32_t write_size,
 528         uint8_t *read_buf,
 529         uint32_t read_size)
 530 {
 531         bool success = true;
 532         uint32_t payload_size =
 533                 dal_ddc_service_is_in_aux_transaction_mode(ddc) ?
 534                         DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;
 535
 536         uint32_t write_payloads =
 537                 (write_size + payload_size - 1) / payload_size;
 538
 539         uint32_t read_payloads =
 540                 (read_size + payload_size - 1) / payload_size;
 541
 542         uint32_t payloads_num = write_payloads + read_payloads;
 543
 544         if (!payloads_num)
 545                 return false;
 546
 547         if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
 548                 struct aux_payload payload;
 549
 550                 payload.i2c_over_aux = true;
 551                 payload.address = address;
 552                 payload.reply = NULL;
 553                 payload.defer_delay = get_defer_delay(ddc);
 554                 payload.write_status_update = false;
 555
 556                 if (write_size != 0) {
 557                         payload.write = true;
 558                         /* should not set mot (middle of transaction) to 0
 559                          * if there are pending read payloads
 560                          */
 561                         payload.mot = !(read_size == 0);
 562                         payload.length = write_size;
 563                         payload.data = write_buf;
 564
 565                         success = dal_ddc_submit_aux_command(ddc, &payload);
 566                 }
 567
 568                 if (read_size != 0 && success) {
 569                         payload.write = false;
 570                         /* should set mot (middle of transaction) to 0
 571                          * since it is the last payload to send
 572                          */
 573                         payload.mot = false;
 574                         payload.length = read_size;
 575                         payload.data = read_buf;
 576
 577                         success = dal_ddc_submit_aux_command(ddc, &payload);
 578                 }
 579         } else {
 580                 struct i2c_command command = {0};
 581                 struct i2c_payloads payloads;
 582
 583                 if (!dal_ddc_i2c_payloads_create(ddc->ctx, &payloads, payloads_num))
 584                         return false;
 585
 586                 command.payloads = dal_ddc_i2c_payloads_get(&payloads);
 587                 command.number_of_payloads = 0;
 588                 command.engine = DDC_I2C_COMMAND_ENGINE;
 589                 command.speed = ddc->ctx->dc->caps.i2c_speed_in_khz;
 590
 591                 dal_ddc_i2c_payloads_add(
 592                         &payloads, address, write_size, write_buf, true);
 593
 594                 dal_ddc_i2c_payloads_add(
 595                         &payloads, address, read_size, read_buf, false);
 596
 597                 command.number_of_payloads =
 598                         dal_ddc_i2c_payloads_get_count(&payloads);
 599
 600                 success = dm_helpers_submit_i2c(
 601                                 ddc->ctx,
 602                                 ddc->link,
 603                                 &command);
 604
 605                 dal_vector_destruct(&payloads.payloads);
 606         }
 607
 608         return success;
 609 }
 610
 611 bool dal_ddc_submit_aux_command(struct ddc_service *ddc,
 612                 struct aux_payload *payload)
 613 {
 614         uint32_t retrieved = 0;
 615         bool ret = false;
 616
 617         if (!ddc)
 618                 return false;
 619
 620         if (!payload)
 621                 return false;
 622
 623         do {
 624                 struct aux_payload current_payload;
 625                 bool is_end_of_payload = (retrieved + DEFAULT_AUX_MAX_DATA_SIZE) >=
 626                                 payload->length;
 627                 uint32_t payload_length = is_end_of_payload ?
 628                                 payload->length - retrieved : DEFAULT_AUX_MAX_DATA_SIZE;
 629
 630                 current_payload.address = payload->address;
 631                 current_payload.data = &payload->data[retrieved];
 632                 current_payload.defer_delay = payload->defer_delay;
 633                 current_payload.i2c_over_aux = payload->i2c_over_aux;
 634                 current_payload.length = payload_length;
 635                 /* set mot (middle of transaction) to false if it is the last payload */
 636                 current_payload.mot = is_end_of_payload ? payload->mot:true;
 637                 current_payload.write_status_update = false;
 638                 current_payload.reply = payload->reply;
 639                 current_payload.write = payload->write;
 640
 641                 ret = dc_link_aux_transfer_with_retries(ddc, &current_payload);
 642
 643                 retrieved += payload_length;
 644         } while (retrieved < payload->length && ret == true);
 645
 646         return ret;
 647 }
 648
 649 /* dc_link_aux_transfer_raw() - Attempt to transfer
 650  * the given aux payload.  This function does not perform
 651  * retries or handle error states.  The reply is returned
 652  * in the payload->reply and the result through
 653  * *operation_result.  Returns the number of bytes transferred,
 654  * or -1 on a failure.
 655  */
 656 int dc_link_aux_transfer_raw(struct ddc_service *ddc,
 657                 struct aux_payload *payload,
 658                 enum aux_return_code_type *operation_result)
 659 {
 660         if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc ||
 661             !ddc->ddc_pin) {
 662                 return dce_aux_transfer_dmub_raw(ddc, payload, operation_result);
 663         } else {
 664                 return dce_aux_transfer_raw(ddc, payload, operation_result);
 665         }
 666 }
 667
 668 /* dc_link_aux_transfer_with_retries() - Attempt to submit an
 669  * aux payload, retrying on timeouts, defers, and busy states
 670  * as outlined in the DP spec.  Returns true if the request
 671  * was successful.
 672  *
 673  * Unless you want to implement your own retry semantics, this
 674  * is probably the one you want.
 675  */
 676 bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
 677                 struct aux_payload *payload)
 678 {
 679         return dce_aux_transfer_with_retries(ddc, payload);
 680 }
 681
 682
 683 bool dc_link_aux_try_to_configure_timeout(struct ddc_service *ddc,
 684                 uint32_t timeout)
 685 {
 686         bool result = false;
 687         struct ddc *ddc_pin = ddc->ddc_pin;
 688
 689         /* Do not try to access nonexistent DDC pin. */
 690         if (ddc->link->ep_type != DISPLAY_ENDPOINT_PHY)
 691                 return true;
 692
 693         if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) {
 694                 ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);
 695                 result = true;
 696         }
 697         return result;
 698 }
 699
 700 /*test only function*/
 701 void dal_ddc_service_set_ddc_pin(
 702         struct ddc_service *ddc_service,
 703         struct ddc *ddc)
 704 {
 705         ddc_service->ddc_pin = ddc;
 706 }
 707
 708 struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service)
 709 {
 710         return ddc_service->ddc_pin;
 711 }
 712
 713 void dal_ddc_service_write_scdc_data(struct ddc_service *ddc_service,
 714                 uint32_t pix_clk,
 715                 bool lte_340_scramble)
 716 {
 717         bool over_340_mhz = pix_clk > 340000 ? 1 : 0;
 718         uint8_t slave_address = HDMI_SCDC_ADDRESS;
 719         uint8_t offset = HDMI_SCDC_SINK_VERSION;
 720         uint8_t sink_version = 0;
 721         uint8_t write_buffer[2] = {0};
 722         /*Lower than 340 Scramble bit from SCDC caps*/
 723
 724         if (ddc_service->link->local_sink &&
 725                 ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)
 726                 return;
 727
 728         dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
 729                         sizeof(offset), &sink_version, sizeof(sink_version));
 730         if (sink_version == 1) {
 731                 /*Source Version = 1*/
 732                 write_buffer[0] = HDMI_SCDC_SOURCE_VERSION;
 733                 write_buffer[1] = 1;
 734                 dal_ddc_service_query_ddc_data(ddc_service, slave_address,
 735                                 write_buffer, sizeof(write_buffer), NULL, 0);
 736                 /*Read Request from SCDC caps*/
 737         }
 738         write_buffer[0] = HDMI_SCDC_TMDS_CONFIG;
 739
 740         if (over_340_mhz) {
 741                 write_buffer[1] = 3;
 742         } else if (lte_340_scramble) {
 743                 write_buffer[1] = 1;
 744         } else {
 745                 write_buffer[1] = 0;
 746         }
 747         dal_ddc_service_query_ddc_data(ddc_service, slave_address, write_buffer,
 748                         sizeof(write_buffer), NULL, 0);
 749 }
 750
 751 void dal_ddc_service_read_scdc_data(struct ddc_service *ddc_service)
 752 {
 753         uint8_t slave_address = HDMI_SCDC_ADDRESS;
 754         uint8_t offset = HDMI_SCDC_TMDS_CONFIG;
 755         uint8_t tmds_config = 0;
 756
 757         if (ddc_service->link->local_sink &&
 758                 ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)
 759                 return;
 760
 761         dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
 762                         sizeof(offset), &tmds_config, sizeof(tmds_config));
 763         if (tmds_config & 0x1) {
 764                 union hdmi_scdc_status_flags_data status_data = {0};
 765                 uint8_t scramble_status = 0;
 766
 767                 offset = HDMI_SCDC_SCRAMBLER_STATUS;
 768                 dal_ddc_service_query_ddc_data(ddc_service, slave_address,
 769                                 &offset, sizeof(offset), &scramble_status,
 770                                 sizeof(scramble_status));
 771                 offset = HDMI_SCDC_STATUS_FLAGS;
 772                 dal_ddc_service_query_ddc_data(ddc_service, slave_address,
 773                                 &offset, sizeof(offset), status_data.byte,
 774                                 sizeof(status_data.byte));
 775         }
 776 }
 777