drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atomfirmware.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48 #include "dce/dmub_psr.h"
  49 #include "dmub/dmub_srv.h"
  50 #include "inc/hw/panel_cntl.h"
  51 #include "inc/link_enc_cfg.h"
  52 #include "inc/link_dpcd.h"
  53 #include "link/link_dp_trace.h"
  54
  55 #include "dc/dcn30/dcn30_vpg.h"
  56
  57 #define DC_LOGGER_INIT(logger)
  58
  59 #define LINK_INFO(...) \
  60         DC_LOG_HW_HOTPLUG(  \
  61                 __VA_ARGS__)
  62
  63 #define RETIMER_REDRIVER_INFO(...) \
  64         DC_LOG_RETIMER_REDRIVER(  \
  65                 __VA_ARGS__)
  66
  67 /*******************************************************************************
  68  * Private functions
  69  ******************************************************************************/
  70 static void dc_link_destruct(struct dc_link *link)
  71 {
  72         int i;
  73
  74         if (link->hpd_gpio) {
  75                 dal_gpio_destroy_irq(&link->hpd_gpio);
  76                 link->hpd_gpio = NULL;
  77         }
  78
  79         if (link->ddc)
  80                 dal_ddc_service_destroy(&link->ddc);
  81
  82         if (link->panel_cntl)
  83                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
  84
  85         if (link->link_enc) {
  86                 /* Update link encoder resource tracking variables. These are used for
  87                  * the dynamic assignment of link encoders to streams. Virtual links
  88                  * are not assigned encoder resources on creation.
  89                  */
  90                 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
  91                         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
  92                         link->dc->res_pool->dig_link_enc_count--;
  93                 }
  94                 link->link_enc->funcs->destroy(&link->link_enc);
  95         }
  96
  97         if (link->local_sink)
  98                 dc_sink_release(link->local_sink);
  99
 100         for (i = 0; i < link->sink_count; ++i)
 101                 dc_sink_release(link->remote_sinks[i]);
 102 }
 103
 104 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 105                           struct graphics_object_id link_id,
 106                           struct gpio_service *gpio_service)
 107 {
 108         enum bp_result bp_result;
 109         struct graphics_object_hpd_info hpd_info;
 110         struct gpio_pin_info pin_info;
 111
 112         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 113                 return NULL;
 114
 115         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 116                 hpd_info.hpd_int_gpio_uid, &pin_info);
 117
 118         if (bp_result != BP_RESULT_OK) {
 119                 ASSERT(bp_result == BP_RESULT_NORECORD);
 120                 return NULL;
 121         }
 122
 123         return dal_gpio_service_create_irq(gpio_service,
 124                                            pin_info.offset,
 125                                            pin_info.mask);
 126 }
 127
 128 /*
 129  *  Function: program_hpd_filter
 130  *
 131  *  @brief
 132  *     Programs HPD filter on associated HPD line
 133  *
 134  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 135  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 136  *
 137  *  @return
 138  *     true on success, false otherwise
 139  */
 140 static bool program_hpd_filter(const struct dc_link *link)
 141 {
 142         bool result = false;
 143         struct gpio *hpd;
 144         int delay_on_connect_in_ms = 0;
 145         int delay_on_disconnect_in_ms = 0;
 146
 147         if (link->is_hpd_filter_disabled)
 148                 return false;
 149         /* Verify feature is supported */
 150         switch (link->connector_signal) {
 151         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 152         case SIGNAL_TYPE_DVI_DUAL_LINK:
 153         case SIGNAL_TYPE_HDMI_TYPE_A:
 154                 /* Program hpd filter */
 155                 delay_on_connect_in_ms = 500;
 156                 delay_on_disconnect_in_ms = 100;
 157                 break;
 158         case SIGNAL_TYPE_DISPLAY_PORT:
 159         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 160                 /* Program hpd filter to allow DP signal to settle */
 161                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 162                  * only 100ms on DELL U2413
 163                  * 0: some passive dongle still show aux mode instead of i2c
 164                  * 20-50: not enough to hide bouncing HPD with passive dongle.
 165                  * also see intermittent i2c read issues.
 166                  */
 167                 delay_on_connect_in_ms = 80;
 168                 delay_on_disconnect_in_ms = 0;
 169                 break;
 170         case SIGNAL_TYPE_LVDS:
 171         case SIGNAL_TYPE_EDP:
 172         default:
 173                 /* Don't program hpd filter */
 174                 return false;
 175         }
 176
 177         /* Obtain HPD handle */
 178         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 179                            link->ctx->gpio_service);
 180
 181         if (!hpd)
 182                 return result;
 183
 184         /* Setup HPD filtering */
 185         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 186                 struct gpio_hpd_config config;
 187
 188                 config.delay_on_connect = delay_on_connect_in_ms;
 189                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 190
 191                 dal_irq_setup_hpd_filter(hpd, &config);
 192
 193                 dal_gpio_close(hpd);
 194
 195                 result = true;
 196         } else {
 197                 ASSERT_CRITICAL(false);
 198         }
 199
 200         /* Release HPD handle */
 201         dal_gpio_destroy_irq(&hpd);
 202
 203         return result;
 204 }
 205
 206 bool dc_link_wait_for_t12(struct dc_link *link)
 207 {
 208         if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 209                 link->dc->hwss.edp_wait_for_T12(link);
 210
 211                 return true;
 212         }
 213
 214         return false;
 215 }
 216
 217 /**
 218  * dc_link_detect_sink() - Determine if there is a sink connected
 219  *
 220  * @link: pointer to the dc link
 221  * @type: Returned connection type
 222  * Does not detect downstream devices, such as MST sinks
 223  * or display connected through active dongles
 224  */
 225 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 226 {
 227         uint32_t is_hpd_high = 0;
 228         struct gpio *hpd_pin;
 229
 230         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 231                 *type = dc_connection_single;
 232                 return true;
 233         }
 234
 235         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 236                 /*in case it is not on*/
 237                 link->dc->hwss.edp_power_control(link, true);
 238                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 239         }
 240
 241         /* Link may not have physical HPD pin. */
 242         if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
 243                 if (link->is_hpd_pending || !link->hpd_status)
 244                         *type = dc_connection_none;
 245                 else
 246                         *type = dc_connection_single;
 247
 248                 return true;
 249         }
 250
 251         /* todo: may need to lock gpio access */
 252         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 253                                link->ctx->gpio_service);
 254         if (!hpd_pin)
 255                 goto hpd_gpio_failure;
 256
 257         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 258         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 259         dal_gpio_close(hpd_pin);
 260         dal_gpio_destroy_irq(&hpd_pin);
 261
 262         if (is_hpd_high) {
 263                 *type = dc_connection_single;
 264                 /* TODO: need to do the actual detection */
 265         } else {
 266                 *type = dc_connection_none;
 267         }
 268
 269         return true;
 270
 271 hpd_gpio_failure:
 272         return false;
 273 }
 274
 275 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 276 {
 277         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 278
 279         switch (sink_signal) {
 280         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 281         case SIGNAL_TYPE_DVI_DUAL_LINK:
 282         case SIGNAL_TYPE_HDMI_TYPE_A:
 283         case SIGNAL_TYPE_LVDS:
 284         case SIGNAL_TYPE_RGB:
 285                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 286                 break;
 287
 288         case SIGNAL_TYPE_DISPLAY_PORT:
 289         case SIGNAL_TYPE_EDP:
 290                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 291                 break;
 292
 293         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 294                 /* MST does not use I2COverAux, but there is the
 295                  * SPECIAL use case for "immediate dwnstrm device
 296                  * access" (EPR#370830).
 297                  */
 298                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 299                 break;
 300
 301         default:
 302                 break;
 303         }
 304
 305         return transaction_type;
 306 }
 307
 308 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 309                                               struct graphics_object_id downstream)
 310 {
 311         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 312                 switch (downstream.id) {
 313                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 314                         switch (encoder.id) {
 315                         case ENCODER_ID_INTERNAL_DAC1:
 316                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 317                         case ENCODER_ID_INTERNAL_DAC2:
 318                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 319                                 return SIGNAL_TYPE_RGB;
 320                         default:
 321                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 322                         }
 323                 break;
 324                 case CONNECTOR_ID_DUAL_LINK_DVII:
 325                 {
 326                         switch (encoder.id) {
 327                         case ENCODER_ID_INTERNAL_DAC1:
 328                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 329                         case ENCODER_ID_INTERNAL_DAC2:
 330                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 331                                 return SIGNAL_TYPE_RGB;
 332                         default:
 333                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 334                         }
 335                 }
 336                 break;
 337                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 338                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 339                 case CONNECTOR_ID_DUAL_LINK_DVID:
 340                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 341                 case CONNECTOR_ID_VGA:
 342                         return SIGNAL_TYPE_RGB;
 343                 case CONNECTOR_ID_HDMI_TYPE_A:
 344                         return SIGNAL_TYPE_HDMI_TYPE_A;
 345                 case CONNECTOR_ID_LVDS:
 346                         return SIGNAL_TYPE_LVDS;
 347                 case CONNECTOR_ID_DISPLAY_PORT:
 348                         return SIGNAL_TYPE_DISPLAY_PORT;
 349                 case CONNECTOR_ID_EDP:
 350                         return SIGNAL_TYPE_EDP;
 351                 default:
 352                         return SIGNAL_TYPE_NONE;
 353                 }
 354         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 355                 switch (downstream.id) {
 356                 case ENCODER_ID_EXTERNAL_NUTMEG:
 357                 case ENCODER_ID_EXTERNAL_TRAVIS:
 358                         return SIGNAL_TYPE_DISPLAY_PORT;
 359                 default:
 360                         return SIGNAL_TYPE_NONE;
 361                 }
 362         }
 363
 364         return SIGNAL_TYPE_NONE;
 365 }
 366
 367 /*
 368  * dc_link_is_dp_sink_present() - Check if there is a native DP
 369  * or passive DP-HDMI dongle connected
 370  */
 371 bool dc_link_is_dp_sink_present(struct dc_link *link)
 372 {
 373         enum gpio_result gpio_result;
 374         uint32_t clock_pin = 0;
 375         uint8_t retry = 0;
 376         struct ddc *ddc;
 377
 378         enum connector_id connector_id =
 379                 dal_graphics_object_id_get_connector_id(link->link_id);
 380
 381         bool present =
 382                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 383                 (connector_id == CONNECTOR_ID_EDP));
 384
 385         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 386
 387         if (!ddc) {
 388                 BREAK_TO_DEBUGGER();
 389                 return present;
 390         }
 391
 392         /* Open GPIO and set it to I2C mode */
 393         /* Note: this GpioMode_Input will be converted
 394          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 395          * which indicates we need additional delay
 396          */
 397
 398         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 399                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 400                 dal_ddc_close(ddc);
 401
 402                 return present;
 403         }
 404
 405         /*
 406          * Read GPIO: DP sink is present if both clock and data pins are zero
 407          *
 408          * [W/A] plug-unplug DP cable, sometimes customer board has
 409          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 410          * then monitor can't br light up. Add retry 3 times
 411          * But in real passive dongle, it need additional 3ms to detect
 412          */
 413         do {
 414                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 415                 ASSERT(gpio_result == GPIO_RESULT_OK);
 416                 if (clock_pin)
 417                         udelay(1000);
 418                 else
 419                         break;
 420         } while (retry++ < 3);
 421
 422         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 423
 424         dal_ddc_close(ddc);
 425
 426         return present;
 427 }
 428
 429 /*
 430  * @brief
 431  * Detect output sink type
 432  */
 433 static enum signal_type link_detect_sink(struct dc_link *link,
 434                                          enum dc_detect_reason reason)
 435 {
 436         enum signal_type result;
 437         struct graphics_object_id enc_id;
 438
 439         if (link->is_dig_mapping_flexible)
 440                 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
 441         else
 442                 enc_id = link->link_enc->id;
 443         result = get_basic_signal_type(enc_id, link->link_id);
 444
 445         /* Use basic signal type for link without physical connector. */
 446         if (link->ep_type != DISPLAY_ENDPOINT_PHY)
 447                 return result;
 448
 449         /* Internal digital encoder will detect only dongles
 450          * that require digital signal
 451          */
 452
 453         /* Detection mechanism is different
 454          * for different native connectors.
 455          * LVDS connector supports only LVDS signal;
 456          * PCIE is a bus slot, the actual connector needs to be detected first;
 457          * eDP connector supports only eDP signal;
 458          * HDMI should check straps for audio
 459          */
 460
 461         /* PCIE detects the actual connector on add-on board */
 462         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 463                 /* ZAZTODO implement PCIE add-on card detection */
 464         }
 465
 466         switch (link->link_id.id) {
 467         case CONNECTOR_ID_HDMI_TYPE_A: {
 468                 /* check audio support:
 469                  * if native HDMI is not supported, switch to DVI
 470                  */
 471                 struct audio_support *aud_support =
 472                                         &link->dc->res_pool->audio_support;
 473
 474                 if (!aud_support->hdmi_audio_native)
 475                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 476                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 477         }
 478         break;
 479         case CONNECTOR_ID_DISPLAY_PORT: {
 480                 /* DP HPD short pulse. Passive DP dongle will not
 481                  * have short pulse
 482                  */
 483                 if (reason != DETECT_REASON_HPDRX) {
 484                         /* Check whether DP signal detected: if not -
 485                          * we assume signal is DVI; it could be corrected
 486                          * to HDMI after dongle detection
 487                          */
 488                         if (!dm_helpers_is_dp_sink_present(link))
 489                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 490                 }
 491         }
 492         break;
 493         default:
 494         break;
 495         }
 496
 497         return result;
 498 }
 499
 500 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 501                                                                  struct audio_support *audio_support)
 502 {
 503         enum signal_type signal = SIGNAL_TYPE_NONE;
 504
 505         switch (dongle_type) {
 506         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 507                 if (audio_support->hdmi_audio_on_dongle)
 508                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 509                 else
 510                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 511                 break;
 512         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 513                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 514                 break;
 515         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 516                 if (audio_support->hdmi_audio_native)
 517                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 518                 else
 519                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 520                 break;
 521         default:
 522                 signal = SIGNAL_TYPE_NONE;
 523                 break;
 524         }
 525
 526         return signal;
 527 }
 528
 529 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 530                                                     struct display_sink_capability *sink_cap,
 531                                                     struct audio_support *audio_support)
 532 {
 533         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 534
 535         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 536                                                         audio_support);
 537 }
 538
 539 static void link_disconnect_sink(struct dc_link *link)
 540 {
 541         if (link->local_sink) {
 542                 dc_sink_release(link->local_sink);
 543                 link->local_sink = NULL;
 544         }
 545
 546         link->dpcd_sink_count = 0;
 547         //link->dpcd_caps.dpcd_rev.raw = 0;
 548 }
 549
 550 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 551 {
 552         dc_sink_release(link->local_sink);
 553         link->local_sink = prev_sink;
 554 }
 555
 556 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 557 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 558 {
 559         bool ret = false;
 560
 561         switch (signal) {
 562         case SIGNAL_TYPE_DISPLAY_PORT:
 563         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 564                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 565                 break;
 566         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 567         case SIGNAL_TYPE_DVI_DUAL_LINK:
 568         case SIGNAL_TYPE_HDMI_TYPE_A:
 569         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 570          * we can poll for bksv but some displays have an issue with this. Since its so rare
 571          * for a display to not be 1.4 capable, this assumtion is ok
 572          */
 573                 ret = true;
 574                 break;
 575         default:
 576                 break;
 577         }
 578         return ret;
 579 }
 580
 581 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 582 {
 583         bool ret = false;
 584
 585         switch (signal) {
 586         case SIGNAL_TYPE_DISPLAY_PORT:
 587         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 588                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 589                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 590                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 591                 break;
 592         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 593         case SIGNAL_TYPE_DVI_DUAL_LINK:
 594         case SIGNAL_TYPE_HDMI_TYPE_A:
 595                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 596                 break;
 597         default:
 598                 break;
 599         }
 600
 601         return ret;
 602 }
 603
 604 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 605 {
 606         struct hdcp_protection_message msg22;
 607         struct hdcp_protection_message msg14;
 608
 609         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 610         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 611         memset(link->hdcp_caps.rx_caps.raw, 0,
 612                 sizeof(link->hdcp_caps.rx_caps.raw));
 613
 614         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 615                         link->ddc->transaction_type ==
 616                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 617                         link->connector_signal == SIGNAL_TYPE_EDP) {
 618                 msg22.data = link->hdcp_caps.rx_caps.raw;
 619                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 620                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 621         } else {
 622                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 623                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 624                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 625         }
 626         msg22.version = HDCP_VERSION_22;
 627         msg22.link = HDCP_LINK_PRIMARY;
 628         msg22.max_retries = 5;
 629         dc_process_hdcp_msg(signal, link, &msg22);
 630
 631         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 632                 msg14.data = &link->hdcp_caps.bcaps.raw;
 633                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 634                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 635                 msg14.version = HDCP_VERSION_14;
 636                 msg14.link = HDCP_LINK_PRIMARY;
 637                 msg14.max_retries = 5;
 638
 639                 dc_process_hdcp_msg(signal, link, &msg14);
 640         }
 641
 642 }
 643 #endif
 644
 645 static void read_current_link_settings_on_detect(struct dc_link *link)
 646 {
 647         union lane_count_set lane_count_set = {0};
 648         uint8_t link_bw_set;
 649         uint8_t link_rate_set;
 650         uint32_t read_dpcd_retry_cnt = 10;
 651         enum dc_status status = DC_ERROR_UNEXPECTED;
 652         int i;
 653         union max_down_spread max_down_spread = {0};
 654
 655         // Read DPCD 00101h to find out the number of lanes currently set
 656         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 657                 status = core_link_read_dpcd(link,
 658                                              DP_LANE_COUNT_SET,
 659                                              &lane_count_set.raw,
 660                                              sizeof(lane_count_set));
 661                 /* First DPCD read after VDD ON can fail if the particular board
 662                  * does not have HPD pin wired correctly. So if DPCD read fails,
 663                  * which it should never happen, retry a few times. Target worst
 664                  * case scenario of 80 ms.
 665                  */
 666                 if (status == DC_OK) {
 667                         link->cur_link_settings.lane_count =
 668                                         lane_count_set.bits.LANE_COUNT_SET;
 669                         break;
 670                 }
 671
 672                 msleep(8);
 673         }
 674
 675         // Read DPCD 00100h to find if standard link rates are set
 676         core_link_read_dpcd(link, DP_LINK_BW_SET,
 677                             &link_bw_set, sizeof(link_bw_set));
 678
 679         if (link_bw_set == 0) {
 680                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 681                         /* If standard link rates are not being used,
 682                          * Read DPCD 00115h to find the edp link rate set used
 683                          */
 684                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 685                                             &link_rate_set, sizeof(link_rate_set));
 686
 687                         // edp_supported_link_rates_count = 0 for DP
 688                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 689                                 link->cur_link_settings.link_rate =
 690                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 691                                 link->cur_link_settings.link_rate_set = link_rate_set;
 692                                 link->cur_link_settings.use_link_rate_set = true;
 693                         }
 694                 } else {
 695                         // Link Rate not found. Seamless boot may not work.
 696                         ASSERT(false);
 697                 }
 698         } else {
 699                 link->cur_link_settings.link_rate = link_bw_set;
 700                 link->cur_link_settings.use_link_rate_set = false;
 701         }
 702         // Read DPCD 00003h to find the max down spread.
 703         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 704                             &max_down_spread.raw, sizeof(max_down_spread));
 705         link->cur_link_settings.link_spread =
 706                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 707                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 708 }
 709
 710 static bool detect_dp(struct dc_link *link,
 711                       struct display_sink_capability *sink_caps,
 712                       enum dc_detect_reason reason)
 713 {
 714         struct audio_support *audio_support = &link->dc->res_pool->audio_support;
 715
 716         sink_caps->signal = link_detect_sink(link, reason);
 717         sink_caps->transaction_type =
 718                 get_ddc_transaction_type(sink_caps->signal);
 719
 720         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 721                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 722                 if (!detect_dp_sink_caps(link))
 723                         return false;
 724
 725                 if (is_dp_branch_device(link))
 726                         /* DP SST branch */
 727                         link->type = dc_connection_sst_branch;
 728         } else {
 729                 /* DP passive dongles */
 730                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 731                                                                 sink_caps,
 732                                                                 audio_support);
 733                 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 734                 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
 735                 link->dpcd_caps.dpcd_rev.raw = 0;
 736         }
 737
 738         return true;
 739 }
 740
 741 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 742 {
 743         if (old_edid->length != new_edid->length)
 744                 return false;
 745
 746         if (new_edid->length == 0)
 747                 return false;
 748
 749         return (memcmp(old_edid->raw_edid,
 750                        new_edid->raw_edid, new_edid->length) == 0);
 751 }
 752
 753 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 754 {
 755         /**
 756          * something is terribly wrong if time out is > 200ms. (5Hz)
 757          * 500 microseconds * 400 tries us 200 ms
 758          **/
 759         unsigned int sleep_time_in_microseconds = 500;
 760         unsigned int tries_allowed = 400;
 761         bool is_in_alt_mode;
 762         unsigned long long enter_timestamp;
 763         unsigned long long finish_timestamp;
 764         unsigned long long time_taken_in_ns;
 765         int tries_taken;
 766
 767         DC_LOGGER_INIT(link->ctx->logger);
 768
 769         if (!link->link_enc->funcs->is_in_alt_mode)
 770                 return true;
 771
 772         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 773         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 774
 775         if (is_in_alt_mode)
 776                 return true;
 777
 778         enter_timestamp = dm_get_timestamp(link->ctx);
 779
 780         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 781                 udelay(sleep_time_in_microseconds);
 782                 /* ask the link if alt mode is enabled, if so return ok */
 783                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 784                         finish_timestamp = dm_get_timestamp(link->ctx);
 785                         time_taken_in_ns =
 786                                 dm_get_elapse_time_in_ns(link->ctx,
 787                                                          finish_timestamp,
 788                                                          enter_timestamp);
 789                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 790                                        div_u64(time_taken_in_ns, 1000000));
 791                         return true;
 792                 }
 793         }
 794         finish_timestamp = dm_get_timestamp(link->ctx);
 795         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 796                                                     enter_timestamp);
 797         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 798                        div_u64(time_taken_in_ns, 1000000));
 799         return false;
 800 }
 801
 802 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 803 {
 804 #if defined(CONFIG_DRM_AMD_DC_DCN)
 805         /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
 806          * reports DSC support.
 807          */
 808         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
 809                         link->type == dc_connection_mst_branch &&
 810                         link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
 811                         link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
 812                         link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
 813                         !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
 814                 link->wa_flags.dpia_mst_dsc_always_on = true;
 815 #endif
 816 }
 817
 818 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 819 {
 820         /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
 821         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 822                 link->wa_flags.dpia_mst_dsc_always_on = false;
 823 }
 824
 825 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
 826 {
 827         DC_LOGGER_INIT(link->ctx->logger);
 828
 829         LINK_INFO("link=%d, mst branch is now Connected\n",
 830                   link->link_index);
 831
 832         apply_dpia_mst_dsc_always_on_wa(link);
 833         link->type = dc_connection_mst_branch;
 834         dm_helpers_dp_update_branch_info(link->ctx, link);
 835         if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
 836                         link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
 837                 link_disconnect_sink(link);
 838         } else {
 839                 link->type = dc_connection_sst_branch;
 840         }
 841
 842         return link->type == dc_connection_mst_branch;
 843 }
 844
 845 static bool reset_cur_dp_mst_topology(struct dc_link *link)
 846 {
 847         bool result = false;
 848         DC_LOGGER_INIT(link->ctx->logger);
 849
 850         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 851                   link->link_index);
 852
 853         revert_dpia_mst_dsc_always_on_wa(link);
 854         result = dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 855
 856         link->mst_stream_alloc_table.stream_count = 0;
 857         memset(link->mst_stream_alloc_table.stream_allocations,
 858                         0,
 859                         sizeof(link->mst_stream_alloc_table.stream_allocations));
 860         return result;
 861 }
 862
 863 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
 864                 enum dc_detect_reason reason)
 865 {
 866         int i;
 867         bool can_apply_seamless_boot = false;
 868
 869         for (i = 0; i < dc->current_state->stream_count; i++) {
 870                 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
 871                         can_apply_seamless_boot = true;
 872                         break;
 873                 }
 874         }
 875
 876         return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
 877 }
 878
 879 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 880 {
 881 #if defined(CONFIG_DRM_AMD_DC_DCN)
 882         dc_z10_restore(dc);
 883 #endif
 884         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
 885 }
 886
 887 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 888 {
 889         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
 890 }
 891
 892 static void set_all_streams_dpms_off_for_link(struct dc_link *link)
 893 {
 894         int i;
 895         struct pipe_ctx *pipe_ctx;
 896         struct dc_stream_update stream_update;
 897         bool dpms_off = true;
 898         struct link_resource link_res = {0};
 899
 900         memset(&stream_update, 0, sizeof(stream_update));
 901         stream_update.dpms_off = &dpms_off;
 902
 903         for (i = 0; i < MAX_PIPES; i++) {
 904                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
 905                 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
 906                                 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) {
 907                         stream_update.stream = pipe_ctx->stream;
 908                         dc_commit_updates_for_stream(link->ctx->dc, NULL, 0,
 909                                         pipe_ctx->stream, &stream_update,
 910                                         link->ctx->dc->current_state);
 911                 }
 912         }
 913
 914         /* link can be also enabled by vbios. In this case it is not recorded
 915          * in pipe_ctx. Disable link phy here to make sure it is completely off
 916          */
 917         dp_disable_link_phy(link, &link_res, link->connector_signal);
 918 }
 919
 920 static void verify_link_capability_destructive(struct dc_link *link,
 921                 struct dc_sink *sink,
 922                 enum dc_detect_reason reason)
 923 {
 924         bool should_prepare_phy_clocks =
 925                         should_prepare_phy_clocks_for_link_verification(link->dc, reason);
 926
 927         if (should_prepare_phy_clocks)
 928                 prepare_phy_clocks_for_destructive_link_verification(link->dc);
 929
 930         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 931                 struct dc_link_settings known_limit_link_setting =
 932                                 dp_get_max_link_cap(link);
 933                 set_all_streams_dpms_off_for_link(link);
 934                 dp_verify_link_cap_with_retries(
 935                                 link, &known_limit_link_setting,
 936                                 LINK_TRAINING_MAX_VERIFY_RETRY);
 937         } else {
 938                 ASSERT(0);
 939         }
 940
 941         if (should_prepare_phy_clocks)
 942                 restore_phy_clocks_for_destructive_link_verification(link->dc);
 943 }
 944
 945 static void verify_link_capability_non_destructive(struct dc_link *link)
 946 {
 947         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 948                 if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
 949                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 950                         /* TODO - should we check link encoder's max link caps here?
 951                          * How do we know which link encoder to check from?
 952                          */
 953                         link->verified_link_cap = link->reported_link_cap;
 954                 else
 955                         link->verified_link_cap = dp_get_max_link_cap(link);
 956         }
 957 }
 958
 959 static bool should_verify_link_capability_destructively(struct dc_link *link,
 960                 enum dc_detect_reason reason)
 961 {
 962         bool destrictive = false;
 963         struct dc_link_settings max_link_cap;
 964         bool is_link_enc_unavailable = link->link_enc &&
 965                         link->dc->res_pool->funcs->link_encs_assign &&
 966                         !link_enc_cfg_is_link_enc_avail(
 967                                         link->ctx->dc,
 968                                         link->link_enc->preferred_engine,
 969                                         link);
 970
 971         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 972                 max_link_cap = dp_get_max_link_cap(link);
 973                 destrictive = true;
 974
 975                 if (link->dc->debug.skip_detection_link_training ||
 976                                 dc_is_embedded_signal(link->local_sink->sink_signal) ||
 977                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
 978                         destrictive = false;
 979                 } else if (dp_get_link_encoding_format(&max_link_cap) ==
 980                                 DP_8b_10b_ENCODING) {
 981                         if (link->dpcd_caps.is_mst_capable ||
 982                                         is_link_enc_unavailable) {
 983                                 destrictive = false;
 984                         }
 985                 }
 986         }
 987
 988         return destrictive;
 989 }
 990
 991 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,
 992                 enum dc_detect_reason reason)
 993 {
 994         if (should_verify_link_capability_destructively(link, reason))
 995                 verify_link_capability_destructive(link, sink, reason);
 996         else
 997                 verify_link_capability_non_destructive(link);
 998 }
 999
1000
1001 /**
1002  * detect_link_and_local_sink() - Detect if a sink is attached to a given link
1003  *
1004  * link->local_sink is created or destroyed as needed.
1005  *
1006  * This does not create remote sinks.
1007  */
1008 static bool detect_link_and_local_sink(struct dc_link *link,
1009                                   enum dc_detect_reason reason)
1010 {
1011         struct dc_sink_init_data sink_init_data = { 0 };
1012         struct display_sink_capability sink_caps = { 0 };
1013         uint32_t i;
1014         bool converter_disable_audio = false;
1015         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
1016         bool same_edid = false;
1017         enum dc_edid_status edid_status;
1018         struct dc_context *dc_ctx = link->ctx;
1019         struct dc_sink *sink = NULL;
1020         struct dc_sink *prev_sink = NULL;
1021         struct dpcd_caps prev_dpcd_caps;
1022         enum dc_connection_type new_connection_type = dc_connection_none;
1023         enum dc_connection_type pre_connection_type = dc_connection_none;
1024         const uint32_t post_oui_delay = 30; // 30ms
1025
1026         DC_LOGGER_INIT(link->ctx->logger);
1027
1028         if (dc_is_virtual_signal(link->connector_signal))
1029                 return false;
1030
1031         if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
1032                 link->connector_signal == SIGNAL_TYPE_EDP) &&
1033                 (!link->dc->config.allow_edp_hotplug_detection)) &&
1034                 link->local_sink) {
1035                 // need to re-write OUI and brightness in resume case
1036                 if (link->connector_signal == SIGNAL_TYPE_EDP &&
1037                         (link->dpcd_sink_ext_caps.bits.oled == 1)) {
1038                         dpcd_set_source_specific_data(link);
1039                         msleep(post_oui_delay);
1040                         dc_link_set_default_brightness_aux(link);
1041                         //TODO: use cached
1042                 }
1043
1044                 return true;
1045         }
1046
1047         if (!dc_link_detect_sink(link, &new_connection_type)) {
1048                 BREAK_TO_DEBUGGER();
1049                 return false;
1050         }
1051
1052         prev_sink = link->local_sink;
1053         if (prev_sink) {
1054                 dc_sink_retain(prev_sink);
1055                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
1056         }
1057
1058         link_disconnect_sink(link);
1059         if (new_connection_type != dc_connection_none) {
1060                 pre_connection_type = link->type;
1061                 link->type = new_connection_type;
1062                 link->link_state_valid = false;
1063
1064                 /* From Disconnected-to-Connected. */
1065                 switch (link->connector_signal) {
1066                 case SIGNAL_TYPE_HDMI_TYPE_A: {
1067                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1068                         if (aud_support->hdmi_audio_native)
1069                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1070                         else
1071                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1072                         break;
1073                 }
1074
1075                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1076                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1077                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1078                         break;
1079                 }
1080
1081                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1082                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1083                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1084                         break;
1085                 }
1086
1087                 case SIGNAL_TYPE_LVDS: {
1088                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1089                         sink_caps.signal = SIGNAL_TYPE_LVDS;
1090                         break;
1091                 }
1092
1093                 case SIGNAL_TYPE_EDP: {
1094                         read_current_link_settings_on_detect(link);
1095
1096                         detect_edp_sink_caps(link);
1097                         read_current_link_settings_on_detect(link);
1098                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1099                         sink_caps.signal = SIGNAL_TYPE_EDP;
1100                         break;
1101                 }
1102
1103                 case SIGNAL_TYPE_DISPLAY_PORT: {
1104                         /* wa HPD high coming too early*/
1105                         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
1106                             link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
1107                                 /* if alt mode times out, return false */
1108                                 if (!wait_for_entering_dp_alt_mode(link))
1109                                         return false;
1110                         }
1111
1112                         if (!detect_dp(link, &sink_caps, reason)) {
1113                                 if (prev_sink)
1114                                         dc_sink_release(prev_sink);
1115                                 return false;
1116                         }
1117
1118                         /* Active SST downstream branch device unplug*/
1119                         if (link->type == dc_connection_sst_branch &&
1120                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1121                                 if (prev_sink)
1122                                         /* Downstream unplug */
1123                                         dc_sink_release(prev_sink);
1124                                 return true;
1125                         }
1126
1127                         /* disable audio for non DP to HDMI active sst converter */
1128                         if (link->type == dc_connection_sst_branch &&
1129                                         is_dp_active_dongle(link) &&
1130                                         (link->dpcd_caps.dongle_type !=
1131                                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1132                                 converter_disable_audio = true;
1133
1134                         // link switch from MST to non-MST stop topology manager
1135                         if (pre_connection_type == dc_connection_mst_branch &&
1136                                         link->type != dc_connection_mst_branch)
1137                                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1138                         break;
1139                 }
1140
1141                 default:
1142                         DC_ERROR("Invalid connector type! signal:%d\n",
1143                                  link->connector_signal);
1144                         if (prev_sink)
1145                                 dc_sink_release(prev_sink);
1146                         return false;
1147                 } /* switch() */
1148
1149                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1150                         link->dpcd_sink_count =
1151                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1152                 else
1153                         link->dpcd_sink_count = 1;
1154
1155                 dal_ddc_service_set_transaction_type(link->ddc,
1156                                                      sink_caps.transaction_type);
1157
1158                 link->aux_mode =
1159                         dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1160
1161                 sink_init_data.link = link;
1162                 sink_init_data.sink_signal = sink_caps.signal;
1163
1164                 sink = dc_sink_create(&sink_init_data);
1165                 if (!sink) {
1166                         DC_ERROR("Failed to create sink!\n");
1167                         if (prev_sink)
1168                                 dc_sink_release(prev_sink);
1169                         return false;
1170                 }
1171
1172                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1173                 sink->converter_disable_audio = converter_disable_audio;
1174
1175                 /* dc_sink_create returns a new reference */
1176                 link->local_sink = sink;
1177
1178                 edid_status = dm_helpers_read_local_edid(link->ctx,
1179                                                          link, sink);
1180
1181                 switch (edid_status) {
1182                 case EDID_BAD_CHECKSUM:
1183                         DC_LOG_ERROR("EDID checksum invalid.\n");
1184                         break;
1185                 case EDID_PARTIAL_VALID:
1186                         DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");
1187                         break;
1188                 case EDID_NO_RESPONSE:
1189                         DC_LOG_ERROR("No EDID read.\n");
1190                         /*
1191                          * Abort detection for non-DP connectors if we have
1192                          * no EDID
1193                          *
1194                          * DP needs to report as connected if HDP is high
1195                          * even if we have no EDID in order to go to
1196                          * fail-safe mode
1197                          */
1198                         if (dc_is_hdmi_signal(link->connector_signal) ||
1199                             dc_is_dvi_signal(link->connector_signal)) {
1200                                 if (prev_sink)
1201                                         dc_sink_release(prev_sink);
1202
1203                                 return false;
1204                         }
1205
1206                         if (link->type == dc_connection_sst_branch &&
1207                                         link->dpcd_caps.dongle_type ==
1208                                                 DISPLAY_DONGLE_DP_VGA_CONVERTER &&
1209                                         reason == DETECT_REASON_HPDRX) {
1210                                 /* Abort detection for DP-VGA adapters when EDID
1211                                  * can't be read and detection reason is VGA-side
1212                                  * hotplug
1213                                  */
1214                                 if (prev_sink)
1215                                         dc_sink_release(prev_sink);
1216                                 link_disconnect_sink(link);
1217
1218                                 return true;
1219                         }
1220
1221                         break;
1222                 default:
1223                         break;
1224                 }
1225
1226                 // Check if edid is the same
1227                 if ((prev_sink) &&
1228                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1229                         same_edid = is_same_edid(&prev_sink->dc_edid,
1230                                                  &sink->dc_edid);
1231
1232                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1233                         link->ctx->dc->debug.hdmi20_disable = true;
1234
1235                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1236                     sink_caps.transaction_type ==
1237                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1238                         /*
1239                          * TODO debug why Dell 2413 doesn't like
1240                          *  two link trainings
1241                          */
1242 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1243                         query_hdcp_capability(sink->sink_signal, link);
1244 #endif
1245                 } else {
1246                         // If edid is the same, then discard new sink and revert back to original sink
1247                         if (same_edid) {
1248                                 link_disconnect_remap(prev_sink, link);
1249                                 sink = prev_sink;
1250                                 prev_sink = NULL;
1251                         }
1252 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1253                         query_hdcp_capability(sink->sink_signal, link);
1254 #endif
1255                 }
1256
1257                 /* HDMI-DVI Dongle */
1258                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1259                     !sink->edid_caps.edid_hdmi)
1260                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1261
1262                 if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
1263                         dp_trace_init(link);
1264
1265                 /* Connectivity log: detection */
1266                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1267                         CONN_DATA_DETECT(link,
1268                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1269                                          DC_EDID_BLOCK_SIZE,
1270                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1271                 }
1272
1273                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1274                         "manufacturer_id = %X, "
1275                         "product_id = %X, "
1276                         "serial_number = %X, "
1277                         "manufacture_week = %d, "
1278                         "manufacture_year = %d, "
1279                         "display_name = %s, "
1280                         "speaker_flag = %d, "
1281                         "audio_mode_count = %d\n",
1282                         __func__,
1283                         sink->edid_caps.manufacturer_id,
1284                         sink->edid_caps.product_id,
1285                         sink->edid_caps.serial_number,
1286                         sink->edid_caps.manufacture_week,
1287                         sink->edid_caps.manufacture_year,
1288                         sink->edid_caps.display_name,
1289                         sink->edid_caps.speaker_flags,
1290                         sink->edid_caps.audio_mode_count);
1291
1292                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1293                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1294                                 "format_code = %d, "
1295                                 "channel_count = %d, "
1296                                 "sample_rate = %d, "
1297                                 "sample_size = %d\n",
1298                                 __func__,
1299                                 i,
1300                                 sink->edid_caps.audio_modes[i].format_code,
1301                                 sink->edid_caps.audio_modes[i].channel_count,
1302                                 sink->edid_caps.audio_modes[i].sample_rate,
1303                                 sink->edid_caps.audio_modes[i].sample_size);
1304                 }
1305         } else {
1306                 /* From Connected-to-Disconnected. */
1307                 link->type = dc_connection_none;
1308                 sink_caps.signal = SIGNAL_TYPE_NONE;
1309                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1310                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1311                  *  the dongle is still there and limits the number of modes we can emulate.
1312                  *  Clear dongle_max_pix_clk on disconnect to fix this
1313                  */
1314                 link->dongle_max_pix_clk = 0;
1315
1316                 dc_link_clear_dprx_states(link);
1317                 dp_trace_reset(link);
1318         }
1319
1320         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1321                   link->link_index, sink,
1322                   (sink_caps.signal ==
1323                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1324                   prev_sink, same_edid);
1325
1326         if (prev_sink)
1327                 dc_sink_release(prev_sink);
1328
1329         return true;
1330 }
1331
1332 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1333 {
1334         bool is_local_sink_detect_success;
1335         bool is_delegated_to_mst_top_mgr = false;
1336         enum dc_connection_type pre_link_type = link->type;
1337
1338         is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
1339
1340         if (is_local_sink_detect_success && link->local_sink)
1341                 verify_link_capability(link, link->local_sink, reason);
1342
1343         if (is_local_sink_detect_success && link->local_sink &&
1344                         dc_is_dp_signal(link->local_sink->sink_signal) &&
1345                         link->dpcd_caps.is_mst_capable)
1346                 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);
1347
1348         if (is_local_sink_detect_success &&
1349                         pre_link_type == dc_connection_mst_branch &&
1350                         link->type != dc_connection_mst_branch)
1351                 is_delegated_to_mst_top_mgr = reset_cur_dp_mst_topology(link);
1352
1353         return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1354 }
1355
1356 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1357 {
1358         uint32_t state;
1359
1360         dal_gpio_lock_pin(dc_link->hpd_gpio);
1361         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1362         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1363
1364         return state;
1365 }
1366
1367 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1368 {
1369         struct gpio *hpd;
1370         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1371
1372         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1373                            link->ctx->gpio_service);
1374
1375         if (hpd) {
1376                 switch (dal_irq_get_source(hpd)) {
1377                 case DC_IRQ_SOURCE_HPD1:
1378                         hpd_id = HPD_SOURCEID1;
1379                 break;
1380                 case DC_IRQ_SOURCE_HPD2:
1381                         hpd_id = HPD_SOURCEID2;
1382                 break;
1383                 case DC_IRQ_SOURCE_HPD3:
1384                         hpd_id = HPD_SOURCEID3;
1385                 break;
1386                 case DC_IRQ_SOURCE_HPD4:
1387                         hpd_id = HPD_SOURCEID4;
1388                 break;
1389                 case DC_IRQ_SOURCE_HPD5:
1390                         hpd_id = HPD_SOURCEID5;
1391                 break;
1392                 case DC_IRQ_SOURCE_HPD6:
1393                         hpd_id = HPD_SOURCEID6;
1394                 break;
1395                 default:
1396                         BREAK_TO_DEBUGGER();
1397                 break;
1398                 }
1399
1400                 dal_gpio_destroy_irq(&hpd);
1401         }
1402
1403         return hpd_id;
1404 }
1405
1406 static enum channel_id get_ddc_line(struct dc_link *link)
1407 {
1408         struct ddc *ddc;
1409         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1410
1411         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1412
1413         if (ddc) {
1414                 switch (dal_ddc_get_line(ddc)) {
1415                 case GPIO_DDC_LINE_DDC1:
1416                         channel = CHANNEL_ID_DDC1;
1417                         break;
1418                 case GPIO_DDC_LINE_DDC2:
1419                         channel = CHANNEL_ID_DDC2;
1420                         break;
1421                 case GPIO_DDC_LINE_DDC3:
1422                         channel = CHANNEL_ID_DDC3;
1423                         break;
1424                 case GPIO_DDC_LINE_DDC4:
1425                         channel = CHANNEL_ID_DDC4;
1426                         break;
1427                 case GPIO_DDC_LINE_DDC5:
1428                         channel = CHANNEL_ID_DDC5;
1429                         break;
1430                 case GPIO_DDC_LINE_DDC6:
1431                         channel = CHANNEL_ID_DDC6;
1432                         break;
1433                 case GPIO_DDC_LINE_DDC_VGA:
1434                         channel = CHANNEL_ID_DDC_VGA;
1435                         break;
1436                 case GPIO_DDC_LINE_I2C_PAD:
1437                         channel = CHANNEL_ID_I2C_PAD;
1438                         break;
1439                 default:
1440                         BREAK_TO_DEBUGGER();
1441                         break;
1442                 }
1443         }
1444
1445         return channel;
1446 }
1447
1448 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1449 {
1450         switch (encoder.id) {
1451         case ENCODER_ID_INTERNAL_UNIPHY:
1452                 switch (encoder.enum_id) {
1453                 case ENUM_ID_1:
1454                         return TRANSMITTER_UNIPHY_A;
1455                 case ENUM_ID_2:
1456                         return TRANSMITTER_UNIPHY_B;
1457                 default:
1458                         return TRANSMITTER_UNKNOWN;
1459                 }
1460         break;
1461         case ENCODER_ID_INTERNAL_UNIPHY1:
1462                 switch (encoder.enum_id) {
1463                 case ENUM_ID_1:
1464                         return TRANSMITTER_UNIPHY_C;
1465                 case ENUM_ID_2:
1466                         return TRANSMITTER_UNIPHY_D;
1467                 default:
1468                         return TRANSMITTER_UNKNOWN;
1469                 }
1470         break;
1471         case ENCODER_ID_INTERNAL_UNIPHY2:
1472                 switch (encoder.enum_id) {
1473                 case ENUM_ID_1:
1474                         return TRANSMITTER_UNIPHY_E;
1475                 case ENUM_ID_2:
1476                         return TRANSMITTER_UNIPHY_F;
1477                 default:
1478                         return TRANSMITTER_UNKNOWN;
1479                 }
1480         break;
1481         case ENCODER_ID_INTERNAL_UNIPHY3:
1482                 switch (encoder.enum_id) {
1483                 case ENUM_ID_1:
1484                         return TRANSMITTER_UNIPHY_G;
1485                 default:
1486                         return TRANSMITTER_UNKNOWN;
1487                 }
1488         break;
1489         case ENCODER_ID_EXTERNAL_NUTMEG:
1490                 switch (encoder.enum_id) {
1491                 case ENUM_ID_1:
1492                         return TRANSMITTER_NUTMEG_CRT;
1493                 default:
1494                         return TRANSMITTER_UNKNOWN;
1495                 }
1496         break;
1497         case ENCODER_ID_EXTERNAL_TRAVIS:
1498                 switch (encoder.enum_id) {
1499                 case ENUM_ID_1:
1500                         return TRANSMITTER_TRAVIS_CRT;
1501                 case ENUM_ID_2:
1502                         return TRANSMITTER_TRAVIS_LCD;
1503                 default:
1504                         return TRANSMITTER_UNKNOWN;
1505                 }
1506         break;
1507         default:
1508                 return TRANSMITTER_UNKNOWN;
1509         }
1510 }
1511
1512 static bool dc_link_construct_legacy(struct dc_link *link,
1513                                      const struct link_init_data *init_params)
1514 {
1515         uint8_t i;
1516         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1517         struct dc_context *dc_ctx = init_params->ctx;
1518         struct encoder_init_data enc_init_data = { 0 };
1519         struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1520         struct integrated_info *info;
1521         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1522         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1523         struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1524
1525         DC_LOGGER_INIT(dc_ctx->logger);
1526
1527         info = kzalloc(sizeof(*info), GFP_KERNEL);
1528         if (!info)
1529                 goto create_fail;
1530
1531         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1532         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1533
1534         link->link_status.dpcd_caps = &link->dpcd_caps;
1535
1536         link->dc = init_params->dc;
1537         link->ctx = dc_ctx;
1538         link->link_index = init_params->link_index;
1539
1540         memset(&link->preferred_training_settings, 0,
1541                sizeof(struct dc_link_training_overrides));
1542         memset(&link->preferred_link_setting, 0,
1543                sizeof(struct dc_link_settings));
1544
1545         link->link_id =
1546                 bios->funcs->get_connector_id(bios, init_params->connector_index);
1547
1548         link->ep_type = DISPLAY_ENDPOINT_PHY;
1549
1550         DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1551
1552         if (bios->funcs->get_disp_connector_caps_info) {
1553                 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1554                 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1555                 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1556         }
1557
1558         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1559                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1560                                      __func__, init_params->connector_index,
1561                                      link->link_id.type, OBJECT_TYPE_CONNECTOR);
1562                 goto create_fail;
1563         }
1564
1565         if (link->dc->res_pool->funcs->link_init)
1566                 link->dc->res_pool->funcs->link_init(link);
1567
1568         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1569                                       link->ctx->gpio_service);
1570
1571         if (link->hpd_gpio) {
1572                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1573                 dal_gpio_unlock_pin(link->hpd_gpio);
1574                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1575
1576                 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1577                 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1578         }
1579
1580         switch (link->link_id.id) {
1581         case CONNECTOR_ID_HDMI_TYPE_A:
1582                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1583
1584                 break;
1585         case CONNECTOR_ID_SINGLE_LINK_DVID:
1586         case CONNECTOR_ID_SINGLE_LINK_DVII:
1587                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1588                 break;
1589         case CONNECTOR_ID_DUAL_LINK_DVID:
1590         case CONNECTOR_ID_DUAL_LINK_DVII:
1591                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1592                 break;
1593         case CONNECTOR_ID_DISPLAY_PORT:
1594                 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1595
1596                 if (link->hpd_gpio)
1597                         link->irq_source_hpd_rx =
1598                                         dal_irq_get_rx_source(link->hpd_gpio);
1599
1600                 break;
1601         case CONNECTOR_ID_EDP:
1602                 link->connector_signal = SIGNAL_TYPE_EDP;
1603
1604                 if (link->hpd_gpio) {
1605                         if (!link->dc->config.allow_edp_hotplug_detection)
1606                                 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1607                         link->irq_source_hpd_rx =
1608                                         dal_irq_get_rx_source(link->hpd_gpio);
1609                 }
1610
1611                 break;
1612         case CONNECTOR_ID_LVDS:
1613                 link->connector_signal = SIGNAL_TYPE_LVDS;
1614                 break;
1615         default:
1616                 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1617                                link->link_id.id);
1618                 goto create_fail;
1619         }
1620
1621         /* TODO: #DAL3 Implement id to str function.*/
1622         LINK_INFO("Connector[%d] description:"
1623                   "signal %d\n",
1624                   init_params->connector_index,
1625                   link->connector_signal);
1626
1627         ddc_service_init_data.ctx = link->ctx;
1628         ddc_service_init_data.id = link->link_id;
1629         ddc_service_init_data.link = link;
1630         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1631
1632         if (!link->ddc) {
1633                 DC_ERROR("Failed to create ddc_service!\n");
1634                 goto ddc_create_fail;
1635         }
1636
1637         if (!link->ddc->ddc_pin) {
1638                 DC_ERROR("Failed to get I2C info for connector!\n");
1639                 goto ddc_create_fail;
1640         }
1641
1642         link->ddc_hw_inst =
1643                 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1644
1645
1646         if (link->dc->res_pool->funcs->panel_cntl_create &&
1647                 (link->link_id.id == CONNECTOR_ID_EDP ||
1648                         link->link_id.id == CONNECTOR_ID_LVDS)) {
1649                 panel_cntl_init_data.ctx = dc_ctx;
1650                 panel_cntl_init_data.inst =
1651                         panel_cntl_init_data.ctx->dc_edp_id_count;
1652                 link->panel_cntl =
1653                         link->dc->res_pool->funcs->panel_cntl_create(
1654                                                                 &panel_cntl_init_data);
1655                 panel_cntl_init_data.ctx->dc_edp_id_count++;
1656
1657                 if (link->panel_cntl == NULL) {
1658                         DC_ERROR("Failed to create link panel_cntl!\n");
1659                         goto panel_cntl_create_fail;
1660                 }
1661         }
1662
1663         enc_init_data.ctx = dc_ctx;
1664         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1665                               &enc_init_data.encoder);
1666         enc_init_data.connector = link->link_id;
1667         enc_init_data.channel = get_ddc_line(link);
1668         enc_init_data.hpd_source = get_hpd_line(link);
1669
1670         link->hpd_src = enc_init_data.hpd_source;
1671
1672         enc_init_data.transmitter =
1673                 translate_encoder_to_transmitter(enc_init_data.encoder);
1674         link->link_enc =
1675                 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1676
1677         if (!link->link_enc) {
1678                 DC_ERROR("Failed to create link encoder!\n");
1679                 goto link_enc_create_fail;
1680         }
1681
1682         DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1683         DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE);
1684
1685         /* Update link encoder tracking variables. These are used for the dynamic
1686          * assignment of link encoders to streams.
1687          */
1688         link->eng_id = link->link_enc->preferred_engine;
1689         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1690         link->dc->res_pool->dig_link_enc_count++;
1691
1692         link->link_enc_hw_inst = link->link_enc->transmitter;
1693
1694         for (i = 0; i < 4; i++) {
1695                 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1696                                              link->link_id, i,
1697                                              &link->device_tag) != BP_RESULT_OK) {
1698                         DC_ERROR("Failed to find device tag!\n");
1699                         goto device_tag_fail;
1700                 }
1701
1702                 /* Look for device tag that matches connector signal,
1703                  * CRT for rgb, LCD for other supported signal tyes
1704                  */
1705                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1706                                                       link->device_tag.dev_id))
1707                         continue;
1708                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1709                     link->connector_signal != SIGNAL_TYPE_RGB)
1710                         continue;
1711                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1712                     link->connector_signal == SIGNAL_TYPE_RGB)
1713                         continue;
1714
1715                 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1716                 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1717                 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1718                 break;
1719         }
1720
1721         if (bios->integrated_info)
1722                 memcpy(info, bios->integrated_info, sizeof(*info));
1723
1724         /* Look for channel mapping corresponding to connector and device tag */
1725         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1726                 struct external_display_path *path =
1727                         &info->ext_disp_conn_info.path[i];
1728
1729                 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1730                     path->device_connector_id.id == link->link_id.id &&
1731                     path->device_connector_id.type == link->link_id.type) {
1732                         if (link->device_tag.acpi_device != 0 &&
1733                             path->device_acpi_enum == link->device_tag.acpi_device) {
1734                                 link->ddi_channel_mapping = path->channel_mapping;
1735                                 link->chip_caps = path->caps;
1736                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1737                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1738                         } else if (path->device_tag ==
1739                                    link->device_tag.dev_id.raw_device_tag) {
1740                                 link->ddi_channel_mapping = path->channel_mapping;
1741                                 link->chip_caps = path->caps;
1742                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1743                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1744                         }
1745
1746                         if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
1747                                 link->bios_forced_drive_settings.VOLTAGE_SWING =
1748                                                 (info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
1749                                 link->bios_forced_drive_settings.PRE_EMPHASIS =
1750                                                 ((info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
1751                         }
1752
1753                         break;
1754                 }
1755         }
1756
1757         if (bios->funcs->get_atom_dc_golden_table)
1758                 bios->funcs->get_atom_dc_golden_table(bios);
1759
1760         /*
1761          * TODO check if GPIO programmed correctly
1762          *
1763          * If GPIO isn't programmed correctly HPD might not rise or drain
1764          * fast enough, leading to bounces.
1765          */
1766         program_hpd_filter(link);
1767
1768         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1769
1770         DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1771         kfree(info);
1772         return true;
1773 device_tag_fail:
1774         link->link_enc->funcs->destroy(&link->link_enc);
1775 link_enc_create_fail:
1776         if (link->panel_cntl != NULL)
1777                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1778 panel_cntl_create_fail:
1779         dal_ddc_service_destroy(&link->ddc);
1780 ddc_create_fail:
1781 create_fail:
1782
1783         if (link->hpd_gpio) {
1784                 dal_gpio_destroy_irq(&link->hpd_gpio);
1785                 link->hpd_gpio = NULL;
1786         }
1787
1788         DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1789         kfree(info);
1790
1791         return false;
1792 }
1793
1794 static bool dc_link_construct_dpia(struct dc_link *link,
1795                                    const struct link_init_data *init_params)
1796 {
1797         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1798         struct dc_context *dc_ctx = init_params->ctx;
1799
1800         DC_LOGGER_INIT(dc_ctx->logger);
1801
1802         /* Initialized irq source for hpd and hpd rx */
1803         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1804         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1805         link->link_status.dpcd_caps = &link->dpcd_caps;
1806
1807         link->dc = init_params->dc;
1808         link->ctx = dc_ctx;
1809         link->link_index = init_params->link_index;
1810
1811         memset(&link->preferred_training_settings, 0,
1812                sizeof(struct dc_link_training_overrides));
1813         memset(&link->preferred_link_setting, 0,
1814                sizeof(struct dc_link_settings));
1815
1816         /* Dummy Init for linkid */
1817         link->link_id.type = OBJECT_TYPE_CONNECTOR;
1818         link->link_id.id = CONNECTOR_ID_DISPLAY_PORT;
1819         link->link_id.enum_id = ENUM_ID_1 + init_params->connector_index;
1820         link->is_internal_display = false;
1821         link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1822         LINK_INFO("Connector[%d] description:signal %d\n",
1823                   init_params->connector_index,
1824                   link->connector_signal);
1825
1826         link->ep_type = DISPLAY_ENDPOINT_USB4_DPIA;
1827         link->is_dig_mapping_flexible = true;
1828
1829         /* TODO: Initialize link : funcs->link_init */
1830
1831         ddc_service_init_data.ctx = link->ctx;
1832         ddc_service_init_data.id = link->link_id;
1833         ddc_service_init_data.link = link;
1834         /* Set indicator for dpia link so that ddc won't be created */
1835         ddc_service_init_data.is_dpia_link = true;
1836
1837         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1838         if (!link->ddc) {
1839                 DC_ERROR("Failed to create ddc_service!\n");
1840                 goto ddc_create_fail;
1841         }
1842
1843         /* Set dpia port index : 0 to number of dpia ports */
1844         link->ddc_hw_inst = init_params->connector_index;
1845
1846         /* TODO: Create link encoder */
1847
1848         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1849
1850         /* Some docks seem to NAK I2C writes to segment pointer with mot=0. */
1851         link->wa_flags.dp_mot_reset_segment = true;
1852
1853         return true;
1854
1855 ddc_create_fail:
1856         return false;
1857 }
1858
1859 static bool dc_link_construct(struct dc_link *link,
1860                               const struct link_init_data *init_params)
1861 {
1862         /* Handle dpia case */
1863         if (init_params->is_dpia_link)
1864                 return dc_link_construct_dpia(link, init_params);
1865         else
1866                 return dc_link_construct_legacy(link, init_params);
1867 }
1868 /*******************************************************************************
1869  * Public functions
1870  ******************************************************************************/
1871 struct dc_link *link_create(const struct link_init_data *init_params)
1872 {
1873         struct dc_link *link =
1874                         kzalloc(sizeof(*link), GFP_KERNEL);
1875
1876         if (NULL == link)
1877                 goto alloc_fail;
1878
1879         if (false == dc_link_construct(link, init_params))
1880                 goto construct_fail;
1881
1882         /*
1883          * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
1884          * since struct preferred_link_setting won't be reset after S3.
1885          */
1886         link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
1887
1888         return link;
1889
1890 construct_fail:
1891         kfree(link);
1892
1893 alloc_fail:
1894         return NULL;
1895 }
1896
1897 void link_destroy(struct dc_link **link)
1898 {
1899         dc_link_destruct(*link);
1900         kfree(*link);
1901         *link = NULL;
1902 }
1903
1904 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1905 {
1906         struct dc_stream_state *stream = pipe_ctx->stream;
1907
1908         if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1909                 struct dc_link *link = stream->link;
1910                 union down_spread_ctrl old_downspread;
1911                 union down_spread_ctrl new_downspread;
1912
1913                 memset(&old_downspread, 0, sizeof(old_downspread));
1914
1915                 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1916                                 &old_downspread.raw, sizeof(old_downspread));
1917
1918                 new_downspread.raw = old_downspread.raw;
1919
1920                 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1921                                 (stream->ignore_msa_timing_param) ? 1 : 0;
1922
1923                 if (new_downspread.raw != old_downspread.raw) {
1924                         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1925                                 &new_downspread.raw, sizeof(new_downspread));
1926                 }
1927
1928         } else {
1929                 dm_helpers_mst_enable_stream_features(stream);
1930         }
1931 }
1932
1933 static enum dc_status enable_link_dp(struct dc_state *state,
1934                                      struct pipe_ctx *pipe_ctx)
1935 {
1936         struct dc_stream_state *stream = pipe_ctx->stream;
1937         enum dc_status status;
1938         bool skip_video_pattern;
1939         struct dc_link *link = stream->link;
1940         struct dc_link_settings link_settings = {0};
1941         bool fec_enable;
1942         int i;
1943         bool apply_seamless_boot_optimization = false;
1944         uint32_t bl_oled_enable_delay = 50; // in ms
1945         const uint32_t post_oui_delay = 30; // 30ms
1946         /* Reduce link bandwidth between failed link training attempts. */
1947         bool do_fallback = false;
1948
1949         // check for seamless boot
1950         for (i = 0; i < state->stream_count; i++) {
1951                 if (state->streams[i]->apply_seamless_boot_optimization) {
1952                         apply_seamless_boot_optimization = true;
1953                         break;
1954                 }
1955         }
1956
1957         /* get link settings for video mode timing */
1958         decide_link_settings(stream, &link_settings);
1959
1960         /* Train with fallback when enabling DPIA link. Conventional links are
1961          * trained with fallback during sink detection.
1962          */
1963         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1964                 do_fallback = true;
1965
1966         /*
1967          * Temporary w/a to get DP2.0 link rates to work with SST.
1968          * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved.
1969          */
1970         if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING &&
1971                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
1972                         link->dc->debug.set_mst_en_for_sst) {
1973                 dp_enable_mst_on_sink(link, true);
1974         }
1975
1976         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1977                 /*in case it is not on*/
1978                 link->dc->hwss.edp_power_control(link, true);
1979                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1980         }
1981
1982         if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING) {
1983                 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
1984         } else {
1985                 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1986                                 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1987                 if (state->clk_mgr && !apply_seamless_boot_optimization)
1988                         state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1989                                         state, false);
1990         }
1991
1992         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1993         dpcd_set_source_specific_data(link);
1994         if (link->dpcd_sink_ext_caps.raw != 0)
1995                 msleep(post_oui_delay);
1996
1997         // similarly, mode switch can cause loss of cable ID
1998         dpcd_write_cable_id_to_dprx(link);
1999
2000         skip_video_pattern = true;
2001
2002         if (link_settings.link_rate == LINK_RATE_LOW)
2003                 skip_video_pattern = false;
2004
2005         if (perform_link_training_with_retries(&link_settings,
2006                                                skip_video_pattern,
2007                                                LINK_TRAINING_ATTEMPTS,
2008                                                pipe_ctx,
2009                                                pipe_ctx->stream->signal,
2010                                                do_fallback)) {
2011                 link->cur_link_settings = link_settings;
2012                 status = DC_OK;
2013         } else {
2014                 status = DC_FAIL_DP_LINK_TRAINING;
2015         }
2016
2017         if (link->preferred_training_settings.fec_enable)
2018                 fec_enable = *link->preferred_training_settings.fec_enable;
2019         else
2020                 fec_enable = true;
2021
2022         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING)
2023                 dp_set_fec_enable(link, fec_enable);
2024
2025         // during mode set we do DP_SET_POWER off then on, aux writes are lost
2026         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
2027                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
2028                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
2029                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
2030                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
2031                         msleep(bl_oled_enable_delay);
2032                 dc_link_backlight_enable_aux(link, true);
2033         }
2034
2035         return status;
2036 }
2037
2038 static enum dc_status enable_link_edp(
2039                 struct dc_state *state,
2040                 struct pipe_ctx *pipe_ctx)
2041 {
2042         enum dc_status status;
2043
2044         status = enable_link_dp(state, pipe_ctx);
2045
2046         return status;
2047 }
2048
2049 static enum dc_status enable_link_dp_mst(
2050                 struct dc_state *state,
2051                 struct pipe_ctx *pipe_ctx)
2052 {
2053         struct dc_link *link = pipe_ctx->stream->link;
2054
2055         /* sink signal type after MST branch is MST. Multiple MST sinks
2056          * share one link. Link DP PHY is enable or training only once.
2057          */
2058         if (link->link_status.link_active)
2059                 return DC_OK;
2060
2061         /* clear payload table */
2062         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
2063
2064         /* to make sure the pending down rep can be processed
2065          * before enabling the link
2066          */
2067         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
2068
2069         /* set the sink to MST mode before enabling the link */
2070         dp_enable_mst_on_sink(link, true);
2071
2072         return enable_link_dp(state, pipe_ctx);
2073 }
2074
2075 void dc_link_blank_all_dp_displays(struct dc *dc)
2076 {
2077         unsigned int i;
2078         uint8_t dpcd_power_state = '\0';
2079         enum dc_status status = DC_ERROR_UNEXPECTED;
2080
2081         for (i = 0; i < dc->link_count; i++) {
2082                 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) ||
2083                         (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL))
2084                         continue;
2085
2086                 /* DP 2.0 spec requires that we read LTTPR caps first */
2087                 dp_retrieve_lttpr_cap(dc->links[i]);
2088                 /* if any of the displays are lit up turn them off */
2089                 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
2090                                                         &dpcd_power_state, sizeof(dpcd_power_state));
2091
2092                 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
2093                         dc_link_blank_dp_stream(dc->links[i], true);
2094         }
2095
2096 }
2097
2098 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init)
2099 {
2100         unsigned int j;
2101         struct dc  *dc = link->ctx->dc;
2102         enum signal_type signal = link->connector_signal;
2103
2104         if ((signal == SIGNAL_TYPE_EDP) ||
2105                 (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
2106                 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
2107                         link->link_enc->funcs->get_dig_frontend &&
2108                         link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
2109                         unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2110
2111                         if (fe != ENGINE_ID_UNKNOWN)
2112                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
2113                                         if (fe == dc->res_pool->stream_enc[j]->id) {
2114                                                 dc->res_pool->stream_enc[j]->funcs->dp_blank(link,
2115                                                                         dc->res_pool->stream_enc[j]);
2116                                                 break;
2117                                         }
2118                                 }
2119                 }
2120
2121                 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)
2122                         dp_receiver_power_ctrl(link, false);
2123         }
2124 }
2125
2126 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
2127                 enum engine_id eng_id,
2128                 struct ext_hdmi_settings *settings)
2129 {
2130         bool result = false;
2131         int i = 0;
2132         struct integrated_info *integrated_info =
2133                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
2134
2135         if (integrated_info == NULL)
2136                 return false;
2137
2138         /*
2139          * Get retimer settings from sbios for passing SI eye test for DCE11
2140          * The setting values are varied based on board revision and port id
2141          * Therefore the setting values of each ports is passed by sbios.
2142          */
2143
2144         // Check if current bios contains ext Hdmi settings
2145         if (integrated_info->gpu_cap_info & 0x20) {
2146                 switch (eng_id) {
2147                 case ENGINE_ID_DIGA:
2148                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
2149                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
2150                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
2151                         memmove(settings->reg_settings,
2152                                         integrated_info->dp0_ext_hdmi_reg_settings,
2153                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
2154                         memmove(settings->reg_settings_6g,
2155                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
2156                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
2157                         result = true;
2158                         break;
2159                 case ENGINE_ID_DIGB:
2160                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
2161                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
2162                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
2163                         memmove(settings->reg_settings,
2164                                         integrated_info->dp1_ext_hdmi_reg_settings,
2165                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
2166                         memmove(settings->reg_settings_6g,
2167                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
2168                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
2169                         result = true;
2170                         break;
2171                 case ENGINE_ID_DIGC:
2172                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
2173                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
2174                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
2175                         memmove(settings->reg_settings,
2176                                         integrated_info->dp2_ext_hdmi_reg_settings,
2177                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
2178                         memmove(settings->reg_settings_6g,
2179                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
2180                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
2181                         result = true;
2182                         break;
2183                 case ENGINE_ID_DIGD:
2184                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
2185                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
2186                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
2187                         memmove(settings->reg_settings,
2188                                         integrated_info->dp3_ext_hdmi_reg_settings,
2189                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
2190                         memmove(settings->reg_settings_6g,
2191                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
2192                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
2193                         result = true;
2194                         break;
2195                 default:
2196                         break;
2197                 }
2198
2199                 if (result == true) {
2200                         // Validate settings from bios integrated info table
2201                         if (settings->slv_addr == 0)
2202                                 return false;
2203                         if (settings->reg_num > 9)
2204                                 return false;
2205                         if (settings->reg_num_6g > 3)
2206                                 return false;
2207
2208                         for (i = 0; i < settings->reg_num; i++) {
2209                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
2210                                         return false;
2211                         }
2212
2213                         for (i = 0; i < settings->reg_num_6g; i++) {
2214                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
2215                                         return false;
2216                         }
2217                 }
2218         }
2219
2220         return result;
2221 }
2222
2223 static bool i2c_write(struct pipe_ctx *pipe_ctx,
2224                 uint8_t address, uint8_t *buffer, uint32_t length)
2225 {
2226         struct i2c_command cmd = {0};
2227         struct i2c_payload payload = {0};
2228
2229         memset(&payload, 0, sizeof(payload));
2230         memset(&cmd, 0, sizeof(cmd));
2231
2232         cmd.number_of_payloads = 1;
2233         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
2234         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
2235
2236         payload.address = address;
2237         payload.data = buffer;
2238         payload.length = length;
2239         payload.write = true;
2240         cmd.payloads = &payload;
2241
2242         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
2243                         pipe_ctx->stream->link, &cmd))
2244                 return true;
2245
2246         return false;
2247 }
2248
2249 static void write_i2c_retimer_setting(
2250                 struct pipe_ctx *pipe_ctx,
2251                 bool is_vga_mode,
2252                 bool is_over_340mhz,
2253                 struct ext_hdmi_settings *settings)
2254 {
2255         uint8_t slave_address = (settings->slv_addr >> 1);
2256         uint8_t buffer[2];
2257         const uint8_t apply_rx_tx_change = 0x4;
2258         uint8_t offset = 0xA;
2259         uint8_t value = 0;
2260         int i = 0;
2261         bool i2c_success = false;
2262         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2263
2264         memset(&buffer, 0, sizeof(buffer));
2265
2266         /* Start Ext-Hdmi programming*/
2267
2268         for (i = 0; i < settings->reg_num; i++) {
2269                 /* Apply 3G settings */
2270                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2271
2272                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
2273                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
2274                         i2c_success = i2c_write(pipe_ctx, slave_address,
2275                                                 buffer, sizeof(buffer));
2276                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2277                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2278                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2279
2280                         if (!i2c_success)
2281                                 goto i2c_write_fail;
2282
2283                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2284                          * needs to be set to 1 on every 0xA-0xC write.
2285                          */
2286                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
2287                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
2288                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
2289
2290                                 /* Query current value from offset 0xA */
2291                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
2292                                         value = settings->reg_settings[i].i2c_reg_val;
2293                                 else {
2294                                         i2c_success =
2295                                                 dal_ddc_service_query_ddc_data(
2296                                                 pipe_ctx->stream->link->ddc,
2297                                                 slave_address, &offset, 1, &value, 1);
2298                                         if (!i2c_success)
2299                                                 goto i2c_write_fail;
2300                                 }
2301
2302                                 buffer[0] = offset;
2303                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2304                                 buffer[1] = value | apply_rx_tx_change;
2305                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2306                                                 buffer, sizeof(buffer));
2307                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2308                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2309                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2310                                 if (!i2c_success)
2311                                         goto i2c_write_fail;
2312                         }
2313                 }
2314         }
2315
2316         /* Apply 3G settings */
2317         if (is_over_340mhz) {
2318                 for (i = 0; i < settings->reg_num_6g; i++) {
2319                         /* Apply 3G settings */
2320                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2321
2322                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2323                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2324                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2325                                                         buffer, sizeof(buffer));
2326                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2327                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2328                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2329
2330                                 if (!i2c_success)
2331                                         goto i2c_write_fail;
2332
2333                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2334                                  * needs to be set to 1 on every 0xA-0xC write.
2335                                  */
2336                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2337                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2338                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2339
2340                                         /* Query current value from offset 0xA */
2341                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2342                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
2343                                         else {
2344                                                 i2c_success =
2345                                                                 dal_ddc_service_query_ddc_data(
2346                                                                 pipe_ctx->stream->link->ddc,
2347                                                                 slave_address, &offset, 1, &value, 1);
2348                                                 if (!i2c_success)
2349                                                         goto i2c_write_fail;
2350                                         }
2351
2352                                         buffer[0] = offset;
2353                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
2354                                         buffer[1] = value | apply_rx_tx_change;
2355                                         i2c_success = i2c_write(pipe_ctx, slave_address,
2356                                                         buffer, sizeof(buffer));
2357                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2358                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2359                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2360                                         if (!i2c_success)
2361                                                 goto i2c_write_fail;
2362                                 }
2363                         }
2364                 }
2365         }
2366
2367         if (is_vga_mode) {
2368                 /* Program additional settings if using 640x480 resolution */
2369
2370                 /* Write offset 0xFF to 0x01 */
2371                 buffer[0] = 0xff;
2372                 buffer[1] = 0x01;
2373                 i2c_success = i2c_write(pipe_ctx, slave_address,
2374                                 buffer, sizeof(buffer));
2375                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2376                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2377                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2378                 if (!i2c_success)
2379                         goto i2c_write_fail;
2380
2381                 /* Write offset 0x00 to 0x23 */
2382                 buffer[0] = 0x00;
2383                 buffer[1] = 0x23;
2384                 i2c_success = i2c_write(pipe_ctx, slave_address,
2385                                 buffer, sizeof(buffer));
2386                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2387                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2388                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2389                 if (!i2c_success)
2390                         goto i2c_write_fail;
2391
2392                 /* Write offset 0xff to 0x00 */
2393                 buffer[0] = 0xff;
2394                 buffer[1] = 0x00;
2395                 i2c_success = i2c_write(pipe_ctx, slave_address,
2396                                 buffer, sizeof(buffer));
2397                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2398                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2399                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2400                 if (!i2c_success)
2401                         goto i2c_write_fail;
2402
2403         }
2404
2405         return;
2406
2407 i2c_write_fail:
2408         DC_LOG_DEBUG("Set retimer failed");
2409 }
2410
2411 static void write_i2c_default_retimer_setting(
2412                 struct pipe_ctx *pipe_ctx,
2413                 bool is_vga_mode,
2414                 bool is_over_340mhz)
2415 {
2416         uint8_t slave_address = (0xBA >> 1);
2417         uint8_t buffer[2];
2418         bool i2c_success = false;
2419         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2420
2421         memset(&buffer, 0, sizeof(buffer));
2422
2423         /* Program Slave Address for tuning single integrity */
2424         /* Write offset 0x0A to 0x13 */
2425         buffer[0] = 0x0A;
2426         buffer[1] = 0x13;
2427         i2c_success = i2c_write(pipe_ctx, slave_address,
2428                         buffer, sizeof(buffer));
2429         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2430                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2431                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2432         if (!i2c_success)
2433                 goto i2c_write_fail;
2434
2435         /* Write offset 0x0A to 0x17 */
2436         buffer[0] = 0x0A;
2437         buffer[1] = 0x17;
2438         i2c_success = i2c_write(pipe_ctx, slave_address,
2439                         buffer, sizeof(buffer));
2440         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2441                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2442                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2443         if (!i2c_success)
2444                 goto i2c_write_fail;
2445
2446         /* Write offset 0x0B to 0xDA or 0xD8 */
2447         buffer[0] = 0x0B;
2448         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2449         i2c_success = i2c_write(pipe_ctx, slave_address,
2450                         buffer, sizeof(buffer));
2451         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2452                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2453                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2454         if (!i2c_success)
2455                 goto i2c_write_fail;
2456
2457         /* Write offset 0x0A to 0x17 */
2458         buffer[0] = 0x0A;
2459         buffer[1] = 0x17;
2460         i2c_success = i2c_write(pipe_ctx, slave_address,
2461                         buffer, sizeof(buffer));
2462         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2463                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2464                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2465         if (!i2c_success)
2466                 goto i2c_write_fail;
2467
2468         /* Write offset 0x0C to 0x1D or 0x91 */
2469         buffer[0] = 0x0C;
2470         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2471         i2c_success = i2c_write(pipe_ctx, slave_address,
2472                         buffer, sizeof(buffer));
2473         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2474                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2475                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2476         if (!i2c_success)
2477                 goto i2c_write_fail;
2478
2479         /* Write offset 0x0A to 0x17 */
2480         buffer[0] = 0x0A;
2481         buffer[1] = 0x17;
2482         i2c_success = i2c_write(pipe_ctx, slave_address,
2483                         buffer, sizeof(buffer));
2484         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2485                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2486                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2487         if (!i2c_success)
2488                 goto i2c_write_fail;
2489
2490
2491         if (is_vga_mode) {
2492                 /* Program additional settings if using 640x480 resolution */
2493
2494                 /* Write offset 0xFF to 0x01 */
2495                 buffer[0] = 0xff;
2496                 buffer[1] = 0x01;
2497                 i2c_success = i2c_write(pipe_ctx, slave_address,
2498                                 buffer, sizeof(buffer));
2499                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2500                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2501                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2502                 if (!i2c_success)
2503                         goto i2c_write_fail;
2504
2505                 /* Write offset 0x00 to 0x23 */
2506                 buffer[0] = 0x00;
2507                 buffer[1] = 0x23;
2508                 i2c_success = i2c_write(pipe_ctx, slave_address,
2509                                 buffer, sizeof(buffer));
2510                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2511                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2512                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2513                 if (!i2c_success)
2514                         goto i2c_write_fail;
2515
2516                 /* Write offset 0xff to 0x00 */
2517                 buffer[0] = 0xff;
2518                 buffer[1] = 0x00;
2519                 i2c_success = i2c_write(pipe_ctx, slave_address,
2520                                 buffer, sizeof(buffer));
2521                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2522                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2523                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2524                 if (!i2c_success)
2525                         goto i2c_write_fail;
2526         }
2527
2528         return;
2529
2530 i2c_write_fail:
2531         DC_LOG_DEBUG("Set default retimer failed");
2532 }
2533
2534 static void write_i2c_redriver_setting(
2535                 struct pipe_ctx *pipe_ctx,
2536                 bool is_over_340mhz)
2537 {
2538         uint8_t slave_address = (0xF0 >> 1);
2539         uint8_t buffer[16];
2540         bool i2c_success = false;
2541         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2542
2543         memset(&buffer, 0, sizeof(buffer));
2544
2545         // Program Slave Address for tuning single integrity
2546         buffer[3] = 0x4E;
2547         buffer[4] = 0x4E;
2548         buffer[5] = 0x4E;
2549         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2550
2551         i2c_success = i2c_write(pipe_ctx, slave_address,
2552                                         buffer, sizeof(buffer));
2553         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2554                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2555                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2556                 i2c_success = %d\n",
2557                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2558
2559         if (!i2c_success)
2560                 DC_LOG_DEBUG("Set redriver failed");
2561 }
2562
2563 static void disable_link(struct dc_link *link, const struct link_resource *link_res,
2564                 enum signal_type signal)
2565 {
2566         /*
2567          * TODO: implement call for dp_set_hw_test_pattern
2568          * it is needed for compliance testing
2569          */
2570
2571         /* Here we need to specify that encoder output settings
2572          * need to be calculated as for the set mode,
2573          * it will lead to querying dynamic link capabilities
2574          * which should be done before enable output
2575          */
2576
2577         if (dc_is_dp_signal(signal)) {
2578                 /* SST DP, eDP */
2579                 struct dc_link_settings link_settings = link->cur_link_settings;
2580                 if (dc_is_dp_sst_signal(signal))
2581                         dp_disable_link_phy(link, link_res, signal);
2582                 else
2583                         dp_disable_link_phy_mst(link, link_res, signal);
2584
2585                 if (dc_is_dp_sst_signal(signal) ||
2586                                 link->mst_stream_alloc_table.stream_count == 0) {
2587                         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
2588                                 dp_set_fec_enable(link, false);
2589                                 dp_set_fec_ready(link, link_res, false);
2590                         }
2591                 }
2592         } else {
2593                 if (signal != SIGNAL_TYPE_VIRTUAL)
2594                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2595         }
2596
2597         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2598                 /* MST disable link only when no stream use the link */
2599                 if (link->mst_stream_alloc_table.stream_count <= 0)
2600                         link->link_status.link_active = false;
2601         } else {
2602                 link->link_status.link_active = false;
2603         }
2604 }
2605
2606 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2607 {
2608         struct dc_stream_state *stream = pipe_ctx->stream;
2609         struct dc_link *link = stream->link;
2610         enum dc_color_depth display_color_depth;
2611         enum engine_id eng_id;
2612         struct ext_hdmi_settings settings = {0};
2613         bool is_over_340mhz = false;
2614         bool is_vga_mode = (stream->timing.h_addressable == 640)
2615                         && (stream->timing.v_addressable == 480);
2616
2617         if (stream->phy_pix_clk == 0)
2618                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2619         if (stream->phy_pix_clk > 340000)
2620                 is_over_340mhz = true;
2621
2622         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2623                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2624                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2625                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2626                         /* DP159, Retimer settings */
2627                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2628
2629                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2630                                 write_i2c_retimer_setting(pipe_ctx,
2631                                                 is_vga_mode, is_over_340mhz, &settings);
2632                         } else {
2633                                 write_i2c_default_retimer_setting(pipe_ctx,
2634                                                 is_vga_mode, is_over_340mhz);
2635                         }
2636                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2637                         /* PI3EQX1204, Redriver settings */
2638                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2639                 }
2640         }
2641
2642         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2643                 dal_ddc_service_write_scdc_data(
2644                         stream->link->ddc,
2645                         stream->phy_pix_clk,
2646                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2647
2648         memset(&stream->link->cur_link_settings, 0,
2649                         sizeof(struct dc_link_settings));
2650
2651         display_color_depth = stream->timing.display_color_depth;
2652         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2653                 display_color_depth = COLOR_DEPTH_888;
2654
2655         link->link_enc->funcs->enable_tmds_output(
2656                         link->link_enc,
2657                         pipe_ctx->clock_source->id,
2658                         display_color_depth,
2659                         pipe_ctx->stream->signal,
2660                         stream->phy_pix_clk);
2661
2662         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2663                 dal_ddc_service_read_scdc_data(link->ddc);
2664 }
2665
2666 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2667 {
2668         struct dc_stream_state *stream = pipe_ctx->stream;
2669         struct dc_link *link = stream->link;
2670
2671         if (stream->phy_pix_clk == 0)
2672                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2673
2674         memset(&stream->link->cur_link_settings, 0,
2675                         sizeof(struct dc_link_settings));
2676
2677         link->link_enc->funcs->enable_lvds_output(
2678                         link->link_enc,
2679                         pipe_ctx->clock_source->id,
2680                         stream->phy_pix_clk);
2681
2682 }
2683
2684 /****************************enable_link***********************************/
2685 static enum dc_status enable_link(
2686                 struct dc_state *state,
2687                 struct pipe_ctx *pipe_ctx)
2688 {
2689         enum dc_status status = DC_ERROR_UNEXPECTED;
2690         struct dc_stream_state *stream = pipe_ctx->stream;
2691         struct dc_link *link = stream->link;
2692
2693         /* There's some scenarios where driver is unloaded with display
2694          * still enabled. When driver is reloaded, it may cause a display
2695          * to not light up if there is a mismatch between old and new
2696          * link settings. Need to call disable first before enabling at
2697          * new link settings.
2698          */
2699         if (link->link_status.link_active) {
2700                 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
2701         }
2702
2703         switch (pipe_ctx->stream->signal) {
2704         case SIGNAL_TYPE_DISPLAY_PORT:
2705                 status = enable_link_dp(state, pipe_ctx);
2706                 break;
2707         case SIGNAL_TYPE_EDP:
2708                 status = enable_link_edp(state, pipe_ctx);
2709                 break;
2710         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2711                 status = enable_link_dp_mst(state, pipe_ctx);
2712                 msleep(200);
2713                 break;
2714         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2715         case SIGNAL_TYPE_DVI_DUAL_LINK:
2716         case SIGNAL_TYPE_HDMI_TYPE_A:
2717                 enable_link_hdmi(pipe_ctx);
2718                 status = DC_OK;
2719                 break;
2720         case SIGNAL_TYPE_LVDS:
2721                 enable_link_lvds(pipe_ctx);
2722                 status = DC_OK;
2723                 break;
2724         case SIGNAL_TYPE_VIRTUAL:
2725                 status = DC_OK;
2726                 break;
2727         default:
2728                 break;
2729         }
2730
2731         if (status == DC_OK)
2732                 pipe_ctx->stream->link->link_status.link_active = true;
2733
2734         return status;
2735 }
2736
2737 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2738 {
2739
2740         uint32_t pxl_clk = timing->pix_clk_100hz;
2741
2742         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2743                 pxl_clk /= 2;
2744         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2745                 pxl_clk = pxl_clk * 2 / 3;
2746
2747         if (timing->display_color_depth == COLOR_DEPTH_101010)
2748                 pxl_clk = pxl_clk * 10 / 8;
2749         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2750                 pxl_clk = pxl_clk * 12 / 8;
2751
2752         return pxl_clk;
2753 }
2754
2755 static bool dp_active_dongle_validate_timing(
2756                 const struct dc_crtc_timing *timing,
2757                 const struct dpcd_caps *dpcd_caps)
2758 {
2759         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2760
2761         switch (dpcd_caps->dongle_type) {
2762         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2763         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2764         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2765                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2766                         return true;
2767                 else
2768                         return false;
2769         default:
2770                 break;
2771         }
2772
2773         if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
2774                         dongle_caps->extendedCapValid == true) {
2775                 /* Check Pixel Encoding */
2776                 switch (timing->pixel_encoding) {
2777                 case PIXEL_ENCODING_RGB:
2778                 case PIXEL_ENCODING_YCBCR444:
2779                         break;
2780                 case PIXEL_ENCODING_YCBCR422:
2781                         if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2782                                 return false;
2783                         break;
2784                 case PIXEL_ENCODING_YCBCR420:
2785                         if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2786                                 return false;
2787                         break;
2788                 default:
2789                         /* Invalid Pixel Encoding*/
2790                         return false;
2791                 }
2792
2793                 switch (timing->display_color_depth) {
2794                 case COLOR_DEPTH_666:
2795                 case COLOR_DEPTH_888:
2796                         /*888 and 666 should always be supported*/
2797                         break;
2798                 case COLOR_DEPTH_101010:
2799                         if (dongle_caps->dp_hdmi_max_bpc < 10)
2800                                 return false;
2801                         break;
2802                 case COLOR_DEPTH_121212:
2803                         if (dongle_caps->dp_hdmi_max_bpc < 12)
2804                                 return false;
2805                         break;
2806                 case COLOR_DEPTH_141414:
2807                 case COLOR_DEPTH_161616:
2808                 default:
2809                         /* These color depths are currently not supported */
2810                         return false;
2811                 }
2812
2813                 /* Check 3D format */
2814                 switch (timing->timing_3d_format) {
2815                 case TIMING_3D_FORMAT_NONE:
2816                 case TIMING_3D_FORMAT_FRAME_ALTERNATE:
2817                         /*Only frame alternate 3D is supported on active dongle*/
2818                         break;
2819                 default:
2820                         /*other 3D formats are not supported due to bad infoframe translation */
2821                         return false;
2822                 }
2823
2824 #if defined(CONFIG_DRM_AMD_DC_DCN)
2825                 if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter
2826                         struct dc_crtc_timing outputTiming = *timing;
2827
2828                         if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
2829                                 /* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */
2830                                 outputTiming.flags.DSC = 0;
2831                         if (dc_bandwidth_in_kbps_from_timing(&outputTiming) > dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
2832                                 return false;
2833                 } else { // DP to HDMI TMDS converter
2834                         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2835                                 return false;
2836                 }
2837 #else
2838                 if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2839                         return false;
2840 #endif
2841         }
2842
2843         if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
2844                         dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
2845                         dongle_caps->dfp_cap_ext.supported) {
2846
2847                 if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
2848                         return false;
2849
2850                 if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
2851                         return false;
2852
2853                 if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
2854                         return false;
2855
2856                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
2857                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2858                                 return false;
2859                         if (timing->display_color_depth == COLOR_DEPTH_666 &&
2860                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
2861                                 return false;
2862                         else if (timing->display_color_depth == COLOR_DEPTH_888 &&
2863                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
2864                                 return false;
2865                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2866                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
2867                                 return false;
2868                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2869                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
2870                                 return false;
2871                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2872                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
2873                                 return false;
2874                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
2875                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2876                                 return false;
2877                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2878                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
2879                                 return false;
2880                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2881                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
2882                                 return false;
2883                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2884                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
2885                                 return false;
2886                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2887                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
2888                                 return false;
2889                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
2890                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2891                                 return false;
2892                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2893                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
2894                                 return false;
2895                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2896                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
2897                                 return false;
2898                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2899                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
2900                                 return false;
2901                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2902                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
2903                                 return false;
2904                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2905                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2906                                 return false;
2907                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2908                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
2909                                 return false;
2910                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2911                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
2912                                 return false;
2913                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2914                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
2915                                 return false;
2916                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2917                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
2918                                 return false;
2919                 }
2920         }
2921
2922         return true;
2923 }
2924
2925 enum dc_status dc_link_validate_mode_timing(
2926                 const struct dc_stream_state *stream,
2927                 struct dc_link *link,
2928                 const struct dc_crtc_timing *timing)
2929 {
2930         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2931         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2932
2933         /* A hack to avoid failing any modes for EDID override feature on
2934          * topology change such as lower quality cable for DP or different dongle
2935          */
2936         if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2937                 return DC_OK;
2938
2939         /* Passive Dongle */
2940         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2941                 return DC_EXCEED_DONGLE_CAP;
2942
2943         /* Active Dongle*/
2944         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2945                 return DC_EXCEED_DONGLE_CAP;
2946
2947         switch (stream->signal) {
2948         case SIGNAL_TYPE_EDP:
2949         case SIGNAL_TYPE_DISPLAY_PORT:
2950                 if (!dp_validate_mode_timing(
2951                                 link,
2952                                 timing))
2953                         return DC_NO_DP_LINK_BANDWIDTH;
2954                 break;
2955
2956         default:
2957                 break;
2958         }
2959
2960         return DC_OK;
2961 }
2962
2963 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2964 {
2965         int i;
2966         struct dc *dc = NULL;
2967         struct abm *abm = NULL;
2968
2969         if (!link || !link->ctx)
2970                 return NULL;
2971
2972         dc = link->ctx->dc;
2973
2974         for (i = 0; i < MAX_PIPES; i++) {
2975                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2976                 struct dc_stream_state *stream = pipe_ctx.stream;
2977
2978                 if (stream && stream->link == link) {
2979                         abm = pipe_ctx.stream_res.abm;
2980                         break;
2981                 }
2982         }
2983         return abm;
2984 }
2985
2986 int dc_link_get_backlight_level(const struct dc_link *link)
2987 {
2988         struct abm *abm = get_abm_from_stream_res(link);
2989         struct panel_cntl *panel_cntl = link->panel_cntl;
2990         struct dc  *dc = link->ctx->dc;
2991         struct dmcu *dmcu = dc->res_pool->dmcu;
2992         bool fw_set_brightness = true;
2993
2994         if (dmcu)
2995                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2996
2997         if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
2998                 return panel_cntl->funcs->get_current_backlight(panel_cntl);
2999         else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
3000                 return (int) abm->funcs->get_current_backlight(abm);
3001         else
3002                 return DC_ERROR_UNEXPECTED;
3003 }
3004
3005 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
3006 {
3007         struct abm *abm = get_abm_from_stream_res(link);
3008
3009         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
3010                 return DC_ERROR_UNEXPECTED;
3011
3012         return (int) abm->funcs->get_target_backlight(abm);
3013 }
3014
3015 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
3016 {
3017         int i;
3018         struct dc *dc = link->ctx->dc;
3019         struct pipe_ctx *pipe_ctx = NULL;
3020
3021         for (i = 0; i < MAX_PIPES; i++) {
3022                 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
3023                         if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
3024                                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
3025                                 break;
3026                         }
3027                 }
3028         }
3029
3030         return pipe_ctx;
3031 }
3032
3033 bool dc_link_set_backlight_level(const struct dc_link *link,
3034                 uint32_t backlight_pwm_u16_16,
3035                 uint32_t frame_ramp)
3036 {
3037         struct dc  *dc = link->ctx->dc;
3038
3039         DC_LOGGER_INIT(link->ctx->logger);
3040         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
3041                         backlight_pwm_u16_16, backlight_pwm_u16_16);
3042
3043         if (dc_is_embedded_signal(link->connector_signal)) {
3044                 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
3045
3046                 if (pipe_ctx) {
3047                         /* Disable brightness ramping when the display is blanked
3048                          * as it can hang the DMCU
3049                          */
3050                         if (pipe_ctx->plane_state == NULL)
3051                                 frame_ramp = 0;
3052                 } else {
3053                         return false;
3054                 }
3055
3056                 dc->hwss.set_backlight_level(
3057                                 pipe_ctx,
3058                                 backlight_pwm_u16_16,
3059                                 frame_ramp);
3060         }
3061         return true;
3062 }
3063
3064 bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
3065                 bool wait, bool force_static, const unsigned int *power_opts)
3066 {
3067         struct dc  *dc = link->ctx->dc;
3068         struct dmcu *dmcu = dc->res_pool->dmcu;
3069         struct dmub_psr *psr = dc->res_pool->psr;
3070         unsigned int panel_inst;
3071
3072         if (psr == NULL && force_static)
3073                 return false;
3074
3075         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3076                 return false;
3077
3078         /* Set power optimization flag */
3079         if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
3080                 link->psr_settings.psr_power_opt = *power_opts;
3081
3082                 if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
3083                         psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
3084         }
3085
3086         /* Enable or Disable PSR */
3087         if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
3088                 link->psr_settings.psr_allow_active = *allow_active;
3089
3090 #if defined(CONFIG_DRM_AMD_DC_DCN)
3091                 if (!link->psr_settings.psr_allow_active)
3092                         dc_z10_restore(dc);
3093 #endif
3094
3095                 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
3096                         if (force_static && psr->funcs->psr_force_static)
3097                                 psr->funcs->psr_force_static(psr, panel_inst);
3098                         psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
3099                 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
3100                         link->psr_settings.psr_feature_enabled)
3101                         dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
3102                 else
3103                         return false;
3104         }
3105
3106         return true;
3107 }
3108
3109 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
3110 {
3111         struct dc  *dc = link->ctx->dc;
3112         struct dmcu *dmcu = dc->res_pool->dmcu;
3113         struct dmub_psr *psr = dc->res_pool->psr;
3114         unsigned int panel_inst;
3115
3116         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3117                 return false;
3118
3119         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3120                 psr->funcs->psr_get_state(psr, state, panel_inst);
3121         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
3122                 dmcu->funcs->get_psr_state(dmcu, state);
3123
3124         return true;
3125 }
3126
3127 static inline enum physical_phy_id
3128 transmitter_to_phy_id(enum transmitter transmitter_value)
3129 {
3130         switch (transmitter_value) {
3131         case TRANSMITTER_UNIPHY_A:
3132                 return PHYLD_0;
3133         case TRANSMITTER_UNIPHY_B:
3134                 return PHYLD_1;
3135         case TRANSMITTER_UNIPHY_C:
3136                 return PHYLD_2;
3137         case TRANSMITTER_UNIPHY_D:
3138                 return PHYLD_3;
3139         case TRANSMITTER_UNIPHY_E:
3140                 return PHYLD_4;
3141         case TRANSMITTER_UNIPHY_F:
3142                 return PHYLD_5;
3143         case TRANSMITTER_NUTMEG_CRT:
3144                 return PHYLD_6;
3145         case TRANSMITTER_TRAVIS_CRT:
3146                 return PHYLD_7;
3147         case TRANSMITTER_TRAVIS_LCD:
3148                 return PHYLD_8;
3149         case TRANSMITTER_UNIPHY_G:
3150                 return PHYLD_9;
3151         case TRANSMITTER_COUNT:
3152                 return PHYLD_COUNT;
3153         case TRANSMITTER_UNKNOWN:
3154                 return PHYLD_UNKNOWN;
3155         default:
3156                 WARN_ONCE(1, "Unknown transmitter value %d\n",
3157                           transmitter_value);
3158                 return PHYLD_UNKNOWN;
3159         }
3160 }
3161
3162 bool dc_link_setup_psr(struct dc_link *link,
3163                 const struct dc_stream_state *stream, struct psr_config *psr_config,
3164                 struct psr_context *psr_context)
3165 {
3166         struct dc *dc;
3167         struct dmcu *dmcu;
3168         struct dmub_psr *psr;
3169         int i;
3170         unsigned int panel_inst;
3171         /* updateSinkPsrDpcdConfig*/
3172         union dpcd_psr_configuration psr_configuration;
3173
3174         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
3175
3176         if (!link)
3177                 return false;
3178
3179         dc = link->ctx->dc;
3180         dmcu = dc->res_pool->dmcu;
3181         psr = dc->res_pool->psr;
3182
3183         if (!dmcu && !psr)
3184                 return false;
3185
3186         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3187                 return false;
3188
3189
3190         memset(&psr_configuration, 0, sizeof(psr_configuration));
3191
3192         psr_configuration.bits.ENABLE                    = 1;
3193         psr_configuration.bits.CRC_VERIFICATION          = 1;
3194         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
3195                         psr_config->psr_frame_capture_indication_req;
3196
3197         /* Check for PSR v2*/
3198         if (psr_config->psr_version == 0x2) {
3199                 /* For PSR v2 selective update.
3200                  * Indicates whether sink should start capturing
3201                  * immediately following active scan line,
3202                  * or starting with the 2nd active scan line.
3203                  */
3204                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
3205                 /*For PSR v2, determines whether Sink should generate
3206                  * IRQ_HPD when CRC mismatch is detected.
3207                  */
3208                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
3209         }
3210
3211         dm_helpers_dp_write_dpcd(
3212                 link->ctx,
3213                 link,
3214                 368,
3215                 &psr_configuration.raw,
3216                 sizeof(psr_configuration.raw));
3217
3218         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
3219         psr_context->transmitterId = link->link_enc->transmitter;
3220         psr_context->engineId = link->link_enc->preferred_engine;
3221
3222         for (i = 0; i < MAX_PIPES; i++) {
3223                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
3224                                 == stream) {
3225                         /* dmcu -1 for all controller id values,
3226                          * therefore +1 here
3227                          */
3228                         psr_context->controllerId =
3229                                 dc->current_state->res_ctx.
3230                                 pipe_ctx[i].stream_res.tg->inst + 1;
3231                         break;
3232                 }
3233         }
3234
3235         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
3236         psr_context->phyType = PHY_TYPE_UNIPHY;
3237         /*PhyId is associated with the transmitter id*/
3238         psr_context->smuPhyId =
3239                 transmitter_to_phy_id(link->link_enc->transmitter);
3240
3241         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
3242         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
3243                                         timing.pix_clk_100hz * 100),
3244                                         stream->timing.v_total),
3245                                         stream->timing.h_total);
3246
3247         psr_context->psrSupportedDisplayConfig = true;
3248         psr_context->psrExitLinkTrainingRequired =
3249                 psr_config->psr_exit_link_training_required;
3250         psr_context->sdpTransmitLineNumDeadline =
3251                 psr_config->psr_sdp_transmit_line_num_deadline;
3252         psr_context->psrFrameCaptureIndicationReq =
3253                 psr_config->psr_frame_capture_indication_req;
3254
3255         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
3256
3257         psr_context->numberOfControllers =
3258                         link->dc->res_pool->timing_generator_count;
3259
3260         psr_context->rfb_update_auto_en = true;
3261
3262         /* 2 frames before enter PSR. */
3263         psr_context->timehyst_frames = 2;
3264         /* half a frame
3265          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
3266          */
3267         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
3268         psr_context->aux_repeats = 10;
3269
3270         psr_context->psr_level.u32all = 0;
3271
3272         /*skip power down the single pipe since it blocks the cstate*/
3273 #if defined(CONFIG_DRM_AMD_DC_DCN)
3274         if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
3275                 switch(link->ctx->asic_id.chip_family) {
3276                 case FAMILY_YELLOW_CARP:
3277                 case AMDGPU_FAMILY_GC_10_3_6:
3278                         if(!dc->debug.disable_z10)
3279                                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
3280                         break;
3281                 default:
3282                         psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3283                         break;
3284                 }
3285         }
3286 #else
3287         if (link->ctx->asic_id.chip_family >= FAMILY_RV)
3288                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3289 #endif
3290
3291         /* SMU will perform additional powerdown sequence.
3292          * For unsupported ASICs, set psr_level flag to skip PSR
3293          *  static screen notification to SMU.
3294          *  (Always set for DAL2, did not check ASIC)
3295          */
3296         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
3297         psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
3298
3299         /* Complete PSR entry before aborting to prevent intermittent
3300          * freezes on certain eDPs
3301          */
3302         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
3303
3304         /* Controls additional delay after remote frame capture before
3305          * continuing power down, default = 0
3306          */
3307         psr_context->frame_delay = 0;
3308
3309         if (psr)
3310                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
3311                         link, psr_context, panel_inst);
3312         else
3313                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
3314
3315         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
3316          * should not happen since firmware should be running at this point
3317          */
3318         if (link->psr_settings.psr_feature_enabled == 0)
3319                 ASSERT(0);
3320
3321         return true;
3322
3323 }
3324
3325 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
3326 {
3327         struct dc  *dc = link->ctx->dc;
3328         struct dmub_psr *psr = dc->res_pool->psr;
3329         unsigned int panel_inst;
3330
3331         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3332                 return;
3333
3334         /* PSR residency measurements only supported on DMCUB */
3335         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3336                 psr->funcs->psr_get_residency(psr, residency, panel_inst);
3337         else
3338                 *residency = 0;
3339 }
3340
3341 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
3342 {
3343         return &link->link_status;
3344 }
3345
3346 void core_link_resume(struct dc_link *link)
3347 {
3348         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
3349                 program_hpd_filter(link);
3350 }
3351
3352 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
3353 {
3354         struct fixed31_32 mbytes_per_sec;
3355         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
3356                         &stream->link->cur_link_settings);
3357         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
3358
3359         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
3360
3361         return dc_fixpt_div_int(mbytes_per_sec, 54);
3362 }
3363
3364 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
3365 {
3366         struct fixed31_32 peak_kbps;
3367         uint32_t numerator = 0;
3368         uint32_t denominator = 1;
3369
3370         /*
3371          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
3372          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
3373          * common multiplier to render an integer PBN for all link rate/lane
3374          * counts combinations
3375          * calculate
3376          * peak_kbps *= (1006/1000)
3377          * peak_kbps *= (64/54)
3378          * peak_kbps *= 8    convert to bytes
3379          */
3380
3381         numerator = 64 * PEAK_FACTOR_X1000;
3382         denominator = 54 * 8 * 1000 * 1000;
3383         kbps *= numerator;
3384         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
3385
3386         return peak_kbps;
3387 }
3388
3389 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
3390 {
3391         uint64_t kbps;
3392
3393         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
3394         return get_pbn_from_bw_in_kbps(kbps);
3395 }
3396
3397 static void update_mst_stream_alloc_table(
3398         struct dc_link *link,
3399         struct stream_encoder *stream_enc,
3400         struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc?
3401         const struct dp_mst_stream_allocation_table *proposed_table)
3402 {
3403         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
3404         struct link_mst_stream_allocation *dc_alloc;
3405
3406         int i;
3407         int j;
3408
3409         /* if DRM proposed_table has more than one new payload */
3410         ASSERT(proposed_table->stream_count -
3411                         link->mst_stream_alloc_table.stream_count < 2);
3412
3413         /* copy proposed_table to link, add stream encoder */
3414         for (i = 0; i < proposed_table->stream_count; i++) {
3415
3416                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
3417                         dc_alloc =
3418                         &link->mst_stream_alloc_table.stream_allocations[j];
3419
3420                         if (dc_alloc->vcp_id ==
3421                                 proposed_table->stream_allocations[i].vcp_id) {
3422
3423                                 work_table[i] = *dc_alloc;
3424                                 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
3425                                 break; /* exit j loop */
3426                         }
3427                 }
3428
3429                 /* new vcp_id */
3430                 if (j == link->mst_stream_alloc_table.stream_count) {
3431                         work_table[i].vcp_id =
3432                                 proposed_table->stream_allocations[i].vcp_id;
3433                         work_table[i].slot_count =
3434                                 proposed_table->stream_allocations[i].slot_count;
3435                         work_table[i].stream_enc = stream_enc;
3436                         work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc;
3437                 }
3438         }
3439
3440         /* update link->mst_stream_alloc_table with work_table */
3441         link->mst_stream_alloc_table.stream_count =
3442                         proposed_table->stream_count;
3443         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
3444                 link->mst_stream_alloc_table.stream_allocations[i] =
3445                                 work_table[i];
3446 }
3447
3448 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
3449 {
3450         const uint32_t VCP_Y_PRECISION = 1000;
3451         uint64_t vcp_x, vcp_y;
3452
3453         // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
3454         avg_time_slots_per_mtp = dc_fixpt_add(
3455                         avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));
3456
3457         vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
3458         vcp_y = dc_fixpt_floor(
3459                         dc_fixpt_mul_int(
3460                                 dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
3461                                 VCP_Y_PRECISION));
3462
3463         if (link->type == dc_connection_mst_branch)
3464                 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
3465                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3466         else
3467                 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
3468                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3469 }
3470
3471 /*
3472  * Payload allocation/deallocation for SST introduced in DP2.0
3473  */
3474 static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
3475                                                  bool allocate)
3476 {
3477         struct dc_stream_state *stream = pipe_ctx->stream;
3478         struct dc_link *link = stream->link;
3479         struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
3480         struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3481         struct link_mst_stream_allocation_table proposed_table = {0};
3482         struct fixed31_32 avg_time_slots_per_mtp;
3483         const struct dc_link_settings empty_link_settings = {0};
3484         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3485         DC_LOGGER_INIT(link->ctx->logger);
3486
3487         /* slot X.Y for SST payload deallocate */
3488         if (!allocate) {
3489                 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3490
3491                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3492
3493                 if (link_hwss->ext.set_throttled_vcp_size)
3494                         link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3495                                         avg_time_slots_per_mtp);
3496                 if (link_hwss->ext.set_hblank_min_symbol_width)
3497                         link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3498                                         &empty_link_settings,
3499                                         avg_time_slots_per_mtp);
3500         }
3501
3502         /* calculate VC payload and update branch with new payload allocation table*/
3503         if (!dpcd_write_128b_132b_sst_payload_allocation_table(
3504                         stream,
3505                         link,
3506                         &proposed_table,
3507                         allocate)) {
3508                 DC_LOG_ERROR("SST Update Payload: Failed to update "
3509                                                 "allocation table for "
3510                                                 "pipe idx: %d\n",
3511                                                 pipe_ctx->pipe_idx);
3512         }
3513
3514         proposed_table.stream_allocations[0].hpo_dp_stream_enc = hpo_dp_stream_encoder;
3515
3516         ASSERT(proposed_table.stream_count == 1);
3517
3518         //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id
3519         DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p      "
3520                 "vcp_id: %d      "
3521                 "slot_count: %d\n",
3522                 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc,
3523                 proposed_table.stream_allocations[0].vcp_id,
3524                 proposed_table.stream_allocations[0].slot_count);
3525
3526         /* program DP source TX for payload */
3527         hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3528                         hpo_dp_link_encoder,
3529                         &proposed_table);
3530
3531         /* poll for ACT handled */
3532         if (!dpcd_poll_for_allocation_change_trigger(link)) {
3533                 // Failures will result in blackscreen and errors logged
3534                 BREAK_TO_DEBUGGER();
3535         }
3536
3537         /* slot X.Y for SST payload allocate */
3538         if (allocate) {
3539                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
3540
3541                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3542
3543                 if (link_hwss->ext.set_throttled_vcp_size)
3544                         link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3545                                         avg_time_slots_per_mtp);
3546                 if (link_hwss->ext.set_hblank_min_symbol_width)
3547                         link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3548                                         &link->cur_link_settings,
3549                                         avg_time_slots_per_mtp);
3550         }
3551
3552         /* Always return DC_OK.
3553          * If part of sequence fails, log failure(s) and show blackscreen
3554          */
3555         return DC_OK;
3556 }
3557
3558 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
3559  * because stream_encoder is not exposed to dm
3560  */
3561 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3562 {
3563         struct dc_stream_state *stream = pipe_ctx->stream;
3564         struct dc_link *link = stream->link;
3565         struct link_encoder *link_encoder = NULL;
3566         struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
3567         struct dp_mst_stream_allocation_table proposed_table = {0};
3568         struct fixed31_32 avg_time_slots_per_mtp;
3569         struct fixed31_32 pbn;
3570         struct fixed31_32 pbn_per_slot;
3571         int i;
3572         enum act_return_status ret;
3573         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3574         DC_LOGGER_INIT(link->ctx->logger);
3575
3576         link_encoder = link_enc_cfg_get_link_enc(link);
3577         ASSERT(link_encoder);
3578
3579         /* enable_link_dp_mst already check link->enabled_stream_count
3580          * and stream is in link->stream[]. This is called during set mode,
3581          * stream_enc is available.
3582          */
3583
3584         /* get calculate VC payload for stream: stream_alloc */
3585         if (dm_helpers_dp_mst_write_payload_allocation_table(
3586                 stream->ctx,
3587                 stream,
3588                 &proposed_table,
3589                 true))
3590                 update_mst_stream_alloc_table(
3591                                         link,
3592                                         pipe_ctx->stream_res.stream_enc,
3593                                         pipe_ctx->stream_res.hpo_dp_stream_enc,
3594                                         &proposed_table);
3595         else
3596                 DC_LOG_WARNING("Failed to update"
3597                                 "MST allocation table for"
3598                                 "pipe idx:%d\n",
3599                                 pipe_ctx->pipe_idx);
3600
3601         DC_LOG_MST("%s  "
3602                         "stream_count: %d: \n ",
3603                         __func__,
3604                         link->mst_stream_alloc_table.stream_count);
3605
3606         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3607                 DC_LOG_MST("stream_enc[%d]: %p      "
3608                 "stream[%d].hpo_dp_stream_enc: %p      "
3609                 "stream[%d].vcp_id: %d      "
3610                 "stream[%d].slot_count: %d\n",
3611                 i,
3612                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3613                 i,
3614                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3615                 i,
3616                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3617                 i,
3618                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3619         }
3620
3621         ASSERT(proposed_table.stream_count > 0);
3622
3623         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3624                 static enum dc_status status;
3625                 uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;
3626
3627                 for (i = 0; i < link->mst_stream_alloc_table.stream_count; i++)
3628                         mst_alloc_slots += link->mst_stream_alloc_table.stream_allocations[i].slot_count;
3629
3630                 status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,
3631                         mst_alloc_slots, &prev_mst_slots_in_use);
3632                 ASSERT(status == DC_OK);
3633                 DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n",
3634                                 status, mst_alloc_slots, prev_mst_slots_in_use);
3635         }
3636
3637         /* program DP source TX for payload */
3638         switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3639         case DP_8b_10b_ENCODING:
3640                 link_encoder->funcs->update_mst_stream_allocation_table(
3641                         link_encoder,
3642                         &link->mst_stream_alloc_table);
3643                 break;
3644         case DP_128b_132b_ENCODING:
3645                 hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3646                                 hpo_dp_link_encoder,
3647                                 &link->mst_stream_alloc_table);
3648                 break;
3649         case DP_UNKNOWN_ENCODING:
3650                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3651                 return DC_ERROR_UNEXPECTED;
3652         }
3653
3654         /* send down message */
3655         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3656                         stream->ctx,
3657                         stream);
3658
3659         if (ret != ACT_LINK_LOST) {
3660                 dm_helpers_dp_mst_send_payload_allocation(
3661                                 stream->ctx,
3662                                 stream,
3663                                 true);
3664         }
3665
3666         /* slot X.Y for only current stream */
3667         pbn_per_slot = get_pbn_per_slot(stream);
3668         if (pbn_per_slot.value == 0) {
3669                 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3670                 return DC_UNSUPPORTED_VALUE;
3671         }
3672         pbn = get_pbn_from_timing(pipe_ctx);
3673         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3674
3675         dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3676
3677         if (link_hwss->ext.set_throttled_vcp_size)
3678                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3679         if (link_hwss->ext.set_hblank_min_symbol_width)
3680                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3681                                 &link->cur_link_settings,
3682                                 avg_time_slots_per_mtp);
3683
3684         return DC_OK;
3685
3686 }
3687
3688 enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3689 {
3690         struct dc_stream_state *stream = pipe_ctx->stream;
3691         struct dc_link *link = stream->link;
3692         struct fixed31_32 avg_time_slots_per_mtp;
3693         struct fixed31_32 pbn;
3694         struct fixed31_32 pbn_per_slot;
3695         struct link_encoder *link_encoder = link->link_enc;
3696         struct dp_mst_stream_allocation_table proposed_table = {0};
3697         uint8_t i;
3698         enum act_return_status ret;
3699         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3700         DC_LOGGER_INIT(link->ctx->logger);
3701
3702         /* decrease throttled vcp size */
3703         pbn_per_slot = get_pbn_per_slot(stream);
3704         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3705         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3706
3707         if (link_hwss->ext.set_throttled_vcp_size)
3708                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3709         if (link_hwss->ext.set_hblank_min_symbol_width)
3710                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3711                                 &link->cur_link_settings,
3712                                 avg_time_slots_per_mtp);
3713
3714         /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3715         dm_helpers_dp_mst_send_payload_allocation(
3716                         stream->ctx,
3717                         stream,
3718                         true);
3719
3720         /* notify immediate branch device table update */
3721         if (dm_helpers_dp_mst_write_payload_allocation_table(
3722                         stream->ctx,
3723                         stream,
3724                         &proposed_table,
3725                         true)) {
3726                 /* update mst stream allocation table software state */
3727                 update_mst_stream_alloc_table(
3728                                 link,
3729                                 pipe_ctx->stream_res.stream_enc,
3730                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3731                                 &proposed_table);
3732         } else {
3733                 DC_LOG_WARNING("Failed to update"
3734                                 "MST allocation table for"
3735                                 "pipe idx:%d\n",
3736                                 pipe_ctx->pipe_idx);
3737         }
3738
3739         DC_LOG_MST("%s  "
3740                         "stream_count: %d: \n ",
3741                         __func__,
3742                         link->mst_stream_alloc_table.stream_count);
3743
3744         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3745                 DC_LOG_MST("stream_enc[%d]: %p      "
3746                                 "stream[%d].vcp_id: %d      "
3747                                 "stream[%d].slot_count: %d\n",
3748                                 i,
3749                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3750                                 i,
3751                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3752                                 i,
3753                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3754         }
3755
3756         ASSERT(proposed_table.stream_count > 0);
3757
3758         /* update mst stream allocation table hardware state */
3759         link_encoder->funcs->update_mst_stream_allocation_table(
3760                         link_encoder,
3761                         &link->mst_stream_alloc_table);
3762
3763         /* poll for immediate branch device ACT handled */
3764         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3765                         stream->ctx,
3766                         stream);
3767
3768         return DC_OK;
3769 }
3770
3771 enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3772 {
3773         struct dc_stream_state *stream = pipe_ctx->stream;
3774         struct dc_link *link = stream->link;
3775         struct fixed31_32 avg_time_slots_per_mtp;
3776         struct fixed31_32 pbn;
3777         struct fixed31_32 pbn_per_slot;
3778         struct link_encoder *link_encoder = link->link_enc;
3779         struct dp_mst_stream_allocation_table proposed_table = {0};
3780         uint8_t i;
3781         enum act_return_status ret;
3782         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3783         DC_LOGGER_INIT(link->ctx->logger);
3784
3785         /* notify immediate branch device table update */
3786         if (dm_helpers_dp_mst_write_payload_allocation_table(
3787                                 stream->ctx,
3788                                 stream,
3789                                 &proposed_table,
3790                                 true)) {
3791                 /* update mst stream allocation table software state */
3792                 update_mst_stream_alloc_table(
3793                                 link,
3794                                 pipe_ctx->stream_res.stream_enc,
3795                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3796                                 &proposed_table);
3797         }
3798
3799         DC_LOG_MST("%s  "
3800                         "stream_count: %d: \n ",
3801                         __func__,
3802                         link->mst_stream_alloc_table.stream_count);
3803
3804         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3805                 DC_LOG_MST("stream_enc[%d]: %p      "
3806                                 "stream[%d].vcp_id: %d      "
3807                                 "stream[%d].slot_count: %d\n",
3808                                 i,
3809                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3810                                 i,
3811                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3812                                 i,
3813                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3814         }
3815
3816         ASSERT(proposed_table.stream_count > 0);
3817
3818         /* update mst stream allocation table hardware state */
3819         link_encoder->funcs->update_mst_stream_allocation_table(
3820                         link_encoder,
3821                         &link->mst_stream_alloc_table);
3822
3823         /* poll for immediate branch device ACT handled */
3824         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3825                         stream->ctx,
3826                         stream);
3827
3828         if (ret != ACT_LINK_LOST) {
3829                 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3830                 dm_helpers_dp_mst_send_payload_allocation(
3831                                 stream->ctx,
3832                                 stream,
3833                                 true);
3834         }
3835
3836         /* increase throttled vcp size */
3837         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3838         pbn_per_slot = get_pbn_per_slot(stream);
3839         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3840
3841         if (link_hwss->ext.set_throttled_vcp_size)
3842                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3843         if (link_hwss->ext.set_hblank_min_symbol_width)
3844                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3845                                 &link->cur_link_settings,
3846                                 avg_time_slots_per_mtp);
3847
3848         return DC_OK;
3849 }
3850
3851 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3852 {
3853         struct dc_stream_state *stream = pipe_ctx->stream;
3854         struct dc_link *link = stream->link;
3855         struct link_encoder *link_encoder = NULL;
3856         struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
3857         struct dp_mst_stream_allocation_table proposed_table = {0};
3858         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3859         int i;
3860         bool mst_mode = (link->type == dc_connection_mst_branch);
3861         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3862         const struct dc_link_settings empty_link_settings = {0};
3863         DC_LOGGER_INIT(link->ctx->logger);
3864
3865         link_encoder = link_enc_cfg_get_link_enc(link);
3866         ASSERT(link_encoder);
3867
3868         /* deallocate_mst_payload is called before disable link. When mode or
3869          * disable/enable monitor, new stream is created which is not in link
3870          * stream[] yet. For this, payload is not allocated yet, so de-alloc
3871          * should not done. For new mode set, map_resources will get engine
3872          * for new stream, so stream_enc->id should be validated until here.
3873          */
3874
3875         /* slot X.Y */
3876         if (link_hwss->ext.set_throttled_vcp_size)
3877                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3878         if (link_hwss->ext.set_hblank_min_symbol_width)
3879                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3880                                 &empty_link_settings,
3881                                 avg_time_slots_per_mtp);
3882
3883         /* TODO: which component is responsible for remove payload table? */
3884         if (mst_mode) {
3885                 if (dm_helpers_dp_mst_write_payload_allocation_table(
3886                                 stream->ctx,
3887                                 stream,
3888                                 &proposed_table,
3889                                 false)) {
3890
3891                         update_mst_stream_alloc_table(
3892                                                 link,
3893                                                 pipe_ctx->stream_res.stream_enc,
3894                                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3895                                                 &proposed_table);
3896                 }
3897                 else {
3898                                 DC_LOG_WARNING("Failed to update"
3899                                                 "MST allocation table for"
3900                                                 "pipe idx:%d\n",
3901                                                 pipe_ctx->pipe_idx);
3902                 }
3903         }
3904
3905         DC_LOG_MST("%s"
3906                         "stream_count: %d: ",
3907                         __func__,
3908                         link->mst_stream_alloc_table.stream_count);
3909
3910         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3911                 DC_LOG_MST("stream_enc[%d]: %p      "
3912                 "stream[%d].hpo_dp_stream_enc: %p      "
3913                 "stream[%d].vcp_id: %d      "
3914                 "stream[%d].slot_count: %d\n",
3915                 i,
3916                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3917                 i,
3918                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3919                 i,
3920                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3921                 i,
3922                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3923         }
3924
3925         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3926                 enum dc_status status;
3927                 uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;
3928
3929                 for (i = 0; i < link->mst_stream_alloc_table.stream_count; i++)
3930                         mst_alloc_slots += link->mst_stream_alloc_table.stream_allocations[i].slot_count;
3931
3932                 status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,
3933                         mst_alloc_slots, &prev_mst_slots_in_use);
3934                 ASSERT(status != DC_NOT_SUPPORTED);
3935                 DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n",
3936                                 status, mst_alloc_slots, prev_mst_slots_in_use);
3937         }
3938
3939         switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3940         case DP_8b_10b_ENCODING:
3941                 link_encoder->funcs->update_mst_stream_allocation_table(
3942                         link_encoder,
3943                         &link->mst_stream_alloc_table);
3944                 break;
3945         case DP_128b_132b_ENCODING:
3946                 hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3947                                 hpo_dp_link_encoder,
3948                                 &link->mst_stream_alloc_table);
3949                 break;
3950         case DP_UNKNOWN_ENCODING:
3951                 DC_LOG_DEBUG("Unknown encoding format\n");
3952                 return DC_ERROR_UNEXPECTED;
3953         }
3954
3955         if (mst_mode) {
3956                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3957                         stream->ctx,
3958                         stream);
3959
3960                 dm_helpers_dp_mst_send_payload_allocation(
3961                         stream->ctx,
3962                         stream,
3963                         false);
3964         }
3965
3966         return DC_OK;
3967 }
3968
3969
3970 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3971 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3972 {
3973         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3974         struct link_encoder *link_enc = NULL;
3975         struct cp_psp_stream_config config = {0};
3976         enum dp_panel_mode panel_mode =
3977                         dp_get_panel_mode(pipe_ctx->stream->link);
3978
3979         if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL)
3980                 return;
3981
3982         link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
3983         ASSERT(link_enc);
3984         if (link_enc == NULL)
3985                 return;
3986
3987         /* otg instance */
3988         config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3989
3990         /* dig front end */
3991         config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3992
3993         /* stream encoder index */
3994         config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
3995         if (is_dp_128b_132b_signal(pipe_ctx))
3996                 config.stream_enc_idx =
3997                                 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
3998
3999         /* dig back end */
4000         config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
4001
4002         /* link encoder index */
4003         config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4004         if (is_dp_128b_132b_signal(pipe_ctx))
4005                 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;
4006
4007         /* dio output index */
4008         config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4009
4010         /* phy index */
4011         config.phy_idx = resource_transmitter_to_phy_idx(
4012                         pipe_ctx->stream->link->dc, link_enc->transmitter);
4013         if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
4014                 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */
4015                 config.phy_idx = 0;
4016
4017         /* stream properties */
4018         config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0;
4019         config.mst_enabled = (pipe_ctx->stream->signal ==
4020                         SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0;
4021         config.dp2_enabled = is_dp_128b_132b_signal(pipe_ctx) ? 1 : 0;
4022         config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ?
4023                         1 : 0;
4024         config.dpms_off = dpms_off;
4025
4026         /* dm stream context */
4027         config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
4028
4029         cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
4030 }
4031 #endif
4032
4033 static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx)
4034 {
4035         struct dc *dc = pipe_ctx->stream->ctx->dc;
4036         struct dc_stream_state *stream = pipe_ctx->stream;
4037         struct link_mst_stream_allocation_table proposed_table = {0};
4038         struct fixed31_32 avg_time_slots_per_mtp;
4039         uint8_t req_slot_count = 0;
4040         uint8_t vc_id = 1; /// VC ID always 1 for SST
4041         struct dc_link_settings link_settings = {0};
4042         const struct link_hwss *link_hwss = get_link_hwss(stream->link, &pipe_ctx->link_res);
4043         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4044
4045         decide_link_settings(stream, &link_settings);
4046         stream->link->cur_link_settings = link_settings;
4047
4048         if (link_hwss->ext.enable_dp_link_output)
4049                 link_hwss->ext.enable_dp_link_output(stream->link, &pipe_ctx->link_res,
4050                                 stream->signal, pipe_ctx->clock_source->id,
4051                                 &link_settings);
4052
4053 #ifdef DIAGS_BUILD
4054         /* Workaround for FPGA HPO capture DP link data:
4055          * HPO capture will set link to active mode
4056          * This workaround is required to get a capture from start of frame
4057          */
4058         if (!dc->debug.fpga_hpo_capture_en) {
4059                 struct encoder_set_dp_phy_pattern_param params = {0};
4060                 params.dp_phy_pattern = DP_TEST_PATTERN_VIDEO_MODE;
4061
4062                 /* Set link active */
4063                 stream->link->hpo_dp_link_enc->funcs->set_link_test_pattern(
4064                                 stream->link->hpo_dp_link_enc,
4065                                 &params);
4066         }
4067 #endif
4068
4069         /* Enable DP_STREAM_ENC */
4070         dc->hwss.enable_stream(pipe_ctx);
4071
4072         /* Set DPS PPS SDP (AKA "info frames") */
4073         if (pipe_ctx->stream->timing.flags.DSC) {
4074                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4075         }
4076
4077         /* Allocate Payload */
4078         if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) {
4079                 // MST case
4080                 uint8_t i;
4081
4082                 proposed_table.stream_count = state->stream_count;
4083                 for (i = 0; i < state->stream_count; i++) {
4084                         avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link);
4085                         req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4086                         proposed_table.stream_allocations[i].slot_count = req_slot_count;
4087                         proposed_table.stream_allocations[i].vcp_id = i+1;
4088                         /* NOTE: This makes assumption that pipe_ctx index is same as stream index */
4089                         proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc;
4090                 }
4091         } else {
4092                 // SST case
4093                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, stream->link);
4094                 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4095                 proposed_table.stream_count = 1; /// Always 1 stream for SST
4096                 proposed_table.stream_allocations[0].slot_count = req_slot_count;
4097                 proposed_table.stream_allocations[0].vcp_id = vc_id;
4098                 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
4099         }
4100
4101         pipe_ctx->link_res.hpo_dp_link_enc->funcs->update_stream_allocation_table(
4102                         pipe_ctx->link_res.hpo_dp_link_enc,
4103                         &proposed_table);
4104
4105         if (link_hwss->ext.set_throttled_vcp_size)
4106                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
4107
4108         dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings);
4109 }
4110
4111 void core_link_enable_stream(
4112                 struct dc_state *state,
4113                 struct pipe_ctx *pipe_ctx)
4114 {
4115         struct dc *dc = pipe_ctx->stream->ctx->dc;
4116         struct dc_stream_state *stream = pipe_ctx->stream;
4117         struct dc_link *link = stream->sink->link;
4118         enum dc_status status;
4119         struct link_encoder *link_enc;
4120         enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
4121         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4122
4123         if (is_dp_128b_132b_signal(pipe_ctx))
4124                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4125
4126         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4127
4128         if (pipe_ctx->stream->sink) {
4129                 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4130                         pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4131                         DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4132                         pipe_ctx->stream->sink->edid_caps.display_name,
4133                         pipe_ctx->stream->signal);
4134                 }
4135         }
4136
4137         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4138                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4139                 return;
4140
4141         link_enc = link_enc_cfg_get_link_enc(link);
4142         ASSERT(link_enc);
4143
4144         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)
4145                         && !is_dp_128b_132b_signal(pipe_ctx)) {
4146                 if (link_enc)
4147                         link_enc->funcs->setup(
4148                                 link_enc,
4149                                 pipe_ctx->stream->signal);
4150                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
4151                         pipe_ctx->stream_res.stream_enc,
4152                         pipe_ctx->stream_res.tg->inst,
4153                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
4154         }
4155
4156         if (is_dp_128b_132b_signal(pipe_ctx)) {
4157                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->set_stream_attribute(
4158                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
4159                                 &stream->timing,
4160                                 stream->output_color_space,
4161                                 stream->use_vsc_sdp_for_colorimetry,
4162                                 stream->timing.flags.DSC,
4163                                 false);
4164                 otg_out_dest = OUT_MUX_HPO_DP;
4165         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
4166                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
4167                                 pipe_ctx->stream_res.stream_enc,
4168                                 &stream->timing,
4169                                 stream->output_color_space,
4170                                 stream->use_vsc_sdp_for_colorimetry,
4171                                 stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4172         }
4173
4174         if (dc_is_dp_signal(pipe_ctx->stream->signal))
4175                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR);
4176
4177         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
4178                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
4179                         pipe_ctx->stream_res.stream_enc,
4180                         &stream->timing,
4181                         stream->phy_pix_clk,
4182                         pipe_ctx->stream_res.audio != NULL);
4183
4184         pipe_ctx->stream->link->link_state_valid = true;
4185
4186         if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4187                 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
4188
4189         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
4190                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
4191                         pipe_ctx->stream_res.stream_enc,
4192                         &stream->timing,
4193                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
4194                         true : false);
4195
4196         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
4197                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
4198                         pipe_ctx->stream_res.stream_enc,
4199                         &stream->timing);
4200
4201         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
4202                 bool apply_edp_fast_boot_optimization =
4203                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
4204
4205                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
4206
4207                 // Enable VPG before building infoframe
4208                 if (vpg && vpg->funcs->vpg_poweron)
4209                         vpg->funcs->vpg_poweron(vpg);
4210
4211                 resource_build_info_frame(pipe_ctx);
4212                 dc->hwss.update_info_frame(pipe_ctx);
4213
4214                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4215                         dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
4216
4217                 /* Do not touch link on seamless boot optimization. */
4218                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
4219                         pipe_ctx->stream->dpms_off = false;
4220
4221                         /* Still enable stream features & audio on seamless boot for DP external displays */
4222                         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
4223                                 enable_stream_features(pipe_ctx);
4224                                 if (pipe_ctx->stream_res.audio != NULL) {
4225                                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
4226                                         dc->hwss.enable_audio_stream(pipe_ctx);
4227                                 }
4228                         }
4229
4230 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4231                         update_psp_stream_config(pipe_ctx, false);
4232 #endif
4233                         return;
4234                 }
4235
4236                 /* eDP lit up by bios already, no need to enable again. */
4237                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
4238                                         apply_edp_fast_boot_optimization &&
4239                                         !pipe_ctx->stream->timing.flags.DSC &&
4240                                         !pipe_ctx->next_odm_pipe) {
4241                         pipe_ctx->stream->dpms_off = false;
4242 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4243                         update_psp_stream_config(pipe_ctx, false);
4244 #endif
4245                         return;
4246                 }
4247
4248                 if (pipe_ctx->stream->dpms_off)
4249                         return;
4250
4251                 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
4252                  * link training). This is to make sure the bandwidth sent to DIG BE won't be
4253                  * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
4254                  * will be automatically set at a later time when the video is enabled
4255                  * (DP_VID_STREAM_EN = 1).
4256                  */
4257                 if (pipe_ctx->stream->timing.flags.DSC) {
4258                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4259                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4260                                 dp_set_dsc_enable(pipe_ctx, true);
4261                 }
4262
4263                 status = enable_link(state, pipe_ctx);
4264
4265                 if (status != DC_OK) {
4266                         DC_LOG_WARNING("enabling link %u failed: %d\n",
4267                         pipe_ctx->stream->link->link_index,
4268                         status);
4269
4270                         /* Abort stream enable *unless* the failure was due to
4271                          * DP link training - some DP monitors will recover and
4272                          * show the stream anyway. But MST displays can't proceed
4273                          * without link training.
4274                          */
4275                         if (status != DC_FAIL_DP_LINK_TRAINING ||
4276                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
4277                                 if (false == stream->link->link_status.link_active)
4278                                         disable_link(stream->link, &pipe_ctx->link_res,
4279                                                         pipe_ctx->stream->signal);
4280                                 BREAK_TO_DEBUGGER();
4281                                 return;
4282                         }
4283                 }
4284
4285                 /* turn off otg test pattern if enable */
4286                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4287                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4288                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4289                                         COLOR_DEPTH_UNDEFINED);
4290
4291                 /* This second call is needed to reconfigure the DIG
4292                  * as a workaround for the incorrect value being applied
4293                  * from transmitter control.
4294                  */
4295                 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
4296                                 is_dp_128b_132b_signal(pipe_ctx)))
4297                         if (link_enc)
4298                                 link_enc->funcs->setup(
4299                                         link_enc,
4300                                         pipe_ctx->stream->signal);
4301
4302                 dc->hwss.enable_stream(pipe_ctx);
4303
4304                 /* Set DPS PPS SDP (AKA "info frames") */
4305                 if (pipe_ctx->stream->timing.flags.DSC) {
4306                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4307                                         dc_is_virtual_signal(pipe_ctx->stream->signal)) {
4308                                 dp_set_dsc_on_rx(pipe_ctx, true);
4309                                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4310                         }
4311                 }
4312
4313                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4314                         dc_link_allocate_mst_payload(pipe_ctx);
4315                 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4316                                 is_dp_128b_132b_signal(pipe_ctx))
4317                         dc_link_update_sst_payload(pipe_ctx, true);
4318
4319                 dc->hwss.unblank_stream(pipe_ctx,
4320                         &pipe_ctx->stream->link->cur_link_settings);
4321
4322                 if (stream->sink_patches.delay_ignore_msa > 0)
4323                         msleep(stream->sink_patches.delay_ignore_msa);
4324
4325                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4326                         enable_stream_features(pipe_ctx);
4327 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4328                 update_psp_stream_config(pipe_ctx, false);
4329 #endif
4330
4331                 dc->hwss.enable_audio_stream(pipe_ctx);
4332
4333         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
4334                 if (is_dp_128b_132b_signal(pipe_ctx)) {
4335                         fpga_dp_hpo_enable_link_and_stream(state, pipe_ctx);
4336                 }
4337                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4338                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
4339                         dp_set_dsc_enable(pipe_ctx, true);
4340
4341         }
4342
4343         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
4344                 core_link_set_avmute(pipe_ctx, false);
4345         }
4346 }
4347
4348 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
4349 {
4350         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4351         struct dc_stream_state *stream = pipe_ctx->stream;
4352         struct dc_link *link = stream->sink->link;
4353         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4354
4355         if (is_dp_128b_132b_signal(pipe_ctx))
4356                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4357
4358         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4359
4360         if (pipe_ctx->stream->sink) {
4361                 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4362                         pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4363                         DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4364                         pipe_ctx->stream->sink->edid_caps.display_name,
4365                         pipe_ctx->stream->signal);
4366                 }
4367         }
4368
4369         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4370                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4371                 return;
4372
4373         if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
4374                 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
4375                         core_link_set_avmute(pipe_ctx, true);
4376         }
4377
4378         dc->hwss.disable_audio_stream(pipe_ctx);
4379
4380 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4381         update_psp_stream_config(pipe_ctx, true);
4382 #endif
4383         dc->hwss.blank_stream(pipe_ctx);
4384
4385         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4386                 deallocate_mst_payload(pipe_ctx);
4387         else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4388                         is_dp_128b_132b_signal(pipe_ctx))
4389                 dc_link_update_sst_payload(pipe_ctx, false);
4390
4391         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4392                 struct ext_hdmi_settings settings = {0};
4393                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
4394
4395                 unsigned short masked_chip_caps = link->chip_caps &
4396                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
4397                 //Need to inform that sink is going to use legacy HDMI mode.
4398                 dal_ddc_service_write_scdc_data(
4399                         link->ddc,
4400                         165000,//vbios only handles 165Mhz.
4401                         false);
4402                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
4403                         /* DP159, Retimer settings */
4404                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
4405                                 write_i2c_retimer_setting(pipe_ctx,
4406                                                 false, false, &settings);
4407                         else
4408                                 write_i2c_default_retimer_setting(pipe_ctx,
4409                                                 false, false);
4410                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
4411                         /* PI3EQX1204, Redriver settings */
4412                         write_i2c_redriver_setting(pipe_ctx, false);
4413                 }
4414         }
4415
4416         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4417                         !is_dp_128b_132b_signal(pipe_ctx)) {
4418
4419                 /* In DP1.x SST mode, our encoder will go to TPS1
4420                  * when link is on but stream is off.
4421                  * Disabling link before stream will avoid exposing TPS1 pattern
4422                  * during the disable sequence as it will confuse some receivers
4423                  * state machine.
4424                  * In DP2 or MST mode, our encoder will stay video active
4425                  */
4426                 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4427                 dc->hwss.disable_stream(pipe_ctx);
4428         } else {
4429                 dc->hwss.disable_stream(pipe_ctx);
4430                 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4431         }
4432
4433         if (pipe_ctx->stream->timing.flags.DSC) {
4434                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4435                         dp_set_dsc_enable(pipe_ctx, false);
4436         }
4437         if (is_dp_128b_132b_signal(pipe_ctx)) {
4438                 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4439                         pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
4440         }
4441
4442         if (vpg && vpg->funcs->vpg_powerdown)
4443                 vpg->funcs->vpg_powerdown(vpg);
4444 }
4445
4446 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
4447 {
4448         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4449
4450         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
4451                 return;
4452
4453         dc->hwss.set_avmute(pipe_ctx, enable);
4454 }
4455
4456 /**
4457  *  dc_link_enable_hpd_filter:
4458  *     If enable is true, programs HPD filter on associated HPD line using
4459  *     delay_on_disconnect/delay_on_connect values dependent on
4460  *     link->connector_signal
4461  *
4462  *     If enable is false, programs HPD filter on associated HPD line with no
4463  *     delays on connect or disconnect
4464  *
4465  *  @link:   pointer to the dc link
4466  *  @enable: boolean specifying whether to enable hbd
4467  */
4468 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
4469 {
4470         struct gpio *hpd;
4471
4472         if (enable) {
4473                 link->is_hpd_filter_disabled = false;
4474                 program_hpd_filter(link);
4475         } else {
4476                 link->is_hpd_filter_disabled = true;
4477                 /* Obtain HPD handle */
4478                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4479
4480                 if (!hpd)
4481                         return;
4482
4483                 /* Setup HPD filtering */
4484                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
4485                         struct gpio_hpd_config config;
4486
4487                         config.delay_on_connect = 0;
4488                         config.delay_on_disconnect = 0;
4489
4490                         dal_irq_setup_hpd_filter(hpd, &config);
4491
4492                         dal_gpio_close(hpd);
4493                 } else {
4494                         ASSERT_CRITICAL(false);
4495                 }
4496                 /* Release HPD handle */
4497                 dal_gpio_destroy_irq(&hpd);
4498         }
4499 }
4500
4501 void dc_link_set_drive_settings(struct dc *dc,
4502                                 struct link_training_settings *lt_settings,
4503                                 const struct dc_link *link)
4504 {
4505
4506         int i;
4507         struct link_resource link_res;
4508
4509         for (i = 0; i < dc->link_count; i++)
4510                 if (dc->links[i] == link)
4511                         break;
4512
4513         if (i >= dc->link_count)
4514                 ASSERT_CRITICAL(false);
4515
4516         dc_link_get_cur_link_res(link, &link_res);
4517         dc_link_dp_set_drive_settings(dc->links[i], &link_res, lt_settings);
4518 }
4519
4520 void dc_link_set_preferred_link_settings(struct dc *dc,
4521                                          struct dc_link_settings *link_setting,
4522                                          struct dc_link *link)
4523 {
4524         int i;
4525         struct pipe_ctx *pipe;
4526         struct dc_stream_state *link_stream;
4527         struct dc_link_settings store_settings = *link_setting;
4528
4529         link->preferred_link_setting = store_settings;
4530
4531         /* Retrain with preferred link settings only relevant for
4532          * DP signal type
4533          * Check for non-DP signal or if passive dongle present
4534          */
4535         if (!dc_is_dp_signal(link->connector_signal) ||
4536                 link->dongle_max_pix_clk > 0)
4537                 return;
4538
4539         for (i = 0; i < MAX_PIPES; i++) {
4540                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4541                 if (pipe->stream && pipe->stream->link) {
4542                         if (pipe->stream->link == link) {
4543                                 link_stream = pipe->stream;
4544                                 break;
4545                         }
4546                 }
4547         }
4548
4549         /* Stream not found */
4550         if (i == MAX_PIPES)
4551                 return;
4552
4553         /* Cannot retrain link if backend is off */
4554         if (link_stream->dpms_off)
4555                 return;
4556
4557         decide_link_settings(link_stream, &store_settings);
4558
4559         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
4560                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
4561                 dp_retrain_link_dp_test(link, &store_settings, false);
4562 }
4563
4564 void dc_link_set_preferred_training_settings(struct dc *dc,
4565                                                  struct dc_link_settings *link_setting,
4566                                                  struct dc_link_training_overrides *lt_overrides,
4567                                                  struct dc_link *link,
4568                                                  bool skip_immediate_retrain)
4569 {
4570         if (lt_overrides != NULL)
4571                 link->preferred_training_settings = *lt_overrides;
4572         else
4573                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
4574
4575         if (link_setting != NULL) {
4576                 link->preferred_link_setting = *link_setting;
4577                 if (dp_get_link_encoding_format(link_setting) == DP_128b_132b_ENCODING)
4578                         /* TODO: add dc update for acquiring link res  */
4579                         skip_immediate_retrain = true;
4580         } else {
4581                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
4582                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
4583         }
4584
4585         /* Retrain now, or wait until next stream update to apply */
4586         if (skip_immediate_retrain == false)
4587                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
4588 }
4589
4590 void dc_link_enable_hpd(const struct dc_link *link)
4591 {
4592         dc_link_dp_enable_hpd(link);
4593 }
4594
4595 void dc_link_disable_hpd(const struct dc_link *link)
4596 {
4597         dc_link_dp_disable_hpd(link);
4598 }
4599
4600 void dc_link_set_test_pattern(struct dc_link *link,
4601                               enum dp_test_pattern test_pattern,
4602                               enum dp_test_pattern_color_space test_pattern_color_space,
4603                               const struct link_training_settings *p_link_settings,
4604                               const unsigned char *p_custom_pattern,
4605                               unsigned int cust_pattern_size)
4606 {
4607         if (link != NULL)
4608                 dc_link_dp_set_test_pattern(
4609                         link,
4610                         test_pattern,
4611                         test_pattern_color_space,
4612                         p_link_settings,
4613                         p_custom_pattern,
4614                         cust_pattern_size);
4615 }
4616
4617 uint32_t dc_link_bandwidth_kbps(
4618         const struct dc_link *link,
4619         const struct dc_link_settings *link_setting)
4620 {
4621         uint32_t total_data_bw_efficiency_x10000 = 0;
4622         uint32_t link_rate_per_lane_kbps = 0;
4623
4624         switch (dp_get_link_encoding_format(link_setting)) {
4625         case DP_8b_10b_ENCODING:
4626                 /* For 8b/10b encoding:
4627                  * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
4628                  * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
4629                  */
4630                 link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
4631                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
4632                 if (dc_link_should_enable_fec(link)) {
4633                         total_data_bw_efficiency_x10000 /= 100;
4634                         total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
4635                 }
4636                 break;
4637         case DP_128b_132b_ENCODING:
4638                 /* For 128b/132b encoding:
4639                  * link rate is defined in the unit of 10mbps per lane.
4640                  * total data bandwidth efficiency is always 96.71%.
4641                  */
4642                 link_rate_per_lane_kbps = link_setting->link_rate * 10000;
4643                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
4644                 break;
4645         default:
4646                 break;
4647         }
4648
4649         /* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
4650         return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
4651 }
4652
4653 const struct dc_link_settings *dc_link_get_link_cap(
4654                 const struct dc_link *link)
4655 {
4656         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
4657                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
4658                 return &link->preferred_link_setting;
4659         return &link->verified_link_cap;
4660 }
4661
4662 void dc_link_overwrite_extended_receiver_cap(
4663                 struct dc_link *link)
4664 {
4665         dp_overwrite_extended_receiver_cap(link);
4666 }
4667
4668 bool dc_link_is_fec_supported(const struct dc_link *link)
4669 {
4670         /* TODO - use asic cap instead of link_enc->features
4671          * we no longer know which link enc to use for this link before commit
4672          */
4673         struct link_encoder *link_enc = NULL;
4674
4675         link_enc = link_enc_cfg_get_link_enc(link);
4676         ASSERT(link_enc);
4677
4678         return (dc_is_dp_signal(link->connector_signal) && link_enc &&
4679                         link_enc->features.fec_supported &&
4680                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
4681                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
4682 }
4683
4684 bool dc_link_should_enable_fec(const struct dc_link *link)
4685 {
4686         bool is_fec_disable = false;
4687         bool ret = false;
4688
4689         if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
4690                         link->local_sink &&
4691                         link->local_sink->edid_caps.panel_patch.disable_fec) ||
4692                         (link->connector_signal == SIGNAL_TYPE_EDP
4693                                 // enable FEC for EDP if DSC is supported
4694                                 && link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT == false
4695                                 ))
4696                 is_fec_disable = true;
4697
4698         if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
4699                 ret = true;
4700
4701         return ret;
4702 }
4703
4704 uint32_t dc_bandwidth_in_kbps_from_timing(
4705                 const struct dc_crtc_timing *timing)
4706 {
4707         uint32_t bits_per_channel = 0;
4708         uint32_t kbps;
4709
4710 #if defined(CONFIG_DRM_AMD_DC_DCN)
4711         if (timing->flags.DSC)
4712                 return dc_dsc_stream_bandwidth_in_kbps(timing,
4713                                 timing->dsc_cfg.bits_per_pixel,
4714                                 timing->dsc_cfg.num_slices_h,
4715                                 timing->dsc_cfg.is_dp);
4716 #endif /* CONFIG_DRM_AMD_DC_DCN */
4717
4718         switch (timing->display_color_depth) {
4719         case COLOR_DEPTH_666:
4720                 bits_per_channel = 6;
4721                 break;
4722         case COLOR_DEPTH_888:
4723                 bits_per_channel = 8;
4724                 break;
4725         case COLOR_DEPTH_101010:
4726                 bits_per_channel = 10;
4727                 break;
4728         case COLOR_DEPTH_121212:
4729                 bits_per_channel = 12;
4730                 break;
4731         case COLOR_DEPTH_141414:
4732                 bits_per_channel = 14;
4733                 break;
4734         case COLOR_DEPTH_161616:
4735                 bits_per_channel = 16;
4736                 break;
4737         default:
4738                 ASSERT(bits_per_channel != 0);
4739                 bits_per_channel = 8;
4740                 break;
4741         }
4742
4743         kbps = timing->pix_clk_100hz / 10;
4744         kbps *= bits_per_channel;
4745
4746         if (timing->flags.Y_ONLY != 1) {
4747                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
4748                 kbps *= 3;
4749                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
4750                         kbps /= 2;
4751                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
4752                         kbps = kbps * 2 / 3;
4753         }
4754
4755         return kbps;
4756
4757 }
4758
4759 void dc_link_get_cur_link_res(const struct dc_link *link,
4760                 struct link_resource *link_res)
4761 {
4762         int i;
4763         struct pipe_ctx *pipe = NULL;
4764
4765         memset(link_res, 0, sizeof(*link_res));
4766
4767         for (i = 0; i < MAX_PIPES; i++) {
4768                 pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];
4769                 if (pipe->stream && pipe->stream->link && pipe->top_pipe == NULL) {
4770                         if (pipe->stream->link == link) {
4771                                 *link_res = pipe->link_res;
4772                                 break;
4773                         }
4774                 }
4775         }
4776
4777 }
4778
4779 /**
4780  * dc_get_cur_link_res_map() - take a snapshot of current link resource allocation state
4781  * @dc: pointer to dc of the dm calling this
4782  * @map: a dc link resource snapshot defined internally to dc.
4783  *
4784  * DM needs to capture a snapshot of current link resource allocation mapping
4785  * and store it in its persistent storage.
4786  *
4787  * Some of the link resource is using first come first serve policy.
4788  * The allocation mapping depends on original hotplug order. This information
4789  * is lost after driver is loaded next time. The snapshot is used in order to
4790  * restore link resource to its previous state so user will get consistent
4791  * link capability allocation across reboot.
4792  *
4793  * Return: none (void function)
4794  *
4795  */
4796 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)
4797 {
4798         struct dc_link *link;
4799         uint32_t i;
4800         uint32_t hpo_dp_recycle_map = 0;
4801
4802         *map = 0;
4803
4804         if (dc->caps.dp_hpo) {
4805                 for (i = 0; i < dc->caps.max_links; i++) {
4806                         link = dc->links[i];
4807                         if (link->link_status.link_active &&
4808                                         dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING &&
4809                                         dp_get_link_encoding_format(&link->cur_link_settings) != DP_128b_132b_ENCODING)
4810                                 /* hpo dp link encoder is considered as recycled, when RX reports 128b/132b encoding capability
4811                                  * but current link doesn't use it.
4812                                  */
4813                                 hpo_dp_recycle_map |= (1 << i);
4814                 }
4815                 *map |= (hpo_dp_recycle_map << LINK_RES_HPO_DP_REC_MAP__SHIFT);
4816         }
4817 }
4818
4819 /**
4820  * dc_restore_link_res_map() - restore link resource allocation state from a snapshot
4821  * @dc: pointer to dc of the dm calling this
4822  * @map: a dc link resource snapshot defined internally to dc.
4823  *
4824  * DM needs to call this function after initial link detection on boot and
4825  * before first commit streams to restore link resource allocation state
4826  * from previous boot session.
4827  *
4828  * Some of the link resource is using first come first serve policy.
4829  * The allocation mapping depends on original hotplug order. This information
4830  * is lost after driver is loaded next time. The snapshot is used in order to
4831  * restore link resource to its previous state so user will get consistent
4832  * link capability allocation across reboot.
4833  *
4834  * Return: none (void function)
4835  *
4836  */
4837 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)
4838 {
4839         struct dc_link *link;
4840         uint32_t i;
4841         unsigned int available_hpo_dp_count;
4842         uint32_t hpo_dp_recycle_map = (*map & LINK_RES_HPO_DP_REC_MAP__MASK)
4843                         >> LINK_RES_HPO_DP_REC_MAP__SHIFT;
4844
4845         if (dc->caps.dp_hpo) {
4846                 available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count;
4847                 /* remove excess 128b/132b encoding support for not recycled links */
4848                 for (i = 0; i < dc->caps.max_links; i++) {
4849                         if ((hpo_dp_recycle_map & (1 << i)) == 0) {
4850                                 link = dc->links[i];
4851                                 if (link->type != dc_connection_none &&
4852                                                 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4853                                         if (available_hpo_dp_count > 0)
4854                                                 available_hpo_dp_count--;
4855                                         else
4856                                                 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4857                                                 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4858                                 }
4859                         }
4860                 }
4861                 /* remove excess 128b/132b encoding support for recycled links */
4862                 for (i = 0; i < dc->caps.max_links; i++) {
4863                         if ((hpo_dp_recycle_map & (1 << i)) != 0) {
4864                                 link = dc->links[i];
4865                                 if (link->type != dc_connection_none &&
4866                                                 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4867                                         if (available_hpo_dp_count > 0)
4868                                                 available_hpo_dp_count--;
4869                                         else
4870                                                 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4871                                                 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4872                                 }
4873                         }
4874                 }
4875         }
4876 }