2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
28 #include "dm_helpers.h"
30 #include "grph_object_id.h"
31 #include "gpio_service_interface.h"
32 #include "core_status.h"
33 #include "dc_link_dp.h"
34 #include "dc_link_ddc.h"
35 #include "link_hwss.h"
38 #include "link_encoder.h"
39 #include "hw_sequencer.h"
42 #include "fixed31_32.h"
43 #include "dpcd_defs.h"
46 #include "dce/dce_11_0_d.h"
47 #include "dce/dce_11_0_enum.h"
48 #include "dce/dce_11_0_sh_mask.h"
50 #define DC_LOGGER_INIT(logger)
53 #define LINK_INFO(...) \
57 #define RETIMER_REDRIVER_INFO(...) \
58 DC_LOG_RETIMER_REDRIVER( \
60 /*******************************************************************************
62 ******************************************************************************/
65 LINK_RATE_REF_FREQ_IN_MHZ = 27,
66 PEAK_FACTOR_X1000 = 1006,
68 * Some receivers fail to train on first try and are good
69 * on subsequent tries. 2 retries should be plenty. If we
70 * don't have a successful training then we don't expect to
73 LINK_TRAINING_MAX_VERIFY_RETRY = 2
76 /*******************************************************************************
78 ******************************************************************************/
79 static void destruct(struct dc_link *link)
84 dal_ddc_service_destroy(&link->ddc);
87 link->link_enc->funcs->destroy(&link->link_enc);
90 dc_sink_release(link->local_sink);
92 for (i = 0; i < link->sink_count; ++i)
93 dc_sink_release(link->remote_sinks[i]);
96 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
97 struct graphics_object_id link_id,
98 struct gpio_service *gpio_service)
100 enum bp_result bp_result;
101 struct graphics_object_hpd_info hpd_info;
102 struct gpio_pin_info pin_info;
104 if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
107 bp_result = dcb->funcs->get_gpio_pin_info(dcb,
108 hpd_info.hpd_int_gpio_uid, &pin_info);
110 if (bp_result != BP_RESULT_OK) {
111 ASSERT(bp_result == BP_RESULT_NORECORD);
115 return dal_gpio_service_create_irq(
122 * Function: program_hpd_filter
125 * Programs HPD filter on associated HPD line
127 * @param [in] delay_on_connect_in_ms: Connect filter timeout
128 * @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
131 * true on success, false otherwise
133 static bool program_hpd_filter(
134 const struct dc_link *link)
140 int delay_on_connect_in_ms = 0;
141 int delay_on_disconnect_in_ms = 0;
143 if (link->is_hpd_filter_disabled)
145 /* Verify feature is supported */
146 switch (link->connector_signal) {
147 case SIGNAL_TYPE_DVI_SINGLE_LINK:
148 case SIGNAL_TYPE_DVI_DUAL_LINK:
149 case SIGNAL_TYPE_HDMI_TYPE_A:
150 /* Program hpd filter */
151 delay_on_connect_in_ms = 500;
152 delay_on_disconnect_in_ms = 100;
154 case SIGNAL_TYPE_DISPLAY_PORT:
155 case SIGNAL_TYPE_DISPLAY_PORT_MST:
156 /* Program hpd filter to allow DP signal to settle */
157 /* 500: not able to detect MST <-> SST switch as HPD is low for
158 * only 100ms on DELL U2413
159 * 0: some passive dongle still show aux mode instead of i2c
160 * 20-50:not enough to hide bouncing HPD with passive dongle.
161 * also see intermittent i2c read issues.
163 delay_on_connect_in_ms = 80;
164 delay_on_disconnect_in_ms = 0;
166 case SIGNAL_TYPE_LVDS:
167 case SIGNAL_TYPE_EDP:
169 /* Don't program hpd filter */
173 /* Obtain HPD handle */
174 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
179 /* Setup HPD filtering */
180 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
181 struct gpio_hpd_config config;
183 config.delay_on_connect = delay_on_connect_in_ms;
184 config.delay_on_disconnect = delay_on_disconnect_in_ms;
186 dal_irq_setup_hpd_filter(hpd, &config);
192 ASSERT_CRITICAL(false);
195 /* Release HPD handle */
196 dal_gpio_destroy_irq(&hpd);
202 * dc_link_detect_sink() - Determine if there is a sink connected
204 * @type: Returned connection type
205 * Does not detect downstream devices, such as MST sinks
206 * or display connected through active dongles
208 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
210 uint32_t is_hpd_high = 0;
211 struct gpio *hpd_pin;
213 if (link->connector_signal == SIGNAL_TYPE_LVDS) {
214 *type = dc_connection_single;
218 /* todo: may need to lock gpio access */
219 hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
221 goto hpd_gpio_failure;
223 dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
224 dal_gpio_get_value(hpd_pin, &is_hpd_high);
225 dal_gpio_close(hpd_pin);
226 dal_gpio_destroy_irq(&hpd_pin);
229 *type = dc_connection_single;
230 /* TODO: need to do the actual detection */
232 *type = dc_connection_none;
241 static enum ddc_transaction_type get_ddc_transaction_type(
242 enum signal_type sink_signal)
244 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
246 switch (sink_signal) {
247 case SIGNAL_TYPE_DVI_SINGLE_LINK:
248 case SIGNAL_TYPE_DVI_DUAL_LINK:
249 case SIGNAL_TYPE_HDMI_TYPE_A:
250 case SIGNAL_TYPE_LVDS:
251 case SIGNAL_TYPE_RGB:
252 transaction_type = DDC_TRANSACTION_TYPE_I2C;
255 case SIGNAL_TYPE_DISPLAY_PORT:
256 case SIGNAL_TYPE_EDP:
257 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
260 case SIGNAL_TYPE_DISPLAY_PORT_MST:
261 /* MST does not use I2COverAux, but there is the
262 * SPECIAL use case for "immediate dwnstrm device
263 * access" (EPR#370830). */
264 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
271 return transaction_type;
274 static enum signal_type get_basic_signal_type(
275 struct graphics_object_id encoder,
276 struct graphics_object_id downstream)
278 if (downstream.type == OBJECT_TYPE_CONNECTOR) {
279 switch (downstream.id) {
280 case CONNECTOR_ID_SINGLE_LINK_DVII:
281 switch (encoder.id) {
282 case ENCODER_ID_INTERNAL_DAC1:
283 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
284 case ENCODER_ID_INTERNAL_DAC2:
285 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
286 return SIGNAL_TYPE_RGB;
288 return SIGNAL_TYPE_DVI_SINGLE_LINK;
291 case CONNECTOR_ID_DUAL_LINK_DVII:
293 switch (encoder.id) {
294 case ENCODER_ID_INTERNAL_DAC1:
295 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
296 case ENCODER_ID_INTERNAL_DAC2:
297 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
298 return SIGNAL_TYPE_RGB;
300 return SIGNAL_TYPE_DVI_DUAL_LINK;
304 case CONNECTOR_ID_SINGLE_LINK_DVID:
305 return SIGNAL_TYPE_DVI_SINGLE_LINK;
306 case CONNECTOR_ID_DUAL_LINK_DVID:
307 return SIGNAL_TYPE_DVI_DUAL_LINK;
308 case CONNECTOR_ID_VGA:
309 return SIGNAL_TYPE_RGB;
310 case CONNECTOR_ID_HDMI_TYPE_A:
311 return SIGNAL_TYPE_HDMI_TYPE_A;
312 case CONNECTOR_ID_LVDS:
313 return SIGNAL_TYPE_LVDS;
314 case CONNECTOR_ID_DISPLAY_PORT:
315 return SIGNAL_TYPE_DISPLAY_PORT;
316 case CONNECTOR_ID_EDP:
317 return SIGNAL_TYPE_EDP;
319 return SIGNAL_TYPE_NONE;
321 } else if (downstream.type == OBJECT_TYPE_ENCODER) {
322 switch (downstream.id) {
323 case ENCODER_ID_EXTERNAL_NUTMEG:
324 case ENCODER_ID_EXTERNAL_TRAVIS:
325 return SIGNAL_TYPE_DISPLAY_PORT;
327 return SIGNAL_TYPE_NONE;
331 return SIGNAL_TYPE_NONE;
335 * dc_link_is_dp_sink_present() - Check if there is a native DP
336 * or passive DP-HDMI dongle connected
338 bool dc_link_is_dp_sink_present(struct dc_link *link)
340 enum gpio_result gpio_result;
341 uint32_t clock_pin = 0;
345 enum connector_id connector_id =
346 dal_graphics_object_id_get_connector_id(link->link_id);
349 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
350 (connector_id == CONNECTOR_ID_EDP));
352 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
359 /* Open GPIO and set it to I2C mode */
360 /* Note: this GpioMode_Input will be converted
361 * to GpioConfigType_I2cAuxDualMode in GPIO component,
362 * which indicates we need additional delay */
364 if (GPIO_RESULT_OK != dal_ddc_open(
365 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
366 dal_gpio_destroy_ddc(&ddc);
371 /* Read GPIO: DP sink is present if both clock and data pins are zero */
372 /* [anaumov] in DAL2, there was no check for GPIO failure */
374 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
375 ASSERT(gpio_result == GPIO_RESULT_OK);
377 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
386 * Detect output sink type
388 static enum signal_type link_detect_sink(
389 struct dc_link *link,
390 enum dc_detect_reason reason)
392 enum signal_type result = get_basic_signal_type(
393 link->link_enc->id, link->link_id);
395 /* Internal digital encoder will detect only dongles
396 * that require digital signal */
398 /* Detection mechanism is different
399 * for different native connectors.
400 * LVDS connector supports only LVDS signal;
401 * PCIE is a bus slot, the actual connector needs to be detected first;
402 * eDP connector supports only eDP signal;
403 * HDMI should check straps for audio */
405 /* PCIE detects the actual connector on add-on board */
407 if (link->link_id.id == CONNECTOR_ID_PCIE) {
408 /* ZAZTODO implement PCIE add-on card detection */
411 switch (link->link_id.id) {
412 case CONNECTOR_ID_HDMI_TYPE_A: {
413 /* check audio support:
414 * if native HDMI is not supported, switch to DVI */
415 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
417 if (!aud_support->hdmi_audio_native)
418 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
419 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
422 case CONNECTOR_ID_DISPLAY_PORT: {
423 /* DP HPD short pulse. Passive DP dongle will not
426 if (reason != DETECT_REASON_HPDRX) {
427 /* Check whether DP signal detected: if not -
428 * we assume signal is DVI; it could be corrected
429 * to HDMI after dongle detection
431 if (!dm_helpers_is_dp_sink_present(link))
432 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
443 static enum signal_type decide_signal_from_strap_and_dongle_type(
444 enum display_dongle_type dongle_type,
445 struct audio_support *audio_support)
447 enum signal_type signal = SIGNAL_TYPE_NONE;
449 switch (dongle_type) {
450 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
451 if (audio_support->hdmi_audio_on_dongle)
452 signal = SIGNAL_TYPE_HDMI_TYPE_A;
454 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
456 case DISPLAY_DONGLE_DP_DVI_DONGLE:
457 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
459 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
460 if (audio_support->hdmi_audio_native)
461 signal = SIGNAL_TYPE_HDMI_TYPE_A;
463 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
466 signal = SIGNAL_TYPE_NONE;
473 static enum signal_type dp_passive_dongle_detection(
474 struct ddc_service *ddc,
475 struct display_sink_capability *sink_cap,
476 struct audio_support *audio_support)
478 dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
480 return decide_signal_from_strap_and_dongle_type(
481 sink_cap->dongle_type,
485 static void link_disconnect_sink(struct dc_link *link)
487 if (link->local_sink) {
488 dc_sink_release(link->local_sink);
489 link->local_sink = NULL;
492 link->dpcd_sink_count = 0;
495 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
497 dc_sink_release(link->local_sink);
498 link->local_sink = prev_sink;
502 static bool detect_dp(
503 struct dc_link *link,
504 struct display_sink_capability *sink_caps,
505 bool *converter_disable_audio,
506 struct audio_support *audio_support,
507 enum dc_detect_reason reason)
510 sink_caps->signal = link_detect_sink(link, reason);
511 sink_caps->transaction_type =
512 get_ddc_transaction_type(sink_caps->signal);
514 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
515 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
516 if (!detect_dp_sink_caps(link))
519 if (is_mst_supported(link)) {
520 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
521 link->type = dc_connection_mst_branch;
523 dal_ddc_service_set_transaction_type(
525 sink_caps->transaction_type);
528 * This call will initiate MST topology discovery. Which
529 * will detect MST ports and add new DRM connector DRM
530 * framework. Then read EDID via remote i2c over aux. In
531 * the end, will notify DRM detect result and save EDID
532 * into DRM framework.
534 * .detect is called by .fill_modes.
535 * .fill_modes is called by user mode ioctl
536 * DRM_IOCTL_MODE_GETCONNECTOR.
538 * .get_modes is called by .fill_modes.
540 * call .get_modes, AMDGPU DM implementation will create
541 * new dc_sink and add to dc_link. For long HPD plug
542 * in/out, MST has its own handle.
544 * Therefore, just after dc_create, link->sink is not
545 * created for MST until user mode app calls
546 * DRM_IOCTL_MODE_GETCONNECTOR.
548 * Need check ->sink usages in case ->sink = NULL
549 * TODO: s3 resume check
551 if (reason == DETECT_REASON_BOOT)
554 dm_helpers_dp_update_branch_info(
558 if (!dm_helpers_dp_mst_start_top_mgr(
561 /* MST not supported */
562 link->type = dc_connection_single;
563 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
567 if (link->type != dc_connection_mst_branch &&
568 is_dp_active_dongle(link)) {
569 /* DP active dongles */
570 link->type = dc_connection_active_dongle;
571 if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
573 * active dongle unplug processing for short irq
575 link_disconnect_sink(link);
579 if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
580 *converter_disable_audio = true;
583 /* DP passive dongles */
584 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
592 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
594 if (old_edid->length != new_edid->length)
597 if (new_edid->length == 0)
600 return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
604 * dc_link_detect() - Detect if a sink is attached to a given link
606 * link->local_sink is created or destroyed as needed.
608 * This does not create remote sinks but will trigger DM
609 * to start MST detection if a branch is detected.
611 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
613 struct dc_sink_init_data sink_init_data = { 0 };
614 struct display_sink_capability sink_caps = { 0 };
616 bool converter_disable_audio = false;
617 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
618 bool same_edid = false;
619 enum dc_edid_status edid_status;
620 struct dc_context *dc_ctx = link->ctx;
621 struct dc_sink *sink = NULL;
622 struct dc_sink *prev_sink = NULL;
623 struct dpcd_caps prev_dpcd_caps;
624 bool same_dpcd = true;
625 enum dc_connection_type new_connection_type = dc_connection_none;
626 DC_LOGGER_INIT(link->ctx->logger);
627 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
630 if (false == dc_link_detect_sink(link, &new_connection_type)) {
635 if (link->connector_signal == SIGNAL_TYPE_EDP &&
639 if (link->connector_signal == SIGNAL_TYPE_LVDS &&
643 prev_sink = link->local_sink;
644 if (prev_sink != NULL) {
645 dc_sink_retain(prev_sink);
646 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
648 link_disconnect_sink(link);
650 if (new_connection_type != dc_connection_none) {
651 link->type = new_connection_type;
653 /* From Disconnected-to-Connected. */
654 switch (link->connector_signal) {
655 case SIGNAL_TYPE_HDMI_TYPE_A: {
656 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
657 if (aud_support->hdmi_audio_native)
658 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
660 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
664 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
665 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
666 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
670 case SIGNAL_TYPE_DVI_DUAL_LINK: {
671 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
672 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
676 case SIGNAL_TYPE_LVDS: {
677 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
678 sink_caps.signal = SIGNAL_TYPE_LVDS;
682 case SIGNAL_TYPE_EDP: {
683 detect_edp_sink_caps(link);
684 sink_caps.transaction_type =
685 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
686 sink_caps.signal = SIGNAL_TYPE_EDP;
690 case SIGNAL_TYPE_DISPLAY_PORT: {
694 &converter_disable_audio,
695 aud_support, reason)) {
696 if (prev_sink != NULL)
697 dc_sink_release(prev_sink);
701 // Check if dpcp block is the same
702 if (prev_sink != NULL) {
703 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
706 /* Active dongle downstream unplug */
707 if (link->type == dc_connection_active_dongle
708 && link->dpcd_caps.sink_count.
709 bits.SINK_COUNT == 0) {
710 if (prev_sink != NULL)
711 dc_sink_release(prev_sink);
715 if (link->type == dc_connection_mst_branch) {
716 LINK_INFO("link=%d, mst branch is now Connected\n",
718 /* Need to setup mst link_cap struct here
719 * otherwise dc_link_detect() will leave mst link_cap
720 * empty which leads to allocate_mst_payload() has "0"
721 * pbn_per_slot value leading to exception on dc_fixpt_div()
723 link->verified_link_cap = link->reported_link_cap;
724 if (prev_sink != NULL)
725 dc_sink_release(prev_sink);
733 DC_ERROR("Invalid connector type! signal:%d\n",
734 link->connector_signal);
735 if (prev_sink != NULL)
736 dc_sink_release(prev_sink);
740 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
741 link->dpcd_sink_count = link->dpcd_caps.sink_count.
744 link->dpcd_sink_count = 1;
746 dal_ddc_service_set_transaction_type(
748 sink_caps.transaction_type);
750 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
753 sink_init_data.link = link;
754 sink_init_data.sink_signal = sink_caps.signal;
756 sink = dc_sink_create(&sink_init_data);
758 DC_ERROR("Failed to create sink!\n");
759 if (prev_sink != NULL)
760 dc_sink_release(prev_sink);
764 sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
765 sink->converter_disable_audio = converter_disable_audio;
767 link->local_sink = sink;
769 edid_status = dm_helpers_read_local_edid(
774 switch (edid_status) {
775 case EDID_BAD_CHECKSUM:
776 DC_LOG_ERROR("EDID checksum invalid.\n");
778 case EDID_NO_RESPONSE:
779 DC_LOG_ERROR("No EDID read.\n");
782 * Abort detection for non-DP connectors if we have
785 * DP needs to report as connected if HDP is high
786 * even if we have no EDID in order to go to
789 if (dc_is_hdmi_signal(link->connector_signal) ||
790 dc_is_dvi_signal(link->connector_signal)) {
791 if (prev_sink != NULL)
792 dc_sink_release(prev_sink);
800 // Check if edid is the same
801 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
802 same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
804 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
805 sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX &&
806 reason != DETECT_REASON_HPDRX) {
808 * TODO debug why Dell 2413 doesn't like
812 /* deal with non-mst cases */
813 for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
816 dp_verify_link_cap(link,
817 &link->reported_link_cap,
825 // If edid is the same, then discard new sink and revert back to original sink
827 link_disconnect_remap(prev_sink, link);
834 /* HDMI-DVI Dongle */
835 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
836 !sink->edid_caps.edid_hdmi)
837 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
839 /* Connectivity log: detection */
840 for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
841 CONN_DATA_DETECT(link,
842 &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
844 "%s: [Block %d] ", sink->edid_caps.display_name, i);
847 DC_LOG_DETECTION_EDID_PARSER("%s: "
848 "manufacturer_id = %X, "
850 "serial_number = %X, "
851 "manufacture_week = %d, "
852 "manufacture_year = %d, "
853 "display_name = %s, "
854 "speaker_flag = %d, "
855 "audio_mode_count = %d\n",
857 sink->edid_caps.manufacturer_id,
858 sink->edid_caps.product_id,
859 sink->edid_caps.serial_number,
860 sink->edid_caps.manufacture_week,
861 sink->edid_caps.manufacture_year,
862 sink->edid_caps.display_name,
863 sink->edid_caps.speaker_flags,
864 sink->edid_caps.audio_mode_count);
866 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
867 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
869 "channel_count = %d, "
871 "sample_size = %d\n",
874 sink->edid_caps.audio_modes[i].format_code,
875 sink->edid_caps.audio_modes[i].channel_count,
876 sink->edid_caps.audio_modes[i].sample_rate,
877 sink->edid_caps.audio_modes[i].sample_size);
881 /* From Connected-to-Disconnected. */
882 if (link->type == dc_connection_mst_branch) {
883 LINK_INFO("link=%d, mst branch is now Disconnected\n",
886 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
888 link->mst_stream_alloc_table.stream_count = 0;
889 memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
892 link->type = dc_connection_none;
893 sink_caps.signal = SIGNAL_TYPE_NONE;
896 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
897 link->link_index, sink,
898 (sink_caps.signal == SIGNAL_TYPE_NONE ?
899 "Disconnected":"Connected"), prev_sink,
900 same_dpcd, same_edid);
902 if (prev_sink != NULL)
903 dc_sink_release(prev_sink);
908 bool dc_link_get_hpd_state(struct dc_link *dc_link)
910 struct gpio *hpd_pin;
913 hpd_pin = get_hpd_gpio(dc_link->ctx->dc_bios,
914 dc_link->link_id, dc_link->ctx->gpio_service);
918 dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
919 dal_gpio_get_value(hpd_pin, &state);
920 dal_gpio_close(hpd_pin);
921 dal_gpio_destroy_irq(&hpd_pin);
926 static enum hpd_source_id get_hpd_line(
927 struct dc_link *link)
930 enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
932 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
935 switch (dal_irq_get_source(hpd)) {
936 case DC_IRQ_SOURCE_HPD1:
937 hpd_id = HPD_SOURCEID1;
939 case DC_IRQ_SOURCE_HPD2:
940 hpd_id = HPD_SOURCEID2;
942 case DC_IRQ_SOURCE_HPD3:
943 hpd_id = HPD_SOURCEID3;
945 case DC_IRQ_SOURCE_HPD4:
946 hpd_id = HPD_SOURCEID4;
948 case DC_IRQ_SOURCE_HPD5:
949 hpd_id = HPD_SOURCEID5;
951 case DC_IRQ_SOURCE_HPD6:
952 hpd_id = HPD_SOURCEID6;
959 dal_gpio_destroy_irq(&hpd);
965 static enum channel_id get_ddc_line(struct dc_link *link)
968 enum channel_id channel = CHANNEL_ID_UNKNOWN;
970 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
973 switch (dal_ddc_get_line(ddc)) {
974 case GPIO_DDC_LINE_DDC1:
975 channel = CHANNEL_ID_DDC1;
977 case GPIO_DDC_LINE_DDC2:
978 channel = CHANNEL_ID_DDC2;
980 case GPIO_DDC_LINE_DDC3:
981 channel = CHANNEL_ID_DDC3;
983 case GPIO_DDC_LINE_DDC4:
984 channel = CHANNEL_ID_DDC4;
986 case GPIO_DDC_LINE_DDC5:
987 channel = CHANNEL_ID_DDC5;
989 case GPIO_DDC_LINE_DDC6:
990 channel = CHANNEL_ID_DDC6;
992 case GPIO_DDC_LINE_DDC_VGA:
993 channel = CHANNEL_ID_DDC_VGA;
995 case GPIO_DDC_LINE_I2C_PAD:
996 channel = CHANNEL_ID_I2C_PAD;
1007 static enum transmitter translate_encoder_to_transmitter(
1008 struct graphics_object_id encoder)
1010 switch (encoder.id) {
1011 case ENCODER_ID_INTERNAL_UNIPHY:
1012 switch (encoder.enum_id) {
1014 return TRANSMITTER_UNIPHY_A;
1016 return TRANSMITTER_UNIPHY_B;
1018 return TRANSMITTER_UNKNOWN;
1021 case ENCODER_ID_INTERNAL_UNIPHY1:
1022 switch (encoder.enum_id) {
1024 return TRANSMITTER_UNIPHY_C;
1026 return TRANSMITTER_UNIPHY_D;
1028 return TRANSMITTER_UNKNOWN;
1031 case ENCODER_ID_INTERNAL_UNIPHY2:
1032 switch (encoder.enum_id) {
1034 return TRANSMITTER_UNIPHY_E;
1036 return TRANSMITTER_UNIPHY_F;
1038 return TRANSMITTER_UNKNOWN;
1041 case ENCODER_ID_INTERNAL_UNIPHY3:
1042 switch (encoder.enum_id) {
1044 return TRANSMITTER_UNIPHY_G;
1046 return TRANSMITTER_UNKNOWN;
1049 case ENCODER_ID_EXTERNAL_NUTMEG:
1050 switch (encoder.enum_id) {
1052 return TRANSMITTER_NUTMEG_CRT;
1054 return TRANSMITTER_UNKNOWN;
1057 case ENCODER_ID_EXTERNAL_TRAVIS:
1058 switch (encoder.enum_id) {
1060 return TRANSMITTER_TRAVIS_CRT;
1062 return TRANSMITTER_TRAVIS_LCD;
1064 return TRANSMITTER_UNKNOWN;
1068 return TRANSMITTER_UNKNOWN;
1072 static bool construct(
1073 struct dc_link *link,
1074 const struct link_init_data *init_params)
1077 struct gpio *hpd_gpio = NULL;
1078 struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1079 struct dc_context *dc_ctx = init_params->ctx;
1080 struct encoder_init_data enc_init_data = { 0 };
1081 struct integrated_info info = {{{ 0 }}};
1082 struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1083 const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1084 DC_LOGGER_INIT(dc_ctx->logger);
1086 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1087 link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1089 link->link_status.dpcd_caps = &link->dpcd_caps;
1091 link->dc = init_params->dc;
1093 link->link_index = init_params->link_index;
1095 link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1097 if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1098 dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1099 __func__, init_params->connector_index,
1100 link->link_id.type, OBJECT_TYPE_CONNECTOR);
1104 if (link->dc->res_pool->funcs->link_init)
1105 link->dc->res_pool->funcs->link_init(link);
1107 hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1109 if (hpd_gpio != NULL)
1110 link->irq_source_hpd = dal_irq_get_source(hpd_gpio);
1112 switch (link->link_id.id) {
1113 case CONNECTOR_ID_HDMI_TYPE_A:
1114 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1117 case CONNECTOR_ID_SINGLE_LINK_DVID:
1118 case CONNECTOR_ID_SINGLE_LINK_DVII:
1119 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1121 case CONNECTOR_ID_DUAL_LINK_DVID:
1122 case CONNECTOR_ID_DUAL_LINK_DVII:
1123 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1125 case CONNECTOR_ID_DISPLAY_PORT:
1126 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1128 if (hpd_gpio != NULL)
1129 link->irq_source_hpd_rx =
1130 dal_irq_get_rx_source(hpd_gpio);
1133 case CONNECTOR_ID_EDP:
1134 link->connector_signal = SIGNAL_TYPE_EDP;
1136 if (hpd_gpio != NULL) {
1137 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1138 link->irq_source_hpd_rx =
1139 dal_irq_get_rx_source(hpd_gpio);
1142 case CONNECTOR_ID_LVDS:
1143 link->connector_signal = SIGNAL_TYPE_LVDS;
1146 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1150 if (hpd_gpio != NULL) {
1151 dal_gpio_destroy_irq(&hpd_gpio);
1155 /* TODO: #DAL3 Implement id to str function.*/
1156 LINK_INFO("Connector[%d] description:"
1158 init_params->connector_index,
1159 link->connector_signal);
1161 ddc_service_init_data.ctx = link->ctx;
1162 ddc_service_init_data.id = link->link_id;
1163 ddc_service_init_data.link = link;
1164 link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1166 if (link->ddc == NULL) {
1167 DC_ERROR("Failed to create ddc_service!\n");
1168 goto ddc_create_fail;
1173 dal_ddc_service_get_ddc_pin(link->ddc));
1175 enc_init_data.ctx = dc_ctx;
1176 bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1177 enc_init_data.connector = link->link_id;
1178 enc_init_data.channel = get_ddc_line(link);
1179 enc_init_data.hpd_source = get_hpd_line(link);
1181 link->hpd_src = enc_init_data.hpd_source;
1183 enc_init_data.transmitter =
1184 translate_encoder_to_transmitter(enc_init_data.encoder);
1185 link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1188 if( link->link_enc == NULL) {
1189 DC_ERROR("Failed to create link encoder!\n");
1190 goto link_enc_create_fail;
1193 link->link_enc_hw_inst = link->link_enc->transmitter;
1195 for (i = 0; i < 4; i++) {
1197 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1198 DC_ERROR("Failed to find device tag!\n");
1199 goto device_tag_fail;
1202 /* Look for device tag that matches connector signal,
1203 * CRT for rgb, LCD for other supported signal tyes
1205 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1207 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1208 && link->connector_signal != SIGNAL_TYPE_RGB)
1210 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1211 && link->connector_signal == SIGNAL_TYPE_RGB)
1216 if (bios->integrated_info)
1217 info = *bios->integrated_info;
1219 /* Look for channel mapping corresponding to connector and device tag */
1220 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1221 struct external_display_path *path =
1222 &info.ext_disp_conn_info.path[i];
1223 if (path->device_connector_id.enum_id == link->link_id.enum_id
1224 && path->device_connector_id.id == link->link_id.id
1225 && path->device_connector_id.type == link->link_id.type) {
1227 if (link->device_tag.acpi_device != 0
1228 && path->device_acpi_enum == link->device_tag.acpi_device) {
1229 link->ddi_channel_mapping = path->channel_mapping;
1230 link->chip_caps = path->caps;
1231 } else if (path->device_tag ==
1232 link->device_tag.dev_id.raw_device_tag) {
1233 link->ddi_channel_mapping = path->channel_mapping;
1234 link->chip_caps = path->caps;
1241 * TODO check if GPIO programmed correctly
1243 * If GPIO isn't programmed correctly HPD might not rise or drain
1244 * fast enough, leading to bounces.
1246 program_hpd_filter(link);
1250 link->link_enc->funcs->destroy(&link->link_enc);
1251 link_enc_create_fail:
1252 dal_ddc_service_destroy(&link->ddc);
1256 if (hpd_gpio != NULL) {
1257 dal_gpio_destroy_irq(&hpd_gpio);
1263 /*******************************************************************************
1265 ******************************************************************************/
1266 struct dc_link *link_create(const struct link_init_data *init_params)
1268 struct dc_link *link =
1269 kzalloc(sizeof(*link), GFP_KERNEL);
1274 if (false == construct(link, init_params))
1275 goto construct_fail;
1286 void link_destroy(struct dc_link **link)
1293 static void dpcd_configure_panel_mode(
1294 struct dc_link *link,
1295 enum dp_panel_mode panel_mode)
1297 union dpcd_edp_config edp_config_set;
1298 bool panel_mode_edp = false;
1299 DC_LOGGER_INIT(link->ctx->logger);
1301 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
1303 if (DP_PANEL_MODE_DEFAULT != panel_mode) {
1305 switch (panel_mode) {
1306 case DP_PANEL_MODE_EDP:
1307 case DP_PANEL_MODE_SPECIAL:
1308 panel_mode_edp = true;
1315 /*set edp panel mode in receiver*/
1316 core_link_read_dpcd(
1318 DP_EDP_CONFIGURATION_SET,
1319 &edp_config_set.raw,
1320 sizeof(edp_config_set.raw));
1322 if (edp_config_set.bits.PANEL_MODE_EDP
1323 != panel_mode_edp) {
1324 enum ddc_result result = DDC_RESULT_UNKNOWN;
1326 edp_config_set.bits.PANEL_MODE_EDP =
1328 result = core_link_write_dpcd(
1330 DP_EDP_CONFIGURATION_SET,
1331 &edp_config_set.raw,
1332 sizeof(edp_config_set.raw));
1334 ASSERT(result == DDC_RESULT_SUCESSFULL);
1337 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
1338 "eDP panel mode enabled: %d \n",
1340 link->dpcd_caps.panel_mode_edp,
1344 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1346 struct dc_stream_state *stream = pipe_ctx->stream;
1347 struct dc_link *link = stream->sink->link;
1348 union down_spread_ctrl old_downspread;
1349 union down_spread_ctrl new_downspread;
1351 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1352 &old_downspread.raw, sizeof(old_downspread));
1354 new_downspread.raw = old_downspread.raw;
1356 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1357 (stream->ignore_msa_timing_param) ? 1 : 0;
1359 if (new_downspread.raw != old_downspread.raw) {
1360 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1361 &new_downspread.raw, sizeof(new_downspread));
1365 static enum dc_status enable_link_dp(
1366 struct dc_state *state,
1367 struct pipe_ctx *pipe_ctx)
1369 struct dc_stream_state *stream = pipe_ctx->stream;
1370 enum dc_status status;
1371 bool skip_video_pattern;
1372 struct dc_link *link = stream->sink->link;
1373 struct dc_link_settings link_settings = {0};
1374 enum dp_panel_mode panel_mode;
1376 /* get link settings for video mode timing */
1377 decide_link_settings(stream, &link_settings);
1379 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1380 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1381 state->dccg->funcs->update_clocks(state->dccg, state, false);
1385 pipe_ctx->stream->signal,
1386 pipe_ctx->clock_source->id,
1389 if (stream->sink->edid_caps.panel_patch.dppowerup_delay > 0) {
1390 int delay_dp_power_up_in_ms = stream->sink->edid_caps.panel_patch.dppowerup_delay;
1392 msleep(delay_dp_power_up_in_ms);
1395 panel_mode = dp_get_panel_mode(link);
1396 dpcd_configure_panel_mode(link, panel_mode);
1398 skip_video_pattern = true;
1400 if (link_settings.link_rate == LINK_RATE_LOW)
1401 skip_video_pattern = false;
1403 if (perform_link_training_with_retries(
1407 LINK_TRAINING_ATTEMPTS)) {
1408 link->cur_link_settings = link_settings;
1412 status = DC_FAIL_DP_LINK_TRAINING;
1417 static enum dc_status enable_link_edp(
1418 struct dc_state *state,
1419 struct pipe_ctx *pipe_ctx)
1421 enum dc_status status;
1422 struct dc_stream_state *stream = pipe_ctx->stream;
1423 struct dc_link *link = stream->sink->link;
1424 /*in case it is not on*/
1425 link->dc->hwss.edp_power_control(link, true);
1426 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1428 status = enable_link_dp(state, pipe_ctx);
1434 static enum dc_status enable_link_dp_mst(
1435 struct dc_state *state,
1436 struct pipe_ctx *pipe_ctx)
1438 struct dc_link *link = pipe_ctx->stream->sink->link;
1440 /* sink signal type after MST branch is MST. Multiple MST sinks
1441 * share one link. Link DP PHY is enable or training only once.
1443 if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1446 /* clear payload table */
1447 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1449 /* set the sink to MST mode before enabling the link */
1450 dp_enable_mst_on_sink(link, true);
1452 return enable_link_dp(state, pipe_ctx);
1455 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1456 enum engine_id eng_id,
1457 struct ext_hdmi_settings *settings)
1459 bool result = false;
1461 struct integrated_info *integrated_info =
1462 pipe_ctx->stream->ctx->dc_bios->integrated_info;
1464 if (integrated_info == NULL)
1468 * Get retimer settings from sbios for passing SI eye test for DCE11
1469 * The setting values are varied based on board revision and port id
1470 * Therefore the setting values of each ports is passed by sbios.
1473 // Check if current bios contains ext Hdmi settings
1474 if (integrated_info->gpu_cap_info & 0x20) {
1476 case ENGINE_ID_DIGA:
1477 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1478 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1479 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1480 memmove(settings->reg_settings,
1481 integrated_info->dp0_ext_hdmi_reg_settings,
1482 sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1483 memmove(settings->reg_settings_6g,
1484 integrated_info->dp0_ext_hdmi_6g_reg_settings,
1485 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1488 case ENGINE_ID_DIGB:
1489 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1490 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1491 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1492 memmove(settings->reg_settings,
1493 integrated_info->dp1_ext_hdmi_reg_settings,
1494 sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1495 memmove(settings->reg_settings_6g,
1496 integrated_info->dp1_ext_hdmi_6g_reg_settings,
1497 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1500 case ENGINE_ID_DIGC:
1501 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1502 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1503 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1504 memmove(settings->reg_settings,
1505 integrated_info->dp2_ext_hdmi_reg_settings,
1506 sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1507 memmove(settings->reg_settings_6g,
1508 integrated_info->dp2_ext_hdmi_6g_reg_settings,
1509 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1512 case ENGINE_ID_DIGD:
1513 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1514 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1515 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1516 memmove(settings->reg_settings,
1517 integrated_info->dp3_ext_hdmi_reg_settings,
1518 sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1519 memmove(settings->reg_settings_6g,
1520 integrated_info->dp3_ext_hdmi_6g_reg_settings,
1521 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1528 if (result == true) {
1529 // Validate settings from bios integrated info table
1530 if (settings->slv_addr == 0)
1532 if (settings->reg_num > 9)
1534 if (settings->reg_num_6g > 3)
1537 for (i = 0; i < settings->reg_num; i++) {
1538 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1542 for (i = 0; i < settings->reg_num_6g; i++) {
1543 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1552 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1553 uint8_t address, uint8_t *buffer, uint32_t length)
1555 struct i2c_command cmd = {0};
1556 struct i2c_payload payload = {0};
1558 memset(&payload, 0, sizeof(payload));
1559 memset(&cmd, 0, sizeof(cmd));
1561 cmd.number_of_payloads = 1;
1562 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1563 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1565 payload.address = address;
1566 payload.data = buffer;
1567 payload.length = length;
1568 payload.write = true;
1569 cmd.payloads = &payload;
1571 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1572 pipe_ctx->stream->sink->link, &cmd))
1578 static void write_i2c_retimer_setting(
1579 struct pipe_ctx *pipe_ctx,
1581 bool is_over_340mhz,
1582 struct ext_hdmi_settings *settings)
1584 uint8_t slave_address = (settings->slv_addr >> 1);
1586 const uint8_t apply_rx_tx_change = 0x4;
1587 uint8_t offset = 0xA;
1590 bool i2c_success = false;
1591 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1593 memset(&buffer, 0, sizeof(buffer));
1595 /* Start Ext-Hdmi programming*/
1597 for (i = 0; i < settings->reg_num; i++) {
1598 /* Apply 3G settings */
1599 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1601 buffer[0] = settings->reg_settings[i].i2c_reg_index;
1602 buffer[1] = settings->reg_settings[i].i2c_reg_val;
1603 i2c_success = i2c_write(pipe_ctx, slave_address,
1604 buffer, sizeof(buffer));
1605 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1606 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1607 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1611 ASSERT(i2c_success);
1613 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1614 * needs to be set to 1 on every 0xA-0xC write.
1616 if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1617 settings->reg_settings[i].i2c_reg_index == 0xB ||
1618 settings->reg_settings[i].i2c_reg_index == 0xC) {
1620 /* Query current value from offset 0xA */
1621 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1622 value = settings->reg_settings[i].i2c_reg_val;
1625 dal_ddc_service_query_ddc_data(
1626 pipe_ctx->stream->sink->link->ddc,
1627 slave_address, &offset, 1, &value, 1);
1630 ASSERT(i2c_success);
1634 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1635 buffer[1] = value | apply_rx_tx_change;
1636 i2c_success = i2c_write(pipe_ctx, slave_address,
1637 buffer, sizeof(buffer));
1638 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1639 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1640 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1643 ASSERT(i2c_success);
1648 /* Apply 3G settings */
1649 if (is_over_340mhz) {
1650 for (i = 0; i < settings->reg_num_6g; i++) {
1651 /* Apply 3G settings */
1652 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1654 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1655 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1656 i2c_success = i2c_write(pipe_ctx, slave_address,
1657 buffer, sizeof(buffer));
1658 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1659 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1660 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1664 ASSERT(i2c_success);
1666 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1667 * needs to be set to 1 on every 0xA-0xC write.
1669 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1670 settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1671 settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1673 /* Query current value from offset 0xA */
1674 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1675 value = settings->reg_settings_6g[i].i2c_reg_val;
1678 dal_ddc_service_query_ddc_data(
1679 pipe_ctx->stream->sink->link->ddc,
1680 slave_address, &offset, 1, &value, 1);
1683 ASSERT(i2c_success);
1687 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1688 buffer[1] = value | apply_rx_tx_change;
1689 i2c_success = i2c_write(pipe_ctx, slave_address,
1690 buffer, sizeof(buffer));
1691 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1692 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1693 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1696 ASSERT(i2c_success);
1703 /* Program additional settings if using 640x480 resolution */
1705 /* Write offset 0xFF to 0x01 */
1708 i2c_success = i2c_write(pipe_ctx, slave_address,
1709 buffer, sizeof(buffer));
1710 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1711 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1712 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1715 ASSERT(i2c_success);
1717 /* Write offset 0x00 to 0x23 */
1720 i2c_success = i2c_write(pipe_ctx, slave_address,
1721 buffer, sizeof(buffer));
1722 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1723 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1724 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1727 ASSERT(i2c_success);
1729 /* Write offset 0xff to 0x00 */
1732 i2c_success = i2c_write(pipe_ctx, slave_address,
1733 buffer, sizeof(buffer));
1734 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1735 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1736 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1739 ASSERT(i2c_success);
1744 static void write_i2c_default_retimer_setting(
1745 struct pipe_ctx *pipe_ctx,
1747 bool is_over_340mhz)
1749 uint8_t slave_address = (0xBA >> 1);
1751 bool i2c_success = false;
1752 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1754 memset(&buffer, 0, sizeof(buffer));
1756 /* Program Slave Address for tuning single integrity */
1757 /* Write offset 0x0A to 0x13 */
1760 i2c_success = i2c_write(pipe_ctx, slave_address,
1761 buffer, sizeof(buffer));
1762 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
1763 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1764 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1767 ASSERT(i2c_success);
1769 /* Write offset 0x0A to 0x17 */
1772 i2c_success = i2c_write(pipe_ctx, slave_address,
1773 buffer, sizeof(buffer));
1774 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1775 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1776 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1779 ASSERT(i2c_success);
1781 /* Write offset 0x0B to 0xDA or 0xD8 */
1783 buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1784 i2c_success = i2c_write(pipe_ctx, slave_address,
1785 buffer, sizeof(buffer));
1786 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1787 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1788 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1791 ASSERT(i2c_success);
1793 /* Write offset 0x0A to 0x17 */
1796 i2c_success = i2c_write(pipe_ctx, slave_address,
1797 buffer, sizeof(buffer));
1798 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1799 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1800 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1803 ASSERT(i2c_success);
1805 /* Write offset 0x0C to 0x1D or 0x91 */
1807 buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1808 i2c_success = i2c_write(pipe_ctx, slave_address,
1809 buffer, sizeof(buffer));
1810 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1811 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1812 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1815 ASSERT(i2c_success);
1817 /* Write offset 0x0A to 0x17 */
1820 i2c_success = i2c_write(pipe_ctx, slave_address,
1821 buffer, sizeof(buffer));
1822 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1823 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1824 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1827 ASSERT(i2c_success);
1831 /* Program additional settings if using 640x480 resolution */
1833 /* Write offset 0xFF to 0x01 */
1836 i2c_success = i2c_write(pipe_ctx, slave_address,
1837 buffer, sizeof(buffer));
1838 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1839 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1840 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1843 ASSERT(i2c_success);
1845 /* Write offset 0x00 to 0x23 */
1848 i2c_success = i2c_write(pipe_ctx, slave_address,
1849 buffer, sizeof(buffer));
1850 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1851 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1852 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1855 ASSERT(i2c_success);
1857 /* Write offset 0xff to 0x00 */
1860 i2c_success = i2c_write(pipe_ctx, slave_address,
1861 buffer, sizeof(buffer));
1862 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
1863 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
1864 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1867 ASSERT(i2c_success);
1871 static void write_i2c_redriver_setting(
1872 struct pipe_ctx *pipe_ctx,
1873 bool is_over_340mhz)
1875 uint8_t slave_address = (0xF0 >> 1);
1877 bool i2c_success = false;
1878 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1880 memset(&buffer, 0, sizeof(buffer));
1882 // Program Slave Address for tuning single integrity
1886 buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
1888 i2c_success = i2c_write(pipe_ctx, slave_address,
1889 buffer, sizeof(buffer));
1890 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
1891 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
1892 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
1893 i2c_success = %d\n",
1894 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
1898 ASSERT(i2c_success);
1901 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1903 struct dc_stream_state *stream = pipe_ctx->stream;
1904 struct dc_link *link = stream->sink->link;
1905 enum dc_color_depth display_color_depth;
1906 enum engine_id eng_id;
1907 struct ext_hdmi_settings settings = {0};
1908 bool is_over_340mhz = false;
1909 bool is_vga_mode = (stream->timing.h_addressable == 640)
1910 && (stream->timing.v_addressable == 480);
1912 if (stream->phy_pix_clk == 0)
1913 stream->phy_pix_clk = stream->timing.pix_clk_khz;
1914 if (stream->phy_pix_clk > 340000)
1915 is_over_340mhz = true;
1917 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
1918 unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
1919 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1920 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1921 /* DP159, Retimer settings */
1922 eng_id = pipe_ctx->stream_res.stream_enc->id;
1924 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
1925 write_i2c_retimer_setting(pipe_ctx,
1926 is_vga_mode, is_over_340mhz, &settings);
1928 write_i2c_default_retimer_setting(pipe_ctx,
1929 is_vga_mode, is_over_340mhz);
1931 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
1932 /* PI3EQX1204, Redriver settings */
1933 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
1937 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1938 dal_ddc_service_write_scdc_data(
1939 stream->sink->link->ddc,
1940 stream->phy_pix_clk,
1941 stream->timing.flags.LTE_340MCSC_SCRAMBLE);
1943 memset(&stream->sink->link->cur_link_settings, 0,
1944 sizeof(struct dc_link_settings));
1946 display_color_depth = stream->timing.display_color_depth;
1947 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1948 display_color_depth = COLOR_DEPTH_888;
1950 link->link_enc->funcs->enable_tmds_output(
1952 pipe_ctx->clock_source->id,
1953 display_color_depth,
1954 pipe_ctx->stream->signal,
1955 stream->phy_pix_clk);
1957 if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
1958 dal_ddc_service_read_scdc_data(link->ddc);
1961 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
1963 struct dc_stream_state *stream = pipe_ctx->stream;
1964 struct dc_link *link = stream->sink->link;
1966 if (stream->phy_pix_clk == 0)
1967 stream->phy_pix_clk = stream->timing.pix_clk_khz;
1969 memset(&stream->sink->link->cur_link_settings, 0,
1970 sizeof(struct dc_link_settings));
1972 link->link_enc->funcs->enable_lvds_output(
1974 pipe_ctx->clock_source->id,
1975 stream->phy_pix_clk);
1979 /****************************enable_link***********************************/
1980 static enum dc_status enable_link(
1981 struct dc_state *state,
1982 struct pipe_ctx *pipe_ctx)
1984 enum dc_status status = DC_ERROR_UNEXPECTED;
1985 switch (pipe_ctx->stream->signal) {
1986 case SIGNAL_TYPE_DISPLAY_PORT:
1987 status = enable_link_dp(state, pipe_ctx);
1989 case SIGNAL_TYPE_EDP:
1990 status = enable_link_edp(state, pipe_ctx);
1992 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1993 status = enable_link_dp_mst(state, pipe_ctx);
1996 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1997 case SIGNAL_TYPE_DVI_DUAL_LINK:
1998 case SIGNAL_TYPE_HDMI_TYPE_A:
1999 enable_link_hdmi(pipe_ctx);
2002 case SIGNAL_TYPE_LVDS:
2003 enable_link_lvds(pipe_ctx);
2006 case SIGNAL_TYPE_VIRTUAL:
2016 static void disable_link(struct dc_link *link, enum signal_type signal)
2019 * TODO: implement call for dp_set_hw_test_pattern
2020 * it is needed for compliance testing
2023 /* here we need to specify that encoder output settings
2024 * need to be calculated as for the set mode,
2025 * it will lead to querying dynamic link capabilities
2026 * which should be done before enable output */
2028 if (dc_is_dp_signal(signal)) {
2030 if (dc_is_dp_sst_signal(signal))
2031 dp_disable_link_phy(link, signal);
2033 dp_disable_link_phy_mst(link, signal);
2035 link->link_enc->funcs->disable_output(link->link_enc, signal);
2038 static bool dp_active_dongle_validate_timing(
2039 const struct dc_crtc_timing *timing,
2040 const struct dpcd_caps *dpcd_caps)
2042 unsigned int required_pix_clk = timing->pix_clk_khz;
2043 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2045 switch (dpcd_caps->dongle_type) {
2046 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2047 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2048 case DISPLAY_DONGLE_DP_DVI_DONGLE:
2049 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2057 if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2058 dongle_caps->extendedCapValid == false)
2061 /* Check Pixel Encoding */
2062 switch (timing->pixel_encoding) {
2063 case PIXEL_ENCODING_RGB:
2064 case PIXEL_ENCODING_YCBCR444:
2066 case PIXEL_ENCODING_YCBCR422:
2067 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2070 case PIXEL_ENCODING_YCBCR420:
2071 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2075 /* Invalid Pixel Encoding*/
2080 /* Check Color Depth and Pixel Clock */
2081 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2082 required_pix_clk /= 2;
2083 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2084 required_pix_clk = required_pix_clk * 2 / 3;
2086 switch (timing->display_color_depth) {
2087 case COLOR_DEPTH_666:
2088 case COLOR_DEPTH_888:
2089 /*888 and 666 should always be supported*/
2091 case COLOR_DEPTH_101010:
2092 if (dongle_caps->dp_hdmi_max_bpc < 10)
2094 required_pix_clk = required_pix_clk * 10 / 8;
2096 case COLOR_DEPTH_121212:
2097 if (dongle_caps->dp_hdmi_max_bpc < 12)
2099 required_pix_clk = required_pix_clk * 12 / 8;
2102 case COLOR_DEPTH_141414:
2103 case COLOR_DEPTH_161616:
2105 /* These color depths are currently not supported */
2109 if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
2115 enum dc_status dc_link_validate_mode_timing(
2116 const struct dc_stream_state *stream,
2117 struct dc_link *link,
2118 const struct dc_crtc_timing *timing)
2120 uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
2121 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2123 /* A hack to avoid failing any modes for EDID override feature on
2124 * topology change such as lower quality cable for DP or different dongle
2126 if (link->remote_sinks[0])
2129 /* Passive Dongle */
2130 if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
2131 return DC_EXCEED_DONGLE_CAP;
2134 if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2135 return DC_EXCEED_DONGLE_CAP;
2137 switch (stream->signal) {
2138 case SIGNAL_TYPE_EDP:
2139 case SIGNAL_TYPE_DISPLAY_PORT:
2140 if (!dp_validate_mode_timing(
2143 return DC_NO_DP_LINK_BANDWIDTH;
2153 int dc_link_get_backlight_level(const struct dc_link *link)
2155 struct abm *abm = link->ctx->dc->res_pool->abm;
2157 if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2158 return DC_ERROR_UNEXPECTED;
2160 return (int) abm->funcs->get_current_backlight(abm);
2163 bool dc_link_set_backlight_level(const struct dc_link *link,
2164 uint32_t backlight_pwm_u16_16,
2165 uint32_t frame_ramp,
2166 const struct dc_stream_state *stream)
2168 struct dc *core_dc = link->ctx->dc;
2169 struct abm *abm = core_dc->res_pool->abm;
2170 struct dmcu *dmcu = core_dc->res_pool->dmcu;
2171 unsigned int controller_id = 0;
2172 bool use_smooth_brightness = true;
2174 DC_LOGGER_INIT(link->ctx->logger);
2176 if ((dmcu == NULL) ||
2178 (abm->funcs->set_backlight_level_pwm == NULL))
2182 ((struct dc_stream_state *)stream)->bl_pwm_level =
2183 backlight_pwm_u16_16;
2185 use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2187 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2188 backlight_pwm_u16_16, backlight_pwm_u16_16);
2190 if (dc_is_embedded_signal(link->connector_signal)) {
2191 for (i = 0; i < MAX_PIPES; i++) {
2192 if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
2193 if (core_dc->current_state->res_ctx.
2194 pipe_ctx[i].stream->sink->link
2196 /* DMCU -1 for all controller id values,
2200 core_dc->current_state->
2201 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2205 abm->funcs->set_backlight_level_pwm(
2207 backlight_pwm_u16_16,
2210 use_smooth_brightness);
2216 bool dc_link_set_abm_disable(const struct dc_link *link)
2218 struct dc *core_dc = link->ctx->dc;
2219 struct abm *abm = core_dc->res_pool->abm;
2221 if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
2224 abm->funcs->set_abm_immediate_disable(abm);
2229 bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
2231 struct dc *core_dc = link->ctx->dc;
2232 struct dmcu *dmcu = core_dc->res_pool->dmcu;
2234 if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_enabled)
2235 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
2240 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2242 return &link->link_status;
2245 void core_link_resume(struct dc_link *link)
2247 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2248 program_hpd_filter(link);
2251 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2253 struct dc_link_settings *link_settings =
2254 &stream->sink->link->cur_link_settings;
2255 uint32_t link_rate_in_mbps =
2256 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
2257 struct fixed31_32 mbps = dc_fixpt_from_int(
2258 link_rate_in_mbps * link_settings->lane_count);
2260 return dc_fixpt_div_int(mbps, 54);
2263 static int get_color_depth(enum dc_color_depth color_depth)
2265 switch (color_depth) {
2266 case COLOR_DEPTH_666: return 6;
2267 case COLOR_DEPTH_888: return 8;
2268 case COLOR_DEPTH_101010: return 10;
2269 case COLOR_DEPTH_121212: return 12;
2270 case COLOR_DEPTH_141414: return 14;
2271 case COLOR_DEPTH_161616: return 16;
2276 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2280 struct fixed31_32 peak_kbps;
2282 uint32_t denominator;
2284 bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2285 kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
2288 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2289 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2290 * common multiplier to render an integer PBN for all link rate/lane
2291 * counts combinations
2293 * peak_kbps *= (1006/1000)
2294 * peak_kbps *= (64/54)
2295 * peak_kbps *= 8 convert to bytes
2298 numerator = 64 * PEAK_FACTOR_X1000;
2299 denominator = 54 * 8 * 1000 * 1000;
2301 peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2306 static void update_mst_stream_alloc_table(
2307 struct dc_link *link,
2308 struct stream_encoder *stream_enc,
2309 const struct dp_mst_stream_allocation_table *proposed_table)
2311 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2313 struct link_mst_stream_allocation *dc_alloc;
2318 /* if DRM proposed_table has more than one new payload */
2319 ASSERT(proposed_table->stream_count -
2320 link->mst_stream_alloc_table.stream_count < 2);
2322 /* copy proposed_table to link, add stream encoder */
2323 for (i = 0; i < proposed_table->stream_count; i++) {
2325 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2327 &link->mst_stream_alloc_table.stream_allocations[j];
2329 if (dc_alloc->vcp_id ==
2330 proposed_table->stream_allocations[i].vcp_id) {
2332 work_table[i] = *dc_alloc;
2333 break; /* exit j loop */
2338 if (j == link->mst_stream_alloc_table.stream_count) {
2339 work_table[i].vcp_id =
2340 proposed_table->stream_allocations[i].vcp_id;
2341 work_table[i].slot_count =
2342 proposed_table->stream_allocations[i].slot_count;
2343 work_table[i].stream_enc = stream_enc;
2347 /* update link->mst_stream_alloc_table with work_table */
2348 link->mst_stream_alloc_table.stream_count =
2349 proposed_table->stream_count;
2350 for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2351 link->mst_stream_alloc_table.stream_allocations[i] =
2355 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2356 * because stream_encoder is not exposed to dm
2358 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2360 struct dc_stream_state *stream = pipe_ctx->stream;
2361 struct dc_link *link = stream->sink->link;
2362 struct link_encoder *link_encoder = link->link_enc;
2363 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2364 struct dp_mst_stream_allocation_table proposed_table = {0};
2365 struct fixed31_32 avg_time_slots_per_mtp;
2366 struct fixed31_32 pbn;
2367 struct fixed31_32 pbn_per_slot;
2369 DC_LOGGER_INIT(link->ctx->logger);
2371 /* enable_link_dp_mst already check link->enabled_stream_count
2372 * and stream is in link->stream[]. This is called during set mode,
2373 * stream_enc is available.
2376 /* get calculate VC payload for stream: stream_alloc */
2377 if (dm_helpers_dp_mst_write_payload_allocation_table(
2382 update_mst_stream_alloc_table(
2383 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2386 DC_LOG_WARNING("Failed to update"
2387 "MST allocation table for"
2389 pipe_ctx->pipe_idx);
2392 "stream_count: %d: \n ",
2394 link->mst_stream_alloc_table.stream_count);
2396 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2397 DC_LOG_MST("stream_enc[%d]: %p "
2398 "stream[%d].vcp_id: %d "
2399 "stream[%d].slot_count: %d\n",
2401 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2403 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2405 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2408 ASSERT(proposed_table.stream_count > 0);
2410 /* program DP source TX for payload */
2411 link_encoder->funcs->update_mst_stream_allocation_table(
2413 &link->mst_stream_alloc_table);
2415 /* send down message */
2416 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2420 dm_helpers_dp_mst_send_payload_allocation(
2425 /* slot X.Y for only current stream */
2426 pbn_per_slot = get_pbn_per_slot(stream);
2427 pbn = get_pbn_from_timing(pipe_ctx);
2428 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2430 stream_encoder->funcs->set_mst_bandwidth(
2432 avg_time_slots_per_mtp);
2438 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2440 struct dc_stream_state *stream = pipe_ctx->stream;
2441 struct dc_link *link = stream->sink->link;
2442 struct link_encoder *link_encoder = link->link_enc;
2443 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2444 struct dp_mst_stream_allocation_table proposed_table = {0};
2445 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2447 bool mst_mode = (link->type == dc_connection_mst_branch);
2448 DC_LOGGER_INIT(link->ctx->logger);
2450 /* deallocate_mst_payload is called before disable link. When mode or
2451 * disable/enable monitor, new stream is created which is not in link
2452 * stream[] yet. For this, payload is not allocated yet, so de-alloc
2453 * should not done. For new mode set, map_resources will get engine
2454 * for new stream, so stream_enc->id should be validated until here.
2458 stream_encoder->funcs->set_mst_bandwidth(
2460 avg_time_slots_per_mtp);
2462 /* TODO: which component is responsible for remove payload table? */
2464 if (dm_helpers_dp_mst_write_payload_allocation_table(
2470 update_mst_stream_alloc_table(
2471 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2474 DC_LOG_WARNING("Failed to update"
2475 "MST allocation table for"
2477 pipe_ctx->pipe_idx);
2482 "stream_count: %d: ",
2484 link->mst_stream_alloc_table.stream_count);
2486 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2487 DC_LOG_MST("stream_enc[%d]: %p "
2488 "stream[%d].vcp_id: %d "
2489 "stream[%d].slot_count: %d\n",
2491 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2493 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2495 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2498 link_encoder->funcs->update_mst_stream_allocation_table(
2500 &link->mst_stream_alloc_table);
2503 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2507 dm_helpers_dp_mst_send_payload_allocation(
2516 void core_link_enable_stream(
2517 struct dc_state *state,
2518 struct pipe_ctx *pipe_ctx)
2520 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2521 struct dc_stream_state *stream = pipe_ctx->stream;
2522 enum dc_status status;
2523 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2525 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) {
2526 stream->sink->link->link_enc->funcs->setup(
2527 stream->sink->link->link_enc,
2528 pipe_ctx->stream->signal);
2529 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
2530 pipe_ctx->stream_res.stream_enc,
2531 pipe_ctx->stream_res.tg->inst,
2532 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
2535 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2536 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
2537 pipe_ctx->stream_res.stream_enc,
2539 stream->output_color_space);
2541 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2542 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
2543 pipe_ctx->stream_res.stream_enc,
2545 stream->phy_pix_clk,
2546 pipe_ctx->stream_res.audio != NULL);
2548 if (dc_is_dvi_signal(pipe_ctx->stream->signal))
2549 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
2550 pipe_ctx->stream_res.stream_enc,
2552 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
2555 if (dc_is_lvds_signal(pipe_ctx->stream->signal))
2556 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
2557 pipe_ctx->stream_res.stream_enc,
2560 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
2561 resource_build_info_frame(pipe_ctx);
2562 core_dc->hwss.update_info_frame(pipe_ctx);
2564 /* eDP lit up by bios already, no need to enable again. */
2565 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2566 pipe_ctx->stream->apply_edp_fast_boot_optimization) {
2567 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2568 pipe_ctx->stream->dpms_off = false;
2572 if (pipe_ctx->stream->dpms_off)
2575 status = enable_link(state, pipe_ctx);
2577 if (status != DC_OK) {
2578 DC_LOG_WARNING("enabling link %u failed: %d\n",
2579 pipe_ctx->stream->sink->link->link_index,
2582 /* Abort stream enable *unless* the failure was due to
2583 * DP link training - some DP monitors will recover and
2584 * show the stream anyway. But MST displays can't proceed
2585 * without link training.
2587 if (status != DC_FAIL_DP_LINK_TRAINING ||
2588 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2589 BREAK_TO_DEBUGGER();
2594 core_dc->hwss.enable_audio_stream(pipe_ctx);
2596 /* turn off otg test pattern if enable */
2597 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2598 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2599 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2600 COLOR_DEPTH_UNDEFINED);
2602 core_dc->hwss.enable_stream(pipe_ctx);
2604 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2605 allocate_mst_payload(pipe_ctx);
2607 core_dc->hwss.unblank_stream(pipe_ctx,
2608 &pipe_ctx->stream->sink->link->cur_link_settings);
2610 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2611 enable_stream_features(pipe_ctx);
2613 dc_link_set_backlight_level(pipe_ctx->stream->sink->link,
2614 pipe_ctx->stream->bl_pwm_level,
2621 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
2623 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2625 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2626 deallocate_mst_payload(pipe_ctx);
2628 core_dc->hwss.blank_stream(pipe_ctx);
2630 core_dc->hwss.disable_stream(pipe_ctx, option);
2632 disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
2635 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2637 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2639 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2642 core_dc->hwss.set_avmute(pipe_ctx, enable);
2646 *****************************************************************************
2647 * Function: dc_link_enable_hpd_filter
2650 * If enable is true, programs HPD filter on associated HPD line using
2651 * delay_on_disconnect/delay_on_connect values dependent on
2652 * link->connector_signal
2654 * If enable is false, programs HPD filter on associated HPD line with no
2655 * delays on connect or disconnect
2657 * @param [in] link: pointer to the dc link
2658 * @param [in] enable: boolean specifying whether to enable hbd
2659 *****************************************************************************
2661 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
2666 link->is_hpd_filter_disabled = false;
2667 program_hpd_filter(link);
2669 link->is_hpd_filter_disabled = true;
2670 /* Obtain HPD handle */
2671 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
2676 /* Setup HPD filtering */
2677 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
2678 struct gpio_hpd_config config;
2680 config.delay_on_connect = 0;
2681 config.delay_on_disconnect = 0;
2683 dal_irq_setup_hpd_filter(hpd, &config);
2685 dal_gpio_close(hpd);
2687 ASSERT_CRITICAL(false);
2689 /* Release HPD handle */
2690 dal_gpio_destroy_irq(&hpd);