drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atomfirmware.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48 #include "dce/dmub_psr.h"
  49 #include "dmub/dmub_srv.h"
  50 #include "inc/hw/panel_cntl.h"
  51
  52 #define DC_LOGGER_INIT(logger)
  53
  54 #define LINK_INFO(...) \
  55         DC_LOG_HW_HOTPLUG(  \
  56                 __VA_ARGS__)
  57
  58 #define RETIMER_REDRIVER_INFO(...) \
  59         DC_LOG_RETIMER_REDRIVER(  \
  60                 __VA_ARGS__)
  61 /*******************************************************************************
  62  * Private structures
  63  ******************************************************************************/
  64
  65 enum {
  66         PEAK_FACTOR_X1000 = 1006,
  67         /*
  68          * Some receivers fail to train on first try and are good
  69          * on subsequent tries. 2 retries should be plenty. If we
  70          * don't have a successful training then we don't expect to
  71          * ever get one.
  72          */
  73         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  74 };
  75
  76 /*******************************************************************************
  77  * Private functions
  78  ******************************************************************************/
  79 static void dc_link_destruct(struct dc_link *link)
  80 {
  81         int i;
  82
  83         if (link->hpd_gpio) {
  84                 dal_gpio_destroy_irq(&link->hpd_gpio);
  85                 link->hpd_gpio = NULL;
  86         }
  87
  88         if (link->ddc)
  89                 dal_ddc_service_destroy(&link->ddc);
  90
  91         if (link->panel_cntl)
  92                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
  93
  94         if (link->link_enc)
  95                 link->link_enc->funcs->destroy(&link->link_enc);
  96
  97         if (link->local_sink)
  98                 dc_sink_release(link->local_sink);
  99
 100         for (i = 0; i < link->sink_count; ++i)
 101                 dc_sink_release(link->remote_sinks[i]);
 102 }
 103
 104 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 105                           struct graphics_object_id link_id,
 106                           struct gpio_service *gpio_service)
 107 {
 108         enum bp_result bp_result;
 109         struct graphics_object_hpd_info hpd_info;
 110         struct gpio_pin_info pin_info;
 111
 112         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 113                 return NULL;
 114
 115         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 116                 hpd_info.hpd_int_gpio_uid, &pin_info);
 117
 118         if (bp_result != BP_RESULT_OK) {
 119                 ASSERT(bp_result == BP_RESULT_NORECORD);
 120                 return NULL;
 121         }
 122
 123         return dal_gpio_service_create_irq(gpio_service,
 124                                            pin_info.offset,
 125                                            pin_info.mask);
 126 }
 127
 128 /*
 129  *  Function: program_hpd_filter
 130  *
 131  *  @brief
 132  *     Programs HPD filter on associated HPD line
 133  *
 134  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 135  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 136  *
 137  *  @return
 138  *     true on success, false otherwise
 139  */
 140 static bool program_hpd_filter(const struct dc_link *link)
 141 {
 142         bool result = false;
 143         struct gpio *hpd;
 144         int delay_on_connect_in_ms = 0;
 145         int delay_on_disconnect_in_ms = 0;
 146
 147         if (link->is_hpd_filter_disabled)
 148                 return false;
 149         /* Verify feature is supported */
 150         switch (link->connector_signal) {
 151         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 152         case SIGNAL_TYPE_DVI_DUAL_LINK:
 153         case SIGNAL_TYPE_HDMI_TYPE_A:
 154                 /* Program hpd filter */
 155                 delay_on_connect_in_ms = 500;
 156                 delay_on_disconnect_in_ms = 100;
 157                 break;
 158         case SIGNAL_TYPE_DISPLAY_PORT:
 159         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 160                 /* Program hpd filter to allow DP signal to settle */
 161                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 162                  * only 100ms on DELL U2413
 163                  * 0: some passive dongle still show aux mode instead of i2c
 164                  * 20-50: not enough to hide bouncing HPD with passive dongle.
 165                  * also see intermittent i2c read issues.
 166                  */
 167                 delay_on_connect_in_ms = 80;
 168                 delay_on_disconnect_in_ms = 0;
 169                 break;
 170         case SIGNAL_TYPE_LVDS:
 171         case SIGNAL_TYPE_EDP:
 172         default:
 173                 /* Don't program hpd filter */
 174                 return false;
 175         }
 176
 177         /* Obtain HPD handle */
 178         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 179                            link->ctx->gpio_service);
 180
 181         if (!hpd)
 182                 return result;
 183
 184         /* Setup HPD filtering */
 185         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 186                 struct gpio_hpd_config config;
 187
 188                 config.delay_on_connect = delay_on_connect_in_ms;
 189                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 190
 191                 dal_irq_setup_hpd_filter(hpd, &config);
 192
 193                 dal_gpio_close(hpd);
 194
 195                 result = true;
 196         } else {
 197                 ASSERT_CRITICAL(false);
 198         }
 199
 200         /* Release HPD handle */
 201         dal_gpio_destroy_irq(&hpd);
 202
 203         return result;
 204 }
 205
 206 bool dc_link_wait_for_t12(struct dc_link *link)
 207 {
 208         if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 209                 link->dc->hwss.edp_wait_for_T12(link);
 210
 211                 return true;
 212         }
 213
 214         return false;
 215 }
 216
 217 /**
 218  * dc_link_detect_sink() - Determine if there is a sink connected
 219  *
 220  * @link: pointer to the dc link
 221  * @type: Returned connection type
 222  * Does not detect downstream devices, such as MST sinks
 223  * or display connected through active dongles
 224  */
 225 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 226 {
 227         uint32_t is_hpd_high = 0;
 228         struct gpio *hpd_pin;
 229
 230         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 231                 *type = dc_connection_single;
 232                 return true;
 233         }
 234
 235         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 236                 /*in case it is not on*/
 237                 link->dc->hwss.edp_power_control(link, true);
 238                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 239         }
 240
 241         /* todo: may need to lock gpio access */
 242         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 243                                link->ctx->gpio_service);
 244         if (!hpd_pin)
 245                 goto hpd_gpio_failure;
 246
 247         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 248         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 249         dal_gpio_close(hpd_pin);
 250         dal_gpio_destroy_irq(&hpd_pin);
 251
 252         if (is_hpd_high) {
 253                 *type = dc_connection_single;
 254                 /* TODO: need to do the actual detection */
 255         } else {
 256                 *type = dc_connection_none;
 257         }
 258
 259         return true;
 260
 261 hpd_gpio_failure:
 262         return false;
 263 }
 264
 265 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 266 {
 267         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 268
 269         switch (sink_signal) {
 270         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 271         case SIGNAL_TYPE_DVI_DUAL_LINK:
 272         case SIGNAL_TYPE_HDMI_TYPE_A:
 273         case SIGNAL_TYPE_LVDS:
 274         case SIGNAL_TYPE_RGB:
 275                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 276                 break;
 277
 278         case SIGNAL_TYPE_DISPLAY_PORT:
 279         case SIGNAL_TYPE_EDP:
 280                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 281                 break;
 282
 283         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 284                 /* MST does not use I2COverAux, but there is the
 285                  * SPECIAL use case for "immediate dwnstrm device
 286                  * access" (EPR#370830).
 287                  */
 288                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 289                 break;
 290
 291         default:
 292                 break;
 293         }
 294
 295         return transaction_type;
 296 }
 297
 298 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 299                                               struct graphics_object_id downstream)
 300 {
 301         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 302                 switch (downstream.id) {
 303                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 304                         switch (encoder.id) {
 305                         case ENCODER_ID_INTERNAL_DAC1:
 306                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 307                         case ENCODER_ID_INTERNAL_DAC2:
 308                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 309                                 return SIGNAL_TYPE_RGB;
 310                         default:
 311                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 312                         }
 313                 break;
 314                 case CONNECTOR_ID_DUAL_LINK_DVII:
 315                 {
 316                         switch (encoder.id) {
 317                         case ENCODER_ID_INTERNAL_DAC1:
 318                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 319                         case ENCODER_ID_INTERNAL_DAC2:
 320                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 321                                 return SIGNAL_TYPE_RGB;
 322                         default:
 323                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 324                         }
 325                 }
 326                 break;
 327                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 328                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 329                 case CONNECTOR_ID_DUAL_LINK_DVID:
 330                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 331                 case CONNECTOR_ID_VGA:
 332                         return SIGNAL_TYPE_RGB;
 333                 case CONNECTOR_ID_HDMI_TYPE_A:
 334                         return SIGNAL_TYPE_HDMI_TYPE_A;
 335                 case CONNECTOR_ID_LVDS:
 336                         return SIGNAL_TYPE_LVDS;
 337                 case CONNECTOR_ID_DISPLAY_PORT:
 338                         return SIGNAL_TYPE_DISPLAY_PORT;
 339                 case CONNECTOR_ID_EDP:
 340                         return SIGNAL_TYPE_EDP;
 341                 default:
 342                         return SIGNAL_TYPE_NONE;
 343                 }
 344         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 345                 switch (downstream.id) {
 346                 case ENCODER_ID_EXTERNAL_NUTMEG:
 347                 case ENCODER_ID_EXTERNAL_TRAVIS:
 348                         return SIGNAL_TYPE_DISPLAY_PORT;
 349                 default:
 350                         return SIGNAL_TYPE_NONE;
 351                 }
 352         }
 353
 354         return SIGNAL_TYPE_NONE;
 355 }
 356
 357 /*
 358  * dc_link_is_dp_sink_present() - Check if there is a native DP
 359  * or passive DP-HDMI dongle connected
 360  */
 361 bool dc_link_is_dp_sink_present(struct dc_link *link)
 362 {
 363         enum gpio_result gpio_result;
 364         uint32_t clock_pin = 0;
 365         uint8_t retry = 0;
 366         struct ddc *ddc;
 367
 368         enum connector_id connector_id =
 369                 dal_graphics_object_id_get_connector_id(link->link_id);
 370
 371         bool present =
 372                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 373                 (connector_id == CONNECTOR_ID_EDP));
 374
 375         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 376
 377         if (!ddc) {
 378                 BREAK_TO_DEBUGGER();
 379                 return present;
 380         }
 381
 382         /* Open GPIO and set it to I2C mode */
 383         /* Note: this GpioMode_Input will be converted
 384          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 385          * which indicates we need additional delay
 386          */
 387
 388         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 389                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 390                 dal_ddc_close(ddc);
 391
 392                 return present;
 393         }
 394
 395         /*
 396          * Read GPIO: DP sink is present if both clock and data pins are zero
 397          *
 398          * [W/A] plug-unplug DP cable, sometimes customer board has
 399          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 400          * then monitor can't br light up. Add retry 3 times
 401          * But in real passive dongle, it need additional 3ms to detect
 402          */
 403         do {
 404                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 405                 ASSERT(gpio_result == GPIO_RESULT_OK);
 406                 if (clock_pin)
 407                         udelay(1000);
 408                 else
 409                         break;
 410         } while (retry++ < 3);
 411
 412         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 413
 414         dal_ddc_close(ddc);
 415
 416         return present;
 417 }
 418
 419 /*
 420  * @brief
 421  * Detect output sink type
 422  */
 423 static enum signal_type link_detect_sink(struct dc_link *link,
 424                                          enum dc_detect_reason reason)
 425 {
 426         enum signal_type result = get_basic_signal_type(link->link_enc->id,
 427                                                         link->link_id);
 428
 429         /* Internal digital encoder will detect only dongles
 430          * that require digital signal
 431          */
 432
 433         /* Detection mechanism is different
 434          * for different native connectors.
 435          * LVDS connector supports only LVDS signal;
 436          * PCIE is a bus slot, the actual connector needs to be detected first;
 437          * eDP connector supports only eDP signal;
 438          * HDMI should check straps for audio
 439          */
 440
 441         /* PCIE detects the actual connector on add-on board */
 442         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 443                 /* ZAZTODO implement PCIE add-on card detection */
 444         }
 445
 446         switch (link->link_id.id) {
 447         case CONNECTOR_ID_HDMI_TYPE_A: {
 448                 /* check audio support:
 449                  * if native HDMI is not supported, switch to DVI
 450                  */
 451                 struct audio_support *aud_support =
 452                                         &link->dc->res_pool->audio_support;
 453
 454                 if (!aud_support->hdmi_audio_native)
 455                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 456                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 457         }
 458         break;
 459         case CONNECTOR_ID_DISPLAY_PORT: {
 460                 /* DP HPD short pulse. Passive DP dongle will not
 461                  * have short pulse
 462                  */
 463                 if (reason != DETECT_REASON_HPDRX) {
 464                         /* Check whether DP signal detected: if not -
 465                          * we assume signal is DVI; it could be corrected
 466                          * to HDMI after dongle detection
 467                          */
 468                         if (!dm_helpers_is_dp_sink_present(link))
 469                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 470                 }
 471         }
 472         break;
 473         default:
 474         break;
 475         }
 476
 477         return result;
 478 }
 479
 480 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 481                                                                  struct audio_support *audio_support)
 482 {
 483         enum signal_type signal = SIGNAL_TYPE_NONE;
 484
 485         switch (dongle_type) {
 486         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 487                 if (audio_support->hdmi_audio_on_dongle)
 488                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 489                 else
 490                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 491                 break;
 492         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 493                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 494                 break;
 495         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 496                 if (audio_support->hdmi_audio_native)
 497                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 498                 else
 499                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 500                 break;
 501         default:
 502                 signal = SIGNAL_TYPE_NONE;
 503                 break;
 504         }
 505
 506         return signal;
 507 }
 508
 509 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 510                                                     struct display_sink_capability *sink_cap,
 511                                                     struct audio_support *audio_support)
 512 {
 513         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 514
 515         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 516                                                         audio_support);
 517 }
 518
 519 static void link_disconnect_sink(struct dc_link *link)
 520 {
 521         if (link->local_sink) {
 522                 dc_sink_release(link->local_sink);
 523                 link->local_sink = NULL;
 524         }
 525
 526         link->dpcd_sink_count = 0;
 527 }
 528
 529 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 530 {
 531         dc_sink_release(link->local_sink);
 532         link->local_sink = prev_sink;
 533 }
 534
 535 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 536 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 537 {
 538         bool ret = false;
 539
 540         switch (signal) {
 541         case SIGNAL_TYPE_DISPLAY_PORT:
 542         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 543                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 544                 break;
 545         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 546         case SIGNAL_TYPE_DVI_DUAL_LINK:
 547         case SIGNAL_TYPE_HDMI_TYPE_A:
 548         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 549          * we can poll for bksv but some displays have an issue with this. Since its so rare
 550          * for a display to not be 1.4 capable, this assumtion is ok
 551          */
 552                 ret = true;
 553                 break;
 554         default:
 555                 break;
 556         }
 557         return ret;
 558 }
 559
 560 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 561 {
 562         bool ret = false;
 563
 564         switch (signal) {
 565         case SIGNAL_TYPE_DISPLAY_PORT:
 566         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 567                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 568                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 569                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 570                 break;
 571         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 572         case SIGNAL_TYPE_DVI_DUAL_LINK:
 573         case SIGNAL_TYPE_HDMI_TYPE_A:
 574                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 575                 break;
 576         default:
 577                 break;
 578         }
 579
 580         return ret;
 581 }
 582
 583 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 584 {
 585         struct hdcp_protection_message msg22;
 586         struct hdcp_protection_message msg14;
 587
 588         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 589         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 590         memset(link->hdcp_caps.rx_caps.raw, 0,
 591                 sizeof(link->hdcp_caps.rx_caps.raw));
 592
 593         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 594                         link->ddc->transaction_type ==
 595                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 596                         link->connector_signal == SIGNAL_TYPE_EDP) {
 597                 msg22.data = link->hdcp_caps.rx_caps.raw;
 598                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 599                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 600         } else {
 601                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 602                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 603                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 604         }
 605         msg22.version = HDCP_VERSION_22;
 606         msg22.link = HDCP_LINK_PRIMARY;
 607         msg22.max_retries = 5;
 608         dc_process_hdcp_msg(signal, link, &msg22);
 609
 610         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 611                 msg14.data = &link->hdcp_caps.bcaps.raw;
 612                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 613                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 614                 msg14.version = HDCP_VERSION_14;
 615                 msg14.link = HDCP_LINK_PRIMARY;
 616                 msg14.max_retries = 5;
 617
 618                 dc_process_hdcp_msg(signal, link, &msg14);
 619         }
 620
 621 }
 622 #endif
 623
 624 static void read_current_link_settings_on_detect(struct dc_link *link)
 625 {
 626         union lane_count_set lane_count_set = { {0} };
 627         uint8_t link_bw_set;
 628         uint8_t link_rate_set;
 629         uint32_t read_dpcd_retry_cnt = 10;
 630         enum dc_status status = DC_ERROR_UNEXPECTED;
 631         int i;
 632         union max_down_spread max_down_spread = { {0} };
 633
 634         // Read DPCD 00101h to find out the number of lanes currently set
 635         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 636                 status = core_link_read_dpcd(link,
 637                                              DP_LANE_COUNT_SET,
 638                                              &lane_count_set.raw,
 639                                              sizeof(lane_count_set));
 640                 /* First DPCD read after VDD ON can fail if the particular board
 641                  * does not have HPD pin wired correctly. So if DPCD read fails,
 642                  * which it should never happen, retry a few times. Target worst
 643                  * case scenario of 80 ms.
 644                  */
 645                 if (status == DC_OK) {
 646                         link->cur_link_settings.lane_count =
 647                                         lane_count_set.bits.LANE_COUNT_SET;
 648                         break;
 649                 }
 650
 651                 msleep(8);
 652         }
 653
 654         // Read DPCD 00100h to find if standard link rates are set
 655         core_link_read_dpcd(link, DP_LINK_BW_SET,
 656                             &link_bw_set, sizeof(link_bw_set));
 657
 658         if (link_bw_set == 0) {
 659                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 660                         /* If standard link rates are not being used,
 661                          * Read DPCD 00115h to find the edp link rate set used
 662                          */
 663                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 664                                             &link_rate_set, sizeof(link_rate_set));
 665
 666                         // edp_supported_link_rates_count = 0 for DP
 667                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 668                                 link->cur_link_settings.link_rate =
 669                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 670                                 link->cur_link_settings.link_rate_set = link_rate_set;
 671                                 link->cur_link_settings.use_link_rate_set = true;
 672                         }
 673                 } else {
 674                         // Link Rate not found. Seamless boot may not work.
 675                         ASSERT(false);
 676                 }
 677         } else {
 678                 link->cur_link_settings.link_rate = link_bw_set;
 679                 link->cur_link_settings.use_link_rate_set = false;
 680         }
 681         // Read DPCD 00003h to find the max down spread.
 682         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 683                             &max_down_spread.raw, sizeof(max_down_spread));
 684         link->cur_link_settings.link_spread =
 685                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 686                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 687 }
 688
 689 static bool detect_dp(struct dc_link *link,
 690                       struct display_sink_capability *sink_caps,
 691                       bool *converter_disable_audio,
 692                       struct audio_support *audio_support,
 693                       enum dc_detect_reason reason)
 694 {
 695         bool boot = false;
 696
 697         sink_caps->signal = link_detect_sink(link, reason);
 698         sink_caps->transaction_type =
 699                 get_ddc_transaction_type(sink_caps->signal);
 700
 701         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 702                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 703                 if (!detect_dp_sink_caps(link))
 704                         return false;
 705                 if (is_mst_supported(link)) {
 706                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 707                         link->type = dc_connection_mst_branch;
 708
 709                         dal_ddc_service_set_transaction_type(link->ddc,
 710                                                              sink_caps->transaction_type);
 711
 712 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 713                         /* In case of fallback to SST when topology discovery below fails
 714                          * HDCP caps will be querried again later by the upper layer (caller
 715                          * of this function). */
 716                         query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
 717 #endif
 718                         /*
 719                          * This call will initiate MST topology discovery. Which
 720                          * will detect MST ports and add new DRM connector DRM
 721                          * framework. Then read EDID via remote i2c over aux. In
 722                          * the end, will notify DRM detect result and save EDID
 723                          * into DRM framework.
 724                          *
 725                          * .detect is called by .fill_modes.
 726                          * .fill_modes is called by user mode ioctl
 727                          * DRM_IOCTL_MODE_GETCONNECTOR.
 728                          *
 729                          * .get_modes is called by .fill_modes.
 730                          *
 731                          * call .get_modes, AMDGPU DM implementation will create
 732                          * new dc_sink and add to dc_link. For long HPD plug
 733                          * in/out, MST has its own handle.
 734                          *
 735                          * Therefore, just after dc_create, link->sink is not
 736                          * created for MST until user mode app calls
 737                          * DRM_IOCTL_MODE_GETCONNECTOR.
 738                          *
 739                          * Need check ->sink usages in case ->sink = NULL
 740                          * TODO: s3 resume check
 741                          */
 742                         if (reason == DETECT_REASON_BOOT)
 743                                 boot = true;
 744
 745                         dm_helpers_dp_update_branch_info(link->ctx, link);
 746
 747                         if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
 748                                                              link, boot)) {
 749                                 /* MST not supported */
 750                                 link->type = dc_connection_single;
 751                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 752                         }
 753                 }
 754
 755                 if (link->type != dc_connection_mst_branch &&
 756                     is_dp_active_dongle(link)) {
 757                         /* DP active dongles */
 758                         link->type = dc_connection_active_dongle;
 759                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 760                                 /*
 761                                  * active dongle unplug processing for short irq
 762                                  */
 763                                 link_disconnect_sink(link);
 764                                 return true;
 765                         }
 766
 767                         if (link->dpcd_caps.dongle_type !=
 768                             DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 769                                 *converter_disable_audio = true;
 770                 }
 771         } else {
 772                 /* DP passive dongles */
 773                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 774                                                                 sink_caps,
 775                                                                 audio_support);
 776                 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 777         }
 778
 779         return true;
 780 }
 781
 782 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 783 {
 784         if (old_edid->length != new_edid->length)
 785                 return false;
 786
 787         if (new_edid->length == 0)
 788                 return false;
 789
 790         return (memcmp(old_edid->raw_edid,
 791                        new_edid->raw_edid, new_edid->length) == 0);
 792 }
 793
 794 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 795 {
 796         /**
 797          * something is terribly wrong if time out is > 200ms. (5Hz)
 798          * 500 microseconds * 400 tries us 200 ms
 799          **/
 800         unsigned int sleep_time_in_microseconds = 500;
 801         unsigned int tries_allowed = 400;
 802         bool is_in_alt_mode;
 803         unsigned long long enter_timestamp;
 804         unsigned long long finish_timestamp;
 805         unsigned long long time_taken_in_ns;
 806         int tries_taken;
 807
 808         DC_LOGGER_INIT(link->ctx->logger);
 809
 810         if (!link->link_enc->funcs->is_in_alt_mode)
 811                 return true;
 812
 813         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 814         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 815
 816         if (is_in_alt_mode)
 817                 return true;
 818
 819         enter_timestamp = dm_get_timestamp(link->ctx);
 820
 821         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 822                 udelay(sleep_time_in_microseconds);
 823                 /* ask the link if alt mode is enabled, if so return ok */
 824                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 825                         finish_timestamp = dm_get_timestamp(link->ctx);
 826                         time_taken_in_ns =
 827                                 dm_get_elapse_time_in_ns(link->ctx,
 828                                                          finish_timestamp,
 829                                                          enter_timestamp);
 830                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 831                                        div_u64(time_taken_in_ns, 1000000));
 832                         return true;
 833                 }
 834         }
 835         finish_timestamp = dm_get_timestamp(link->ctx);
 836         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 837                                                     enter_timestamp);
 838         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 839                        div_u64(time_taken_in_ns, 1000000));
 840         return false;
 841 }
 842
 843 /*
 844  * dc_link_detect() - Detect if a sink is attached to a given link
 845  *
 846  * link->local_sink is created or destroyed as needed.
 847  *
 848  * This does not create remote sinks but will trigger DM
 849  * to start MST detection if a branch is detected.
 850  */
 851 static bool dc_link_detect_helper(struct dc_link *link,
 852                                   enum dc_detect_reason reason)
 853 {
 854         struct dc_sink_init_data sink_init_data = { 0 };
 855         struct display_sink_capability sink_caps = { 0 };
 856         uint8_t i;
 857         bool converter_disable_audio = false;
 858         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 859         bool same_edid = false;
 860         enum dc_edid_status edid_status;
 861         struct dc_context *dc_ctx = link->ctx;
 862         struct dc_sink *sink = NULL;
 863         struct dc_sink *prev_sink = NULL;
 864         struct dpcd_caps prev_dpcd_caps;
 865         bool same_dpcd = true;
 866         enum dc_connection_type new_connection_type = dc_connection_none;
 867         enum dc_connection_type pre_connection_type = dc_connection_none;
 868         bool perform_dp_seamless_boot = false;
 869         const uint32_t post_oui_delay = 30; // 30ms
 870
 871         DC_LOGGER_INIT(link->ctx->logger);
 872
 873         if (dc_is_virtual_signal(link->connector_signal))
 874                 return false;
 875
 876         if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
 877              link->connector_signal == SIGNAL_TYPE_EDP) &&
 878             link->local_sink) {
 879                 // need to re-write OUI and brightness in resume case
 880                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 881                         dpcd_set_source_specific_data(link);
 882                         msleep(post_oui_delay);
 883                         dc_link_set_default_brightness_aux(link);
 884                         //TODO: use cached
 885                 }
 886
 887                 return true;
 888         }
 889
 890         if (!dc_link_detect_sink(link, &new_connection_type)) {
 891                 BREAK_TO_DEBUGGER();
 892                 return false;
 893         }
 894
 895         prev_sink = link->local_sink;
 896         if (prev_sink) {
 897                 dc_sink_retain(prev_sink);
 898                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 899         }
 900
 901         link_disconnect_sink(link);
 902         if (new_connection_type != dc_connection_none) {
 903                 pre_connection_type = link->type;
 904                 link->type = new_connection_type;
 905                 link->link_state_valid = false;
 906
 907                 /* From Disconnected-to-Connected. */
 908                 switch (link->connector_signal) {
 909                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 910                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 911                         if (aud_support->hdmi_audio_native)
 912                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 913                         else
 914                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 915                         break;
 916                 }
 917
 918                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 919                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 920                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 921                         break;
 922                 }
 923
 924                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 925                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 926                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 927                         break;
 928                 }
 929
 930                 case SIGNAL_TYPE_LVDS: {
 931                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 932                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 933                         break;
 934                 }
 935
 936                 case SIGNAL_TYPE_EDP: {
 937                         read_current_link_settings_on_detect(link);
 938
 939                         detect_edp_sink_caps(link);
 940                         read_current_link_settings_on_detect(link);
 941                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 942                         sink_caps.signal = SIGNAL_TYPE_EDP;
 943                         break;
 944                 }
 945
 946                 case SIGNAL_TYPE_DISPLAY_PORT: {
 947                         /* wa HPD high coming too early*/
 948                         if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 949                                 /* if alt mode times out, return false */
 950                                 if (!wait_for_entering_dp_alt_mode(link))
 951                                         return false;
 952                         }
 953
 954                         if (!detect_dp(link, &sink_caps,
 955                                        &converter_disable_audio,
 956                                        aud_support, reason)) {
 957                                 if (prev_sink)
 958                                         dc_sink_release(prev_sink);
 959                                 return false;
 960                         }
 961
 962                         // Check if dpcp block is the same
 963                         if (prev_sink) {
 964                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps,
 965                                            sizeof(struct dpcd_caps)))
 966                                         same_dpcd = false;
 967                         }
 968                         /* Active dongle downstream unplug*/
 969                         if (link->type == dc_connection_active_dongle &&
 970                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 971                                 if (prev_sink)
 972                                         /* Downstream unplug */
 973                                         dc_sink_release(prev_sink);
 974                                 return true;
 975                         }
 976
 977                         // link switch from MST to non-MST stop topology manager
 978                         if (pre_connection_type == dc_connection_mst_branch &&
 979                                 link->type != dc_connection_mst_branch) {
 980                                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 981                         }
 982
 983                         if (link->type == dc_connection_mst_branch) {
 984                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 985                                           link->link_index);
 986                                 /* Need to setup mst link_cap struct here
 987                                  * otherwise dc_link_detect() will leave mst link_cap
 988                                  * empty which leads to allocate_mst_payload() has "0"
 989                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 990                                  */
 991                                 dp_verify_mst_link_cap(link);
 992
 993                                 if (prev_sink)
 994                                         dc_sink_release(prev_sink);
 995                                 return false;
 996                         }
 997
 998                         // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
 999                         if (reason == DETECT_REASON_BOOT &&
1000                             !dc_ctx->dc->config.power_down_display_on_boot &&
1001                             link->link_status.link_active)
1002                                 perform_dp_seamless_boot = true;
1003
1004                         if (perform_dp_seamless_boot) {
1005                                 read_current_link_settings_on_detect(link);
1006                                 link->verified_link_cap = link->reported_link_cap;
1007                         }
1008
1009                         break;
1010                 }
1011
1012                 default:
1013                         DC_ERROR("Invalid connector type! signal:%d\n",
1014                                  link->connector_signal);
1015                         if (prev_sink)
1016                                 dc_sink_release(prev_sink);
1017                         return false;
1018                 } /* switch() */
1019
1020                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1021                         link->dpcd_sink_count =
1022                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1023                 else
1024                         link->dpcd_sink_count = 1;
1025
1026                 dal_ddc_service_set_transaction_type(link->ddc,
1027                                                      sink_caps.transaction_type);
1028
1029                 link->aux_mode =
1030                         dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1031
1032                 sink_init_data.link = link;
1033                 sink_init_data.sink_signal = sink_caps.signal;
1034
1035                 sink = dc_sink_create(&sink_init_data);
1036                 if (!sink) {
1037                         DC_ERROR("Failed to create sink!\n");
1038                         if (prev_sink)
1039                                 dc_sink_release(prev_sink);
1040                         return false;
1041                 }
1042
1043                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1044                 sink->converter_disable_audio = converter_disable_audio;
1045
1046                 /* dc_sink_create returns a new reference */
1047                 link->local_sink = sink;
1048
1049                 edid_status = dm_helpers_read_local_edid(link->ctx,
1050                                                          link, sink);
1051
1052                 switch (edid_status) {
1053                 case EDID_BAD_CHECKSUM:
1054                         DC_LOG_ERROR("EDID checksum invalid.\n");
1055                         break;
1056                 case EDID_NO_RESPONSE:
1057                         DC_LOG_ERROR("No EDID read.\n");
1058                         /*
1059                          * Abort detection for non-DP connectors if we have
1060                          * no EDID
1061                          *
1062                          * DP needs to report as connected if HDP is high
1063                          * even if we have no EDID in order to go to
1064                          * fail-safe mode
1065                          */
1066                         if (dc_is_hdmi_signal(link->connector_signal) ||
1067                             dc_is_dvi_signal(link->connector_signal)) {
1068                                 if (prev_sink)
1069                                         dc_sink_release(prev_sink);
1070
1071                                 return false;
1072                         }
1073                         break;
1074                 default:
1075                         break;
1076                 }
1077
1078                 // Check if edid is the same
1079                 if ((prev_sink) &&
1080                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1081                         same_edid = is_same_edid(&prev_sink->dc_edid,
1082                                                  &sink->dc_edid);
1083
1084                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1085                         link->ctx->dc->debug.hdmi20_disable = true;
1086
1087                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1088                     sink_caps.transaction_type ==
1089                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1090                         /*
1091                          * TODO debug why Dell 2413 doesn't like
1092                          *  two link trainings
1093                          */
1094 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1095                         query_hdcp_capability(sink->sink_signal, link);
1096 #endif
1097
1098                         // verify link cap for SST non-seamless boot
1099                         if (!perform_dp_seamless_boot)
1100                                 dp_verify_link_cap_with_retries(link,
1101                                                                 &link->reported_link_cap,
1102                                                                 LINK_TRAINING_MAX_VERIFY_RETRY);
1103                 } else {
1104                         // If edid is the same, then discard new sink and revert back to original sink
1105                         if (same_edid) {
1106                                 link_disconnect_remap(prev_sink, link);
1107                                 sink = prev_sink;
1108                                 prev_sink = NULL;
1109                         }
1110 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1111                         query_hdcp_capability(sink->sink_signal, link);
1112 #endif
1113                 }
1114
1115                 /* HDMI-DVI Dongle */
1116                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1117                     !sink->edid_caps.edid_hdmi)
1118                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1119
1120                 /* Connectivity log: detection */
1121                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1122                         CONN_DATA_DETECT(link,
1123                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1124                                          DC_EDID_BLOCK_SIZE,
1125                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1126                 }
1127
1128                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1129                         "manufacturer_id = %X, "
1130                         "product_id = %X, "
1131                         "serial_number = %X, "
1132                         "manufacture_week = %d, "
1133                         "manufacture_year = %d, "
1134                         "display_name = %s, "
1135                         "speaker_flag = %d, "
1136                         "audio_mode_count = %d\n",
1137                         __func__,
1138                         sink->edid_caps.manufacturer_id,
1139                         sink->edid_caps.product_id,
1140                         sink->edid_caps.serial_number,
1141                         sink->edid_caps.manufacture_week,
1142                         sink->edid_caps.manufacture_year,
1143                         sink->edid_caps.display_name,
1144                         sink->edid_caps.speaker_flags,
1145                         sink->edid_caps.audio_mode_count);
1146
1147                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1148                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1149                                 "format_code = %d, "
1150                                 "channel_count = %d, "
1151                                 "sample_rate = %d, "
1152                                 "sample_size = %d\n",
1153                                 __func__,
1154                                 i,
1155                                 sink->edid_caps.audio_modes[i].format_code,
1156                                 sink->edid_caps.audio_modes[i].channel_count,
1157                                 sink->edid_caps.audio_modes[i].sample_rate,
1158                                 sink->edid_caps.audio_modes[i].sample_size);
1159                 }
1160         } else {
1161                 /* From Connected-to-Disconnected. */
1162                 if (link->type == dc_connection_mst_branch) {
1163                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
1164                                   link->link_index);
1165
1166                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1167
1168                         link->mst_stream_alloc_table.stream_count = 0;
1169                         memset(link->mst_stream_alloc_table.stream_allocations,
1170                                0,
1171                                sizeof(link->mst_stream_alloc_table.stream_allocations));
1172                 }
1173
1174                 link->type = dc_connection_none;
1175                 sink_caps.signal = SIGNAL_TYPE_NONE;
1176                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1177                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1178                  *  the dongle is still there and limits the number of modes we can emulate.
1179                  *  Clear dongle_max_pix_clk on disconnect to fix this
1180                  */
1181                 link->dongle_max_pix_clk = 0;
1182         }
1183
1184         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
1185                   link->link_index, sink,
1186                   (sink_caps.signal ==
1187                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1188                   prev_sink, same_dpcd, same_edid);
1189
1190         if (prev_sink)
1191                 dc_sink_release(prev_sink);
1192
1193         return true;
1194 }
1195
1196 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1197 {
1198         const struct dc *dc = link->dc;
1199         bool ret;
1200
1201         /* get out of low power state */
1202         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1203
1204         ret = dc_link_detect_helper(link, reason);
1205
1206         /* Go back to power optimized state */
1207         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1208
1209         return ret;
1210 }
1211
1212 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1213 {
1214         uint32_t state;
1215
1216         dal_gpio_lock_pin(dc_link->hpd_gpio);
1217         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1218         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1219
1220         return state;
1221 }
1222
1223 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1224 {
1225         struct gpio *hpd;
1226         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1227
1228         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1229                            link->ctx->gpio_service);
1230
1231         if (hpd) {
1232                 switch (dal_irq_get_source(hpd)) {
1233                 case DC_IRQ_SOURCE_HPD1:
1234                         hpd_id = HPD_SOURCEID1;
1235                 break;
1236                 case DC_IRQ_SOURCE_HPD2:
1237                         hpd_id = HPD_SOURCEID2;
1238                 break;
1239                 case DC_IRQ_SOURCE_HPD3:
1240                         hpd_id = HPD_SOURCEID3;
1241                 break;
1242                 case DC_IRQ_SOURCE_HPD4:
1243                         hpd_id = HPD_SOURCEID4;
1244                 break;
1245                 case DC_IRQ_SOURCE_HPD5:
1246                         hpd_id = HPD_SOURCEID5;
1247                 break;
1248                 case DC_IRQ_SOURCE_HPD6:
1249                         hpd_id = HPD_SOURCEID6;
1250                 break;
1251                 default:
1252                         BREAK_TO_DEBUGGER();
1253                 break;
1254                 }
1255
1256                 dal_gpio_destroy_irq(&hpd);
1257         }
1258
1259         return hpd_id;
1260 }
1261
1262 static enum channel_id get_ddc_line(struct dc_link *link)
1263 {
1264         struct ddc *ddc;
1265         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1266
1267         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1268
1269         if (ddc) {
1270                 switch (dal_ddc_get_line(ddc)) {
1271                 case GPIO_DDC_LINE_DDC1:
1272                         channel = CHANNEL_ID_DDC1;
1273                         break;
1274                 case GPIO_DDC_LINE_DDC2:
1275                         channel = CHANNEL_ID_DDC2;
1276                         break;
1277                 case GPIO_DDC_LINE_DDC3:
1278                         channel = CHANNEL_ID_DDC3;
1279                         break;
1280                 case GPIO_DDC_LINE_DDC4:
1281                         channel = CHANNEL_ID_DDC4;
1282                         break;
1283                 case GPIO_DDC_LINE_DDC5:
1284                         channel = CHANNEL_ID_DDC5;
1285                         break;
1286                 case GPIO_DDC_LINE_DDC6:
1287                         channel = CHANNEL_ID_DDC6;
1288                         break;
1289                 case GPIO_DDC_LINE_DDC_VGA:
1290                         channel = CHANNEL_ID_DDC_VGA;
1291                         break;
1292                 case GPIO_DDC_LINE_I2C_PAD:
1293                         channel = CHANNEL_ID_I2C_PAD;
1294                         break;
1295                 default:
1296                         BREAK_TO_DEBUGGER();
1297                         break;
1298                 }
1299         }
1300
1301         return channel;
1302 }
1303
1304 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1305 {
1306         switch (encoder.id) {
1307         case ENCODER_ID_INTERNAL_UNIPHY:
1308                 switch (encoder.enum_id) {
1309                 case ENUM_ID_1:
1310                         return TRANSMITTER_UNIPHY_A;
1311                 case ENUM_ID_2:
1312                         return TRANSMITTER_UNIPHY_B;
1313                 default:
1314                         return TRANSMITTER_UNKNOWN;
1315                 }
1316         break;
1317         case ENCODER_ID_INTERNAL_UNIPHY1:
1318                 switch (encoder.enum_id) {
1319                 case ENUM_ID_1:
1320                         return TRANSMITTER_UNIPHY_C;
1321                 case ENUM_ID_2:
1322                         return TRANSMITTER_UNIPHY_D;
1323                 default:
1324                         return TRANSMITTER_UNKNOWN;
1325                 }
1326         break;
1327         case ENCODER_ID_INTERNAL_UNIPHY2:
1328                 switch (encoder.enum_id) {
1329                 case ENUM_ID_1:
1330                         return TRANSMITTER_UNIPHY_E;
1331                 case ENUM_ID_2:
1332                         return TRANSMITTER_UNIPHY_F;
1333                 default:
1334                         return TRANSMITTER_UNKNOWN;
1335                 }
1336         break;
1337         case ENCODER_ID_INTERNAL_UNIPHY3:
1338                 switch (encoder.enum_id) {
1339                 case ENUM_ID_1:
1340                         return TRANSMITTER_UNIPHY_G;
1341                 default:
1342                         return TRANSMITTER_UNKNOWN;
1343                 }
1344         break;
1345         case ENCODER_ID_EXTERNAL_NUTMEG:
1346                 switch (encoder.enum_id) {
1347                 case ENUM_ID_1:
1348                         return TRANSMITTER_NUTMEG_CRT;
1349                 default:
1350                         return TRANSMITTER_UNKNOWN;
1351                 }
1352         break;
1353         case ENCODER_ID_EXTERNAL_TRAVIS:
1354                 switch (encoder.enum_id) {
1355                 case ENUM_ID_1:
1356                         return TRANSMITTER_TRAVIS_CRT;
1357                 case ENUM_ID_2:
1358                         return TRANSMITTER_TRAVIS_LCD;
1359                 default:
1360                         return TRANSMITTER_UNKNOWN;
1361                 }
1362         break;
1363         default:
1364                 return TRANSMITTER_UNKNOWN;
1365         }
1366 }
1367
1368 static bool dc_link_construct(struct dc_link *link,
1369                               const struct link_init_data *init_params)
1370 {
1371         uint8_t i;
1372         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1373         struct dc_context *dc_ctx = init_params->ctx;
1374         struct encoder_init_data enc_init_data = { 0 };
1375         struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1376         struct integrated_info *info;
1377         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1378         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1379         struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1380
1381         DC_LOGGER_INIT(dc_ctx->logger);
1382
1383         info = kzalloc(sizeof(*info), GFP_KERNEL);
1384         if (!info)
1385                 goto create_fail;
1386
1387         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1388         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1389
1390         link->link_status.dpcd_caps = &link->dpcd_caps;
1391
1392         link->dc = init_params->dc;
1393         link->ctx = dc_ctx;
1394         link->link_index = init_params->link_index;
1395
1396         memset(&link->preferred_training_settings, 0,
1397                sizeof(struct dc_link_training_overrides));
1398         memset(&link->preferred_link_setting, 0,
1399                sizeof(struct dc_link_settings));
1400
1401         link->link_id =
1402                 bios->funcs->get_connector_id(bios, init_params->connector_index);
1403
1404         DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1405
1406         if (bios->funcs->get_disp_connector_caps_info) {
1407                 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1408                 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1409                 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1410         }
1411
1412         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1413                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1414                                      __func__, init_params->connector_index,
1415                                      link->link_id.type, OBJECT_TYPE_CONNECTOR);
1416                 goto create_fail;
1417         }
1418
1419         if (link->dc->res_pool->funcs->link_init)
1420                 link->dc->res_pool->funcs->link_init(link);
1421
1422         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1423                                       link->ctx->gpio_service);
1424
1425         if (link->hpd_gpio) {
1426                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1427                 dal_gpio_unlock_pin(link->hpd_gpio);
1428                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1429
1430                 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1431                 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1432         }
1433
1434         switch (link->link_id.id) {
1435         case CONNECTOR_ID_HDMI_TYPE_A:
1436                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1437
1438                 break;
1439         case CONNECTOR_ID_SINGLE_LINK_DVID:
1440         case CONNECTOR_ID_SINGLE_LINK_DVII:
1441                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1442                 break;
1443         case CONNECTOR_ID_DUAL_LINK_DVID:
1444         case CONNECTOR_ID_DUAL_LINK_DVII:
1445                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1446                 break;
1447         case CONNECTOR_ID_DISPLAY_PORT:
1448                 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1449
1450                 if (link->hpd_gpio)
1451                         link->irq_source_hpd_rx =
1452                                         dal_irq_get_rx_source(link->hpd_gpio);
1453
1454                 break;
1455         case CONNECTOR_ID_EDP:
1456                 link->connector_signal = SIGNAL_TYPE_EDP;
1457
1458                 if (link->hpd_gpio) {
1459                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1460                         link->irq_source_hpd_rx =
1461                                         dal_irq_get_rx_source(link->hpd_gpio);
1462                 }
1463
1464                 break;
1465         case CONNECTOR_ID_LVDS:
1466                 link->connector_signal = SIGNAL_TYPE_LVDS;
1467                 break;
1468         default:
1469                 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1470                                link->link_id.id);
1471                 goto create_fail;
1472         }
1473
1474         /* TODO: #DAL3 Implement id to str function.*/
1475         LINK_INFO("Connector[%d] description:"
1476                   "signal %d\n",
1477                   init_params->connector_index,
1478                   link->connector_signal);
1479
1480         ddc_service_init_data.ctx = link->ctx;
1481         ddc_service_init_data.id = link->link_id;
1482         ddc_service_init_data.link = link;
1483         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1484
1485         if (!link->ddc) {
1486                 DC_ERROR("Failed to create ddc_service!\n");
1487                 goto ddc_create_fail;
1488         }
1489
1490         if (!link->ddc->ddc_pin) {
1491                 DC_ERROR("Failed to get I2C info for connector!\n");
1492                 goto ddc_create_fail;
1493         }
1494
1495         link->ddc_hw_inst =
1496                 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1497
1498
1499         if (link->dc->res_pool->funcs->panel_cntl_create &&
1500                 (link->link_id.id == CONNECTOR_ID_EDP ||
1501                         link->link_id.id == CONNECTOR_ID_LVDS)) {
1502                 panel_cntl_init_data.ctx = dc_ctx;
1503                 panel_cntl_init_data.inst = 0;
1504                 link->panel_cntl =
1505                         link->dc->res_pool->funcs->panel_cntl_create(
1506                                                                 &panel_cntl_init_data);
1507
1508                 if (link->panel_cntl == NULL) {
1509                         DC_ERROR("Failed to create link panel_cntl!\n");
1510                         goto panel_cntl_create_fail;
1511                 }
1512         }
1513
1514         enc_init_data.ctx = dc_ctx;
1515         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1516                               &enc_init_data.encoder);
1517         enc_init_data.connector = link->link_id;
1518         enc_init_data.channel = get_ddc_line(link);
1519         enc_init_data.hpd_source = get_hpd_line(link);
1520
1521         link->hpd_src = enc_init_data.hpd_source;
1522
1523         enc_init_data.transmitter =
1524                 translate_encoder_to_transmitter(enc_init_data.encoder);
1525         link->link_enc =
1526                 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1527
1528         if (!link->link_enc) {
1529                 DC_ERROR("Failed to create link encoder!\n");
1530                 goto link_enc_create_fail;
1531         }
1532
1533         DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1534
1535         link->link_enc_hw_inst = link->link_enc->transmitter;
1536
1537         for (i = 0; i < 4; i++) {
1538                 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1539                                              link->link_id, i,
1540                                              &link->device_tag) != BP_RESULT_OK) {
1541                         DC_ERROR("Failed to find device tag!\n");
1542                         goto device_tag_fail;
1543                 }
1544
1545                 /* Look for device tag that matches connector signal,
1546                  * CRT for rgb, LCD for other supported signal tyes
1547                  */
1548                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1549                                                       link->device_tag.dev_id))
1550                         continue;
1551                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1552                     link->connector_signal != SIGNAL_TYPE_RGB)
1553                         continue;
1554                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1555                     link->connector_signal == SIGNAL_TYPE_RGB)
1556                         continue;
1557
1558                 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1559                 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1560                 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1561                 break;
1562         }
1563
1564         if (bios->integrated_info)
1565                 memcpy(info, bios->integrated_info, sizeof(*info));
1566
1567         /* Look for channel mapping corresponding to connector and device tag */
1568         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1569                 struct external_display_path *path =
1570                         &info->ext_disp_conn_info.path[i];
1571
1572                 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1573                     path->device_connector_id.id == link->link_id.id &&
1574                     path->device_connector_id.type == link->link_id.type) {
1575                         if (link->device_tag.acpi_device != 0 &&
1576                             path->device_acpi_enum == link->device_tag.acpi_device) {
1577                                 link->ddi_channel_mapping = path->channel_mapping;
1578                                 link->chip_caps = path->caps;
1579                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1580                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1581                         } else if (path->device_tag ==
1582                                    link->device_tag.dev_id.raw_device_tag) {
1583                                 link->ddi_channel_mapping = path->channel_mapping;
1584                                 link->chip_caps = path->caps;
1585                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1586                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1587                         }
1588                         break;
1589                 }
1590         }
1591
1592         if (bios->funcs->get_atom_dc_golden_table)
1593                 bios->funcs->get_atom_dc_golden_table(bios);
1594
1595         /*
1596          * TODO check if GPIO programmed correctly
1597          *
1598          * If GPIO isn't programmed correctly HPD might not rise or drain
1599          * fast enough, leading to bounces.
1600          */
1601         program_hpd_filter(link);
1602
1603         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1604
1605         DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1606         return true;
1607 device_tag_fail:
1608         link->link_enc->funcs->destroy(&link->link_enc);
1609 link_enc_create_fail:
1610         if (link->panel_cntl != NULL)
1611                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1612 panel_cntl_create_fail:
1613         dal_ddc_service_destroy(&link->ddc);
1614 ddc_create_fail:
1615 create_fail:
1616
1617         if (link->hpd_gpio) {
1618                 dal_gpio_destroy_irq(&link->hpd_gpio);
1619                 link->hpd_gpio = NULL;
1620         }
1621
1622         DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1623         kfree(info);
1624
1625         return false;
1626 }
1627
1628 /*******************************************************************************
1629  * Public functions
1630  ******************************************************************************/
1631 struct dc_link *link_create(const struct link_init_data *init_params)
1632 {
1633         struct dc_link *link =
1634                         kzalloc(sizeof(*link), GFP_KERNEL);
1635
1636         if (NULL == link)
1637                 goto alloc_fail;
1638
1639         if (false == dc_link_construct(link, init_params))
1640                 goto construct_fail;
1641
1642         return link;
1643
1644 construct_fail:
1645         kfree(link);
1646
1647 alloc_fail:
1648         return NULL;
1649 }
1650
1651 void link_destroy(struct dc_link **link)
1652 {
1653         dc_link_destruct(*link);
1654         kfree(*link);
1655         *link = NULL;
1656 }
1657
1658 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1659 {
1660         struct dc_stream_state *stream = pipe_ctx->stream;
1661         struct dc_link *link = stream->link;
1662         union down_spread_ctrl old_downspread;
1663         union down_spread_ctrl new_downspread;
1664
1665         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1666                         &old_downspread.raw, sizeof(old_downspread));
1667
1668         new_downspread.raw = old_downspread.raw;
1669
1670         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1671                         (stream->ignore_msa_timing_param) ? 1 : 0;
1672
1673         if (new_downspread.raw != old_downspread.raw) {
1674                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1675                         &new_downspread.raw, sizeof(new_downspread));
1676         }
1677 }
1678
1679 static enum dc_status enable_link_dp(struct dc_state *state,
1680                                      struct pipe_ctx *pipe_ctx)
1681 {
1682         struct dc_stream_state *stream = pipe_ctx->stream;
1683         enum dc_status status;
1684         bool skip_video_pattern;
1685         struct dc_link *link = stream->link;
1686         struct dc_link_settings link_settings = {0};
1687         bool fec_enable;
1688         int i;
1689         bool apply_seamless_boot_optimization = false;
1690         uint32_t bl_oled_enable_delay = 50; // in ms
1691         const uint32_t post_oui_delay = 30; // 30ms
1692
1693         // check for seamless boot
1694         for (i = 0; i < state->stream_count; i++) {
1695                 if (state->streams[i]->apply_seamless_boot_optimization) {
1696                         apply_seamless_boot_optimization = true;
1697                         break;
1698                 }
1699         }
1700
1701         /* get link settings for video mode timing */
1702         decide_link_settings(stream, &link_settings);
1703
1704         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1705                 /*in case it is not on*/
1706                 link->dc->hwss.edp_power_control(link, true);
1707                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1708         }
1709
1710         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1711                         link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1712         if (state->clk_mgr && !apply_seamless_boot_optimization)
1713                 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1714                                                      state, false);
1715
1716         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1717         dpcd_set_source_specific_data(link);
1718         if (link->dpcd_sink_ext_caps.raw != 0)
1719                 msleep(post_oui_delay);
1720
1721         skip_video_pattern = true;
1722
1723         if (link_settings.link_rate == LINK_RATE_LOW)
1724                 skip_video_pattern = false;
1725
1726         if (perform_link_training_with_retries(&link_settings,
1727                                                skip_video_pattern,
1728                                                LINK_TRAINING_ATTEMPTS,
1729                                                pipe_ctx,
1730                                                pipe_ctx->stream->signal)) {
1731                 link->cur_link_settings = link_settings;
1732                 status = DC_OK;
1733         } else {
1734                 status = DC_FAIL_DP_LINK_TRAINING;
1735         }
1736
1737         if (link->preferred_training_settings.fec_enable)
1738                 fec_enable = *link->preferred_training_settings.fec_enable;
1739         else
1740                 fec_enable = true;
1741
1742         dp_set_fec_enable(link, fec_enable);
1743
1744         // during mode set we do DP_SET_POWER off then on, aux writes are lost
1745         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
1746                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
1747                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
1748                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
1749                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
1750                         msleep(bl_oled_enable_delay);
1751                 dc_link_backlight_enable_aux(link, true);
1752         }
1753
1754         return status;
1755 }
1756
1757 static enum dc_status enable_link_edp(
1758                 struct dc_state *state,
1759                 struct pipe_ctx *pipe_ctx)
1760 {
1761         enum dc_status status;
1762
1763         status = enable_link_dp(state, pipe_ctx);
1764
1765         return status;
1766 }
1767
1768 static enum dc_status enable_link_dp_mst(
1769                 struct dc_state *state,
1770                 struct pipe_ctx *pipe_ctx)
1771 {
1772         struct dc_link *link = pipe_ctx->stream->link;
1773
1774         /* sink signal type after MST branch is MST. Multiple MST sinks
1775          * share one link. Link DP PHY is enable or training only once.
1776          */
1777         if (link->link_status.link_active)
1778                 return DC_OK;
1779
1780         /* clear payload table */
1781         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1782
1783         /* to make sure the pending down rep can be processed
1784          * before enabling the link
1785          */
1786         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1787
1788         /* set the sink to MST mode before enabling the link */
1789         dp_enable_mst_on_sink(link, true);
1790
1791         return enable_link_dp(state, pipe_ctx);
1792 }
1793
1794 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1795                 enum engine_id eng_id,
1796                 struct ext_hdmi_settings *settings)
1797 {
1798         bool result = false;
1799         int i = 0;
1800         struct integrated_info *integrated_info =
1801                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1802
1803         if (integrated_info == NULL)
1804                 return false;
1805
1806         /*
1807          * Get retimer settings from sbios for passing SI eye test for DCE11
1808          * The setting values are varied based on board revision and port id
1809          * Therefore the setting values of each ports is passed by sbios.
1810          */
1811
1812         // Check if current bios contains ext Hdmi settings
1813         if (integrated_info->gpu_cap_info & 0x20) {
1814                 switch (eng_id) {
1815                 case ENGINE_ID_DIGA:
1816                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1817                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1818                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1819                         memmove(settings->reg_settings,
1820                                         integrated_info->dp0_ext_hdmi_reg_settings,
1821                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1822                         memmove(settings->reg_settings_6g,
1823                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1824                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1825                         result = true;
1826                         break;
1827                 case ENGINE_ID_DIGB:
1828                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1829                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1830                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1831                         memmove(settings->reg_settings,
1832                                         integrated_info->dp1_ext_hdmi_reg_settings,
1833                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1834                         memmove(settings->reg_settings_6g,
1835                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1836                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1837                         result = true;
1838                         break;
1839                 case ENGINE_ID_DIGC:
1840                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1841                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1842                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1843                         memmove(settings->reg_settings,
1844                                         integrated_info->dp2_ext_hdmi_reg_settings,
1845                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1846                         memmove(settings->reg_settings_6g,
1847                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1848                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1849                         result = true;
1850                         break;
1851                 case ENGINE_ID_DIGD:
1852                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1853                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1854                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1855                         memmove(settings->reg_settings,
1856                                         integrated_info->dp3_ext_hdmi_reg_settings,
1857                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1858                         memmove(settings->reg_settings_6g,
1859                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1860                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1861                         result = true;
1862                         break;
1863                 default:
1864                         break;
1865                 }
1866
1867                 if (result == true) {
1868                         // Validate settings from bios integrated info table
1869                         if (settings->slv_addr == 0)
1870                                 return false;
1871                         if (settings->reg_num > 9)
1872                                 return false;
1873                         if (settings->reg_num_6g > 3)
1874                                 return false;
1875
1876                         for (i = 0; i < settings->reg_num; i++) {
1877                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1878                                         return false;
1879                         }
1880
1881                         for (i = 0; i < settings->reg_num_6g; i++) {
1882                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1883                                         return false;
1884                         }
1885                 }
1886         }
1887
1888         return result;
1889 }
1890
1891 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1892                 uint8_t address, uint8_t *buffer, uint32_t length)
1893 {
1894         struct i2c_command cmd = {0};
1895         struct i2c_payload payload = {0};
1896
1897         memset(&payload, 0, sizeof(payload));
1898         memset(&cmd, 0, sizeof(cmd));
1899
1900         cmd.number_of_payloads = 1;
1901         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1902         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1903
1904         payload.address = address;
1905         payload.data = buffer;
1906         payload.length = length;
1907         payload.write = true;
1908         cmd.payloads = &payload;
1909
1910         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1911                         pipe_ctx->stream->link, &cmd))
1912                 return true;
1913
1914         return false;
1915 }
1916
1917 static void write_i2c_retimer_setting(
1918                 struct pipe_ctx *pipe_ctx,
1919                 bool is_vga_mode,
1920                 bool is_over_340mhz,
1921                 struct ext_hdmi_settings *settings)
1922 {
1923         uint8_t slave_address = (settings->slv_addr >> 1);
1924         uint8_t buffer[2];
1925         const uint8_t apply_rx_tx_change = 0x4;
1926         uint8_t offset = 0xA;
1927         uint8_t value = 0;
1928         int i = 0;
1929         bool i2c_success = false;
1930         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1931
1932         memset(&buffer, 0, sizeof(buffer));
1933
1934         /* Start Ext-Hdmi programming*/
1935
1936         for (i = 0; i < settings->reg_num; i++) {
1937                 /* Apply 3G settings */
1938                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1939
1940                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1941                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1942                         i2c_success = i2c_write(pipe_ctx, slave_address,
1943                                                 buffer, sizeof(buffer));
1944                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1945                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1946                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1947
1948                         if (!i2c_success)
1949                                 goto i2c_write_fail;
1950
1951                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1952                          * needs to be set to 1 on every 0xA-0xC write.
1953                          */
1954                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1955                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1956                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1957
1958                                 /* Query current value from offset 0xA */
1959                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1960                                         value = settings->reg_settings[i].i2c_reg_val;
1961                                 else {
1962                                         i2c_success =
1963                                                 dal_ddc_service_query_ddc_data(
1964                                                 pipe_ctx->stream->link->ddc,
1965                                                 slave_address, &offset, 1, &value, 1);
1966                                         if (!i2c_success)
1967                                                 goto i2c_write_fail;
1968                                 }
1969
1970                                 buffer[0] = offset;
1971                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1972                                 buffer[1] = value | apply_rx_tx_change;
1973                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1974                                                 buffer, sizeof(buffer));
1975                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1976                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1977                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1978                                 if (!i2c_success)
1979                                         goto i2c_write_fail;
1980                         }
1981                 }
1982         }
1983
1984         /* Apply 3G settings */
1985         if (is_over_340mhz) {
1986                 for (i = 0; i < settings->reg_num_6g; i++) {
1987                         /* Apply 3G settings */
1988                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1989
1990                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1991                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1992                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1993                                                         buffer, sizeof(buffer));
1994                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1995                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1996                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1997
1998                                 if (!i2c_success)
1999                                         goto i2c_write_fail;
2000
2001                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2002                                  * needs to be set to 1 on every 0xA-0xC write.
2003                                  */
2004                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2005                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2006                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2007
2008                                         /* Query current value from offset 0xA */
2009                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2010                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
2011                                         else {
2012                                                 i2c_success =
2013                                                                 dal_ddc_service_query_ddc_data(
2014                                                                 pipe_ctx->stream->link->ddc,
2015                                                                 slave_address, &offset, 1, &value, 1);
2016                                                 if (!i2c_success)
2017                                                         goto i2c_write_fail;
2018                                         }
2019
2020                                         buffer[0] = offset;
2021                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
2022                                         buffer[1] = value | apply_rx_tx_change;
2023                                         i2c_success = i2c_write(pipe_ctx, slave_address,
2024                                                         buffer, sizeof(buffer));
2025                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2026                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2027                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2028                                         if (!i2c_success)
2029                                                 goto i2c_write_fail;
2030                                 }
2031                         }
2032                 }
2033         }
2034
2035         if (is_vga_mode) {
2036                 /* Program additional settings if using 640x480 resolution */
2037
2038                 /* Write offset 0xFF to 0x01 */
2039                 buffer[0] = 0xff;
2040                 buffer[1] = 0x01;
2041                 i2c_success = i2c_write(pipe_ctx, slave_address,
2042                                 buffer, sizeof(buffer));
2043                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2044                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2045                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2046                 if (!i2c_success)
2047                         goto i2c_write_fail;
2048
2049                 /* Write offset 0x00 to 0x23 */
2050                 buffer[0] = 0x00;
2051                 buffer[1] = 0x23;
2052                 i2c_success = i2c_write(pipe_ctx, slave_address,
2053                                 buffer, sizeof(buffer));
2054                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2055                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2056                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2057                 if (!i2c_success)
2058                         goto i2c_write_fail;
2059
2060                 /* Write offset 0xff to 0x00 */
2061                 buffer[0] = 0xff;
2062                 buffer[1] = 0x00;
2063                 i2c_success = i2c_write(pipe_ctx, slave_address,
2064                                 buffer, sizeof(buffer));
2065                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2066                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2067                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2068                 if (!i2c_success)
2069                         goto i2c_write_fail;
2070
2071         }
2072
2073         return;
2074
2075 i2c_write_fail:
2076         DC_LOG_DEBUG("Set retimer failed");
2077 }
2078
2079 static void write_i2c_default_retimer_setting(
2080                 struct pipe_ctx *pipe_ctx,
2081                 bool is_vga_mode,
2082                 bool is_over_340mhz)
2083 {
2084         uint8_t slave_address = (0xBA >> 1);
2085         uint8_t buffer[2];
2086         bool i2c_success = false;
2087         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2088
2089         memset(&buffer, 0, sizeof(buffer));
2090
2091         /* Program Slave Address for tuning single integrity */
2092         /* Write offset 0x0A to 0x13 */
2093         buffer[0] = 0x0A;
2094         buffer[1] = 0x13;
2095         i2c_success = i2c_write(pipe_ctx, slave_address,
2096                         buffer, sizeof(buffer));
2097         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2098                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2099                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2100         if (!i2c_success)
2101                 goto i2c_write_fail;
2102
2103         /* Write offset 0x0A to 0x17 */
2104         buffer[0] = 0x0A;
2105         buffer[1] = 0x17;
2106         i2c_success = i2c_write(pipe_ctx, slave_address,
2107                         buffer, sizeof(buffer));
2108         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2109                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2110                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2111         if (!i2c_success)
2112                 goto i2c_write_fail;
2113
2114         /* Write offset 0x0B to 0xDA or 0xD8 */
2115         buffer[0] = 0x0B;
2116         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2117         i2c_success = i2c_write(pipe_ctx, slave_address,
2118                         buffer, sizeof(buffer));
2119         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2120                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2121                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2122         if (!i2c_success)
2123                 goto i2c_write_fail;
2124
2125         /* Write offset 0x0A to 0x17 */
2126         buffer[0] = 0x0A;
2127         buffer[1] = 0x17;
2128         i2c_success = i2c_write(pipe_ctx, slave_address,
2129                         buffer, sizeof(buffer));
2130         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2131                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2132                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2133         if (!i2c_success)
2134                 goto i2c_write_fail;
2135
2136         /* Write offset 0x0C to 0x1D or 0x91 */
2137         buffer[0] = 0x0C;
2138         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2139         i2c_success = i2c_write(pipe_ctx, slave_address,
2140                         buffer, sizeof(buffer));
2141         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2142                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2143                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2144         if (!i2c_success)
2145                 goto i2c_write_fail;
2146
2147         /* Write offset 0x0A to 0x17 */
2148         buffer[0] = 0x0A;
2149         buffer[1] = 0x17;
2150         i2c_success = i2c_write(pipe_ctx, slave_address,
2151                         buffer, sizeof(buffer));
2152         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2153                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2154                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2155         if (!i2c_success)
2156                 goto i2c_write_fail;
2157
2158
2159         if (is_vga_mode) {
2160                 /* Program additional settings if using 640x480 resolution */
2161
2162                 /* Write offset 0xFF to 0x01 */
2163                 buffer[0] = 0xff;
2164                 buffer[1] = 0x01;
2165                 i2c_success = i2c_write(pipe_ctx, slave_address,
2166                                 buffer, sizeof(buffer));
2167                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2168                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2169                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2170                 if (!i2c_success)
2171                         goto i2c_write_fail;
2172
2173                 /* Write offset 0x00 to 0x23 */
2174                 buffer[0] = 0x00;
2175                 buffer[1] = 0x23;
2176                 i2c_success = i2c_write(pipe_ctx, slave_address,
2177                                 buffer, sizeof(buffer));
2178                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2179                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2180                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2181                 if (!i2c_success)
2182                         goto i2c_write_fail;
2183
2184                 /* Write offset 0xff to 0x00 */
2185                 buffer[0] = 0xff;
2186                 buffer[1] = 0x00;
2187                 i2c_success = i2c_write(pipe_ctx, slave_address,
2188                                 buffer, sizeof(buffer));
2189                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2190                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2191                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2192                 if (!i2c_success)
2193                         goto i2c_write_fail;
2194         }
2195
2196         return;
2197
2198 i2c_write_fail:
2199         DC_LOG_DEBUG("Set default retimer failed");
2200 }
2201
2202 static void write_i2c_redriver_setting(
2203                 struct pipe_ctx *pipe_ctx,
2204                 bool is_over_340mhz)
2205 {
2206         uint8_t slave_address = (0xF0 >> 1);
2207         uint8_t buffer[16];
2208         bool i2c_success = false;
2209         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2210
2211         memset(&buffer, 0, sizeof(buffer));
2212
2213         // Program Slave Address for tuning single integrity
2214         buffer[3] = 0x4E;
2215         buffer[4] = 0x4E;
2216         buffer[5] = 0x4E;
2217         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2218
2219         i2c_success = i2c_write(pipe_ctx, slave_address,
2220                                         buffer, sizeof(buffer));
2221         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2222                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2223                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2224                 i2c_success = %d\n",
2225                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2226
2227         if (!i2c_success)
2228                 DC_LOG_DEBUG("Set redriver failed");
2229 }
2230
2231 static void disable_link(struct dc_link *link, enum signal_type signal)
2232 {
2233         /*
2234          * TODO: implement call for dp_set_hw_test_pattern
2235          * it is needed for compliance testing
2236          */
2237
2238         /* Here we need to specify that encoder output settings
2239          * need to be calculated as for the set mode,
2240          * it will lead to querying dynamic link capabilities
2241          * which should be done before enable output
2242          */
2243
2244         if (dc_is_dp_signal(signal)) {
2245                 /* SST DP, eDP */
2246                 if (dc_is_dp_sst_signal(signal))
2247                         dp_disable_link_phy(link, signal);
2248                 else
2249                         dp_disable_link_phy_mst(link, signal);
2250
2251                 if (dc_is_dp_sst_signal(signal) ||
2252                                 link->mst_stream_alloc_table.stream_count == 0) {
2253                         dp_set_fec_enable(link, false);
2254                         dp_set_fec_ready(link, false);
2255                 }
2256         } else {
2257                 if (signal != SIGNAL_TYPE_VIRTUAL)
2258                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2259         }
2260
2261         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2262                 /* MST disable link only when no stream use the link */
2263                 if (link->mst_stream_alloc_table.stream_count <= 0)
2264                         link->link_status.link_active = false;
2265         } else {
2266                 link->link_status.link_active = false;
2267         }
2268 }
2269
2270 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2271 {
2272         struct dc_stream_state *stream = pipe_ctx->stream;
2273         struct dc_link *link = stream->link;
2274         enum dc_color_depth display_color_depth;
2275         enum engine_id eng_id;
2276         struct ext_hdmi_settings settings = {0};
2277         bool is_over_340mhz = false;
2278         bool is_vga_mode = (stream->timing.h_addressable == 640)
2279                         && (stream->timing.v_addressable == 480);
2280
2281         if (stream->phy_pix_clk == 0)
2282                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2283         if (stream->phy_pix_clk > 340000)
2284                 is_over_340mhz = true;
2285
2286         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2287                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2288                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2289                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2290                         /* DP159, Retimer settings */
2291                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2292
2293                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2294                                 write_i2c_retimer_setting(pipe_ctx,
2295                                                 is_vga_mode, is_over_340mhz, &settings);
2296                         } else {
2297                                 write_i2c_default_retimer_setting(pipe_ctx,
2298                                                 is_vga_mode, is_over_340mhz);
2299                         }
2300                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2301                         /* PI3EQX1204, Redriver settings */
2302                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2303                 }
2304         }
2305
2306         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2307                 dal_ddc_service_write_scdc_data(
2308                         stream->link->ddc,
2309                         stream->phy_pix_clk,
2310                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2311
2312         memset(&stream->link->cur_link_settings, 0,
2313                         sizeof(struct dc_link_settings));
2314
2315         display_color_depth = stream->timing.display_color_depth;
2316         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2317                 display_color_depth = COLOR_DEPTH_888;
2318
2319         link->link_enc->funcs->enable_tmds_output(
2320                         link->link_enc,
2321                         pipe_ctx->clock_source->id,
2322                         display_color_depth,
2323                         pipe_ctx->stream->signal,
2324                         stream->phy_pix_clk);
2325
2326         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2327                 dal_ddc_service_read_scdc_data(link->ddc);
2328 }
2329
2330 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2331 {
2332         struct dc_stream_state *stream = pipe_ctx->stream;
2333         struct dc_link *link = stream->link;
2334
2335         if (stream->phy_pix_clk == 0)
2336                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2337
2338         memset(&stream->link->cur_link_settings, 0,
2339                         sizeof(struct dc_link_settings));
2340
2341         link->link_enc->funcs->enable_lvds_output(
2342                         link->link_enc,
2343                         pipe_ctx->clock_source->id,
2344                         stream->phy_pix_clk);
2345
2346 }
2347
2348 /****************************enable_link***********************************/
2349 static enum dc_status enable_link(
2350                 struct dc_state *state,
2351                 struct pipe_ctx *pipe_ctx)
2352 {
2353         enum dc_status status = DC_ERROR_UNEXPECTED;
2354         struct dc_stream_state *stream = pipe_ctx->stream;
2355         struct dc_link *link = stream->link;
2356
2357         /* There's some scenarios where driver is unloaded with display
2358          * still enabled. When driver is reloaded, it may cause a display
2359          * to not light up if there is a mismatch between old and new
2360          * link settings. Need to call disable first before enabling at
2361          * new link settings.
2362          */
2363         if (link->link_status.link_active) {
2364                 disable_link(link, pipe_ctx->stream->signal);
2365         }
2366
2367         switch (pipe_ctx->stream->signal) {
2368         case SIGNAL_TYPE_DISPLAY_PORT:
2369                 status = enable_link_dp(state, pipe_ctx);
2370                 break;
2371         case SIGNAL_TYPE_EDP:
2372                 status = enable_link_edp(state, pipe_ctx);
2373                 break;
2374         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2375                 status = enable_link_dp_mst(state, pipe_ctx);
2376                 msleep(200);
2377                 break;
2378         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2379         case SIGNAL_TYPE_DVI_DUAL_LINK:
2380         case SIGNAL_TYPE_HDMI_TYPE_A:
2381                 enable_link_hdmi(pipe_ctx);
2382                 status = DC_OK;
2383                 break;
2384         case SIGNAL_TYPE_LVDS:
2385                 enable_link_lvds(pipe_ctx);
2386                 status = DC_OK;
2387                 break;
2388         case SIGNAL_TYPE_VIRTUAL:
2389                 status = DC_OK;
2390                 break;
2391         default:
2392                 break;
2393         }
2394
2395         if (status == DC_OK)
2396                 pipe_ctx->stream->link->link_status.link_active = true;
2397
2398         return status;
2399 }
2400
2401 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2402 {
2403
2404         uint32_t pxl_clk = timing->pix_clk_100hz;
2405
2406         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2407                 pxl_clk /= 2;
2408         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2409                 pxl_clk = pxl_clk * 2 / 3;
2410
2411         if (timing->display_color_depth == COLOR_DEPTH_101010)
2412                 pxl_clk = pxl_clk * 10 / 8;
2413         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2414                 pxl_clk = pxl_clk * 12 / 8;
2415
2416         return pxl_clk;
2417 }
2418
2419 static bool dp_active_dongle_validate_timing(
2420                 const struct dc_crtc_timing *timing,
2421                 const struct dpcd_caps *dpcd_caps)
2422 {
2423         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2424
2425         switch (dpcd_caps->dongle_type) {
2426         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2427         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2428         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2429                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2430                         return true;
2431                 else
2432                         return false;
2433         default:
2434                 break;
2435         }
2436
2437         if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2438                 dongle_caps->extendedCapValid == false)
2439                 return true;
2440
2441         /* Check Pixel Encoding */
2442         switch (timing->pixel_encoding) {
2443         case PIXEL_ENCODING_RGB:
2444         case PIXEL_ENCODING_YCBCR444:
2445                 break;
2446         case PIXEL_ENCODING_YCBCR422:
2447                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2448                         return false;
2449                 break;
2450         case PIXEL_ENCODING_YCBCR420:
2451                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2452                         return false;
2453                 break;
2454         default:
2455                 /* Invalid Pixel Encoding*/
2456                 return false;
2457         }
2458
2459         switch (timing->display_color_depth) {
2460         case COLOR_DEPTH_666:
2461         case COLOR_DEPTH_888:
2462                 /*888 and 666 should always be supported*/
2463                 break;
2464         case COLOR_DEPTH_101010:
2465                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2466                         return false;
2467                 break;
2468         case COLOR_DEPTH_121212:
2469                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2470                         return false;
2471                 break;
2472         case COLOR_DEPTH_141414:
2473         case COLOR_DEPTH_161616:
2474         default:
2475                 /* These color depths are currently not supported */
2476                 return false;
2477         }
2478
2479         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2480                 return false;
2481
2482         return true;
2483 }
2484
2485 enum dc_status dc_link_validate_mode_timing(
2486                 const struct dc_stream_state *stream,
2487                 struct dc_link *link,
2488                 const struct dc_crtc_timing *timing)
2489 {
2490         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2491         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2492
2493         /* A hack to avoid failing any modes for EDID override feature on
2494          * topology change such as lower quality cable for DP or different dongle
2495          */
2496         if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2497                 return DC_OK;
2498
2499         /* Passive Dongle */
2500         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2501                 return DC_EXCEED_DONGLE_CAP;
2502
2503         /* Active Dongle*/
2504         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2505                 return DC_EXCEED_DONGLE_CAP;
2506
2507         switch (stream->signal) {
2508         case SIGNAL_TYPE_EDP:
2509         case SIGNAL_TYPE_DISPLAY_PORT:
2510                 if (!dp_validate_mode_timing(
2511                                 link,
2512                                 timing))
2513                         return DC_NO_DP_LINK_BANDWIDTH;
2514                 break;
2515
2516         default:
2517                 break;
2518         }
2519
2520         return DC_OK;
2521 }
2522
2523 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2524 {
2525         int i;
2526         struct dc *dc = NULL;
2527         struct abm *abm = NULL;
2528
2529         if (!link || !link->ctx)
2530                 return NULL;
2531
2532         dc = link->ctx->dc;
2533
2534         for (i = 0; i < MAX_PIPES; i++) {
2535                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2536                 struct dc_stream_state *stream = pipe_ctx.stream;
2537
2538                 if (stream && stream->link == link) {
2539                         abm = pipe_ctx.stream_res.abm;
2540                         break;
2541                 }
2542         }
2543         return abm;
2544 }
2545
2546 int dc_link_get_backlight_level(const struct dc_link *link)
2547 {
2548
2549         struct abm *abm = get_abm_from_stream_res(link);
2550
2551         if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2552                 return DC_ERROR_UNEXPECTED;
2553
2554         return (int) abm->funcs->get_current_backlight(abm);
2555 }
2556
2557 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
2558 {
2559         struct abm *abm = get_abm_from_stream_res(link);
2560
2561         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
2562                 return DC_ERROR_UNEXPECTED;
2563
2564         return (int) abm->funcs->get_target_backlight(abm);
2565 }
2566
2567 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
2568 {
2569         int i;
2570         struct dc *dc = link->ctx->dc;
2571         struct pipe_ctx *pipe_ctx = NULL;
2572
2573         for (i = 0; i < MAX_PIPES; i++) {
2574                 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
2575                         if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
2576                                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2577                                 break;
2578                         }
2579                 }
2580         }
2581
2582         return pipe_ctx;
2583 }
2584
2585 bool dc_link_set_backlight_level(const struct dc_link *link,
2586                 uint32_t backlight_pwm_u16_16,
2587                 uint32_t frame_ramp)
2588 {
2589         struct dc  *dc = link->ctx->dc;
2590
2591         DC_LOGGER_INIT(link->ctx->logger);
2592         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2593                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2594
2595         if (dc_is_embedded_signal(link->connector_signal)) {
2596                 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
2597
2598                 if (pipe_ctx) {
2599                         /* Disable brightness ramping when the display is blanked
2600                          * as it can hang the DMCU
2601                          */
2602                         if (pipe_ctx->plane_state == NULL)
2603                                 frame_ramp = 0;
2604                 } else {
2605                         return false;
2606                 }
2607
2608                 dc->hwss.set_backlight_level(
2609                                 pipe_ctx,
2610                                 backlight_pwm_u16_16,
2611                                 frame_ramp);
2612         }
2613         return true;
2614 }
2615
2616 bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
2617                 bool wait, bool force_static)
2618 {
2619         struct dc  *dc = link->ctx->dc;
2620         struct dmcu *dmcu = dc->res_pool->dmcu;
2621         struct dmub_psr *psr = dc->res_pool->psr;
2622
2623         if (psr == NULL && force_static)
2624                 return false;
2625
2626         link->psr_settings.psr_allow_active = allow_active;
2627
2628         if (psr != NULL && link->psr_settings.psr_feature_enabled) {
2629                 if (force_static && psr->funcs->psr_force_static)
2630                         psr->funcs->psr_force_static(psr);
2631                 psr->funcs->psr_enable(psr, allow_active, wait);
2632         } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
2633                 dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
2634         else
2635                 return false;
2636
2637         return true;
2638 }
2639
2640 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
2641 {
2642         struct dc  *dc = link->ctx->dc;
2643         struct dmcu *dmcu = dc->res_pool->dmcu;
2644         struct dmub_psr *psr = dc->res_pool->psr;
2645
2646         if (psr != NULL && link->psr_settings.psr_feature_enabled)
2647                 psr->funcs->psr_get_state(psr, state);
2648         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
2649                 dmcu->funcs->get_psr_state(dmcu, state);
2650
2651         return true;
2652 }
2653
2654 static inline enum physical_phy_id
2655 transmitter_to_phy_id(enum transmitter transmitter_value)
2656 {
2657         switch (transmitter_value) {
2658         case TRANSMITTER_UNIPHY_A:
2659                 return PHYLD_0;
2660         case TRANSMITTER_UNIPHY_B:
2661                 return PHYLD_1;
2662         case TRANSMITTER_UNIPHY_C:
2663                 return PHYLD_2;
2664         case TRANSMITTER_UNIPHY_D:
2665                 return PHYLD_3;
2666         case TRANSMITTER_UNIPHY_E:
2667                 return PHYLD_4;
2668         case TRANSMITTER_UNIPHY_F:
2669                 return PHYLD_5;
2670         case TRANSMITTER_NUTMEG_CRT:
2671                 return PHYLD_6;
2672         case TRANSMITTER_TRAVIS_CRT:
2673                 return PHYLD_7;
2674         case TRANSMITTER_TRAVIS_LCD:
2675                 return PHYLD_8;
2676         case TRANSMITTER_UNIPHY_G:
2677                 return PHYLD_9;
2678         case TRANSMITTER_COUNT:
2679                 return PHYLD_COUNT;
2680         case TRANSMITTER_UNKNOWN:
2681                 return PHYLD_UNKNOWN;
2682         default:
2683                 WARN_ONCE(1, "Unknown transmitter value %d\n",
2684                           transmitter_value);
2685                 return PHYLD_UNKNOWN;
2686         }
2687 }
2688
2689 bool dc_link_setup_psr(struct dc_link *link,
2690                 const struct dc_stream_state *stream, struct psr_config *psr_config,
2691                 struct psr_context *psr_context)
2692 {
2693         struct dc *dc;
2694         struct dmcu *dmcu;
2695         struct dmub_psr *psr;
2696         int i;
2697         /* updateSinkPsrDpcdConfig*/
2698         union dpcd_psr_configuration psr_configuration;
2699
2700         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
2701
2702         if (!link)
2703                 return false;
2704
2705         dc = link->ctx->dc;
2706         dmcu = dc->res_pool->dmcu;
2707         psr = dc->res_pool->psr;
2708
2709         if (!dmcu && !psr)
2710                 return false;
2711
2712
2713         memset(&psr_configuration, 0, sizeof(psr_configuration));
2714
2715         psr_configuration.bits.ENABLE                    = 1;
2716         psr_configuration.bits.CRC_VERIFICATION          = 1;
2717         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
2718                         psr_config->psr_frame_capture_indication_req;
2719
2720         /* Check for PSR v2*/
2721         if (psr_config->psr_version == 0x2) {
2722                 /* For PSR v2 selective update.
2723                  * Indicates whether sink should start capturing
2724                  * immediately following active scan line,
2725                  * or starting with the 2nd active scan line.
2726                  */
2727                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
2728                 /*For PSR v2, determines whether Sink should generate
2729                  * IRQ_HPD when CRC mismatch is detected.
2730                  */
2731                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
2732         }
2733
2734         dm_helpers_dp_write_dpcd(
2735                 link->ctx,
2736                 link,
2737                 368,
2738                 &psr_configuration.raw,
2739                 sizeof(psr_configuration.raw));
2740
2741         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
2742         psr_context->transmitterId = link->link_enc->transmitter;
2743         psr_context->engineId = link->link_enc->preferred_engine;
2744
2745         for (i = 0; i < MAX_PIPES; i++) {
2746                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
2747                                 == stream) {
2748                         /* dmcu -1 for all controller id values,
2749                          * therefore +1 here
2750                          */
2751                         psr_context->controllerId =
2752                                 dc->current_state->res_ctx.
2753                                 pipe_ctx[i].stream_res.tg->inst + 1;
2754                         break;
2755                 }
2756         }
2757
2758         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
2759         psr_context->phyType = PHY_TYPE_UNIPHY;
2760         /*PhyId is associated with the transmitter id*/
2761         psr_context->smuPhyId =
2762                 transmitter_to_phy_id(link->link_enc->transmitter);
2763
2764         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
2765         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
2766                                         timing.pix_clk_100hz * 100),
2767                                         stream->timing.v_total),
2768                                         stream->timing.h_total);
2769
2770         psr_context->psrSupportedDisplayConfig = true;
2771         psr_context->psrExitLinkTrainingRequired =
2772                 psr_config->psr_exit_link_training_required;
2773         psr_context->sdpTransmitLineNumDeadline =
2774                 psr_config->psr_sdp_transmit_line_num_deadline;
2775         psr_context->psrFrameCaptureIndicationReq =
2776                 psr_config->psr_frame_capture_indication_req;
2777
2778         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
2779
2780         psr_context->numberOfControllers =
2781                         link->dc->res_pool->timing_generator_count;
2782
2783         psr_context->rfb_update_auto_en = true;
2784
2785         /* 2 frames before enter PSR. */
2786         psr_context->timehyst_frames = 2;
2787         /* half a frame
2788          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
2789          */
2790         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
2791         psr_context->aux_repeats = 10;
2792
2793         psr_context->psr_level.u32all = 0;
2794
2795 #if defined(CONFIG_DRM_AMD_DC_DCN)
2796         /*skip power down the single pipe since it blocks the cstate*/
2797         if ((link->ctx->asic_id.chip_family == FAMILY_RV) &&
2798              ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
2799                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
2800 #endif
2801
2802         /* SMU will perform additional powerdown sequence.
2803          * For unsupported ASICs, set psr_level flag to skip PSR
2804          *  static screen notification to SMU.
2805          *  (Always set for DAL2, did not check ASIC)
2806          */
2807         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
2808         psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
2809
2810         /* Complete PSR entry before aborting to prevent intermittent
2811          * freezes on certain eDPs
2812          */
2813         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
2814
2815         /* Controls additional delay after remote frame capture before
2816          * continuing power down, default = 0
2817          */
2818         psr_context->frame_delay = 0;
2819
2820         if (psr)
2821                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context);
2822         else
2823                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
2824
2825         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
2826          * should not happen since firmware should be running at this point
2827          */
2828         if (link->psr_settings.psr_feature_enabled == 0)
2829                 ASSERT(0);
2830
2831         return true;
2832
2833 }
2834
2835 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
2836 {
2837         struct dc  *dc = link->ctx->dc;
2838         struct dmub_psr *psr = dc->res_pool->psr;
2839
2840         // PSR residency measurements only supported on DMCUB
2841         if (psr != NULL && link->psr_settings.psr_feature_enabled)
2842                 psr->funcs->psr_get_residency(psr, residency);
2843         else
2844                 *residency = 0;
2845 }
2846
2847 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2848 {
2849         return &link->link_status;
2850 }
2851
2852 void core_link_resume(struct dc_link *link)
2853 {
2854         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2855                 program_hpd_filter(link);
2856 }
2857
2858 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2859 {
2860         struct fixed31_32 mbytes_per_sec;
2861         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
2862                         &stream->link->cur_link_settings);
2863         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
2864
2865         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2866
2867         return dc_fixpt_div_int(mbytes_per_sec, 54);
2868 }
2869
2870 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
2871 {
2872         struct fixed31_32 peak_kbps;
2873         uint32_t numerator;
2874         uint32_t denominator;
2875
2876         /*
2877          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2878          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2879          * common multiplier to render an integer PBN for all link rate/lane
2880          * counts combinations
2881          * calculate
2882          * peak_kbps *= (1006/1000)
2883          * peak_kbps *= (64/54)
2884          * peak_kbps *= 8    convert to bytes
2885          */
2886
2887         numerator = 64 * PEAK_FACTOR_X1000;
2888         denominator = 54 * 8 * 1000 * 1000;
2889         kbps *= numerator;
2890         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2891
2892         return peak_kbps;
2893 }
2894
2895 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2896 {
2897         uint64_t kbps;
2898
2899         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2900         return get_pbn_from_bw_in_kbps(kbps);
2901 }
2902
2903 static void update_mst_stream_alloc_table(
2904         struct dc_link *link,
2905         struct stream_encoder *stream_enc,
2906         const struct dp_mst_stream_allocation_table *proposed_table)
2907 {
2908         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2909                         { 0 } };
2910         struct link_mst_stream_allocation *dc_alloc;
2911
2912         int i;
2913         int j;
2914
2915         /* if DRM proposed_table has more than one new payload */
2916         ASSERT(proposed_table->stream_count -
2917                         link->mst_stream_alloc_table.stream_count < 2);
2918
2919         /* copy proposed_table to link, add stream encoder */
2920         for (i = 0; i < proposed_table->stream_count; i++) {
2921
2922                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2923                         dc_alloc =
2924                         &link->mst_stream_alloc_table.stream_allocations[j];
2925
2926                         if (dc_alloc->vcp_id ==
2927                                 proposed_table->stream_allocations[i].vcp_id) {
2928
2929                                 work_table[i] = *dc_alloc;
2930                                 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
2931                                 break; /* exit j loop */
2932                         }
2933                 }
2934
2935                 /* new vcp_id */
2936                 if (j == link->mst_stream_alloc_table.stream_count) {
2937                         work_table[i].vcp_id =
2938                                 proposed_table->stream_allocations[i].vcp_id;
2939                         work_table[i].slot_count =
2940                                 proposed_table->stream_allocations[i].slot_count;
2941                         work_table[i].stream_enc = stream_enc;
2942                 }
2943         }
2944
2945         /* update link->mst_stream_alloc_table with work_table */
2946         link->mst_stream_alloc_table.stream_count =
2947                         proposed_table->stream_count;
2948         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2949                 link->mst_stream_alloc_table.stream_allocations[i] =
2950                                 work_table[i];
2951 }
2952
2953 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2954  * because stream_encoder is not exposed to dm
2955  */
2956 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2957 {
2958         struct dc_stream_state *stream = pipe_ctx->stream;
2959         struct dc_link *link = stream->link;
2960         struct link_encoder *link_encoder = link->link_enc;
2961         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2962         struct dp_mst_stream_allocation_table proposed_table = {0};
2963         struct fixed31_32 avg_time_slots_per_mtp;
2964         struct fixed31_32 pbn;
2965         struct fixed31_32 pbn_per_slot;
2966         uint8_t i;
2967         enum act_return_status ret;
2968         DC_LOGGER_INIT(link->ctx->logger);
2969
2970         /* enable_link_dp_mst already check link->enabled_stream_count
2971          * and stream is in link->stream[]. This is called during set mode,
2972          * stream_enc is available.
2973          */
2974
2975         /* get calculate VC payload for stream: stream_alloc */
2976         if (dm_helpers_dp_mst_write_payload_allocation_table(
2977                 stream->ctx,
2978                 stream,
2979                 &proposed_table,
2980                 true)) {
2981                 update_mst_stream_alloc_table(
2982                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2983         }
2984         else
2985                 DC_LOG_WARNING("Failed to update"
2986                                 "MST allocation table for"
2987                                 "pipe idx:%d\n",
2988                                 pipe_ctx->pipe_idx);
2989
2990         DC_LOG_MST("%s  "
2991                         "stream_count: %d: \n ",
2992                         __func__,
2993                         link->mst_stream_alloc_table.stream_count);
2994
2995         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2996                 DC_LOG_MST("stream_enc[%d]: %p      "
2997                 "stream[%d].vcp_id: %d      "
2998                 "stream[%d].slot_count: %d\n",
2999                 i,
3000                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3001                 i,
3002                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3003                 i,
3004                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3005         }
3006
3007         ASSERT(proposed_table.stream_count > 0);
3008
3009         /* program DP source TX for payload */
3010         link_encoder->funcs->update_mst_stream_allocation_table(
3011                 link_encoder,
3012                 &link->mst_stream_alloc_table);
3013
3014         /* send down message */
3015         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3016                         stream->ctx,
3017                         stream);
3018
3019         if (ret != ACT_LINK_LOST) {
3020                 dm_helpers_dp_mst_send_payload_allocation(
3021                                 stream->ctx,
3022                                 stream,
3023                                 true);
3024         }
3025
3026         /* slot X.Y for only current stream */
3027         pbn_per_slot = get_pbn_per_slot(stream);
3028         if (pbn_per_slot.value == 0) {
3029                 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3030                 return DC_UNSUPPORTED_VALUE;
3031         }
3032         pbn = get_pbn_from_timing(pipe_ctx);
3033         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3034
3035         stream_encoder->funcs->set_throttled_vcp_size(
3036                 stream_encoder,
3037                 avg_time_slots_per_mtp);
3038
3039         return DC_OK;
3040
3041 }
3042
3043 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3044 {
3045         struct dc_stream_state *stream = pipe_ctx->stream;
3046         struct dc_link *link = stream->link;
3047         struct link_encoder *link_encoder = link->link_enc;
3048         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3049         struct dp_mst_stream_allocation_table proposed_table = {0};
3050         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3051         uint8_t i;
3052         bool mst_mode = (link->type == dc_connection_mst_branch);
3053         DC_LOGGER_INIT(link->ctx->logger);
3054
3055         /* deallocate_mst_payload is called before disable link. When mode or
3056          * disable/enable monitor, new stream is created which is not in link
3057          * stream[] yet. For this, payload is not allocated yet, so de-alloc
3058          * should not done. For new mode set, map_resources will get engine
3059          * for new stream, so stream_enc->id should be validated until here.
3060          */
3061
3062         /* slot X.Y */
3063         stream_encoder->funcs->set_throttled_vcp_size(
3064                 stream_encoder,
3065                 avg_time_slots_per_mtp);
3066
3067         /* TODO: which component is responsible for remove payload table? */
3068         if (mst_mode) {
3069                 if (dm_helpers_dp_mst_write_payload_allocation_table(
3070                                 stream->ctx,
3071                                 stream,
3072                                 &proposed_table,
3073                                 false)) {
3074
3075                         update_mst_stream_alloc_table(
3076                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3077                 }
3078                 else {
3079                                 DC_LOG_WARNING("Failed to update"
3080                                                 "MST allocation table for"
3081                                                 "pipe idx:%d\n",
3082                                                 pipe_ctx->pipe_idx);
3083                 }
3084         }
3085
3086         DC_LOG_MST("%s"
3087                         "stream_count: %d: ",
3088                         __func__,
3089                         link->mst_stream_alloc_table.stream_count);
3090
3091         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3092                 DC_LOG_MST("stream_enc[%d]: %p      "
3093                 "stream[%d].vcp_id: %d      "
3094                 "stream[%d].slot_count: %d\n",
3095                 i,
3096                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3097                 i,
3098                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3099                 i,
3100                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3101         }
3102
3103         link_encoder->funcs->update_mst_stream_allocation_table(
3104                 link_encoder,
3105                 &link->mst_stream_alloc_table);
3106
3107         if (mst_mode) {
3108                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3109                         stream->ctx,
3110                         stream);
3111
3112                 dm_helpers_dp_mst_send_payload_allocation(
3113                         stream->ctx,
3114                         stream,
3115                         false);
3116         }
3117
3118         return DC_OK;
3119 }
3120
3121 enum dc_status dc_link_reallocate_mst_payload(struct dc_link *link)
3122 {
3123         int i;
3124         struct pipe_ctx *pipe_ctx;
3125
3126         // Clear all of MST payload then reallocate
3127         for (i = 0; i < MAX_PIPES; i++) {
3128                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3129
3130                 /* driver enable split pipe for external monitors
3131                  * we have to check pipe_ctx is split pipe or not
3132                  * If it's split pipe, driver using top pipe to
3133                  * reaallocate.
3134                  */
3135                 if (!pipe_ctx || pipe_ctx->top_pipe)
3136                         continue;
3137
3138                 if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
3139                                 pipe_ctx->stream->dpms_off == false &&
3140                                 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3141                         deallocate_mst_payload(pipe_ctx);
3142                 }
3143         }
3144
3145         for (i = 0; i < MAX_PIPES; i++) {
3146                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3147
3148                 if (!pipe_ctx || pipe_ctx->top_pipe)
3149                         continue;
3150
3151                 if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
3152                                 pipe_ctx->stream->dpms_off == false &&
3153                                 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3154                         /* enable/disable PHY will clear connection between BE and FE
3155                          * need to restore it.
3156                          */
3157                         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
3158                                                                         pipe_ctx->stream_res.stream_enc->id, true);
3159                         dc_link_allocate_mst_payload(pipe_ctx);
3160                 }
3161         }
3162
3163         return DC_OK;
3164 }
3165
3166 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3167 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3168 {
3169         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3170         if (cp_psp && cp_psp->funcs.update_stream_config) {
3171                 struct cp_psp_stream_config config = {0};
3172                 enum dp_panel_mode panel_mode =
3173                                 dp_get_panel_mode(pipe_ctx->stream->link);
3174
3175                 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3176                 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3177                 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
3178                 config.dpms_off = dpms_off;
3179                 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
3180                 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
3181                 config.mst_enabled = (pipe_ctx->stream->signal ==
3182                                 SIGNAL_TYPE_DISPLAY_PORT_MST);
3183                 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
3184         }
3185 }
3186 #endif
3187
3188 void core_link_enable_stream(
3189                 struct dc_state *state,
3190                 struct pipe_ctx *pipe_ctx)
3191 {
3192         struct dc *dc = pipe_ctx->stream->ctx->dc;
3193         struct dc_stream_state *stream = pipe_ctx->stream;
3194         enum dc_status status;
3195 #if defined(CONFIG_DRM_AMD_DC_DCN)
3196         enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
3197 #endif
3198         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
3199
3200         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3201                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3202                 return;
3203
3204         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3205                 stream->link->link_enc->funcs->setup(
3206                         stream->link->link_enc,
3207                         pipe_ctx->stream->signal);
3208                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
3209                         pipe_ctx->stream_res.stream_enc,
3210                         pipe_ctx->stream_res.tg->inst,
3211                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
3212         }
3213
3214         if (dc_is_dp_signal(pipe_ctx->stream->signal))
3215                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
3216                         pipe_ctx->stream_res.stream_enc,
3217                         &stream->timing,
3218                         stream->output_color_space,
3219                         stream->use_vsc_sdp_for_colorimetry,
3220                         stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
3221
3222         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
3223                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
3224                         pipe_ctx->stream_res.stream_enc,
3225                         &stream->timing,
3226                         stream->phy_pix_clk,
3227                         pipe_ctx->stream_res.audio != NULL);
3228
3229         pipe_ctx->stream->link->link_state_valid = true;
3230
3231 #if defined(CONFIG_DRM_AMD_DC_DCN)
3232         if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
3233                 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
3234 #endif
3235
3236         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
3237                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
3238                         pipe_ctx->stream_res.stream_enc,
3239                         &stream->timing,
3240                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
3241                         true : false);
3242
3243         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
3244                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
3245                         pipe_ctx->stream_res.stream_enc,
3246                         &stream->timing);
3247
3248         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
3249                 bool apply_edp_fast_boot_optimization =
3250                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
3251
3252                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
3253
3254                 resource_build_info_frame(pipe_ctx);
3255                 dc->hwss.update_info_frame(pipe_ctx);
3256
3257                 /* Do not touch link on seamless boot optimization. */
3258                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
3259                         pipe_ctx->stream->dpms_off = false;
3260 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3261                         update_psp_stream_config(pipe_ctx, false);
3262 #endif
3263                         return;
3264                 }
3265
3266                 /* eDP lit up by bios already, no need to enable again. */
3267                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
3268                                         apply_edp_fast_boot_optimization) {
3269                         pipe_ctx->stream->dpms_off = false;
3270 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3271                         update_psp_stream_config(pipe_ctx, false);
3272 #endif
3273                         return;
3274                 }
3275
3276                 if (pipe_ctx->stream->dpms_off)
3277                         return;
3278
3279                 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
3280                  * link training). This is to make sure the bandwidth sent to DIG BE won't be
3281                  * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
3282                  * will be automatically set at a later time when the video is enabled
3283                  * (DP_VID_STREAM_EN = 1).
3284                  */
3285                 if (pipe_ctx->stream->timing.flags.DSC) {
3286                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3287                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3288                                 dp_set_dsc_enable(pipe_ctx, true);
3289                 }
3290
3291                 status = enable_link(state, pipe_ctx);
3292
3293                 if (status != DC_OK) {
3294                         DC_LOG_WARNING("enabling link %u failed: %d\n",
3295                         pipe_ctx->stream->link->link_index,
3296                         status);
3297
3298                         /* Abort stream enable *unless* the failure was due to
3299                          * DP link training - some DP monitors will recover and
3300                          * show the stream anyway. But MST displays can't proceed
3301                          * without link training.
3302                          */
3303                         if (status != DC_FAIL_DP_LINK_TRAINING ||
3304                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3305                                 BREAK_TO_DEBUGGER();
3306                                 return;
3307                         }
3308                 }
3309
3310                 /* turn off otg test pattern if enable */
3311                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3312                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3313                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3314                                         COLOR_DEPTH_UNDEFINED);
3315
3316                 /* This second call is needed to reconfigure the DIG
3317                  * as a workaround for the incorrect value being applied
3318                  * from transmitter control.
3319                  */
3320                 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
3321                         stream->link->link_enc->funcs->setup(
3322                                 stream->link->link_enc,
3323                                 pipe_ctx->stream->signal);
3324
3325                 dc->hwss.enable_stream(pipe_ctx);
3326
3327                 /* Set DPS PPS SDP (AKA "info frames") */
3328                 if (pipe_ctx->stream->timing.flags.DSC) {
3329                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3330                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3331                                 dp_set_dsc_pps_sdp(pipe_ctx, true);
3332                 }
3333
3334                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3335                         dc_link_allocate_mst_payload(pipe_ctx);
3336
3337                 dc->hwss.unblank_stream(pipe_ctx,
3338                         &pipe_ctx->stream->link->cur_link_settings);
3339
3340                 if (stream->sink_patches.delay_ignore_msa > 0)
3341                         msleep(stream->sink_patches.delay_ignore_msa);
3342
3343                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3344                         enable_stream_features(pipe_ctx);
3345 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3346                 update_psp_stream_config(pipe_ctx, false);
3347 #endif
3348
3349                 dc->hwss.enable_audio_stream(pipe_ctx);
3350
3351         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
3352                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3353                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
3354                         dp_set_dsc_enable(pipe_ctx, true);
3355
3356         }
3357
3358         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3359                 core_link_set_avmute(pipe_ctx, false);
3360         }
3361 }
3362
3363 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
3364 {
3365         struct dc  *dc = pipe_ctx->stream->ctx->dc;
3366         struct dc_stream_state *stream = pipe_ctx->stream;
3367         struct dc_link *link = stream->sink->link;
3368
3369         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3370                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3371                 return;
3372
3373         if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
3374                 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
3375                         core_link_set_avmute(pipe_ctx, true);
3376         }
3377
3378         dc->hwss.disable_audio_stream(pipe_ctx);
3379
3380 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3381         update_psp_stream_config(pipe_ctx, true);
3382 #endif
3383         dc->hwss.blank_stream(pipe_ctx);
3384
3385         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3386                 deallocate_mst_payload(pipe_ctx);
3387
3388         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
3389                 struct ext_hdmi_settings settings = {0};
3390                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
3391
3392                 unsigned short masked_chip_caps = link->chip_caps &
3393                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
3394                 //Need to inform that sink is going to use legacy HDMI mode.
3395                 dal_ddc_service_write_scdc_data(
3396                         link->ddc,
3397                         165000,//vbios only handles 165Mhz.
3398                         false);
3399                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
3400                         /* DP159, Retimer settings */
3401                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
3402                                 write_i2c_retimer_setting(pipe_ctx,
3403                                                 false, false, &settings);
3404                         else
3405                                 write_i2c_default_retimer_setting(pipe_ctx,
3406                                                 false, false);
3407                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
3408                         /* PI3EQX1204, Redriver settings */
3409                         write_i2c_redriver_setting(pipe_ctx, false);
3410                 }
3411         }
3412
3413         disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
3414
3415         dc->hwss.disable_stream(pipe_ctx);
3416
3417         if (pipe_ctx->stream->timing.flags.DSC) {
3418                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3419                         dp_set_dsc_enable(pipe_ctx, false);
3420         }
3421 }
3422
3423 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
3424 {
3425         struct dc  *dc = pipe_ctx->stream->ctx->dc;
3426
3427         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
3428                 return;
3429
3430         dc->hwss.set_avmute(pipe_ctx, enable);
3431 }
3432
3433 /**
3434  *  dc_link_enable_hpd_filter:
3435  *     If enable is true, programs HPD filter on associated HPD line using
3436  *     delay_on_disconnect/delay_on_connect values dependent on
3437  *     link->connector_signal
3438  *
3439  *     If enable is false, programs HPD filter on associated HPD line with no
3440  *     delays on connect or disconnect
3441  *
3442  *  @link:   pointer to the dc link
3443  *  @enable: boolean specifying whether to enable hbd
3444  */
3445 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
3446 {
3447         struct gpio *hpd;
3448
3449         if (enable) {
3450                 link->is_hpd_filter_disabled = false;
3451                 program_hpd_filter(link);
3452         } else {
3453                 link->is_hpd_filter_disabled = true;
3454                 /* Obtain HPD handle */
3455                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
3456
3457                 if (!hpd)
3458                         return;
3459
3460                 /* Setup HPD filtering */
3461                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
3462                         struct gpio_hpd_config config;
3463
3464                         config.delay_on_connect = 0;
3465                         config.delay_on_disconnect = 0;
3466
3467                         dal_irq_setup_hpd_filter(hpd, &config);
3468
3469                         dal_gpio_close(hpd);
3470                 } else {
3471                         ASSERT_CRITICAL(false);
3472                 }
3473                 /* Release HPD handle */
3474                 dal_gpio_destroy_irq(&hpd);
3475         }
3476 }
3477
3478 uint32_t dc_bandwidth_in_kbps_from_timing(
3479         const struct dc_crtc_timing *timing)
3480 {
3481         uint32_t bits_per_channel = 0;
3482         uint32_t kbps;
3483         struct fixed31_32 link_bw_kbps;
3484
3485         if (timing->flags.DSC) {
3486                 link_bw_kbps = dc_fixpt_from_int(timing->pix_clk_100hz);
3487                 link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160);
3488                 link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps, timing->dsc_cfg.bits_per_pixel);
3489                 kbps = dc_fixpt_ceil(link_bw_kbps);
3490                 return kbps;
3491         }
3492
3493         switch (timing->display_color_depth) {
3494         case COLOR_DEPTH_666:
3495                 bits_per_channel = 6;
3496                 break;
3497         case COLOR_DEPTH_888:
3498                 bits_per_channel = 8;
3499                 break;
3500         case COLOR_DEPTH_101010:
3501                 bits_per_channel = 10;
3502                 break;
3503         case COLOR_DEPTH_121212:
3504                 bits_per_channel = 12;
3505                 break;
3506         case COLOR_DEPTH_141414:
3507                 bits_per_channel = 14;
3508                 break;
3509         case COLOR_DEPTH_161616:
3510                 bits_per_channel = 16;
3511                 break;
3512         default:
3513                 ASSERT(bits_per_channel != 0);
3514                 bits_per_channel = 8;
3515                 break;
3516         }
3517
3518         kbps = timing->pix_clk_100hz / 10;
3519         kbps *= bits_per_channel;
3520
3521         if (timing->flags.Y_ONLY != 1) {
3522                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
3523                 kbps *= 3;
3524                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3525                         kbps /= 2;
3526                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
3527                         kbps = kbps * 2 / 3;
3528         }
3529
3530         return kbps;
3531
3532 }
3533
3534 void dc_link_set_drive_settings(struct dc *dc,
3535                                 struct link_training_settings *lt_settings,
3536                                 const struct dc_link *link)
3537 {
3538
3539         int i;
3540
3541         for (i = 0; i < dc->link_count; i++) {
3542                 if (dc->links[i] == link)
3543                         break;
3544         }
3545
3546         if (i >= dc->link_count)
3547                 ASSERT_CRITICAL(false);
3548
3549         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
3550 }
3551
3552 void dc_link_perform_link_training(struct dc *dc,
3553                                    struct dc_link_settings *link_setting,
3554                                    bool skip_video_pattern)
3555 {
3556         int i;
3557
3558         for (i = 0; i < dc->link_count; i++)
3559                 dc_link_dp_perform_link_training(
3560                         dc->links[i],
3561                         link_setting,
3562                         skip_video_pattern);
3563 }
3564
3565 void dc_link_set_preferred_link_settings(struct dc *dc,
3566                                          struct dc_link_settings *link_setting,
3567                                          struct dc_link *link)
3568 {
3569         int i;
3570         struct pipe_ctx *pipe;
3571         struct dc_stream_state *link_stream;
3572         struct dc_link_settings store_settings = *link_setting;
3573
3574         link->preferred_link_setting = store_settings;
3575
3576         /* Retrain with preferred link settings only relevant for
3577          * DP signal type
3578          * Check for non-DP signal or if passive dongle present
3579          */
3580         if (!dc_is_dp_signal(link->connector_signal) ||
3581                 link->dongle_max_pix_clk > 0)
3582                 return;
3583
3584         for (i = 0; i < MAX_PIPES; i++) {
3585                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3586                 if (pipe->stream && pipe->stream->link) {
3587                         if (pipe->stream->link == link) {
3588                                 link_stream = pipe->stream;
3589                                 break;
3590                         }
3591                 }
3592         }
3593
3594         /* Stream not found */
3595         if (i == MAX_PIPES)
3596                 return;
3597
3598         /* Cannot retrain link if backend is off */
3599         if (link_stream->dpms_off)
3600                 return;
3601
3602         decide_link_settings(link_stream, &store_settings);
3603
3604         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3605                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
3606                 dp_retrain_link_dp_test(link, &store_settings, false);
3607 }
3608
3609 void dc_link_set_preferred_training_settings(struct dc *dc,
3610                                                  struct dc_link_settings *link_setting,
3611                                                  struct dc_link_training_overrides *lt_overrides,
3612                                                  struct dc_link *link,
3613                                                  bool skip_immediate_retrain)
3614 {
3615         if (lt_overrides != NULL)
3616                 link->preferred_training_settings = *lt_overrides;
3617         else
3618                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
3619
3620         if (link_setting != NULL) {
3621                 link->preferred_link_setting = *link_setting;
3622         } else {
3623                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3624                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3625         }
3626
3627         /* Retrain now, or wait until next stream update to apply */
3628         if (skip_immediate_retrain == false)
3629                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
3630 }
3631
3632 void dc_link_enable_hpd(const struct dc_link *link)
3633 {
3634         dc_link_dp_enable_hpd(link);
3635 }
3636
3637 void dc_link_disable_hpd(const struct dc_link *link)
3638 {
3639         dc_link_dp_disable_hpd(link);
3640 }
3641
3642 void dc_link_set_test_pattern(struct dc_link *link,
3643                               enum dp_test_pattern test_pattern,
3644                               enum dp_test_pattern_color_space test_pattern_color_space,
3645                               const struct link_training_settings *p_link_settings,
3646                               const unsigned char *p_custom_pattern,
3647                               unsigned int cust_pattern_size)
3648 {
3649         if (link != NULL)
3650                 dc_link_dp_set_test_pattern(
3651                         link,
3652                         test_pattern,
3653                         test_pattern_color_space,
3654                         p_link_settings,
3655                         p_custom_pattern,
3656                         cust_pattern_size);
3657 }
3658
3659 uint32_t dc_link_bandwidth_kbps(
3660         const struct dc_link *link,
3661         const struct dc_link_settings *link_setting)
3662 {
3663         uint32_t link_bw_kbps =
3664                 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
3665
3666         link_bw_kbps *= 8;   /* 8 bits per byte*/
3667         link_bw_kbps *= link_setting->lane_count;
3668
3669         if (dc_link_should_enable_fec(link)) {
3670                 /* Account for FEC overhead.
3671                  * We have to do it based on caps,
3672                  * and not based on FEC being set ready,
3673                  * because FEC is set ready too late in
3674                  * the process to correctly be picked up
3675                  * by mode enumeration.
3676                  *
3677                  * There's enough zeros at the end of 'kbps'
3678                  * that make the below operation 100% precise
3679                  * for our purposes.
3680                  * 'long long' makes it work even for HDMI 2.1
3681                  * max bandwidth (and much, much bigger bandwidths
3682                  * than that, actually).
3683                  *
3684                  * NOTE: Reducing link BW by 3% may not be precise
3685                  * because it may be a stream BT that increases by 3%, and so
3686                  * 1/1.03 = 0.970873 factor should have been used instead,
3687                  * but the difference is minimal and is in a safe direction,
3688                  * which all works well around potential ambiguity of DP 1.4a spec.
3689                  */
3690                 long long fec_link_bw_kbps = link_bw_kbps * 970LL;
3691                 link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL));
3692         }
3693
3694         return link_bw_kbps;
3695
3696 }
3697
3698 const struct dc_link_settings *dc_link_get_link_cap(
3699                 const struct dc_link *link)
3700 {
3701         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
3702                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
3703                 return &link->preferred_link_setting;
3704         return &link->verified_link_cap;
3705 }
3706
3707 void dc_link_overwrite_extended_receiver_cap(
3708                 struct dc_link *link)
3709 {
3710         dp_overwrite_extended_receiver_cap(link);
3711 }
3712
3713 bool dc_link_is_fec_supported(const struct dc_link *link)
3714 {
3715         return (dc_is_dp_signal(link->connector_signal) &&
3716                         link->link_enc->features.fec_supported &&
3717                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
3718                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
3719 }
3720
3721 bool dc_link_should_enable_fec(const struct dc_link *link)
3722 {
3723         bool is_fec_disable = false;
3724         bool ret = false;
3725
3726         if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
3727                         link->local_sink &&
3728                         link->local_sink->edid_caps.panel_patch.disable_fec) ||
3729                         link->connector_signal == SIGNAL_TYPE_EDP) // Disable FEC for eDP
3730                 is_fec_disable = true;
3731
3732         if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
3733                 ret = true;
3734
3735         return ret;
3736 }