drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atomfirmware.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48 #include "dce/dmub_psr.h"
  49 #include "dmub/dmub_srv.h"
  50 #include "inc/hw/panel_cntl.h"
  51
  52 #define DC_LOGGER_INIT(logger)
  53
  54 #define LINK_INFO(...) \
  55         DC_LOG_HW_HOTPLUG(  \
  56                 __VA_ARGS__)
  57
  58 #define RETIMER_REDRIVER_INFO(...) \
  59         DC_LOG_RETIMER_REDRIVER(  \
  60                 __VA_ARGS__)
  61 /*******************************************************************************
  62  * Private structures
  63  ******************************************************************************/
  64
  65 enum {
  66         PEAK_FACTOR_X1000 = 1006,
  67         /*
  68          * Some receivers fail to train on first try and are good
  69          * on subsequent tries. 2 retries should be plenty. If we
  70          * don't have a successful training then we don't expect to
  71          * ever get one.
  72          */
  73         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  74 };
  75
  76 /*******************************************************************************
  77  * Private functions
  78  ******************************************************************************/
  79 static void dc_link_destruct(struct dc_link *link)
  80 {
  81         int i;
  82
  83         if (link->hpd_gpio) {
  84                 dal_gpio_destroy_irq(&link->hpd_gpio);
  85                 link->hpd_gpio = NULL;
  86         }
  87
  88         if (link->ddc)
  89                 dal_ddc_service_destroy(&link->ddc);
  90
  91         if (link->panel_cntl)
  92                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
  93
  94         if (link->link_enc) {
  95                 /* Update link encoder resource tracking variables. These are used for
  96                  * the dynamic assignment of link encoders to streams. Virtual links
  97                  * are not assigned encoder resources on creation.
  98                  */
  99                 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
 100                         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
 101                         link->dc->res_pool->dig_link_enc_count--;
 102                 }
 103                 link->link_enc->funcs->destroy(&link->link_enc);
 104         }
 105
 106         if (link->local_sink)
 107                 dc_sink_release(link->local_sink);
 108
 109         for (i = 0; i < link->sink_count; ++i)
 110                 dc_sink_release(link->remote_sinks[i]);
 111 }
 112
 113 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 114                           struct graphics_object_id link_id,
 115                           struct gpio_service *gpio_service)
 116 {
 117         enum bp_result bp_result;
 118         struct graphics_object_hpd_info hpd_info;
 119         struct gpio_pin_info pin_info;
 120
 121         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 122                 return NULL;
 123
 124         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 125                 hpd_info.hpd_int_gpio_uid, &pin_info);
 126
 127         if (bp_result != BP_RESULT_OK) {
 128                 ASSERT(bp_result == BP_RESULT_NORECORD);
 129                 return NULL;
 130         }
 131
 132         return dal_gpio_service_create_irq(gpio_service,
 133                                            pin_info.offset,
 134                                            pin_info.mask);
 135 }
 136
 137 /*
 138  *  Function: program_hpd_filter
 139  *
 140  *  @brief
 141  *     Programs HPD filter on associated HPD line
 142  *
 143  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 144  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 145  *
 146  *  @return
 147  *     true on success, false otherwise
 148  */
 149 static bool program_hpd_filter(const struct dc_link *link)
 150 {
 151         bool result = false;
 152         struct gpio *hpd;
 153         int delay_on_connect_in_ms = 0;
 154         int delay_on_disconnect_in_ms = 0;
 155
 156         if (link->is_hpd_filter_disabled)
 157                 return false;
 158         /* Verify feature is supported */
 159         switch (link->connector_signal) {
 160         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 161         case SIGNAL_TYPE_DVI_DUAL_LINK:
 162         case SIGNAL_TYPE_HDMI_TYPE_A:
 163                 /* Program hpd filter */
 164                 delay_on_connect_in_ms = 500;
 165                 delay_on_disconnect_in_ms = 100;
 166                 break;
 167         case SIGNAL_TYPE_DISPLAY_PORT:
 168         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 169                 /* Program hpd filter to allow DP signal to settle */
 170                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 171                  * only 100ms on DELL U2413
 172                  * 0: some passive dongle still show aux mode instead of i2c
 173                  * 20-50: not enough to hide bouncing HPD with passive dongle.
 174                  * also see intermittent i2c read issues.
 175                  */
 176                 delay_on_connect_in_ms = 80;
 177                 delay_on_disconnect_in_ms = 0;
 178                 break;
 179         case SIGNAL_TYPE_LVDS:
 180         case SIGNAL_TYPE_EDP:
 181         default:
 182                 /* Don't program hpd filter */
 183                 return false;
 184         }
 185
 186         /* Obtain HPD handle */
 187         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 188                            link->ctx->gpio_service);
 189
 190         if (!hpd)
 191                 return result;
 192
 193         /* Setup HPD filtering */
 194         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 195                 struct gpio_hpd_config config;
 196
 197                 config.delay_on_connect = delay_on_connect_in_ms;
 198                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 199
 200                 dal_irq_setup_hpd_filter(hpd, &config);
 201
 202                 dal_gpio_close(hpd);
 203
 204                 result = true;
 205         } else {
 206                 ASSERT_CRITICAL(false);
 207         }
 208
 209         /* Release HPD handle */
 210         dal_gpio_destroy_irq(&hpd);
 211
 212         return result;
 213 }
 214
 215 bool dc_link_wait_for_t12(struct dc_link *link)
 216 {
 217         if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 218                 link->dc->hwss.edp_wait_for_T12(link);
 219
 220                 return true;
 221         }
 222
 223         return false;
 224 }
 225
 226 /**
 227  * dc_link_detect_sink() - Determine if there is a sink connected
 228  *
 229  * @link: pointer to the dc link
 230  * @type: Returned connection type
 231  * Does not detect downstream devices, such as MST sinks
 232  * or display connected through active dongles
 233  */
 234 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 235 {
 236         uint32_t is_hpd_high = 0;
 237         struct gpio *hpd_pin;
 238
 239         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 240                 *type = dc_connection_single;
 241                 return true;
 242         }
 243
 244         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 245                 /*in case it is not on*/
 246                 link->dc->hwss.edp_power_control(link, true);
 247                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 248         }
 249
 250         /* todo: may need to lock gpio access */
 251         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 252                                link->ctx->gpio_service);
 253         if (!hpd_pin)
 254                 goto hpd_gpio_failure;
 255
 256         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 257         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 258         dal_gpio_close(hpd_pin);
 259         dal_gpio_destroy_irq(&hpd_pin);
 260
 261         if (is_hpd_high) {
 262                 *type = dc_connection_single;
 263                 /* TODO: need to do the actual detection */
 264         } else {
 265                 *type = dc_connection_none;
 266         }
 267
 268         return true;
 269
 270 hpd_gpio_failure:
 271         return false;
 272 }
 273
 274 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 275 {
 276         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 277
 278         switch (sink_signal) {
 279         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 280         case SIGNAL_TYPE_DVI_DUAL_LINK:
 281         case SIGNAL_TYPE_HDMI_TYPE_A:
 282         case SIGNAL_TYPE_LVDS:
 283         case SIGNAL_TYPE_RGB:
 284                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 285                 break;
 286
 287         case SIGNAL_TYPE_DISPLAY_PORT:
 288         case SIGNAL_TYPE_EDP:
 289                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 290                 break;
 291
 292         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 293                 /* MST does not use I2COverAux, but there is the
 294                  * SPECIAL use case for "immediate dwnstrm device
 295                  * access" (EPR#370830).
 296                  */
 297                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 298                 break;
 299
 300         default:
 301                 break;
 302         }
 303
 304         return transaction_type;
 305 }
 306
 307 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 308                                               struct graphics_object_id downstream)
 309 {
 310         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 311                 switch (downstream.id) {
 312                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 313                         switch (encoder.id) {
 314                         case ENCODER_ID_INTERNAL_DAC1:
 315                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 316                         case ENCODER_ID_INTERNAL_DAC2:
 317                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 318                                 return SIGNAL_TYPE_RGB;
 319                         default:
 320                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 321                         }
 322                 break;
 323                 case CONNECTOR_ID_DUAL_LINK_DVII:
 324                 {
 325                         switch (encoder.id) {
 326                         case ENCODER_ID_INTERNAL_DAC1:
 327                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 328                         case ENCODER_ID_INTERNAL_DAC2:
 329                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 330                                 return SIGNAL_TYPE_RGB;
 331                         default:
 332                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 333                         }
 334                 }
 335                 break;
 336                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 337                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 338                 case CONNECTOR_ID_DUAL_LINK_DVID:
 339                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 340                 case CONNECTOR_ID_VGA:
 341                         return SIGNAL_TYPE_RGB;
 342                 case CONNECTOR_ID_HDMI_TYPE_A:
 343                         return SIGNAL_TYPE_HDMI_TYPE_A;
 344                 case CONNECTOR_ID_LVDS:
 345                         return SIGNAL_TYPE_LVDS;
 346                 case CONNECTOR_ID_DISPLAY_PORT:
 347                         return SIGNAL_TYPE_DISPLAY_PORT;
 348                 case CONNECTOR_ID_EDP:
 349                         return SIGNAL_TYPE_EDP;
 350                 default:
 351                         return SIGNAL_TYPE_NONE;
 352                 }
 353         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 354                 switch (downstream.id) {
 355                 case ENCODER_ID_EXTERNAL_NUTMEG:
 356                 case ENCODER_ID_EXTERNAL_TRAVIS:
 357                         return SIGNAL_TYPE_DISPLAY_PORT;
 358                 default:
 359                         return SIGNAL_TYPE_NONE;
 360                 }
 361         }
 362
 363         return SIGNAL_TYPE_NONE;
 364 }
 365
 366 /*
 367  * dc_link_is_dp_sink_present() - Check if there is a native DP
 368  * or passive DP-HDMI dongle connected
 369  */
 370 bool dc_link_is_dp_sink_present(struct dc_link *link)
 371 {
 372         enum gpio_result gpio_result;
 373         uint32_t clock_pin = 0;
 374         uint8_t retry = 0;
 375         struct ddc *ddc;
 376
 377         enum connector_id connector_id =
 378                 dal_graphics_object_id_get_connector_id(link->link_id);
 379
 380         bool present =
 381                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 382                 (connector_id == CONNECTOR_ID_EDP));
 383
 384         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 385
 386         if (!ddc) {
 387                 BREAK_TO_DEBUGGER();
 388                 return present;
 389         }
 390
 391         /* Open GPIO and set it to I2C mode */
 392         /* Note: this GpioMode_Input will be converted
 393          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 394          * which indicates we need additional delay
 395          */
 396
 397         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 398                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 399                 dal_ddc_close(ddc);
 400
 401                 return present;
 402         }
 403
 404         /*
 405          * Read GPIO: DP sink is present if both clock and data pins are zero
 406          *
 407          * [W/A] plug-unplug DP cable, sometimes customer board has
 408          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 409          * then monitor can't br light up. Add retry 3 times
 410          * But in real passive dongle, it need additional 3ms to detect
 411          */
 412         do {
 413                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 414                 ASSERT(gpio_result == GPIO_RESULT_OK);
 415                 if (clock_pin)
 416                         udelay(1000);
 417                 else
 418                         break;
 419         } while (retry++ < 3);
 420
 421         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 422
 423         dal_ddc_close(ddc);
 424
 425         return present;
 426 }
 427
 428 /*
 429  * @brief
 430  * Detect output sink type
 431  */
 432 static enum signal_type link_detect_sink(struct dc_link *link,
 433                                          enum dc_detect_reason reason)
 434 {
 435         enum signal_type result = get_basic_signal_type(link->link_enc->id,
 436                                                         link->link_id);
 437
 438         /* Internal digital encoder will detect only dongles
 439          * that require digital signal
 440          */
 441
 442         /* Detection mechanism is different
 443          * for different native connectors.
 444          * LVDS connector supports only LVDS signal;
 445          * PCIE is a bus slot, the actual connector needs to be detected first;
 446          * eDP connector supports only eDP signal;
 447          * HDMI should check straps for audio
 448          */
 449
 450         /* PCIE detects the actual connector on add-on board */
 451         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 452                 /* ZAZTODO implement PCIE add-on card detection */
 453         }
 454
 455         switch (link->link_id.id) {
 456         case CONNECTOR_ID_HDMI_TYPE_A: {
 457                 /* check audio support:
 458                  * if native HDMI is not supported, switch to DVI
 459                  */
 460                 struct audio_support *aud_support =
 461                                         &link->dc->res_pool->audio_support;
 462
 463                 if (!aud_support->hdmi_audio_native)
 464                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 465                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 466         }
 467         break;
 468         case CONNECTOR_ID_DISPLAY_PORT: {
 469                 /* DP HPD short pulse. Passive DP dongle will not
 470                  * have short pulse
 471                  */
 472                 if (reason != DETECT_REASON_HPDRX) {
 473                         /* Check whether DP signal detected: if not -
 474                          * we assume signal is DVI; it could be corrected
 475                          * to HDMI after dongle detection
 476                          */
 477                         if (!dm_helpers_is_dp_sink_present(link))
 478                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 479                 }
 480         }
 481         break;
 482         default:
 483         break;
 484         }
 485
 486         return result;
 487 }
 488
 489 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 490                                                                  struct audio_support *audio_support)
 491 {
 492         enum signal_type signal = SIGNAL_TYPE_NONE;
 493
 494         switch (dongle_type) {
 495         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 496                 if (audio_support->hdmi_audio_on_dongle)
 497                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 498                 else
 499                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 500                 break;
 501         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 502                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 503                 break;
 504         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 505                 if (audio_support->hdmi_audio_native)
 506                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 507                 else
 508                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 509                 break;
 510         default:
 511                 signal = SIGNAL_TYPE_NONE;
 512                 break;
 513         }
 514
 515         return signal;
 516 }
 517
 518 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 519                                                     struct display_sink_capability *sink_cap,
 520                                                     struct audio_support *audio_support)
 521 {
 522         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 523
 524         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 525                                                         audio_support);
 526 }
 527
 528 static void link_disconnect_sink(struct dc_link *link)
 529 {
 530         if (link->local_sink) {
 531                 dc_sink_release(link->local_sink);
 532                 link->local_sink = NULL;
 533         }
 534
 535         link->dpcd_sink_count = 0;
 536 }
 537
 538 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 539 {
 540         dc_sink_release(link->local_sink);
 541         link->local_sink = prev_sink;
 542 }
 543
 544 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 545 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 546 {
 547         bool ret = false;
 548
 549         switch (signal) {
 550         case SIGNAL_TYPE_DISPLAY_PORT:
 551         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 552                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 553                 break;
 554         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 555         case SIGNAL_TYPE_DVI_DUAL_LINK:
 556         case SIGNAL_TYPE_HDMI_TYPE_A:
 557         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 558          * we can poll for bksv but some displays have an issue with this. Since its so rare
 559          * for a display to not be 1.4 capable, this assumtion is ok
 560          */
 561                 ret = true;
 562                 break;
 563         default:
 564                 break;
 565         }
 566         return ret;
 567 }
 568
 569 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 570 {
 571         bool ret = false;
 572
 573         switch (signal) {
 574         case SIGNAL_TYPE_DISPLAY_PORT:
 575         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 576                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 577                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 578                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 579                 break;
 580         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 581         case SIGNAL_TYPE_DVI_DUAL_LINK:
 582         case SIGNAL_TYPE_HDMI_TYPE_A:
 583                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 584                 break;
 585         default:
 586                 break;
 587         }
 588
 589         return ret;
 590 }
 591
 592 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 593 {
 594         struct hdcp_protection_message msg22;
 595         struct hdcp_protection_message msg14;
 596
 597         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 598         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 599         memset(link->hdcp_caps.rx_caps.raw, 0,
 600                 sizeof(link->hdcp_caps.rx_caps.raw));
 601
 602         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 603                         link->ddc->transaction_type ==
 604                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 605                         link->connector_signal == SIGNAL_TYPE_EDP) {
 606                 msg22.data = link->hdcp_caps.rx_caps.raw;
 607                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 608                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 609         } else {
 610                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 611                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 612                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 613         }
 614         msg22.version = HDCP_VERSION_22;
 615         msg22.link = HDCP_LINK_PRIMARY;
 616         msg22.max_retries = 5;
 617         dc_process_hdcp_msg(signal, link, &msg22);
 618
 619         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 620                 msg14.data = &link->hdcp_caps.bcaps.raw;
 621                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 622                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 623                 msg14.version = HDCP_VERSION_14;
 624                 msg14.link = HDCP_LINK_PRIMARY;
 625                 msg14.max_retries = 5;
 626
 627                 dc_process_hdcp_msg(signal, link, &msg14);
 628         }
 629
 630 }
 631 #endif
 632
 633 static void read_current_link_settings_on_detect(struct dc_link *link)
 634 {
 635         union lane_count_set lane_count_set = { {0} };
 636         uint8_t link_bw_set;
 637         uint8_t link_rate_set;
 638         uint32_t read_dpcd_retry_cnt = 10;
 639         enum dc_status status = DC_ERROR_UNEXPECTED;
 640         int i;
 641         union max_down_spread max_down_spread = { {0} };
 642
 643         // Read DPCD 00101h to find out the number of lanes currently set
 644         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 645                 status = core_link_read_dpcd(link,
 646                                              DP_LANE_COUNT_SET,
 647                                              &lane_count_set.raw,
 648                                              sizeof(lane_count_set));
 649                 /* First DPCD read after VDD ON can fail if the particular board
 650                  * does not have HPD pin wired correctly. So if DPCD read fails,
 651                  * which it should never happen, retry a few times. Target worst
 652                  * case scenario of 80 ms.
 653                  */
 654                 if (status == DC_OK) {
 655                         link->cur_link_settings.lane_count =
 656                                         lane_count_set.bits.LANE_COUNT_SET;
 657                         break;
 658                 }
 659
 660                 msleep(8);
 661         }
 662
 663         // Read DPCD 00100h to find if standard link rates are set
 664         core_link_read_dpcd(link, DP_LINK_BW_SET,
 665                             &link_bw_set, sizeof(link_bw_set));
 666
 667         if (link_bw_set == 0) {
 668                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 669                         /* If standard link rates are not being used,
 670                          * Read DPCD 00115h to find the edp link rate set used
 671                          */
 672                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 673                                             &link_rate_set, sizeof(link_rate_set));
 674
 675                         // edp_supported_link_rates_count = 0 for DP
 676                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 677                                 link->cur_link_settings.link_rate =
 678                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 679                                 link->cur_link_settings.link_rate_set = link_rate_set;
 680                                 link->cur_link_settings.use_link_rate_set = true;
 681                         }
 682                 } else {
 683                         // Link Rate not found. Seamless boot may not work.
 684                         ASSERT(false);
 685                 }
 686         } else {
 687                 link->cur_link_settings.link_rate = link_bw_set;
 688                 link->cur_link_settings.use_link_rate_set = false;
 689         }
 690         // Read DPCD 00003h to find the max down spread.
 691         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 692                             &max_down_spread.raw, sizeof(max_down_spread));
 693         link->cur_link_settings.link_spread =
 694                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 695                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 696 }
 697
 698 static bool detect_dp(struct dc_link *link,
 699                       struct display_sink_capability *sink_caps,
 700                       bool *converter_disable_audio,
 701                       struct audio_support *audio_support,
 702                       enum dc_detect_reason reason)
 703 {
 704         bool boot = false;
 705
 706         sink_caps->signal = link_detect_sink(link, reason);
 707         sink_caps->transaction_type =
 708                 get_ddc_transaction_type(sink_caps->signal);
 709
 710         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 711                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 712                 if (!detect_dp_sink_caps(link))
 713                         return false;
 714                 if (is_mst_supported(link)) {
 715                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 716                         link->type = dc_connection_mst_branch;
 717
 718                         dal_ddc_service_set_transaction_type(link->ddc,
 719                                                              sink_caps->transaction_type);
 720
 721 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 722                         /* In case of fallback to SST when topology discovery below fails
 723                          * HDCP caps will be querried again later by the upper layer (caller
 724                          * of this function). */
 725                         query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
 726 #endif
 727                         /*
 728                          * This call will initiate MST topology discovery. Which
 729                          * will detect MST ports and add new DRM connector DRM
 730                          * framework. Then read EDID via remote i2c over aux. In
 731                          * the end, will notify DRM detect result and save EDID
 732                          * into DRM framework.
 733                          *
 734                          * .detect is called by .fill_modes.
 735                          * .fill_modes is called by user mode ioctl
 736                          * DRM_IOCTL_MODE_GETCONNECTOR.
 737                          *
 738                          * .get_modes is called by .fill_modes.
 739                          *
 740                          * call .get_modes, AMDGPU DM implementation will create
 741                          * new dc_sink and add to dc_link. For long HPD plug
 742                          * in/out, MST has its own handle.
 743                          *
 744                          * Therefore, just after dc_create, link->sink is not
 745                          * created for MST until user mode app calls
 746                          * DRM_IOCTL_MODE_GETCONNECTOR.
 747                          *
 748                          * Need check ->sink usages in case ->sink = NULL
 749                          * TODO: s3 resume check
 750                          */
 751                         if (reason == DETECT_REASON_BOOT)
 752                                 boot = true;
 753
 754                         dm_helpers_dp_update_branch_info(link->ctx, link);
 755
 756                         if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
 757                                                              link, boot)) {
 758                                 /* MST not supported */
 759                                 link->type = dc_connection_single;
 760                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 761                         }
 762                 }
 763
 764                 if (link->type != dc_connection_mst_branch &&
 765                     is_dp_active_dongle(link)) {
 766                         /* DP active dongles */
 767                         link->type = dc_connection_active_dongle;
 768                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 769                                 /*
 770                                  * active dongle unplug processing for short irq
 771                                  */
 772                                 link_disconnect_sink(link);
 773                                 return true;
 774                         }
 775
 776                         if (link->dpcd_caps.dongle_type !=
 777                             DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 778                                 *converter_disable_audio = true;
 779                 }
 780         } else {
 781                 /* DP passive dongles */
 782                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 783                                                                 sink_caps,
 784                                                                 audio_support);
 785                 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 786         }
 787
 788         return true;
 789 }
 790
 791 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 792 {
 793         if (old_edid->length != new_edid->length)
 794                 return false;
 795
 796         if (new_edid->length == 0)
 797                 return false;
 798
 799         return (memcmp(old_edid->raw_edid,
 800                        new_edid->raw_edid, new_edid->length) == 0);
 801 }
 802
 803 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 804 {
 805         /**
 806          * something is terribly wrong if time out is > 200ms. (5Hz)
 807          * 500 microseconds * 400 tries us 200 ms
 808          **/
 809         unsigned int sleep_time_in_microseconds = 500;
 810         unsigned int tries_allowed = 400;
 811         bool is_in_alt_mode;
 812         unsigned long long enter_timestamp;
 813         unsigned long long finish_timestamp;
 814         unsigned long long time_taken_in_ns;
 815         int tries_taken;
 816
 817         DC_LOGGER_INIT(link->ctx->logger);
 818
 819         if (!link->link_enc->funcs->is_in_alt_mode)
 820                 return true;
 821
 822         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 823         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 824
 825         if (is_in_alt_mode)
 826                 return true;
 827
 828         enter_timestamp = dm_get_timestamp(link->ctx);
 829
 830         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 831                 udelay(sleep_time_in_microseconds);
 832                 /* ask the link if alt mode is enabled, if so return ok */
 833                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 834                         finish_timestamp = dm_get_timestamp(link->ctx);
 835                         time_taken_in_ns =
 836                                 dm_get_elapse_time_in_ns(link->ctx,
 837                                                          finish_timestamp,
 838                                                          enter_timestamp);
 839                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 840                                        div_u64(time_taken_in_ns, 1000000));
 841                         return true;
 842                 }
 843         }
 844         finish_timestamp = dm_get_timestamp(link->ctx);
 845         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 846                                                     enter_timestamp);
 847         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 848                        div_u64(time_taken_in_ns, 1000000));
 849         return false;
 850 }
 851
 852 /*
 853  * dc_link_detect() - Detect if a sink is attached to a given link
 854  *
 855  * link->local_sink is created or destroyed as needed.
 856  *
 857  * This does not create remote sinks but will trigger DM
 858  * to start MST detection if a branch is detected.
 859  */
 860 static bool dc_link_detect_helper(struct dc_link *link,
 861                                   enum dc_detect_reason reason)
 862 {
 863         struct dc_sink_init_data sink_init_data = { 0 };
 864         struct display_sink_capability sink_caps = { 0 };
 865         uint8_t i;
 866         bool converter_disable_audio = false;
 867         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 868         bool same_edid = false;
 869         enum dc_edid_status edid_status;
 870         struct dc_context *dc_ctx = link->ctx;
 871         struct dc_sink *sink = NULL;
 872         struct dc_sink *prev_sink = NULL;
 873         struct dpcd_caps prev_dpcd_caps;
 874         bool same_dpcd = true;
 875         enum dc_connection_type new_connection_type = dc_connection_none;
 876         enum dc_connection_type pre_connection_type = dc_connection_none;
 877         bool perform_dp_seamless_boot = false;
 878         const uint32_t post_oui_delay = 30; // 30ms
 879
 880         DC_LOGGER_INIT(link->ctx->logger);
 881
 882         if (dc_is_virtual_signal(link->connector_signal))
 883                 return false;
 884
 885         if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
 886              link->connector_signal == SIGNAL_TYPE_EDP) &&
 887             link->local_sink) {
 888                 // need to re-write OUI and brightness in resume case
 889                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 890                         dpcd_set_source_specific_data(link);
 891                         msleep(post_oui_delay);
 892                         dc_link_set_default_brightness_aux(link);
 893                         //TODO: use cached
 894                 }
 895
 896                 return true;
 897         }
 898
 899         if (!dc_link_detect_sink(link, &new_connection_type)) {
 900                 BREAK_TO_DEBUGGER();
 901                 return false;
 902         }
 903
 904         prev_sink = link->local_sink;
 905         if (prev_sink) {
 906                 dc_sink_retain(prev_sink);
 907                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 908         }
 909
 910         link_disconnect_sink(link);
 911         if (new_connection_type != dc_connection_none) {
 912                 pre_connection_type = link->type;
 913                 link->type = new_connection_type;
 914                 link->link_state_valid = false;
 915
 916                 /* From Disconnected-to-Connected. */
 917                 switch (link->connector_signal) {
 918                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 919                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 920                         if (aud_support->hdmi_audio_native)
 921                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 922                         else
 923                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 924                         break;
 925                 }
 926
 927                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 928                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 929                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 930                         break;
 931                 }
 932
 933                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 934                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 935                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 936                         break;
 937                 }
 938
 939                 case SIGNAL_TYPE_LVDS: {
 940                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 941                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 942                         break;
 943                 }
 944
 945                 case SIGNAL_TYPE_EDP: {
 946                         read_current_link_settings_on_detect(link);
 947
 948                         detect_edp_sink_caps(link);
 949                         read_current_link_settings_on_detect(link);
 950                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 951                         sink_caps.signal = SIGNAL_TYPE_EDP;
 952                         break;
 953                 }
 954
 955                 case SIGNAL_TYPE_DISPLAY_PORT: {
 956                         /* wa HPD high coming too early*/
 957                         if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 958                                 /* if alt mode times out, return false */
 959                                 if (!wait_for_entering_dp_alt_mode(link))
 960                                         return false;
 961                         }
 962
 963                         if (!detect_dp(link, &sink_caps,
 964                                        &converter_disable_audio,
 965                                        aud_support, reason)) {
 966                                 if (prev_sink)
 967                                         dc_sink_release(prev_sink);
 968                                 return false;
 969                         }
 970
 971                         // Check if dpcp block is the same
 972                         if (prev_sink) {
 973                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps,
 974                                            sizeof(struct dpcd_caps)))
 975                                         same_dpcd = false;
 976                         }
 977                         /* Active dongle downstream unplug*/
 978                         if (link->type == dc_connection_active_dongle &&
 979                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 980                                 if (prev_sink)
 981                                         /* Downstream unplug */
 982                                         dc_sink_release(prev_sink);
 983                                 return true;
 984                         }
 985
 986                         // link switch from MST to non-MST stop topology manager
 987                         if (pre_connection_type == dc_connection_mst_branch &&
 988                                 link->type != dc_connection_mst_branch) {
 989                                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 990                         }
 991
 992                         if (link->type == dc_connection_mst_branch) {
 993                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 994                                           link->link_index);
 995                                 /* Need to setup mst link_cap struct here
 996                                  * otherwise dc_link_detect() will leave mst link_cap
 997                                  * empty which leads to allocate_mst_payload() has "0"
 998                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 999                                  */
1000                                 dp_verify_mst_link_cap(link);
1001
1002                                 if (prev_sink)
1003                                         dc_sink_release(prev_sink);
1004                                 return false;
1005                         }
1006
1007                         // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
1008                         if (reason == DETECT_REASON_BOOT &&
1009                             !dc_ctx->dc->config.power_down_display_on_boot &&
1010                             link->link_status.link_active)
1011                                 perform_dp_seamless_boot = true;
1012
1013                         if (perform_dp_seamless_boot) {
1014                                 read_current_link_settings_on_detect(link);
1015                                 link->verified_link_cap = link->reported_link_cap;
1016                         }
1017
1018                         break;
1019                 }
1020
1021                 default:
1022                         DC_ERROR("Invalid connector type! signal:%d\n",
1023                                  link->connector_signal);
1024                         if (prev_sink)
1025                                 dc_sink_release(prev_sink);
1026                         return false;
1027                 } /* switch() */
1028
1029                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1030                         link->dpcd_sink_count =
1031                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1032                 else
1033                         link->dpcd_sink_count = 1;
1034
1035                 dal_ddc_service_set_transaction_type(link->ddc,
1036                                                      sink_caps.transaction_type);
1037
1038                 link->aux_mode =
1039                         dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1040
1041                 sink_init_data.link = link;
1042                 sink_init_data.sink_signal = sink_caps.signal;
1043
1044                 sink = dc_sink_create(&sink_init_data);
1045                 if (!sink) {
1046                         DC_ERROR("Failed to create sink!\n");
1047                         if (prev_sink)
1048                                 dc_sink_release(prev_sink);
1049                         return false;
1050                 }
1051
1052                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1053                 sink->converter_disable_audio = converter_disable_audio;
1054
1055                 /* dc_sink_create returns a new reference */
1056                 link->local_sink = sink;
1057
1058                 edid_status = dm_helpers_read_local_edid(link->ctx,
1059                                                          link, sink);
1060
1061                 switch (edid_status) {
1062                 case EDID_BAD_CHECKSUM:
1063                         DC_LOG_ERROR("EDID checksum invalid.\n");
1064                         break;
1065                 case EDID_NO_RESPONSE:
1066                         DC_LOG_ERROR("No EDID read.\n");
1067                         /*
1068                          * Abort detection for non-DP connectors if we have
1069                          * no EDID
1070                          *
1071                          * DP needs to report as connected if HDP is high
1072                          * even if we have no EDID in order to go to
1073                          * fail-safe mode
1074                          */
1075                         if (dc_is_hdmi_signal(link->connector_signal) ||
1076                             dc_is_dvi_signal(link->connector_signal)) {
1077                                 if (prev_sink)
1078                                         dc_sink_release(prev_sink);
1079
1080                                 return false;
1081                         }
1082                         break;
1083                 default:
1084                         break;
1085                 }
1086
1087                 // Check if edid is the same
1088                 if ((prev_sink) &&
1089                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1090                         same_edid = is_same_edid(&prev_sink->dc_edid,
1091                                                  &sink->dc_edid);
1092
1093                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1094                         link->ctx->dc->debug.hdmi20_disable = true;
1095
1096                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1097                     sink_caps.transaction_type ==
1098                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1099                         /*
1100                          * TODO debug why Dell 2413 doesn't like
1101                          *  two link trainings
1102                          */
1103 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1104                         query_hdcp_capability(sink->sink_signal, link);
1105 #endif
1106
1107                         // verify link cap for SST non-seamless boot
1108                         if (!perform_dp_seamless_boot)
1109                                 dp_verify_link_cap_with_retries(link,
1110                                                                 &link->reported_link_cap,
1111                                                                 LINK_TRAINING_MAX_VERIFY_RETRY);
1112                 } else {
1113                         // If edid is the same, then discard new sink and revert back to original sink
1114                         if (same_edid) {
1115                                 link_disconnect_remap(prev_sink, link);
1116                                 sink = prev_sink;
1117                                 prev_sink = NULL;
1118                         }
1119 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1120                         query_hdcp_capability(sink->sink_signal, link);
1121 #endif
1122                 }
1123
1124                 /* HDMI-DVI Dongle */
1125                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1126                     !sink->edid_caps.edid_hdmi)
1127                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1128
1129                 /* Connectivity log: detection */
1130                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1131                         CONN_DATA_DETECT(link,
1132                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1133                                          DC_EDID_BLOCK_SIZE,
1134                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1135                 }
1136
1137                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1138                         "manufacturer_id = %X, "
1139                         "product_id = %X, "
1140                         "serial_number = %X, "
1141                         "manufacture_week = %d, "
1142                         "manufacture_year = %d, "
1143                         "display_name = %s, "
1144                         "speaker_flag = %d, "
1145                         "audio_mode_count = %d\n",
1146                         __func__,
1147                         sink->edid_caps.manufacturer_id,
1148                         sink->edid_caps.product_id,
1149                         sink->edid_caps.serial_number,
1150                         sink->edid_caps.manufacture_week,
1151                         sink->edid_caps.manufacture_year,
1152                         sink->edid_caps.display_name,
1153                         sink->edid_caps.speaker_flags,
1154                         sink->edid_caps.audio_mode_count);
1155
1156                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1157                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1158                                 "format_code = %d, "
1159                                 "channel_count = %d, "
1160                                 "sample_rate = %d, "
1161                                 "sample_size = %d\n",
1162                                 __func__,
1163                                 i,
1164                                 sink->edid_caps.audio_modes[i].format_code,
1165                                 sink->edid_caps.audio_modes[i].channel_count,
1166                                 sink->edid_caps.audio_modes[i].sample_rate,
1167                                 sink->edid_caps.audio_modes[i].sample_size);
1168                 }
1169         } else {
1170                 /* From Connected-to-Disconnected. */
1171                 if (link->type == dc_connection_mst_branch) {
1172                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
1173                                   link->link_index);
1174
1175                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1176
1177                         link->mst_stream_alloc_table.stream_count = 0;
1178                         memset(link->mst_stream_alloc_table.stream_allocations,
1179                                0,
1180                                sizeof(link->mst_stream_alloc_table.stream_allocations));
1181                 }
1182
1183                 link->type = dc_connection_none;
1184                 sink_caps.signal = SIGNAL_TYPE_NONE;
1185                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1186                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1187                  *  the dongle is still there and limits the number of modes we can emulate.
1188                  *  Clear dongle_max_pix_clk on disconnect to fix this
1189                  */
1190                 link->dongle_max_pix_clk = 0;
1191         }
1192
1193         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
1194                   link->link_index, sink,
1195                   (sink_caps.signal ==
1196                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1197                   prev_sink, same_dpcd, same_edid);
1198
1199         if (prev_sink)
1200                 dc_sink_release(prev_sink);
1201
1202         return true;
1203 }
1204
1205 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1206 {
1207         const struct dc *dc = link->dc;
1208         bool ret;
1209
1210         /* get out of low power state */
1211         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1212
1213         ret = dc_link_detect_helper(link, reason);
1214
1215         /* Go back to power optimized state */
1216         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1217
1218         return ret;
1219 }
1220
1221 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1222 {
1223         uint32_t state;
1224
1225         dal_gpio_lock_pin(dc_link->hpd_gpio);
1226         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1227         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1228
1229         return state;
1230 }
1231
1232 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1233 {
1234         struct gpio *hpd;
1235         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1236
1237         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1238                            link->ctx->gpio_service);
1239
1240         if (hpd) {
1241                 switch (dal_irq_get_source(hpd)) {
1242                 case DC_IRQ_SOURCE_HPD1:
1243                         hpd_id = HPD_SOURCEID1;
1244                 break;
1245                 case DC_IRQ_SOURCE_HPD2:
1246                         hpd_id = HPD_SOURCEID2;
1247                 break;
1248                 case DC_IRQ_SOURCE_HPD3:
1249                         hpd_id = HPD_SOURCEID3;
1250                 break;
1251                 case DC_IRQ_SOURCE_HPD4:
1252                         hpd_id = HPD_SOURCEID4;
1253                 break;
1254                 case DC_IRQ_SOURCE_HPD5:
1255                         hpd_id = HPD_SOURCEID5;
1256                 break;
1257                 case DC_IRQ_SOURCE_HPD6:
1258                         hpd_id = HPD_SOURCEID6;
1259                 break;
1260                 default:
1261                         BREAK_TO_DEBUGGER();
1262                 break;
1263                 }
1264
1265                 dal_gpio_destroy_irq(&hpd);
1266         }
1267
1268         return hpd_id;
1269 }
1270
1271 static enum channel_id get_ddc_line(struct dc_link *link)
1272 {
1273         struct ddc *ddc;
1274         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1275
1276         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1277
1278         if (ddc) {
1279                 switch (dal_ddc_get_line(ddc)) {
1280                 case GPIO_DDC_LINE_DDC1:
1281                         channel = CHANNEL_ID_DDC1;
1282                         break;
1283                 case GPIO_DDC_LINE_DDC2:
1284                         channel = CHANNEL_ID_DDC2;
1285                         break;
1286                 case GPIO_DDC_LINE_DDC3:
1287                         channel = CHANNEL_ID_DDC3;
1288                         break;
1289                 case GPIO_DDC_LINE_DDC4:
1290                         channel = CHANNEL_ID_DDC4;
1291                         break;
1292                 case GPIO_DDC_LINE_DDC5:
1293                         channel = CHANNEL_ID_DDC5;
1294                         break;
1295                 case GPIO_DDC_LINE_DDC6:
1296                         channel = CHANNEL_ID_DDC6;
1297                         break;
1298                 case GPIO_DDC_LINE_DDC_VGA:
1299                         channel = CHANNEL_ID_DDC_VGA;
1300                         break;
1301                 case GPIO_DDC_LINE_I2C_PAD:
1302                         channel = CHANNEL_ID_I2C_PAD;
1303                         break;
1304                 default:
1305                         BREAK_TO_DEBUGGER();
1306                         break;
1307                 }
1308         }
1309
1310         return channel;
1311 }
1312
1313 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1314 {
1315         switch (encoder.id) {
1316         case ENCODER_ID_INTERNAL_UNIPHY:
1317                 switch (encoder.enum_id) {
1318                 case ENUM_ID_1:
1319                         return TRANSMITTER_UNIPHY_A;
1320                 case ENUM_ID_2:
1321                         return TRANSMITTER_UNIPHY_B;
1322                 default:
1323                         return TRANSMITTER_UNKNOWN;
1324                 }
1325         break;
1326         case ENCODER_ID_INTERNAL_UNIPHY1:
1327                 switch (encoder.enum_id) {
1328                 case ENUM_ID_1:
1329                         return TRANSMITTER_UNIPHY_C;
1330                 case ENUM_ID_2:
1331                         return TRANSMITTER_UNIPHY_D;
1332                 default:
1333                         return TRANSMITTER_UNKNOWN;
1334                 }
1335         break;
1336         case ENCODER_ID_INTERNAL_UNIPHY2:
1337                 switch (encoder.enum_id) {
1338                 case ENUM_ID_1:
1339                         return TRANSMITTER_UNIPHY_E;
1340                 case ENUM_ID_2:
1341                         return TRANSMITTER_UNIPHY_F;
1342                 default:
1343                         return TRANSMITTER_UNKNOWN;
1344                 }
1345         break;
1346         case ENCODER_ID_INTERNAL_UNIPHY3:
1347                 switch (encoder.enum_id) {
1348                 case ENUM_ID_1:
1349                         return TRANSMITTER_UNIPHY_G;
1350                 default:
1351                         return TRANSMITTER_UNKNOWN;
1352                 }
1353         break;
1354         case ENCODER_ID_EXTERNAL_NUTMEG:
1355                 switch (encoder.enum_id) {
1356                 case ENUM_ID_1:
1357                         return TRANSMITTER_NUTMEG_CRT;
1358                 default:
1359                         return TRANSMITTER_UNKNOWN;
1360                 }
1361         break;
1362         case ENCODER_ID_EXTERNAL_TRAVIS:
1363                 switch (encoder.enum_id) {
1364                 case ENUM_ID_1:
1365                         return TRANSMITTER_TRAVIS_CRT;
1366                 case ENUM_ID_2:
1367                         return TRANSMITTER_TRAVIS_LCD;
1368                 default:
1369                         return TRANSMITTER_UNKNOWN;
1370                 }
1371         break;
1372         default:
1373                 return TRANSMITTER_UNKNOWN;
1374         }
1375 }
1376
1377 static bool dc_link_construct(struct dc_link *link,
1378                               const struct link_init_data *init_params)
1379 {
1380         uint8_t i;
1381         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1382         struct dc_context *dc_ctx = init_params->ctx;
1383         struct encoder_init_data enc_init_data = { 0 };
1384         struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1385         struct integrated_info *info;
1386         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1387         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1388         struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1389
1390         DC_LOGGER_INIT(dc_ctx->logger);
1391
1392         info = kzalloc(sizeof(*info), GFP_KERNEL);
1393         if (!info)
1394                 goto create_fail;
1395
1396         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1397         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1398
1399         link->link_status.dpcd_caps = &link->dpcd_caps;
1400
1401         link->dc = init_params->dc;
1402         link->ctx = dc_ctx;
1403         link->link_index = init_params->link_index;
1404
1405         memset(&link->preferred_training_settings, 0,
1406                sizeof(struct dc_link_training_overrides));
1407         memset(&link->preferred_link_setting, 0,
1408                sizeof(struct dc_link_settings));
1409
1410         link->link_id =
1411                 bios->funcs->get_connector_id(bios, init_params->connector_index);
1412
1413         link->ep_type = DISPLAY_ENDPOINT_PHY;
1414
1415         DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1416
1417         if (bios->funcs->get_disp_connector_caps_info) {
1418                 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1419                 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1420                 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1421         }
1422
1423         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1424                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1425                                      __func__, init_params->connector_index,
1426                                      link->link_id.type, OBJECT_TYPE_CONNECTOR);
1427                 goto create_fail;
1428         }
1429
1430         if (link->dc->res_pool->funcs->link_init)
1431                 link->dc->res_pool->funcs->link_init(link);
1432
1433         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1434                                       link->ctx->gpio_service);
1435
1436         if (link->hpd_gpio) {
1437                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1438                 dal_gpio_unlock_pin(link->hpd_gpio);
1439                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1440
1441                 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1442                 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1443         }
1444
1445         switch (link->link_id.id) {
1446         case CONNECTOR_ID_HDMI_TYPE_A:
1447                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1448
1449                 break;
1450         case CONNECTOR_ID_SINGLE_LINK_DVID:
1451         case CONNECTOR_ID_SINGLE_LINK_DVII:
1452                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1453                 break;
1454         case CONNECTOR_ID_DUAL_LINK_DVID:
1455         case CONNECTOR_ID_DUAL_LINK_DVII:
1456                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1457                 break;
1458         case CONNECTOR_ID_DISPLAY_PORT:
1459                 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1460
1461                 if (link->hpd_gpio)
1462                         link->irq_source_hpd_rx =
1463                                         dal_irq_get_rx_source(link->hpd_gpio);
1464
1465                 break;
1466         case CONNECTOR_ID_EDP:
1467                 link->connector_signal = SIGNAL_TYPE_EDP;
1468
1469                 if (link->hpd_gpio) {
1470                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1471                         link->irq_source_hpd_rx =
1472                                         dal_irq_get_rx_source(link->hpd_gpio);
1473                 }
1474
1475                 break;
1476         case CONNECTOR_ID_LVDS:
1477                 link->connector_signal = SIGNAL_TYPE_LVDS;
1478                 break;
1479         default:
1480                 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1481                                link->link_id.id);
1482                 goto create_fail;
1483         }
1484
1485         /* TODO: #DAL3 Implement id to str function.*/
1486         LINK_INFO("Connector[%d] description:"
1487                   "signal %d\n",
1488                   init_params->connector_index,
1489                   link->connector_signal);
1490
1491         ddc_service_init_data.ctx = link->ctx;
1492         ddc_service_init_data.id = link->link_id;
1493         ddc_service_init_data.link = link;
1494         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1495
1496         if (!link->ddc) {
1497                 DC_ERROR("Failed to create ddc_service!\n");
1498                 goto ddc_create_fail;
1499         }
1500
1501         if (!link->ddc->ddc_pin) {
1502                 DC_ERROR("Failed to get I2C info for connector!\n");
1503                 goto ddc_create_fail;
1504         }
1505
1506         link->ddc_hw_inst =
1507                 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1508
1509
1510         if (link->dc->res_pool->funcs->panel_cntl_create &&
1511                 (link->link_id.id == CONNECTOR_ID_EDP ||
1512                         link->link_id.id == CONNECTOR_ID_LVDS)) {
1513                 panel_cntl_init_data.ctx = dc_ctx;
1514                 panel_cntl_init_data.inst =
1515                         panel_cntl_init_data.ctx->dc_edp_id_count;
1516                 link->panel_cntl =
1517                         link->dc->res_pool->funcs->panel_cntl_create(
1518                                                                 &panel_cntl_init_data);
1519                 panel_cntl_init_data.ctx->dc_edp_id_count++;
1520
1521                 if (link->panel_cntl == NULL) {
1522                         DC_ERROR("Failed to create link panel_cntl!\n");
1523                         goto panel_cntl_create_fail;
1524                 }
1525         }
1526
1527         enc_init_data.ctx = dc_ctx;
1528         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1529                               &enc_init_data.encoder);
1530         enc_init_data.connector = link->link_id;
1531         enc_init_data.channel = get_ddc_line(link);
1532         enc_init_data.hpd_source = get_hpd_line(link);
1533
1534         link->hpd_src = enc_init_data.hpd_source;
1535
1536         enc_init_data.transmitter =
1537                 translate_encoder_to_transmitter(enc_init_data.encoder);
1538         link->link_enc =
1539                 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1540
1541         if (!link->link_enc) {
1542                 DC_ERROR("Failed to create link encoder!\n");
1543                 goto link_enc_create_fail;
1544         }
1545
1546         DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1547
1548         /* Update link encoder tracking variables. These are used for the dynamic
1549          * assignment of link encoders to streams.
1550          */
1551         link->eng_id = link->link_enc->preferred_engine;
1552         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1553         link->dc->res_pool->dig_link_enc_count++;
1554
1555         link->link_enc_hw_inst = link->link_enc->transmitter;
1556
1557         for (i = 0; i < 4; i++) {
1558                 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1559                                              link->link_id, i,
1560                                              &link->device_tag) != BP_RESULT_OK) {
1561                         DC_ERROR("Failed to find device tag!\n");
1562                         goto device_tag_fail;
1563                 }
1564
1565                 /* Look for device tag that matches connector signal,
1566                  * CRT for rgb, LCD for other supported signal tyes
1567                  */
1568                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1569                                                       link->device_tag.dev_id))
1570                         continue;
1571                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1572                     link->connector_signal != SIGNAL_TYPE_RGB)
1573                         continue;
1574                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1575                     link->connector_signal == SIGNAL_TYPE_RGB)
1576                         continue;
1577
1578                 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1579                 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1580                 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1581                 break;
1582         }
1583
1584         if (bios->integrated_info)
1585                 memcpy(info, bios->integrated_info, sizeof(*info));
1586
1587         /* Look for channel mapping corresponding to connector and device tag */
1588         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1589                 struct external_display_path *path =
1590                         &info->ext_disp_conn_info.path[i];
1591
1592                 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1593                     path->device_connector_id.id == link->link_id.id &&
1594                     path->device_connector_id.type == link->link_id.type) {
1595                         if (link->device_tag.acpi_device != 0 &&
1596                             path->device_acpi_enum == link->device_tag.acpi_device) {
1597                                 link->ddi_channel_mapping = path->channel_mapping;
1598                                 link->chip_caps = path->caps;
1599                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1600                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1601                         } else if (path->device_tag ==
1602                                    link->device_tag.dev_id.raw_device_tag) {
1603                                 link->ddi_channel_mapping = path->channel_mapping;
1604                                 link->chip_caps = path->caps;
1605                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1606                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1607                         }
1608                         break;
1609                 }
1610         }
1611
1612         if (bios->funcs->get_atom_dc_golden_table)
1613                 bios->funcs->get_atom_dc_golden_table(bios);
1614
1615         /*
1616          * TODO check if GPIO programmed correctly
1617          *
1618          * If GPIO isn't programmed correctly HPD might not rise or drain
1619          * fast enough, leading to bounces.
1620          */
1621         program_hpd_filter(link);
1622
1623         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1624
1625         DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1626         kfree(info);
1627         return true;
1628 device_tag_fail:
1629         link->link_enc->funcs->destroy(&link->link_enc);
1630 link_enc_create_fail:
1631         if (link->panel_cntl != NULL)
1632                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1633 panel_cntl_create_fail:
1634         dal_ddc_service_destroy(&link->ddc);
1635 ddc_create_fail:
1636 create_fail:
1637
1638         if (link->hpd_gpio) {
1639                 dal_gpio_destroy_irq(&link->hpd_gpio);
1640                 link->hpd_gpio = NULL;
1641         }
1642
1643         DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1644         kfree(info);
1645
1646         return false;
1647 }
1648
1649 /*******************************************************************************
1650  * Public functions
1651  ******************************************************************************/
1652 struct dc_link *link_create(const struct link_init_data *init_params)
1653 {
1654         struct dc_link *link =
1655                         kzalloc(sizeof(*link), GFP_KERNEL);
1656
1657         if (NULL == link)
1658                 goto alloc_fail;
1659
1660         if (false == dc_link_construct(link, init_params))
1661                 goto construct_fail;
1662
1663         return link;
1664
1665 construct_fail:
1666         kfree(link);
1667
1668 alloc_fail:
1669         return NULL;
1670 }
1671
1672 void link_destroy(struct dc_link **link)
1673 {
1674         dc_link_destruct(*link);
1675         kfree(*link);
1676         *link = NULL;
1677 }
1678
1679 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1680 {
1681         struct dc_stream_state *stream = pipe_ctx->stream;
1682
1683         if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1684                 struct dc_link *link = stream->link;
1685                 union down_spread_ctrl old_downspread;
1686                 union down_spread_ctrl new_downspread;
1687
1688                 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1689                                 &old_downspread.raw, sizeof(old_downspread));
1690
1691                 new_downspread.raw = old_downspread.raw;
1692
1693                 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1694                                 (stream->ignore_msa_timing_param) ? 1 : 0;
1695
1696                 if (new_downspread.raw != old_downspread.raw) {
1697                         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1698                                 &new_downspread.raw, sizeof(new_downspread));
1699                 }
1700
1701         } else {
1702                 dm_helpers_mst_enable_stream_features(stream);
1703         }
1704 }
1705
1706 static enum dc_status enable_link_dp(struct dc_state *state,
1707                                      struct pipe_ctx *pipe_ctx)
1708 {
1709         struct dc_stream_state *stream = pipe_ctx->stream;
1710         enum dc_status status;
1711         bool skip_video_pattern;
1712         struct dc_link *link = stream->link;
1713         struct dc_link_settings link_settings = {0};
1714         bool fec_enable;
1715         int i;
1716         bool apply_seamless_boot_optimization = false;
1717         uint32_t bl_oled_enable_delay = 50; // in ms
1718         const uint32_t post_oui_delay = 30; // 30ms
1719
1720         // check for seamless boot
1721         for (i = 0; i < state->stream_count; i++) {
1722                 if (state->streams[i]->apply_seamless_boot_optimization) {
1723                         apply_seamless_boot_optimization = true;
1724                         break;
1725                 }
1726         }
1727
1728         /* get link settings for video mode timing */
1729         decide_link_settings(stream, &link_settings);
1730
1731         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1732                 /*in case it is not on*/
1733                 link->dc->hwss.edp_power_control(link, true);
1734                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1735         }
1736
1737         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1738                         link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1739         if (state->clk_mgr && !apply_seamless_boot_optimization)
1740                 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1741                                                      state, false);
1742
1743         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1744         dpcd_set_source_specific_data(link);
1745         if (link->dpcd_sink_ext_caps.raw != 0)
1746                 msleep(post_oui_delay);
1747
1748         skip_video_pattern = true;
1749
1750         if (link_settings.link_rate == LINK_RATE_LOW)
1751                 skip_video_pattern = false;
1752
1753         if (perform_link_training_with_retries(&link_settings,
1754                                                skip_video_pattern,
1755                                                LINK_TRAINING_ATTEMPTS,
1756                                                pipe_ctx,
1757                                                pipe_ctx->stream->signal)) {
1758                 link->cur_link_settings = link_settings;
1759                 status = DC_OK;
1760         } else {
1761                 status = DC_FAIL_DP_LINK_TRAINING;
1762         }
1763
1764         if (link->preferred_training_settings.fec_enable)
1765                 fec_enable = *link->preferred_training_settings.fec_enable;
1766         else
1767                 fec_enable = true;
1768
1769         dp_set_fec_enable(link, fec_enable);
1770
1771         // during mode set we do DP_SET_POWER off then on, aux writes are lost
1772         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
1773                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
1774                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
1775                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
1776                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
1777                         msleep(bl_oled_enable_delay);
1778                 dc_link_backlight_enable_aux(link, true);
1779         }
1780
1781         return status;
1782 }
1783
1784 static enum dc_status enable_link_edp(
1785                 struct dc_state *state,
1786                 struct pipe_ctx *pipe_ctx)
1787 {
1788         enum dc_status status;
1789
1790         status = enable_link_dp(state, pipe_ctx);
1791
1792         return status;
1793 }
1794
1795 static enum dc_status enable_link_dp_mst(
1796                 struct dc_state *state,
1797                 struct pipe_ctx *pipe_ctx)
1798 {
1799         struct dc_link *link = pipe_ctx->stream->link;
1800
1801         /* sink signal type after MST branch is MST. Multiple MST sinks
1802          * share one link. Link DP PHY is enable or training only once.
1803          */
1804         if (link->link_status.link_active)
1805                 return DC_OK;
1806
1807         /* clear payload table */
1808         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1809
1810         /* to make sure the pending down rep can be processed
1811          * before enabling the link
1812          */
1813         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1814
1815         /* set the sink to MST mode before enabling the link */
1816         dp_enable_mst_on_sink(link, true);
1817
1818         return enable_link_dp(state, pipe_ctx);
1819 }
1820
1821 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1822                 enum engine_id eng_id,
1823                 struct ext_hdmi_settings *settings)
1824 {
1825         bool result = false;
1826         int i = 0;
1827         struct integrated_info *integrated_info =
1828                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1829
1830         if (integrated_info == NULL)
1831                 return false;
1832
1833         /*
1834          * Get retimer settings from sbios for passing SI eye test for DCE11
1835          * The setting values are varied based on board revision and port id
1836          * Therefore the setting values of each ports is passed by sbios.
1837          */
1838
1839         // Check if current bios contains ext Hdmi settings
1840         if (integrated_info->gpu_cap_info & 0x20) {
1841                 switch (eng_id) {
1842                 case ENGINE_ID_DIGA:
1843                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1844                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1845                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1846                         memmove(settings->reg_settings,
1847                                         integrated_info->dp0_ext_hdmi_reg_settings,
1848                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1849                         memmove(settings->reg_settings_6g,
1850                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1851                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1852                         result = true;
1853                         break;
1854                 case ENGINE_ID_DIGB:
1855                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1856                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1857                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1858                         memmove(settings->reg_settings,
1859                                         integrated_info->dp1_ext_hdmi_reg_settings,
1860                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1861                         memmove(settings->reg_settings_6g,
1862                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1863                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1864                         result = true;
1865                         break;
1866                 case ENGINE_ID_DIGC:
1867                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1868                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1869                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1870                         memmove(settings->reg_settings,
1871                                         integrated_info->dp2_ext_hdmi_reg_settings,
1872                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1873                         memmove(settings->reg_settings_6g,
1874                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1875                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1876                         result = true;
1877                         break;
1878                 case ENGINE_ID_DIGD:
1879                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1880                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1881                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1882                         memmove(settings->reg_settings,
1883                                         integrated_info->dp3_ext_hdmi_reg_settings,
1884                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1885                         memmove(settings->reg_settings_6g,
1886                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1887                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1888                         result = true;
1889                         break;
1890                 default:
1891                         break;
1892                 }
1893
1894                 if (result == true) {
1895                         // Validate settings from bios integrated info table
1896                         if (settings->slv_addr == 0)
1897                                 return false;
1898                         if (settings->reg_num > 9)
1899                                 return false;
1900                         if (settings->reg_num_6g > 3)
1901                                 return false;
1902
1903                         for (i = 0; i < settings->reg_num; i++) {
1904                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1905                                         return false;
1906                         }
1907
1908                         for (i = 0; i < settings->reg_num_6g; i++) {
1909                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1910                                         return false;
1911                         }
1912                 }
1913         }
1914
1915         return result;
1916 }
1917
1918 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1919                 uint8_t address, uint8_t *buffer, uint32_t length)
1920 {
1921         struct i2c_command cmd = {0};
1922         struct i2c_payload payload = {0};
1923
1924         memset(&payload, 0, sizeof(payload));
1925         memset(&cmd, 0, sizeof(cmd));
1926
1927         cmd.number_of_payloads = 1;
1928         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1929         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1930
1931         payload.address = address;
1932         payload.data = buffer;
1933         payload.length = length;
1934         payload.write = true;
1935         cmd.payloads = &payload;
1936
1937         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1938                         pipe_ctx->stream->link, &cmd))
1939                 return true;
1940
1941         return false;
1942 }
1943
1944 static void write_i2c_retimer_setting(
1945                 struct pipe_ctx *pipe_ctx,
1946                 bool is_vga_mode,
1947                 bool is_over_340mhz,
1948                 struct ext_hdmi_settings *settings)
1949 {
1950         uint8_t slave_address = (settings->slv_addr >> 1);
1951         uint8_t buffer[2];
1952         const uint8_t apply_rx_tx_change = 0x4;
1953         uint8_t offset = 0xA;
1954         uint8_t value = 0;
1955         int i = 0;
1956         bool i2c_success = false;
1957         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1958
1959         memset(&buffer, 0, sizeof(buffer));
1960
1961         /* Start Ext-Hdmi programming*/
1962
1963         for (i = 0; i < settings->reg_num; i++) {
1964                 /* Apply 3G settings */
1965                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1966
1967                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1968                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1969                         i2c_success = i2c_write(pipe_ctx, slave_address,
1970                                                 buffer, sizeof(buffer));
1971                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1972                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1973                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1974
1975                         if (!i2c_success)
1976                                 goto i2c_write_fail;
1977
1978                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1979                          * needs to be set to 1 on every 0xA-0xC write.
1980                          */
1981                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1982                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1983                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1984
1985                                 /* Query current value from offset 0xA */
1986                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1987                                         value = settings->reg_settings[i].i2c_reg_val;
1988                                 else {
1989                                         i2c_success =
1990                                                 dal_ddc_service_query_ddc_data(
1991                                                 pipe_ctx->stream->link->ddc,
1992                                                 slave_address, &offset, 1, &value, 1);
1993                                         if (!i2c_success)
1994                                                 goto i2c_write_fail;
1995                                 }
1996
1997                                 buffer[0] = offset;
1998                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1999                                 buffer[1] = value | apply_rx_tx_change;
2000                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2001                                                 buffer, sizeof(buffer));
2002                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2003                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2004                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2005                                 if (!i2c_success)
2006                                         goto i2c_write_fail;
2007                         }
2008                 }
2009         }
2010
2011         /* Apply 3G settings */
2012         if (is_over_340mhz) {
2013                 for (i = 0; i < settings->reg_num_6g; i++) {
2014                         /* Apply 3G settings */
2015                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2016
2017                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2018                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2019                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2020                                                         buffer, sizeof(buffer));
2021                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2022                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2023                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2024
2025                                 if (!i2c_success)
2026                                         goto i2c_write_fail;
2027
2028                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2029                                  * needs to be set to 1 on every 0xA-0xC write.
2030                                  */
2031                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2032                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2033                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2034
2035                                         /* Query current value from offset 0xA */
2036                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2037                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
2038                                         else {
2039                                                 i2c_success =
2040                                                                 dal_ddc_service_query_ddc_data(
2041                                                                 pipe_ctx->stream->link->ddc,
2042                                                                 slave_address, &offset, 1, &value, 1);
2043                                                 if (!i2c_success)
2044                                                         goto i2c_write_fail;
2045                                         }
2046
2047                                         buffer[0] = offset;
2048                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
2049                                         buffer[1] = value | apply_rx_tx_change;
2050                                         i2c_success = i2c_write(pipe_ctx, slave_address,
2051                                                         buffer, sizeof(buffer));
2052                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2053                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2054                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2055                                         if (!i2c_success)
2056                                                 goto i2c_write_fail;
2057                                 }
2058                         }
2059                 }
2060         }
2061
2062         if (is_vga_mode) {
2063                 /* Program additional settings if using 640x480 resolution */
2064
2065                 /* Write offset 0xFF to 0x01 */
2066                 buffer[0] = 0xff;
2067                 buffer[1] = 0x01;
2068                 i2c_success = i2c_write(pipe_ctx, slave_address,
2069                                 buffer, sizeof(buffer));
2070                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2071                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2072                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2073                 if (!i2c_success)
2074                         goto i2c_write_fail;
2075
2076                 /* Write offset 0x00 to 0x23 */
2077                 buffer[0] = 0x00;
2078                 buffer[1] = 0x23;
2079                 i2c_success = i2c_write(pipe_ctx, slave_address,
2080                                 buffer, sizeof(buffer));
2081                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2082                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2083                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2084                 if (!i2c_success)
2085                         goto i2c_write_fail;
2086
2087                 /* Write offset 0xff to 0x00 */
2088                 buffer[0] = 0xff;
2089                 buffer[1] = 0x00;
2090                 i2c_success = i2c_write(pipe_ctx, slave_address,
2091                                 buffer, sizeof(buffer));
2092                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2093                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2094                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2095                 if (!i2c_success)
2096                         goto i2c_write_fail;
2097
2098         }
2099
2100         return;
2101
2102 i2c_write_fail:
2103         DC_LOG_DEBUG("Set retimer failed");
2104 }
2105
2106 static void write_i2c_default_retimer_setting(
2107                 struct pipe_ctx *pipe_ctx,
2108                 bool is_vga_mode,
2109                 bool is_over_340mhz)
2110 {
2111         uint8_t slave_address = (0xBA >> 1);
2112         uint8_t buffer[2];
2113         bool i2c_success = false;
2114         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2115
2116         memset(&buffer, 0, sizeof(buffer));
2117
2118         /* Program Slave Address for tuning single integrity */
2119         /* Write offset 0x0A to 0x13 */
2120         buffer[0] = 0x0A;
2121         buffer[1] = 0x13;
2122         i2c_success = i2c_write(pipe_ctx, slave_address,
2123                         buffer, sizeof(buffer));
2124         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2125                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2126                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2127         if (!i2c_success)
2128                 goto i2c_write_fail;
2129
2130         /* Write offset 0x0A to 0x17 */
2131         buffer[0] = 0x0A;
2132         buffer[1] = 0x17;
2133         i2c_success = i2c_write(pipe_ctx, slave_address,
2134                         buffer, sizeof(buffer));
2135         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2136                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2137                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2138         if (!i2c_success)
2139                 goto i2c_write_fail;
2140
2141         /* Write offset 0x0B to 0xDA or 0xD8 */
2142         buffer[0] = 0x0B;
2143         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2144         i2c_success = i2c_write(pipe_ctx, slave_address,
2145                         buffer, sizeof(buffer));
2146         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2147                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2148                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2149         if (!i2c_success)
2150                 goto i2c_write_fail;
2151
2152         /* Write offset 0x0A to 0x17 */
2153         buffer[0] = 0x0A;
2154         buffer[1] = 0x17;
2155         i2c_success = i2c_write(pipe_ctx, slave_address,
2156                         buffer, sizeof(buffer));
2157         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2158                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2159                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2160         if (!i2c_success)
2161                 goto i2c_write_fail;
2162
2163         /* Write offset 0x0C to 0x1D or 0x91 */
2164         buffer[0] = 0x0C;
2165         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2166         i2c_success = i2c_write(pipe_ctx, slave_address,
2167                         buffer, sizeof(buffer));
2168         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2169                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2170                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2171         if (!i2c_success)
2172                 goto i2c_write_fail;
2173
2174         /* Write offset 0x0A to 0x17 */
2175         buffer[0] = 0x0A;
2176         buffer[1] = 0x17;
2177         i2c_success = i2c_write(pipe_ctx, slave_address,
2178                         buffer, sizeof(buffer));
2179         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2180                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2181                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2182         if (!i2c_success)
2183                 goto i2c_write_fail;
2184
2185
2186         if (is_vga_mode) {
2187                 /* Program additional settings if using 640x480 resolution */
2188
2189                 /* Write offset 0xFF to 0x01 */
2190                 buffer[0] = 0xff;
2191                 buffer[1] = 0x01;
2192                 i2c_success = i2c_write(pipe_ctx, slave_address,
2193                                 buffer, sizeof(buffer));
2194                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2195                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2196                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2197                 if (!i2c_success)
2198                         goto i2c_write_fail;
2199
2200                 /* Write offset 0x00 to 0x23 */
2201                 buffer[0] = 0x00;
2202                 buffer[1] = 0x23;
2203                 i2c_success = i2c_write(pipe_ctx, slave_address,
2204                                 buffer, sizeof(buffer));
2205                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2206                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2207                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2208                 if (!i2c_success)
2209                         goto i2c_write_fail;
2210
2211                 /* Write offset 0xff to 0x00 */
2212                 buffer[0] = 0xff;
2213                 buffer[1] = 0x00;
2214                 i2c_success = i2c_write(pipe_ctx, slave_address,
2215                                 buffer, sizeof(buffer));
2216                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2217                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2218                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2219                 if (!i2c_success)
2220                         goto i2c_write_fail;
2221         }
2222
2223         return;
2224
2225 i2c_write_fail:
2226         DC_LOG_DEBUG("Set default retimer failed");
2227 }
2228
2229 static void write_i2c_redriver_setting(
2230                 struct pipe_ctx *pipe_ctx,
2231                 bool is_over_340mhz)
2232 {
2233         uint8_t slave_address = (0xF0 >> 1);
2234         uint8_t buffer[16];
2235         bool i2c_success = false;
2236         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2237
2238         memset(&buffer, 0, sizeof(buffer));
2239
2240         // Program Slave Address for tuning single integrity
2241         buffer[3] = 0x4E;
2242         buffer[4] = 0x4E;
2243         buffer[5] = 0x4E;
2244         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2245
2246         i2c_success = i2c_write(pipe_ctx, slave_address,
2247                                         buffer, sizeof(buffer));
2248         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2249                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2250                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2251                 i2c_success = %d\n",
2252                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2253
2254         if (!i2c_success)
2255                 DC_LOG_DEBUG("Set redriver failed");
2256 }
2257
2258 static void disable_link(struct dc_link *link, enum signal_type signal)
2259 {
2260         /*
2261          * TODO: implement call for dp_set_hw_test_pattern
2262          * it is needed for compliance testing
2263          */
2264
2265         /* Here we need to specify that encoder output settings
2266          * need to be calculated as for the set mode,
2267          * it will lead to querying dynamic link capabilities
2268          * which should be done before enable output
2269          */
2270
2271         if (dc_is_dp_signal(signal)) {
2272                 /* SST DP, eDP */
2273                 if (dc_is_dp_sst_signal(signal))
2274                         dp_disable_link_phy(link, signal);
2275                 else
2276                         dp_disable_link_phy_mst(link, signal);
2277
2278                 if (dc_is_dp_sst_signal(signal) ||
2279                                 link->mst_stream_alloc_table.stream_count == 0) {
2280                         dp_set_fec_enable(link, false);
2281                         dp_set_fec_ready(link, false);
2282                 }
2283         } else {
2284                 if (signal != SIGNAL_TYPE_VIRTUAL)
2285                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2286         }
2287
2288         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2289                 /* MST disable link only when no stream use the link */
2290                 if (link->mst_stream_alloc_table.stream_count <= 0)
2291                         link->link_status.link_active = false;
2292         } else {
2293                 link->link_status.link_active = false;
2294         }
2295 }
2296
2297 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2298 {
2299         struct dc_stream_state *stream = pipe_ctx->stream;
2300         struct dc_link *link = stream->link;
2301         enum dc_color_depth display_color_depth;
2302         enum engine_id eng_id;
2303         struct ext_hdmi_settings settings = {0};
2304         bool is_over_340mhz = false;
2305         bool is_vga_mode = (stream->timing.h_addressable == 640)
2306                         && (stream->timing.v_addressable == 480);
2307
2308         if (stream->phy_pix_clk == 0)
2309                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2310         if (stream->phy_pix_clk > 340000)
2311                 is_over_340mhz = true;
2312
2313         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2314                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2315                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2316                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2317                         /* DP159, Retimer settings */
2318                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2319
2320                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2321                                 write_i2c_retimer_setting(pipe_ctx,
2322                                                 is_vga_mode, is_over_340mhz, &settings);
2323                         } else {
2324                                 write_i2c_default_retimer_setting(pipe_ctx,
2325                                                 is_vga_mode, is_over_340mhz);
2326                         }
2327                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2328                         /* PI3EQX1204, Redriver settings */
2329                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2330                 }
2331         }
2332
2333         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2334                 dal_ddc_service_write_scdc_data(
2335                         stream->link->ddc,
2336                         stream->phy_pix_clk,
2337                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2338
2339         memset(&stream->link->cur_link_settings, 0,
2340                         sizeof(struct dc_link_settings));
2341
2342         display_color_depth = stream->timing.display_color_depth;
2343         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2344                 display_color_depth = COLOR_DEPTH_888;
2345
2346         link->link_enc->funcs->enable_tmds_output(
2347                         link->link_enc,
2348                         pipe_ctx->clock_source->id,
2349                         display_color_depth,
2350                         pipe_ctx->stream->signal,
2351                         stream->phy_pix_clk);
2352
2353         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2354                 dal_ddc_service_read_scdc_data(link->ddc);
2355 }
2356
2357 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2358 {
2359         struct dc_stream_state *stream = pipe_ctx->stream;
2360         struct dc_link *link = stream->link;
2361
2362         if (stream->phy_pix_clk == 0)
2363                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2364
2365         memset(&stream->link->cur_link_settings, 0,
2366                         sizeof(struct dc_link_settings));
2367
2368         link->link_enc->funcs->enable_lvds_output(
2369                         link->link_enc,
2370                         pipe_ctx->clock_source->id,
2371                         stream->phy_pix_clk);
2372
2373 }
2374
2375 /****************************enable_link***********************************/
2376 static enum dc_status enable_link(
2377                 struct dc_state *state,
2378                 struct pipe_ctx *pipe_ctx)
2379 {
2380         enum dc_status status = DC_ERROR_UNEXPECTED;
2381         struct dc_stream_state *stream = pipe_ctx->stream;
2382         struct dc_link *link = stream->link;
2383
2384         /* There's some scenarios where driver is unloaded with display
2385          * still enabled. When driver is reloaded, it may cause a display
2386          * to not light up if there is a mismatch between old and new
2387          * link settings. Need to call disable first before enabling at
2388          * new link settings.
2389          */
2390         if (link->link_status.link_active) {
2391                 disable_link(link, pipe_ctx->stream->signal);
2392         }
2393
2394         switch (pipe_ctx->stream->signal) {
2395         case SIGNAL_TYPE_DISPLAY_PORT:
2396                 status = enable_link_dp(state, pipe_ctx);
2397                 break;
2398         case SIGNAL_TYPE_EDP:
2399                 status = enable_link_edp(state, pipe_ctx);
2400                 break;
2401         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2402                 status = enable_link_dp_mst(state, pipe_ctx);
2403                 msleep(200);
2404                 break;
2405         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2406         case SIGNAL_TYPE_DVI_DUAL_LINK:
2407         case SIGNAL_TYPE_HDMI_TYPE_A:
2408                 enable_link_hdmi(pipe_ctx);
2409                 status = DC_OK;
2410                 break;
2411         case SIGNAL_TYPE_LVDS:
2412                 enable_link_lvds(pipe_ctx);
2413                 status = DC_OK;
2414                 break;
2415         case SIGNAL_TYPE_VIRTUAL:
2416                 status = DC_OK;
2417                 break;
2418         default:
2419                 break;
2420         }
2421
2422         if (status == DC_OK)
2423                 pipe_ctx->stream->link->link_status.link_active = true;
2424
2425         return status;
2426 }
2427
2428 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2429 {
2430
2431         uint32_t pxl_clk = timing->pix_clk_100hz;
2432
2433         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2434                 pxl_clk /= 2;
2435         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2436                 pxl_clk = pxl_clk * 2 / 3;
2437
2438         if (timing->display_color_depth == COLOR_DEPTH_101010)
2439                 pxl_clk = pxl_clk * 10 / 8;
2440         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2441                 pxl_clk = pxl_clk * 12 / 8;
2442
2443         return pxl_clk;
2444 }
2445
2446 static bool dp_active_dongle_validate_timing(
2447                 const struct dc_crtc_timing *timing,
2448                 const struct dpcd_caps *dpcd_caps)
2449 {
2450         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2451
2452         switch (dpcd_caps->dongle_type) {
2453         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2454         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2455         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2456                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2457                         return true;
2458                 else
2459                         return false;
2460         default:
2461                 break;
2462         }
2463
2464         if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2465                 dongle_caps->extendedCapValid == false)
2466                 return true;
2467
2468         /* Check Pixel Encoding */
2469         switch (timing->pixel_encoding) {
2470         case PIXEL_ENCODING_RGB:
2471         case PIXEL_ENCODING_YCBCR444:
2472                 break;
2473         case PIXEL_ENCODING_YCBCR422:
2474                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2475                         return false;
2476                 break;
2477         case PIXEL_ENCODING_YCBCR420:
2478                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2479                         return false;
2480                 break;
2481         default:
2482                 /* Invalid Pixel Encoding*/
2483                 return false;
2484         }
2485
2486         switch (timing->display_color_depth) {
2487         case COLOR_DEPTH_666:
2488         case COLOR_DEPTH_888:
2489                 /*888 and 666 should always be supported*/
2490                 break;
2491         case COLOR_DEPTH_101010:
2492                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2493                         return false;
2494                 break;
2495         case COLOR_DEPTH_121212:
2496                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2497                         return false;
2498                 break;
2499         case COLOR_DEPTH_141414:
2500         case COLOR_DEPTH_161616:
2501         default:
2502                 /* These color depths are currently not supported */
2503                 return false;
2504         }
2505
2506         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2507                 return false;
2508
2509         return true;
2510 }
2511
2512 enum dc_status dc_link_validate_mode_timing(
2513                 const struct dc_stream_state *stream,
2514                 struct dc_link *link,
2515                 const struct dc_crtc_timing *timing)
2516 {
2517         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2518         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2519
2520         /* A hack to avoid failing any modes for EDID override feature on
2521          * topology change such as lower quality cable for DP or different dongle
2522          */
2523         if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2524                 return DC_OK;
2525
2526         /* Passive Dongle */
2527         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2528                 return DC_EXCEED_DONGLE_CAP;
2529
2530         /* Active Dongle*/
2531         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2532                 return DC_EXCEED_DONGLE_CAP;
2533
2534         switch (stream->signal) {
2535         case SIGNAL_TYPE_EDP:
2536         case SIGNAL_TYPE_DISPLAY_PORT:
2537                 if (!dp_validate_mode_timing(
2538                                 link,
2539                                 timing))
2540                         return DC_NO_DP_LINK_BANDWIDTH;
2541                 break;
2542
2543         default:
2544                 break;
2545         }
2546
2547         return DC_OK;
2548 }
2549
2550 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2551 {
2552         int i;
2553         struct dc *dc = NULL;
2554         struct abm *abm = NULL;
2555
2556         if (!link || !link->ctx)
2557                 return NULL;
2558
2559         dc = link->ctx->dc;
2560
2561         for (i = 0; i < MAX_PIPES; i++) {
2562                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2563                 struct dc_stream_state *stream = pipe_ctx.stream;
2564
2565                 if (stream && stream->link == link) {
2566                         abm = pipe_ctx.stream_res.abm;
2567                         break;
2568                 }
2569         }
2570         return abm;
2571 }
2572
2573 int dc_link_get_backlight_level(const struct dc_link *link)
2574 {
2575
2576         struct abm *abm = get_abm_from_stream_res(link);
2577
2578         if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2579                 return DC_ERROR_UNEXPECTED;
2580
2581         return (int) abm->funcs->get_current_backlight(abm);
2582 }
2583
2584 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
2585 {
2586         struct abm *abm = get_abm_from_stream_res(link);
2587
2588         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
2589                 return DC_ERROR_UNEXPECTED;
2590
2591         return (int) abm->funcs->get_target_backlight(abm);
2592 }
2593
2594 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
2595 {
2596         int i;
2597         struct dc *dc = link->ctx->dc;
2598         struct pipe_ctx *pipe_ctx = NULL;
2599
2600         for (i = 0; i < MAX_PIPES; i++) {
2601                 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
2602                         if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
2603                                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2604                                 break;
2605                         }
2606                 }
2607         }
2608
2609         return pipe_ctx;
2610 }
2611
2612 bool dc_link_set_backlight_level(const struct dc_link *link,
2613                 uint32_t backlight_pwm_u16_16,
2614                 uint32_t frame_ramp)
2615 {
2616         struct dc  *dc = link->ctx->dc;
2617
2618         DC_LOGGER_INIT(link->ctx->logger);
2619         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2620                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2621
2622         if (dc_is_embedded_signal(link->connector_signal)) {
2623                 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
2624
2625                 if (pipe_ctx) {
2626                         /* Disable brightness ramping when the display is blanked
2627                          * as it can hang the DMCU
2628                          */
2629                         if (pipe_ctx->plane_state == NULL)
2630                                 frame_ramp = 0;
2631                 } else {
2632                         return false;
2633                 }
2634
2635                 dc->hwss.set_backlight_level(
2636                                 pipe_ctx,
2637                                 backlight_pwm_u16_16,
2638                                 frame_ramp);
2639         }
2640         return true;
2641 }
2642
2643 bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
2644                 bool wait, bool force_static)
2645 {
2646         struct dc  *dc = link->ctx->dc;
2647         struct dmcu *dmcu = dc->res_pool->dmcu;
2648         struct dmub_psr *psr = dc->res_pool->psr;
2649
2650         if (psr == NULL && force_static)
2651                 return false;
2652
2653         link->psr_settings.psr_allow_active = allow_active;
2654
2655         if (psr != NULL && link->psr_settings.psr_feature_enabled) {
2656                 if (force_static && psr->funcs->psr_force_static)
2657                         psr->funcs->psr_force_static(psr);
2658                 psr->funcs->psr_enable(psr, allow_active, wait);
2659         } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
2660                 dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
2661         else
2662                 return false;
2663
2664         return true;
2665 }
2666
2667 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
2668 {
2669         struct dc  *dc = link->ctx->dc;
2670         struct dmcu *dmcu = dc->res_pool->dmcu;
2671         struct dmub_psr *psr = dc->res_pool->psr;
2672
2673         if (psr != NULL && link->psr_settings.psr_feature_enabled)
2674                 psr->funcs->psr_get_state(psr, state);
2675         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
2676                 dmcu->funcs->get_psr_state(dmcu, state);
2677
2678         return true;
2679 }
2680
2681 static inline enum physical_phy_id
2682 transmitter_to_phy_id(enum transmitter transmitter_value)
2683 {
2684         switch (transmitter_value) {
2685         case TRANSMITTER_UNIPHY_A:
2686                 return PHYLD_0;
2687         case TRANSMITTER_UNIPHY_B:
2688                 return PHYLD_1;
2689         case TRANSMITTER_UNIPHY_C:
2690                 return PHYLD_2;
2691         case TRANSMITTER_UNIPHY_D:
2692                 return PHYLD_3;
2693         case TRANSMITTER_UNIPHY_E:
2694                 return PHYLD_4;
2695         case TRANSMITTER_UNIPHY_F:
2696                 return PHYLD_5;
2697         case TRANSMITTER_NUTMEG_CRT:
2698                 return PHYLD_6;
2699         case TRANSMITTER_TRAVIS_CRT:
2700                 return PHYLD_7;
2701         case TRANSMITTER_TRAVIS_LCD:
2702                 return PHYLD_8;
2703         case TRANSMITTER_UNIPHY_G:
2704                 return PHYLD_9;
2705         case TRANSMITTER_COUNT:
2706                 return PHYLD_COUNT;
2707         case TRANSMITTER_UNKNOWN:
2708                 return PHYLD_UNKNOWN;
2709         default:
2710                 WARN_ONCE(1, "Unknown transmitter value %d\n",
2711                           transmitter_value);
2712                 return PHYLD_UNKNOWN;
2713         }
2714 }
2715
2716 bool dc_link_setup_psr(struct dc_link *link,
2717                 const struct dc_stream_state *stream, struct psr_config *psr_config,
2718                 struct psr_context *psr_context)
2719 {
2720         struct dc *dc;
2721         struct dmcu *dmcu;
2722         struct dmub_psr *psr;
2723         int i;
2724         /* updateSinkPsrDpcdConfig*/
2725         union dpcd_psr_configuration psr_configuration;
2726
2727         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
2728
2729         if (!link)
2730                 return false;
2731
2732         dc = link->ctx->dc;
2733         dmcu = dc->res_pool->dmcu;
2734         psr = dc->res_pool->psr;
2735
2736         if (!dmcu && !psr)
2737                 return false;
2738
2739
2740         memset(&psr_configuration, 0, sizeof(psr_configuration));
2741
2742         psr_configuration.bits.ENABLE                    = 1;
2743         psr_configuration.bits.CRC_VERIFICATION          = 1;
2744         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
2745                         psr_config->psr_frame_capture_indication_req;
2746
2747         /* Check for PSR v2*/
2748         if (psr_config->psr_version == 0x2) {
2749                 /* For PSR v2 selective update.
2750                  * Indicates whether sink should start capturing
2751                  * immediately following active scan line,
2752                  * or starting with the 2nd active scan line.
2753                  */
2754                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
2755                 /*For PSR v2, determines whether Sink should generate
2756                  * IRQ_HPD when CRC mismatch is detected.
2757                  */
2758                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
2759         }
2760
2761         dm_helpers_dp_write_dpcd(
2762                 link->ctx,
2763                 link,
2764                 368,
2765                 &psr_configuration.raw,
2766                 sizeof(psr_configuration.raw));
2767
2768         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
2769         psr_context->transmitterId = link->link_enc->transmitter;
2770         psr_context->engineId = link->link_enc->preferred_engine;
2771
2772         for (i = 0; i < MAX_PIPES; i++) {
2773                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
2774                                 == stream) {
2775                         /* dmcu -1 for all controller id values,
2776                          * therefore +1 here
2777                          */
2778                         psr_context->controllerId =
2779                                 dc->current_state->res_ctx.
2780                                 pipe_ctx[i].stream_res.tg->inst + 1;
2781                         break;
2782                 }
2783         }
2784
2785         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
2786         psr_context->phyType = PHY_TYPE_UNIPHY;
2787         /*PhyId is associated with the transmitter id*/
2788         psr_context->smuPhyId =
2789                 transmitter_to_phy_id(link->link_enc->transmitter);
2790
2791         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
2792         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
2793                                         timing.pix_clk_100hz * 100),
2794                                         stream->timing.v_total),
2795                                         stream->timing.h_total);
2796
2797         psr_context->psrSupportedDisplayConfig = true;
2798         psr_context->psrExitLinkTrainingRequired =
2799                 psr_config->psr_exit_link_training_required;
2800         psr_context->sdpTransmitLineNumDeadline =
2801                 psr_config->psr_sdp_transmit_line_num_deadline;
2802         psr_context->psrFrameCaptureIndicationReq =
2803                 psr_config->psr_frame_capture_indication_req;
2804
2805         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
2806
2807         psr_context->numberOfControllers =
2808                         link->dc->res_pool->timing_generator_count;
2809
2810         psr_context->rfb_update_auto_en = true;
2811
2812         /* 2 frames before enter PSR. */
2813         psr_context->timehyst_frames = 2;
2814         /* half a frame
2815          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
2816          */
2817         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
2818         psr_context->aux_repeats = 10;
2819
2820         psr_context->psr_level.u32all = 0;
2821
2822         /*skip power down the single pipe since it blocks the cstate*/
2823         if (link->ctx->asic_id.chip_family >= FAMILY_RV)
2824                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
2825
2826         /* SMU will perform additional powerdown sequence.
2827          * For unsupported ASICs, set psr_level flag to skip PSR
2828          *  static screen notification to SMU.
2829          *  (Always set for DAL2, did not check ASIC)
2830          */
2831         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
2832         psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
2833
2834         /* Complete PSR entry before aborting to prevent intermittent
2835          * freezes on certain eDPs
2836          */
2837         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
2838
2839         /* Controls additional delay after remote frame capture before
2840          * continuing power down, default = 0
2841          */
2842         psr_context->frame_delay = 0;
2843
2844         if (psr)
2845                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context);
2846         else
2847                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
2848
2849         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
2850          * should not happen since firmware should be running at this point
2851          */
2852         if (link->psr_settings.psr_feature_enabled == 0)
2853                 ASSERT(0);
2854
2855         return true;
2856
2857 }
2858
2859 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
2860 {
2861         struct dc  *dc = link->ctx->dc;
2862         struct dmub_psr *psr = dc->res_pool->psr;
2863
2864         // PSR residency measurements only supported on DMCUB
2865         if (psr != NULL && link->psr_settings.psr_feature_enabled)
2866                 psr->funcs->psr_get_residency(psr, residency);
2867         else
2868                 *residency = 0;
2869 }
2870
2871 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2872 {
2873         return &link->link_status;
2874 }
2875
2876 void core_link_resume(struct dc_link *link)
2877 {
2878         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2879                 program_hpd_filter(link);
2880 }
2881
2882 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2883 {
2884         struct fixed31_32 mbytes_per_sec;
2885         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
2886                         &stream->link->cur_link_settings);
2887         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
2888
2889         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2890
2891         return dc_fixpt_div_int(mbytes_per_sec, 54);
2892 }
2893
2894 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
2895 {
2896         struct fixed31_32 peak_kbps;
2897         uint32_t numerator = 0;
2898         uint32_t denominator = 1;
2899
2900         /*
2901          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2902          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2903          * common multiplier to render an integer PBN for all link rate/lane
2904          * counts combinations
2905          * calculate
2906          * peak_kbps *= (1006/1000)
2907          * peak_kbps *= (64/54)
2908          * peak_kbps *= 8    convert to bytes
2909          */
2910
2911         numerator = 64 * PEAK_FACTOR_X1000;
2912         denominator = 54 * 8 * 1000 * 1000;
2913         kbps *= numerator;
2914         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2915
2916         return peak_kbps;
2917 }
2918
2919 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2920 {
2921         uint64_t kbps;
2922
2923         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2924         return get_pbn_from_bw_in_kbps(kbps);
2925 }
2926
2927 static void update_mst_stream_alloc_table(
2928         struct dc_link *link,
2929         struct stream_encoder *stream_enc,
2930         const struct dp_mst_stream_allocation_table *proposed_table)
2931 {
2932         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2933                         { 0 } };
2934         struct link_mst_stream_allocation *dc_alloc;
2935
2936         int i;
2937         int j;
2938
2939         /* if DRM proposed_table has more than one new payload */
2940         ASSERT(proposed_table->stream_count -
2941                         link->mst_stream_alloc_table.stream_count < 2);
2942
2943         /* copy proposed_table to link, add stream encoder */
2944         for (i = 0; i < proposed_table->stream_count; i++) {
2945
2946                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2947                         dc_alloc =
2948                         &link->mst_stream_alloc_table.stream_allocations[j];
2949
2950                         if (dc_alloc->vcp_id ==
2951                                 proposed_table->stream_allocations[i].vcp_id) {
2952
2953                                 work_table[i] = *dc_alloc;
2954                                 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
2955                                 break; /* exit j loop */
2956                         }
2957                 }
2958
2959                 /* new vcp_id */
2960                 if (j == link->mst_stream_alloc_table.stream_count) {
2961                         work_table[i].vcp_id =
2962                                 proposed_table->stream_allocations[i].vcp_id;
2963                         work_table[i].slot_count =
2964                                 proposed_table->stream_allocations[i].slot_count;
2965                         work_table[i].stream_enc = stream_enc;
2966                 }
2967         }
2968
2969         /* update link->mst_stream_alloc_table with work_table */
2970         link->mst_stream_alloc_table.stream_count =
2971                         proposed_table->stream_count;
2972         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2973                 link->mst_stream_alloc_table.stream_allocations[i] =
2974                                 work_table[i];
2975 }
2976
2977 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2978  * because stream_encoder is not exposed to dm
2979  */
2980 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2981 {
2982         struct dc_stream_state *stream = pipe_ctx->stream;
2983         struct dc_link *link = stream->link;
2984         struct link_encoder *link_encoder = link->link_enc;
2985         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2986         struct dp_mst_stream_allocation_table proposed_table = {0};
2987         struct fixed31_32 avg_time_slots_per_mtp;
2988         struct fixed31_32 pbn;
2989         struct fixed31_32 pbn_per_slot;
2990         uint8_t i;
2991         enum act_return_status ret;
2992         DC_LOGGER_INIT(link->ctx->logger);
2993
2994         /* enable_link_dp_mst already check link->enabled_stream_count
2995          * and stream is in link->stream[]. This is called during set mode,
2996          * stream_enc is available.
2997          */
2998
2999         /* get calculate VC payload for stream: stream_alloc */
3000         if (dm_helpers_dp_mst_write_payload_allocation_table(
3001                 stream->ctx,
3002                 stream,
3003                 &proposed_table,
3004                 true)) {
3005                 update_mst_stream_alloc_table(
3006                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3007         }
3008         else
3009                 DC_LOG_WARNING("Failed to update"
3010                                 "MST allocation table for"
3011                                 "pipe idx:%d\n",
3012                                 pipe_ctx->pipe_idx);
3013
3014         DC_LOG_MST("%s  "
3015                         "stream_count: %d: \n ",
3016                         __func__,
3017                         link->mst_stream_alloc_table.stream_count);
3018
3019         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3020                 DC_LOG_MST("stream_enc[%d]: %p      "
3021                 "stream[%d].vcp_id: %d      "
3022                 "stream[%d].slot_count: %d\n",
3023                 i,
3024                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3025                 i,
3026                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3027                 i,
3028                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3029         }
3030
3031         ASSERT(proposed_table.stream_count > 0);
3032
3033         /* program DP source TX for payload */
3034         link_encoder->funcs->update_mst_stream_allocation_table(
3035                 link_encoder,
3036                 &link->mst_stream_alloc_table);
3037
3038         /* send down message */
3039         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3040                         stream->ctx,
3041                         stream);
3042
3043         if (ret != ACT_LINK_LOST) {
3044                 dm_helpers_dp_mst_send_payload_allocation(
3045                                 stream->ctx,
3046                                 stream,
3047                                 true);
3048         }
3049
3050         /* slot X.Y for only current stream */
3051         pbn_per_slot = get_pbn_per_slot(stream);
3052         if (pbn_per_slot.value == 0) {
3053                 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3054                 return DC_UNSUPPORTED_VALUE;
3055         }
3056         pbn = get_pbn_from_timing(pipe_ctx);
3057         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3058
3059         stream_encoder->funcs->set_throttled_vcp_size(
3060                 stream_encoder,
3061                 avg_time_slots_per_mtp);
3062
3063         return DC_OK;
3064
3065 }
3066
3067 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3068 {
3069         struct dc_stream_state *stream = pipe_ctx->stream;
3070         struct dc_link *link = stream->link;
3071         struct link_encoder *link_encoder = link->link_enc;
3072         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3073         struct dp_mst_stream_allocation_table proposed_table = {0};
3074         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3075         uint8_t i;
3076         bool mst_mode = (link->type == dc_connection_mst_branch);
3077         DC_LOGGER_INIT(link->ctx->logger);
3078
3079         /* deallocate_mst_payload is called before disable link. When mode or
3080          * disable/enable monitor, new stream is created which is not in link
3081          * stream[] yet. For this, payload is not allocated yet, so de-alloc
3082          * should not done. For new mode set, map_resources will get engine
3083          * for new stream, so stream_enc->id should be validated until here.
3084          */
3085
3086         /* slot X.Y */
3087         stream_encoder->funcs->set_throttled_vcp_size(
3088                 stream_encoder,
3089                 avg_time_slots_per_mtp);
3090
3091         /* TODO: which component is responsible for remove payload table? */
3092         if (mst_mode) {
3093                 if (dm_helpers_dp_mst_write_payload_allocation_table(
3094                                 stream->ctx,
3095                                 stream,
3096                                 &proposed_table,
3097                                 false)) {
3098
3099                         update_mst_stream_alloc_table(
3100                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3101                 }
3102                 else {
3103                                 DC_LOG_WARNING("Failed to update"
3104                                                 "MST allocation table for"
3105                                                 "pipe idx:%d\n",
3106                                                 pipe_ctx->pipe_idx);
3107                 }
3108         }
3109
3110         DC_LOG_MST("%s"
3111                         "stream_count: %d: ",
3112                         __func__,
3113                         link->mst_stream_alloc_table.stream_count);
3114
3115         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3116                 DC_LOG_MST("stream_enc[%d]: %p      "
3117                 "stream[%d].vcp_id: %d      "
3118                 "stream[%d].slot_count: %d\n",
3119                 i,
3120                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3121                 i,
3122                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3123                 i,
3124                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3125         }
3126
3127         link_encoder->funcs->update_mst_stream_allocation_table(
3128                 link_encoder,
3129                 &link->mst_stream_alloc_table);
3130
3131         if (mst_mode) {
3132                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3133                         stream->ctx,
3134                         stream);
3135
3136                 dm_helpers_dp_mst_send_payload_allocation(
3137                         stream->ctx,
3138                         stream,
3139                         false);
3140         }
3141
3142         return DC_OK;
3143 }
3144
3145
3146 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3147 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3148 {
3149         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3150         if (cp_psp && cp_psp->funcs.update_stream_config) {
3151                 struct cp_psp_stream_config config = {0};
3152                 enum dp_panel_mode panel_mode =
3153                                 dp_get_panel_mode(pipe_ctx->stream->link);
3154
3155                 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3156                 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3157                 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
3158                 config.dpms_off = dpms_off;
3159                 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
3160                 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
3161                 config.mst_enabled = (pipe_ctx->stream->signal ==
3162                                 SIGNAL_TYPE_DISPLAY_PORT_MST);
3163                 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
3164         }
3165 }
3166 #endif
3167
3168 void core_link_enable_stream(
3169                 struct dc_state *state,
3170                 struct pipe_ctx *pipe_ctx)
3171 {
3172         struct dc *dc = pipe_ctx->stream->ctx->dc;
3173         struct dc_stream_state *stream = pipe_ctx->stream;
3174         enum dc_status status;
3175 #if defined(CONFIG_DRM_AMD_DC_DCN)
3176         enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
3177 #endif
3178         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
3179
3180         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3181                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3182                 return;
3183
3184         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3185                 stream->link->link_enc->funcs->setup(
3186                         stream->link->link_enc,
3187                         pipe_ctx->stream->signal);
3188                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
3189                         pipe_ctx->stream_res.stream_enc,
3190                         pipe_ctx->stream_res.tg->inst,
3191                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
3192         }
3193
3194         if (dc_is_dp_signal(pipe_ctx->stream->signal))
3195                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
3196                         pipe_ctx->stream_res.stream_enc,
3197                         &stream->timing,
3198                         stream->output_color_space,
3199                         stream->use_vsc_sdp_for_colorimetry,
3200                         stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
3201
3202         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
3203                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
3204                         pipe_ctx->stream_res.stream_enc,
3205                         &stream->timing,
3206                         stream->phy_pix_clk,
3207                         pipe_ctx->stream_res.audio != NULL);
3208
3209         pipe_ctx->stream->link->link_state_valid = true;
3210
3211 #if defined(CONFIG_DRM_AMD_DC_DCN)
3212         if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
3213                 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
3214 #endif
3215
3216         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
3217                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
3218                         pipe_ctx->stream_res.stream_enc,
3219                         &stream->timing,
3220                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
3221                         true : false);
3222
3223         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
3224                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
3225                         pipe_ctx->stream_res.stream_enc,
3226                         &stream->timing);
3227
3228         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
3229                 bool apply_edp_fast_boot_optimization =
3230                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
3231
3232                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
3233
3234                 resource_build_info_frame(pipe_ctx);
3235                 dc->hwss.update_info_frame(pipe_ctx);
3236
3237                 /* Do not touch link on seamless boot optimization. */
3238                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
3239                         pipe_ctx->stream->dpms_off = false;
3240
3241                         /* Still enable stream features & audio on seamless boot for DP external displays */
3242                         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
3243                                 enable_stream_features(pipe_ctx);
3244                                 if (pipe_ctx->stream_res.audio != NULL) {
3245                                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
3246                                         dc->hwss.enable_audio_stream(pipe_ctx);
3247                                 }
3248                         }
3249
3250 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3251                         update_psp_stream_config(pipe_ctx, false);
3252 #endif
3253                         return;
3254                 }
3255
3256                 /* eDP lit up by bios already, no need to enable again. */
3257                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
3258                                         apply_edp_fast_boot_optimization &&
3259                                         !pipe_ctx->stream->timing.flags.DSC) {
3260                         pipe_ctx->stream->dpms_off = false;
3261 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3262                         update_psp_stream_config(pipe_ctx, false);
3263 #endif
3264                         return;
3265                 }
3266
3267                 if (pipe_ctx->stream->dpms_off)
3268                         return;
3269
3270                 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
3271                  * link training). This is to make sure the bandwidth sent to DIG BE won't be
3272                  * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
3273                  * will be automatically set at a later time when the video is enabled
3274                  * (DP_VID_STREAM_EN = 1).
3275                  */
3276                 if (pipe_ctx->stream->timing.flags.DSC) {
3277                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3278                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3279                                 dp_set_dsc_enable(pipe_ctx, true);
3280                 }
3281
3282                 status = enable_link(state, pipe_ctx);
3283
3284                 if (status != DC_OK) {
3285                         DC_LOG_WARNING("enabling link %u failed: %d\n",
3286                         pipe_ctx->stream->link->link_index,
3287                         status);
3288
3289                         /* Abort stream enable *unless* the failure was due to
3290                          * DP link training - some DP monitors will recover and
3291                          * show the stream anyway. But MST displays can't proceed
3292                          * without link training.
3293                          */
3294                         if (status != DC_FAIL_DP_LINK_TRAINING ||
3295                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3296                                 BREAK_TO_DEBUGGER();
3297                                 return;
3298                         }
3299                 }
3300
3301                 /* turn off otg test pattern if enable */
3302                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3303                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3304                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3305                                         COLOR_DEPTH_UNDEFINED);
3306
3307                 /* This second call is needed to reconfigure the DIG
3308                  * as a workaround for the incorrect value being applied
3309                  * from transmitter control.
3310                  */
3311                 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
3312                         stream->link->link_enc->funcs->setup(
3313                                 stream->link->link_enc,
3314                                 pipe_ctx->stream->signal);
3315
3316                 dc->hwss.enable_stream(pipe_ctx);
3317
3318                 /* Set DPS PPS SDP (AKA "info frames") */
3319                 if (pipe_ctx->stream->timing.flags.DSC) {
3320                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3321                                         dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3322                                 dp_set_dsc_on_rx(pipe_ctx, true);
3323                                 dp_set_dsc_pps_sdp(pipe_ctx, true);
3324                         }
3325                 }
3326
3327                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3328                         dc_link_allocate_mst_payload(pipe_ctx);
3329
3330                 dc->hwss.unblank_stream(pipe_ctx,
3331                         &pipe_ctx->stream->link->cur_link_settings);
3332
3333                 if (stream->sink_patches.delay_ignore_msa > 0)
3334                         msleep(stream->sink_patches.delay_ignore_msa);
3335
3336                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3337                         enable_stream_features(pipe_ctx);
3338 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3339                 update_psp_stream_config(pipe_ctx, false);
3340 #endif
3341
3342                 dc->hwss.enable_audio_stream(pipe_ctx);
3343
3344         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
3345                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3346                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
3347                         dp_set_dsc_enable(pipe_ctx, true);
3348
3349         }
3350
3351         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3352                 core_link_set_avmute(pipe_ctx, false);
3353         }
3354 }
3355
3356 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
3357 {
3358         struct dc  *dc = pipe_ctx->stream->ctx->dc;
3359         struct dc_stream_state *stream = pipe_ctx->stream;
3360         struct dc_link *link = stream->sink->link;
3361
3362         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3363                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3364                 return;
3365
3366         if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
3367                 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
3368                         core_link_set_avmute(pipe_ctx, true);
3369         }
3370
3371         dc->hwss.disable_audio_stream(pipe_ctx);
3372
3373 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3374         update_psp_stream_config(pipe_ctx, true);
3375 #endif
3376         dc->hwss.blank_stream(pipe_ctx);
3377
3378         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3379                 deallocate_mst_payload(pipe_ctx);
3380
3381         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
3382                 struct ext_hdmi_settings settings = {0};
3383                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
3384
3385                 unsigned short masked_chip_caps = link->chip_caps &
3386                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
3387                 //Need to inform that sink is going to use legacy HDMI mode.
3388                 dal_ddc_service_write_scdc_data(
3389                         link->ddc,
3390                         165000,//vbios only handles 165Mhz.
3391                         false);
3392                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
3393                         /* DP159, Retimer settings */
3394                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
3395                                 write_i2c_retimer_setting(pipe_ctx,
3396                                                 false, false, &settings);
3397                         else
3398                                 write_i2c_default_retimer_setting(pipe_ctx,
3399                                                 false, false);
3400                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
3401                         /* PI3EQX1204, Redriver settings */
3402                         write_i2c_redriver_setting(pipe_ctx, false);
3403                 }
3404         }
3405
3406         disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
3407
3408         dc->hwss.disable_stream(pipe_ctx);
3409
3410         if (pipe_ctx->stream->timing.flags.DSC) {
3411                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3412                         dp_set_dsc_enable(pipe_ctx, false);
3413         }
3414 }
3415
3416 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
3417 {
3418         struct dc  *dc = pipe_ctx->stream->ctx->dc;
3419
3420         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
3421                 return;
3422
3423         dc->hwss.set_avmute(pipe_ctx, enable);
3424 }
3425
3426 /**
3427  *  dc_link_enable_hpd_filter:
3428  *     If enable is true, programs HPD filter on associated HPD line using
3429  *     delay_on_disconnect/delay_on_connect values dependent on
3430  *     link->connector_signal
3431  *
3432  *     If enable is false, programs HPD filter on associated HPD line with no
3433  *     delays on connect or disconnect
3434  *
3435  *  @link:   pointer to the dc link
3436  *  @enable: boolean specifying whether to enable hbd
3437  */
3438 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
3439 {
3440         struct gpio *hpd;
3441
3442         if (enable) {
3443                 link->is_hpd_filter_disabled = false;
3444                 program_hpd_filter(link);
3445         } else {
3446                 link->is_hpd_filter_disabled = true;
3447                 /* Obtain HPD handle */
3448                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
3449
3450                 if (!hpd)
3451                         return;
3452
3453                 /* Setup HPD filtering */
3454                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
3455                         struct gpio_hpd_config config;
3456
3457                         config.delay_on_connect = 0;
3458                         config.delay_on_disconnect = 0;
3459
3460                         dal_irq_setup_hpd_filter(hpd, &config);
3461
3462                         dal_gpio_close(hpd);
3463                 } else {
3464                         ASSERT_CRITICAL(false);
3465                 }
3466                 /* Release HPD handle */
3467                 dal_gpio_destroy_irq(&hpd);
3468         }
3469 }
3470
3471 uint32_t dc_bandwidth_in_kbps_from_timing(
3472         const struct dc_crtc_timing *timing)
3473 {
3474         uint32_t bits_per_channel = 0;
3475         uint32_t kbps;
3476
3477 #if defined(CONFIG_DRM_AMD_DC_DCN)
3478         if (timing->flags.DSC) {
3479                 return dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, timing->dsc_cfg.bits_per_pixel);
3480         }
3481 #endif
3482
3483         switch (timing->display_color_depth) {
3484         case COLOR_DEPTH_666:
3485                 bits_per_channel = 6;
3486                 break;
3487         case COLOR_DEPTH_888:
3488                 bits_per_channel = 8;
3489                 break;
3490         case COLOR_DEPTH_101010:
3491                 bits_per_channel = 10;
3492                 break;
3493         case COLOR_DEPTH_121212:
3494                 bits_per_channel = 12;
3495                 break;
3496         case COLOR_DEPTH_141414:
3497                 bits_per_channel = 14;
3498                 break;
3499         case COLOR_DEPTH_161616:
3500                 bits_per_channel = 16;
3501                 break;
3502         default:
3503                 ASSERT(bits_per_channel != 0);
3504                 bits_per_channel = 8;
3505                 break;
3506         }
3507
3508         kbps = timing->pix_clk_100hz / 10;
3509         kbps *= bits_per_channel;
3510
3511         if (timing->flags.Y_ONLY != 1) {
3512                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
3513                 kbps *= 3;
3514                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3515                         kbps /= 2;
3516                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
3517                         kbps = kbps * 2 / 3;
3518         }
3519
3520         return kbps;
3521
3522 }
3523
3524 void dc_link_set_drive_settings(struct dc *dc,
3525                                 struct link_training_settings *lt_settings,
3526                                 const struct dc_link *link)
3527 {
3528
3529         int i;
3530
3531         for (i = 0; i < dc->link_count; i++) {
3532                 if (dc->links[i] == link)
3533                         break;
3534         }
3535
3536         if (i >= dc->link_count)
3537                 ASSERT_CRITICAL(false);
3538
3539         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
3540 }
3541
3542 void dc_link_perform_link_training(struct dc *dc,
3543                                    struct dc_link_settings *link_setting,
3544                                    bool skip_video_pattern)
3545 {
3546         int i;
3547
3548         for (i = 0; i < dc->link_count; i++)
3549                 dc_link_dp_perform_link_training(
3550                         dc->links[i],
3551                         link_setting,
3552                         skip_video_pattern);
3553 }
3554
3555 void dc_link_set_preferred_link_settings(struct dc *dc,
3556                                          struct dc_link_settings *link_setting,
3557                                          struct dc_link *link)
3558 {
3559         int i;
3560         struct pipe_ctx *pipe;
3561         struct dc_stream_state *link_stream;
3562         struct dc_link_settings store_settings = *link_setting;
3563
3564         link->preferred_link_setting = store_settings;
3565
3566         /* Retrain with preferred link settings only relevant for
3567          * DP signal type
3568          * Check for non-DP signal or if passive dongle present
3569          */
3570         if (!dc_is_dp_signal(link->connector_signal) ||
3571                 link->dongle_max_pix_clk > 0)
3572                 return;
3573
3574         for (i = 0; i < MAX_PIPES; i++) {
3575                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3576                 if (pipe->stream && pipe->stream->link) {
3577                         if (pipe->stream->link == link) {
3578                                 link_stream = pipe->stream;
3579                                 break;
3580                         }
3581                 }
3582         }
3583
3584         /* Stream not found */
3585         if (i == MAX_PIPES)
3586                 return;
3587
3588         /* Cannot retrain link if backend is off */
3589         if (link_stream->dpms_off)
3590                 return;
3591
3592         decide_link_settings(link_stream, &store_settings);
3593
3594         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3595                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
3596                 dp_retrain_link_dp_test(link, &store_settings, false);
3597 }
3598
3599 void dc_link_set_preferred_training_settings(struct dc *dc,
3600                                                  struct dc_link_settings *link_setting,
3601                                                  struct dc_link_training_overrides *lt_overrides,
3602                                                  struct dc_link *link,
3603                                                  bool skip_immediate_retrain)
3604 {
3605         if (lt_overrides != NULL)
3606                 link->preferred_training_settings = *lt_overrides;
3607         else
3608                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
3609
3610         if (link_setting != NULL) {
3611                 link->preferred_link_setting = *link_setting;
3612         } else {
3613                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3614                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3615         }
3616
3617         /* Retrain now, or wait until next stream update to apply */
3618         if (skip_immediate_retrain == false)
3619                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
3620 }
3621
3622 void dc_link_enable_hpd(const struct dc_link *link)
3623 {
3624         dc_link_dp_enable_hpd(link);
3625 }
3626
3627 void dc_link_disable_hpd(const struct dc_link *link)
3628 {
3629         dc_link_dp_disable_hpd(link);
3630 }
3631
3632 void dc_link_set_test_pattern(struct dc_link *link,
3633                               enum dp_test_pattern test_pattern,
3634                               enum dp_test_pattern_color_space test_pattern_color_space,
3635                               const struct link_training_settings *p_link_settings,
3636                               const unsigned char *p_custom_pattern,
3637                               unsigned int cust_pattern_size)
3638 {
3639         if (link != NULL)
3640                 dc_link_dp_set_test_pattern(
3641                         link,
3642                         test_pattern,
3643                         test_pattern_color_space,
3644                         p_link_settings,
3645                         p_custom_pattern,
3646                         cust_pattern_size);
3647 }
3648
3649 uint32_t dc_link_bandwidth_kbps(
3650         const struct dc_link *link,
3651         const struct dc_link_settings *link_setting)
3652 {
3653         uint32_t link_bw_kbps =
3654                 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
3655
3656         link_bw_kbps *= 8;   /* 8 bits per byte*/
3657         link_bw_kbps *= link_setting->lane_count;
3658
3659         if (dc_link_should_enable_fec(link)) {
3660                 /* Account for FEC overhead.
3661                  * We have to do it based on caps,
3662                  * and not based on FEC being set ready,
3663                  * because FEC is set ready too late in
3664                  * the process to correctly be picked up
3665                  * by mode enumeration.
3666                  *
3667                  * There's enough zeros at the end of 'kbps'
3668                  * that make the below operation 100% precise
3669                  * for our purposes.
3670                  * 'long long' makes it work even for HDMI 2.1
3671                  * max bandwidth (and much, much bigger bandwidths
3672                  * than that, actually).
3673                  *
3674                  * NOTE: Reducing link BW by 3% may not be precise
3675                  * because it may be a stream BT that increases by 3%, and so
3676                  * 1/1.03 = 0.970873 factor should have been used instead,
3677                  * but the difference is minimal and is in a safe direction,
3678                  * which all works well around potential ambiguity of DP 1.4a spec.
3679                  */
3680                 long long fec_link_bw_kbps = link_bw_kbps * 970LL;
3681                 link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL));
3682         }
3683
3684         return link_bw_kbps;
3685
3686 }
3687
3688 const struct dc_link_settings *dc_link_get_link_cap(
3689                 const struct dc_link *link)
3690 {
3691         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
3692                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
3693                 return &link->preferred_link_setting;
3694         return &link->verified_link_cap;
3695 }
3696
3697 void dc_link_overwrite_extended_receiver_cap(
3698                 struct dc_link *link)
3699 {
3700         dp_overwrite_extended_receiver_cap(link);
3701 }
3702
3703 bool dc_link_is_fec_supported(const struct dc_link *link)
3704 {
3705         return (dc_is_dp_signal(link->connector_signal) &&
3706                         link->link_enc->features.fec_supported &&
3707                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
3708                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
3709 }
3710
3711 bool dc_link_should_enable_fec(const struct dc_link *link)
3712 {
3713         bool is_fec_disable = false;
3714         bool ret = false;
3715
3716         if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
3717                         link->local_sink &&
3718                         link->local_sink->edid_caps.panel_patch.disable_fec) ||
3719                         (link->connector_signal == SIGNAL_TYPE_EDP &&
3720                                         link->dc->debug.force_enable_edp_fec == false)) // Disable FEC for eDP
3721                 is_fec_disable = true;
3722
3723         if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
3724                 ret = true;
3725
3726         return ret;
3727 }