drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atomfirmware.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48 #include "dce/dmub_psr.h"
  49 #include "dmub/dmub_srv.h"
  50 #include "inc/hw/panel_cntl.h"
  51 #include "inc/link_enc_cfg.h"
  52 #include "inc/link_dpcd.h"
  53 #include "link/link_dp_trace.h"
  54
  55 #include "dc/dcn30/dcn30_vpg.h"
  56
  57 #define DC_LOGGER_INIT(logger)
  58
  59 #define LINK_INFO(...) \
  60         DC_LOG_HW_HOTPLUG(  \
  61                 __VA_ARGS__)
  62
  63 #define RETIMER_REDRIVER_INFO(...) \
  64         DC_LOG_RETIMER_REDRIVER(  \
  65                 __VA_ARGS__)
  66
  67 /*******************************************************************************
  68  * Private functions
  69  ******************************************************************************/
  70 static void dc_link_destruct(struct dc_link *link)
  71 {
  72         int i;
  73
  74         if (link->hpd_gpio) {
  75                 dal_gpio_destroy_irq(&link->hpd_gpio);
  76                 link->hpd_gpio = NULL;
  77         }
  78
  79         if (link->ddc)
  80                 dal_ddc_service_destroy(&link->ddc);
  81
  82         if (link->panel_cntl)
  83                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
  84
  85         if (link->link_enc) {
  86                 /* Update link encoder resource tracking variables. These are used for
  87                  * the dynamic assignment of link encoders to streams. Virtual links
  88                  * are not assigned encoder resources on creation.
  89                  */
  90                 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
  91                         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
  92                         link->dc->res_pool->dig_link_enc_count--;
  93                 }
  94                 link->link_enc->funcs->destroy(&link->link_enc);
  95         }
  96
  97         if (link->local_sink)
  98                 dc_sink_release(link->local_sink);
  99
 100         for (i = 0; i < link->sink_count; ++i)
 101                 dc_sink_release(link->remote_sinks[i]);
 102 }
 103
 104 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 105                           struct graphics_object_id link_id,
 106                           struct gpio_service *gpio_service)
 107 {
 108         enum bp_result bp_result;
 109         struct graphics_object_hpd_info hpd_info;
 110         struct gpio_pin_info pin_info;
 111
 112         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 113                 return NULL;
 114
 115         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 116                 hpd_info.hpd_int_gpio_uid, &pin_info);
 117
 118         if (bp_result != BP_RESULT_OK) {
 119                 ASSERT(bp_result == BP_RESULT_NORECORD);
 120                 return NULL;
 121         }
 122
 123         return dal_gpio_service_create_irq(gpio_service,
 124                                            pin_info.offset,
 125                                            pin_info.mask);
 126 }
 127
 128 /*
 129  *  Function: program_hpd_filter
 130  *
 131  *  @brief
 132  *     Programs HPD filter on associated HPD line
 133  *
 134  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 135  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 136  *
 137  *  @return
 138  *     true on success, false otherwise
 139  */
 140 static bool program_hpd_filter(const struct dc_link *link)
 141 {
 142         bool result = false;
 143         struct gpio *hpd;
 144         int delay_on_connect_in_ms = 0;
 145         int delay_on_disconnect_in_ms = 0;
 146
 147         if (link->is_hpd_filter_disabled)
 148                 return false;
 149         /* Verify feature is supported */
 150         switch (link->connector_signal) {
 151         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 152         case SIGNAL_TYPE_DVI_DUAL_LINK:
 153         case SIGNAL_TYPE_HDMI_TYPE_A:
 154                 /* Program hpd filter */
 155                 delay_on_connect_in_ms = 500;
 156                 delay_on_disconnect_in_ms = 100;
 157                 break;
 158         case SIGNAL_TYPE_DISPLAY_PORT:
 159         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 160                 /* Program hpd filter to allow DP signal to settle */
 161                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 162                  * only 100ms on DELL U2413
 163                  * 0: some passive dongle still show aux mode instead of i2c
 164                  * 20-50: not enough to hide bouncing HPD with passive dongle.
 165                  * also see intermittent i2c read issues.
 166                  */
 167                 delay_on_connect_in_ms = 80;
 168                 delay_on_disconnect_in_ms = 0;
 169                 break;
 170         case SIGNAL_TYPE_LVDS:
 171         case SIGNAL_TYPE_EDP:
 172         default:
 173                 /* Don't program hpd filter */
 174                 return false;
 175         }
 176
 177         /* Obtain HPD handle */
 178         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 179                            link->ctx->gpio_service);
 180
 181         if (!hpd)
 182                 return result;
 183
 184         /* Setup HPD filtering */
 185         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 186                 struct gpio_hpd_config config;
 187
 188                 config.delay_on_connect = delay_on_connect_in_ms;
 189                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 190
 191                 dal_irq_setup_hpd_filter(hpd, &config);
 192
 193                 dal_gpio_close(hpd);
 194
 195                 result = true;
 196         } else {
 197                 ASSERT_CRITICAL(false);
 198         }
 199
 200         /* Release HPD handle */
 201         dal_gpio_destroy_irq(&hpd);
 202
 203         return result;
 204 }
 205
 206 bool dc_link_wait_for_t12(struct dc_link *link)
 207 {
 208         if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 209                 link->dc->hwss.edp_wait_for_T12(link);
 210
 211                 return true;
 212         }
 213
 214         return false;
 215 }
 216
 217 /**
 218  * dc_link_detect_sink() - Determine if there is a sink connected
 219  *
 220  * @link: pointer to the dc link
 221  * @type: Returned connection type
 222  * Does not detect downstream devices, such as MST sinks
 223  * or display connected through active dongles
 224  */
 225 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 226 {
 227         uint32_t is_hpd_high = 0;
 228         struct gpio *hpd_pin;
 229
 230         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 231                 *type = dc_connection_single;
 232                 return true;
 233         }
 234
 235         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 236                 /*in case it is not on*/
 237                 link->dc->hwss.edp_power_control(link, true);
 238                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 239         }
 240
 241         /* Link may not have physical HPD pin. */
 242         if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
 243                 if (link->is_hpd_pending || !link->hpd_status)
 244                         *type = dc_connection_none;
 245                 else
 246                         *type = dc_connection_single;
 247
 248                 return true;
 249         }
 250
 251         /* todo: may need to lock gpio access */
 252         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 253                                link->ctx->gpio_service);
 254         if (!hpd_pin)
 255                 goto hpd_gpio_failure;
 256
 257         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 258         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 259         dal_gpio_close(hpd_pin);
 260         dal_gpio_destroy_irq(&hpd_pin);
 261
 262         if (is_hpd_high) {
 263                 *type = dc_connection_single;
 264                 /* TODO: need to do the actual detection */
 265         } else {
 266                 *type = dc_connection_none;
 267         }
 268
 269         return true;
 270
 271 hpd_gpio_failure:
 272         return false;
 273 }
 274
 275 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 276 {
 277         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 278
 279         switch (sink_signal) {
 280         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 281         case SIGNAL_TYPE_DVI_DUAL_LINK:
 282         case SIGNAL_TYPE_HDMI_TYPE_A:
 283         case SIGNAL_TYPE_LVDS:
 284         case SIGNAL_TYPE_RGB:
 285                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 286                 break;
 287
 288         case SIGNAL_TYPE_DISPLAY_PORT:
 289         case SIGNAL_TYPE_EDP:
 290                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 291                 break;
 292
 293         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 294                 /* MST does not use I2COverAux, but there is the
 295                  * SPECIAL use case for "immediate dwnstrm device
 296                  * access" (EPR#370830).
 297                  */
 298                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 299                 break;
 300
 301         default:
 302                 break;
 303         }
 304
 305         return transaction_type;
 306 }
 307
 308 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 309                                               struct graphics_object_id downstream)
 310 {
 311         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 312                 switch (downstream.id) {
 313                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 314                         switch (encoder.id) {
 315                         case ENCODER_ID_INTERNAL_DAC1:
 316                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 317                         case ENCODER_ID_INTERNAL_DAC2:
 318                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 319                                 return SIGNAL_TYPE_RGB;
 320                         default:
 321                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 322                         }
 323                 break;
 324                 case CONNECTOR_ID_DUAL_LINK_DVII:
 325                 {
 326                         switch (encoder.id) {
 327                         case ENCODER_ID_INTERNAL_DAC1:
 328                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 329                         case ENCODER_ID_INTERNAL_DAC2:
 330                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 331                                 return SIGNAL_TYPE_RGB;
 332                         default:
 333                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 334                         }
 335                 }
 336                 break;
 337                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 338                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 339                 case CONNECTOR_ID_DUAL_LINK_DVID:
 340                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 341                 case CONNECTOR_ID_VGA:
 342                         return SIGNAL_TYPE_RGB;
 343                 case CONNECTOR_ID_HDMI_TYPE_A:
 344                         return SIGNAL_TYPE_HDMI_TYPE_A;
 345                 case CONNECTOR_ID_LVDS:
 346                         return SIGNAL_TYPE_LVDS;
 347                 case CONNECTOR_ID_DISPLAY_PORT:
 348                         return SIGNAL_TYPE_DISPLAY_PORT;
 349                 case CONNECTOR_ID_EDP:
 350                         return SIGNAL_TYPE_EDP;
 351                 default:
 352                         return SIGNAL_TYPE_NONE;
 353                 }
 354         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 355                 switch (downstream.id) {
 356                 case ENCODER_ID_EXTERNAL_NUTMEG:
 357                 case ENCODER_ID_EXTERNAL_TRAVIS:
 358                         return SIGNAL_TYPE_DISPLAY_PORT;
 359                 default:
 360                         return SIGNAL_TYPE_NONE;
 361                 }
 362         }
 363
 364         return SIGNAL_TYPE_NONE;
 365 }
 366
 367 /*
 368  * dc_link_is_dp_sink_present() - Check if there is a native DP
 369  * or passive DP-HDMI dongle connected
 370  */
 371 bool dc_link_is_dp_sink_present(struct dc_link *link)
 372 {
 373         enum gpio_result gpio_result;
 374         uint32_t clock_pin = 0;
 375         uint8_t retry = 0;
 376         struct ddc *ddc;
 377
 378         enum connector_id connector_id =
 379                 dal_graphics_object_id_get_connector_id(link->link_id);
 380
 381         bool present =
 382                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 383                 (connector_id == CONNECTOR_ID_EDP));
 384
 385         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 386
 387         if (!ddc) {
 388                 BREAK_TO_DEBUGGER();
 389                 return present;
 390         }
 391
 392         /* Open GPIO and set it to I2C mode */
 393         /* Note: this GpioMode_Input will be converted
 394          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 395          * which indicates we need additional delay
 396          */
 397
 398         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 399                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 400                 dal_ddc_close(ddc);
 401
 402                 return present;
 403         }
 404
 405         /*
 406          * Read GPIO: DP sink is present if both clock and data pins are zero
 407          *
 408          * [W/A] plug-unplug DP cable, sometimes customer board has
 409          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 410          * then monitor can't br light up. Add retry 3 times
 411          * But in real passive dongle, it need additional 3ms to detect
 412          */
 413         do {
 414                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 415                 ASSERT(gpio_result == GPIO_RESULT_OK);
 416                 if (clock_pin)
 417                         udelay(1000);
 418                 else
 419                         break;
 420         } while (retry++ < 3);
 421
 422         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 423
 424         dal_ddc_close(ddc);
 425
 426         return present;
 427 }
 428
 429 /*
 430  * @brief
 431  * Detect output sink type
 432  */
 433 static enum signal_type link_detect_sink(struct dc_link *link,
 434                                          enum dc_detect_reason reason)
 435 {
 436         enum signal_type result;
 437         struct graphics_object_id enc_id;
 438
 439         if (link->is_dig_mapping_flexible)
 440                 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
 441         else
 442                 enc_id = link->link_enc->id;
 443         result = get_basic_signal_type(enc_id, link->link_id);
 444
 445         /* Use basic signal type for link without physical connector. */
 446         if (link->ep_type != DISPLAY_ENDPOINT_PHY)
 447                 return result;
 448
 449         /* Internal digital encoder will detect only dongles
 450          * that require digital signal
 451          */
 452
 453         /* Detection mechanism is different
 454          * for different native connectors.
 455          * LVDS connector supports only LVDS signal;
 456          * PCIE is a bus slot, the actual connector needs to be detected first;
 457          * eDP connector supports only eDP signal;
 458          * HDMI should check straps for audio
 459          */
 460
 461         /* PCIE detects the actual connector on add-on board */
 462         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 463                 /* ZAZTODO implement PCIE add-on card detection */
 464         }
 465
 466         switch (link->link_id.id) {
 467         case CONNECTOR_ID_HDMI_TYPE_A: {
 468                 /* check audio support:
 469                  * if native HDMI is not supported, switch to DVI
 470                  */
 471                 struct audio_support *aud_support =
 472                                         &link->dc->res_pool->audio_support;
 473
 474                 if (!aud_support->hdmi_audio_native)
 475                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 476                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 477         }
 478         break;
 479         case CONNECTOR_ID_DISPLAY_PORT: {
 480                 /* DP HPD short pulse. Passive DP dongle will not
 481                  * have short pulse
 482                  */
 483                 if (reason != DETECT_REASON_HPDRX) {
 484                         /* Check whether DP signal detected: if not -
 485                          * we assume signal is DVI; it could be corrected
 486                          * to HDMI after dongle detection
 487                          */
 488                         if (!dm_helpers_is_dp_sink_present(link))
 489                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 490                 }
 491         }
 492         break;
 493         default:
 494         break;
 495         }
 496
 497         return result;
 498 }
 499
 500 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 501                                                                  struct audio_support *audio_support)
 502 {
 503         enum signal_type signal = SIGNAL_TYPE_NONE;
 504
 505         switch (dongle_type) {
 506         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 507                 if (audio_support->hdmi_audio_on_dongle)
 508                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 509                 else
 510                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 511                 break;
 512         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 513                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 514                 break;
 515         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 516                 if (audio_support->hdmi_audio_native)
 517                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 518                 else
 519                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 520                 break;
 521         default:
 522                 signal = SIGNAL_TYPE_NONE;
 523                 break;
 524         }
 525
 526         return signal;
 527 }
 528
 529 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 530                                                     struct display_sink_capability *sink_cap,
 531                                                     struct audio_support *audio_support)
 532 {
 533         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 534
 535         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 536                                                         audio_support);
 537 }
 538
 539 static void link_disconnect_sink(struct dc_link *link)
 540 {
 541         if (link->local_sink) {
 542                 dc_sink_release(link->local_sink);
 543                 link->local_sink = NULL;
 544         }
 545
 546         link->dpcd_sink_count = 0;
 547         //link->dpcd_caps.dpcd_rev.raw = 0;
 548 }
 549
 550 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 551 {
 552         dc_sink_release(link->local_sink);
 553         link->local_sink = prev_sink;
 554 }
 555
 556 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 557 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 558 {
 559         bool ret = false;
 560
 561         switch (signal) {
 562         case SIGNAL_TYPE_DISPLAY_PORT:
 563         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 564                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 565                 break;
 566         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 567         case SIGNAL_TYPE_DVI_DUAL_LINK:
 568         case SIGNAL_TYPE_HDMI_TYPE_A:
 569         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 570          * we can poll for bksv but some displays have an issue with this. Since its so rare
 571          * for a display to not be 1.4 capable, this assumtion is ok
 572          */
 573                 ret = true;
 574                 break;
 575         default:
 576                 break;
 577         }
 578         return ret;
 579 }
 580
 581 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 582 {
 583         bool ret = false;
 584
 585         switch (signal) {
 586         case SIGNAL_TYPE_DISPLAY_PORT:
 587         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 588                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 589                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 590                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 591                 break;
 592         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 593         case SIGNAL_TYPE_DVI_DUAL_LINK:
 594         case SIGNAL_TYPE_HDMI_TYPE_A:
 595                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 596                 break;
 597         default:
 598                 break;
 599         }
 600
 601         return ret;
 602 }
 603
 604 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 605 {
 606         struct hdcp_protection_message msg22;
 607         struct hdcp_protection_message msg14;
 608
 609         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 610         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 611         memset(link->hdcp_caps.rx_caps.raw, 0,
 612                 sizeof(link->hdcp_caps.rx_caps.raw));
 613
 614         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 615                         link->ddc->transaction_type ==
 616                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 617                         link->connector_signal == SIGNAL_TYPE_EDP) {
 618                 msg22.data = link->hdcp_caps.rx_caps.raw;
 619                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 620                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 621         } else {
 622                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 623                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 624                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 625         }
 626         msg22.version = HDCP_VERSION_22;
 627         msg22.link = HDCP_LINK_PRIMARY;
 628         msg22.max_retries = 5;
 629         dc_process_hdcp_msg(signal, link, &msg22);
 630
 631         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 632                 msg14.data = &link->hdcp_caps.bcaps.raw;
 633                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 634                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 635                 msg14.version = HDCP_VERSION_14;
 636                 msg14.link = HDCP_LINK_PRIMARY;
 637                 msg14.max_retries = 5;
 638
 639                 dc_process_hdcp_msg(signal, link, &msg14);
 640         }
 641
 642 }
 643 #endif
 644
 645 static void read_current_link_settings_on_detect(struct dc_link *link)
 646 {
 647         union lane_count_set lane_count_set = {0};
 648         uint8_t link_bw_set;
 649         uint8_t link_rate_set;
 650         uint32_t read_dpcd_retry_cnt = 10;
 651         enum dc_status status = DC_ERROR_UNEXPECTED;
 652         int i;
 653         union max_down_spread max_down_spread = {0};
 654
 655         // Read DPCD 00101h to find out the number of lanes currently set
 656         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 657                 status = core_link_read_dpcd(link,
 658                                              DP_LANE_COUNT_SET,
 659                                              &lane_count_set.raw,
 660                                              sizeof(lane_count_set));
 661                 /* First DPCD read after VDD ON can fail if the particular board
 662                  * does not have HPD pin wired correctly. So if DPCD read fails,
 663                  * which it should never happen, retry a few times. Target worst
 664                  * case scenario of 80 ms.
 665                  */
 666                 if (status == DC_OK) {
 667                         link->cur_link_settings.lane_count =
 668                                         lane_count_set.bits.LANE_COUNT_SET;
 669                         break;
 670                 }
 671
 672                 msleep(8);
 673         }
 674
 675         // Read DPCD 00100h to find if standard link rates are set
 676         core_link_read_dpcd(link, DP_LINK_BW_SET,
 677                             &link_bw_set, sizeof(link_bw_set));
 678
 679         if (link_bw_set == 0) {
 680                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 681                         /* If standard link rates are not being used,
 682                          * Read DPCD 00115h to find the edp link rate set used
 683                          */
 684                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 685                                             &link_rate_set, sizeof(link_rate_set));
 686
 687                         // edp_supported_link_rates_count = 0 for DP
 688                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 689                                 link->cur_link_settings.link_rate =
 690                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 691                                 link->cur_link_settings.link_rate_set = link_rate_set;
 692                                 link->cur_link_settings.use_link_rate_set = true;
 693                         }
 694                 } else {
 695                         // Link Rate not found. Seamless boot may not work.
 696                         ASSERT(false);
 697                 }
 698         } else {
 699                 link->cur_link_settings.link_rate = link_bw_set;
 700                 link->cur_link_settings.use_link_rate_set = false;
 701         }
 702         // Read DPCD 00003h to find the max down spread.
 703         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 704                             &max_down_spread.raw, sizeof(max_down_spread));
 705         link->cur_link_settings.link_spread =
 706                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 707                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 708 }
 709
 710 static bool detect_dp(struct dc_link *link,
 711                       struct display_sink_capability *sink_caps,
 712                       enum dc_detect_reason reason)
 713 {
 714         struct audio_support *audio_support = &link->dc->res_pool->audio_support;
 715
 716         sink_caps->signal = link_detect_sink(link, reason);
 717         sink_caps->transaction_type =
 718                 get_ddc_transaction_type(sink_caps->signal);
 719
 720         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 721                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 722                 if (!detect_dp_sink_caps(link))
 723                         return false;
 724
 725                 if (is_dp_branch_device(link))
 726                         /* DP SST branch */
 727                         link->type = dc_connection_sst_branch;
 728         } else {
 729                 /* DP passive dongles */
 730                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 731                                                                 sink_caps,
 732                                                                 audio_support);
 733                 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 734                 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
 735                 link->dpcd_caps.dpcd_rev.raw = 0;
 736         }
 737
 738         return true;
 739 }
 740
 741 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 742 {
 743         if (old_edid->length != new_edid->length)
 744                 return false;
 745
 746         if (new_edid->length == 0)
 747                 return false;
 748
 749         return (memcmp(old_edid->raw_edid,
 750                        new_edid->raw_edid, new_edid->length) == 0);
 751 }
 752
 753 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 754 {
 755         /**
 756          * something is terribly wrong if time out is > 200ms. (5Hz)
 757          * 500 microseconds * 400 tries us 200 ms
 758          **/
 759         unsigned int sleep_time_in_microseconds = 500;
 760         unsigned int tries_allowed = 400;
 761         bool is_in_alt_mode;
 762         unsigned long long enter_timestamp;
 763         unsigned long long finish_timestamp;
 764         unsigned long long time_taken_in_ns;
 765         int tries_taken;
 766
 767         DC_LOGGER_INIT(link->ctx->logger);
 768
 769         if (!link->link_enc->funcs->is_in_alt_mode)
 770                 return true;
 771
 772         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 773         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 774
 775         if (is_in_alt_mode)
 776                 return true;
 777
 778         enter_timestamp = dm_get_timestamp(link->ctx);
 779
 780         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 781                 udelay(sleep_time_in_microseconds);
 782                 /* ask the link if alt mode is enabled, if so return ok */
 783                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 784                         finish_timestamp = dm_get_timestamp(link->ctx);
 785                         time_taken_in_ns =
 786                                 dm_get_elapse_time_in_ns(link->ctx,
 787                                                          finish_timestamp,
 788                                                          enter_timestamp);
 789                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 790                                        div_u64(time_taken_in_ns, 1000000));
 791                         return true;
 792                 }
 793         }
 794         finish_timestamp = dm_get_timestamp(link->ctx);
 795         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 796                                                     enter_timestamp);
 797         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 798                        div_u64(time_taken_in_ns, 1000000));
 799         return false;
 800 }
 801
 802 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 803 {
 804 #if defined(CONFIG_DRM_AMD_DC_DCN)
 805         /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
 806          * reports DSC support.
 807          */
 808         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
 809                         link->type == dc_connection_mst_branch &&
 810                         link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
 811                         link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
 812                         link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
 813                         !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
 814                 link->wa_flags.dpia_mst_dsc_always_on = true;
 815 #endif
 816 }
 817
 818 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 819 {
 820         /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
 821         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 822                 link->wa_flags.dpia_mst_dsc_always_on = false;
 823 }
 824
 825 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
 826 {
 827         DC_LOGGER_INIT(link->ctx->logger);
 828
 829         LINK_INFO("link=%d, mst branch is now Connected\n",
 830                   link->link_index);
 831
 832         apply_dpia_mst_dsc_always_on_wa(link);
 833         link->type = dc_connection_mst_branch;
 834         dm_helpers_dp_update_branch_info(link->ctx, link);
 835         if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
 836                         link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
 837                 link_disconnect_sink(link);
 838         } else {
 839                 link->type = dc_connection_sst_branch;
 840         }
 841
 842         return link->type == dc_connection_mst_branch;
 843 }
 844
 845 static bool reset_cur_dp_mst_topology(struct dc_link *link)
 846 {
 847         bool result = false;
 848         DC_LOGGER_INIT(link->ctx->logger);
 849
 850         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 851                   link->link_index);
 852
 853         revert_dpia_mst_dsc_always_on_wa(link);
 854         result = dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 855
 856         link->mst_stream_alloc_table.stream_count = 0;
 857         memset(link->mst_stream_alloc_table.stream_allocations,
 858                         0,
 859                         sizeof(link->mst_stream_alloc_table.stream_allocations));
 860         return result;
 861 }
 862
 863 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
 864                 enum dc_detect_reason reason)
 865 {
 866         int i;
 867         bool can_apply_seamless_boot = false;
 868
 869         for (i = 0; i < dc->current_state->stream_count; i++) {
 870                 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
 871                         can_apply_seamless_boot = true;
 872                         break;
 873                 }
 874         }
 875
 876         return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
 877 }
 878
 879 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 880 {
 881 #if defined(CONFIG_DRM_AMD_DC_DCN)
 882         dc_z10_restore(dc);
 883 #endif
 884         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
 885 }
 886
 887 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 888 {
 889         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
 890 }
 891
 892 static void set_all_streams_dpms_off_for_link(struct dc_link *link)
 893 {
 894         int i;
 895         struct pipe_ctx *pipe_ctx;
 896         struct dc_stream_update stream_update;
 897         bool dpms_off = true;
 898         struct link_resource link_res = {0};
 899
 900         memset(&stream_update, 0, sizeof(stream_update));
 901         stream_update.dpms_off = &dpms_off;
 902
 903         for (i = 0; i < MAX_PIPES; i++) {
 904                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
 905                 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
 906                                 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) {
 907                         stream_update.stream = pipe_ctx->stream;
 908                         dc_commit_updates_for_stream(link->ctx->dc, NULL, 0,
 909                                         pipe_ctx->stream, &stream_update,
 910                                         link->ctx->dc->current_state);
 911                 }
 912         }
 913
 914         /* link can be also enabled by vbios. In this case it is not recorded
 915          * in pipe_ctx. Disable link phy here to make sure it is completely off
 916          */
 917         dp_disable_link_phy(link, &link_res, link->connector_signal);
 918 }
 919
 920 static void verify_link_capability_destructive(struct dc_link *link,
 921                 struct dc_sink *sink,
 922                 enum dc_detect_reason reason)
 923 {
 924         bool should_prepare_phy_clocks =
 925                         should_prepare_phy_clocks_for_link_verification(link->dc, reason);
 926
 927         if (should_prepare_phy_clocks)
 928                 prepare_phy_clocks_for_destructive_link_verification(link->dc);
 929
 930         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 931                 struct dc_link_settings known_limit_link_setting =
 932                                 dp_get_max_link_cap(link);
 933                 set_all_streams_dpms_off_for_link(link);
 934                 dp_verify_link_cap_with_retries(
 935                                 link, &known_limit_link_setting,
 936                                 LINK_TRAINING_MAX_VERIFY_RETRY);
 937         } else {
 938                 ASSERT(0);
 939         }
 940
 941         if (should_prepare_phy_clocks)
 942                 restore_phy_clocks_for_destructive_link_verification(link->dc);
 943 }
 944
 945 static void verify_link_capability_non_destructive(struct dc_link *link)
 946 {
 947         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 948                 if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
 949                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 950                         /* TODO - should we check link encoder's max link caps here?
 951                          * How do we know which link encoder to check from?
 952                          */
 953                         link->verified_link_cap = link->reported_link_cap;
 954                 else
 955                         link->verified_link_cap = dp_get_max_link_cap(link);
 956         }
 957 }
 958
 959 static bool should_verify_link_capability_destructively(struct dc_link *link,
 960                 enum dc_detect_reason reason)
 961 {
 962         bool destrictive = false;
 963         struct dc_link_settings max_link_cap;
 964         bool is_link_enc_unavailable = link->link_enc &&
 965                         link->dc->res_pool->funcs->link_encs_assign &&
 966                         !link_enc_cfg_is_link_enc_avail(
 967                                         link->ctx->dc,
 968                                         link->link_enc->preferred_engine,
 969                                         link);
 970
 971         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 972                 max_link_cap = dp_get_max_link_cap(link);
 973                 destrictive = true;
 974
 975                 if (link->dc->debug.skip_detection_link_training ||
 976                                 dc_is_embedded_signal(link->local_sink->sink_signal) ||
 977                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
 978                         destrictive = false;
 979                 } else if (dp_get_link_encoding_format(&max_link_cap) ==
 980                                 DP_8b_10b_ENCODING) {
 981                         if (link->dpcd_caps.is_mst_capable ||
 982                                         is_link_enc_unavailable) {
 983                                 destrictive = false;
 984                         }
 985                 }
 986         } else if (dc_is_hdmi_signal(link->local_sink->sink_signal))
 987                 destrictive = true;
 988
 989         return destrictive;
 990 }
 991
 992 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,
 993                 enum dc_detect_reason reason)
 994 {
 995         if (should_verify_link_capability_destructively(link, reason))
 996                 verify_link_capability_destructive(link, sink, reason);
 997         else
 998                 verify_link_capability_non_destructive(link);
 999 }
1000
1001
1002 /**
1003  * detect_link_and_local_sink() - Detect if a sink is attached to a given link
1004  *
1005  * link->local_sink is created or destroyed as needed.
1006  *
1007  * This does not create remote sinks.
1008  */
1009 static bool detect_link_and_local_sink(struct dc_link *link,
1010                                   enum dc_detect_reason reason)
1011 {
1012         struct dc_sink_init_data sink_init_data = { 0 };
1013         struct display_sink_capability sink_caps = { 0 };
1014         uint32_t i;
1015         bool converter_disable_audio = false;
1016         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
1017         bool same_edid = false;
1018         enum dc_edid_status edid_status;
1019         struct dc_context *dc_ctx = link->ctx;
1020         struct dc_sink *sink = NULL;
1021         struct dc_sink *prev_sink = NULL;
1022         struct dpcd_caps prev_dpcd_caps;
1023         enum dc_connection_type new_connection_type = dc_connection_none;
1024         enum dc_connection_type pre_connection_type = dc_connection_none;
1025         const uint32_t post_oui_delay = 30; // 30ms
1026
1027         DC_LOGGER_INIT(link->ctx->logger);
1028
1029         if (dc_is_virtual_signal(link->connector_signal))
1030                 return false;
1031
1032         if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
1033                 link->connector_signal == SIGNAL_TYPE_EDP) &&
1034                 (!link->dc->config.allow_edp_hotplug_detection)) &&
1035                 link->local_sink) {
1036                 // need to re-write OUI and brightness in resume case
1037                 if (link->connector_signal == SIGNAL_TYPE_EDP &&
1038                         (link->dpcd_sink_ext_caps.bits.oled == 1)) {
1039                         dpcd_set_source_specific_data(link);
1040                         msleep(post_oui_delay);
1041                         dc_link_set_default_brightness_aux(link);
1042                         //TODO: use cached
1043                 }
1044
1045                 return true;
1046         }
1047
1048         if (!dc_link_detect_sink(link, &new_connection_type)) {
1049                 BREAK_TO_DEBUGGER();
1050                 return false;
1051         }
1052
1053         prev_sink = link->local_sink;
1054         if (prev_sink) {
1055                 dc_sink_retain(prev_sink);
1056                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
1057         }
1058
1059         link_disconnect_sink(link);
1060         if (new_connection_type != dc_connection_none) {
1061                 pre_connection_type = link->type;
1062                 link->type = new_connection_type;
1063                 link->link_state_valid = false;
1064
1065                 /* From Disconnected-to-Connected. */
1066                 switch (link->connector_signal) {
1067                 case SIGNAL_TYPE_HDMI_TYPE_A: {
1068                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1069                         if (aud_support->hdmi_audio_native)
1070                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1071                         else
1072                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1073                         break;
1074                 }
1075
1076                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1077                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1078                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1079                         break;
1080                 }
1081
1082                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1083                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1084                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1085                         break;
1086                 }
1087
1088                 case SIGNAL_TYPE_LVDS: {
1089                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1090                         sink_caps.signal = SIGNAL_TYPE_LVDS;
1091                         break;
1092                 }
1093
1094                 case SIGNAL_TYPE_EDP: {
1095                         read_current_link_settings_on_detect(link);
1096
1097                         detect_edp_sink_caps(link);
1098                         read_current_link_settings_on_detect(link);
1099                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1100                         sink_caps.signal = SIGNAL_TYPE_EDP;
1101                         break;
1102                 }
1103
1104                 case SIGNAL_TYPE_DISPLAY_PORT: {
1105                         /* wa HPD high coming too early*/
1106                         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
1107                             link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
1108                                 /* if alt mode times out, return false */
1109                                 if (!wait_for_entering_dp_alt_mode(link))
1110                                         return false;
1111                         }
1112
1113                         if (!detect_dp(link, &sink_caps, reason)) {
1114                                 if (prev_sink)
1115                                         dc_sink_release(prev_sink);
1116                                 return false;
1117                         }
1118
1119                         /* Active SST downstream branch device unplug*/
1120                         if (link->type == dc_connection_sst_branch &&
1121                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1122                                 if (prev_sink)
1123                                         /* Downstream unplug */
1124                                         dc_sink_release(prev_sink);
1125                                 return true;
1126                         }
1127
1128                         /* disable audio for non DP to HDMI active sst converter */
1129                         if (link->type == dc_connection_sst_branch &&
1130                                         is_dp_active_dongle(link) &&
1131                                         (link->dpcd_caps.dongle_type !=
1132                                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1133                                 converter_disable_audio = true;
1134
1135                         // link switch from MST to non-MST stop topology manager
1136                         if (pre_connection_type == dc_connection_mst_branch &&
1137                                         link->type != dc_connection_mst_branch)
1138                                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1139                         break;
1140                 }
1141
1142                 default:
1143                         DC_ERROR("Invalid connector type! signal:%d\n",
1144                                  link->connector_signal);
1145                         if (prev_sink)
1146                                 dc_sink_release(prev_sink);
1147                         return false;
1148                 } /* switch() */
1149
1150                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1151                         link->dpcd_sink_count =
1152                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1153                 else
1154                         link->dpcd_sink_count = 1;
1155
1156                 dal_ddc_service_set_transaction_type(link->ddc,
1157                                                      sink_caps.transaction_type);
1158
1159                 link->aux_mode =
1160                         dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1161
1162                 sink_init_data.link = link;
1163                 sink_init_data.sink_signal = sink_caps.signal;
1164
1165                 sink = dc_sink_create(&sink_init_data);
1166                 if (!sink) {
1167                         DC_ERROR("Failed to create sink!\n");
1168                         if (prev_sink)
1169                                 dc_sink_release(prev_sink);
1170                         return false;
1171                 }
1172
1173                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1174                 sink->converter_disable_audio = converter_disable_audio;
1175
1176                 /* dc_sink_create returns a new reference */
1177                 link->local_sink = sink;
1178
1179                 edid_status = dm_helpers_read_local_edid(link->ctx,
1180                                                          link, sink);
1181
1182                 switch (edid_status) {
1183                 case EDID_BAD_CHECKSUM:
1184                         DC_LOG_ERROR("EDID checksum invalid.\n");
1185                         break;
1186                 case EDID_PARTIAL_VALID:
1187                         DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");
1188                         break;
1189                 case EDID_NO_RESPONSE:
1190                         DC_LOG_ERROR("No EDID read.\n");
1191                         /*
1192                          * Abort detection for non-DP connectors if we have
1193                          * no EDID
1194                          *
1195                          * DP needs to report as connected if HDP is high
1196                          * even if we have no EDID in order to go to
1197                          * fail-safe mode
1198                          */
1199                         if (dc_is_hdmi_signal(link->connector_signal) ||
1200                             dc_is_dvi_signal(link->connector_signal)) {
1201                                 if (prev_sink)
1202                                         dc_sink_release(prev_sink);
1203
1204                                 return false;
1205                         }
1206
1207                         if (link->type == dc_connection_sst_branch &&
1208                                         link->dpcd_caps.dongle_type ==
1209                                                 DISPLAY_DONGLE_DP_VGA_CONVERTER &&
1210                                         reason == DETECT_REASON_HPDRX) {
1211                                 /* Abort detection for DP-VGA adapters when EDID
1212                                  * can't be read and detection reason is VGA-side
1213                                  * hotplug
1214                                  */
1215                                 if (prev_sink)
1216                                         dc_sink_release(prev_sink);
1217                                 link_disconnect_sink(link);
1218
1219                                 return true;
1220                         }
1221
1222                         break;
1223                 default:
1224                         break;
1225                 }
1226
1227                 // Check if edid is the same
1228                 if ((prev_sink) &&
1229                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1230                         same_edid = is_same_edid(&prev_sink->dc_edid,
1231                                                  &sink->dc_edid);
1232
1233                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1234                         link->ctx->dc->debug.hdmi20_disable = true;
1235
1236                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1237                     sink_caps.transaction_type ==
1238                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1239                         /*
1240                          * TODO debug why Dell 2413 doesn't like
1241                          *  two link trainings
1242                          */
1243 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1244                         query_hdcp_capability(sink->sink_signal, link);
1245 #endif
1246                 } else {
1247                         // If edid is the same, then discard new sink and revert back to original sink
1248                         if (same_edid) {
1249                                 link_disconnect_remap(prev_sink, link);
1250                                 sink = prev_sink;
1251                                 prev_sink = NULL;
1252                         }
1253 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1254                         query_hdcp_capability(sink->sink_signal, link);
1255 #endif
1256                 }
1257
1258                 /* HDMI-DVI Dongle */
1259                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1260                     !sink->edid_caps.edid_hdmi)
1261                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1262
1263                 if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
1264                         dp_trace_init(link);
1265
1266                 /* Connectivity log: detection */
1267                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1268                         CONN_DATA_DETECT(link,
1269                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1270                                          DC_EDID_BLOCK_SIZE,
1271                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1272                 }
1273
1274                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1275                         "manufacturer_id = %X, "
1276                         "product_id = %X, "
1277                         "serial_number = %X, "
1278                         "manufacture_week = %d, "
1279                         "manufacture_year = %d, "
1280                         "display_name = %s, "
1281                         "speaker_flag = %d, "
1282                         "audio_mode_count = %d\n",
1283                         __func__,
1284                         sink->edid_caps.manufacturer_id,
1285                         sink->edid_caps.product_id,
1286                         sink->edid_caps.serial_number,
1287                         sink->edid_caps.manufacture_week,
1288                         sink->edid_caps.manufacture_year,
1289                         sink->edid_caps.display_name,
1290                         sink->edid_caps.speaker_flags,
1291                         sink->edid_caps.audio_mode_count);
1292
1293                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1294                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1295                                 "format_code = %d, "
1296                                 "channel_count = %d, "
1297                                 "sample_rate = %d, "
1298                                 "sample_size = %d\n",
1299                                 __func__,
1300                                 i,
1301                                 sink->edid_caps.audio_modes[i].format_code,
1302                                 sink->edid_caps.audio_modes[i].channel_count,
1303                                 sink->edid_caps.audio_modes[i].sample_rate,
1304                                 sink->edid_caps.audio_modes[i].sample_size);
1305                 }
1306         } else {
1307                 /* From Connected-to-Disconnected. */
1308                 link->type = dc_connection_none;
1309                 sink_caps.signal = SIGNAL_TYPE_NONE;
1310                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1311                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1312                  *  the dongle is still there and limits the number of modes we can emulate.
1313                  *  Clear dongle_max_pix_clk on disconnect to fix this
1314                  */
1315                 link->dongle_max_pix_clk = 0;
1316
1317                 dc_link_clear_dprx_states(link);
1318                 dp_trace_reset(link);
1319         }
1320
1321         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1322                   link->link_index, sink,
1323                   (sink_caps.signal ==
1324                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1325                   prev_sink, same_edid);
1326
1327         if (prev_sink)
1328                 dc_sink_release(prev_sink);
1329
1330         return true;
1331 }
1332
1333 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1334 {
1335         bool is_local_sink_detect_success;
1336         bool is_delegated_to_mst_top_mgr = false;
1337         enum dc_connection_type pre_link_type = link->type;
1338
1339         is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
1340
1341         if (is_local_sink_detect_success && link->local_sink)
1342                 verify_link_capability(link, link->local_sink, reason);
1343
1344         if (is_local_sink_detect_success && link->local_sink &&
1345                         dc_is_dp_signal(link->local_sink->sink_signal) &&
1346                         link->dpcd_caps.is_mst_capable)
1347                 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);
1348
1349         if (is_local_sink_detect_success &&
1350                         pre_link_type == dc_connection_mst_branch &&
1351                         link->type != dc_connection_mst_branch)
1352                 is_delegated_to_mst_top_mgr = reset_cur_dp_mst_topology(link);
1353
1354         return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1355 }
1356
1357 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1358 {
1359         uint32_t state;
1360
1361         dal_gpio_lock_pin(dc_link->hpd_gpio);
1362         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1363         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1364
1365         return state;
1366 }
1367
1368 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1369 {
1370         struct gpio *hpd;
1371         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1372
1373         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1374                            link->ctx->gpio_service);
1375
1376         if (hpd) {
1377                 switch (dal_irq_get_source(hpd)) {
1378                 case DC_IRQ_SOURCE_HPD1:
1379                         hpd_id = HPD_SOURCEID1;
1380                 break;
1381                 case DC_IRQ_SOURCE_HPD2:
1382                         hpd_id = HPD_SOURCEID2;
1383                 break;
1384                 case DC_IRQ_SOURCE_HPD3:
1385                         hpd_id = HPD_SOURCEID3;
1386                 break;
1387                 case DC_IRQ_SOURCE_HPD4:
1388                         hpd_id = HPD_SOURCEID4;
1389                 break;
1390                 case DC_IRQ_SOURCE_HPD5:
1391                         hpd_id = HPD_SOURCEID5;
1392                 break;
1393                 case DC_IRQ_SOURCE_HPD6:
1394                         hpd_id = HPD_SOURCEID6;
1395                 break;
1396                 default:
1397                         BREAK_TO_DEBUGGER();
1398                 break;
1399                 }
1400
1401                 dal_gpio_destroy_irq(&hpd);
1402         }
1403
1404         return hpd_id;
1405 }
1406
1407 static enum channel_id get_ddc_line(struct dc_link *link)
1408 {
1409         struct ddc *ddc;
1410         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1411
1412         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1413
1414         if (ddc) {
1415                 switch (dal_ddc_get_line(ddc)) {
1416                 case GPIO_DDC_LINE_DDC1:
1417                         channel = CHANNEL_ID_DDC1;
1418                         break;
1419                 case GPIO_DDC_LINE_DDC2:
1420                         channel = CHANNEL_ID_DDC2;
1421                         break;
1422                 case GPIO_DDC_LINE_DDC3:
1423                         channel = CHANNEL_ID_DDC3;
1424                         break;
1425                 case GPIO_DDC_LINE_DDC4:
1426                         channel = CHANNEL_ID_DDC4;
1427                         break;
1428                 case GPIO_DDC_LINE_DDC5:
1429                         channel = CHANNEL_ID_DDC5;
1430                         break;
1431                 case GPIO_DDC_LINE_DDC6:
1432                         channel = CHANNEL_ID_DDC6;
1433                         break;
1434                 case GPIO_DDC_LINE_DDC_VGA:
1435                         channel = CHANNEL_ID_DDC_VGA;
1436                         break;
1437                 case GPIO_DDC_LINE_I2C_PAD:
1438                         channel = CHANNEL_ID_I2C_PAD;
1439                         break;
1440                 default:
1441                         BREAK_TO_DEBUGGER();
1442                         break;
1443                 }
1444         }
1445
1446         return channel;
1447 }
1448
1449 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1450 {
1451         switch (encoder.id) {
1452         case ENCODER_ID_INTERNAL_UNIPHY:
1453                 switch (encoder.enum_id) {
1454                 case ENUM_ID_1:
1455                         return TRANSMITTER_UNIPHY_A;
1456                 case ENUM_ID_2:
1457                         return TRANSMITTER_UNIPHY_B;
1458                 default:
1459                         return TRANSMITTER_UNKNOWN;
1460                 }
1461         break;
1462         case ENCODER_ID_INTERNAL_UNIPHY1:
1463                 switch (encoder.enum_id) {
1464                 case ENUM_ID_1:
1465                         return TRANSMITTER_UNIPHY_C;
1466                 case ENUM_ID_2:
1467                         return TRANSMITTER_UNIPHY_D;
1468                 default:
1469                         return TRANSMITTER_UNKNOWN;
1470                 }
1471         break;
1472         case ENCODER_ID_INTERNAL_UNIPHY2:
1473                 switch (encoder.enum_id) {
1474                 case ENUM_ID_1:
1475                         return TRANSMITTER_UNIPHY_E;
1476                 case ENUM_ID_2:
1477                         return TRANSMITTER_UNIPHY_F;
1478                 default:
1479                         return TRANSMITTER_UNKNOWN;
1480                 }
1481         break;
1482         case ENCODER_ID_INTERNAL_UNIPHY3:
1483                 switch (encoder.enum_id) {
1484                 case ENUM_ID_1:
1485                         return TRANSMITTER_UNIPHY_G;
1486                 default:
1487                         return TRANSMITTER_UNKNOWN;
1488                 }
1489         break;
1490         case ENCODER_ID_EXTERNAL_NUTMEG:
1491                 switch (encoder.enum_id) {
1492                 case ENUM_ID_1:
1493                         return TRANSMITTER_NUTMEG_CRT;
1494                 default:
1495                         return TRANSMITTER_UNKNOWN;
1496                 }
1497         break;
1498         case ENCODER_ID_EXTERNAL_TRAVIS:
1499                 switch (encoder.enum_id) {
1500                 case ENUM_ID_1:
1501                         return TRANSMITTER_TRAVIS_CRT;
1502                 case ENUM_ID_2:
1503                         return TRANSMITTER_TRAVIS_LCD;
1504                 default:
1505                         return TRANSMITTER_UNKNOWN;
1506                 }
1507         break;
1508         default:
1509                 return TRANSMITTER_UNKNOWN;
1510         }
1511 }
1512
1513 static bool dc_link_construct_legacy(struct dc_link *link,
1514                                      const struct link_init_data *init_params)
1515 {
1516         uint8_t i;
1517         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1518         struct dc_context *dc_ctx = init_params->ctx;
1519         struct encoder_init_data enc_init_data = { 0 };
1520         struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1521         struct integrated_info *info;
1522         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1523         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1524         struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1525
1526         DC_LOGGER_INIT(dc_ctx->logger);
1527
1528         info = kzalloc(sizeof(*info), GFP_KERNEL);
1529         if (!info)
1530                 goto create_fail;
1531
1532         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1533         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1534
1535         link->link_status.dpcd_caps = &link->dpcd_caps;
1536
1537         link->dc = init_params->dc;
1538         link->ctx = dc_ctx;
1539         link->link_index = init_params->link_index;
1540
1541         memset(&link->preferred_training_settings, 0,
1542                sizeof(struct dc_link_training_overrides));
1543         memset(&link->preferred_link_setting, 0,
1544                sizeof(struct dc_link_settings));
1545
1546         link->link_id =
1547                 bios->funcs->get_connector_id(bios, init_params->connector_index);
1548
1549         link->ep_type = DISPLAY_ENDPOINT_PHY;
1550
1551         DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1552
1553         if (bios->funcs->get_disp_connector_caps_info) {
1554                 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1555                 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1556                 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1557         }
1558
1559         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1560                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1561                                      __func__, init_params->connector_index,
1562                                      link->link_id.type, OBJECT_TYPE_CONNECTOR);
1563                 goto create_fail;
1564         }
1565
1566         if (link->dc->res_pool->funcs->link_init)
1567                 link->dc->res_pool->funcs->link_init(link);
1568
1569         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1570                                       link->ctx->gpio_service);
1571
1572         if (link->hpd_gpio) {
1573                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1574                 dal_gpio_unlock_pin(link->hpd_gpio);
1575                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1576
1577                 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1578                 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1579         }
1580
1581         switch (link->link_id.id) {
1582         case CONNECTOR_ID_HDMI_TYPE_A:
1583                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1584
1585                 break;
1586         case CONNECTOR_ID_SINGLE_LINK_DVID:
1587         case CONNECTOR_ID_SINGLE_LINK_DVII:
1588                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1589                 break;
1590         case CONNECTOR_ID_DUAL_LINK_DVID:
1591         case CONNECTOR_ID_DUAL_LINK_DVII:
1592                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1593                 break;
1594         case CONNECTOR_ID_DISPLAY_PORT:
1595                 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1596
1597                 if (link->hpd_gpio)
1598                         link->irq_source_hpd_rx =
1599                                         dal_irq_get_rx_source(link->hpd_gpio);
1600
1601                 break;
1602         case CONNECTOR_ID_EDP:
1603                 link->connector_signal = SIGNAL_TYPE_EDP;
1604
1605                 if (link->hpd_gpio) {
1606                         if (!link->dc->config.allow_edp_hotplug_detection)
1607                                 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1608                         link->irq_source_hpd_rx =
1609                                         dal_irq_get_rx_source(link->hpd_gpio);
1610                 }
1611
1612                 break;
1613         case CONNECTOR_ID_LVDS:
1614                 link->connector_signal = SIGNAL_TYPE_LVDS;
1615                 break;
1616         default:
1617                 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1618                                link->link_id.id);
1619                 goto create_fail;
1620         }
1621
1622         /* TODO: #DAL3 Implement id to str function.*/
1623         LINK_INFO("Connector[%d] description:"
1624                   "signal %d\n",
1625                   init_params->connector_index,
1626                   link->connector_signal);
1627
1628         ddc_service_init_data.ctx = link->ctx;
1629         ddc_service_init_data.id = link->link_id;
1630         ddc_service_init_data.link = link;
1631         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1632
1633         if (!link->ddc) {
1634                 DC_ERROR("Failed to create ddc_service!\n");
1635                 goto ddc_create_fail;
1636         }
1637
1638         if (!link->ddc->ddc_pin) {
1639                 DC_ERROR("Failed to get I2C info for connector!\n");
1640                 goto ddc_create_fail;
1641         }
1642
1643         link->ddc_hw_inst =
1644                 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1645
1646
1647         if (link->dc->res_pool->funcs->panel_cntl_create &&
1648                 (link->link_id.id == CONNECTOR_ID_EDP ||
1649                         link->link_id.id == CONNECTOR_ID_LVDS)) {
1650                 panel_cntl_init_data.ctx = dc_ctx;
1651                 panel_cntl_init_data.inst =
1652                         panel_cntl_init_data.ctx->dc_edp_id_count;
1653                 link->panel_cntl =
1654                         link->dc->res_pool->funcs->panel_cntl_create(
1655                                                                 &panel_cntl_init_data);
1656                 panel_cntl_init_data.ctx->dc_edp_id_count++;
1657
1658                 if (link->panel_cntl == NULL) {
1659                         DC_ERROR("Failed to create link panel_cntl!\n");
1660                         goto panel_cntl_create_fail;
1661                 }
1662         }
1663
1664         enc_init_data.ctx = dc_ctx;
1665         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1666                               &enc_init_data.encoder);
1667         enc_init_data.connector = link->link_id;
1668         enc_init_data.channel = get_ddc_line(link);
1669         enc_init_data.hpd_source = get_hpd_line(link);
1670
1671         link->hpd_src = enc_init_data.hpd_source;
1672
1673         enc_init_data.transmitter =
1674                 translate_encoder_to_transmitter(enc_init_data.encoder);
1675         link->link_enc =
1676                 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1677
1678         if (!link->link_enc) {
1679                 DC_ERROR("Failed to create link encoder!\n");
1680                 goto link_enc_create_fail;
1681         }
1682
1683         DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1684         DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE);
1685
1686         /* Update link encoder tracking variables. These are used for the dynamic
1687          * assignment of link encoders to streams.
1688          */
1689         link->eng_id = link->link_enc->preferred_engine;
1690         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1691         link->dc->res_pool->dig_link_enc_count++;
1692
1693         link->link_enc_hw_inst = link->link_enc->transmitter;
1694
1695         for (i = 0; i < 4; i++) {
1696                 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1697                                              link->link_id, i,
1698                                              &link->device_tag) != BP_RESULT_OK) {
1699                         DC_ERROR("Failed to find device tag!\n");
1700                         goto device_tag_fail;
1701                 }
1702
1703                 /* Look for device tag that matches connector signal,
1704                  * CRT for rgb, LCD for other supported signal tyes
1705                  */
1706                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1707                                                       link->device_tag.dev_id))
1708                         continue;
1709                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1710                     link->connector_signal != SIGNAL_TYPE_RGB)
1711                         continue;
1712                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1713                     link->connector_signal == SIGNAL_TYPE_RGB)
1714                         continue;
1715
1716                 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1717                 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1718                 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1719                 break;
1720         }
1721
1722         if (bios->integrated_info)
1723                 memcpy(info, bios->integrated_info, sizeof(*info));
1724
1725         /* Look for channel mapping corresponding to connector and device tag */
1726         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1727                 struct external_display_path *path =
1728                         &info->ext_disp_conn_info.path[i];
1729
1730                 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1731                     path->device_connector_id.id == link->link_id.id &&
1732                     path->device_connector_id.type == link->link_id.type) {
1733                         if (link->device_tag.acpi_device != 0 &&
1734                             path->device_acpi_enum == link->device_tag.acpi_device) {
1735                                 link->ddi_channel_mapping = path->channel_mapping;
1736                                 link->chip_caps = path->caps;
1737                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1738                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1739                         } else if (path->device_tag ==
1740                                    link->device_tag.dev_id.raw_device_tag) {
1741                                 link->ddi_channel_mapping = path->channel_mapping;
1742                                 link->chip_caps = path->caps;
1743                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1744                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1745                         }
1746
1747                         if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
1748                                 link->bios_forced_drive_settings.VOLTAGE_SWING =
1749                                                 (info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
1750                                 link->bios_forced_drive_settings.PRE_EMPHASIS =
1751                                                 ((info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
1752                         }
1753
1754                         break;
1755                 }
1756         }
1757
1758         if (bios->funcs->get_atom_dc_golden_table)
1759                 bios->funcs->get_atom_dc_golden_table(bios);
1760
1761         /*
1762          * TODO check if GPIO programmed correctly
1763          *
1764          * If GPIO isn't programmed correctly HPD might not rise or drain
1765          * fast enough, leading to bounces.
1766          */
1767         program_hpd_filter(link);
1768
1769         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1770
1771         DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1772         kfree(info);
1773         return true;
1774 device_tag_fail:
1775         link->link_enc->funcs->destroy(&link->link_enc);
1776 link_enc_create_fail:
1777         if (link->panel_cntl != NULL)
1778                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1779 panel_cntl_create_fail:
1780         dal_ddc_service_destroy(&link->ddc);
1781 ddc_create_fail:
1782 create_fail:
1783
1784         if (link->hpd_gpio) {
1785                 dal_gpio_destroy_irq(&link->hpd_gpio);
1786                 link->hpd_gpio = NULL;
1787         }
1788
1789         DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1790         kfree(info);
1791
1792         return false;
1793 }
1794
1795 static bool dc_link_construct_dpia(struct dc_link *link,
1796                                    const struct link_init_data *init_params)
1797 {
1798         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1799         struct dc_context *dc_ctx = init_params->ctx;
1800
1801         DC_LOGGER_INIT(dc_ctx->logger);
1802
1803         /* Initialized irq source for hpd and hpd rx */
1804         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1805         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1806         link->link_status.dpcd_caps = &link->dpcd_caps;
1807
1808         link->dc = init_params->dc;
1809         link->ctx = dc_ctx;
1810         link->link_index = init_params->link_index;
1811
1812         memset(&link->preferred_training_settings, 0,
1813                sizeof(struct dc_link_training_overrides));
1814         memset(&link->preferred_link_setting, 0,
1815                sizeof(struct dc_link_settings));
1816
1817         /* Dummy Init for linkid */
1818         link->link_id.type = OBJECT_TYPE_CONNECTOR;
1819         link->link_id.id = CONNECTOR_ID_DISPLAY_PORT;
1820         link->link_id.enum_id = ENUM_ID_1 + init_params->connector_index;
1821         link->is_internal_display = false;
1822         link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1823         LINK_INFO("Connector[%d] description:signal %d\n",
1824                   init_params->connector_index,
1825                   link->connector_signal);
1826
1827         link->ep_type = DISPLAY_ENDPOINT_USB4_DPIA;
1828         link->is_dig_mapping_flexible = true;
1829
1830         /* TODO: Initialize link : funcs->link_init */
1831
1832         ddc_service_init_data.ctx = link->ctx;
1833         ddc_service_init_data.id = link->link_id;
1834         ddc_service_init_data.link = link;
1835         /* Set indicator for dpia link so that ddc won't be created */
1836         ddc_service_init_data.is_dpia_link = true;
1837
1838         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1839         if (!link->ddc) {
1840                 DC_ERROR("Failed to create ddc_service!\n");
1841                 goto ddc_create_fail;
1842         }
1843
1844         /* Set dpia port index : 0 to number of dpia ports */
1845         link->ddc_hw_inst = init_params->connector_index;
1846
1847         /* TODO: Create link encoder */
1848
1849         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1850
1851         /* Some docks seem to NAK I2C writes to segment pointer with mot=0. */
1852         link->wa_flags.dp_mot_reset_segment = true;
1853
1854         return true;
1855
1856 ddc_create_fail:
1857         return false;
1858 }
1859
1860 static bool dc_link_construct(struct dc_link *link,
1861                               const struct link_init_data *init_params)
1862 {
1863         /* Handle dpia case */
1864         if (init_params->is_dpia_link)
1865                 return dc_link_construct_dpia(link, init_params);
1866         else
1867                 return dc_link_construct_legacy(link, init_params);
1868 }
1869 /*******************************************************************************
1870  * Public functions
1871  ******************************************************************************/
1872 struct dc_link *link_create(const struct link_init_data *init_params)
1873 {
1874         struct dc_link *link =
1875                         kzalloc(sizeof(*link), GFP_KERNEL);
1876
1877         if (NULL == link)
1878                 goto alloc_fail;
1879
1880         if (false == dc_link_construct(link, init_params))
1881                 goto construct_fail;
1882
1883         /*
1884          * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
1885          * since struct preferred_link_setting won't be reset after S3.
1886          */
1887         link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
1888
1889         return link;
1890
1891 construct_fail:
1892         kfree(link);
1893
1894 alloc_fail:
1895         return NULL;
1896 }
1897
1898 void link_destroy(struct dc_link **link)
1899 {
1900         dc_link_destruct(*link);
1901         kfree(*link);
1902         *link = NULL;
1903 }
1904
1905 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1906 {
1907         struct dc_stream_state *stream = pipe_ctx->stream;
1908
1909         if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1910                 struct dc_link *link = stream->link;
1911                 union down_spread_ctrl old_downspread;
1912                 union down_spread_ctrl new_downspread;
1913
1914                 memset(&old_downspread, 0, sizeof(old_downspread));
1915
1916                 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1917                                 &old_downspread.raw, sizeof(old_downspread));
1918
1919                 new_downspread.raw = old_downspread.raw;
1920
1921                 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1922                                 (stream->ignore_msa_timing_param) ? 1 : 0;
1923
1924                 if (new_downspread.raw != old_downspread.raw) {
1925                         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1926                                 &new_downspread.raw, sizeof(new_downspread));
1927                 }
1928
1929         } else {
1930                 dm_helpers_mst_enable_stream_features(stream);
1931         }
1932 }
1933
1934 static enum dc_status enable_link_dp(struct dc_state *state,
1935                                      struct pipe_ctx *pipe_ctx)
1936 {
1937         struct dc_stream_state *stream = pipe_ctx->stream;
1938         enum dc_status status;
1939         bool skip_video_pattern;
1940         struct dc_link *link = stream->link;
1941         struct dc_link_settings link_settings = {0};
1942         bool fec_enable;
1943         int i;
1944         bool apply_seamless_boot_optimization = false;
1945         uint32_t bl_oled_enable_delay = 50; // in ms
1946         const uint32_t post_oui_delay = 30; // 30ms
1947         /* Reduce link bandwidth between failed link training attempts. */
1948         bool do_fallback = false;
1949
1950         // check for seamless boot
1951         for (i = 0; i < state->stream_count; i++) {
1952                 if (state->streams[i]->apply_seamless_boot_optimization) {
1953                         apply_seamless_boot_optimization = true;
1954                         break;
1955                 }
1956         }
1957
1958         /* get link settings for video mode timing */
1959         decide_link_settings(stream, &link_settings);
1960
1961         /* Train with fallback when enabling DPIA link. Conventional links are
1962          * trained with fallback during sink detection.
1963          */
1964         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1965                 do_fallback = true;
1966
1967         /*
1968          * Temporary w/a to get DP2.0 link rates to work with SST.
1969          * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved.
1970          */
1971         if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING &&
1972                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
1973                         link->dc->debug.set_mst_en_for_sst) {
1974                 dp_enable_mst_on_sink(link, true);
1975         }
1976
1977         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1978                 /*in case it is not on*/
1979                 link->dc->hwss.edp_power_control(link, true);
1980                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1981         }
1982
1983         if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING) {
1984                 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
1985         } else {
1986                 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1987                                 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1988                 if (state->clk_mgr && !apply_seamless_boot_optimization)
1989                         state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1990                                         state, false);
1991         }
1992
1993         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1994         dpcd_set_source_specific_data(link);
1995         if (link->dpcd_sink_ext_caps.raw != 0)
1996                 msleep(post_oui_delay);
1997
1998         // similarly, mode switch can cause loss of cable ID
1999         dpcd_write_cable_id_to_dprx(link);
2000
2001         skip_video_pattern = true;
2002
2003         if (link_settings.link_rate == LINK_RATE_LOW)
2004                 skip_video_pattern = false;
2005
2006         if (perform_link_training_with_retries(&link_settings,
2007                                                skip_video_pattern,
2008                                                LINK_TRAINING_ATTEMPTS,
2009                                                pipe_ctx,
2010                                                pipe_ctx->stream->signal,
2011                                                do_fallback)) {
2012                 link->cur_link_settings = link_settings;
2013                 status = DC_OK;
2014         } else {
2015                 status = DC_FAIL_DP_LINK_TRAINING;
2016         }
2017
2018         if (link->preferred_training_settings.fec_enable)
2019                 fec_enable = *link->preferred_training_settings.fec_enable;
2020         else
2021                 fec_enable = true;
2022
2023         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING)
2024                 dp_set_fec_enable(link, fec_enable);
2025
2026         // during mode set we do DP_SET_POWER off then on, aux writes are lost
2027         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
2028                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
2029                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
2030                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
2031                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
2032                         msleep(bl_oled_enable_delay);
2033                 dc_link_backlight_enable_aux(link, true);
2034         }
2035
2036         return status;
2037 }
2038
2039 static enum dc_status enable_link_edp(
2040                 struct dc_state *state,
2041                 struct pipe_ctx *pipe_ctx)
2042 {
2043         enum dc_status status;
2044
2045         status = enable_link_dp(state, pipe_ctx);
2046
2047         return status;
2048 }
2049
2050 static enum dc_status enable_link_dp_mst(
2051                 struct dc_state *state,
2052                 struct pipe_ctx *pipe_ctx)
2053 {
2054         struct dc_link *link = pipe_ctx->stream->link;
2055
2056         /* sink signal type after MST branch is MST. Multiple MST sinks
2057          * share one link. Link DP PHY is enable or training only once.
2058          */
2059         if (link->link_status.link_active)
2060                 return DC_OK;
2061
2062         /* clear payload table */
2063         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
2064
2065         /* to make sure the pending down rep can be processed
2066          * before enabling the link
2067          */
2068         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
2069
2070         /* set the sink to MST mode before enabling the link */
2071         dp_enable_mst_on_sink(link, true);
2072
2073         return enable_link_dp(state, pipe_ctx);
2074 }
2075
2076 void dc_link_blank_all_dp_displays(struct dc *dc)
2077 {
2078         unsigned int i;
2079         uint8_t dpcd_power_state = '\0';
2080         enum dc_status status = DC_ERROR_UNEXPECTED;
2081
2082         for (i = 0; i < dc->link_count; i++) {
2083                 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) ||
2084                         (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL))
2085                         continue;
2086
2087                 /* DP 2.0 spec requires that we read LTTPR caps first */
2088                 dp_retrieve_lttpr_cap(dc->links[i]);
2089                 /* if any of the displays are lit up turn them off */
2090                 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
2091                                                         &dpcd_power_state, sizeof(dpcd_power_state));
2092
2093                 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
2094                         dc_link_blank_dp_stream(dc->links[i], true);
2095         }
2096
2097 }
2098
2099 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init)
2100 {
2101         unsigned int j;
2102         struct dc  *dc = link->ctx->dc;
2103         enum signal_type signal = link->connector_signal;
2104
2105         if ((signal == SIGNAL_TYPE_EDP) ||
2106                 (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
2107                 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
2108                         link->link_enc->funcs->get_dig_frontend &&
2109                         link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
2110                         unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2111
2112                         if (fe != ENGINE_ID_UNKNOWN)
2113                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
2114                                         if (fe == dc->res_pool->stream_enc[j]->id) {
2115                                                 dc->res_pool->stream_enc[j]->funcs->dp_blank(link,
2116                                                                         dc->res_pool->stream_enc[j]);
2117                                                 break;
2118                                         }
2119                                 }
2120                 }
2121
2122                 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)
2123                         dp_receiver_power_ctrl(link, false);
2124         }
2125 }
2126
2127 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
2128                 enum engine_id eng_id,
2129                 struct ext_hdmi_settings *settings)
2130 {
2131         bool result = false;
2132         int i = 0;
2133         struct integrated_info *integrated_info =
2134                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
2135
2136         if (integrated_info == NULL)
2137                 return false;
2138
2139         /*
2140          * Get retimer settings from sbios for passing SI eye test for DCE11
2141          * The setting values are varied based on board revision and port id
2142          * Therefore the setting values of each ports is passed by sbios.
2143          */
2144
2145         // Check if current bios contains ext Hdmi settings
2146         if (integrated_info->gpu_cap_info & 0x20) {
2147                 switch (eng_id) {
2148                 case ENGINE_ID_DIGA:
2149                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
2150                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
2151                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
2152                         memmove(settings->reg_settings,
2153                                         integrated_info->dp0_ext_hdmi_reg_settings,
2154                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
2155                         memmove(settings->reg_settings_6g,
2156                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
2157                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
2158                         result = true;
2159                         break;
2160                 case ENGINE_ID_DIGB:
2161                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
2162                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
2163                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
2164                         memmove(settings->reg_settings,
2165                                         integrated_info->dp1_ext_hdmi_reg_settings,
2166                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
2167                         memmove(settings->reg_settings_6g,
2168                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
2169                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
2170                         result = true;
2171                         break;
2172                 case ENGINE_ID_DIGC:
2173                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
2174                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
2175                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
2176                         memmove(settings->reg_settings,
2177                                         integrated_info->dp2_ext_hdmi_reg_settings,
2178                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
2179                         memmove(settings->reg_settings_6g,
2180                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
2181                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
2182                         result = true;
2183                         break;
2184                 case ENGINE_ID_DIGD:
2185                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
2186                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
2187                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
2188                         memmove(settings->reg_settings,
2189                                         integrated_info->dp3_ext_hdmi_reg_settings,
2190                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
2191                         memmove(settings->reg_settings_6g,
2192                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
2193                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
2194                         result = true;
2195                         break;
2196                 default:
2197                         break;
2198                 }
2199
2200                 if (result == true) {
2201                         // Validate settings from bios integrated info table
2202                         if (settings->slv_addr == 0)
2203                                 return false;
2204                         if (settings->reg_num > 9)
2205                                 return false;
2206                         if (settings->reg_num_6g > 3)
2207                                 return false;
2208
2209                         for (i = 0; i < settings->reg_num; i++) {
2210                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
2211                                         return false;
2212                         }
2213
2214                         for (i = 0; i < settings->reg_num_6g; i++) {
2215                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
2216                                         return false;
2217                         }
2218                 }
2219         }
2220
2221         return result;
2222 }
2223
2224 static bool i2c_write(struct pipe_ctx *pipe_ctx,
2225                 uint8_t address, uint8_t *buffer, uint32_t length)
2226 {
2227         struct i2c_command cmd = {0};
2228         struct i2c_payload payload = {0};
2229
2230         memset(&payload, 0, sizeof(payload));
2231         memset(&cmd, 0, sizeof(cmd));
2232
2233         cmd.number_of_payloads = 1;
2234         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
2235         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
2236
2237         payload.address = address;
2238         payload.data = buffer;
2239         payload.length = length;
2240         payload.write = true;
2241         cmd.payloads = &payload;
2242
2243         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
2244                         pipe_ctx->stream->link, &cmd))
2245                 return true;
2246
2247         return false;
2248 }
2249
2250 static void write_i2c_retimer_setting(
2251                 struct pipe_ctx *pipe_ctx,
2252                 bool is_vga_mode,
2253                 bool is_over_340mhz,
2254                 struct ext_hdmi_settings *settings)
2255 {
2256         uint8_t slave_address = (settings->slv_addr >> 1);
2257         uint8_t buffer[2];
2258         const uint8_t apply_rx_tx_change = 0x4;
2259         uint8_t offset = 0xA;
2260         uint8_t value = 0;
2261         int i = 0;
2262         bool i2c_success = false;
2263         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2264
2265         memset(&buffer, 0, sizeof(buffer));
2266
2267         /* Start Ext-Hdmi programming*/
2268
2269         for (i = 0; i < settings->reg_num; i++) {
2270                 /* Apply 3G settings */
2271                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2272
2273                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
2274                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
2275                         i2c_success = i2c_write(pipe_ctx, slave_address,
2276                                                 buffer, sizeof(buffer));
2277                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2278                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2279                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2280
2281                         if (!i2c_success)
2282                                 goto i2c_write_fail;
2283
2284                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2285                          * needs to be set to 1 on every 0xA-0xC write.
2286                          */
2287                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
2288                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
2289                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
2290
2291                                 /* Query current value from offset 0xA */
2292                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
2293                                         value = settings->reg_settings[i].i2c_reg_val;
2294                                 else {
2295                                         i2c_success =
2296                                                 dal_ddc_service_query_ddc_data(
2297                                                 pipe_ctx->stream->link->ddc,
2298                                                 slave_address, &offset, 1, &value, 1);
2299                                         if (!i2c_success)
2300                                                 goto i2c_write_fail;
2301                                 }
2302
2303                                 buffer[0] = offset;
2304                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2305                                 buffer[1] = value | apply_rx_tx_change;
2306                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2307                                                 buffer, sizeof(buffer));
2308                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2309                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2310                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2311                                 if (!i2c_success)
2312                                         goto i2c_write_fail;
2313                         }
2314                 }
2315         }
2316
2317         /* Apply 3G settings */
2318         if (is_over_340mhz) {
2319                 for (i = 0; i < settings->reg_num_6g; i++) {
2320                         /* Apply 3G settings */
2321                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2322
2323                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2324                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2325                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2326                                                         buffer, sizeof(buffer));
2327                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2328                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2329                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2330
2331                                 if (!i2c_success)
2332                                         goto i2c_write_fail;
2333
2334                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2335                                  * needs to be set to 1 on every 0xA-0xC write.
2336                                  */
2337                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2338                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2339                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2340
2341                                         /* Query current value from offset 0xA */
2342                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2343                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
2344                                         else {
2345                                                 i2c_success =
2346                                                                 dal_ddc_service_query_ddc_data(
2347                                                                 pipe_ctx->stream->link->ddc,
2348                                                                 slave_address, &offset, 1, &value, 1);
2349                                                 if (!i2c_success)
2350                                                         goto i2c_write_fail;
2351                                         }
2352
2353                                         buffer[0] = offset;
2354                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
2355                                         buffer[1] = value | apply_rx_tx_change;
2356                                         i2c_success = i2c_write(pipe_ctx, slave_address,
2357                                                         buffer, sizeof(buffer));
2358                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2359                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2360                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2361                                         if (!i2c_success)
2362                                                 goto i2c_write_fail;
2363                                 }
2364                         }
2365                 }
2366         }
2367
2368         if (is_vga_mode) {
2369                 /* Program additional settings if using 640x480 resolution */
2370
2371                 /* Write offset 0xFF to 0x01 */
2372                 buffer[0] = 0xff;
2373                 buffer[1] = 0x01;
2374                 i2c_success = i2c_write(pipe_ctx, slave_address,
2375                                 buffer, sizeof(buffer));
2376                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2377                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2378                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2379                 if (!i2c_success)
2380                         goto i2c_write_fail;
2381
2382                 /* Write offset 0x00 to 0x23 */
2383                 buffer[0] = 0x00;
2384                 buffer[1] = 0x23;
2385                 i2c_success = i2c_write(pipe_ctx, slave_address,
2386                                 buffer, sizeof(buffer));
2387                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2388                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2389                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2390                 if (!i2c_success)
2391                         goto i2c_write_fail;
2392
2393                 /* Write offset 0xff to 0x00 */
2394                 buffer[0] = 0xff;
2395                 buffer[1] = 0x00;
2396                 i2c_success = i2c_write(pipe_ctx, slave_address,
2397                                 buffer, sizeof(buffer));
2398                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2399                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2400                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2401                 if (!i2c_success)
2402                         goto i2c_write_fail;
2403
2404         }
2405
2406         return;
2407
2408 i2c_write_fail:
2409         DC_LOG_DEBUG("Set retimer failed");
2410 }
2411
2412 static void write_i2c_default_retimer_setting(
2413                 struct pipe_ctx *pipe_ctx,
2414                 bool is_vga_mode,
2415                 bool is_over_340mhz)
2416 {
2417         uint8_t slave_address = (0xBA >> 1);
2418         uint8_t buffer[2];
2419         bool i2c_success = false;
2420         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2421
2422         memset(&buffer, 0, sizeof(buffer));
2423
2424         /* Program Slave Address for tuning single integrity */
2425         /* Write offset 0x0A to 0x13 */
2426         buffer[0] = 0x0A;
2427         buffer[1] = 0x13;
2428         i2c_success = i2c_write(pipe_ctx, slave_address,
2429                         buffer, sizeof(buffer));
2430         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2431                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2432                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2433         if (!i2c_success)
2434                 goto i2c_write_fail;
2435
2436         /* Write offset 0x0A to 0x17 */
2437         buffer[0] = 0x0A;
2438         buffer[1] = 0x17;
2439         i2c_success = i2c_write(pipe_ctx, slave_address,
2440                         buffer, sizeof(buffer));
2441         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2442                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2443                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2444         if (!i2c_success)
2445                 goto i2c_write_fail;
2446
2447         /* Write offset 0x0B to 0xDA or 0xD8 */
2448         buffer[0] = 0x0B;
2449         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2450         i2c_success = i2c_write(pipe_ctx, slave_address,
2451                         buffer, sizeof(buffer));
2452         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2453                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2454                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2455         if (!i2c_success)
2456                 goto i2c_write_fail;
2457
2458         /* Write offset 0x0A to 0x17 */
2459         buffer[0] = 0x0A;
2460         buffer[1] = 0x17;
2461         i2c_success = i2c_write(pipe_ctx, slave_address,
2462                         buffer, sizeof(buffer));
2463         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2464                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2465                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2466         if (!i2c_success)
2467                 goto i2c_write_fail;
2468
2469         /* Write offset 0x0C to 0x1D or 0x91 */
2470         buffer[0] = 0x0C;
2471         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2472         i2c_success = i2c_write(pipe_ctx, slave_address,
2473                         buffer, sizeof(buffer));
2474         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2475                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2476                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2477         if (!i2c_success)
2478                 goto i2c_write_fail;
2479
2480         /* Write offset 0x0A to 0x17 */
2481         buffer[0] = 0x0A;
2482         buffer[1] = 0x17;
2483         i2c_success = i2c_write(pipe_ctx, slave_address,
2484                         buffer, sizeof(buffer));
2485         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2486                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2487                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2488         if (!i2c_success)
2489                 goto i2c_write_fail;
2490
2491
2492         if (is_vga_mode) {
2493                 /* Program additional settings if using 640x480 resolution */
2494
2495                 /* Write offset 0xFF to 0x01 */
2496                 buffer[0] = 0xff;
2497                 buffer[1] = 0x01;
2498                 i2c_success = i2c_write(pipe_ctx, slave_address,
2499                                 buffer, sizeof(buffer));
2500                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2501                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2502                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2503                 if (!i2c_success)
2504                         goto i2c_write_fail;
2505
2506                 /* Write offset 0x00 to 0x23 */
2507                 buffer[0] = 0x00;
2508                 buffer[1] = 0x23;
2509                 i2c_success = i2c_write(pipe_ctx, slave_address,
2510                                 buffer, sizeof(buffer));
2511                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2512                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2513                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2514                 if (!i2c_success)
2515                         goto i2c_write_fail;
2516
2517                 /* Write offset 0xff to 0x00 */
2518                 buffer[0] = 0xff;
2519                 buffer[1] = 0x00;
2520                 i2c_success = i2c_write(pipe_ctx, slave_address,
2521                                 buffer, sizeof(buffer));
2522                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2523                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2524                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2525                 if (!i2c_success)
2526                         goto i2c_write_fail;
2527         }
2528
2529         return;
2530
2531 i2c_write_fail:
2532         DC_LOG_DEBUG("Set default retimer failed");
2533 }
2534
2535 static void write_i2c_redriver_setting(
2536                 struct pipe_ctx *pipe_ctx,
2537                 bool is_over_340mhz)
2538 {
2539         uint8_t slave_address = (0xF0 >> 1);
2540         uint8_t buffer[16];
2541         bool i2c_success = false;
2542         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2543
2544         memset(&buffer, 0, sizeof(buffer));
2545
2546         // Program Slave Address for tuning single integrity
2547         buffer[3] = 0x4E;
2548         buffer[4] = 0x4E;
2549         buffer[5] = 0x4E;
2550         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2551
2552         i2c_success = i2c_write(pipe_ctx, slave_address,
2553                                         buffer, sizeof(buffer));
2554         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2555                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2556                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2557                 i2c_success = %d\n",
2558                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2559
2560         if (!i2c_success)
2561                 DC_LOG_DEBUG("Set redriver failed");
2562 }
2563
2564 static void disable_link(struct dc_link *link, const struct link_resource *link_res,
2565                 enum signal_type signal)
2566 {
2567         /*
2568          * TODO: implement call for dp_set_hw_test_pattern
2569          * it is needed for compliance testing
2570          */
2571
2572         /* Here we need to specify that encoder output settings
2573          * need to be calculated as for the set mode,
2574          * it will lead to querying dynamic link capabilities
2575          * which should be done before enable output
2576          */
2577
2578         if (dc_is_dp_signal(signal)) {
2579                 /* SST DP, eDP */
2580                 struct dc_link_settings link_settings = link->cur_link_settings;
2581                 if (dc_is_dp_sst_signal(signal))
2582                         dp_disable_link_phy(link, link_res, signal);
2583                 else
2584                         dp_disable_link_phy_mst(link, link_res, signal);
2585
2586                 if (dc_is_dp_sst_signal(signal) ||
2587                                 link->mst_stream_alloc_table.stream_count == 0) {
2588                         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
2589                                 dp_set_fec_enable(link, false);
2590                                 dp_set_fec_ready(link, link_res, false);
2591                         }
2592                 }
2593         } else {
2594                 if (signal != SIGNAL_TYPE_VIRTUAL)
2595                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2596         }
2597
2598         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2599                 /* MST disable link only when no stream use the link */
2600                 if (link->mst_stream_alloc_table.stream_count <= 0)
2601                         link->link_status.link_active = false;
2602         } else {
2603                 link->link_status.link_active = false;
2604         }
2605 }
2606
2607 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2608 {
2609         struct dc_stream_state *stream = pipe_ctx->stream;
2610         struct dc_link *link = stream->link;
2611         enum dc_color_depth display_color_depth;
2612         enum engine_id eng_id;
2613         struct ext_hdmi_settings settings = {0};
2614         bool is_over_340mhz = false;
2615         bool is_vga_mode = (stream->timing.h_addressable == 640)
2616                         && (stream->timing.v_addressable == 480);
2617
2618         if (stream->phy_pix_clk == 0)
2619                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2620         if (stream->phy_pix_clk > 340000)
2621                 is_over_340mhz = true;
2622
2623         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2624                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2625                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2626                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2627                         /* DP159, Retimer settings */
2628                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2629
2630                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2631                                 write_i2c_retimer_setting(pipe_ctx,
2632                                                 is_vga_mode, is_over_340mhz, &settings);
2633                         } else {
2634                                 write_i2c_default_retimer_setting(pipe_ctx,
2635                                                 is_vga_mode, is_over_340mhz);
2636                         }
2637                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2638                         /* PI3EQX1204, Redriver settings */
2639                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2640                 }
2641         }
2642
2643         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2644                 dal_ddc_service_write_scdc_data(
2645                         stream->link->ddc,
2646                         stream->phy_pix_clk,
2647                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2648
2649         memset(&stream->link->cur_link_settings, 0,
2650                         sizeof(struct dc_link_settings));
2651
2652         display_color_depth = stream->timing.display_color_depth;
2653         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2654                 display_color_depth = COLOR_DEPTH_888;
2655
2656         link->link_enc->funcs->enable_tmds_output(
2657                         link->link_enc,
2658                         pipe_ctx->clock_source->id,
2659                         display_color_depth,
2660                         pipe_ctx->stream->signal,
2661                         stream->phy_pix_clk);
2662
2663         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2664                 dal_ddc_service_read_scdc_data(link->ddc);
2665 }
2666
2667 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2668 {
2669         struct dc_stream_state *stream = pipe_ctx->stream;
2670         struct dc_link *link = stream->link;
2671
2672         if (stream->phy_pix_clk == 0)
2673                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2674
2675         memset(&stream->link->cur_link_settings, 0,
2676                         sizeof(struct dc_link_settings));
2677
2678         link->link_enc->funcs->enable_lvds_output(
2679                         link->link_enc,
2680                         pipe_ctx->clock_source->id,
2681                         stream->phy_pix_clk);
2682
2683 }
2684
2685 /****************************enable_link***********************************/
2686 static enum dc_status enable_link(
2687                 struct dc_state *state,
2688                 struct pipe_ctx *pipe_ctx)
2689 {
2690         enum dc_status status = DC_ERROR_UNEXPECTED;
2691         struct dc_stream_state *stream = pipe_ctx->stream;
2692         struct dc_link *link = stream->link;
2693
2694         /* There's some scenarios where driver is unloaded with display
2695          * still enabled. When driver is reloaded, it may cause a display
2696          * to not light up if there is a mismatch between old and new
2697          * link settings. Need to call disable first before enabling at
2698          * new link settings.
2699          */
2700         if (link->link_status.link_active) {
2701                 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
2702         }
2703
2704         switch (pipe_ctx->stream->signal) {
2705         case SIGNAL_TYPE_DISPLAY_PORT:
2706                 status = enable_link_dp(state, pipe_ctx);
2707                 break;
2708         case SIGNAL_TYPE_EDP:
2709                 status = enable_link_edp(state, pipe_ctx);
2710                 break;
2711         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2712                 status = enable_link_dp_mst(state, pipe_ctx);
2713                 msleep(200);
2714                 break;
2715         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2716         case SIGNAL_TYPE_DVI_DUAL_LINK:
2717         case SIGNAL_TYPE_HDMI_TYPE_A:
2718                 enable_link_hdmi(pipe_ctx);
2719                 status = DC_OK;
2720                 break;
2721         case SIGNAL_TYPE_LVDS:
2722                 enable_link_lvds(pipe_ctx);
2723                 status = DC_OK;
2724                 break;
2725         case SIGNAL_TYPE_VIRTUAL:
2726                 status = DC_OK;
2727                 break;
2728         default:
2729                 break;
2730         }
2731
2732         if (status == DC_OK)
2733                 pipe_ctx->stream->link->link_status.link_active = true;
2734
2735         return status;
2736 }
2737
2738 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2739 {
2740
2741         uint32_t pxl_clk = timing->pix_clk_100hz;
2742
2743         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2744                 pxl_clk /= 2;
2745         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2746                 pxl_clk = pxl_clk * 2 / 3;
2747
2748         if (timing->display_color_depth == COLOR_DEPTH_101010)
2749                 pxl_clk = pxl_clk * 10 / 8;
2750         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2751                 pxl_clk = pxl_clk * 12 / 8;
2752
2753         return pxl_clk;
2754 }
2755
2756 static bool dp_active_dongle_validate_timing(
2757                 const struct dc_crtc_timing *timing,
2758                 const struct dpcd_caps *dpcd_caps)
2759 {
2760         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2761
2762         switch (dpcd_caps->dongle_type) {
2763         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2764         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2765         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2766                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2767                         return true;
2768                 else
2769                         return false;
2770         default:
2771                 break;
2772         }
2773
2774         if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
2775                         dongle_caps->extendedCapValid == true) {
2776                 /* Check Pixel Encoding */
2777                 switch (timing->pixel_encoding) {
2778                 case PIXEL_ENCODING_RGB:
2779                 case PIXEL_ENCODING_YCBCR444:
2780                         break;
2781                 case PIXEL_ENCODING_YCBCR422:
2782                         if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2783                                 return false;
2784                         break;
2785                 case PIXEL_ENCODING_YCBCR420:
2786                         if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2787                                 return false;
2788                         break;
2789                 default:
2790                         /* Invalid Pixel Encoding*/
2791                         return false;
2792                 }
2793
2794                 switch (timing->display_color_depth) {
2795                 case COLOR_DEPTH_666:
2796                 case COLOR_DEPTH_888:
2797                         /*888 and 666 should always be supported*/
2798                         break;
2799                 case COLOR_DEPTH_101010:
2800                         if (dongle_caps->dp_hdmi_max_bpc < 10)
2801                                 return false;
2802                         break;
2803                 case COLOR_DEPTH_121212:
2804                         if (dongle_caps->dp_hdmi_max_bpc < 12)
2805                                 return false;
2806                         break;
2807                 case COLOR_DEPTH_141414:
2808                 case COLOR_DEPTH_161616:
2809                 default:
2810                         /* These color depths are currently not supported */
2811                         return false;
2812                 }
2813
2814                 /* Check 3D format */
2815                 switch (timing->timing_3d_format) {
2816                 case TIMING_3D_FORMAT_NONE:
2817                 case TIMING_3D_FORMAT_FRAME_ALTERNATE:
2818                         /*Only frame alternate 3D is supported on active dongle*/
2819                         break;
2820                 default:
2821                         /*other 3D formats are not supported due to bad infoframe translation */
2822                         return false;
2823                 }
2824
2825 #if defined(CONFIG_DRM_AMD_DC_DCN)
2826                 if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter
2827                         struct dc_crtc_timing outputTiming = *timing;
2828
2829                         if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
2830                                 /* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */
2831                                 outputTiming.flags.DSC = 0;
2832                         if (dc_bandwidth_in_kbps_from_timing(&outputTiming) > dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
2833                                 return false;
2834                 } else { // DP to HDMI TMDS converter
2835                         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2836                                 return false;
2837                 }
2838 #else
2839                 if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2840                         return false;
2841 #endif
2842         }
2843
2844         if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
2845                         dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
2846                         dongle_caps->dfp_cap_ext.supported) {
2847
2848                 if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
2849                         return false;
2850
2851                 if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
2852                         return false;
2853
2854                 if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
2855                         return false;
2856
2857                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
2858                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2859                                 return false;
2860                         if (timing->display_color_depth == COLOR_DEPTH_666 &&
2861                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
2862                                 return false;
2863                         else if (timing->display_color_depth == COLOR_DEPTH_888 &&
2864                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
2865                                 return false;
2866                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2867                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
2868                                 return false;
2869                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2870                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
2871                                 return false;
2872                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2873                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
2874                                 return false;
2875                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
2876                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2877                                 return false;
2878                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2879                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
2880                                 return false;
2881                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2882                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
2883                                 return false;
2884                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2885                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
2886                                 return false;
2887                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2888                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
2889                                 return false;
2890                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
2891                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2892                                 return false;
2893                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2894                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
2895                                 return false;
2896                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2897                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
2898                                 return false;
2899                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2900                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
2901                                 return false;
2902                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2903                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
2904                                 return false;
2905                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2906                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2907                                 return false;
2908                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2909                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
2910                                 return false;
2911                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2912                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
2913                                 return false;
2914                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2915                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
2916                                 return false;
2917                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2918                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
2919                                 return false;
2920                 }
2921         }
2922
2923         return true;
2924 }
2925
2926 enum dc_status dc_link_validate_mode_timing(
2927                 const struct dc_stream_state *stream,
2928                 struct dc_link *link,
2929                 const struct dc_crtc_timing *timing)
2930 {
2931         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2932         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2933
2934         /* A hack to avoid failing any modes for EDID override feature on
2935          * topology change such as lower quality cable for DP or different dongle
2936          */
2937         if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2938                 return DC_OK;
2939
2940         /* Passive Dongle */
2941         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2942                 return DC_EXCEED_DONGLE_CAP;
2943
2944         /* Active Dongle*/
2945         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2946                 return DC_EXCEED_DONGLE_CAP;
2947
2948         switch (stream->signal) {
2949         case SIGNAL_TYPE_EDP:
2950         case SIGNAL_TYPE_DISPLAY_PORT:
2951                 if (!dp_validate_mode_timing(
2952                                 link,
2953                                 timing))
2954                         return DC_NO_DP_LINK_BANDWIDTH;
2955                 break;
2956
2957         default:
2958                 break;
2959         }
2960
2961         return DC_OK;
2962 }
2963
2964 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2965 {
2966         int i;
2967         struct dc *dc = NULL;
2968         struct abm *abm = NULL;
2969
2970         if (!link || !link->ctx)
2971                 return NULL;
2972
2973         dc = link->ctx->dc;
2974
2975         for (i = 0; i < MAX_PIPES; i++) {
2976                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2977                 struct dc_stream_state *stream = pipe_ctx.stream;
2978
2979                 if (stream && stream->link == link) {
2980                         abm = pipe_ctx.stream_res.abm;
2981                         break;
2982                 }
2983         }
2984         return abm;
2985 }
2986
2987 int dc_link_get_backlight_level(const struct dc_link *link)
2988 {
2989         struct abm *abm = get_abm_from_stream_res(link);
2990         struct panel_cntl *panel_cntl = link->panel_cntl;
2991         struct dc  *dc = link->ctx->dc;
2992         struct dmcu *dmcu = dc->res_pool->dmcu;
2993         bool fw_set_brightness = true;
2994
2995         if (dmcu)
2996                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2997
2998         if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
2999                 return panel_cntl->funcs->get_current_backlight(panel_cntl);
3000         else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
3001                 return (int) abm->funcs->get_current_backlight(abm);
3002         else
3003                 return DC_ERROR_UNEXPECTED;
3004 }
3005
3006 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
3007 {
3008         struct abm *abm = get_abm_from_stream_res(link);
3009
3010         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
3011                 return DC_ERROR_UNEXPECTED;
3012
3013         return (int) abm->funcs->get_target_backlight(abm);
3014 }
3015
3016 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
3017 {
3018         int i;
3019         struct dc *dc = link->ctx->dc;
3020         struct pipe_ctx *pipe_ctx = NULL;
3021
3022         for (i = 0; i < MAX_PIPES; i++) {
3023                 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
3024                         if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
3025                                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
3026                                 break;
3027                         }
3028                 }
3029         }
3030
3031         return pipe_ctx;
3032 }
3033
3034 bool dc_link_set_backlight_level(const struct dc_link *link,
3035                 uint32_t backlight_pwm_u16_16,
3036                 uint32_t frame_ramp)
3037 {
3038         struct dc  *dc = link->ctx->dc;
3039
3040         DC_LOGGER_INIT(link->ctx->logger);
3041         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
3042                         backlight_pwm_u16_16, backlight_pwm_u16_16);
3043
3044         if (dc_is_embedded_signal(link->connector_signal)) {
3045                 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
3046
3047                 if (pipe_ctx) {
3048                         /* Disable brightness ramping when the display is blanked
3049                          * as it can hang the DMCU
3050                          */
3051                         if (pipe_ctx->plane_state == NULL)
3052                                 frame_ramp = 0;
3053                 } else {
3054                         return false;
3055                 }
3056
3057                 dc->hwss.set_backlight_level(
3058                                 pipe_ctx,
3059                                 backlight_pwm_u16_16,
3060                                 frame_ramp);
3061         }
3062         return true;
3063 }
3064
3065 bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
3066                 bool wait, bool force_static, const unsigned int *power_opts)
3067 {
3068         struct dc  *dc = link->ctx->dc;
3069         struct dmcu *dmcu = dc->res_pool->dmcu;
3070         struct dmub_psr *psr = dc->res_pool->psr;
3071         unsigned int panel_inst;
3072
3073         if (psr == NULL && force_static)
3074                 return false;
3075
3076         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3077                 return false;
3078
3079         /* Set power optimization flag */
3080         if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
3081                 link->psr_settings.psr_power_opt = *power_opts;
3082
3083                 if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
3084                         psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
3085         }
3086
3087         /* Enable or Disable PSR */
3088         if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
3089                 link->psr_settings.psr_allow_active = *allow_active;
3090
3091 #if defined(CONFIG_DRM_AMD_DC_DCN)
3092                 if (!link->psr_settings.psr_allow_active)
3093                         dc_z10_restore(dc);
3094 #endif
3095
3096                 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
3097                         if (force_static && psr->funcs->psr_force_static)
3098                                 psr->funcs->psr_force_static(psr, panel_inst);
3099                         psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
3100                 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
3101                         link->psr_settings.psr_feature_enabled)
3102                         dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
3103                 else
3104                         return false;
3105         }
3106
3107         return true;
3108 }
3109
3110 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
3111 {
3112         struct dc  *dc = link->ctx->dc;
3113         struct dmcu *dmcu = dc->res_pool->dmcu;
3114         struct dmub_psr *psr = dc->res_pool->psr;
3115         unsigned int panel_inst;
3116
3117         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3118                 return false;
3119
3120         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3121                 psr->funcs->psr_get_state(psr, state, panel_inst);
3122         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
3123                 dmcu->funcs->get_psr_state(dmcu, state);
3124
3125         return true;
3126 }
3127
3128 static inline enum physical_phy_id
3129 transmitter_to_phy_id(enum transmitter transmitter_value)
3130 {
3131         switch (transmitter_value) {
3132         case TRANSMITTER_UNIPHY_A:
3133                 return PHYLD_0;
3134         case TRANSMITTER_UNIPHY_B:
3135                 return PHYLD_1;
3136         case TRANSMITTER_UNIPHY_C:
3137                 return PHYLD_2;
3138         case TRANSMITTER_UNIPHY_D:
3139                 return PHYLD_3;
3140         case TRANSMITTER_UNIPHY_E:
3141                 return PHYLD_4;
3142         case TRANSMITTER_UNIPHY_F:
3143                 return PHYLD_5;
3144         case TRANSMITTER_NUTMEG_CRT:
3145                 return PHYLD_6;
3146         case TRANSMITTER_TRAVIS_CRT:
3147                 return PHYLD_7;
3148         case TRANSMITTER_TRAVIS_LCD:
3149                 return PHYLD_8;
3150         case TRANSMITTER_UNIPHY_G:
3151                 return PHYLD_9;
3152         case TRANSMITTER_COUNT:
3153                 return PHYLD_COUNT;
3154         case TRANSMITTER_UNKNOWN:
3155                 return PHYLD_UNKNOWN;
3156         default:
3157                 WARN_ONCE(1, "Unknown transmitter value %d\n",
3158                           transmitter_value);
3159                 return PHYLD_UNKNOWN;
3160         }
3161 }
3162
3163 bool dc_link_setup_psr(struct dc_link *link,
3164                 const struct dc_stream_state *stream, struct psr_config *psr_config,
3165                 struct psr_context *psr_context)
3166 {
3167         struct dc *dc;
3168         struct dmcu *dmcu;
3169         struct dmub_psr *psr;
3170         int i;
3171         unsigned int panel_inst;
3172         /* updateSinkPsrDpcdConfig*/
3173         union dpcd_psr_configuration psr_configuration;
3174
3175         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
3176
3177         if (!link)
3178                 return false;
3179
3180         dc = link->ctx->dc;
3181         dmcu = dc->res_pool->dmcu;
3182         psr = dc->res_pool->psr;
3183
3184         if (!dmcu && !psr)
3185                 return false;
3186
3187         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3188                 return false;
3189
3190
3191         memset(&psr_configuration, 0, sizeof(psr_configuration));
3192
3193         psr_configuration.bits.ENABLE                    = 1;
3194         psr_configuration.bits.CRC_VERIFICATION          = 1;
3195         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
3196                         psr_config->psr_frame_capture_indication_req;
3197
3198         /* Check for PSR v2*/
3199         if (psr_config->psr_version == 0x2) {
3200                 /* For PSR v2 selective update.
3201                  * Indicates whether sink should start capturing
3202                  * immediately following active scan line,
3203                  * or starting with the 2nd active scan line.
3204                  */
3205                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
3206                 /*For PSR v2, determines whether Sink should generate
3207                  * IRQ_HPD when CRC mismatch is detected.
3208                  */
3209                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
3210         }
3211
3212         dm_helpers_dp_write_dpcd(
3213                 link->ctx,
3214                 link,
3215                 368,
3216                 &psr_configuration.raw,
3217                 sizeof(psr_configuration.raw));
3218
3219         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
3220         psr_context->transmitterId = link->link_enc->transmitter;
3221         psr_context->engineId = link->link_enc->preferred_engine;
3222
3223         for (i = 0; i < MAX_PIPES; i++) {
3224                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
3225                                 == stream) {
3226                         /* dmcu -1 for all controller id values,
3227                          * therefore +1 here
3228                          */
3229                         psr_context->controllerId =
3230                                 dc->current_state->res_ctx.
3231                                 pipe_ctx[i].stream_res.tg->inst + 1;
3232                         break;
3233                 }
3234         }
3235
3236         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
3237         psr_context->phyType = PHY_TYPE_UNIPHY;
3238         /*PhyId is associated with the transmitter id*/
3239         psr_context->smuPhyId =
3240                 transmitter_to_phy_id(link->link_enc->transmitter);
3241
3242         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
3243         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
3244                                         timing.pix_clk_100hz * 100),
3245                                         stream->timing.v_total),
3246                                         stream->timing.h_total);
3247
3248         psr_context->psrSupportedDisplayConfig = true;
3249         psr_context->psrExitLinkTrainingRequired =
3250                 psr_config->psr_exit_link_training_required;
3251         psr_context->sdpTransmitLineNumDeadline =
3252                 psr_config->psr_sdp_transmit_line_num_deadline;
3253         psr_context->psrFrameCaptureIndicationReq =
3254                 psr_config->psr_frame_capture_indication_req;
3255
3256         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
3257
3258         psr_context->numberOfControllers =
3259                         link->dc->res_pool->timing_generator_count;
3260
3261         psr_context->rfb_update_auto_en = true;
3262
3263         /* 2 frames before enter PSR. */
3264         psr_context->timehyst_frames = 2;
3265         /* half a frame
3266          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
3267          */
3268         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
3269         psr_context->aux_repeats = 10;
3270
3271         psr_context->psr_level.u32all = 0;
3272
3273         /*skip power down the single pipe since it blocks the cstate*/
3274 #if defined(CONFIG_DRM_AMD_DC_DCN)
3275         if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
3276                 switch(link->ctx->asic_id.chip_family) {
3277                 case FAMILY_YELLOW_CARP:
3278                 case AMDGPU_FAMILY_GC_10_3_6:
3279                         if(!dc->debug.disable_z10)
3280                                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
3281                         break;
3282                 default:
3283                         psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3284                         break;
3285                 }
3286         }
3287 #else
3288         if (link->ctx->asic_id.chip_family >= FAMILY_RV)
3289                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3290 #endif
3291
3292         /* SMU will perform additional powerdown sequence.
3293          * For unsupported ASICs, set psr_level flag to skip PSR
3294          *  static screen notification to SMU.
3295          *  (Always set for DAL2, did not check ASIC)
3296          */
3297         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
3298         psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
3299
3300         /* Complete PSR entry before aborting to prevent intermittent
3301          * freezes on certain eDPs
3302          */
3303         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
3304
3305         /* Controls additional delay after remote frame capture before
3306          * continuing power down, default = 0
3307          */
3308         psr_context->frame_delay = 0;
3309
3310         if (psr)
3311                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
3312                         link, psr_context, panel_inst);
3313         else
3314                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
3315
3316         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
3317          * should not happen since firmware should be running at this point
3318          */
3319         if (link->psr_settings.psr_feature_enabled == 0)
3320                 ASSERT(0);
3321
3322         return true;
3323
3324 }
3325
3326 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
3327 {
3328         struct dc  *dc = link->ctx->dc;
3329         struct dmub_psr *psr = dc->res_pool->psr;
3330         unsigned int panel_inst;
3331
3332         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3333                 return;
3334
3335         /* PSR residency measurements only supported on DMCUB */
3336         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3337                 psr->funcs->psr_get_residency(psr, residency, panel_inst);
3338         else
3339                 *residency = 0;
3340 }
3341
3342 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
3343 {
3344         return &link->link_status;
3345 }
3346
3347 void core_link_resume(struct dc_link *link)
3348 {
3349         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
3350                 program_hpd_filter(link);
3351 }
3352
3353 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
3354 {
3355         struct fixed31_32 mbytes_per_sec;
3356         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
3357                         &stream->link->cur_link_settings);
3358         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
3359
3360         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
3361
3362         return dc_fixpt_div_int(mbytes_per_sec, 54);
3363 }
3364
3365 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
3366 {
3367         struct fixed31_32 peak_kbps;
3368         uint32_t numerator = 0;
3369         uint32_t denominator = 1;
3370
3371         /*
3372          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
3373          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
3374          * common multiplier to render an integer PBN for all link rate/lane
3375          * counts combinations
3376          * calculate
3377          * peak_kbps *= (1006/1000)
3378          * peak_kbps *= (64/54)
3379          * peak_kbps *= 8    convert to bytes
3380          */
3381
3382         numerator = 64 * PEAK_FACTOR_X1000;
3383         denominator = 54 * 8 * 1000 * 1000;
3384         kbps *= numerator;
3385         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
3386
3387         return peak_kbps;
3388 }
3389
3390 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
3391 {
3392         uint64_t kbps;
3393
3394         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
3395         return get_pbn_from_bw_in_kbps(kbps);
3396 }
3397
3398 static void update_mst_stream_alloc_table(
3399         struct dc_link *link,
3400         struct stream_encoder *stream_enc,
3401         struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc?
3402         const struct dp_mst_stream_allocation_table *proposed_table)
3403 {
3404         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
3405         struct link_mst_stream_allocation *dc_alloc;
3406
3407         int i;
3408         int j;
3409
3410         /* if DRM proposed_table has more than one new payload */
3411         ASSERT(proposed_table->stream_count -
3412                         link->mst_stream_alloc_table.stream_count < 2);
3413
3414         /* copy proposed_table to link, add stream encoder */
3415         for (i = 0; i < proposed_table->stream_count; i++) {
3416
3417                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
3418                         dc_alloc =
3419                         &link->mst_stream_alloc_table.stream_allocations[j];
3420
3421                         if (dc_alloc->vcp_id ==
3422                                 proposed_table->stream_allocations[i].vcp_id) {
3423
3424                                 work_table[i] = *dc_alloc;
3425                                 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
3426                                 break; /* exit j loop */
3427                         }
3428                 }
3429
3430                 /* new vcp_id */
3431                 if (j == link->mst_stream_alloc_table.stream_count) {
3432                         work_table[i].vcp_id =
3433                                 proposed_table->stream_allocations[i].vcp_id;
3434                         work_table[i].slot_count =
3435                                 proposed_table->stream_allocations[i].slot_count;
3436                         work_table[i].stream_enc = stream_enc;
3437                         work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc;
3438                 }
3439         }
3440
3441         /* update link->mst_stream_alloc_table with work_table */
3442         link->mst_stream_alloc_table.stream_count =
3443                         proposed_table->stream_count;
3444         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
3445                 link->mst_stream_alloc_table.stream_allocations[i] =
3446                                 work_table[i];
3447 }
3448
3449 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
3450 {
3451         const uint32_t VCP_Y_PRECISION = 1000;
3452         uint64_t vcp_x, vcp_y;
3453
3454         // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
3455         avg_time_slots_per_mtp = dc_fixpt_add(
3456                         avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));
3457
3458         vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
3459         vcp_y = dc_fixpt_floor(
3460                         dc_fixpt_mul_int(
3461                                 dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
3462                                 VCP_Y_PRECISION));
3463
3464         if (link->type == dc_connection_mst_branch)
3465                 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
3466                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3467         else
3468                 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
3469                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3470 }
3471
3472 /*
3473  * Payload allocation/deallocation for SST introduced in DP2.0
3474  */
3475 static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
3476                                                  bool allocate)
3477 {
3478         struct dc_stream_state *stream = pipe_ctx->stream;
3479         struct dc_link *link = stream->link;
3480         struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
3481         struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3482         struct link_mst_stream_allocation_table proposed_table = {0};
3483         struct fixed31_32 avg_time_slots_per_mtp;
3484         const struct dc_link_settings empty_link_settings = {0};
3485         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3486         DC_LOGGER_INIT(link->ctx->logger);
3487
3488         /* slot X.Y for SST payload deallocate */
3489         if (!allocate) {
3490                 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3491
3492                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3493
3494                 if (link_hwss->ext.set_throttled_vcp_size)
3495                         link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3496                                         avg_time_slots_per_mtp);
3497                 if (link_hwss->ext.set_hblank_min_symbol_width)
3498                         link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3499                                         &empty_link_settings,
3500                                         avg_time_slots_per_mtp);
3501         }
3502
3503         /* calculate VC payload and update branch with new payload allocation table*/
3504         if (!dpcd_write_128b_132b_sst_payload_allocation_table(
3505                         stream,
3506                         link,
3507                         &proposed_table,
3508                         allocate)) {
3509                 DC_LOG_ERROR("SST Update Payload: Failed to update "
3510                                                 "allocation table for "
3511                                                 "pipe idx: %d\n",
3512                                                 pipe_ctx->pipe_idx);
3513         }
3514
3515         proposed_table.stream_allocations[0].hpo_dp_stream_enc = hpo_dp_stream_encoder;
3516
3517         ASSERT(proposed_table.stream_count == 1);
3518
3519         //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id
3520         DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p      "
3521                 "vcp_id: %d      "
3522                 "slot_count: %d\n",
3523                 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc,
3524                 proposed_table.stream_allocations[0].vcp_id,
3525                 proposed_table.stream_allocations[0].slot_count);
3526
3527         /* program DP source TX for payload */
3528         hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3529                         hpo_dp_link_encoder,
3530                         &proposed_table);
3531
3532         /* poll for ACT handled */
3533         if (!dpcd_poll_for_allocation_change_trigger(link)) {
3534                 // Failures will result in blackscreen and errors logged
3535                 BREAK_TO_DEBUGGER();
3536         }
3537
3538         /* slot X.Y for SST payload allocate */
3539         if (allocate) {
3540                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
3541
3542                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3543
3544                 if (link_hwss->ext.set_throttled_vcp_size)
3545                         link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3546                                         avg_time_slots_per_mtp);
3547                 if (link_hwss->ext.set_hblank_min_symbol_width)
3548                         link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3549                                         &link->cur_link_settings,
3550                                         avg_time_slots_per_mtp);
3551         }
3552
3553         /* Always return DC_OK.
3554          * If part of sequence fails, log failure(s) and show blackscreen
3555          */
3556         return DC_OK;
3557 }
3558
3559 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
3560  * because stream_encoder is not exposed to dm
3561  */
3562 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3563 {
3564         struct dc_stream_state *stream = pipe_ctx->stream;
3565         struct dc_link *link = stream->link;
3566         struct link_encoder *link_encoder = NULL;
3567         struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
3568         struct dp_mst_stream_allocation_table proposed_table = {0};
3569         struct fixed31_32 avg_time_slots_per_mtp;
3570         struct fixed31_32 pbn;
3571         struct fixed31_32 pbn_per_slot;
3572         int i;
3573         enum act_return_status ret;
3574         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3575         DC_LOGGER_INIT(link->ctx->logger);
3576
3577         link_encoder = link_enc_cfg_get_link_enc(link);
3578         ASSERT(link_encoder);
3579
3580         /* enable_link_dp_mst already check link->enabled_stream_count
3581          * and stream is in link->stream[]. This is called during set mode,
3582          * stream_enc is available.
3583          */
3584
3585         /* get calculate VC payload for stream: stream_alloc */
3586         if (dm_helpers_dp_mst_write_payload_allocation_table(
3587                 stream->ctx,
3588                 stream,
3589                 &proposed_table,
3590                 true))
3591                 update_mst_stream_alloc_table(
3592                                         link,
3593                                         pipe_ctx->stream_res.stream_enc,
3594                                         pipe_ctx->stream_res.hpo_dp_stream_enc,
3595                                         &proposed_table);
3596         else
3597                 DC_LOG_WARNING("Failed to update"
3598                                 "MST allocation table for"
3599                                 "pipe idx:%d\n",
3600                                 pipe_ctx->pipe_idx);
3601
3602         DC_LOG_MST("%s  "
3603                         "stream_count: %d: \n ",
3604                         __func__,
3605                         link->mst_stream_alloc_table.stream_count);
3606
3607         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3608                 DC_LOG_MST("stream_enc[%d]: %p      "
3609                 "stream[%d].hpo_dp_stream_enc: %p      "
3610                 "stream[%d].vcp_id: %d      "
3611                 "stream[%d].slot_count: %d\n",
3612                 i,
3613                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3614                 i,
3615                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3616                 i,
3617                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3618                 i,
3619                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3620         }
3621
3622         ASSERT(proposed_table.stream_count > 0);
3623
3624         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3625                 static enum dc_status status;
3626                 uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;
3627
3628                 for (i = 0; i < link->mst_stream_alloc_table.stream_count; i++)
3629                         mst_alloc_slots += link->mst_stream_alloc_table.stream_allocations[i].slot_count;
3630
3631                 status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,
3632                         mst_alloc_slots, &prev_mst_slots_in_use);
3633                 ASSERT(status == DC_OK);
3634                 DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n",
3635                                 status, mst_alloc_slots, prev_mst_slots_in_use);
3636         }
3637
3638         /* program DP source TX for payload */
3639         switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3640         case DP_8b_10b_ENCODING:
3641                 link_encoder->funcs->update_mst_stream_allocation_table(
3642                         link_encoder,
3643                         &link->mst_stream_alloc_table);
3644                 break;
3645         case DP_128b_132b_ENCODING:
3646                 hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3647                                 hpo_dp_link_encoder,
3648                                 &link->mst_stream_alloc_table);
3649                 break;
3650         case DP_UNKNOWN_ENCODING:
3651                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3652                 return DC_ERROR_UNEXPECTED;
3653         }
3654
3655         /* send down message */
3656         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3657                         stream->ctx,
3658                         stream);
3659
3660         if (ret != ACT_LINK_LOST) {
3661                 dm_helpers_dp_mst_send_payload_allocation(
3662                                 stream->ctx,
3663                                 stream,
3664                                 true);
3665         }
3666
3667         /* slot X.Y for only current stream */
3668         pbn_per_slot = get_pbn_per_slot(stream);
3669         if (pbn_per_slot.value == 0) {
3670                 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3671                 return DC_UNSUPPORTED_VALUE;
3672         }
3673         pbn = get_pbn_from_timing(pipe_ctx);
3674         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3675
3676         dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3677
3678         if (link_hwss->ext.set_throttled_vcp_size)
3679                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3680         if (link_hwss->ext.set_hblank_min_symbol_width)
3681                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3682                                 &link->cur_link_settings,
3683                                 avg_time_slots_per_mtp);
3684
3685         return DC_OK;
3686
3687 }
3688
3689 enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3690 {
3691         struct dc_stream_state *stream = pipe_ctx->stream;
3692         struct dc_link *link = stream->link;
3693         struct fixed31_32 avg_time_slots_per_mtp;
3694         struct fixed31_32 pbn;
3695         struct fixed31_32 pbn_per_slot;
3696         struct link_encoder *link_encoder = link->link_enc;
3697         struct dp_mst_stream_allocation_table proposed_table = {0};
3698         uint8_t i;
3699         enum act_return_status ret;
3700         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3701         DC_LOGGER_INIT(link->ctx->logger);
3702
3703         /* decrease throttled vcp size */
3704         pbn_per_slot = get_pbn_per_slot(stream);
3705         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3706         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3707
3708         if (link_hwss->ext.set_throttled_vcp_size)
3709                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3710         if (link_hwss->ext.set_hblank_min_symbol_width)
3711                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3712                                 &link->cur_link_settings,
3713                                 avg_time_slots_per_mtp);
3714
3715         /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3716         dm_helpers_dp_mst_send_payload_allocation(
3717                         stream->ctx,
3718                         stream,
3719                         true);
3720
3721         /* notify immediate branch device table update */
3722         if (dm_helpers_dp_mst_write_payload_allocation_table(
3723                         stream->ctx,
3724                         stream,
3725                         &proposed_table,
3726                         true)) {
3727                 /* update mst stream allocation table software state */
3728                 update_mst_stream_alloc_table(
3729                                 link,
3730                                 pipe_ctx->stream_res.stream_enc,
3731                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3732                                 &proposed_table);
3733         } else {
3734                 DC_LOG_WARNING("Failed to update"
3735                                 "MST allocation table for"
3736                                 "pipe idx:%d\n",
3737                                 pipe_ctx->pipe_idx);
3738         }
3739
3740         DC_LOG_MST("%s  "
3741                         "stream_count: %d: \n ",
3742                         __func__,
3743                         link->mst_stream_alloc_table.stream_count);
3744
3745         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3746                 DC_LOG_MST("stream_enc[%d]: %p      "
3747                                 "stream[%d].vcp_id: %d      "
3748                                 "stream[%d].slot_count: %d\n",
3749                                 i,
3750                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3751                                 i,
3752                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3753                                 i,
3754                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3755         }
3756
3757         ASSERT(proposed_table.stream_count > 0);
3758
3759         /* update mst stream allocation table hardware state */
3760         link_encoder->funcs->update_mst_stream_allocation_table(
3761                         link_encoder,
3762                         &link->mst_stream_alloc_table);
3763
3764         /* poll for immediate branch device ACT handled */
3765         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3766                         stream->ctx,
3767                         stream);
3768
3769         return DC_OK;
3770 }
3771
3772 enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3773 {
3774         struct dc_stream_state *stream = pipe_ctx->stream;
3775         struct dc_link *link = stream->link;
3776         struct fixed31_32 avg_time_slots_per_mtp;
3777         struct fixed31_32 pbn;
3778         struct fixed31_32 pbn_per_slot;
3779         struct link_encoder *link_encoder = link->link_enc;
3780         struct dp_mst_stream_allocation_table proposed_table = {0};
3781         uint8_t i;
3782         enum act_return_status ret;
3783         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3784         DC_LOGGER_INIT(link->ctx->logger);
3785
3786         /* notify immediate branch device table update */
3787         if (dm_helpers_dp_mst_write_payload_allocation_table(
3788                                 stream->ctx,
3789                                 stream,
3790                                 &proposed_table,
3791                                 true)) {
3792                 /* update mst stream allocation table software state */
3793                 update_mst_stream_alloc_table(
3794                                 link,
3795                                 pipe_ctx->stream_res.stream_enc,
3796                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3797                                 &proposed_table);
3798         }
3799
3800         DC_LOG_MST("%s  "
3801                         "stream_count: %d: \n ",
3802                         __func__,
3803                         link->mst_stream_alloc_table.stream_count);
3804
3805         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3806                 DC_LOG_MST("stream_enc[%d]: %p      "
3807                                 "stream[%d].vcp_id: %d      "
3808                                 "stream[%d].slot_count: %d\n",
3809                                 i,
3810                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3811                                 i,
3812                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3813                                 i,
3814                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3815         }
3816
3817         ASSERT(proposed_table.stream_count > 0);
3818
3819         /* update mst stream allocation table hardware state */
3820         link_encoder->funcs->update_mst_stream_allocation_table(
3821                         link_encoder,
3822                         &link->mst_stream_alloc_table);
3823
3824         /* poll for immediate branch device ACT handled */
3825         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3826                         stream->ctx,
3827                         stream);
3828
3829         if (ret != ACT_LINK_LOST) {
3830                 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3831                 dm_helpers_dp_mst_send_payload_allocation(
3832                                 stream->ctx,
3833                                 stream,
3834                                 true);
3835         }
3836
3837         /* increase throttled vcp size */
3838         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3839         pbn_per_slot = get_pbn_per_slot(stream);
3840         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3841
3842         if (link_hwss->ext.set_throttled_vcp_size)
3843                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3844         if (link_hwss->ext.set_hblank_min_symbol_width)
3845                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3846                                 &link->cur_link_settings,
3847                                 avg_time_slots_per_mtp);
3848
3849         return DC_OK;
3850 }
3851
3852 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3853 {
3854         struct dc_stream_state *stream = pipe_ctx->stream;
3855         struct dc_link *link = stream->link;
3856         struct link_encoder *link_encoder = NULL;
3857         struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
3858         struct dp_mst_stream_allocation_table proposed_table = {0};
3859         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3860         int i;
3861         bool mst_mode = (link->type == dc_connection_mst_branch);
3862         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3863         const struct dc_link_settings empty_link_settings = {0};
3864         DC_LOGGER_INIT(link->ctx->logger);
3865
3866         link_encoder = link_enc_cfg_get_link_enc(link);
3867         ASSERT(link_encoder);
3868
3869         /* deallocate_mst_payload is called before disable link. When mode or
3870          * disable/enable monitor, new stream is created which is not in link
3871          * stream[] yet. For this, payload is not allocated yet, so de-alloc
3872          * should not done. For new mode set, map_resources will get engine
3873          * for new stream, so stream_enc->id should be validated until here.
3874          */
3875
3876         /* slot X.Y */
3877         if (link_hwss->ext.set_throttled_vcp_size)
3878                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3879         if (link_hwss->ext.set_hblank_min_symbol_width)
3880                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3881                                 &empty_link_settings,
3882                                 avg_time_slots_per_mtp);
3883
3884         /* TODO: which component is responsible for remove payload table? */
3885         if (mst_mode) {
3886                 if (dm_helpers_dp_mst_write_payload_allocation_table(
3887                                 stream->ctx,
3888                                 stream,
3889                                 &proposed_table,
3890                                 false)) {
3891
3892                         update_mst_stream_alloc_table(
3893                                                 link,
3894                                                 pipe_ctx->stream_res.stream_enc,
3895                                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3896                                                 &proposed_table);
3897                 }
3898                 else {
3899                                 DC_LOG_WARNING("Failed to update"
3900                                                 "MST allocation table for"
3901                                                 "pipe idx:%d\n",
3902                                                 pipe_ctx->pipe_idx);
3903                 }
3904         }
3905
3906         DC_LOG_MST("%s"
3907                         "stream_count: %d: ",
3908                         __func__,
3909                         link->mst_stream_alloc_table.stream_count);
3910
3911         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3912                 DC_LOG_MST("stream_enc[%d]: %p      "
3913                 "stream[%d].hpo_dp_stream_enc: %p      "
3914                 "stream[%d].vcp_id: %d      "
3915                 "stream[%d].slot_count: %d\n",
3916                 i,
3917                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3918                 i,
3919                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3920                 i,
3921                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3922                 i,
3923                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3924         }
3925
3926         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3927                 enum dc_status status;
3928                 uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;
3929
3930                 for (i = 0; i < link->mst_stream_alloc_table.stream_count; i++)
3931                         mst_alloc_slots += link->mst_stream_alloc_table.stream_allocations[i].slot_count;
3932
3933                 status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,
3934                         mst_alloc_slots, &prev_mst_slots_in_use);
3935                 ASSERT(status != DC_NOT_SUPPORTED);
3936                 DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n",
3937                                 status, mst_alloc_slots, prev_mst_slots_in_use);
3938         }
3939
3940         switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3941         case DP_8b_10b_ENCODING:
3942                 link_encoder->funcs->update_mst_stream_allocation_table(
3943                         link_encoder,
3944                         &link->mst_stream_alloc_table);
3945                 break;
3946         case DP_128b_132b_ENCODING:
3947                 hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3948                                 hpo_dp_link_encoder,
3949                                 &link->mst_stream_alloc_table);
3950                 break;
3951         case DP_UNKNOWN_ENCODING:
3952                 DC_LOG_DEBUG("Unknown encoding format\n");
3953                 return DC_ERROR_UNEXPECTED;
3954         }
3955
3956         if (mst_mode) {
3957                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3958                         stream->ctx,
3959                         stream);
3960
3961                 dm_helpers_dp_mst_send_payload_allocation(
3962                         stream->ctx,
3963                         stream,
3964                         false);
3965         }
3966
3967         return DC_OK;
3968 }
3969
3970
3971 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3972 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3973 {
3974         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3975         struct link_encoder *link_enc = NULL;
3976         struct cp_psp_stream_config config = {0};
3977         enum dp_panel_mode panel_mode =
3978                         dp_get_panel_mode(pipe_ctx->stream->link);
3979
3980         if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL)
3981                 return;
3982
3983         link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
3984         ASSERT(link_enc);
3985         if (link_enc == NULL)
3986                 return;
3987
3988         /* otg instance */
3989         config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3990
3991         /* dig front end */
3992         config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3993
3994         /* stream encoder index */
3995         config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
3996         if (is_dp_128b_132b_signal(pipe_ctx))
3997                 config.stream_enc_idx =
3998                                 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
3999
4000         /* dig back end */
4001         config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
4002
4003         /* link encoder index */
4004         config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4005         if (is_dp_128b_132b_signal(pipe_ctx))
4006                 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;
4007
4008         /* dio output index */
4009         config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4010
4011         /* phy index */
4012         config.phy_idx = resource_transmitter_to_phy_idx(
4013                         pipe_ctx->stream->link->dc, link_enc->transmitter);
4014         if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
4015                 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */
4016                 config.phy_idx = 0;
4017
4018         /* stream properties */
4019         config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0;
4020         config.mst_enabled = (pipe_ctx->stream->signal ==
4021                         SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0;
4022         config.dp2_enabled = is_dp_128b_132b_signal(pipe_ctx) ? 1 : 0;
4023         config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ?
4024                         1 : 0;
4025         config.dpms_off = dpms_off;
4026
4027         /* dm stream context */
4028         config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
4029
4030         cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
4031 }
4032 #endif
4033
4034 static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx)
4035 {
4036         struct dc *dc = pipe_ctx->stream->ctx->dc;
4037         struct dc_stream_state *stream = pipe_ctx->stream;
4038         struct link_mst_stream_allocation_table proposed_table = {0};
4039         struct fixed31_32 avg_time_slots_per_mtp;
4040         uint8_t req_slot_count = 0;
4041         uint8_t vc_id = 1; /// VC ID always 1 for SST
4042         struct dc_link_settings link_settings = {0};
4043         const struct link_hwss *link_hwss = get_link_hwss(stream->link, &pipe_ctx->link_res);
4044         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4045
4046         decide_link_settings(stream, &link_settings);
4047         stream->link->cur_link_settings = link_settings;
4048
4049         if (link_hwss->ext.enable_dp_link_output)
4050                 link_hwss->ext.enable_dp_link_output(stream->link, &pipe_ctx->link_res,
4051                                 stream->signal, pipe_ctx->clock_source->id,
4052                                 &link_settings);
4053
4054 #ifdef DIAGS_BUILD
4055         /* Workaround for FPGA HPO capture DP link data:
4056          * HPO capture will set link to active mode
4057          * This workaround is required to get a capture from start of frame
4058          */
4059         if (!dc->debug.fpga_hpo_capture_en) {
4060                 struct encoder_set_dp_phy_pattern_param params = {0};
4061                 params.dp_phy_pattern = DP_TEST_PATTERN_VIDEO_MODE;
4062
4063                 /* Set link active */
4064                 stream->link->hpo_dp_link_enc->funcs->set_link_test_pattern(
4065                                 stream->link->hpo_dp_link_enc,
4066                                 &params);
4067         }
4068 #endif
4069
4070         /* Enable DP_STREAM_ENC */
4071         dc->hwss.enable_stream(pipe_ctx);
4072
4073         /* Set DPS PPS SDP (AKA "info frames") */
4074         if (pipe_ctx->stream->timing.flags.DSC) {
4075                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4076         }
4077
4078         /* Allocate Payload */
4079         if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) {
4080                 // MST case
4081                 uint8_t i;
4082
4083                 proposed_table.stream_count = state->stream_count;
4084                 for (i = 0; i < state->stream_count; i++) {
4085                         avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link);
4086                         req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4087                         proposed_table.stream_allocations[i].slot_count = req_slot_count;
4088                         proposed_table.stream_allocations[i].vcp_id = i+1;
4089                         /* NOTE: This makes assumption that pipe_ctx index is same as stream index */
4090                         proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc;
4091                 }
4092         } else {
4093                 // SST case
4094                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, stream->link);
4095                 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4096                 proposed_table.stream_count = 1; /// Always 1 stream for SST
4097                 proposed_table.stream_allocations[0].slot_count = req_slot_count;
4098                 proposed_table.stream_allocations[0].vcp_id = vc_id;
4099                 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
4100         }
4101
4102         pipe_ctx->link_res.hpo_dp_link_enc->funcs->update_stream_allocation_table(
4103                         pipe_ctx->link_res.hpo_dp_link_enc,
4104                         &proposed_table);
4105
4106         if (link_hwss->ext.set_throttled_vcp_size)
4107                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
4108
4109         dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings);
4110 }
4111
4112 void core_link_enable_stream(
4113                 struct dc_state *state,
4114                 struct pipe_ctx *pipe_ctx)
4115 {
4116         struct dc *dc = pipe_ctx->stream->ctx->dc;
4117         struct dc_stream_state *stream = pipe_ctx->stream;
4118         struct dc_link *link = stream->sink->link;
4119         enum dc_status status;
4120         struct link_encoder *link_enc;
4121         enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
4122         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4123
4124         if (is_dp_128b_132b_signal(pipe_ctx))
4125                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4126
4127         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4128
4129         if (pipe_ctx->stream->sink) {
4130                 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4131                         pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4132                         DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4133                         pipe_ctx->stream->sink->edid_caps.display_name,
4134                         pipe_ctx->stream->signal);
4135                 }
4136         }
4137
4138         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4139                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4140                 return;
4141
4142         link_enc = link_enc_cfg_get_link_enc(link);
4143         ASSERT(link_enc);
4144
4145         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)
4146                         && !is_dp_128b_132b_signal(pipe_ctx)) {
4147                 if (link_enc)
4148                         link_enc->funcs->setup(
4149                                 link_enc,
4150                                 pipe_ctx->stream->signal);
4151                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
4152                         pipe_ctx->stream_res.stream_enc,
4153                         pipe_ctx->stream_res.tg->inst,
4154                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
4155         }
4156
4157         if (is_dp_128b_132b_signal(pipe_ctx)) {
4158                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->set_stream_attribute(
4159                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
4160                                 &stream->timing,
4161                                 stream->output_color_space,
4162                                 stream->use_vsc_sdp_for_colorimetry,
4163                                 stream->timing.flags.DSC,
4164                                 false);
4165                 otg_out_dest = OUT_MUX_HPO_DP;
4166         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
4167                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
4168                                 pipe_ctx->stream_res.stream_enc,
4169                                 &stream->timing,
4170                                 stream->output_color_space,
4171                                 stream->use_vsc_sdp_for_colorimetry,
4172                                 stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4173         }
4174
4175         if (dc_is_dp_signal(pipe_ctx->stream->signal))
4176                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR);
4177
4178         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
4179                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
4180                         pipe_ctx->stream_res.stream_enc,
4181                         &stream->timing,
4182                         stream->phy_pix_clk,
4183                         pipe_ctx->stream_res.audio != NULL);
4184
4185         pipe_ctx->stream->link->link_state_valid = true;
4186
4187         if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4188                 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
4189
4190         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
4191                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
4192                         pipe_ctx->stream_res.stream_enc,
4193                         &stream->timing,
4194                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
4195                         true : false);
4196
4197         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
4198                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
4199                         pipe_ctx->stream_res.stream_enc,
4200                         &stream->timing);
4201
4202         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
4203                 bool apply_edp_fast_boot_optimization =
4204                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
4205
4206                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
4207
4208                 // Enable VPG before building infoframe
4209                 if (vpg && vpg->funcs->vpg_poweron)
4210                         vpg->funcs->vpg_poweron(vpg);
4211
4212                 resource_build_info_frame(pipe_ctx);
4213                 dc->hwss.update_info_frame(pipe_ctx);
4214
4215                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4216                         dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
4217
4218                 /* Do not touch link on seamless boot optimization. */
4219                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
4220                         pipe_ctx->stream->dpms_off = false;
4221
4222                         /* Still enable stream features & audio on seamless boot for DP external displays */
4223                         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
4224                                 enable_stream_features(pipe_ctx);
4225                                 if (pipe_ctx->stream_res.audio != NULL) {
4226                                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
4227                                         dc->hwss.enable_audio_stream(pipe_ctx);
4228                                 }
4229                         }
4230
4231 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4232                         update_psp_stream_config(pipe_ctx, false);
4233 #endif
4234                         return;
4235                 }
4236
4237                 /* eDP lit up by bios already, no need to enable again. */
4238                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
4239                                         apply_edp_fast_boot_optimization &&
4240                                         !pipe_ctx->stream->timing.flags.DSC &&
4241                                         !pipe_ctx->next_odm_pipe) {
4242                         pipe_ctx->stream->dpms_off = false;
4243 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4244                         update_psp_stream_config(pipe_ctx, false);
4245 #endif
4246                         return;
4247                 }
4248
4249                 if (pipe_ctx->stream->dpms_off)
4250                         return;
4251
4252                 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
4253                  * link training). This is to make sure the bandwidth sent to DIG BE won't be
4254                  * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
4255                  * will be automatically set at a later time when the video is enabled
4256                  * (DP_VID_STREAM_EN = 1).
4257                  */
4258                 if (pipe_ctx->stream->timing.flags.DSC) {
4259                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4260                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4261                                 dp_set_dsc_enable(pipe_ctx, true);
4262                 }
4263
4264                 status = enable_link(state, pipe_ctx);
4265
4266                 if (status != DC_OK) {
4267                         DC_LOG_WARNING("enabling link %u failed: %d\n",
4268                         pipe_ctx->stream->link->link_index,
4269                         status);
4270
4271                         /* Abort stream enable *unless* the failure was due to
4272                          * DP link training - some DP monitors will recover and
4273                          * show the stream anyway. But MST displays can't proceed
4274                          * without link training.
4275                          */
4276                         if (status != DC_FAIL_DP_LINK_TRAINING ||
4277                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
4278                                 if (false == stream->link->link_status.link_active)
4279                                         disable_link(stream->link, &pipe_ctx->link_res,
4280                                                         pipe_ctx->stream->signal);
4281                                 BREAK_TO_DEBUGGER();
4282                                 return;
4283                         }
4284                 }
4285
4286                 /* turn off otg test pattern if enable */
4287                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4288                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4289                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4290                                         COLOR_DEPTH_UNDEFINED);
4291
4292                 /* This second call is needed to reconfigure the DIG
4293                  * as a workaround for the incorrect value being applied
4294                  * from transmitter control.
4295                  */
4296                 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
4297                                 is_dp_128b_132b_signal(pipe_ctx)))
4298                         if (link_enc)
4299                                 link_enc->funcs->setup(
4300                                         link_enc,
4301                                         pipe_ctx->stream->signal);
4302
4303                 dc->hwss.enable_stream(pipe_ctx);
4304
4305                 /* Set DPS PPS SDP (AKA "info frames") */
4306                 if (pipe_ctx->stream->timing.flags.DSC) {
4307                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4308                                         dc_is_virtual_signal(pipe_ctx->stream->signal)) {
4309                                 dp_set_dsc_on_rx(pipe_ctx, true);
4310                                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4311                         }
4312                 }
4313
4314                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4315                         dc_link_allocate_mst_payload(pipe_ctx);
4316                 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4317                                 is_dp_128b_132b_signal(pipe_ctx))
4318                         dc_link_update_sst_payload(pipe_ctx, true);
4319
4320                 dc->hwss.unblank_stream(pipe_ctx,
4321                         &pipe_ctx->stream->link->cur_link_settings);
4322
4323                 if (stream->sink_patches.delay_ignore_msa > 0)
4324                         msleep(stream->sink_patches.delay_ignore_msa);
4325
4326                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4327                         enable_stream_features(pipe_ctx);
4328 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4329                 update_psp_stream_config(pipe_ctx, false);
4330 #endif
4331
4332                 dc->hwss.enable_audio_stream(pipe_ctx);
4333
4334         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
4335                 if (is_dp_128b_132b_signal(pipe_ctx)) {
4336                         fpga_dp_hpo_enable_link_and_stream(state, pipe_ctx);
4337                 }
4338                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4339                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
4340                         dp_set_dsc_enable(pipe_ctx, true);
4341
4342         }
4343
4344         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
4345                 core_link_set_avmute(pipe_ctx, false);
4346         }
4347 }
4348
4349 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
4350 {
4351         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4352         struct dc_stream_state *stream = pipe_ctx->stream;
4353         struct dc_link *link = stream->sink->link;
4354         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4355
4356         if (is_dp_128b_132b_signal(pipe_ctx))
4357                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4358
4359         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4360
4361         if (pipe_ctx->stream->sink) {
4362                 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4363                         pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4364                         DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4365                         pipe_ctx->stream->sink->edid_caps.display_name,
4366                         pipe_ctx->stream->signal);
4367                 }
4368         }
4369
4370         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4371                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4372                 return;
4373
4374         if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
4375                 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
4376                         core_link_set_avmute(pipe_ctx, true);
4377         }
4378
4379         dc->hwss.disable_audio_stream(pipe_ctx);
4380
4381 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4382         update_psp_stream_config(pipe_ctx, true);
4383 #endif
4384         dc->hwss.blank_stream(pipe_ctx);
4385
4386         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4387                 deallocate_mst_payload(pipe_ctx);
4388         else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4389                         is_dp_128b_132b_signal(pipe_ctx))
4390                 dc_link_update_sst_payload(pipe_ctx, false);
4391
4392         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4393                 struct ext_hdmi_settings settings = {0};
4394                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
4395
4396                 unsigned short masked_chip_caps = link->chip_caps &
4397                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
4398                 //Need to inform that sink is going to use legacy HDMI mode.
4399                 dal_ddc_service_write_scdc_data(
4400                         link->ddc,
4401                         165000,//vbios only handles 165Mhz.
4402                         false);
4403                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
4404                         /* DP159, Retimer settings */
4405                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
4406                                 write_i2c_retimer_setting(pipe_ctx,
4407                                                 false, false, &settings);
4408                         else
4409                                 write_i2c_default_retimer_setting(pipe_ctx,
4410                                                 false, false);
4411                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
4412                         /* PI3EQX1204, Redriver settings */
4413                         write_i2c_redriver_setting(pipe_ctx, false);
4414                 }
4415         }
4416
4417         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4418                         !is_dp_128b_132b_signal(pipe_ctx)) {
4419
4420                 /* In DP1.x SST mode, our encoder will go to TPS1
4421                  * when link is on but stream is off.
4422                  * Disabling link before stream will avoid exposing TPS1 pattern
4423                  * during the disable sequence as it will confuse some receivers
4424                  * state machine.
4425                  * In DP2 or MST mode, our encoder will stay video active
4426                  */
4427                 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4428                 dc->hwss.disable_stream(pipe_ctx);
4429         } else {
4430                 dc->hwss.disable_stream(pipe_ctx);
4431                 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4432         }
4433
4434         if (pipe_ctx->stream->timing.flags.DSC) {
4435                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4436                         dp_set_dsc_enable(pipe_ctx, false);
4437         }
4438         if (is_dp_128b_132b_signal(pipe_ctx)) {
4439                 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4440                         pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
4441         }
4442
4443         if (vpg && vpg->funcs->vpg_powerdown)
4444                 vpg->funcs->vpg_powerdown(vpg);
4445 }
4446
4447 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
4448 {
4449         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4450
4451         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
4452                 return;
4453
4454         dc->hwss.set_avmute(pipe_ctx, enable);
4455 }
4456
4457 /**
4458  *  dc_link_enable_hpd_filter:
4459  *     If enable is true, programs HPD filter on associated HPD line using
4460  *     delay_on_disconnect/delay_on_connect values dependent on
4461  *     link->connector_signal
4462  *
4463  *     If enable is false, programs HPD filter on associated HPD line with no
4464  *     delays on connect or disconnect
4465  *
4466  *  @link:   pointer to the dc link
4467  *  @enable: boolean specifying whether to enable hbd
4468  */
4469 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
4470 {
4471         struct gpio *hpd;
4472
4473         if (enable) {
4474                 link->is_hpd_filter_disabled = false;
4475                 program_hpd_filter(link);
4476         } else {
4477                 link->is_hpd_filter_disabled = true;
4478                 /* Obtain HPD handle */
4479                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4480
4481                 if (!hpd)
4482                         return;
4483
4484                 /* Setup HPD filtering */
4485                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
4486                         struct gpio_hpd_config config;
4487
4488                         config.delay_on_connect = 0;
4489                         config.delay_on_disconnect = 0;
4490
4491                         dal_irq_setup_hpd_filter(hpd, &config);
4492
4493                         dal_gpio_close(hpd);
4494                 } else {
4495                         ASSERT_CRITICAL(false);
4496                 }
4497                 /* Release HPD handle */
4498                 dal_gpio_destroy_irq(&hpd);
4499         }
4500 }
4501
4502 void dc_link_set_drive_settings(struct dc *dc,
4503                                 struct link_training_settings *lt_settings,
4504                                 const struct dc_link *link)
4505 {
4506
4507         int i;
4508         struct link_resource link_res;
4509
4510         for (i = 0; i < dc->link_count; i++)
4511                 if (dc->links[i] == link)
4512                         break;
4513
4514         if (i >= dc->link_count)
4515                 ASSERT_CRITICAL(false);
4516
4517         dc_link_get_cur_link_res(link, &link_res);
4518         dc_link_dp_set_drive_settings(dc->links[i], &link_res, lt_settings);
4519 }
4520
4521 void dc_link_set_preferred_link_settings(struct dc *dc,
4522                                          struct dc_link_settings *link_setting,
4523                                          struct dc_link *link)
4524 {
4525         int i;
4526         struct pipe_ctx *pipe;
4527         struct dc_stream_state *link_stream;
4528         struct dc_link_settings store_settings = *link_setting;
4529
4530         link->preferred_link_setting = store_settings;
4531
4532         /* Retrain with preferred link settings only relevant for
4533          * DP signal type
4534          * Check for non-DP signal or if passive dongle present
4535          */
4536         if (!dc_is_dp_signal(link->connector_signal) ||
4537                 link->dongle_max_pix_clk > 0)
4538                 return;
4539
4540         for (i = 0; i < MAX_PIPES; i++) {
4541                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4542                 if (pipe->stream && pipe->stream->link) {
4543                         if (pipe->stream->link == link) {
4544                                 link_stream = pipe->stream;
4545                                 break;
4546                         }
4547                 }
4548         }
4549
4550         /* Stream not found */
4551         if (i == MAX_PIPES)
4552                 return;
4553
4554         /* Cannot retrain link if backend is off */
4555         if (link_stream->dpms_off)
4556                 return;
4557
4558         decide_link_settings(link_stream, &store_settings);
4559
4560         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
4561                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
4562                 dp_retrain_link_dp_test(link, &store_settings, false);
4563 }
4564
4565 void dc_link_set_preferred_training_settings(struct dc *dc,
4566                                                  struct dc_link_settings *link_setting,
4567                                                  struct dc_link_training_overrides *lt_overrides,
4568                                                  struct dc_link *link,
4569                                                  bool skip_immediate_retrain)
4570 {
4571         if (lt_overrides != NULL)
4572                 link->preferred_training_settings = *lt_overrides;
4573         else
4574                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
4575
4576         if (link_setting != NULL) {
4577                 link->preferred_link_setting = *link_setting;
4578                 if (dp_get_link_encoding_format(link_setting) == DP_128b_132b_ENCODING)
4579                         /* TODO: add dc update for acquiring link res  */
4580                         skip_immediate_retrain = true;
4581         } else {
4582                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
4583                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
4584         }
4585
4586         /* Retrain now, or wait until next stream update to apply */
4587         if (skip_immediate_retrain == false)
4588                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
4589 }
4590
4591 void dc_link_enable_hpd(const struct dc_link *link)
4592 {
4593         dc_link_dp_enable_hpd(link);
4594 }
4595
4596 void dc_link_disable_hpd(const struct dc_link *link)
4597 {
4598         dc_link_dp_disable_hpd(link);
4599 }
4600
4601 void dc_link_set_test_pattern(struct dc_link *link,
4602                               enum dp_test_pattern test_pattern,
4603                               enum dp_test_pattern_color_space test_pattern_color_space,
4604                               const struct link_training_settings *p_link_settings,
4605                               const unsigned char *p_custom_pattern,
4606                               unsigned int cust_pattern_size)
4607 {
4608         if (link != NULL)
4609                 dc_link_dp_set_test_pattern(
4610                         link,
4611                         test_pattern,
4612                         test_pattern_color_space,
4613                         p_link_settings,
4614                         p_custom_pattern,
4615                         cust_pattern_size);
4616 }
4617
4618 uint32_t dc_link_bandwidth_kbps(
4619         const struct dc_link *link,
4620         const struct dc_link_settings *link_setting)
4621 {
4622         uint32_t total_data_bw_efficiency_x10000 = 0;
4623         uint32_t link_rate_per_lane_kbps = 0;
4624
4625         switch (dp_get_link_encoding_format(link_setting)) {
4626         case DP_8b_10b_ENCODING:
4627                 /* For 8b/10b encoding:
4628                  * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
4629                  * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
4630                  */
4631                 link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
4632                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
4633                 if (dc_link_should_enable_fec(link)) {
4634                         total_data_bw_efficiency_x10000 /= 100;
4635                         total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
4636                 }
4637                 break;
4638         case DP_128b_132b_ENCODING:
4639                 /* For 128b/132b encoding:
4640                  * link rate is defined in the unit of 10mbps per lane.
4641                  * total data bandwidth efficiency is always 96.71%.
4642                  */
4643                 link_rate_per_lane_kbps = link_setting->link_rate * 10000;
4644                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
4645                 break;
4646         default:
4647                 break;
4648         }
4649
4650         /* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
4651         return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
4652 }
4653
4654 const struct dc_link_settings *dc_link_get_link_cap(
4655                 const struct dc_link *link)
4656 {
4657         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
4658                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
4659                 return &link->preferred_link_setting;
4660         return &link->verified_link_cap;
4661 }
4662
4663 void dc_link_overwrite_extended_receiver_cap(
4664                 struct dc_link *link)
4665 {
4666         dp_overwrite_extended_receiver_cap(link);
4667 }
4668
4669 bool dc_link_is_fec_supported(const struct dc_link *link)
4670 {
4671         /* TODO - use asic cap instead of link_enc->features
4672          * we no longer know which link enc to use for this link before commit
4673          */
4674         struct link_encoder *link_enc = NULL;
4675
4676         link_enc = link_enc_cfg_get_link_enc(link);
4677         ASSERT(link_enc);
4678
4679         return (dc_is_dp_signal(link->connector_signal) && link_enc &&
4680                         link_enc->features.fec_supported &&
4681                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
4682                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
4683 }
4684
4685 bool dc_link_should_enable_fec(const struct dc_link *link)
4686 {
4687         bool is_fec_disable = false;
4688         bool ret = false;
4689
4690         if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
4691                         link->local_sink &&
4692                         link->local_sink->edid_caps.panel_patch.disable_fec) ||
4693                         (link->connector_signal == SIGNAL_TYPE_EDP
4694                                 // enable FEC for EDP if DSC is supported
4695                                 && link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT == false
4696                                 ))
4697                 is_fec_disable = true;
4698
4699         if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
4700                 ret = true;
4701
4702         return ret;
4703 }
4704
4705 uint32_t dc_bandwidth_in_kbps_from_timing(
4706                 const struct dc_crtc_timing *timing)
4707 {
4708         uint32_t bits_per_channel = 0;
4709         uint32_t kbps;
4710
4711 #if defined(CONFIG_DRM_AMD_DC_DCN)
4712         if (timing->flags.DSC)
4713                 return dc_dsc_stream_bandwidth_in_kbps(timing,
4714                                 timing->dsc_cfg.bits_per_pixel,
4715                                 timing->dsc_cfg.num_slices_h,
4716                                 timing->dsc_cfg.is_dp);
4717 #endif /* CONFIG_DRM_AMD_DC_DCN */
4718
4719         switch (timing->display_color_depth) {
4720         case COLOR_DEPTH_666:
4721                 bits_per_channel = 6;
4722                 break;
4723         case COLOR_DEPTH_888:
4724                 bits_per_channel = 8;
4725                 break;
4726         case COLOR_DEPTH_101010:
4727                 bits_per_channel = 10;
4728                 break;
4729         case COLOR_DEPTH_121212:
4730                 bits_per_channel = 12;
4731                 break;
4732         case COLOR_DEPTH_141414:
4733                 bits_per_channel = 14;
4734                 break;
4735         case COLOR_DEPTH_161616:
4736                 bits_per_channel = 16;
4737                 break;
4738         default:
4739                 ASSERT(bits_per_channel != 0);
4740                 bits_per_channel = 8;
4741                 break;
4742         }
4743
4744         kbps = timing->pix_clk_100hz / 10;
4745         kbps *= bits_per_channel;
4746
4747         if (timing->flags.Y_ONLY != 1) {
4748                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
4749                 kbps *= 3;
4750                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
4751                         kbps /= 2;
4752                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
4753                         kbps = kbps * 2 / 3;
4754         }
4755
4756         return kbps;
4757
4758 }
4759
4760 void dc_link_get_cur_link_res(const struct dc_link *link,
4761                 struct link_resource *link_res)
4762 {
4763         int i;
4764         struct pipe_ctx *pipe = NULL;
4765
4766         memset(link_res, 0, sizeof(*link_res));
4767
4768         for (i = 0; i < MAX_PIPES; i++) {
4769                 pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];
4770                 if (pipe->stream && pipe->stream->link && pipe->top_pipe == NULL) {
4771                         if (pipe->stream->link == link) {
4772                                 *link_res = pipe->link_res;
4773                                 break;
4774                         }
4775                 }
4776         }
4777
4778 }
4779
4780 /**
4781  * dc_get_cur_link_res_map() - take a snapshot of current link resource allocation state
4782  * @dc: pointer to dc of the dm calling this
4783  * @map: a dc link resource snapshot defined internally to dc.
4784  *
4785  * DM needs to capture a snapshot of current link resource allocation mapping
4786  * and store it in its persistent storage.
4787  *
4788  * Some of the link resource is using first come first serve policy.
4789  * The allocation mapping depends on original hotplug order. This information
4790  * is lost after driver is loaded next time. The snapshot is used in order to
4791  * restore link resource to its previous state so user will get consistent
4792  * link capability allocation across reboot.
4793  *
4794  * Return: none (void function)
4795  *
4796  */
4797 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)
4798 {
4799         struct dc_link *link;
4800         uint32_t i;
4801         uint32_t hpo_dp_recycle_map = 0;
4802
4803         *map = 0;
4804
4805         if (dc->caps.dp_hpo) {
4806                 for (i = 0; i < dc->caps.max_links; i++) {
4807                         link = dc->links[i];
4808                         if (link->link_status.link_active &&
4809                                         dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING &&
4810                                         dp_get_link_encoding_format(&link->cur_link_settings) != DP_128b_132b_ENCODING)
4811                                 /* hpo dp link encoder is considered as recycled, when RX reports 128b/132b encoding capability
4812                                  * but current link doesn't use it.
4813                                  */
4814                                 hpo_dp_recycle_map |= (1 << i);
4815                 }
4816                 *map |= (hpo_dp_recycle_map << LINK_RES_HPO_DP_REC_MAP__SHIFT);
4817         }
4818 }
4819
4820 /**
4821  * dc_restore_link_res_map() - restore link resource allocation state from a snapshot
4822  * @dc: pointer to dc of the dm calling this
4823  * @map: a dc link resource snapshot defined internally to dc.
4824  *
4825  * DM needs to call this function after initial link detection on boot and
4826  * before first commit streams to restore link resource allocation state
4827  * from previous boot session.
4828  *
4829  * Some of the link resource is using first come first serve policy.
4830  * The allocation mapping depends on original hotplug order. This information
4831  * is lost after driver is loaded next time. The snapshot is used in order to
4832  * restore link resource to its previous state so user will get consistent
4833  * link capability allocation across reboot.
4834  *
4835  * Return: none (void function)
4836  *
4837  */
4838 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)
4839 {
4840         struct dc_link *link;
4841         uint32_t i;
4842         unsigned int available_hpo_dp_count;
4843         uint32_t hpo_dp_recycle_map = (*map & LINK_RES_HPO_DP_REC_MAP__MASK)
4844                         >> LINK_RES_HPO_DP_REC_MAP__SHIFT;
4845
4846         if (dc->caps.dp_hpo) {
4847                 available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count;
4848                 /* remove excess 128b/132b encoding support for not recycled links */
4849                 for (i = 0; i < dc->caps.max_links; i++) {
4850                         if ((hpo_dp_recycle_map & (1 << i)) == 0) {
4851                                 link = dc->links[i];
4852                                 if (link->type != dc_connection_none &&
4853                                                 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4854                                         if (available_hpo_dp_count > 0)
4855                                                 available_hpo_dp_count--;
4856                                         else
4857                                                 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4858                                                 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4859                                 }
4860                         }
4861                 }
4862                 /* remove excess 128b/132b encoding support for recycled links */
4863                 for (i = 0; i < dc->caps.max_links; i++) {
4864                         if ((hpo_dp_recycle_map & (1 << i)) != 0) {
4865                                 link = dc->links[i];
4866                                 if (link->type != dc_connection_none &&
4867                                                 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4868                                         if (available_hpo_dp_count > 0)
4869                                                 available_hpo_dp_count--;
4870                                         else
4871                                                 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4872                                                 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4873                                 }
4874                         }
4875                 }
4876         }
4877 }