drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "atom.h"
  28 #include "dm_helpers.h"
  29 #include "dc.h"
  30 #include "grph_object_id.h"
  31 #include "gpio_service_interface.h"
  32 #include "core_status.h"
  33 #include "dc_link_dp.h"
  34 #include "dc_link_ddc.h"
  35 #include "link_hwss.h"
  36 #include "opp.h"
  37
  38 #include "link_encoder.h"
  39 #include "hw_sequencer.h"
  40 #include "resource.h"
  41 #include "abm.h"
  42 #include "fixed31_32.h"
  43 #include "dpcd_defs.h"
  44 #include "dmcu.h"
  45
  46 #include "dce/dce_11_0_d.h"
  47 #include "dce/dce_11_0_enum.h"
  48 #include "dce/dce_11_0_sh_mask.h"
  49
  50 #define DC_LOGGER_INIT(logger)
  51
  52
  53 #define LINK_INFO(...) \
  54         DC_LOG_HW_HOTPLUG(  \
  55                 __VA_ARGS__)
  56
  57 #define RETIMER_REDRIVER_INFO(...) \
  58         DC_LOG_RETIMER_REDRIVER(  \
  59                 __VA_ARGS__)
  60 /*******************************************************************************
  61  * Private structures
  62  ******************************************************************************/
  63
  64 enum {
  65         LINK_RATE_REF_FREQ_IN_MHZ = 27,
  66         PEAK_FACTOR_X1000 = 1006,
  67         /*
  68         * Some receivers fail to train on first try and are good
  69         * on subsequent tries. 2 retries should be plenty. If we
  70         * don't have a successful training then we don't expect to
  71         * ever get one.
  72         */
  73         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  74 };
  75
  76 /*******************************************************************************
  77  * Private functions
  78  ******************************************************************************/
  79 static void destruct(struct dc_link *link)
  80 {
  81         int i;
  82
  83         if (link->ddc)
  84                 dal_ddc_service_destroy(&link->ddc);
  85
  86         if(link->link_enc)
  87                 link->link_enc->funcs->destroy(&link->link_enc);
  88
  89         if (link->local_sink)
  90                 dc_sink_release(link->local_sink);
  91
  92         for (i = 0; i < link->sink_count; ++i)
  93                 dc_sink_release(link->remote_sinks[i]);
  94 }
  95
  96 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
  97                 struct graphics_object_id link_id,
  98                 struct gpio_service *gpio_service)
  99 {
 100         enum bp_result bp_result;
 101         struct graphics_object_hpd_info hpd_info;
 102         struct gpio_pin_info pin_info;
 103
 104         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 105                 return NULL;
 106
 107         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 108                 hpd_info.hpd_int_gpio_uid, &pin_info);
 109
 110         if (bp_result != BP_RESULT_OK) {
 111                 ASSERT(bp_result == BP_RESULT_NORECORD);
 112                 return NULL;
 113         }
 114
 115         return dal_gpio_service_create_irq(
 116                 gpio_service,
 117                 pin_info.offset,
 118                 pin_info.mask);
 119 }
 120
 121 /*
 122  *  Function: program_hpd_filter
 123  *
 124  *  @brief
 125  *     Programs HPD filter on associated HPD line
 126  *
 127  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 128  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 129  *
 130  *  @return
 131  *     true on success, false otherwise
 132  */
 133 static bool program_hpd_filter(
 134         const struct dc_link *link)
 135 {
 136         bool result = false;
 137
 138         struct gpio *hpd;
 139
 140         int delay_on_connect_in_ms = 0;
 141         int delay_on_disconnect_in_ms = 0;
 142
 143         if (link->is_hpd_filter_disabled)
 144                 return false;
 145         /* Verify feature is supported */
 146         switch (link->connector_signal) {
 147         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 148         case SIGNAL_TYPE_DVI_DUAL_LINK:
 149         case SIGNAL_TYPE_HDMI_TYPE_A:
 150                 /* Program hpd filter */
 151                 delay_on_connect_in_ms = 500;
 152                 delay_on_disconnect_in_ms = 100;
 153                 break;
 154         case SIGNAL_TYPE_DISPLAY_PORT:
 155         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 156                 /* Program hpd filter to allow DP signal to settle */
 157                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 158                  *      only 100ms on DELL U2413
 159                  * 0:   some passive dongle still show aux mode instead of i2c
 160                  * 20-50:not enough to hide bouncing HPD with passive dongle.
 161                  *      also see intermittent i2c read issues.
 162                  */
 163                 delay_on_connect_in_ms = 80;
 164                 delay_on_disconnect_in_ms = 0;
 165                 break;
 166         case SIGNAL_TYPE_LVDS:
 167         case SIGNAL_TYPE_EDP:
 168         default:
 169                 /* Don't program hpd filter */
 170                 return false;
 171         }
 172
 173         /* Obtain HPD handle */
 174         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 175
 176         if (!hpd)
 177                 return result;
 178
 179         /* Setup HPD filtering */
 180         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 181                 struct gpio_hpd_config config;
 182
 183                 config.delay_on_connect = delay_on_connect_in_ms;
 184                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 185
 186                 dal_irq_setup_hpd_filter(hpd, &config);
 187
 188                 dal_gpio_close(hpd);
 189
 190                 result = true;
 191         } else {
 192                 ASSERT_CRITICAL(false);
 193         }
 194
 195         /* Release HPD handle */
 196         dal_gpio_destroy_irq(&hpd);
 197
 198         return result;
 199 }
 200
 201 /**
 202  * dc_link_detect_sink() - Determine if there is a sink connected
 203  *
 204  * @type: Returned connection type
 205  * Does not detect downstream devices, such as MST sinks
 206  * or display connected through active dongles
 207  */
 208 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 209 {
 210         uint32_t is_hpd_high = 0;
 211         struct gpio *hpd_pin;
 212
 213         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 214                 *type = dc_connection_single;
 215                 return true;
 216         }
 217
 218         /* todo: may need to lock gpio access */
 219         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 220         if (hpd_pin == NULL)
 221                 goto hpd_gpio_failure;
 222
 223         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 224         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 225         dal_gpio_close(hpd_pin);
 226         dal_gpio_destroy_irq(&hpd_pin);
 227
 228         if (is_hpd_high) {
 229                 *type = dc_connection_single;
 230                 /* TODO: need to do the actual detection */
 231         } else {
 232                 *type = dc_connection_none;
 233         }
 234
 235         return true;
 236
 237 hpd_gpio_failure:
 238         return false;
 239 }
 240
 241 static enum ddc_transaction_type get_ddc_transaction_type(
 242                 enum signal_type sink_signal)
 243 {
 244         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 245
 246         switch (sink_signal) {
 247         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 248         case SIGNAL_TYPE_DVI_DUAL_LINK:
 249         case SIGNAL_TYPE_HDMI_TYPE_A:
 250         case SIGNAL_TYPE_LVDS:
 251         case SIGNAL_TYPE_RGB:
 252                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 253                 break;
 254
 255         case SIGNAL_TYPE_DISPLAY_PORT:
 256         case SIGNAL_TYPE_EDP:
 257                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 258                 break;
 259
 260         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 261                 /* MST does not use I2COverAux, but there is the
 262                  * SPECIAL use case for "immediate dwnstrm device
 263                  * access" (EPR#370830). */
 264                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 265                 break;
 266
 267         default:
 268                 break;
 269         }
 270
 271         return transaction_type;
 272 }
 273
 274 static enum signal_type get_basic_signal_type(
 275         struct graphics_object_id encoder,
 276         struct graphics_object_id downstream)
 277 {
 278         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 279                 switch (downstream.id) {
 280                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 281                         switch (encoder.id) {
 282                         case ENCODER_ID_INTERNAL_DAC1:
 283                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 284                         case ENCODER_ID_INTERNAL_DAC2:
 285                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 286                                 return SIGNAL_TYPE_RGB;
 287                         default:
 288                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 289                         }
 290                 break;
 291                 case CONNECTOR_ID_DUAL_LINK_DVII:
 292                 {
 293                         switch (encoder.id) {
 294                         case ENCODER_ID_INTERNAL_DAC1:
 295                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 296                         case ENCODER_ID_INTERNAL_DAC2:
 297                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 298                                 return SIGNAL_TYPE_RGB;
 299                         default:
 300                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 301                         }
 302                 }
 303                 break;
 304                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 305                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 306                 case CONNECTOR_ID_DUAL_LINK_DVID:
 307                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 308                 case CONNECTOR_ID_VGA:
 309                         return SIGNAL_TYPE_RGB;
 310                 case CONNECTOR_ID_HDMI_TYPE_A:
 311                         return SIGNAL_TYPE_HDMI_TYPE_A;
 312                 case CONNECTOR_ID_LVDS:
 313                         return SIGNAL_TYPE_LVDS;
 314                 case CONNECTOR_ID_DISPLAY_PORT:
 315                         return SIGNAL_TYPE_DISPLAY_PORT;
 316                 case CONNECTOR_ID_EDP:
 317                         return SIGNAL_TYPE_EDP;
 318                 default:
 319                         return SIGNAL_TYPE_NONE;
 320                 }
 321         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 322                 switch (downstream.id) {
 323                 case ENCODER_ID_EXTERNAL_NUTMEG:
 324                 case ENCODER_ID_EXTERNAL_TRAVIS:
 325                         return SIGNAL_TYPE_DISPLAY_PORT;
 326                 default:
 327                         return SIGNAL_TYPE_NONE;
 328                 }
 329         }
 330
 331         return SIGNAL_TYPE_NONE;
 332 }
 333
 334 /**
 335  * dc_link_is_dp_sink_present() - Check if there is a native DP
 336  * or passive DP-HDMI dongle connected
 337  */
 338 bool dc_link_is_dp_sink_present(struct dc_link *link)
 339 {
 340         enum gpio_result gpio_result;
 341         uint32_t clock_pin = 0;
 342
 343         struct ddc *ddc;
 344
 345         enum connector_id connector_id =
 346                 dal_graphics_object_id_get_connector_id(link->link_id);
 347
 348         bool present =
 349                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 350                 (connector_id == CONNECTOR_ID_EDP));
 351
 352         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 353
 354         if (!ddc) {
 355                 BREAK_TO_DEBUGGER();
 356                 return present;
 357         }
 358
 359         /* Open GPIO and set it to I2C mode */
 360         /* Note: this GpioMode_Input will be converted
 361          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 362          * which indicates we need additional delay */
 363
 364         if (GPIO_RESULT_OK != dal_ddc_open(
 365                 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
 366                 dal_gpio_destroy_ddc(&ddc);
 367
 368                 return present;
 369         }
 370
 371         /* Read GPIO: DP sink is present if both clock and data pins are zero */
 372         /* [anaumov] in DAL2, there was no check for GPIO failure */
 373
 374         gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 375         ASSERT(gpio_result == GPIO_RESULT_OK);
 376
 377         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 378
 379         dal_ddc_close(ddc);
 380
 381         return present;
 382 }
 383
 384 /*
 385  * @brief
 386  * Detect output sink type
 387  */
 388 static enum signal_type link_detect_sink(
 389         struct dc_link *link,
 390         enum dc_detect_reason reason)
 391 {
 392         enum signal_type result = get_basic_signal_type(
 393                 link->link_enc->id, link->link_id);
 394
 395         /* Internal digital encoder will detect only dongles
 396          * that require digital signal */
 397
 398         /* Detection mechanism is different
 399          * for different native connectors.
 400          * LVDS connector supports only LVDS signal;
 401          * PCIE is a bus slot, the actual connector needs to be detected first;
 402          * eDP connector supports only eDP signal;
 403          * HDMI should check straps for audio */
 404
 405         /* PCIE detects the actual connector on add-on board */
 406
 407         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 408                 /* ZAZTODO implement PCIE add-on card detection */
 409         }
 410
 411         switch (link->link_id.id) {
 412         case CONNECTOR_ID_HDMI_TYPE_A: {
 413                 /* check audio support:
 414                  * if native HDMI is not supported, switch to DVI */
 415                 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 416
 417                 if (!aud_support->hdmi_audio_native)
 418                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 419                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 420         }
 421         break;
 422         case CONNECTOR_ID_DISPLAY_PORT: {
 423                 /* DP HPD short pulse. Passive DP dongle will not
 424                  * have short pulse
 425                  */
 426                 if (reason != DETECT_REASON_HPDRX) {
 427                         /* Check whether DP signal detected: if not -
 428                          * we assume signal is DVI; it could be corrected
 429                          * to HDMI after dongle detection
 430                          */
 431                         if (!dm_helpers_is_dp_sink_present(link))
 432                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 433                 }
 434         }
 435         break;
 436         default:
 437         break;
 438         }
 439
 440         return result;
 441 }
 442
 443 static enum signal_type decide_signal_from_strap_and_dongle_type(
 444                 enum display_dongle_type dongle_type,
 445                 struct audio_support *audio_support)
 446 {
 447         enum signal_type signal = SIGNAL_TYPE_NONE;
 448
 449         switch (dongle_type) {
 450         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 451                 if (audio_support->hdmi_audio_on_dongle)
 452                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 453                 else
 454                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 455                 break;
 456         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 457                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 458                 break;
 459         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 460                 if (audio_support->hdmi_audio_native)
 461                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 462                 else
 463                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 464                 break;
 465         default:
 466                 signal = SIGNAL_TYPE_NONE;
 467                 break;
 468         }
 469
 470         return signal;
 471 }
 472
 473 static enum signal_type dp_passive_dongle_detection(
 474                 struct ddc_service *ddc,
 475                 struct display_sink_capability *sink_cap,
 476                 struct audio_support *audio_support)
 477 {
 478         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 479                                                 ddc, sink_cap);
 480         return decide_signal_from_strap_and_dongle_type(
 481                         sink_cap->dongle_type,
 482                         audio_support);
 483 }
 484
 485 static void link_disconnect_sink(struct dc_link *link)
 486 {
 487         if (link->local_sink) {
 488                 dc_sink_release(link->local_sink);
 489                 link->local_sink = NULL;
 490         }
 491
 492         link->dpcd_sink_count = 0;
 493 }
 494
 495 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 496 {
 497         dc_sink_release(link->local_sink);
 498         link->local_sink = prev_sink;
 499 }
 500
 501
 502 static bool detect_dp(
 503         struct dc_link *link,
 504         struct display_sink_capability *sink_caps,
 505         bool *converter_disable_audio,
 506         struct audio_support *audio_support,
 507         enum dc_detect_reason reason)
 508 {
 509         bool boot = false;
 510         sink_caps->signal = link_detect_sink(link, reason);
 511         sink_caps->transaction_type =
 512                 get_ddc_transaction_type(sink_caps->signal);
 513
 514         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 515                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 516                 if (!detect_dp_sink_caps(link))
 517                         return false;
 518
 519                 if (is_mst_supported(link)) {
 520                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 521                         link->type = dc_connection_mst_branch;
 522
 523                         dal_ddc_service_set_transaction_type(
 524                                                         link->ddc,
 525                                                         sink_caps->transaction_type);
 526
 527                         /*
 528                          * This call will initiate MST topology discovery. Which
 529                          * will detect MST ports and add new DRM connector DRM
 530                          * framework. Then read EDID via remote i2c over aux. In
 531                          * the end, will notify DRM detect result and save EDID
 532                          * into DRM framework.
 533                          *
 534                          * .detect is called by .fill_modes.
 535                          * .fill_modes is called by user mode ioctl
 536                          * DRM_IOCTL_MODE_GETCONNECTOR.
 537                          *
 538                          * .get_modes is called by .fill_modes.
 539                          *
 540                          * call .get_modes, AMDGPU DM implementation will create
 541                          * new dc_sink and add to dc_link. For long HPD plug
 542                          * in/out, MST has its own handle.
 543                          *
 544                          * Therefore, just after dc_create, link->sink is not
 545                          * created for MST until user mode app calls
 546                          * DRM_IOCTL_MODE_GETCONNECTOR.
 547                          *
 548                          * Need check ->sink usages in case ->sink = NULL
 549                          * TODO: s3 resume check
 550                          */
 551                         if (reason == DETECT_REASON_BOOT)
 552                                 boot = true;
 553
 554                         dm_helpers_dp_update_branch_info(
 555                                 link->ctx,
 556                                 link);
 557
 558                         if (!dm_helpers_dp_mst_start_top_mgr(
 559                                 link->ctx,
 560                                 link, boot)) {
 561                                 /* MST not supported */
 562                                 link->type = dc_connection_single;
 563                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 564                         }
 565                 }
 566
 567                 if (link->type != dc_connection_mst_branch &&
 568                         is_dp_active_dongle(link)) {
 569                         /* DP active dongles */
 570                         link->type = dc_connection_active_dongle;
 571                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 572                                 /*
 573                                  * active dongle unplug processing for short irq
 574                                  */
 575                                 link_disconnect_sink(link);
 576                                 return true;
 577                         }
 578
 579                         if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 580                                 *converter_disable_audio = true;
 581                 }
 582         } else {
 583                 /* DP passive dongles */
 584                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 585                                 sink_caps,
 586                                 audio_support);
 587         }
 588
 589         return true;
 590 }
 591
 592 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 593 {
 594         if (old_edid->length != new_edid->length)
 595                 return false;
 596
 597         if (new_edid->length == 0)
 598                 return false;
 599
 600         return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
 601 }
 602
 603 /**
 604  * dc_link_detect() - Detect if a sink is attached to a given link
 605  *
 606  * link->local_sink is created or destroyed as needed.
 607  *
 608  * This does not create remote sinks but will trigger DM
 609  * to start MST detection if a branch is detected.
 610  */
 611 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 612 {
 613         struct dc_sink_init_data sink_init_data = { 0 };
 614         struct display_sink_capability sink_caps = { 0 };
 615         uint8_t i;
 616         bool converter_disable_audio = false;
 617         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 618         bool same_edid = false;
 619         enum dc_edid_status edid_status;
 620         struct dc_context *dc_ctx = link->ctx;
 621         struct dc_sink *sink = NULL;
 622         struct dc_sink *prev_sink = NULL;
 623         struct dpcd_caps prev_dpcd_caps;
 624         bool same_dpcd = true;
 625         enum dc_connection_type new_connection_type = dc_connection_none;
 626         DC_LOGGER_INIT(link->ctx->logger);
 627         if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
 628                 return false;
 629
 630         if (false == dc_link_detect_sink(link, &new_connection_type)) {
 631                 BREAK_TO_DEBUGGER();
 632                 return false;
 633         }
 634
 635         if (link->connector_signal == SIGNAL_TYPE_EDP &&
 636                         link->local_sink)
 637                 return true;
 638
 639         if (link->connector_signal == SIGNAL_TYPE_LVDS &&
 640                         link->local_sink)
 641                 return true;
 642
 643         prev_sink = link->local_sink;
 644         if (prev_sink != NULL) {
 645                 dc_sink_retain(prev_sink);
 646                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 647         }
 648         link_disconnect_sink(link);
 649
 650         if (new_connection_type != dc_connection_none) {
 651                 link->type = new_connection_type;
 652
 653                 /* From Disconnected-to-Connected. */
 654                 switch (link->connector_signal) {
 655                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 656                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 657                         if (aud_support->hdmi_audio_native)
 658                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 659                         else
 660                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 661                         break;
 662                 }
 663
 664                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 665                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 666                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 667                         break;
 668                 }
 669
 670                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 671                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 672                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 673                         break;
 674                 }
 675
 676                 case SIGNAL_TYPE_LVDS: {
 677                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 678                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 679                         break;
 680                 }
 681
 682                 case SIGNAL_TYPE_EDP: {
 683                         detect_edp_sink_caps(link);
 684                         sink_caps.transaction_type =
 685                                 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 686                         sink_caps.signal = SIGNAL_TYPE_EDP;
 687                         break;
 688                 }
 689
 690                 case SIGNAL_TYPE_DISPLAY_PORT: {
 691                         if (!detect_dp(
 692                                 link,
 693                                 &sink_caps,
 694                                 &converter_disable_audio,
 695                                 aud_support, reason)) {
 696                                 if (prev_sink != NULL)
 697                                         dc_sink_release(prev_sink);
 698                                 return false;
 699                         }
 700
 701                         // Check if dpcp block is the same
 702                         if (prev_sink != NULL) {
 703                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
 704                                         same_dpcd = false;
 705                         }
 706                         /* Active dongle downstream unplug */
 707                         if (link->type == dc_connection_active_dongle
 708                                         && link->dpcd_caps.sink_count.
 709                                         bits.SINK_COUNT == 0) {
 710                                 if (prev_sink != NULL)
 711                                         dc_sink_release(prev_sink);
 712                                 return true;
 713                         }
 714
 715                         if (link->type == dc_connection_mst_branch) {
 716                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 717                                         link->link_index);
 718                                 /* Need to setup mst link_cap struct here
 719                                  * otherwise dc_link_detect() will leave mst link_cap
 720                                  * empty which leads to allocate_mst_payload() has "0"
 721                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 722                                  */
 723                                 link->verified_link_cap = link->reported_link_cap;
 724                                 if (prev_sink != NULL)
 725                                         dc_sink_release(prev_sink);
 726                                 return false;
 727                         }
 728
 729                         break;
 730                 }
 731
 732                 default:
 733                         DC_ERROR("Invalid connector type! signal:%d\n",
 734                                 link->connector_signal);
 735                         if (prev_sink != NULL)
 736                                 dc_sink_release(prev_sink);
 737                         return false;
 738                 } /* switch() */
 739
 740                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
 741                         link->dpcd_sink_count = link->dpcd_caps.sink_count.
 742                                         bits.SINK_COUNT;
 743                 else
 744                         link->dpcd_sink_count = 1;
 745
 746                 dal_ddc_service_set_transaction_type(
 747                                                 link->ddc,
 748                                                 sink_caps.transaction_type);
 749
 750                 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
 751                                 link->ddc);
 752
 753                 sink_init_data.link = link;
 754                 sink_init_data.sink_signal = sink_caps.signal;
 755
 756                 sink = dc_sink_create(&sink_init_data);
 757                 if (!sink) {
 758                         DC_ERROR("Failed to create sink!\n");
 759                         if (prev_sink != NULL)
 760                                 dc_sink_release(prev_sink);
 761                         return false;
 762                 }
 763
 764                 sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
 765                 sink->converter_disable_audio = converter_disable_audio;
 766
 767                 link->local_sink = sink;
 768
 769                 edid_status = dm_helpers_read_local_edid(
 770                                 link->ctx,
 771                                 link,
 772                                 sink);
 773
 774                 switch (edid_status) {
 775                 case EDID_BAD_CHECKSUM:
 776                         DC_LOG_ERROR("EDID checksum invalid.\n");
 777                         break;
 778                 case EDID_NO_RESPONSE:
 779                         DC_LOG_ERROR("No EDID read.\n");
 780
 781                         /*
 782                          * Abort detection for non-DP connectors if we have
 783                          * no EDID
 784                          *
 785                          * DP needs to report as connected if HDP is high
 786                          * even if we have no EDID in order to go to
 787                          * fail-safe mode
 788                          */
 789                         if (dc_is_hdmi_signal(link->connector_signal) ||
 790                             dc_is_dvi_signal(link->connector_signal)) {
 791                                 if (prev_sink != NULL)
 792                                         dc_sink_release(prev_sink);
 793
 794                                 return false;
 795                         }
 796                 default:
 797                         break;
 798                 }
 799
 800                 // Check if edid is the same
 801                 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
 802                         same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
 803
 804                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 805                         sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX &&
 806                         reason != DETECT_REASON_HPDRX) {
 807                         /*
 808                          * TODO debug why Dell 2413 doesn't like
 809                          *  two link trainings
 810                          */
 811
 812                         /* deal with non-mst cases */
 813                         for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
 814                                 int fail_count = 0;
 815
 816                                 dp_verify_link_cap(link,
 817                                                   &link->reported_link_cap,
 818                                                   &fail_count);
 819
 820                                 if (fail_count == 0)
 821                                         break;
 822                         }
 823
 824                 } else {
 825                         // If edid is the same, then discard new sink and revert back to original sink
 826                         if (same_edid) {
 827                                 link_disconnect_remap(prev_sink, link);
 828                                 sink = prev_sink;
 829                                 prev_sink = NULL;
 830
 831                         }
 832                 }
 833
 834                 /* HDMI-DVI Dongle */
 835                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
 836                                 !sink->edid_caps.edid_hdmi)
 837                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 838
 839                 /* Connectivity log: detection */
 840                 for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
 841                         CONN_DATA_DETECT(link,
 842                                         &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
 843                                         EDID_BLOCK_SIZE,
 844                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
 845                 }
 846
 847                 DC_LOG_DETECTION_EDID_PARSER("%s: "
 848                         "manufacturer_id = %X, "
 849                         "product_id = %X, "
 850                         "serial_number = %X, "
 851                         "manufacture_week = %d, "
 852                         "manufacture_year = %d, "
 853                         "display_name = %s, "
 854                         "speaker_flag = %d, "
 855                         "audio_mode_count = %d\n",
 856                         __func__,
 857                         sink->edid_caps.manufacturer_id,
 858                         sink->edid_caps.product_id,
 859                         sink->edid_caps.serial_number,
 860                         sink->edid_caps.manufacture_week,
 861                         sink->edid_caps.manufacture_year,
 862                         sink->edid_caps.display_name,
 863                         sink->edid_caps.speaker_flags,
 864                         sink->edid_caps.audio_mode_count);
 865
 866                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
 867                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
 868                                 "format_code = %d, "
 869                                 "channel_count = %d, "
 870                                 "sample_rate = %d, "
 871                                 "sample_size = %d\n",
 872                                 __func__,
 873                                 i,
 874                                 sink->edid_caps.audio_modes[i].format_code,
 875                                 sink->edid_caps.audio_modes[i].channel_count,
 876                                 sink->edid_caps.audio_modes[i].sample_rate,
 877                                 sink->edid_caps.audio_modes[i].sample_size);
 878                 }
 879
 880         } else {
 881                 /* From Connected-to-Disconnected. */
 882                 if (link->type == dc_connection_mst_branch) {
 883                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 884                                 link->link_index);
 885
 886                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 887
 888                         link->mst_stream_alloc_table.stream_count = 0;
 889                         memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
 890                 }
 891
 892                 link->type = dc_connection_none;
 893                 sink_caps.signal = SIGNAL_TYPE_NONE;
 894         }
 895
 896         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
 897                 link->link_index, sink,
 898                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
 899                         "Disconnected":"Connected"), prev_sink,
 900                         same_dpcd, same_edid);
 901
 902         if (prev_sink != NULL)
 903                 dc_sink_release(prev_sink);
 904
 905         return true;
 906 }
 907
 908 bool dc_link_get_hpd_state(struct dc_link *dc_link)
 909 {
 910         struct gpio *hpd_pin;
 911         uint32_t state;
 912
 913         hpd_pin = get_hpd_gpio(dc_link->ctx->dc_bios,
 914                                         dc_link->link_id, dc_link->ctx->gpio_service);
 915         if (hpd_pin == NULL)
 916                 ASSERT(false);
 917
 918         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 919         dal_gpio_get_value(hpd_pin, &state);
 920         dal_gpio_close(hpd_pin);
 921         dal_gpio_destroy_irq(&hpd_pin);
 922
 923         return state;
 924 }
 925
 926 static enum hpd_source_id get_hpd_line(
 927                 struct dc_link *link)
 928 {
 929         struct gpio *hpd;
 930         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
 931
 932         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 933
 934         if (hpd) {
 935                 switch (dal_irq_get_source(hpd)) {
 936                 case DC_IRQ_SOURCE_HPD1:
 937                         hpd_id = HPD_SOURCEID1;
 938                 break;
 939                 case DC_IRQ_SOURCE_HPD2:
 940                         hpd_id = HPD_SOURCEID2;
 941                 break;
 942                 case DC_IRQ_SOURCE_HPD3:
 943                         hpd_id = HPD_SOURCEID3;
 944                 break;
 945                 case DC_IRQ_SOURCE_HPD4:
 946                         hpd_id = HPD_SOURCEID4;
 947                 break;
 948                 case DC_IRQ_SOURCE_HPD5:
 949                         hpd_id = HPD_SOURCEID5;
 950                 break;
 951                 case DC_IRQ_SOURCE_HPD6:
 952                         hpd_id = HPD_SOURCEID6;
 953                 break;
 954                 default:
 955                         BREAK_TO_DEBUGGER();
 956                 break;
 957                 }
 958
 959                 dal_gpio_destroy_irq(&hpd);
 960         }
 961
 962         return hpd_id;
 963 }
 964
 965 static enum channel_id get_ddc_line(struct dc_link *link)
 966 {
 967         struct ddc *ddc;
 968         enum channel_id channel = CHANNEL_ID_UNKNOWN;
 969
 970         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 971
 972         if (ddc) {
 973                 switch (dal_ddc_get_line(ddc)) {
 974                 case GPIO_DDC_LINE_DDC1:
 975                         channel = CHANNEL_ID_DDC1;
 976                         break;
 977                 case GPIO_DDC_LINE_DDC2:
 978                         channel = CHANNEL_ID_DDC2;
 979                         break;
 980                 case GPIO_DDC_LINE_DDC3:
 981                         channel = CHANNEL_ID_DDC3;
 982                         break;
 983                 case GPIO_DDC_LINE_DDC4:
 984                         channel = CHANNEL_ID_DDC4;
 985                         break;
 986                 case GPIO_DDC_LINE_DDC5:
 987                         channel = CHANNEL_ID_DDC5;
 988                         break;
 989                 case GPIO_DDC_LINE_DDC6:
 990                         channel = CHANNEL_ID_DDC6;
 991                         break;
 992                 case GPIO_DDC_LINE_DDC_VGA:
 993                         channel = CHANNEL_ID_DDC_VGA;
 994                         break;
 995                 case GPIO_DDC_LINE_I2C_PAD:
 996                         channel = CHANNEL_ID_I2C_PAD;
 997                         break;
 998                 default:
 999                         BREAK_TO_DEBUGGER();
1000                         break;
1001                 }
1002         }
1003
1004         return channel;
1005 }
1006
1007 static enum transmitter translate_encoder_to_transmitter(
1008         struct graphics_object_id encoder)
1009 {
1010         switch (encoder.id) {
1011         case ENCODER_ID_INTERNAL_UNIPHY:
1012                 switch (encoder.enum_id) {
1013                 case ENUM_ID_1:
1014                         return TRANSMITTER_UNIPHY_A;
1015                 case ENUM_ID_2:
1016                         return TRANSMITTER_UNIPHY_B;
1017                 default:
1018                         return TRANSMITTER_UNKNOWN;
1019                 }
1020         break;
1021         case ENCODER_ID_INTERNAL_UNIPHY1:
1022                 switch (encoder.enum_id) {
1023                 case ENUM_ID_1:
1024                         return TRANSMITTER_UNIPHY_C;
1025                 case ENUM_ID_2:
1026                         return TRANSMITTER_UNIPHY_D;
1027                 default:
1028                         return TRANSMITTER_UNKNOWN;
1029                 }
1030         break;
1031         case ENCODER_ID_INTERNAL_UNIPHY2:
1032                 switch (encoder.enum_id) {
1033                 case ENUM_ID_1:
1034                         return TRANSMITTER_UNIPHY_E;
1035                 case ENUM_ID_2:
1036                         return TRANSMITTER_UNIPHY_F;
1037                 default:
1038                         return TRANSMITTER_UNKNOWN;
1039                 }
1040         break;
1041         case ENCODER_ID_INTERNAL_UNIPHY3:
1042                 switch (encoder.enum_id) {
1043                 case ENUM_ID_1:
1044                         return TRANSMITTER_UNIPHY_G;
1045                 default:
1046                         return TRANSMITTER_UNKNOWN;
1047                 }
1048         break;
1049         case ENCODER_ID_EXTERNAL_NUTMEG:
1050                 switch (encoder.enum_id) {
1051                 case ENUM_ID_1:
1052                         return TRANSMITTER_NUTMEG_CRT;
1053                 default:
1054                         return TRANSMITTER_UNKNOWN;
1055                 }
1056         break;
1057         case ENCODER_ID_EXTERNAL_TRAVIS:
1058                 switch (encoder.enum_id) {
1059                 case ENUM_ID_1:
1060                         return TRANSMITTER_TRAVIS_CRT;
1061                 case ENUM_ID_2:
1062                         return TRANSMITTER_TRAVIS_LCD;
1063                 default:
1064                         return TRANSMITTER_UNKNOWN;
1065                 }
1066         break;
1067         default:
1068                 return TRANSMITTER_UNKNOWN;
1069         }
1070 }
1071
1072 static bool construct(
1073         struct dc_link *link,
1074         const struct link_init_data *init_params)
1075 {
1076         uint8_t i;
1077         struct gpio *hpd_gpio = NULL;
1078         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1079         struct dc_context *dc_ctx = init_params->ctx;
1080         struct encoder_init_data enc_init_data = { 0 };
1081         struct integrated_info info = {{{ 0 }}};
1082         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1083         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1084         DC_LOGGER_INIT(dc_ctx->logger);
1085
1086         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1087         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1088
1089         link->link_status.dpcd_caps = &link->dpcd_caps;
1090
1091         link->dc = init_params->dc;
1092         link->ctx = dc_ctx;
1093         link->link_index = init_params->link_index;
1094
1095         link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1096
1097         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1098                 dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1099                          __func__, init_params->connector_index,
1100                          link->link_id.type, OBJECT_TYPE_CONNECTOR);
1101                 goto create_fail;
1102         }
1103
1104         if (link->dc->res_pool->funcs->link_init)
1105                 link->dc->res_pool->funcs->link_init(link);
1106
1107         hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1108
1109         if (hpd_gpio != NULL)
1110                 link->irq_source_hpd = dal_irq_get_source(hpd_gpio);
1111
1112         switch (link->link_id.id) {
1113         case CONNECTOR_ID_HDMI_TYPE_A:
1114                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1115
1116                 break;
1117         case CONNECTOR_ID_SINGLE_LINK_DVID:
1118         case CONNECTOR_ID_SINGLE_LINK_DVII:
1119                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1120                 break;
1121         case CONNECTOR_ID_DUAL_LINK_DVID:
1122         case CONNECTOR_ID_DUAL_LINK_DVII:
1123                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1124                 break;
1125         case CONNECTOR_ID_DISPLAY_PORT:
1126                 link->connector_signal =        SIGNAL_TYPE_DISPLAY_PORT;
1127
1128                 if (hpd_gpio != NULL)
1129                         link->irq_source_hpd_rx =
1130                                         dal_irq_get_rx_source(hpd_gpio);
1131
1132                 break;
1133         case CONNECTOR_ID_EDP:
1134                 link->connector_signal = SIGNAL_TYPE_EDP;
1135
1136                 if (hpd_gpio != NULL) {
1137                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1138                         link->irq_source_hpd_rx =
1139                                         dal_irq_get_rx_source(hpd_gpio);
1140                 }
1141                 break;
1142         case CONNECTOR_ID_LVDS:
1143                 link->connector_signal = SIGNAL_TYPE_LVDS;
1144                 break;
1145         default:
1146                 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1147                 goto create_fail;
1148         }
1149
1150         if (hpd_gpio != NULL) {
1151                 dal_gpio_destroy_irq(&hpd_gpio);
1152                 hpd_gpio = NULL;
1153         }
1154
1155         /* TODO: #DAL3 Implement id to str function.*/
1156         LINK_INFO("Connector[%d] description:"
1157                         "signal %d\n",
1158                         init_params->connector_index,
1159                         link->connector_signal);
1160
1161         ddc_service_init_data.ctx = link->ctx;
1162         ddc_service_init_data.id = link->link_id;
1163         ddc_service_init_data.link = link;
1164         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1165
1166         if (link->ddc == NULL) {
1167                 DC_ERROR("Failed to create ddc_service!\n");
1168                 goto ddc_create_fail;
1169         }
1170
1171         link->ddc_hw_inst =
1172                 dal_ddc_get_line(
1173                         dal_ddc_service_get_ddc_pin(link->ddc));
1174
1175         enc_init_data.ctx = dc_ctx;
1176         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1177         enc_init_data.connector = link->link_id;
1178         enc_init_data.channel = get_ddc_line(link);
1179         enc_init_data.hpd_source = get_hpd_line(link);
1180
1181         link->hpd_src = enc_init_data.hpd_source;
1182
1183         enc_init_data.transmitter =
1184                         translate_encoder_to_transmitter(enc_init_data.encoder);
1185         link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1186                                                                 &enc_init_data);
1187
1188         if( link->link_enc == NULL) {
1189                 DC_ERROR("Failed to create link encoder!\n");
1190                 goto link_enc_create_fail;
1191         }
1192
1193         link->link_enc_hw_inst = link->link_enc->transmitter;
1194
1195         for (i = 0; i < 4; i++) {
1196                 if (BP_RESULT_OK !=
1197                                 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1198                         DC_ERROR("Failed to find device tag!\n");
1199                         goto device_tag_fail;
1200                 }
1201
1202                 /* Look for device tag that matches connector signal,
1203                  * CRT for rgb, LCD for other supported signal tyes
1204                  */
1205                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1206                         continue;
1207                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1208                         && link->connector_signal != SIGNAL_TYPE_RGB)
1209                         continue;
1210                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1211                         && link->connector_signal == SIGNAL_TYPE_RGB)
1212                         continue;
1213                 break;
1214         }
1215
1216         if (bios->integrated_info)
1217                 info = *bios->integrated_info;
1218
1219         /* Look for channel mapping corresponding to connector and device tag */
1220         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1221                 struct external_display_path *path =
1222                         &info.ext_disp_conn_info.path[i];
1223                 if (path->device_connector_id.enum_id == link->link_id.enum_id
1224                         && path->device_connector_id.id == link->link_id.id
1225                         && path->device_connector_id.type == link->link_id.type) {
1226
1227                         if (link->device_tag.acpi_device != 0
1228                                 && path->device_acpi_enum == link->device_tag.acpi_device) {
1229                                 link->ddi_channel_mapping = path->channel_mapping;
1230                                 link->chip_caps = path->caps;
1231                         } else if (path->device_tag ==
1232                                         link->device_tag.dev_id.raw_device_tag) {
1233                                 link->ddi_channel_mapping = path->channel_mapping;
1234                                 link->chip_caps = path->caps;
1235                         }
1236                         break;
1237                 }
1238         }
1239
1240         /*
1241          * TODO check if GPIO programmed correctly
1242          *
1243          * If GPIO isn't programmed correctly HPD might not rise or drain
1244          * fast enough, leading to bounces.
1245          */
1246         program_hpd_filter(link);
1247
1248         return true;
1249 device_tag_fail:
1250         link->link_enc->funcs->destroy(&link->link_enc);
1251 link_enc_create_fail:
1252         dal_ddc_service_destroy(&link->ddc);
1253 ddc_create_fail:
1254 create_fail:
1255
1256         if (hpd_gpio != NULL) {
1257                 dal_gpio_destroy_irq(&hpd_gpio);
1258         }
1259
1260         return false;
1261 }
1262
1263 /*******************************************************************************
1264  * Public functions
1265  ******************************************************************************/
1266 struct dc_link *link_create(const struct link_init_data *init_params)
1267 {
1268         struct dc_link *link =
1269                         kzalloc(sizeof(*link), GFP_KERNEL);
1270
1271         if (NULL == link)
1272                 goto alloc_fail;
1273
1274         if (false == construct(link, init_params))
1275                 goto construct_fail;
1276
1277         return link;
1278
1279 construct_fail:
1280         kfree(link);
1281
1282 alloc_fail:
1283         return NULL;
1284 }
1285
1286 void link_destroy(struct dc_link **link)
1287 {
1288         destruct(*link);
1289         kfree(*link);
1290         *link = NULL;
1291 }
1292
1293 static void dpcd_configure_panel_mode(
1294         struct dc_link *link,
1295         enum dp_panel_mode panel_mode)
1296 {
1297         union dpcd_edp_config edp_config_set;
1298         bool panel_mode_edp = false;
1299         DC_LOGGER_INIT(link->ctx->logger);
1300
1301         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
1302
1303         if (DP_PANEL_MODE_DEFAULT != panel_mode) {
1304
1305                 switch (panel_mode) {
1306                 case DP_PANEL_MODE_EDP:
1307                 case DP_PANEL_MODE_SPECIAL:
1308                         panel_mode_edp = true;
1309                         break;
1310
1311                 default:
1312                         break;
1313                 }
1314
1315                 /*set edp panel mode in receiver*/
1316                 core_link_read_dpcd(
1317                         link,
1318                         DP_EDP_CONFIGURATION_SET,
1319                         &edp_config_set.raw,
1320                         sizeof(edp_config_set.raw));
1321
1322                 if (edp_config_set.bits.PANEL_MODE_EDP
1323                         != panel_mode_edp) {
1324                         enum ddc_result result = DDC_RESULT_UNKNOWN;
1325
1326                         edp_config_set.bits.PANEL_MODE_EDP =
1327                         panel_mode_edp;
1328                         result = core_link_write_dpcd(
1329                                 link,
1330                                 DP_EDP_CONFIGURATION_SET,
1331                                 &edp_config_set.raw,
1332                                 sizeof(edp_config_set.raw));
1333
1334                         ASSERT(result == DDC_RESULT_SUCESSFULL);
1335                 }
1336         }
1337         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
1338                         "eDP panel mode enabled: %d \n",
1339                         link->link_index,
1340                         link->dpcd_caps.panel_mode_edp,
1341                         panel_mode_edp);
1342 }
1343
1344 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1345 {
1346         struct dc_stream_state *stream = pipe_ctx->stream;
1347         struct dc_link *link = stream->sink->link;
1348         union down_spread_ctrl old_downspread;
1349         union down_spread_ctrl new_downspread;
1350
1351         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1352                         &old_downspread.raw, sizeof(old_downspread));
1353
1354         new_downspread.raw = old_downspread.raw;
1355
1356         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1357                         (stream->ignore_msa_timing_param) ? 1 : 0;
1358
1359         if (new_downspread.raw != old_downspread.raw) {
1360                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1361                         &new_downspread.raw, sizeof(new_downspread));
1362         }
1363 }
1364
1365 static enum dc_status enable_link_dp(
1366                 struct dc_state *state,
1367                 struct pipe_ctx *pipe_ctx)
1368 {
1369         struct dc_stream_state *stream = pipe_ctx->stream;
1370         enum dc_status status;
1371         bool skip_video_pattern;
1372         struct dc_link *link = stream->sink->link;
1373         struct dc_link_settings link_settings = {0};
1374         enum dp_panel_mode panel_mode;
1375
1376         /* get link settings for video mode timing */
1377         decide_link_settings(stream, &link_settings);
1378
1379         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1380                         link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1381         state->dccg->funcs->update_clocks(state->dccg, state, false);
1382
1383         dp_enable_link_phy(
1384                 link,
1385                 pipe_ctx->stream->signal,
1386                 pipe_ctx->clock_source->id,
1387                 &link_settings);
1388
1389         if (stream->sink->edid_caps.panel_patch.dppowerup_delay > 0) {
1390                 int delay_dp_power_up_in_ms = stream->sink->edid_caps.panel_patch.dppowerup_delay;
1391
1392                 msleep(delay_dp_power_up_in_ms);
1393         }
1394
1395         panel_mode = dp_get_panel_mode(link);
1396         dpcd_configure_panel_mode(link, panel_mode);
1397
1398         skip_video_pattern = true;
1399
1400         if (link_settings.link_rate == LINK_RATE_LOW)
1401                         skip_video_pattern = false;
1402
1403         if (perform_link_training_with_retries(
1404                         link,
1405                         &link_settings,
1406                         skip_video_pattern,
1407                         LINK_TRAINING_ATTEMPTS)) {
1408                 link->cur_link_settings = link_settings;
1409                 status = DC_OK;
1410         }
1411         else
1412                 status = DC_FAIL_DP_LINK_TRAINING;
1413
1414         return status;
1415 }
1416
1417 static enum dc_status enable_link_edp(
1418                 struct dc_state *state,
1419                 struct pipe_ctx *pipe_ctx)
1420 {
1421         enum dc_status status;
1422         struct dc_stream_state *stream = pipe_ctx->stream;
1423         struct dc_link *link = stream->sink->link;
1424         /*in case it is not on*/
1425         link->dc->hwss.edp_power_control(link, true);
1426         link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1427
1428         status = enable_link_dp(state, pipe_ctx);
1429
1430
1431         return status;
1432 }
1433
1434 static enum dc_status enable_link_dp_mst(
1435                 struct dc_state *state,
1436                 struct pipe_ctx *pipe_ctx)
1437 {
1438         struct dc_link *link = pipe_ctx->stream->sink->link;
1439
1440         /* sink signal type after MST branch is MST. Multiple MST sinks
1441          * share one link. Link DP PHY is enable or training only once.
1442          */
1443         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1444                 return DC_OK;
1445
1446         /* clear payload table */
1447         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1448
1449         /* set the sink to MST mode before enabling the link */
1450         dp_enable_mst_on_sink(link, true);
1451
1452         return enable_link_dp(state, pipe_ctx);
1453 }
1454
1455 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1456                 enum engine_id eng_id,
1457                 struct ext_hdmi_settings *settings)
1458 {
1459         bool result = false;
1460         int i = 0;
1461         struct integrated_info *integrated_info =
1462                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1463
1464         if (integrated_info == NULL)
1465                 return false;
1466
1467         /*
1468          * Get retimer settings from sbios for passing SI eye test for DCE11
1469          * The setting values are varied based on board revision and port id
1470          * Therefore the setting values of each ports is passed by sbios.
1471          */
1472
1473         // Check if current bios contains ext Hdmi settings
1474         if (integrated_info->gpu_cap_info & 0x20) {
1475                 switch (eng_id) {
1476                 case ENGINE_ID_DIGA:
1477                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1478                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1479                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1480                         memmove(settings->reg_settings,
1481                                         integrated_info->dp0_ext_hdmi_reg_settings,
1482                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1483                         memmove(settings->reg_settings_6g,
1484                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1485                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1486                         result = true;
1487                         break;
1488                 case ENGINE_ID_DIGB:
1489                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1490                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1491                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1492                         memmove(settings->reg_settings,
1493                                         integrated_info->dp1_ext_hdmi_reg_settings,
1494                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1495                         memmove(settings->reg_settings_6g,
1496                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1497                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1498                         result = true;
1499                         break;
1500                 case ENGINE_ID_DIGC:
1501                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1502                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1503                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1504                         memmove(settings->reg_settings,
1505                                         integrated_info->dp2_ext_hdmi_reg_settings,
1506                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1507                         memmove(settings->reg_settings_6g,
1508                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1509                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1510                         result = true;
1511                         break;
1512                 case ENGINE_ID_DIGD:
1513                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1514                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1515                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1516                         memmove(settings->reg_settings,
1517                                         integrated_info->dp3_ext_hdmi_reg_settings,
1518                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1519                         memmove(settings->reg_settings_6g,
1520                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1521                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1522                         result = true;
1523                         break;
1524                 default:
1525                         break;
1526                 }
1527
1528                 if (result == true) {
1529                         // Validate settings from bios integrated info table
1530                         if (settings->slv_addr == 0)
1531                                 return false;
1532                         if (settings->reg_num > 9)
1533                                 return false;
1534                         if (settings->reg_num_6g > 3)
1535                                 return false;
1536
1537                         for (i = 0; i < settings->reg_num; i++) {
1538                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1539                                         return false;
1540                         }
1541
1542                         for (i = 0; i < settings->reg_num_6g; i++) {
1543                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1544                                         return false;
1545                         }
1546                 }
1547         }
1548
1549         return result;
1550 }
1551
1552 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1553                 uint8_t address, uint8_t *buffer, uint32_t length)
1554 {
1555         struct i2c_command cmd = {0};
1556         struct i2c_payload payload = {0};
1557
1558         memset(&payload, 0, sizeof(payload));
1559         memset(&cmd, 0, sizeof(cmd));
1560
1561         cmd.number_of_payloads = 1;
1562         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1563         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1564
1565         payload.address = address;
1566         payload.data = buffer;
1567         payload.length = length;
1568         payload.write = true;
1569         cmd.payloads = &payload;
1570
1571         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1572                         pipe_ctx->stream->sink->link, &cmd))
1573                 return true;
1574
1575         return false;
1576 }
1577
1578 static void write_i2c_retimer_setting(
1579                 struct pipe_ctx *pipe_ctx,
1580                 bool is_vga_mode,
1581                 bool is_over_340mhz,
1582                 struct ext_hdmi_settings *settings)
1583 {
1584         uint8_t slave_address = (settings->slv_addr >> 1);
1585         uint8_t buffer[2];
1586         const uint8_t apply_rx_tx_change = 0x4;
1587         uint8_t offset = 0xA;
1588         uint8_t value = 0;
1589         int i = 0;
1590         bool i2c_success = false;
1591         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1592
1593         memset(&buffer, 0, sizeof(buffer));
1594
1595         /* Start Ext-Hdmi programming*/
1596
1597         for (i = 0; i < settings->reg_num; i++) {
1598                 /* Apply 3G settings */
1599                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1600
1601                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1602                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1603                         i2c_success = i2c_write(pipe_ctx, slave_address,
1604                                                 buffer, sizeof(buffer));
1605                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1606                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1607                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1608
1609                         if (!i2c_success)
1610                                 /* Write failure */
1611                                 ASSERT(i2c_success);
1612
1613                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1614                          * needs to be set to 1 on every 0xA-0xC write.
1615                          */
1616                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1617                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1618                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1619
1620                                 /* Query current value from offset 0xA */
1621                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1622                                         value = settings->reg_settings[i].i2c_reg_val;
1623                                 else {
1624                                         i2c_success =
1625                                                 dal_ddc_service_query_ddc_data(
1626                                                 pipe_ctx->stream->sink->link->ddc,
1627                                                 slave_address, &offset, 1, &value, 1);
1628                                         if (!i2c_success)
1629                                                 /* Write failure */
1630                                                 ASSERT(i2c_success);
1631                                 }
1632
1633                                 buffer[0] = offset;
1634                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1635                                 buffer[1] = value | apply_rx_tx_change;
1636                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1637                                                 buffer, sizeof(buffer));
1638                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1639                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1640                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1641                                 if (!i2c_success)
1642                                         /* Write failure */
1643                                         ASSERT(i2c_success);
1644                         }
1645                 }
1646         }
1647
1648         /* Apply 3G settings */
1649         if (is_over_340mhz) {
1650                 for (i = 0; i < settings->reg_num_6g; i++) {
1651                         /* Apply 3G settings */
1652                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1653
1654                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1655                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1656                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1657                                                         buffer, sizeof(buffer));
1658                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1659                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1660                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1661
1662                                 if (!i2c_success)
1663                                         /* Write failure */
1664                                         ASSERT(i2c_success);
1665
1666                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1667                                  * needs to be set to 1 on every 0xA-0xC write.
1668                                  */
1669                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1670                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1671                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1672
1673                                         /* Query current value from offset 0xA */
1674                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1675                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1676                                         else {
1677                                                 i2c_success =
1678                                                                 dal_ddc_service_query_ddc_data(
1679                                                                 pipe_ctx->stream->sink->link->ddc,
1680                                                                 slave_address, &offset, 1, &value, 1);
1681                                                 if (!i2c_success)
1682                                                         /* Write failure */
1683                                                         ASSERT(i2c_success);
1684                                         }
1685
1686                                         buffer[0] = offset;
1687                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1688                                         buffer[1] = value | apply_rx_tx_change;
1689                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1690                                                         buffer, sizeof(buffer));
1691                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1692                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1693                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1694                                         if (!i2c_success)
1695                                                 /* Write failure */
1696                                                 ASSERT(i2c_success);
1697                                 }
1698                         }
1699                 }
1700         }
1701
1702         if (is_vga_mode) {
1703                 /* Program additional settings if using 640x480 resolution */
1704
1705                 /* Write offset 0xFF to 0x01 */
1706                 buffer[0] = 0xff;
1707                 buffer[1] = 0x01;
1708                 i2c_success = i2c_write(pipe_ctx, slave_address,
1709                                 buffer, sizeof(buffer));
1710                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1711                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1712                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1713                 if (!i2c_success)
1714                         /* Write failure */
1715                         ASSERT(i2c_success);
1716
1717                 /* Write offset 0x00 to 0x23 */
1718                 buffer[0] = 0x00;
1719                 buffer[1] = 0x23;
1720                 i2c_success = i2c_write(pipe_ctx, slave_address,
1721                                 buffer, sizeof(buffer));
1722                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1723                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1724                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1725                 if (!i2c_success)
1726                         /* Write failure */
1727                         ASSERT(i2c_success);
1728
1729                 /* Write offset 0xff to 0x00 */
1730                 buffer[0] = 0xff;
1731                 buffer[1] = 0x00;
1732                 i2c_success = i2c_write(pipe_ctx, slave_address,
1733                                 buffer, sizeof(buffer));
1734                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1735                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1736                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1737                 if (!i2c_success)
1738                         /* Write failure */
1739                         ASSERT(i2c_success);
1740
1741         }
1742 }
1743
1744 static void write_i2c_default_retimer_setting(
1745                 struct pipe_ctx *pipe_ctx,
1746                 bool is_vga_mode,
1747                 bool is_over_340mhz)
1748 {
1749         uint8_t slave_address = (0xBA >> 1);
1750         uint8_t buffer[2];
1751         bool i2c_success = false;
1752         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1753
1754         memset(&buffer, 0, sizeof(buffer));
1755
1756         /* Program Slave Address for tuning single integrity */
1757         /* Write offset 0x0A to 0x13 */
1758         buffer[0] = 0x0A;
1759         buffer[1] = 0x13;
1760         i2c_success = i2c_write(pipe_ctx, slave_address,
1761                         buffer, sizeof(buffer));
1762         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
1763                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1764                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1765         if (!i2c_success)
1766                 /* Write failure */
1767                 ASSERT(i2c_success);
1768
1769         /* Write offset 0x0A to 0x17 */
1770         buffer[0] = 0x0A;
1771         buffer[1] = 0x17;
1772         i2c_success = i2c_write(pipe_ctx, slave_address,
1773                         buffer, sizeof(buffer));
1774         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1775                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1776                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1777         if (!i2c_success)
1778                 /* Write failure */
1779                 ASSERT(i2c_success);
1780
1781         /* Write offset 0x0B to 0xDA or 0xD8 */
1782         buffer[0] = 0x0B;
1783         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1784         i2c_success = i2c_write(pipe_ctx, slave_address,
1785                         buffer, sizeof(buffer));
1786         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1787                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1788                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1789         if (!i2c_success)
1790                 /* Write failure */
1791                 ASSERT(i2c_success);
1792
1793         /* Write offset 0x0A to 0x17 */
1794         buffer[0] = 0x0A;
1795         buffer[1] = 0x17;
1796         i2c_success = i2c_write(pipe_ctx, slave_address,
1797                         buffer, sizeof(buffer));
1798         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1799                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1800                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1801         if (!i2c_success)
1802                 /* Write failure */
1803                 ASSERT(i2c_success);
1804
1805         /* Write offset 0x0C to 0x1D or 0x91 */
1806         buffer[0] = 0x0C;
1807         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1808         i2c_success = i2c_write(pipe_ctx, slave_address,
1809                         buffer, sizeof(buffer));
1810         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1811                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1812                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1813         if (!i2c_success)
1814                 /* Write failure */
1815                 ASSERT(i2c_success);
1816
1817         /* Write offset 0x0A to 0x17 */
1818         buffer[0] = 0x0A;
1819         buffer[1] = 0x17;
1820         i2c_success = i2c_write(pipe_ctx, slave_address,
1821                         buffer, sizeof(buffer));
1822         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1823                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1824                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1825         if (!i2c_success)
1826                 /* Write failure */
1827                 ASSERT(i2c_success);
1828
1829
1830         if (is_vga_mode) {
1831                 /* Program additional settings if using 640x480 resolution */
1832
1833                 /* Write offset 0xFF to 0x01 */
1834                 buffer[0] = 0xff;
1835                 buffer[1] = 0x01;
1836                 i2c_success = i2c_write(pipe_ctx, slave_address,
1837                                 buffer, sizeof(buffer));
1838                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1839                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1840                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1841                 if (!i2c_success)
1842                         /* Write failure */
1843                         ASSERT(i2c_success);
1844
1845                 /* Write offset 0x00 to 0x23 */
1846                 buffer[0] = 0x00;
1847                 buffer[1] = 0x23;
1848                 i2c_success = i2c_write(pipe_ctx, slave_address,
1849                                 buffer, sizeof(buffer));
1850                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1851                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1852                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1853                 if (!i2c_success)
1854                         /* Write failure */
1855                         ASSERT(i2c_success);
1856
1857                 /* Write offset 0xff to 0x00 */
1858                 buffer[0] = 0xff;
1859                 buffer[1] = 0x00;
1860                 i2c_success = i2c_write(pipe_ctx, slave_address,
1861                                 buffer, sizeof(buffer));
1862                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
1863                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
1864                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1865                 if (!i2c_success)
1866                         /* Write failure */
1867                         ASSERT(i2c_success);
1868         }
1869 }
1870
1871 static void write_i2c_redriver_setting(
1872                 struct pipe_ctx *pipe_ctx,
1873                 bool is_over_340mhz)
1874 {
1875         uint8_t slave_address = (0xF0 >> 1);
1876         uint8_t buffer[16];
1877         bool i2c_success = false;
1878         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1879
1880         memset(&buffer, 0, sizeof(buffer));
1881
1882         // Program Slave Address for tuning single integrity
1883         buffer[3] = 0x4E;
1884         buffer[4] = 0x4E;
1885         buffer[5] = 0x4E;
1886         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
1887
1888         i2c_success = i2c_write(pipe_ctx, slave_address,
1889                                         buffer, sizeof(buffer));
1890         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
1891                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
1892                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
1893                 i2c_success = %d\n",
1894                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
1895
1896         if (!i2c_success)
1897                 /* Write failure */
1898                 ASSERT(i2c_success);
1899 }
1900
1901 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1902 {
1903         struct dc_stream_state *stream = pipe_ctx->stream;
1904         struct dc_link *link = stream->sink->link;
1905         enum dc_color_depth display_color_depth;
1906         enum engine_id eng_id;
1907         struct ext_hdmi_settings settings = {0};
1908         bool is_over_340mhz = false;
1909         bool is_vga_mode = (stream->timing.h_addressable == 640)
1910                         && (stream->timing.v_addressable == 480);
1911
1912         if (stream->phy_pix_clk == 0)
1913                 stream->phy_pix_clk = stream->timing.pix_clk_khz;
1914         if (stream->phy_pix_clk > 340000)
1915                 is_over_340mhz = true;
1916
1917         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
1918                 unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
1919                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1920                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1921                         /* DP159, Retimer settings */
1922                         eng_id = pipe_ctx->stream_res.stream_enc->id;
1923
1924                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
1925                                 write_i2c_retimer_setting(pipe_ctx,
1926                                                 is_vga_mode, is_over_340mhz, &settings);
1927                         } else {
1928                                 write_i2c_default_retimer_setting(pipe_ctx,
1929                                                 is_vga_mode, is_over_340mhz);
1930                         }
1931                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
1932                         /* PI3EQX1204, Redriver settings */
1933                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
1934                 }
1935         }
1936
1937         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1938                 dal_ddc_service_write_scdc_data(
1939                         stream->sink->link->ddc,
1940                         stream->phy_pix_clk,
1941                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
1942
1943         memset(&stream->sink->link->cur_link_settings, 0,
1944                         sizeof(struct dc_link_settings));
1945
1946         display_color_depth = stream->timing.display_color_depth;
1947         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1948                 display_color_depth = COLOR_DEPTH_888;
1949
1950         link->link_enc->funcs->enable_tmds_output(
1951                         link->link_enc,
1952                         pipe_ctx->clock_source->id,
1953                         display_color_depth,
1954                         pipe_ctx->stream->signal,
1955                         stream->phy_pix_clk);
1956
1957         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
1958                 dal_ddc_service_read_scdc_data(link->ddc);
1959 }
1960
1961 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
1962 {
1963         struct dc_stream_state *stream = pipe_ctx->stream;
1964         struct dc_link *link = stream->sink->link;
1965
1966         if (stream->phy_pix_clk == 0)
1967                 stream->phy_pix_clk = stream->timing.pix_clk_khz;
1968
1969         memset(&stream->sink->link->cur_link_settings, 0,
1970                         sizeof(struct dc_link_settings));
1971
1972         link->link_enc->funcs->enable_lvds_output(
1973                         link->link_enc,
1974                         pipe_ctx->clock_source->id,
1975                         stream->phy_pix_clk);
1976
1977 }
1978
1979 /****************************enable_link***********************************/
1980 static enum dc_status enable_link(
1981                 struct dc_state *state,
1982                 struct pipe_ctx *pipe_ctx)
1983 {
1984         enum dc_status status = DC_ERROR_UNEXPECTED;
1985         switch (pipe_ctx->stream->signal) {
1986         case SIGNAL_TYPE_DISPLAY_PORT:
1987                 status = enable_link_dp(state, pipe_ctx);
1988                 break;
1989         case SIGNAL_TYPE_EDP:
1990                 status = enable_link_edp(state, pipe_ctx);
1991                 break;
1992         case SIGNAL_TYPE_DISPLAY_PORT_MST:
1993                 status = enable_link_dp_mst(state, pipe_ctx);
1994                 msleep(200);
1995                 break;
1996         case SIGNAL_TYPE_DVI_SINGLE_LINK:
1997         case SIGNAL_TYPE_DVI_DUAL_LINK:
1998         case SIGNAL_TYPE_HDMI_TYPE_A:
1999                 enable_link_hdmi(pipe_ctx);
2000                 status = DC_OK;
2001                 break;
2002         case SIGNAL_TYPE_LVDS:
2003                 enable_link_lvds(pipe_ctx);
2004                 status = DC_OK;
2005                 break;
2006         case SIGNAL_TYPE_VIRTUAL:
2007                 status = DC_OK;
2008                 break;
2009         default:
2010                 break;
2011         }
2012
2013         return status;
2014 }
2015
2016 static void disable_link(struct dc_link *link, enum signal_type signal)
2017 {
2018         /*
2019          * TODO: implement call for dp_set_hw_test_pattern
2020          * it is needed for compliance testing
2021          */
2022
2023         /* here we need to specify that encoder output settings
2024          * need to be calculated as for the set mode,
2025          * it will lead to querying dynamic link capabilities
2026          * which should be done before enable output */
2027
2028         if (dc_is_dp_signal(signal)) {
2029                 /* SST DP, eDP */
2030                 if (dc_is_dp_sst_signal(signal))
2031                         dp_disable_link_phy(link, signal);
2032                 else
2033                         dp_disable_link_phy_mst(link, signal);
2034         } else
2035                 link->link_enc->funcs->disable_output(link->link_enc, signal);
2036 }
2037
2038 static bool dp_active_dongle_validate_timing(
2039                 const struct dc_crtc_timing *timing,
2040                 const struct dpcd_caps *dpcd_caps)
2041 {
2042         unsigned int required_pix_clk = timing->pix_clk_khz;
2043         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2044
2045         switch (dpcd_caps->dongle_type) {
2046         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2047         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2048         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2049                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2050                         return true;
2051                 else
2052                         return false;
2053         default:
2054                 break;
2055         }
2056
2057         if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2058                 dongle_caps->extendedCapValid == false)
2059                 return true;
2060
2061         /* Check Pixel Encoding */
2062         switch (timing->pixel_encoding) {
2063         case PIXEL_ENCODING_RGB:
2064         case PIXEL_ENCODING_YCBCR444:
2065                 break;
2066         case PIXEL_ENCODING_YCBCR422:
2067                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2068                         return false;
2069                 break;
2070         case PIXEL_ENCODING_YCBCR420:
2071                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2072                         return false;
2073                 break;
2074         default:
2075                 /* Invalid Pixel Encoding*/
2076                 return false;
2077         }
2078
2079
2080         /* Check Color Depth and Pixel Clock */
2081         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2082                 required_pix_clk /= 2;
2083         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2084                 required_pix_clk = required_pix_clk * 2 / 3;
2085
2086         switch (timing->display_color_depth) {
2087         case COLOR_DEPTH_666:
2088         case COLOR_DEPTH_888:
2089                 /*888 and 666 should always be supported*/
2090                 break;
2091         case COLOR_DEPTH_101010:
2092                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2093                         return false;
2094                 required_pix_clk = required_pix_clk * 10 / 8;
2095                 break;
2096         case COLOR_DEPTH_121212:
2097                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2098                         return false;
2099                 required_pix_clk = required_pix_clk * 12 / 8;
2100                 break;
2101
2102         case COLOR_DEPTH_141414:
2103         case COLOR_DEPTH_161616:
2104         default:
2105                 /* These color depths are currently not supported */
2106                 return false;
2107         }
2108
2109         if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
2110                 return false;
2111
2112         return true;
2113 }
2114
2115 enum dc_status dc_link_validate_mode_timing(
2116                 const struct dc_stream_state *stream,
2117                 struct dc_link *link,
2118                 const struct dc_crtc_timing *timing)
2119 {
2120         uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
2121         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2122
2123         /* A hack to avoid failing any modes for EDID override feature on
2124          * topology change such as lower quality cable for DP or different dongle
2125          */
2126         if (link->remote_sinks[0])
2127                 return DC_OK;
2128
2129         /* Passive Dongle */
2130         if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
2131                 return DC_EXCEED_DONGLE_CAP;
2132
2133         /* Active Dongle*/
2134         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2135                 return DC_EXCEED_DONGLE_CAP;
2136
2137         switch (stream->signal) {
2138         case SIGNAL_TYPE_EDP:
2139         case SIGNAL_TYPE_DISPLAY_PORT:
2140                 if (!dp_validate_mode_timing(
2141                                 link,
2142                                 timing))
2143                         return DC_NO_DP_LINK_BANDWIDTH;
2144                 break;
2145
2146         default:
2147                 break;
2148         }
2149
2150         return DC_OK;
2151 }
2152
2153 int dc_link_get_backlight_level(const struct dc_link *link)
2154 {
2155         struct abm *abm = link->ctx->dc->res_pool->abm;
2156
2157         if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2158                 return DC_ERROR_UNEXPECTED;
2159
2160         return (int) abm->funcs->get_current_backlight(abm);
2161 }
2162
2163 bool dc_link_set_backlight_level(const struct dc_link *link,
2164                 uint32_t backlight_pwm_u16_16,
2165                 uint32_t frame_ramp,
2166                 const struct dc_stream_state *stream)
2167 {
2168         struct dc  *core_dc = link->ctx->dc;
2169         struct abm *abm = core_dc->res_pool->abm;
2170         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2171         unsigned int controller_id = 0;
2172         bool use_smooth_brightness = true;
2173         int i;
2174         DC_LOGGER_INIT(link->ctx->logger);
2175
2176         if ((dmcu == NULL) ||
2177                 (abm == NULL) ||
2178                 (abm->funcs->set_backlight_level_pwm == NULL))
2179                 return false;
2180
2181         if (stream)
2182                 ((struct dc_stream_state *)stream)->bl_pwm_level =
2183                                 backlight_pwm_u16_16;
2184
2185         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2186
2187         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2188                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2189
2190         if (dc_is_embedded_signal(link->connector_signal)) {
2191                 for (i = 0; i < MAX_PIPES; i++) {
2192                         if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
2193                                 if (core_dc->current_state->res_ctx.
2194                                                 pipe_ctx[i].stream->sink->link
2195                                                 == link)
2196                                         /* DMCU -1 for all controller id values,
2197                                          * therefore +1 here
2198                                          */
2199                                         controller_id =
2200                                                 core_dc->current_state->
2201                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2202                                                 1;
2203                         }
2204                 }
2205                 abm->funcs->set_backlight_level_pwm(
2206                                 abm,
2207                                 backlight_pwm_u16_16,
2208                                 frame_ramp,
2209                                 controller_id,
2210                                 use_smooth_brightness);
2211         }
2212
2213         return true;
2214 }
2215
2216 bool dc_link_set_abm_disable(const struct dc_link *link)
2217 {
2218         struct dc  *core_dc = link->ctx->dc;
2219         struct abm *abm = core_dc->res_pool->abm;
2220
2221         if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
2222                 return false;
2223
2224         abm->funcs->set_abm_immediate_disable(abm);
2225
2226         return true;
2227 }
2228
2229 bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
2230 {
2231         struct dc  *core_dc = link->ctx->dc;
2232         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2233
2234         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_enabled)
2235                 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
2236
2237         return true;
2238 }
2239
2240 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2241 {
2242         return &link->link_status;
2243 }
2244
2245 void core_link_resume(struct dc_link *link)
2246 {
2247         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2248                 program_hpd_filter(link);
2249 }
2250
2251 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2252 {
2253         struct dc_link_settings *link_settings =
2254                         &stream->sink->link->cur_link_settings;
2255         uint32_t link_rate_in_mbps =
2256                         link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
2257         struct fixed31_32 mbps = dc_fixpt_from_int(
2258                         link_rate_in_mbps * link_settings->lane_count);
2259
2260         return dc_fixpt_div_int(mbps, 54);
2261 }
2262
2263 static int get_color_depth(enum dc_color_depth color_depth)
2264 {
2265         switch (color_depth) {
2266         case COLOR_DEPTH_666: return 6;
2267         case COLOR_DEPTH_888: return 8;
2268         case COLOR_DEPTH_101010: return 10;
2269         case COLOR_DEPTH_121212: return 12;
2270         case COLOR_DEPTH_141414: return 14;
2271         case COLOR_DEPTH_161616: return 16;
2272         default: return 0;
2273         }
2274 }
2275
2276 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2277 {
2278         uint32_t bpc;
2279         uint64_t kbps;
2280         struct fixed31_32 peak_kbps;
2281         uint32_t numerator;
2282         uint32_t denominator;
2283
2284         bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2285         kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
2286
2287         /*
2288          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2289          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2290          * common multiplier to render an integer PBN for all link rate/lane
2291          * counts combinations
2292          * calculate
2293          * peak_kbps *= (1006/1000)
2294          * peak_kbps *= (64/54)
2295          * peak_kbps *= 8    convert to bytes
2296          */
2297
2298         numerator = 64 * PEAK_FACTOR_X1000;
2299         denominator = 54 * 8 * 1000 * 1000;
2300         kbps *= numerator;
2301         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2302
2303         return peak_kbps;
2304 }
2305
2306 static void update_mst_stream_alloc_table(
2307         struct dc_link *link,
2308         struct stream_encoder *stream_enc,
2309         const struct dp_mst_stream_allocation_table *proposed_table)
2310 {
2311         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2312                         { 0 } };
2313         struct link_mst_stream_allocation *dc_alloc;
2314
2315         int i;
2316         int j;
2317
2318         /* if DRM proposed_table has more than one new payload */
2319         ASSERT(proposed_table->stream_count -
2320                         link->mst_stream_alloc_table.stream_count < 2);
2321
2322         /* copy proposed_table to link, add stream encoder */
2323         for (i = 0; i < proposed_table->stream_count; i++) {
2324
2325                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2326                         dc_alloc =
2327                         &link->mst_stream_alloc_table.stream_allocations[j];
2328
2329                         if (dc_alloc->vcp_id ==
2330                                 proposed_table->stream_allocations[i].vcp_id) {
2331
2332                                 work_table[i] = *dc_alloc;
2333                                 break; /* exit j loop */
2334                         }
2335                 }
2336
2337                 /* new vcp_id */
2338                 if (j == link->mst_stream_alloc_table.stream_count) {
2339                         work_table[i].vcp_id =
2340                                 proposed_table->stream_allocations[i].vcp_id;
2341                         work_table[i].slot_count =
2342                                 proposed_table->stream_allocations[i].slot_count;
2343                         work_table[i].stream_enc = stream_enc;
2344                 }
2345         }
2346
2347         /* update link->mst_stream_alloc_table with work_table */
2348         link->mst_stream_alloc_table.stream_count =
2349                         proposed_table->stream_count;
2350         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2351                 link->mst_stream_alloc_table.stream_allocations[i] =
2352                                 work_table[i];
2353 }
2354
2355 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2356  * because stream_encoder is not exposed to dm
2357  */
2358 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2359 {
2360         struct dc_stream_state *stream = pipe_ctx->stream;
2361         struct dc_link *link = stream->sink->link;
2362         struct link_encoder *link_encoder = link->link_enc;
2363         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2364         struct dp_mst_stream_allocation_table proposed_table = {0};
2365         struct fixed31_32 avg_time_slots_per_mtp;
2366         struct fixed31_32 pbn;
2367         struct fixed31_32 pbn_per_slot;
2368         uint8_t i;
2369         DC_LOGGER_INIT(link->ctx->logger);
2370
2371         /* enable_link_dp_mst already check link->enabled_stream_count
2372          * and stream is in link->stream[]. This is called during set mode,
2373          * stream_enc is available.
2374          */
2375
2376         /* get calculate VC payload for stream: stream_alloc */
2377         if (dm_helpers_dp_mst_write_payload_allocation_table(
2378                 stream->ctx,
2379                 stream,
2380                 &proposed_table,
2381                 true)) {
2382                 update_mst_stream_alloc_table(
2383                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2384         }
2385         else
2386                 DC_LOG_WARNING("Failed to update"
2387                                 "MST allocation table for"
2388                                 "pipe idx:%d\n",
2389                                 pipe_ctx->pipe_idx);
2390
2391         DC_LOG_MST("%s  "
2392                         "stream_count: %d: \n ",
2393                         __func__,
2394                         link->mst_stream_alloc_table.stream_count);
2395
2396         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2397                 DC_LOG_MST("stream_enc[%d]: %p      "
2398                 "stream[%d].vcp_id: %d      "
2399                 "stream[%d].slot_count: %d\n",
2400                 i,
2401                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2402                 i,
2403                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2404                 i,
2405                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2406         }
2407
2408         ASSERT(proposed_table.stream_count > 0);
2409
2410         /* program DP source TX for payload */
2411         link_encoder->funcs->update_mst_stream_allocation_table(
2412                 link_encoder,
2413                 &link->mst_stream_alloc_table);
2414
2415         /* send down message */
2416         dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2417                         stream->ctx,
2418                         stream);
2419
2420         dm_helpers_dp_mst_send_payload_allocation(
2421                         stream->ctx,
2422                         stream,
2423                         true);
2424
2425         /* slot X.Y for only current stream */
2426         pbn_per_slot = get_pbn_per_slot(stream);
2427         pbn = get_pbn_from_timing(pipe_ctx);
2428         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2429
2430         stream_encoder->funcs->set_mst_bandwidth(
2431                 stream_encoder,
2432                 avg_time_slots_per_mtp);
2433
2434         return DC_OK;
2435
2436 }
2437
2438 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2439 {
2440         struct dc_stream_state *stream = pipe_ctx->stream;
2441         struct dc_link *link = stream->sink->link;
2442         struct link_encoder *link_encoder = link->link_enc;
2443         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2444         struct dp_mst_stream_allocation_table proposed_table = {0};
2445         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2446         uint8_t i;
2447         bool mst_mode = (link->type == dc_connection_mst_branch);
2448         DC_LOGGER_INIT(link->ctx->logger);
2449
2450         /* deallocate_mst_payload is called before disable link. When mode or
2451          * disable/enable monitor, new stream is created which is not in link
2452          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2453          * should not done. For new mode set, map_resources will get engine
2454          * for new stream, so stream_enc->id should be validated until here.
2455          */
2456
2457         /* slot X.Y */
2458         stream_encoder->funcs->set_mst_bandwidth(
2459                 stream_encoder,
2460                 avg_time_slots_per_mtp);
2461
2462         /* TODO: which component is responsible for remove payload table? */
2463         if (mst_mode) {
2464                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2465                                 stream->ctx,
2466                                 stream,
2467                                 &proposed_table,
2468                                 false)) {
2469
2470                         update_mst_stream_alloc_table(
2471                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2472                 }
2473                 else {
2474                                 DC_LOG_WARNING("Failed to update"
2475                                                 "MST allocation table for"
2476                                                 "pipe idx:%d\n",
2477                                                 pipe_ctx->pipe_idx);
2478                 }
2479         }
2480
2481         DC_LOG_MST("%s"
2482                         "stream_count: %d: ",
2483                         __func__,
2484                         link->mst_stream_alloc_table.stream_count);
2485
2486         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2487                 DC_LOG_MST("stream_enc[%d]: %p      "
2488                 "stream[%d].vcp_id: %d      "
2489                 "stream[%d].slot_count: %d\n",
2490                 i,
2491                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2492                 i,
2493                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2494                 i,
2495                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2496         }
2497
2498         link_encoder->funcs->update_mst_stream_allocation_table(
2499                 link_encoder,
2500                 &link->mst_stream_alloc_table);
2501
2502         if (mst_mode) {
2503                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2504                         stream->ctx,
2505                         stream);
2506
2507                 dm_helpers_dp_mst_send_payload_allocation(
2508                         stream->ctx,
2509                         stream,
2510                         false);
2511         }
2512
2513         return DC_OK;
2514 }
2515
2516 void core_link_enable_stream(
2517                 struct dc_state *state,
2518                 struct pipe_ctx *pipe_ctx)
2519 {
2520         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2521         struct dc_stream_state *stream = pipe_ctx->stream;
2522         enum dc_status status;
2523         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2524
2525         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) {
2526                 stream->sink->link->link_enc->funcs->setup(
2527                         stream->sink->link->link_enc,
2528                         pipe_ctx->stream->signal);
2529                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
2530                         pipe_ctx->stream_res.stream_enc,
2531                         pipe_ctx->stream_res.tg->inst,
2532                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
2533         }
2534
2535         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2536                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
2537                         pipe_ctx->stream_res.stream_enc,
2538                         &stream->timing,
2539                         stream->output_color_space);
2540
2541         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2542                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
2543                         pipe_ctx->stream_res.stream_enc,
2544                         &stream->timing,
2545                         stream->phy_pix_clk,
2546                         pipe_ctx->stream_res.audio != NULL);
2547
2548         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
2549                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
2550                         pipe_ctx->stream_res.stream_enc,
2551                         &stream->timing,
2552                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
2553                         true : false);
2554
2555         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
2556                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
2557                         pipe_ctx->stream_res.stream_enc,
2558                         &stream->timing);
2559
2560         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
2561                 resource_build_info_frame(pipe_ctx);
2562                 core_dc->hwss.update_info_frame(pipe_ctx);
2563
2564                 /* eDP lit up by bios already, no need to enable again. */
2565                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2566                                 pipe_ctx->stream->apply_edp_fast_boot_optimization) {
2567                         pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2568                         pipe_ctx->stream->dpms_off = false;
2569                         return;
2570                 }
2571
2572                 if (pipe_ctx->stream->dpms_off)
2573                         return;
2574
2575                 status = enable_link(state, pipe_ctx);
2576
2577                 if (status != DC_OK) {
2578                         DC_LOG_WARNING("enabling link %u failed: %d\n",
2579                         pipe_ctx->stream->sink->link->link_index,
2580                         status);
2581
2582                         /* Abort stream enable *unless* the failure was due to
2583                          * DP link training - some DP monitors will recover and
2584                          * show the stream anyway. But MST displays can't proceed
2585                          * without link training.
2586                          */
2587                         if (status != DC_FAIL_DP_LINK_TRAINING ||
2588                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2589                                 BREAK_TO_DEBUGGER();
2590                                 return;
2591                         }
2592                 }
2593
2594                 core_dc->hwss.enable_audio_stream(pipe_ctx);
2595
2596                 /* turn off otg test pattern if enable */
2597                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2598                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2599                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2600                                         COLOR_DEPTH_UNDEFINED);
2601
2602                 core_dc->hwss.enable_stream(pipe_ctx);
2603
2604                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2605                         allocate_mst_payload(pipe_ctx);
2606
2607                 core_dc->hwss.unblank_stream(pipe_ctx,
2608                         &pipe_ctx->stream->sink->link->cur_link_settings);
2609
2610                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2611                         enable_stream_features(pipe_ctx);
2612
2613                 dc_link_set_backlight_level(pipe_ctx->stream->sink->link,
2614                                 pipe_ctx->stream->bl_pwm_level,
2615                                 0,
2616                                 pipe_ctx->stream);
2617         }
2618
2619 }
2620
2621 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
2622 {
2623         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2624
2625         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2626                 deallocate_mst_payload(pipe_ctx);
2627
2628         core_dc->hwss.blank_stream(pipe_ctx);
2629
2630         core_dc->hwss.disable_stream(pipe_ctx, option);
2631
2632         disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
2633 }
2634
2635 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2636 {
2637         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2638
2639         if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2640                 return;
2641
2642         core_dc->hwss.set_avmute(pipe_ctx, enable);
2643 }
2644
2645 /**
2646  *****************************************************************************
2647  *  Function: dc_link_enable_hpd_filter
2648  *
2649  *  @brief
2650  *     If enable is true, programs HPD filter on associated HPD line using
2651  *     delay_on_disconnect/delay_on_connect values dependent on
2652  *     link->connector_signal
2653  *
2654  *     If enable is false, programs HPD filter on associated HPD line with no
2655  *     delays on connect or disconnect
2656  *
2657  *  @param [in] link: pointer to the dc link
2658  *  @param [in] enable: boolean specifying whether to enable hbd
2659  *****************************************************************************
2660  */
2661 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
2662 {
2663         struct gpio *hpd;
2664
2665         if (enable) {
2666                 link->is_hpd_filter_disabled = false;
2667                 program_hpd_filter(link);
2668         } else {
2669                 link->is_hpd_filter_disabled = true;
2670                 /* Obtain HPD handle */
2671                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
2672
2673                 if (!hpd)
2674                         return;
2675
2676                 /* Setup HPD filtering */
2677                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
2678                         struct gpio_hpd_config config;
2679
2680                         config.delay_on_connect = 0;
2681                         config.delay_on_disconnect = 0;
2682
2683                         dal_irq_setup_hpd_filter(hpd, &config);
2684
2685                         dal_gpio_close(hpd);
2686                 } else {
2687                         ASSERT_CRITICAL(false);
2688                 }
2689                 /* Release HPD handle */
2690                 dal_gpio_destroy_irq(&hpd);
2691         }
2692 }
2693