drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atomfirmware.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48 #include "dce/dmub_psr.h"
  49 #include "dmub/dmub_srv.h"
  50 #include "inc/hw/panel_cntl.h"
  51 #include "inc/link_enc_cfg.h"
  52 #include "inc/link_dpcd.h"
  53
  54 #include "dc/dcn30/dcn30_vpg.h"
  55
  56 #define DC_LOGGER_INIT(logger)
  57
  58 #define LINK_INFO(...) \
  59         DC_LOG_HW_HOTPLUG(  \
  60                 __VA_ARGS__)
  61
  62 #define RETIMER_REDRIVER_INFO(...) \
  63         DC_LOG_RETIMER_REDRIVER(  \
  64                 __VA_ARGS__)
  65
  66 /*******************************************************************************
  67  * Private functions
  68  ******************************************************************************/
  69 #if defined(CONFIG_DRM_AMD_DC_DCN)
  70 static bool add_dp_hpo_link_encoder_to_link(struct dc_link *link)
  71 {
  72         struct hpo_dp_link_encoder *enc = resource_get_unused_hpo_dp_link_encoder(
  73                                         link->dc->res_pool);
  74
  75         if (!link->hpo_dp_link_enc && enc) {
  76                 link->hpo_dp_link_enc = enc;
  77                 link->hpo_dp_link_enc->transmitter = link->link_enc->transmitter;
  78                 link->hpo_dp_link_enc->hpd_source = link->link_enc->hpd_source;
  79         }
  80
  81         return (link->hpo_dp_link_enc != NULL);
  82 }
  83
  84 static void remove_dp_hpo_link_encoder_from_link(struct dc_link *link)
  85 {
  86         if (link->hpo_dp_link_enc) {
  87                 link->hpo_dp_link_enc->hpd_source = HPD_SOURCEID_UNKNOWN;
  88                 link->hpo_dp_link_enc->transmitter = TRANSMITTER_UNKNOWN;
  89                 link->hpo_dp_link_enc = NULL;
  90         }
  91 }
  92 #endif
  93
  94 static void dc_link_destruct(struct dc_link *link)
  95 {
  96         int i;
  97
  98         if (link->hpd_gpio) {
  99                 dal_gpio_destroy_irq(&link->hpd_gpio);
 100                 link->hpd_gpio = NULL;
 101         }
 102
 103         if (link->ddc)
 104                 dal_ddc_service_destroy(&link->ddc);
 105
 106         if (link->panel_cntl)
 107                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
 108
 109         if (link->link_enc) {
 110                 /* Update link encoder resource tracking variables. These are used for
 111                  * the dynamic assignment of link encoders to streams. Virtual links
 112                  * are not assigned encoder resources on creation.
 113                  */
 114                 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
 115                         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
 116                         link->dc->res_pool->dig_link_enc_count--;
 117                 }
 118                 link->link_enc->funcs->destroy(&link->link_enc);
 119         }
 120
 121 #if defined(CONFIG_DRM_AMD_DC_DCN)
 122         if (link->hpo_dp_link_enc) {
 123                 remove_dp_hpo_link_encoder_from_link(link);
 124         }
 125 #endif
 126
 127         if (link->local_sink)
 128                 dc_sink_release(link->local_sink);
 129
 130         for (i = 0; i < link->sink_count; ++i)
 131                 dc_sink_release(link->remote_sinks[i]);
 132 }
 133
 134 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 135                           struct graphics_object_id link_id,
 136                           struct gpio_service *gpio_service)
 137 {
 138         enum bp_result bp_result;
 139         struct graphics_object_hpd_info hpd_info;
 140         struct gpio_pin_info pin_info;
 141
 142         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 143                 return NULL;
 144
 145         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 146                 hpd_info.hpd_int_gpio_uid, &pin_info);
 147
 148         if (bp_result != BP_RESULT_OK) {
 149                 ASSERT(bp_result == BP_RESULT_NORECORD);
 150                 return NULL;
 151         }
 152
 153         return dal_gpio_service_create_irq(gpio_service,
 154                                            pin_info.offset,
 155                                            pin_info.mask);
 156 }
 157
 158 /*
 159  *  Function: program_hpd_filter
 160  *
 161  *  @brief
 162  *     Programs HPD filter on associated HPD line
 163  *
 164  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 165  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 166  *
 167  *  @return
 168  *     true on success, false otherwise
 169  */
 170 static bool program_hpd_filter(const struct dc_link *link)
 171 {
 172         bool result = false;
 173         struct gpio *hpd;
 174         int delay_on_connect_in_ms = 0;
 175         int delay_on_disconnect_in_ms = 0;
 176
 177         if (link->is_hpd_filter_disabled)
 178                 return false;
 179         /* Verify feature is supported */
 180         switch (link->connector_signal) {
 181         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 182         case SIGNAL_TYPE_DVI_DUAL_LINK:
 183         case SIGNAL_TYPE_HDMI_TYPE_A:
 184                 /* Program hpd filter */
 185                 delay_on_connect_in_ms = 500;
 186                 delay_on_disconnect_in_ms = 100;
 187                 break;
 188         case SIGNAL_TYPE_DISPLAY_PORT:
 189         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 190                 /* Program hpd filter to allow DP signal to settle */
 191                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 192                  * only 100ms on DELL U2413
 193                  * 0: some passive dongle still show aux mode instead of i2c
 194                  * 20-50: not enough to hide bouncing HPD with passive dongle.
 195                  * also see intermittent i2c read issues.
 196                  */
 197                 delay_on_connect_in_ms = 80;
 198                 delay_on_disconnect_in_ms = 0;
 199                 break;
 200         case SIGNAL_TYPE_LVDS:
 201         case SIGNAL_TYPE_EDP:
 202         default:
 203                 /* Don't program hpd filter */
 204                 return false;
 205         }
 206
 207         /* Obtain HPD handle */
 208         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 209                            link->ctx->gpio_service);
 210
 211         if (!hpd)
 212                 return result;
 213
 214         /* Setup HPD filtering */
 215         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 216                 struct gpio_hpd_config config;
 217
 218                 config.delay_on_connect = delay_on_connect_in_ms;
 219                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 220
 221                 dal_irq_setup_hpd_filter(hpd, &config);
 222
 223                 dal_gpio_close(hpd);
 224
 225                 result = true;
 226         } else {
 227                 ASSERT_CRITICAL(false);
 228         }
 229
 230         /* Release HPD handle */
 231         dal_gpio_destroy_irq(&hpd);
 232
 233         return result;
 234 }
 235
 236 bool dc_link_wait_for_t12(struct dc_link *link)
 237 {
 238         if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 239                 link->dc->hwss.edp_wait_for_T12(link);
 240
 241                 return true;
 242         }
 243
 244         return false;
 245 }
 246
 247 /**
 248  * dc_link_detect_sink() - Determine if there is a sink connected
 249  *
 250  * @link: pointer to the dc link
 251  * @type: Returned connection type
 252  * Does not detect downstream devices, such as MST sinks
 253  * or display connected through active dongles
 254  */
 255 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 256 {
 257         uint32_t is_hpd_high = 0;
 258         struct gpio *hpd_pin;
 259
 260         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 261                 *type = dc_connection_single;
 262                 return true;
 263         }
 264
 265         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 266                 /*in case it is not on*/
 267                 link->dc->hwss.edp_power_control(link, true);
 268                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 269         }
 270
 271         /* Link may not have physical HPD pin. */
 272         if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
 273                 if (link->is_hpd_pending || !link->hpd_status)
 274                         *type = dc_connection_none;
 275                 else
 276                         *type = dc_connection_single;
 277
 278                 return true;
 279         }
 280
 281         /* todo: may need to lock gpio access */
 282         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 283                                link->ctx->gpio_service);
 284         if (!hpd_pin)
 285                 goto hpd_gpio_failure;
 286
 287         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 288         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 289         dal_gpio_close(hpd_pin);
 290         dal_gpio_destroy_irq(&hpd_pin);
 291
 292         if (is_hpd_high) {
 293                 *type = dc_connection_single;
 294                 /* TODO: need to do the actual detection */
 295         } else {
 296                 *type = dc_connection_none;
 297         }
 298
 299         return true;
 300
 301 hpd_gpio_failure:
 302         return false;
 303 }
 304
 305 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 306 {
 307         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 308
 309         switch (sink_signal) {
 310         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 311         case SIGNAL_TYPE_DVI_DUAL_LINK:
 312         case SIGNAL_TYPE_HDMI_TYPE_A:
 313         case SIGNAL_TYPE_LVDS:
 314         case SIGNAL_TYPE_RGB:
 315                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 316                 break;
 317
 318         case SIGNAL_TYPE_DISPLAY_PORT:
 319         case SIGNAL_TYPE_EDP:
 320                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 321                 break;
 322
 323         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 324                 /* MST does not use I2COverAux, but there is the
 325                  * SPECIAL use case for "immediate dwnstrm device
 326                  * access" (EPR#370830).
 327                  */
 328                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 329                 break;
 330
 331         default:
 332                 break;
 333         }
 334
 335         return transaction_type;
 336 }
 337
 338 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 339                                               struct graphics_object_id downstream)
 340 {
 341         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 342                 switch (downstream.id) {
 343                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 344                         switch (encoder.id) {
 345                         case ENCODER_ID_INTERNAL_DAC1:
 346                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 347                         case ENCODER_ID_INTERNAL_DAC2:
 348                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 349                                 return SIGNAL_TYPE_RGB;
 350                         default:
 351                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 352                         }
 353                 break;
 354                 case CONNECTOR_ID_DUAL_LINK_DVII:
 355                 {
 356                         switch (encoder.id) {
 357                         case ENCODER_ID_INTERNAL_DAC1:
 358                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 359                         case ENCODER_ID_INTERNAL_DAC2:
 360                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 361                                 return SIGNAL_TYPE_RGB;
 362                         default:
 363                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 364                         }
 365                 }
 366                 break;
 367                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 368                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 369                 case CONNECTOR_ID_DUAL_LINK_DVID:
 370                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 371                 case CONNECTOR_ID_VGA:
 372                         return SIGNAL_TYPE_RGB;
 373                 case CONNECTOR_ID_HDMI_TYPE_A:
 374                         return SIGNAL_TYPE_HDMI_TYPE_A;
 375                 case CONNECTOR_ID_LVDS:
 376                         return SIGNAL_TYPE_LVDS;
 377                 case CONNECTOR_ID_DISPLAY_PORT:
 378                         return SIGNAL_TYPE_DISPLAY_PORT;
 379                 case CONNECTOR_ID_EDP:
 380                         return SIGNAL_TYPE_EDP;
 381                 default:
 382                         return SIGNAL_TYPE_NONE;
 383                 }
 384         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 385                 switch (downstream.id) {
 386                 case ENCODER_ID_EXTERNAL_NUTMEG:
 387                 case ENCODER_ID_EXTERNAL_TRAVIS:
 388                         return SIGNAL_TYPE_DISPLAY_PORT;
 389                 default:
 390                         return SIGNAL_TYPE_NONE;
 391                 }
 392         }
 393
 394         return SIGNAL_TYPE_NONE;
 395 }
 396
 397 /*
 398  * dc_link_is_dp_sink_present() - Check if there is a native DP
 399  * or passive DP-HDMI dongle connected
 400  */
 401 bool dc_link_is_dp_sink_present(struct dc_link *link)
 402 {
 403         enum gpio_result gpio_result;
 404         uint32_t clock_pin = 0;
 405         uint8_t retry = 0;
 406         struct ddc *ddc;
 407
 408         enum connector_id connector_id =
 409                 dal_graphics_object_id_get_connector_id(link->link_id);
 410
 411         bool present =
 412                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 413                 (connector_id == CONNECTOR_ID_EDP));
 414
 415         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 416
 417         if (!ddc) {
 418                 BREAK_TO_DEBUGGER();
 419                 return present;
 420         }
 421
 422         /* Open GPIO and set it to I2C mode */
 423         /* Note: this GpioMode_Input will be converted
 424          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 425          * which indicates we need additional delay
 426          */
 427
 428         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 429                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 430                 dal_ddc_close(ddc);
 431
 432                 return present;
 433         }
 434
 435         /*
 436          * Read GPIO: DP sink is present if both clock and data pins are zero
 437          *
 438          * [W/A] plug-unplug DP cable, sometimes customer board has
 439          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 440          * then monitor can't br light up. Add retry 3 times
 441          * But in real passive dongle, it need additional 3ms to detect
 442          */
 443         do {
 444                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 445                 ASSERT(gpio_result == GPIO_RESULT_OK);
 446                 if (clock_pin)
 447                         udelay(1000);
 448                 else
 449                         break;
 450         } while (retry++ < 3);
 451
 452         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 453
 454         dal_ddc_close(ddc);
 455
 456         return present;
 457 }
 458
 459 /*
 460  * @brief
 461  * Detect output sink type
 462  */
 463 static enum signal_type link_detect_sink(struct dc_link *link,
 464                                          enum dc_detect_reason reason)
 465 {
 466         enum signal_type result;
 467         struct graphics_object_id enc_id;
 468
 469         if (link->is_dig_mapping_flexible)
 470                 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
 471         else
 472                 enc_id = link->link_enc->id;
 473         result = get_basic_signal_type(enc_id, link->link_id);
 474
 475         /* Use basic signal type for link without physical connector. */
 476         if (link->ep_type != DISPLAY_ENDPOINT_PHY)
 477                 return result;
 478
 479         /* Internal digital encoder will detect only dongles
 480          * that require digital signal
 481          */
 482
 483         /* Detection mechanism is different
 484          * for different native connectors.
 485          * LVDS connector supports only LVDS signal;
 486          * PCIE is a bus slot, the actual connector needs to be detected first;
 487          * eDP connector supports only eDP signal;
 488          * HDMI should check straps for audio
 489          */
 490
 491         /* PCIE detects the actual connector on add-on board */
 492         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 493                 /* ZAZTODO implement PCIE add-on card detection */
 494         }
 495
 496         switch (link->link_id.id) {
 497         case CONNECTOR_ID_HDMI_TYPE_A: {
 498                 /* check audio support:
 499                  * if native HDMI is not supported, switch to DVI
 500                  */
 501                 struct audio_support *aud_support =
 502                                         &link->dc->res_pool->audio_support;
 503
 504                 if (!aud_support->hdmi_audio_native)
 505                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 506                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 507         }
 508         break;
 509         case CONNECTOR_ID_DISPLAY_PORT: {
 510                 /* DP HPD short pulse. Passive DP dongle will not
 511                  * have short pulse
 512                  */
 513                 if (reason != DETECT_REASON_HPDRX) {
 514                         /* Check whether DP signal detected: if not -
 515                          * we assume signal is DVI; it could be corrected
 516                          * to HDMI after dongle detection
 517                          */
 518                         if (!dm_helpers_is_dp_sink_present(link))
 519                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 520                 }
 521         }
 522         break;
 523         default:
 524         break;
 525         }
 526
 527         return result;
 528 }
 529
 530 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 531                                                                  struct audio_support *audio_support)
 532 {
 533         enum signal_type signal = SIGNAL_TYPE_NONE;
 534
 535         switch (dongle_type) {
 536         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 537                 if (audio_support->hdmi_audio_on_dongle)
 538                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 539                 else
 540                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 541                 break;
 542         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 543                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 544                 break;
 545         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 546                 if (audio_support->hdmi_audio_native)
 547                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 548                 else
 549                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 550                 break;
 551         default:
 552                 signal = SIGNAL_TYPE_NONE;
 553                 break;
 554         }
 555
 556         return signal;
 557 }
 558
 559 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 560                                                     struct display_sink_capability *sink_cap,
 561                                                     struct audio_support *audio_support)
 562 {
 563         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 564
 565         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 566                                                         audio_support);
 567 }
 568
 569 static void link_disconnect_sink(struct dc_link *link)
 570 {
 571         if (link->local_sink) {
 572                 dc_sink_release(link->local_sink);
 573                 link->local_sink = NULL;
 574         }
 575
 576         link->dpcd_sink_count = 0;
 577         //link->dpcd_caps.dpcd_rev.raw = 0;
 578 }
 579
 580 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 581 {
 582         dc_sink_release(link->local_sink);
 583         link->local_sink = prev_sink;
 584 }
 585
 586 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 587 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 588 {
 589         bool ret = false;
 590
 591         switch (signal) {
 592         case SIGNAL_TYPE_DISPLAY_PORT:
 593         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 594                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 595                 break;
 596         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 597         case SIGNAL_TYPE_DVI_DUAL_LINK:
 598         case SIGNAL_TYPE_HDMI_TYPE_A:
 599         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 600          * we can poll for bksv but some displays have an issue with this. Since its so rare
 601          * for a display to not be 1.4 capable, this assumtion is ok
 602          */
 603                 ret = true;
 604                 break;
 605         default:
 606                 break;
 607         }
 608         return ret;
 609 }
 610
 611 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 612 {
 613         bool ret = false;
 614
 615         switch (signal) {
 616         case SIGNAL_TYPE_DISPLAY_PORT:
 617         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 618                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 619                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 620                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 621                 break;
 622         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 623         case SIGNAL_TYPE_DVI_DUAL_LINK:
 624         case SIGNAL_TYPE_HDMI_TYPE_A:
 625                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 626                 break;
 627         default:
 628                 break;
 629         }
 630
 631         return ret;
 632 }
 633
 634 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 635 {
 636         struct hdcp_protection_message msg22;
 637         struct hdcp_protection_message msg14;
 638
 639         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 640         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 641         memset(link->hdcp_caps.rx_caps.raw, 0,
 642                 sizeof(link->hdcp_caps.rx_caps.raw));
 643
 644         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 645                         link->ddc->transaction_type ==
 646                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 647                         link->connector_signal == SIGNAL_TYPE_EDP) {
 648                 msg22.data = link->hdcp_caps.rx_caps.raw;
 649                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 650                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 651         } else {
 652                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 653                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 654                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 655         }
 656         msg22.version = HDCP_VERSION_22;
 657         msg22.link = HDCP_LINK_PRIMARY;
 658         msg22.max_retries = 5;
 659         dc_process_hdcp_msg(signal, link, &msg22);
 660
 661         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 662                 msg14.data = &link->hdcp_caps.bcaps.raw;
 663                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 664                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 665                 msg14.version = HDCP_VERSION_14;
 666                 msg14.link = HDCP_LINK_PRIMARY;
 667                 msg14.max_retries = 5;
 668
 669                 dc_process_hdcp_msg(signal, link, &msg14);
 670         }
 671
 672 }
 673 #endif
 674
 675 static void read_current_link_settings_on_detect(struct dc_link *link)
 676 {
 677         union lane_count_set lane_count_set = {0};
 678         uint8_t link_bw_set;
 679         uint8_t link_rate_set;
 680         uint32_t read_dpcd_retry_cnt = 10;
 681         enum dc_status status = DC_ERROR_UNEXPECTED;
 682         int i;
 683         union max_down_spread max_down_spread = {0};
 684
 685         // Read DPCD 00101h to find out the number of lanes currently set
 686         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 687                 status = core_link_read_dpcd(link,
 688                                              DP_LANE_COUNT_SET,
 689                                              &lane_count_set.raw,
 690                                              sizeof(lane_count_set));
 691                 /* First DPCD read after VDD ON can fail if the particular board
 692                  * does not have HPD pin wired correctly. So if DPCD read fails,
 693                  * which it should never happen, retry a few times. Target worst
 694                  * case scenario of 80 ms.
 695                  */
 696                 if (status == DC_OK) {
 697                         link->cur_link_settings.lane_count =
 698                                         lane_count_set.bits.LANE_COUNT_SET;
 699                         break;
 700                 }
 701
 702                 msleep(8);
 703         }
 704
 705         // Read DPCD 00100h to find if standard link rates are set
 706         core_link_read_dpcd(link, DP_LINK_BW_SET,
 707                             &link_bw_set, sizeof(link_bw_set));
 708
 709         if (link_bw_set == 0) {
 710                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 711                         /* If standard link rates are not being used,
 712                          * Read DPCD 00115h to find the edp link rate set used
 713                          */
 714                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 715                                             &link_rate_set, sizeof(link_rate_set));
 716
 717                         // edp_supported_link_rates_count = 0 for DP
 718                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 719                                 link->cur_link_settings.link_rate =
 720                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 721                                 link->cur_link_settings.link_rate_set = link_rate_set;
 722                                 link->cur_link_settings.use_link_rate_set = true;
 723                         }
 724                 } else {
 725                         // Link Rate not found. Seamless boot may not work.
 726                         ASSERT(false);
 727                 }
 728         } else {
 729                 link->cur_link_settings.link_rate = link_bw_set;
 730                 link->cur_link_settings.use_link_rate_set = false;
 731         }
 732         // Read DPCD 00003h to find the max down spread.
 733         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 734                             &max_down_spread.raw, sizeof(max_down_spread));
 735         link->cur_link_settings.link_spread =
 736                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 737                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 738 }
 739
 740 static bool detect_dp(struct dc_link *link,
 741                       struct display_sink_capability *sink_caps,
 742                       enum dc_detect_reason reason)
 743 {
 744         struct audio_support *audio_support = &link->dc->res_pool->audio_support;
 745
 746         sink_caps->signal = link_detect_sink(link, reason);
 747         sink_caps->transaction_type =
 748                 get_ddc_transaction_type(sink_caps->signal);
 749
 750         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 751                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 752                 if (!detect_dp_sink_caps(link))
 753                         return false;
 754                 if (is_mst_supported(link)) {
 755                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 756                         link->type = dc_connection_mst_branch;
 757
 758                         dal_ddc_service_set_transaction_type(link->ddc,
 759                                                              sink_caps->transaction_type);
 760
 761 #if defined(CONFIG_DRM_AMD_DC_DCN)
 762                         /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
 763                          * reports DSC support.
 764                          */
 765                         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
 766                                         link->type == dc_connection_mst_branch &&
 767                                         link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
 768                                         link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
 769                                         !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
 770                                 link->wa_flags.dpia_mst_dsc_always_on = true;
 771 #endif
 772
 773 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 774                         /* In case of fallback to SST when topology discovery below fails
 775                          * HDCP caps will be querried again later by the upper layer (caller
 776                          * of this function). */
 777                         query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
 778 #endif
 779                 }
 780
 781                 if (link->type != dc_connection_mst_branch &&
 782                                 is_dp_branch_device(link))
 783                         /* DP SST branch */
 784                         link->type = dc_connection_sst_branch;
 785         } else {
 786                 /* DP passive dongles */
 787                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 788                                                                 sink_caps,
 789                                                                 audio_support);
 790                 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 791                 link->dpcd_caps.dpcd_rev.raw = 0;
 792         }
 793
 794         return true;
 795 }
 796
 797 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 798 {
 799         if (old_edid->length != new_edid->length)
 800                 return false;
 801
 802         if (new_edid->length == 0)
 803                 return false;
 804
 805         return (memcmp(old_edid->raw_edid,
 806                        new_edid->raw_edid, new_edid->length) == 0);
 807 }
 808
 809 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 810 {
 811         /**
 812          * something is terribly wrong if time out is > 200ms. (5Hz)
 813          * 500 microseconds * 400 tries us 200 ms
 814          **/
 815         unsigned int sleep_time_in_microseconds = 500;
 816         unsigned int tries_allowed = 400;
 817         bool is_in_alt_mode;
 818         unsigned long long enter_timestamp;
 819         unsigned long long finish_timestamp;
 820         unsigned long long time_taken_in_ns;
 821         int tries_taken;
 822
 823         DC_LOGGER_INIT(link->ctx->logger);
 824
 825         if (!link->link_enc->funcs->is_in_alt_mode)
 826                 return true;
 827
 828         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 829         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 830
 831         if (is_in_alt_mode)
 832                 return true;
 833
 834         enter_timestamp = dm_get_timestamp(link->ctx);
 835
 836         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 837                 udelay(sleep_time_in_microseconds);
 838                 /* ask the link if alt mode is enabled, if so return ok */
 839                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 840                         finish_timestamp = dm_get_timestamp(link->ctx);
 841                         time_taken_in_ns =
 842                                 dm_get_elapse_time_in_ns(link->ctx,
 843                                                          finish_timestamp,
 844                                                          enter_timestamp);
 845                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 846                                        div_u64(time_taken_in_ns, 1000000));
 847                         return true;
 848                 }
 849         }
 850         finish_timestamp = dm_get_timestamp(link->ctx);
 851         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 852                                                     enter_timestamp);
 853         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 854                        div_u64(time_taken_in_ns, 1000000));
 855         return false;
 856 }
 857
 858 /*
 859  * dc_link_detect() - Detect if a sink is attached to a given link
 860  *
 861  * link->local_sink is created or destroyed as needed.
 862  *
 863  * This does not create remote sinks but will trigger DM
 864  * to start MST detection if a branch is detected.
 865  */
 866 static bool dc_link_detect_helper(struct dc_link *link,
 867                                   enum dc_detect_reason reason)
 868 {
 869         struct dc_sink_init_data sink_init_data = { 0 };
 870         struct display_sink_capability sink_caps = { 0 };
 871         uint32_t i;
 872         bool converter_disable_audio = false;
 873         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 874         bool same_edid = false;
 875         enum dc_edid_status edid_status;
 876         struct dc_context *dc_ctx = link->ctx;
 877         struct dc_sink *sink = NULL;
 878         struct dc_sink *prev_sink = NULL;
 879         struct dpcd_caps prev_dpcd_caps;
 880         enum dc_connection_type new_connection_type = dc_connection_none;
 881         enum dc_connection_type pre_connection_type = dc_connection_none;
 882         bool perform_dp_seamless_boot = false;
 883         const uint32_t post_oui_delay = 30; // 30ms
 884
 885         DC_LOGGER_INIT(link->ctx->logger);
 886
 887         if (dc_is_virtual_signal(link->connector_signal))
 888                 return false;
 889
 890         if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
 891                 link->connector_signal == SIGNAL_TYPE_EDP) &&
 892                 (!link->dc->config.allow_edp_hotplug_detection)) &&
 893                 link->local_sink) {
 894                 // need to re-write OUI and brightness in resume case
 895                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 896                         dpcd_set_source_specific_data(link);
 897                         msleep(post_oui_delay);
 898                         dc_link_set_default_brightness_aux(link);
 899                         //TODO: use cached
 900                 }
 901
 902                 return true;
 903         }
 904
 905         if (!dc_link_detect_sink(link, &new_connection_type)) {
 906                 BREAK_TO_DEBUGGER();
 907                 return false;
 908         }
 909
 910         prev_sink = link->local_sink;
 911         if (prev_sink) {
 912                 dc_sink_retain(prev_sink);
 913                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 914         }
 915
 916         link_disconnect_sink(link);
 917         if (new_connection_type != dc_connection_none) {
 918                 pre_connection_type = link->type;
 919                 link->type = new_connection_type;
 920                 link->link_state_valid = false;
 921
 922                 /* From Disconnected-to-Connected. */
 923                 switch (link->connector_signal) {
 924                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 925                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 926                         if (aud_support->hdmi_audio_native)
 927                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 928                         else
 929                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 930                         break;
 931                 }
 932
 933                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 934                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 935                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 936                         break;
 937                 }
 938
 939                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 940                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 941                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 942                         break;
 943                 }
 944
 945                 case SIGNAL_TYPE_LVDS: {
 946                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 947                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 948                         break;
 949                 }
 950
 951                 case SIGNAL_TYPE_EDP: {
 952                         read_current_link_settings_on_detect(link);
 953
 954                         detect_edp_sink_caps(link);
 955                         read_current_link_settings_on_detect(link);
 956                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 957                         sink_caps.signal = SIGNAL_TYPE_EDP;
 958                         break;
 959                 }
 960
 961                 case SIGNAL_TYPE_DISPLAY_PORT: {
 962                         /* wa HPD high coming too early*/
 963                         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
 964                             link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 965                                 /* if alt mode times out, return false */
 966                                 if (!wait_for_entering_dp_alt_mode(link))
 967                                         return false;
 968                         }
 969
 970                         if (!detect_dp(link, &sink_caps, reason)) {
 971                                 if (prev_sink)
 972                                         dc_sink_release(prev_sink);
 973                                 return false;
 974                         }
 975
 976 #if defined(CONFIG_DRM_AMD_DC_DCN)
 977                         if (dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING)
 978                                 add_dp_hpo_link_encoder_to_link(link);
 979 #endif
 980
 981                         if (link->type == dc_connection_mst_branch) {
 982                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 983                                           link->link_index);
 984                                 /* Need to setup mst link_cap struct here
 985                                  * otherwise dc_link_detect() will leave mst link_cap
 986                                  * empty which leads to allocate_mst_payload() has "0"
 987                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 988                                  */
 989                                 dp_verify_mst_link_cap(link);
 990
 991                                 /*
 992                                  * This call will initiate MST topology discovery. Which
 993                                  * will detect MST ports and add new DRM connector DRM
 994                                  * framework. Then read EDID via remote i2c over aux. In
 995                                  * the end, will notify DRM detect result and save EDID
 996                                  * into DRM framework.
 997                                  *
 998                                  * .detect is called by .fill_modes.
 999                                  * .fill_modes is called by user mode ioctl
1000                                  * DRM_IOCTL_MODE_GETCONNECTOR.
1001                                  *
1002                                  * .get_modes is called by .fill_modes.
1003                                  *
1004                                  * call .get_modes, AMDGPU DM implementation will create
1005                                  * new dc_sink and add to dc_link. For long HPD plug
1006                                  * in/out, MST has its own handle.
1007                                  *
1008                                  * Therefore, just after dc_create, link->sink is not
1009                                  * created for MST until user mode app calls
1010                                  * DRM_IOCTL_MODE_GETCONNECTOR.
1011                                  *
1012                                  * Need check ->sink usages in case ->sink = NULL
1013                                  * TODO: s3 resume check
1014                                  */
1015
1016                                 dm_helpers_dp_update_branch_info(link->ctx, link);
1017                                 if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
1018                                                 link, reason == DETECT_REASON_BOOT)) {
1019                                         if (prev_sink)
1020                                                 dc_sink_release(prev_sink);
1021                                         return false;
1022                                 } else {
1023                                         link->type = dc_connection_sst_branch;
1024                                         sink_caps.signal = SIGNAL_TYPE_DISPLAY_PORT;
1025                                 }
1026                         }
1027
1028                         /* Active SST downstream branch device unplug*/
1029                         if (link->type == dc_connection_sst_branch &&
1030                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1031                                 if (prev_sink)
1032                                         /* Downstream unplug */
1033                                         dc_sink_release(prev_sink);
1034                                 return true;
1035                         }
1036
1037                         /* disable audio for non DP to HDMI active sst converter */
1038                         if (link->type == dc_connection_sst_branch &&
1039                                         is_dp_active_dongle(link) &&
1040                                         (link->dpcd_caps.dongle_type !=
1041                                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1042                                 converter_disable_audio = true;
1043
1044                         // link switch from MST to non-MST stop topology manager
1045                         if (pre_connection_type == dc_connection_mst_branch &&
1046                                         link->type != dc_connection_mst_branch)
1047                                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1048
1049
1050                         // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
1051                         if (reason == DETECT_REASON_BOOT &&
1052                                         !dc_ctx->dc->config.power_down_display_on_boot &&
1053                                         link->link_status.link_active)
1054                                 perform_dp_seamless_boot = true;
1055
1056                         if (perform_dp_seamless_boot) {
1057                                 read_current_link_settings_on_detect(link);
1058                                 link->verified_link_cap = link->reported_link_cap;
1059                         }
1060
1061                         break;
1062                 }
1063
1064                 default:
1065                         DC_ERROR("Invalid connector type! signal:%d\n",
1066                                  link->connector_signal);
1067                         if (prev_sink)
1068                                 dc_sink_release(prev_sink);
1069                         return false;
1070                 } /* switch() */
1071
1072                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1073                         link->dpcd_sink_count =
1074                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1075                 else
1076                         link->dpcd_sink_count = 1;
1077
1078                 dal_ddc_service_set_transaction_type(link->ddc,
1079                                                      sink_caps.transaction_type);
1080
1081                 link->aux_mode =
1082                         dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1083
1084                 sink_init_data.link = link;
1085                 sink_init_data.sink_signal = sink_caps.signal;
1086
1087                 sink = dc_sink_create(&sink_init_data);
1088                 if (!sink) {
1089                         DC_ERROR("Failed to create sink!\n");
1090                         if (prev_sink)
1091                                 dc_sink_release(prev_sink);
1092                         return false;
1093                 }
1094
1095                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1096                 sink->converter_disable_audio = converter_disable_audio;
1097
1098                 /* dc_sink_create returns a new reference */
1099                 link->local_sink = sink;
1100
1101                 edid_status = dm_helpers_read_local_edid(link->ctx,
1102                                                          link, sink);
1103
1104                 switch (edid_status) {
1105                 case EDID_BAD_CHECKSUM:
1106                         DC_LOG_ERROR("EDID checksum invalid.\n");
1107                         break;
1108                 case EDID_NO_RESPONSE:
1109                         DC_LOG_ERROR("No EDID read.\n");
1110                         /*
1111                          * Abort detection for non-DP connectors if we have
1112                          * no EDID
1113                          *
1114                          * DP needs to report as connected if HDP is high
1115                          * even if we have no EDID in order to go to
1116                          * fail-safe mode
1117                          */
1118                         if (dc_is_hdmi_signal(link->connector_signal) ||
1119                             dc_is_dvi_signal(link->connector_signal)) {
1120                                 if (prev_sink)
1121                                         dc_sink_release(prev_sink);
1122
1123                                 return false;
1124                         }
1125                         break;
1126                 default:
1127                         break;
1128                 }
1129
1130                 // Check if edid is the same
1131                 if ((prev_sink) &&
1132                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1133                         same_edid = is_same_edid(&prev_sink->dc_edid,
1134                                                  &sink->dc_edid);
1135
1136                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1137                         link->ctx->dc->debug.hdmi20_disable = true;
1138
1139                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1140                     sink_caps.transaction_type ==
1141                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1142                         /*
1143                          * TODO debug why Dell 2413 doesn't like
1144                          *  two link trainings
1145                          */
1146 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1147                         query_hdcp_capability(sink->sink_signal, link);
1148 #endif
1149
1150                         // verify link cap for SST non-seamless boot
1151                         if (!perform_dp_seamless_boot)
1152                                 dp_verify_link_cap_with_retries(link,
1153                                                                 &link->reported_link_cap,
1154                                                                 LINK_TRAINING_MAX_VERIFY_RETRY);
1155                 } else {
1156                         // If edid is the same, then discard new sink and revert back to original sink
1157                         if (same_edid) {
1158                                 link_disconnect_remap(prev_sink, link);
1159                                 sink = prev_sink;
1160                                 prev_sink = NULL;
1161                         }
1162 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1163                         query_hdcp_capability(sink->sink_signal, link);
1164 #endif
1165                 }
1166
1167                 /* HDMI-DVI Dongle */
1168                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1169                     !sink->edid_caps.edid_hdmi)
1170                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1171
1172                 /* Connectivity log: detection */
1173                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1174                         CONN_DATA_DETECT(link,
1175                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1176                                          DC_EDID_BLOCK_SIZE,
1177                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1178                 }
1179
1180                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1181                         "manufacturer_id = %X, "
1182                         "product_id = %X, "
1183                         "serial_number = %X, "
1184                         "manufacture_week = %d, "
1185                         "manufacture_year = %d, "
1186                         "display_name = %s, "
1187                         "speaker_flag = %d, "
1188                         "audio_mode_count = %d\n",
1189                         __func__,
1190                         sink->edid_caps.manufacturer_id,
1191                         sink->edid_caps.product_id,
1192                         sink->edid_caps.serial_number,
1193                         sink->edid_caps.manufacture_week,
1194                         sink->edid_caps.manufacture_year,
1195                         sink->edid_caps.display_name,
1196                         sink->edid_caps.speaker_flags,
1197                         sink->edid_caps.audio_mode_count);
1198
1199                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1200                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1201                                 "format_code = %d, "
1202                                 "channel_count = %d, "
1203                                 "sample_rate = %d, "
1204                                 "sample_size = %d\n",
1205                                 __func__,
1206                                 i,
1207                                 sink->edid_caps.audio_modes[i].format_code,
1208                                 sink->edid_caps.audio_modes[i].channel_count,
1209                                 sink->edid_caps.audio_modes[i].sample_rate,
1210                                 sink->edid_caps.audio_modes[i].sample_size);
1211                 }
1212         } else {
1213                 /* From Connected-to-Disconnected. */
1214                 if (link->type == dc_connection_mst_branch) {
1215                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
1216                                   link->link_index);
1217
1218                         /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
1219                         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1220                                 link->wa_flags.dpia_mst_dsc_always_on = false;
1221
1222                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1223
1224                         link->mst_stream_alloc_table.stream_count = 0;
1225                         memset(link->mst_stream_alloc_table.stream_allocations,
1226                                0,
1227                                sizeof(link->mst_stream_alloc_table.stream_allocations));
1228                 }
1229
1230 #if defined(CONFIG_DRM_AMD_DC_DCN)
1231                 if (dp_get_link_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING)
1232                         reset_dp_hpo_stream_encoders_for_link(link);
1233 #endif
1234
1235                 link->type = dc_connection_none;
1236                 sink_caps.signal = SIGNAL_TYPE_NONE;
1237                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1238                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1239                  *  the dongle is still there and limits the number of modes we can emulate.
1240                  *  Clear dongle_max_pix_clk on disconnect to fix this
1241                  */
1242                 link->dongle_max_pix_clk = 0;
1243         }
1244
1245         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1246                   link->link_index, sink,
1247                   (sink_caps.signal ==
1248                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1249                   prev_sink, same_edid);
1250
1251         if (prev_sink)
1252                 dc_sink_release(prev_sink);
1253
1254         return true;
1255 }
1256
1257 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1258 {
1259         const struct dc *dc = link->dc;
1260         bool ret;
1261         bool can_apply_seamless_boot = false;
1262         int i;
1263
1264         for (i = 0; i < dc->current_state->stream_count; i++) {
1265                 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
1266                         can_apply_seamless_boot = true;
1267                         break;
1268                 }
1269         }
1270
1271 #if defined(CONFIG_DRM_AMD_DC_DCN)
1272         dc_z10_restore(dc);
1273 #endif
1274
1275         /* get out of low power state */
1276         if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
1277                 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1278
1279         ret = dc_link_detect_helper(link, reason);
1280
1281         /* Go back to power optimized state */
1282         if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
1283                 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1284
1285         return ret;
1286 }
1287
1288 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1289 {
1290         uint32_t state;
1291
1292         dal_gpio_lock_pin(dc_link->hpd_gpio);
1293         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1294         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1295
1296         return state;
1297 }
1298
1299 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1300 {
1301         struct gpio *hpd;
1302         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1303
1304         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1305                            link->ctx->gpio_service);
1306
1307         if (hpd) {
1308                 switch (dal_irq_get_source(hpd)) {
1309                 case DC_IRQ_SOURCE_HPD1:
1310                         hpd_id = HPD_SOURCEID1;
1311                 break;
1312                 case DC_IRQ_SOURCE_HPD2:
1313                         hpd_id = HPD_SOURCEID2;
1314                 break;
1315                 case DC_IRQ_SOURCE_HPD3:
1316                         hpd_id = HPD_SOURCEID3;
1317                 break;
1318                 case DC_IRQ_SOURCE_HPD4:
1319                         hpd_id = HPD_SOURCEID4;
1320                 break;
1321                 case DC_IRQ_SOURCE_HPD5:
1322                         hpd_id = HPD_SOURCEID5;
1323                 break;
1324                 case DC_IRQ_SOURCE_HPD6:
1325                         hpd_id = HPD_SOURCEID6;
1326                 break;
1327                 default:
1328                         BREAK_TO_DEBUGGER();
1329                 break;
1330                 }
1331
1332                 dal_gpio_destroy_irq(&hpd);
1333         }
1334
1335         return hpd_id;
1336 }
1337
1338 static enum channel_id get_ddc_line(struct dc_link *link)
1339 {
1340         struct ddc *ddc;
1341         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1342
1343         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1344
1345         if (ddc) {
1346                 switch (dal_ddc_get_line(ddc)) {
1347                 case GPIO_DDC_LINE_DDC1:
1348                         channel = CHANNEL_ID_DDC1;
1349                         break;
1350                 case GPIO_DDC_LINE_DDC2:
1351                         channel = CHANNEL_ID_DDC2;
1352                         break;
1353                 case GPIO_DDC_LINE_DDC3:
1354                         channel = CHANNEL_ID_DDC3;
1355                         break;
1356                 case GPIO_DDC_LINE_DDC4:
1357                         channel = CHANNEL_ID_DDC4;
1358                         break;
1359                 case GPIO_DDC_LINE_DDC5:
1360                         channel = CHANNEL_ID_DDC5;
1361                         break;
1362                 case GPIO_DDC_LINE_DDC6:
1363                         channel = CHANNEL_ID_DDC6;
1364                         break;
1365                 case GPIO_DDC_LINE_DDC_VGA:
1366                         channel = CHANNEL_ID_DDC_VGA;
1367                         break;
1368                 case GPIO_DDC_LINE_I2C_PAD:
1369                         channel = CHANNEL_ID_I2C_PAD;
1370                         break;
1371                 default:
1372                         BREAK_TO_DEBUGGER();
1373                         break;
1374                 }
1375         }
1376
1377         return channel;
1378 }
1379
1380 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1381 {
1382         switch (encoder.id) {
1383         case ENCODER_ID_INTERNAL_UNIPHY:
1384                 switch (encoder.enum_id) {
1385                 case ENUM_ID_1:
1386                         return TRANSMITTER_UNIPHY_A;
1387                 case ENUM_ID_2:
1388                         return TRANSMITTER_UNIPHY_B;
1389                 default:
1390                         return TRANSMITTER_UNKNOWN;
1391                 }
1392         break;
1393         case ENCODER_ID_INTERNAL_UNIPHY1:
1394                 switch (encoder.enum_id) {
1395                 case ENUM_ID_1:
1396                         return TRANSMITTER_UNIPHY_C;
1397                 case ENUM_ID_2:
1398                         return TRANSMITTER_UNIPHY_D;
1399                 default:
1400                         return TRANSMITTER_UNKNOWN;
1401                 }
1402         break;
1403         case ENCODER_ID_INTERNAL_UNIPHY2:
1404                 switch (encoder.enum_id) {
1405                 case ENUM_ID_1:
1406                         return TRANSMITTER_UNIPHY_E;
1407                 case ENUM_ID_2:
1408                         return TRANSMITTER_UNIPHY_F;
1409                 default:
1410                         return TRANSMITTER_UNKNOWN;
1411                 }
1412         break;
1413         case ENCODER_ID_INTERNAL_UNIPHY3:
1414                 switch (encoder.enum_id) {
1415                 case ENUM_ID_1:
1416                         return TRANSMITTER_UNIPHY_G;
1417                 default:
1418                         return TRANSMITTER_UNKNOWN;
1419                 }
1420         break;
1421         case ENCODER_ID_EXTERNAL_NUTMEG:
1422                 switch (encoder.enum_id) {
1423                 case ENUM_ID_1:
1424                         return TRANSMITTER_NUTMEG_CRT;
1425                 default:
1426                         return TRANSMITTER_UNKNOWN;
1427                 }
1428         break;
1429         case ENCODER_ID_EXTERNAL_TRAVIS:
1430                 switch (encoder.enum_id) {
1431                 case ENUM_ID_1:
1432                         return TRANSMITTER_TRAVIS_CRT;
1433                 case ENUM_ID_2:
1434                         return TRANSMITTER_TRAVIS_LCD;
1435                 default:
1436                         return TRANSMITTER_UNKNOWN;
1437                 }
1438         break;
1439         default:
1440                 return TRANSMITTER_UNKNOWN;
1441         }
1442 }
1443
1444 static bool dc_link_construct_legacy(struct dc_link *link,
1445                                      const struct link_init_data *init_params)
1446 {
1447         uint8_t i;
1448         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1449         struct dc_context *dc_ctx = init_params->ctx;
1450         struct encoder_init_data enc_init_data = { 0 };
1451         struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1452         struct integrated_info *info;
1453         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1454         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1455         struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1456
1457         DC_LOGGER_INIT(dc_ctx->logger);
1458
1459         info = kzalloc(sizeof(*info), GFP_KERNEL);
1460         if (!info)
1461                 goto create_fail;
1462
1463         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1464         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1465
1466         link->link_status.dpcd_caps = &link->dpcd_caps;
1467
1468         link->dc = init_params->dc;
1469         link->ctx = dc_ctx;
1470         link->link_index = init_params->link_index;
1471
1472         memset(&link->preferred_training_settings, 0,
1473                sizeof(struct dc_link_training_overrides));
1474         memset(&link->preferred_link_setting, 0,
1475                sizeof(struct dc_link_settings));
1476
1477         link->link_id =
1478                 bios->funcs->get_connector_id(bios, init_params->connector_index);
1479
1480         link->ep_type = DISPLAY_ENDPOINT_PHY;
1481
1482         DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1483
1484         if (bios->funcs->get_disp_connector_caps_info) {
1485                 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1486                 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1487                 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1488         }
1489
1490         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1491                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1492                                      __func__, init_params->connector_index,
1493                                      link->link_id.type, OBJECT_TYPE_CONNECTOR);
1494                 goto create_fail;
1495         }
1496
1497         if (link->dc->res_pool->funcs->link_init)
1498                 link->dc->res_pool->funcs->link_init(link);
1499
1500         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1501                                       link->ctx->gpio_service);
1502
1503         if (link->hpd_gpio) {
1504                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1505                 dal_gpio_unlock_pin(link->hpd_gpio);
1506                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1507
1508                 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1509                 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1510         }
1511
1512         switch (link->link_id.id) {
1513         case CONNECTOR_ID_HDMI_TYPE_A:
1514                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1515
1516                 break;
1517         case CONNECTOR_ID_SINGLE_LINK_DVID:
1518         case CONNECTOR_ID_SINGLE_LINK_DVII:
1519                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1520                 break;
1521         case CONNECTOR_ID_DUAL_LINK_DVID:
1522         case CONNECTOR_ID_DUAL_LINK_DVII:
1523                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1524                 break;
1525         case CONNECTOR_ID_DISPLAY_PORT:
1526                 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1527
1528                 if (link->hpd_gpio)
1529                         link->irq_source_hpd_rx =
1530                                         dal_irq_get_rx_source(link->hpd_gpio);
1531
1532                 break;
1533         case CONNECTOR_ID_EDP:
1534                 link->connector_signal = SIGNAL_TYPE_EDP;
1535
1536                 if (link->hpd_gpio) {
1537                         if (!link->dc->config.allow_edp_hotplug_detection)
1538                                 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1539                         link->irq_source_hpd_rx =
1540                                         dal_irq_get_rx_source(link->hpd_gpio);
1541                 }
1542
1543                 break;
1544         case CONNECTOR_ID_LVDS:
1545                 link->connector_signal = SIGNAL_TYPE_LVDS;
1546                 break;
1547         default:
1548                 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1549                                link->link_id.id);
1550                 goto create_fail;
1551         }
1552
1553         /* TODO: #DAL3 Implement id to str function.*/
1554         LINK_INFO("Connector[%d] description:"
1555                   "signal %d\n",
1556                   init_params->connector_index,
1557                   link->connector_signal);
1558
1559         ddc_service_init_data.ctx = link->ctx;
1560         ddc_service_init_data.id = link->link_id;
1561         ddc_service_init_data.link = link;
1562         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1563
1564         if (!link->ddc) {
1565                 DC_ERROR("Failed to create ddc_service!\n");
1566                 goto ddc_create_fail;
1567         }
1568
1569         if (!link->ddc->ddc_pin) {
1570                 DC_ERROR("Failed to get I2C info for connector!\n");
1571                 goto ddc_create_fail;
1572         }
1573
1574         link->ddc_hw_inst =
1575                 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1576
1577
1578         if (link->dc->res_pool->funcs->panel_cntl_create &&
1579                 (link->link_id.id == CONNECTOR_ID_EDP ||
1580                         link->link_id.id == CONNECTOR_ID_LVDS)) {
1581                 panel_cntl_init_data.ctx = dc_ctx;
1582                 panel_cntl_init_data.inst =
1583                         panel_cntl_init_data.ctx->dc_edp_id_count;
1584                 link->panel_cntl =
1585                         link->dc->res_pool->funcs->panel_cntl_create(
1586                                                                 &panel_cntl_init_data);
1587                 panel_cntl_init_data.ctx->dc_edp_id_count++;
1588
1589                 if (link->panel_cntl == NULL) {
1590                         DC_ERROR("Failed to create link panel_cntl!\n");
1591                         goto panel_cntl_create_fail;
1592                 }
1593         }
1594
1595         enc_init_data.ctx = dc_ctx;
1596         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1597                               &enc_init_data.encoder);
1598         enc_init_data.connector = link->link_id;
1599         enc_init_data.channel = get_ddc_line(link);
1600         enc_init_data.hpd_source = get_hpd_line(link);
1601
1602         link->hpd_src = enc_init_data.hpd_source;
1603
1604         enc_init_data.transmitter =
1605                 translate_encoder_to_transmitter(enc_init_data.encoder);
1606         link->link_enc =
1607                 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1608
1609         if (!link->link_enc) {
1610                 DC_ERROR("Failed to create link encoder!\n");
1611                 goto link_enc_create_fail;
1612         }
1613
1614         DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1615 #if defined(CONFIG_DRM_AMD_DC_DCN)
1616         DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE);
1617 #endif
1618
1619         /* Update link encoder tracking variables. These are used for the dynamic
1620          * assignment of link encoders to streams.
1621          */
1622         link->eng_id = link->link_enc->preferred_engine;
1623         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1624         link->dc->res_pool->dig_link_enc_count++;
1625
1626         link->link_enc_hw_inst = link->link_enc->transmitter;
1627
1628         for (i = 0; i < 4; i++) {
1629                 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1630                                              link->link_id, i,
1631                                              &link->device_tag) != BP_RESULT_OK) {
1632                         DC_ERROR("Failed to find device tag!\n");
1633                         goto device_tag_fail;
1634                 }
1635
1636                 /* Look for device tag that matches connector signal,
1637                  * CRT for rgb, LCD for other supported signal tyes
1638                  */
1639                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1640                                                       link->device_tag.dev_id))
1641                         continue;
1642                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1643                     link->connector_signal != SIGNAL_TYPE_RGB)
1644                         continue;
1645                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1646                     link->connector_signal == SIGNAL_TYPE_RGB)
1647                         continue;
1648
1649                 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1650                 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1651                 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1652                 break;
1653         }
1654
1655         if (bios->integrated_info)
1656                 memcpy(info, bios->integrated_info, sizeof(*info));
1657
1658         /* Look for channel mapping corresponding to connector and device tag */
1659         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1660                 struct external_display_path *path =
1661                         &info->ext_disp_conn_info.path[i];
1662
1663                 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1664                     path->device_connector_id.id == link->link_id.id &&
1665                     path->device_connector_id.type == link->link_id.type) {
1666                         if (link->device_tag.acpi_device != 0 &&
1667                             path->device_acpi_enum == link->device_tag.acpi_device) {
1668                                 link->ddi_channel_mapping = path->channel_mapping;
1669                                 link->chip_caps = path->caps;
1670                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1671                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1672                         } else if (path->device_tag ==
1673                                    link->device_tag.dev_id.raw_device_tag) {
1674                                 link->ddi_channel_mapping = path->channel_mapping;
1675                                 link->chip_caps = path->caps;
1676                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1677                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1678                         }
1679
1680                         if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
1681                                 link->bios_forced_drive_settings.VOLTAGE_SWING =
1682                                                 (info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
1683                                 link->bios_forced_drive_settings.PRE_EMPHASIS =
1684                                                 ((info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
1685                         }
1686
1687                         break;
1688                 }
1689         }
1690
1691         if (bios->funcs->get_atom_dc_golden_table)
1692                 bios->funcs->get_atom_dc_golden_table(bios);
1693
1694         /*
1695          * TODO check if GPIO programmed correctly
1696          *
1697          * If GPIO isn't programmed correctly HPD might not rise or drain
1698          * fast enough, leading to bounces.
1699          */
1700         program_hpd_filter(link);
1701
1702         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1703
1704         DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1705         kfree(info);
1706         return true;
1707 device_tag_fail:
1708         link->link_enc->funcs->destroy(&link->link_enc);
1709 link_enc_create_fail:
1710         if (link->panel_cntl != NULL)
1711                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1712 panel_cntl_create_fail:
1713         dal_ddc_service_destroy(&link->ddc);
1714 ddc_create_fail:
1715 create_fail:
1716
1717         if (link->hpd_gpio) {
1718                 dal_gpio_destroy_irq(&link->hpd_gpio);
1719                 link->hpd_gpio = NULL;
1720         }
1721
1722         DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1723         kfree(info);
1724
1725         return false;
1726 }
1727
1728 static bool dc_link_construct_dpia(struct dc_link *link,
1729                                    const struct link_init_data *init_params)
1730 {
1731         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1732         struct dc_context *dc_ctx = init_params->ctx;
1733
1734         DC_LOGGER_INIT(dc_ctx->logger);
1735
1736         /* Initialized irq source for hpd and hpd rx */
1737         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1738         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1739         link->link_status.dpcd_caps = &link->dpcd_caps;
1740
1741         link->dc = init_params->dc;
1742         link->ctx = dc_ctx;
1743         link->link_index = init_params->link_index;
1744
1745         memset(&link->preferred_training_settings, 0,
1746                sizeof(struct dc_link_training_overrides));
1747         memset(&link->preferred_link_setting, 0,
1748                sizeof(struct dc_link_settings));
1749
1750         /* Dummy Init for linkid */
1751         link->link_id.type = OBJECT_TYPE_CONNECTOR;
1752         link->link_id.id = CONNECTOR_ID_DISPLAY_PORT;
1753         link->link_id.enum_id = ENUM_ID_1 + init_params->connector_index;
1754         link->is_internal_display = false;
1755         link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1756         LINK_INFO("Connector[%d] description:signal %d\n",
1757                   init_params->connector_index,
1758                   link->connector_signal);
1759
1760         link->ep_type = DISPLAY_ENDPOINT_USB4_DPIA;
1761         link->is_dig_mapping_flexible = true;
1762
1763         /* TODO: Initialize link : funcs->link_init */
1764
1765         ddc_service_init_data.ctx = link->ctx;
1766         ddc_service_init_data.id = link->link_id;
1767         ddc_service_init_data.link = link;
1768         /* Set indicator for dpia link so that ddc won't be created */
1769         ddc_service_init_data.is_dpia_link = true;
1770
1771         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1772         if (!link->ddc) {
1773                 DC_ERROR("Failed to create ddc_service!\n");
1774                 goto ddc_create_fail;
1775         }
1776
1777         /* Set dpia port index : 0 to number of dpia ports */
1778         link->ddc_hw_inst = init_params->connector_index;
1779
1780         /* TODO: Create link encoder */
1781
1782         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1783
1784         /* Some docks seem to NAK I2C writes to segment pointer with mot=0. */
1785         link->wa_flags.dp_mot_reset_segment = true;
1786
1787         return true;
1788
1789 ddc_create_fail:
1790         return false;
1791 }
1792
1793 static bool dc_link_construct(struct dc_link *link,
1794                               const struct link_init_data *init_params)
1795 {
1796         /* Handle dpia case */
1797         if (init_params->is_dpia_link)
1798                 return dc_link_construct_dpia(link, init_params);
1799         else
1800                 return dc_link_construct_legacy(link, init_params);
1801 }
1802 /*******************************************************************************
1803  * Public functions
1804  ******************************************************************************/
1805 struct dc_link *link_create(const struct link_init_data *init_params)
1806 {
1807         struct dc_link *link =
1808                         kzalloc(sizeof(*link), GFP_KERNEL);
1809
1810         if (NULL == link)
1811                 goto alloc_fail;
1812
1813         if (false == dc_link_construct(link, init_params))
1814                 goto construct_fail;
1815
1816         /*
1817          * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
1818          * since struct preferred_link_setting won't be reset after S3.
1819          */
1820         link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
1821
1822         return link;
1823
1824 construct_fail:
1825         kfree(link);
1826
1827 alloc_fail:
1828         return NULL;
1829 }
1830
1831 void link_destroy(struct dc_link **link)
1832 {
1833         dc_link_destruct(*link);
1834         kfree(*link);
1835         *link = NULL;
1836 }
1837
1838 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1839 {
1840         struct dc_stream_state *stream = pipe_ctx->stream;
1841
1842         if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1843                 struct dc_link *link = stream->link;
1844                 union down_spread_ctrl old_downspread;
1845                 union down_spread_ctrl new_downspread;
1846
1847                 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1848                                 &old_downspread.raw, sizeof(old_downspread));
1849
1850                 new_downspread.raw = old_downspread.raw;
1851
1852                 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1853                                 (stream->ignore_msa_timing_param) ? 1 : 0;
1854
1855                 if (new_downspread.raw != old_downspread.raw) {
1856                         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1857                                 &new_downspread.raw, sizeof(new_downspread));
1858                 }
1859
1860         } else {
1861                 dm_helpers_mst_enable_stream_features(stream);
1862         }
1863 }
1864
1865 static enum dc_status enable_link_dp(struct dc_state *state,
1866                                      struct pipe_ctx *pipe_ctx)
1867 {
1868         struct dc_stream_state *stream = pipe_ctx->stream;
1869         enum dc_status status;
1870         bool skip_video_pattern;
1871         struct dc_link *link = stream->link;
1872         struct dc_link_settings link_settings = {0};
1873         bool fec_enable;
1874         int i;
1875         bool apply_seamless_boot_optimization = false;
1876         uint32_t bl_oled_enable_delay = 50; // in ms
1877         const uint32_t post_oui_delay = 30; // 30ms
1878         /* Reduce link bandwidth between failed link training attempts. */
1879         bool do_fallback = false;
1880
1881         // check for seamless boot
1882         for (i = 0; i < state->stream_count; i++) {
1883                 if (state->streams[i]->apply_seamless_boot_optimization) {
1884                         apply_seamless_boot_optimization = true;
1885                         break;
1886                 }
1887         }
1888
1889         /* get link settings for video mode timing */
1890         decide_link_settings(stream, &link_settings);
1891
1892         /* Train with fallback when enabling DPIA link. Conventional links are
1893          * trained with fallback during sink detection.
1894          */
1895         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1896                 do_fallback = true;
1897
1898 #if defined(CONFIG_DRM_AMD_DC_DCN)
1899         /*
1900          * Temporary w/a to get DP2.0 link rates to work with SST.
1901          * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved.
1902          */
1903         if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING &&
1904                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
1905                         link->dc->debug.set_mst_en_for_sst) {
1906                 dp_enable_mst_on_sink(link, true);
1907         }
1908 #endif
1909
1910         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1911                 /*in case it is not on*/
1912                 link->dc->hwss.edp_power_control(link, true);
1913                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1914         }
1915
1916 #if defined(CONFIG_DRM_AMD_DC_DCN)
1917         if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING) {
1918                 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
1919         } else {
1920                 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1921                                 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1922                 if (state->clk_mgr && !apply_seamless_boot_optimization)
1923                         state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1924                                         state, false);
1925         }
1926 #else
1927         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1928                 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1929         if (state->clk_mgr && !apply_seamless_boot_optimization)
1930                 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1931                                                                                         state, false);
1932 #endif
1933
1934         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1935         dpcd_set_source_specific_data(link);
1936         if (link->dpcd_sink_ext_caps.raw != 0)
1937                 msleep(post_oui_delay);
1938
1939         skip_video_pattern = true;
1940
1941         if (link_settings.link_rate == LINK_RATE_LOW)
1942                 skip_video_pattern = false;
1943
1944         if (perform_link_training_with_retries(&link_settings,
1945                                                skip_video_pattern,
1946                                                LINK_TRAINING_ATTEMPTS,
1947                                                pipe_ctx,
1948                                                pipe_ctx->stream->signal,
1949                                                do_fallback)) {
1950                 link->cur_link_settings = link_settings;
1951                 status = DC_OK;
1952         } else {
1953                 status = DC_FAIL_DP_LINK_TRAINING;
1954         }
1955
1956         if (link->preferred_training_settings.fec_enable)
1957                 fec_enable = *link->preferred_training_settings.fec_enable;
1958         else
1959                 fec_enable = true;
1960
1961 #if defined(CONFIG_DRM_AMD_DC_DCN)
1962         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING)
1963                 dp_set_fec_enable(link, fec_enable);
1964 #else
1965         dp_set_fec_enable(link, fec_enable);
1966 #endif
1967
1968         // during mode set we do DP_SET_POWER off then on, aux writes are lost
1969         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
1970                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
1971                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
1972                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
1973                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
1974                         msleep(bl_oled_enable_delay);
1975                 dc_link_backlight_enable_aux(link, true);
1976         }
1977
1978         return status;
1979 }
1980
1981 static enum dc_status enable_link_edp(
1982                 struct dc_state *state,
1983                 struct pipe_ctx *pipe_ctx)
1984 {
1985         enum dc_status status;
1986
1987         status = enable_link_dp(state, pipe_ctx);
1988
1989         return status;
1990 }
1991
1992 static enum dc_status enable_link_dp_mst(
1993                 struct dc_state *state,
1994                 struct pipe_ctx *pipe_ctx)
1995 {
1996         struct dc_link *link = pipe_ctx->stream->link;
1997
1998         /* sink signal type after MST branch is MST. Multiple MST sinks
1999          * share one link. Link DP PHY is enable or training only once.
2000          */
2001         if (link->link_status.link_active)
2002                 return DC_OK;
2003
2004         /* clear payload table */
2005         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
2006
2007         /* to make sure the pending down rep can be processed
2008          * before enabling the link
2009          */
2010         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
2011
2012         /* set the sink to MST mode before enabling the link */
2013         dp_enable_mst_on_sink(link, true);
2014
2015         return enable_link_dp(state, pipe_ctx);
2016 }
2017
2018 void dc_link_blank_all_dp_displays(struct dc *dc)
2019 {
2020         unsigned int i;
2021         uint8_t dpcd_power_state = '\0';
2022         enum dc_status status = DC_ERROR_UNEXPECTED;
2023
2024         for (i = 0; i < dc->link_count; i++) {
2025                 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) ||
2026                         (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL))
2027                         continue;
2028
2029                 /* DP 2.0 spec requires that we read LTTPR caps first */
2030                 dp_retrieve_lttpr_cap(dc->links[i]);
2031                 /* if any of the displays are lit up turn them off */
2032                 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
2033                                                         &dpcd_power_state, sizeof(dpcd_power_state));
2034
2035                 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
2036                         dc_link_blank_dp_stream(dc->links[i], true);
2037         }
2038
2039 }
2040
2041 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init)
2042 {
2043         unsigned int j;
2044         struct dc  *dc = link->ctx->dc;
2045         enum signal_type signal = link->connector_signal;
2046
2047         if ((signal == SIGNAL_TYPE_EDP) ||
2048                 (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
2049                 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
2050                         link->link_enc->funcs->get_dig_frontend &&
2051                         link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
2052                         unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2053
2054                         if (fe != ENGINE_ID_UNKNOWN)
2055                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
2056                                         if (fe == dc->res_pool->stream_enc[j]->id) {
2057                                                 dc->res_pool->stream_enc[j]->funcs->dp_blank(link,
2058                                                                         dc->res_pool->stream_enc[j]);
2059                                                 break;
2060                                         }
2061                                 }
2062                 }
2063
2064                 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)
2065                         dp_receiver_power_ctrl(link, false);
2066         }
2067 }
2068
2069 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
2070                 enum engine_id eng_id,
2071                 struct ext_hdmi_settings *settings)
2072 {
2073         bool result = false;
2074         int i = 0;
2075         struct integrated_info *integrated_info =
2076                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
2077
2078         if (integrated_info == NULL)
2079                 return false;
2080
2081         /*
2082          * Get retimer settings from sbios for passing SI eye test for DCE11
2083          * The setting values are varied based on board revision and port id
2084          * Therefore the setting values of each ports is passed by sbios.
2085          */
2086
2087         // Check if current bios contains ext Hdmi settings
2088         if (integrated_info->gpu_cap_info & 0x20) {
2089                 switch (eng_id) {
2090                 case ENGINE_ID_DIGA:
2091                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
2092                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
2093                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
2094                         memmove(settings->reg_settings,
2095                                         integrated_info->dp0_ext_hdmi_reg_settings,
2096                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
2097                         memmove(settings->reg_settings_6g,
2098                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
2099                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
2100                         result = true;
2101                         break;
2102                 case ENGINE_ID_DIGB:
2103                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
2104                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
2105                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
2106                         memmove(settings->reg_settings,
2107                                         integrated_info->dp1_ext_hdmi_reg_settings,
2108                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
2109                         memmove(settings->reg_settings_6g,
2110                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
2111                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
2112                         result = true;
2113                         break;
2114                 case ENGINE_ID_DIGC:
2115                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
2116                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
2117                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
2118                         memmove(settings->reg_settings,
2119                                         integrated_info->dp2_ext_hdmi_reg_settings,
2120                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
2121                         memmove(settings->reg_settings_6g,
2122                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
2123                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
2124                         result = true;
2125                         break;
2126                 case ENGINE_ID_DIGD:
2127                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
2128                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
2129                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
2130                         memmove(settings->reg_settings,
2131                                         integrated_info->dp3_ext_hdmi_reg_settings,
2132                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
2133                         memmove(settings->reg_settings_6g,
2134                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
2135                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
2136                         result = true;
2137                         break;
2138                 default:
2139                         break;
2140                 }
2141
2142                 if (result == true) {
2143                         // Validate settings from bios integrated info table
2144                         if (settings->slv_addr == 0)
2145                                 return false;
2146                         if (settings->reg_num > 9)
2147                                 return false;
2148                         if (settings->reg_num_6g > 3)
2149                                 return false;
2150
2151                         for (i = 0; i < settings->reg_num; i++) {
2152                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
2153                                         return false;
2154                         }
2155
2156                         for (i = 0; i < settings->reg_num_6g; i++) {
2157                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
2158                                         return false;
2159                         }
2160                 }
2161         }
2162
2163         return result;
2164 }
2165
2166 static bool i2c_write(struct pipe_ctx *pipe_ctx,
2167                 uint8_t address, uint8_t *buffer, uint32_t length)
2168 {
2169         struct i2c_command cmd = {0};
2170         struct i2c_payload payload = {0};
2171
2172         memset(&payload, 0, sizeof(payload));
2173         memset(&cmd, 0, sizeof(cmd));
2174
2175         cmd.number_of_payloads = 1;
2176         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
2177         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
2178
2179         payload.address = address;
2180         payload.data = buffer;
2181         payload.length = length;
2182         payload.write = true;
2183         cmd.payloads = &payload;
2184
2185         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
2186                         pipe_ctx->stream->link, &cmd))
2187                 return true;
2188
2189         return false;
2190 }
2191
2192 static void write_i2c_retimer_setting(
2193                 struct pipe_ctx *pipe_ctx,
2194                 bool is_vga_mode,
2195                 bool is_over_340mhz,
2196                 struct ext_hdmi_settings *settings)
2197 {
2198         uint8_t slave_address = (settings->slv_addr >> 1);
2199         uint8_t buffer[2];
2200         const uint8_t apply_rx_tx_change = 0x4;
2201         uint8_t offset = 0xA;
2202         uint8_t value = 0;
2203         int i = 0;
2204         bool i2c_success = false;
2205         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2206
2207         memset(&buffer, 0, sizeof(buffer));
2208
2209         /* Start Ext-Hdmi programming*/
2210
2211         for (i = 0; i < settings->reg_num; i++) {
2212                 /* Apply 3G settings */
2213                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2214
2215                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
2216                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
2217                         i2c_success = i2c_write(pipe_ctx, slave_address,
2218                                                 buffer, sizeof(buffer));
2219                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2220                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2221                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2222
2223                         if (!i2c_success)
2224                                 goto i2c_write_fail;
2225
2226                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2227                          * needs to be set to 1 on every 0xA-0xC write.
2228                          */
2229                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
2230                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
2231                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
2232
2233                                 /* Query current value from offset 0xA */
2234                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
2235                                         value = settings->reg_settings[i].i2c_reg_val;
2236                                 else {
2237                                         i2c_success =
2238                                                 dal_ddc_service_query_ddc_data(
2239                                                 pipe_ctx->stream->link->ddc,
2240                                                 slave_address, &offset, 1, &value, 1);
2241                                         if (!i2c_success)
2242                                                 goto i2c_write_fail;
2243                                 }
2244
2245                                 buffer[0] = offset;
2246                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2247                                 buffer[1] = value | apply_rx_tx_change;
2248                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2249                                                 buffer, sizeof(buffer));
2250                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2251                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2252                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2253                                 if (!i2c_success)
2254                                         goto i2c_write_fail;
2255                         }
2256                 }
2257         }
2258
2259         /* Apply 3G settings */
2260         if (is_over_340mhz) {
2261                 for (i = 0; i < settings->reg_num_6g; i++) {
2262                         /* Apply 3G settings */
2263                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2264
2265                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2266                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2267                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2268                                                         buffer, sizeof(buffer));
2269                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2270                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2271                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2272
2273                                 if (!i2c_success)
2274                                         goto i2c_write_fail;
2275
2276                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2277                                  * needs to be set to 1 on every 0xA-0xC write.
2278                                  */
2279                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2280                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2281                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2282
2283                                         /* Query current value from offset 0xA */
2284                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2285                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
2286                                         else {
2287                                                 i2c_success =
2288                                                                 dal_ddc_service_query_ddc_data(
2289                                                                 pipe_ctx->stream->link->ddc,
2290                                                                 slave_address, &offset, 1, &value, 1);
2291                                                 if (!i2c_success)
2292                                                         goto i2c_write_fail;
2293                                         }
2294
2295                                         buffer[0] = offset;
2296                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
2297                                         buffer[1] = value | apply_rx_tx_change;
2298                                         i2c_success = i2c_write(pipe_ctx, slave_address,
2299                                                         buffer, sizeof(buffer));
2300                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2301                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2302                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2303                                         if (!i2c_success)
2304                                                 goto i2c_write_fail;
2305                                 }
2306                         }
2307                 }
2308         }
2309
2310         if (is_vga_mode) {
2311                 /* Program additional settings if using 640x480 resolution */
2312
2313                 /* Write offset 0xFF to 0x01 */
2314                 buffer[0] = 0xff;
2315                 buffer[1] = 0x01;
2316                 i2c_success = i2c_write(pipe_ctx, slave_address,
2317                                 buffer, sizeof(buffer));
2318                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2319                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2320                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2321                 if (!i2c_success)
2322                         goto i2c_write_fail;
2323
2324                 /* Write offset 0x00 to 0x23 */
2325                 buffer[0] = 0x00;
2326                 buffer[1] = 0x23;
2327                 i2c_success = i2c_write(pipe_ctx, slave_address,
2328                                 buffer, sizeof(buffer));
2329                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2330                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2331                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2332                 if (!i2c_success)
2333                         goto i2c_write_fail;
2334
2335                 /* Write offset 0xff to 0x00 */
2336                 buffer[0] = 0xff;
2337                 buffer[1] = 0x00;
2338                 i2c_success = i2c_write(pipe_ctx, slave_address,
2339                                 buffer, sizeof(buffer));
2340                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2341                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2342                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2343                 if (!i2c_success)
2344                         goto i2c_write_fail;
2345
2346         }
2347
2348         return;
2349
2350 i2c_write_fail:
2351         DC_LOG_DEBUG("Set retimer failed");
2352 }
2353
2354 static void write_i2c_default_retimer_setting(
2355                 struct pipe_ctx *pipe_ctx,
2356                 bool is_vga_mode,
2357                 bool is_over_340mhz)
2358 {
2359         uint8_t slave_address = (0xBA >> 1);
2360         uint8_t buffer[2];
2361         bool i2c_success = false;
2362         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2363
2364         memset(&buffer, 0, sizeof(buffer));
2365
2366         /* Program Slave Address for tuning single integrity */
2367         /* Write offset 0x0A to 0x13 */
2368         buffer[0] = 0x0A;
2369         buffer[1] = 0x13;
2370         i2c_success = i2c_write(pipe_ctx, slave_address,
2371                         buffer, sizeof(buffer));
2372         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2373                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2374                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2375         if (!i2c_success)
2376                 goto i2c_write_fail;
2377
2378         /* Write offset 0x0A to 0x17 */
2379         buffer[0] = 0x0A;
2380         buffer[1] = 0x17;
2381         i2c_success = i2c_write(pipe_ctx, slave_address,
2382                         buffer, sizeof(buffer));
2383         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2384                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2385                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2386         if (!i2c_success)
2387                 goto i2c_write_fail;
2388
2389         /* Write offset 0x0B to 0xDA or 0xD8 */
2390         buffer[0] = 0x0B;
2391         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2392         i2c_success = i2c_write(pipe_ctx, slave_address,
2393                         buffer, sizeof(buffer));
2394         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2395                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2396                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2397         if (!i2c_success)
2398                 goto i2c_write_fail;
2399
2400         /* Write offset 0x0A to 0x17 */
2401         buffer[0] = 0x0A;
2402         buffer[1] = 0x17;
2403         i2c_success = i2c_write(pipe_ctx, slave_address,
2404                         buffer, sizeof(buffer));
2405         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2406                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2407                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2408         if (!i2c_success)
2409                 goto i2c_write_fail;
2410
2411         /* Write offset 0x0C to 0x1D or 0x91 */
2412         buffer[0] = 0x0C;
2413         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2414         i2c_success = i2c_write(pipe_ctx, slave_address,
2415                         buffer, sizeof(buffer));
2416         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2417                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2418                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2419         if (!i2c_success)
2420                 goto i2c_write_fail;
2421
2422         /* Write offset 0x0A to 0x17 */
2423         buffer[0] = 0x0A;
2424         buffer[1] = 0x17;
2425         i2c_success = i2c_write(pipe_ctx, slave_address,
2426                         buffer, sizeof(buffer));
2427         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2428                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2429                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2430         if (!i2c_success)
2431                 goto i2c_write_fail;
2432
2433
2434         if (is_vga_mode) {
2435                 /* Program additional settings if using 640x480 resolution */
2436
2437                 /* Write offset 0xFF to 0x01 */
2438                 buffer[0] = 0xff;
2439                 buffer[1] = 0x01;
2440                 i2c_success = i2c_write(pipe_ctx, slave_address,
2441                                 buffer, sizeof(buffer));
2442                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2443                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2444                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2445                 if (!i2c_success)
2446                         goto i2c_write_fail;
2447
2448                 /* Write offset 0x00 to 0x23 */
2449                 buffer[0] = 0x00;
2450                 buffer[1] = 0x23;
2451                 i2c_success = i2c_write(pipe_ctx, slave_address,
2452                                 buffer, sizeof(buffer));
2453                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2454                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2455                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2456                 if (!i2c_success)
2457                         goto i2c_write_fail;
2458
2459                 /* Write offset 0xff to 0x00 */
2460                 buffer[0] = 0xff;
2461                 buffer[1] = 0x00;
2462                 i2c_success = i2c_write(pipe_ctx, slave_address,
2463                                 buffer, sizeof(buffer));
2464                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2465                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2466                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2467                 if (!i2c_success)
2468                         goto i2c_write_fail;
2469         }
2470
2471         return;
2472
2473 i2c_write_fail:
2474         DC_LOG_DEBUG("Set default retimer failed");
2475 }
2476
2477 static void write_i2c_redriver_setting(
2478                 struct pipe_ctx *pipe_ctx,
2479                 bool is_over_340mhz)
2480 {
2481         uint8_t slave_address = (0xF0 >> 1);
2482         uint8_t buffer[16];
2483         bool i2c_success = false;
2484         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2485
2486         memset(&buffer, 0, sizeof(buffer));
2487
2488         // Program Slave Address for tuning single integrity
2489         buffer[3] = 0x4E;
2490         buffer[4] = 0x4E;
2491         buffer[5] = 0x4E;
2492         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2493
2494         i2c_success = i2c_write(pipe_ctx, slave_address,
2495                                         buffer, sizeof(buffer));
2496         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2497                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2498                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2499                 i2c_success = %d\n",
2500                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2501
2502         if (!i2c_success)
2503                 DC_LOG_DEBUG("Set redriver failed");
2504 }
2505
2506 static void disable_link(struct dc_link *link, enum signal_type signal)
2507 {
2508         /*
2509          * TODO: implement call for dp_set_hw_test_pattern
2510          * it is needed for compliance testing
2511          */
2512
2513         /* Here we need to specify that encoder output settings
2514          * need to be calculated as for the set mode,
2515          * it will lead to querying dynamic link capabilities
2516          * which should be done before enable output
2517          */
2518
2519         if (dc_is_dp_signal(signal)) {
2520                 /* SST DP, eDP */
2521 #if defined(CONFIG_DRM_AMD_DC_DCN)
2522                 struct dc_link_settings link_settings = link->cur_link_settings;
2523 #endif
2524                 if (dc_is_dp_sst_signal(signal))
2525                         dp_disable_link_phy(link, signal);
2526                 else
2527                         dp_disable_link_phy_mst(link, signal);
2528
2529                 if (dc_is_dp_sst_signal(signal) ||
2530                                 link->mst_stream_alloc_table.stream_count == 0) {
2531 #if defined(CONFIG_DRM_AMD_DC_DCN)
2532                         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
2533                                 dp_set_fec_enable(link, false);
2534                                 dp_set_fec_ready(link, false);
2535                         }
2536 #else
2537                         dp_set_fec_enable(link, false);
2538                         dp_set_fec_ready(link, false);
2539 #endif
2540                 }
2541         } else {
2542                 if (signal != SIGNAL_TYPE_VIRTUAL)
2543                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2544         }
2545
2546         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2547                 /* MST disable link only when no stream use the link */
2548                 if (link->mst_stream_alloc_table.stream_count <= 0)
2549                         link->link_status.link_active = false;
2550         } else {
2551                 link->link_status.link_active = false;
2552         }
2553 }
2554
2555 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2556 {
2557         struct dc_stream_state *stream = pipe_ctx->stream;
2558         struct dc_link *link = stream->link;
2559         enum dc_color_depth display_color_depth;
2560         enum engine_id eng_id;
2561         struct ext_hdmi_settings settings = {0};
2562         bool is_over_340mhz = false;
2563         bool is_vga_mode = (stream->timing.h_addressable == 640)
2564                         && (stream->timing.v_addressable == 480);
2565
2566         if (stream->phy_pix_clk == 0)
2567                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2568         if (stream->phy_pix_clk > 340000)
2569                 is_over_340mhz = true;
2570
2571         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2572                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2573                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2574                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2575                         /* DP159, Retimer settings */
2576                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2577
2578                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2579                                 write_i2c_retimer_setting(pipe_ctx,
2580                                                 is_vga_mode, is_over_340mhz, &settings);
2581                         } else {
2582                                 write_i2c_default_retimer_setting(pipe_ctx,
2583                                                 is_vga_mode, is_over_340mhz);
2584                         }
2585                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2586                         /* PI3EQX1204, Redriver settings */
2587                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2588                 }
2589         }
2590
2591         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2592                 dal_ddc_service_write_scdc_data(
2593                         stream->link->ddc,
2594                         stream->phy_pix_clk,
2595                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2596
2597         memset(&stream->link->cur_link_settings, 0,
2598                         sizeof(struct dc_link_settings));
2599
2600         display_color_depth = stream->timing.display_color_depth;
2601         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2602                 display_color_depth = COLOR_DEPTH_888;
2603
2604         link->link_enc->funcs->enable_tmds_output(
2605                         link->link_enc,
2606                         pipe_ctx->clock_source->id,
2607                         display_color_depth,
2608                         pipe_ctx->stream->signal,
2609                         stream->phy_pix_clk);
2610
2611         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2612                 dal_ddc_service_read_scdc_data(link->ddc);
2613 }
2614
2615 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2616 {
2617         struct dc_stream_state *stream = pipe_ctx->stream;
2618         struct dc_link *link = stream->link;
2619
2620         if (stream->phy_pix_clk == 0)
2621                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2622
2623         memset(&stream->link->cur_link_settings, 0,
2624                         sizeof(struct dc_link_settings));
2625
2626         link->link_enc->funcs->enable_lvds_output(
2627                         link->link_enc,
2628                         pipe_ctx->clock_source->id,
2629                         stream->phy_pix_clk);
2630
2631 }
2632
2633 /****************************enable_link***********************************/
2634 static enum dc_status enable_link(
2635                 struct dc_state *state,
2636                 struct pipe_ctx *pipe_ctx)
2637 {
2638         enum dc_status status = DC_ERROR_UNEXPECTED;
2639         struct dc_stream_state *stream = pipe_ctx->stream;
2640         struct dc_link *link = stream->link;
2641
2642         /* There's some scenarios where driver is unloaded with display
2643          * still enabled. When driver is reloaded, it may cause a display
2644          * to not light up if there is a mismatch between old and new
2645          * link settings. Need to call disable first before enabling at
2646          * new link settings.
2647          */
2648         if (link->link_status.link_active) {
2649                 disable_link(link, pipe_ctx->stream->signal);
2650         }
2651
2652         switch (pipe_ctx->stream->signal) {
2653         case SIGNAL_TYPE_DISPLAY_PORT:
2654                 status = enable_link_dp(state, pipe_ctx);
2655                 break;
2656         case SIGNAL_TYPE_EDP:
2657                 status = enable_link_edp(state, pipe_ctx);
2658                 break;
2659         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2660                 status = enable_link_dp_mst(state, pipe_ctx);
2661                 msleep(200);
2662                 break;
2663         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2664         case SIGNAL_TYPE_DVI_DUAL_LINK:
2665         case SIGNAL_TYPE_HDMI_TYPE_A:
2666                 enable_link_hdmi(pipe_ctx);
2667                 status = DC_OK;
2668                 break;
2669         case SIGNAL_TYPE_LVDS:
2670                 enable_link_lvds(pipe_ctx);
2671                 status = DC_OK;
2672                 break;
2673         case SIGNAL_TYPE_VIRTUAL:
2674                 status = DC_OK;
2675                 break;
2676         default:
2677                 break;
2678         }
2679
2680         if (status == DC_OK)
2681                 pipe_ctx->stream->link->link_status.link_active = true;
2682
2683         return status;
2684 }
2685
2686 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2687 {
2688
2689         uint32_t pxl_clk = timing->pix_clk_100hz;
2690
2691         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2692                 pxl_clk /= 2;
2693         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2694                 pxl_clk = pxl_clk * 2 / 3;
2695
2696         if (timing->display_color_depth == COLOR_DEPTH_101010)
2697                 pxl_clk = pxl_clk * 10 / 8;
2698         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2699                 pxl_clk = pxl_clk * 12 / 8;
2700
2701         return pxl_clk;
2702 }
2703
2704 static bool dp_active_dongle_validate_timing(
2705                 const struct dc_crtc_timing *timing,
2706                 const struct dpcd_caps *dpcd_caps)
2707 {
2708         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2709
2710         switch (dpcd_caps->dongle_type) {
2711         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2712         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2713         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2714                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2715                         return true;
2716                 else
2717                         return false;
2718         default:
2719                 break;
2720         }
2721
2722 #if defined(CONFIG_DRM_AMD_DC_DCN)
2723         if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
2724                         dongle_caps->extendedCapValid == true) {
2725 #else
2726         if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2727                 dongle_caps->extendedCapValid == false)
2728                 return true;
2729 #endif
2730
2731         /* Check Pixel Encoding */
2732         switch (timing->pixel_encoding) {
2733         case PIXEL_ENCODING_RGB:
2734         case PIXEL_ENCODING_YCBCR444:
2735                 break;
2736         case PIXEL_ENCODING_YCBCR422:
2737                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2738                         return false;
2739                 break;
2740         case PIXEL_ENCODING_YCBCR420:
2741                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2742                         return false;
2743                 break;
2744         default:
2745                 /* Invalid Pixel Encoding*/
2746                 return false;
2747         }
2748
2749         switch (timing->display_color_depth) {
2750         case COLOR_DEPTH_666:
2751         case COLOR_DEPTH_888:
2752                 /*888 and 666 should always be supported*/
2753                 break;
2754         case COLOR_DEPTH_101010:
2755                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2756                         return false;
2757                 break;
2758         case COLOR_DEPTH_121212:
2759                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2760                         return false;
2761                 break;
2762         case COLOR_DEPTH_141414:
2763         case COLOR_DEPTH_161616:
2764         default:
2765                 /* These color depths are currently not supported */
2766                 return false;
2767         }
2768
2769         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2770                 return false;
2771
2772 #if defined(CONFIG_DRM_AMD_DC_DCN)
2773         }
2774
2775         if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
2776                         dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
2777                         dongle_caps->dfp_cap_ext.supported) {
2778
2779                 if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
2780                         return false;
2781
2782                 if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
2783                         return false;
2784
2785                 if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
2786                         return false;
2787
2788                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
2789                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2790                                 return false;
2791                         if (timing->display_color_depth == COLOR_DEPTH_666 &&
2792                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
2793                                 return false;
2794                         else if (timing->display_color_depth == COLOR_DEPTH_888 &&
2795                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
2796                                 return false;
2797                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2798                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
2799                                 return false;
2800                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2801                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
2802                                 return false;
2803                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2804                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
2805                                 return false;
2806                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
2807                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2808                                 return false;
2809                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2810                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
2811                                 return false;
2812                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2813                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
2814                                 return false;
2815                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2816                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
2817                                 return false;
2818                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2819                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
2820                                 return false;
2821                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
2822                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2823                                 return false;
2824                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2825                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
2826                                 return false;
2827                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2828                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
2829                                 return false;
2830                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2831                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
2832                                 return false;
2833                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2834                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
2835                                 return false;
2836                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2837                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2838                                 return false;
2839                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2840                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
2841                                 return false;
2842                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2843                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
2844                                 return false;
2845                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2846                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
2847                                 return false;
2848                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2849                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
2850                                 return false;
2851                 }
2852         }
2853 #endif
2854
2855         return true;
2856 }
2857
2858 enum dc_status dc_link_validate_mode_timing(
2859                 const struct dc_stream_state *stream,
2860                 struct dc_link *link,
2861                 const struct dc_crtc_timing *timing)
2862 {
2863         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2864         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2865
2866         /* A hack to avoid failing any modes for EDID override feature on
2867          * topology change such as lower quality cable for DP or different dongle
2868          */
2869         if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2870                 return DC_OK;
2871
2872         /* Passive Dongle */
2873         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2874                 return DC_EXCEED_DONGLE_CAP;
2875
2876         /* Active Dongle*/
2877         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2878                 return DC_EXCEED_DONGLE_CAP;
2879
2880         switch (stream->signal) {
2881         case SIGNAL_TYPE_EDP:
2882         case SIGNAL_TYPE_DISPLAY_PORT:
2883                 if (!dp_validate_mode_timing(
2884                                 link,
2885                                 timing))
2886                         return DC_NO_DP_LINK_BANDWIDTH;
2887                 break;
2888
2889         default:
2890                 break;
2891         }
2892
2893         return DC_OK;
2894 }
2895
2896 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2897 {
2898         int i;
2899         struct dc *dc = NULL;
2900         struct abm *abm = NULL;
2901
2902         if (!link || !link->ctx)
2903                 return NULL;
2904
2905         dc = link->ctx->dc;
2906
2907         for (i = 0; i < MAX_PIPES; i++) {
2908                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2909                 struct dc_stream_state *stream = pipe_ctx.stream;
2910
2911                 if (stream && stream->link == link) {
2912                         abm = pipe_ctx.stream_res.abm;
2913                         break;
2914                 }
2915         }
2916         return abm;
2917 }
2918
2919 int dc_link_get_backlight_level(const struct dc_link *link)
2920 {
2921         struct abm *abm = get_abm_from_stream_res(link);
2922         struct panel_cntl *panel_cntl = link->panel_cntl;
2923         struct dc  *dc = link->ctx->dc;
2924         struct dmcu *dmcu = dc->res_pool->dmcu;
2925         bool fw_set_brightness = true;
2926
2927         if (dmcu)
2928                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2929
2930         if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
2931                 return panel_cntl->funcs->get_current_backlight(panel_cntl);
2932         else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
2933                 return (int) abm->funcs->get_current_backlight(abm);
2934         else
2935                 return DC_ERROR_UNEXPECTED;
2936 }
2937
2938 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
2939 {
2940         struct abm *abm = get_abm_from_stream_res(link);
2941
2942         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
2943                 return DC_ERROR_UNEXPECTED;
2944
2945         return (int) abm->funcs->get_target_backlight(abm);
2946 }
2947
2948 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
2949 {
2950         int i;
2951         struct dc *dc = link->ctx->dc;
2952         struct pipe_ctx *pipe_ctx = NULL;
2953
2954         for (i = 0; i < MAX_PIPES; i++) {
2955                 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
2956                         if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
2957                                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2958                                 break;
2959                         }
2960                 }
2961         }
2962
2963         return pipe_ctx;
2964 }
2965
2966 bool dc_link_set_backlight_level(const struct dc_link *link,
2967                 uint32_t backlight_pwm_u16_16,
2968                 uint32_t frame_ramp)
2969 {
2970         struct dc  *dc = link->ctx->dc;
2971
2972         DC_LOGGER_INIT(link->ctx->logger);
2973         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2974                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2975
2976         if (dc_is_embedded_signal(link->connector_signal)) {
2977                 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
2978
2979                 if (pipe_ctx) {
2980                         /* Disable brightness ramping when the display is blanked
2981                          * as it can hang the DMCU
2982                          */
2983                         if (pipe_ctx->plane_state == NULL)
2984                                 frame_ramp = 0;
2985                 } else {
2986                         return false;
2987                 }
2988
2989                 dc->hwss.set_backlight_level(
2990                                 pipe_ctx,
2991                                 backlight_pwm_u16_16,
2992                                 frame_ramp);
2993         }
2994         return true;
2995 }
2996
2997 bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
2998                 bool wait, bool force_static, const unsigned int *power_opts)
2999 {
3000         struct dc  *dc = link->ctx->dc;
3001         struct dmcu *dmcu = dc->res_pool->dmcu;
3002         struct dmub_psr *psr = dc->res_pool->psr;
3003         unsigned int panel_inst;
3004
3005         if (psr == NULL && force_static)
3006                 return false;
3007
3008         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3009                 return false;
3010
3011         /* Set power optimization flag */
3012         if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
3013                 link->psr_settings.psr_power_opt = *power_opts;
3014
3015                 if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
3016                         psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
3017         }
3018
3019         /* Enable or Disable PSR */
3020         if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
3021                 link->psr_settings.psr_allow_active = *allow_active;
3022
3023 #if defined(CONFIG_DRM_AMD_DC_DCN)
3024                 if (!link->psr_settings.psr_allow_active)
3025                         dc_z10_restore(dc);
3026 #endif
3027
3028                 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
3029                         if (force_static && psr->funcs->psr_force_static)
3030                                 psr->funcs->psr_force_static(psr, panel_inst);
3031                         psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
3032                 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
3033                         link->psr_settings.psr_feature_enabled)
3034                         dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
3035                 else
3036                         return false;
3037         }
3038
3039         return true;
3040 }
3041
3042 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
3043 {
3044         struct dc  *dc = link->ctx->dc;
3045         struct dmcu *dmcu = dc->res_pool->dmcu;
3046         struct dmub_psr *psr = dc->res_pool->psr;
3047         unsigned int panel_inst;
3048
3049         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3050                 return false;
3051
3052         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3053                 psr->funcs->psr_get_state(psr, state, panel_inst);
3054         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
3055                 dmcu->funcs->get_psr_state(dmcu, state);
3056
3057         return true;
3058 }
3059
3060 static inline enum physical_phy_id
3061 transmitter_to_phy_id(enum transmitter transmitter_value)
3062 {
3063         switch (transmitter_value) {
3064         case TRANSMITTER_UNIPHY_A:
3065                 return PHYLD_0;
3066         case TRANSMITTER_UNIPHY_B:
3067                 return PHYLD_1;
3068         case TRANSMITTER_UNIPHY_C:
3069                 return PHYLD_2;
3070         case TRANSMITTER_UNIPHY_D:
3071                 return PHYLD_3;
3072         case TRANSMITTER_UNIPHY_E:
3073                 return PHYLD_4;
3074         case TRANSMITTER_UNIPHY_F:
3075                 return PHYLD_5;
3076         case TRANSMITTER_NUTMEG_CRT:
3077                 return PHYLD_6;
3078         case TRANSMITTER_TRAVIS_CRT:
3079                 return PHYLD_7;
3080         case TRANSMITTER_TRAVIS_LCD:
3081                 return PHYLD_8;
3082         case TRANSMITTER_UNIPHY_G:
3083                 return PHYLD_9;
3084         case TRANSMITTER_COUNT:
3085                 return PHYLD_COUNT;
3086         case TRANSMITTER_UNKNOWN:
3087                 return PHYLD_UNKNOWN;
3088         default:
3089                 WARN_ONCE(1, "Unknown transmitter value %d\n",
3090                           transmitter_value);
3091                 return PHYLD_UNKNOWN;
3092         }
3093 }
3094
3095 bool dc_link_setup_psr(struct dc_link *link,
3096                 const struct dc_stream_state *stream, struct psr_config *psr_config,
3097                 struct psr_context *psr_context)
3098 {
3099         struct dc *dc;
3100         struct dmcu *dmcu;
3101         struct dmub_psr *psr;
3102         int i;
3103         unsigned int panel_inst;
3104         /* updateSinkPsrDpcdConfig*/
3105         union dpcd_psr_configuration psr_configuration;
3106
3107         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
3108
3109         if (!link)
3110                 return false;
3111
3112         dc = link->ctx->dc;
3113         dmcu = dc->res_pool->dmcu;
3114         psr = dc->res_pool->psr;
3115
3116         if (!dmcu && !psr)
3117                 return false;
3118
3119         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3120                 return false;
3121
3122
3123         memset(&psr_configuration, 0, sizeof(psr_configuration));
3124
3125         psr_configuration.bits.ENABLE                    = 1;
3126         psr_configuration.bits.CRC_VERIFICATION          = 1;
3127         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
3128                         psr_config->psr_frame_capture_indication_req;
3129
3130         /* Check for PSR v2*/
3131         if (psr_config->psr_version == 0x2) {
3132                 /* For PSR v2 selective update.
3133                  * Indicates whether sink should start capturing
3134                  * immediately following active scan line,
3135                  * or starting with the 2nd active scan line.
3136                  */
3137                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
3138                 /*For PSR v2, determines whether Sink should generate
3139                  * IRQ_HPD when CRC mismatch is detected.
3140                  */
3141                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
3142         }
3143
3144         dm_helpers_dp_write_dpcd(
3145                 link->ctx,
3146                 link,
3147                 368,
3148                 &psr_configuration.raw,
3149                 sizeof(psr_configuration.raw));
3150
3151         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
3152         psr_context->transmitterId = link->link_enc->transmitter;
3153         psr_context->engineId = link->link_enc->preferred_engine;
3154
3155         for (i = 0; i < MAX_PIPES; i++) {
3156                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
3157                                 == stream) {
3158                         /* dmcu -1 for all controller id values,
3159                          * therefore +1 here
3160                          */
3161                         psr_context->controllerId =
3162                                 dc->current_state->res_ctx.
3163                                 pipe_ctx[i].stream_res.tg->inst + 1;
3164                         break;
3165                 }
3166         }
3167
3168         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
3169         psr_context->phyType = PHY_TYPE_UNIPHY;
3170         /*PhyId is associated with the transmitter id*/
3171         psr_context->smuPhyId =
3172                 transmitter_to_phy_id(link->link_enc->transmitter);
3173
3174         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
3175         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
3176                                         timing.pix_clk_100hz * 100),
3177                                         stream->timing.v_total),
3178                                         stream->timing.h_total);
3179
3180         psr_context->psrSupportedDisplayConfig = true;
3181         psr_context->psrExitLinkTrainingRequired =
3182                 psr_config->psr_exit_link_training_required;
3183         psr_context->sdpTransmitLineNumDeadline =
3184                 psr_config->psr_sdp_transmit_line_num_deadline;
3185         psr_context->psrFrameCaptureIndicationReq =
3186                 psr_config->psr_frame_capture_indication_req;
3187
3188         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
3189
3190         psr_context->numberOfControllers =
3191                         link->dc->res_pool->timing_generator_count;
3192
3193         psr_context->rfb_update_auto_en = true;
3194
3195         /* 2 frames before enter PSR. */
3196         psr_context->timehyst_frames = 2;
3197         /* half a frame
3198          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
3199          */
3200         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
3201         psr_context->aux_repeats = 10;
3202
3203         psr_context->psr_level.u32all = 0;
3204
3205         /*skip power down the single pipe since it blocks the cstate*/
3206 #if defined(CONFIG_DRM_AMD_DC_DCN)
3207         if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
3208                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3209                 if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10)
3210                         psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
3211         }
3212 #else
3213         if (link->ctx->asic_id.chip_family >= FAMILY_RV)
3214                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3215 #endif
3216
3217         /* SMU will perform additional powerdown sequence.
3218          * For unsupported ASICs, set psr_level flag to skip PSR
3219          *  static screen notification to SMU.
3220          *  (Always set for DAL2, did not check ASIC)
3221          */
3222         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
3223         psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
3224
3225         /* Complete PSR entry before aborting to prevent intermittent
3226          * freezes on certain eDPs
3227          */
3228         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
3229
3230         /* Controls additional delay after remote frame capture before
3231          * continuing power down, default = 0
3232          */
3233         psr_context->frame_delay = 0;
3234
3235         if (psr)
3236                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
3237                         link, psr_context, panel_inst);
3238         else
3239                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
3240
3241         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
3242          * should not happen since firmware should be running at this point
3243          */
3244         if (link->psr_settings.psr_feature_enabled == 0)
3245                 ASSERT(0);
3246
3247         return true;
3248
3249 }
3250
3251 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
3252 {
3253         struct dc  *dc = link->ctx->dc;
3254         struct dmub_psr *psr = dc->res_pool->psr;
3255         unsigned int panel_inst;
3256
3257         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3258                 return;
3259
3260         /* PSR residency measurements only supported on DMCUB */
3261         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3262                 psr->funcs->psr_get_residency(psr, residency, panel_inst);
3263         else
3264                 *residency = 0;
3265 }
3266
3267 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
3268 {
3269         return &link->link_status;
3270 }
3271
3272 void core_link_resume(struct dc_link *link)
3273 {
3274         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
3275                 program_hpd_filter(link);
3276 }
3277
3278 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
3279 {
3280         struct fixed31_32 mbytes_per_sec;
3281         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
3282                         &stream->link->cur_link_settings);
3283         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
3284
3285         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
3286
3287         return dc_fixpt_div_int(mbytes_per_sec, 54);
3288 }
3289
3290 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
3291 {
3292         struct fixed31_32 peak_kbps;
3293         uint32_t numerator = 0;
3294         uint32_t denominator = 1;
3295
3296         /*
3297          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
3298          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
3299          * common multiplier to render an integer PBN for all link rate/lane
3300          * counts combinations
3301          * calculate
3302          * peak_kbps *= (1006/1000)
3303          * peak_kbps *= (64/54)
3304          * peak_kbps *= 8    convert to bytes
3305          */
3306
3307         numerator = 64 * PEAK_FACTOR_X1000;
3308         denominator = 54 * 8 * 1000 * 1000;
3309         kbps *= numerator;
3310         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
3311
3312         return peak_kbps;
3313 }
3314
3315 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
3316 {
3317         uint64_t kbps;
3318
3319         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
3320         return get_pbn_from_bw_in_kbps(kbps);
3321 }
3322
3323 static void update_mst_stream_alloc_table(
3324         struct dc_link *link,
3325         struct stream_encoder *stream_enc,
3326 #if defined(CONFIG_DRM_AMD_DC_DCN)
3327         struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc?
3328 #endif
3329         const struct dp_mst_stream_allocation_table *proposed_table)
3330 {
3331         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
3332         struct link_mst_stream_allocation *dc_alloc;
3333
3334         int i;
3335         int j;
3336
3337         /* if DRM proposed_table has more than one new payload */
3338         ASSERT(proposed_table->stream_count -
3339                         link->mst_stream_alloc_table.stream_count < 2);
3340
3341         /* copy proposed_table to link, add stream encoder */
3342         for (i = 0; i < proposed_table->stream_count; i++) {
3343
3344                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
3345                         dc_alloc =
3346                         &link->mst_stream_alloc_table.stream_allocations[j];
3347
3348                         if (dc_alloc->vcp_id ==
3349                                 proposed_table->stream_allocations[i].vcp_id) {
3350
3351                                 work_table[i] = *dc_alloc;
3352                                 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
3353                                 break; /* exit j loop */
3354                         }
3355                 }
3356
3357                 /* new vcp_id */
3358                 if (j == link->mst_stream_alloc_table.stream_count) {
3359                         work_table[i].vcp_id =
3360                                 proposed_table->stream_allocations[i].vcp_id;
3361                         work_table[i].slot_count =
3362                                 proposed_table->stream_allocations[i].slot_count;
3363                         work_table[i].stream_enc = stream_enc;
3364 #if defined(CONFIG_DRM_AMD_DC_DCN)
3365                         work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc;
3366 #endif
3367                 }
3368         }
3369
3370         /* update link->mst_stream_alloc_table with work_table */
3371         link->mst_stream_alloc_table.stream_count =
3372                         proposed_table->stream_count;
3373         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
3374                 link->mst_stream_alloc_table.stream_allocations[i] =
3375                                 work_table[i];
3376 }
3377 #if defined(CONFIG_DRM_AMD_DC_DCN)
3378 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
3379 {
3380         const uint32_t VCP_Y_PRECISION = 1000;
3381         uint64_t vcp_x, vcp_y;
3382
3383         // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
3384         avg_time_slots_per_mtp = dc_fixpt_add(
3385                         avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));
3386
3387         vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
3388         vcp_y = dc_fixpt_floor(
3389                         dc_fixpt_mul_int(
3390                                 dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
3391                                 VCP_Y_PRECISION));
3392
3393         if (link->type == dc_connection_mst_branch)
3394                 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
3395                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3396         else
3397                 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
3398                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3399 }
3400
3401 /*
3402  * Payload allocation/deallocation for SST introduced in DP2.0
3403  */
3404 enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx, bool allocate)
3405 {
3406         struct dc_stream_state *stream = pipe_ctx->stream;
3407         struct dc_link *link = stream->link;
3408         struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3409         struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3410         struct link_mst_stream_allocation_table proposed_table = {0};
3411         struct fixed31_32 avg_time_slots_per_mtp;
3412         DC_LOGGER_INIT(link->ctx->logger);
3413
3414         /* slot X.Y for SST payload deallocate */
3415         if (!allocate) {
3416                 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3417
3418                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3419
3420                 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3421                                 hpo_dp_link_encoder,
3422                                 hpo_dp_stream_encoder->inst,
3423                                 avg_time_slots_per_mtp);
3424         }
3425
3426         /* calculate VC payload and update branch with new payload allocation table*/
3427         if (!dpcd_write_128b_132b_sst_payload_allocation_table(
3428                         stream,
3429                         link,
3430                         &proposed_table,
3431                         allocate)) {
3432                 DC_LOG_ERROR("SST Update Payload: Failed to update "
3433                                                 "allocation table for "
3434                                                 "pipe idx: %d\n",
3435                                                 pipe_ctx->pipe_idx);
3436         }
3437
3438         proposed_table.stream_allocations[0].hpo_dp_stream_enc = hpo_dp_stream_encoder;
3439
3440         ASSERT(proposed_table.stream_count == 1);
3441
3442         //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id
3443         DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p      "
3444                 "vcp_id: %d      "
3445                 "slot_count: %d\n",
3446                 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc,
3447                 proposed_table.stream_allocations[0].vcp_id,
3448                 proposed_table.stream_allocations[0].slot_count);
3449
3450         /* program DP source TX for payload */
3451         hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3452                         hpo_dp_link_encoder,
3453                         &proposed_table);
3454
3455         /* poll for ACT handled */
3456         if (!dpcd_poll_for_allocation_change_trigger(link)) {
3457                 // Failures will result in blackscreen and errors logged
3458                 BREAK_TO_DEBUGGER();
3459         }
3460
3461         /* slot X.Y for SST payload allocate */
3462         if (allocate) {
3463                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
3464
3465                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3466
3467                 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3468                                 hpo_dp_link_encoder,
3469                                 hpo_dp_stream_encoder->inst,
3470                                 avg_time_slots_per_mtp);
3471         }
3472
3473         /* Always return DC_OK.
3474          * If part of sequence fails, log failure(s) and show blackscreen
3475          */
3476         return DC_OK;
3477 }
3478 #endif
3479
3480 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
3481  * because stream_encoder is not exposed to dm
3482  */
3483 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3484 {
3485         struct dc_stream_state *stream = pipe_ctx->stream;
3486         struct dc_link *link = stream->link;
3487         struct link_encoder *link_encoder = NULL;
3488         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3489 #if defined(CONFIG_DRM_AMD_DC_DCN)
3490         struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3491         struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3492 #endif
3493         struct dp_mst_stream_allocation_table proposed_table = {0};
3494         struct fixed31_32 avg_time_slots_per_mtp;
3495         struct fixed31_32 pbn;
3496         struct fixed31_32 pbn_per_slot;
3497         int i;
3498         enum act_return_status ret;
3499         DC_LOGGER_INIT(link->ctx->logger);
3500
3501         /* Link encoder may have been dynamically assigned to non-physical display endpoint. */
3502         if (link->ep_type == DISPLAY_ENDPOINT_PHY)
3503                 link_encoder = link->link_enc;
3504         else if (link->dc->res_pool->funcs->link_encs_assign)
3505                 link_encoder = link_enc_cfg_get_link_enc_used_by_stream(pipe_ctx->stream->ctx->dc, stream);
3506         ASSERT(link_encoder);
3507
3508         /* enable_link_dp_mst already check link->enabled_stream_count
3509          * and stream is in link->stream[]. This is called during set mode,
3510          * stream_enc is available.
3511          */
3512
3513         /* get calculate VC payload for stream: stream_alloc */
3514         if (dm_helpers_dp_mst_write_payload_allocation_table(
3515                 stream->ctx,
3516                 stream,
3517                 &proposed_table,
3518                 true)) {
3519                 update_mst_stream_alloc_table(
3520 #if defined(CONFIG_DRM_AMD_DC_DCN)
3521                                         link,
3522                                         pipe_ctx->stream_res.stream_enc,
3523                                         pipe_ctx->stream_res.hpo_dp_stream_enc,
3524                                         &proposed_table);
3525 #else
3526                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3527 #endif
3528         }
3529         else
3530                 DC_LOG_WARNING("Failed to update"
3531                                 "MST allocation table for"
3532                                 "pipe idx:%d\n",
3533                                 pipe_ctx->pipe_idx);
3534
3535         DC_LOG_MST("%s  "
3536                         "stream_count: %d: \n ",
3537                         __func__,
3538                         link->mst_stream_alloc_table.stream_count);
3539
3540         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3541 #if defined(CONFIG_DRM_AMD_DC_DCN)
3542                 DC_LOG_MST("stream_enc[%d]: %p      "
3543                 "stream[%d].hpo_dp_stream_enc: %p      "
3544                 "stream[%d].vcp_id: %d      "
3545                 "stream[%d].slot_count: %d\n",
3546                 i,
3547                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3548                 i,
3549                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3550                 i,
3551                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3552                 i,
3553                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3554 #else
3555                 DC_LOG_MST("stream_enc[%d]: %p      "
3556                 "stream[%d].vcp_id: %d      "
3557                 "stream[%d].slot_count: %d\n",
3558                 i,
3559                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3560                 i,
3561                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3562                 i,
3563                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3564 #endif
3565         }
3566
3567         ASSERT(proposed_table.stream_count > 0);
3568
3569         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3570                 static enum dc_status status;
3571                 uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;
3572
3573                 for (i = 0; i < link->mst_stream_alloc_table.stream_count; i++)
3574                         mst_alloc_slots += link->mst_stream_alloc_table.stream_allocations[i].slot_count;
3575
3576                 status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,
3577                         mst_alloc_slots, &prev_mst_slots_in_use);
3578                 ASSERT(status == DC_OK);
3579                 DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n",
3580                                 status, mst_alloc_slots, prev_mst_slots_in_use);
3581         }
3582
3583         /* program DP source TX for payload */
3584 #if defined(CONFIG_DRM_AMD_DC_DCN)
3585         switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3586         case DP_8b_10b_ENCODING:
3587                 link_encoder->funcs->update_mst_stream_allocation_table(
3588                         link_encoder,
3589                         &link->mst_stream_alloc_table);
3590                 break;
3591         case DP_128b_132b_ENCODING:
3592                 hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3593                                 hpo_dp_link_encoder,
3594                                 &link->mst_stream_alloc_table);
3595                 break;
3596         case DP_UNKNOWN_ENCODING:
3597                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3598                 return DC_ERROR_UNEXPECTED;
3599         }
3600 #else
3601         link_encoder->funcs->update_mst_stream_allocation_table(
3602                 link_encoder,
3603                 &link->mst_stream_alloc_table);
3604 #endif
3605
3606         /* send down message */
3607         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3608                         stream->ctx,
3609                         stream);
3610
3611         if (ret != ACT_LINK_LOST) {
3612                 dm_helpers_dp_mst_send_payload_allocation(
3613                                 stream->ctx,
3614                                 stream,
3615                                 true);
3616         }
3617
3618         /* slot X.Y for only current stream */
3619         pbn_per_slot = get_pbn_per_slot(stream);
3620         if (pbn_per_slot.value == 0) {
3621                 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3622                 return DC_UNSUPPORTED_VALUE;
3623         }
3624         pbn = get_pbn_from_timing(pipe_ctx);
3625         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3626
3627 #if defined(CONFIG_DRM_AMD_DC_DCN)
3628         switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3629         case DP_8b_10b_ENCODING:
3630                 stream_encoder->funcs->set_throttled_vcp_size(
3631                         stream_encoder,
3632                         avg_time_slots_per_mtp);
3633                 break;
3634         case DP_128b_132b_ENCODING:
3635                 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3636                                 hpo_dp_link_encoder,
3637                                 hpo_dp_stream_encoder->inst,
3638                                 avg_time_slots_per_mtp);
3639                 break;
3640         case DP_UNKNOWN_ENCODING:
3641                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3642                 return DC_ERROR_UNEXPECTED;
3643         }
3644 #else
3645         stream_encoder->funcs->set_throttled_vcp_size(
3646                 stream_encoder,
3647                 avg_time_slots_per_mtp);
3648 #endif
3649
3650         return DC_OK;
3651
3652 }
3653
3654 #if defined(CONFIG_DRM_AMD_DC_DCN)
3655 enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3656 {
3657         struct dc_stream_state *stream = pipe_ctx->stream;
3658         struct dc_link *link = stream->link;
3659         struct fixed31_32 avg_time_slots_per_mtp;
3660         struct fixed31_32 pbn;
3661         struct fixed31_32 pbn_per_slot;
3662         struct link_encoder *link_encoder = link->link_enc;
3663         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3664         struct dp_mst_stream_allocation_table proposed_table = {0};
3665         uint8_t i;
3666         enum act_return_status ret;
3667         DC_LOGGER_INIT(link->ctx->logger);
3668
3669         /* decrease throttled vcp size */
3670         pbn_per_slot = get_pbn_per_slot(stream);
3671         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3672         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3673
3674         stream_encoder->funcs->set_throttled_vcp_size(
3675                                 stream_encoder,
3676                                 avg_time_slots_per_mtp);
3677
3678         /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3679         dm_helpers_dp_mst_send_payload_allocation(
3680                         stream->ctx,
3681                         stream,
3682                         true);
3683
3684         /* notify immediate branch device table update */
3685         if (dm_helpers_dp_mst_write_payload_allocation_table(
3686                         stream->ctx,
3687                         stream,
3688                         &proposed_table,
3689                         true)) {
3690                 /* update mst stream allocation table software state */
3691                 update_mst_stream_alloc_table(
3692                                 link,
3693                                 pipe_ctx->stream_res.stream_enc,
3694                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3695                                 &proposed_table);
3696         } else {
3697                 DC_LOG_WARNING("Failed to update"
3698                                 "MST allocation table for"
3699                                 "pipe idx:%d\n",
3700                                 pipe_ctx->pipe_idx);
3701         }
3702
3703         DC_LOG_MST("%s  "
3704                         "stream_count: %d: \n ",
3705                         __func__,
3706                         link->mst_stream_alloc_table.stream_count);
3707
3708         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3709                 DC_LOG_MST("stream_enc[%d]: %p      "
3710                                 "stream[%d].vcp_id: %d      "
3711                                 "stream[%d].slot_count: %d\n",
3712                                 i,
3713                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3714                                 i,
3715                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3716                                 i,
3717                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3718         }
3719
3720         ASSERT(proposed_table.stream_count > 0);
3721
3722         /* update mst stream allocation table hardware state */
3723         link_encoder->funcs->update_mst_stream_allocation_table(
3724                         link_encoder,
3725                         &link->mst_stream_alloc_table);
3726
3727         /* poll for immediate branch device ACT handled */
3728         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3729                         stream->ctx,
3730                         stream);
3731
3732         return DC_OK;
3733 }
3734
3735 enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3736 {
3737         struct dc_stream_state *stream = pipe_ctx->stream;
3738         struct dc_link *link = stream->link;
3739         struct fixed31_32 avg_time_slots_per_mtp;
3740         struct fixed31_32 pbn;
3741         struct fixed31_32 pbn_per_slot;
3742         struct link_encoder *link_encoder = link->link_enc;
3743         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3744         struct dp_mst_stream_allocation_table proposed_table = {0};
3745         uint8_t i;
3746         enum act_return_status ret;
3747         DC_LOGGER_INIT(link->ctx->logger);
3748
3749         /* notify immediate branch device table update */
3750         if (dm_helpers_dp_mst_write_payload_allocation_table(
3751                                 stream->ctx,
3752                                 stream,
3753                                 &proposed_table,
3754                                 true)) {
3755                 /* update mst stream allocation table software state */
3756                 update_mst_stream_alloc_table(
3757                                 link,
3758                                 pipe_ctx->stream_res.stream_enc,
3759                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3760                                 &proposed_table);
3761         }
3762
3763         DC_LOG_MST("%s  "
3764                         "stream_count: %d: \n ",
3765                         __func__,
3766                         link->mst_stream_alloc_table.stream_count);
3767
3768         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3769                 DC_LOG_MST("stream_enc[%d]: %p      "
3770                                 "stream[%d].vcp_id: %d      "
3771                                 "stream[%d].slot_count: %d\n",
3772                                 i,
3773                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3774                                 i,
3775                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3776                                 i,
3777                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3778         }
3779
3780         ASSERT(proposed_table.stream_count > 0);
3781
3782         /* update mst stream allocation table hardware state */
3783         link_encoder->funcs->update_mst_stream_allocation_table(
3784                         link_encoder,
3785                         &link->mst_stream_alloc_table);
3786
3787         /* poll for immediate branch device ACT handled */
3788         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3789                         stream->ctx,
3790                         stream);
3791
3792         if (ret != ACT_LINK_LOST) {
3793                 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3794                 dm_helpers_dp_mst_send_payload_allocation(
3795                                 stream->ctx,
3796                                 stream,
3797                                 true);
3798         }
3799
3800         /* increase throttled vcp size */
3801         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3802         pbn_per_slot = get_pbn_per_slot(stream);
3803         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3804
3805         stream_encoder->funcs->set_throttled_vcp_size(
3806                                 stream_encoder,
3807                                 avg_time_slots_per_mtp);
3808
3809         return DC_OK;
3810 }
3811 #endif
3812
3813 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3814 {
3815         struct dc_stream_state *stream = pipe_ctx->stream;
3816         struct dc_link *link = stream->link;
3817         struct link_encoder *link_encoder = NULL;
3818         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3819 #if defined(CONFIG_DRM_AMD_DC_DCN)
3820         struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3821         struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3822 #endif
3823         struct dp_mst_stream_allocation_table proposed_table = {0};
3824         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3825         int i;
3826         bool mst_mode = (link->type == dc_connection_mst_branch);
3827         DC_LOGGER_INIT(link->ctx->logger);
3828
3829         /* Link encoder may have been dynamically assigned to non-physical display endpoint. */
3830         if (link->ep_type == DISPLAY_ENDPOINT_PHY)
3831                 link_encoder = link->link_enc;
3832         else if (link->dc->res_pool->funcs->link_encs_assign)
3833                 link_encoder = link_enc_cfg_get_link_enc_used_by_stream(pipe_ctx->stream->ctx->dc, stream);
3834         ASSERT(link_encoder);
3835
3836         /* deallocate_mst_payload is called before disable link. When mode or
3837          * disable/enable monitor, new stream is created which is not in link
3838          * stream[] yet. For this, payload is not allocated yet, so de-alloc
3839          * should not done. For new mode set, map_resources will get engine
3840          * for new stream, so stream_enc->id should be validated until here.
3841          */
3842
3843         /* slot X.Y */
3844 #if defined(CONFIG_DRM_AMD_DC_DCN)
3845         switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3846         case DP_8b_10b_ENCODING:
3847                 stream_encoder->funcs->set_throttled_vcp_size(
3848                         stream_encoder,
3849                         avg_time_slots_per_mtp);
3850                 break;
3851         case DP_128b_132b_ENCODING:
3852                 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3853                                 hpo_dp_link_encoder,
3854                                 hpo_dp_stream_encoder->inst,
3855                                 avg_time_slots_per_mtp);
3856                 break;
3857         case DP_UNKNOWN_ENCODING:
3858                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3859                 return DC_ERROR_UNEXPECTED;
3860         }
3861 #else
3862         stream_encoder->funcs->set_throttled_vcp_size(
3863                 stream_encoder,
3864                 avg_time_slots_per_mtp);
3865 #endif
3866
3867         /* TODO: which component is responsible for remove payload table? */
3868         if (mst_mode) {
3869                 if (dm_helpers_dp_mst_write_payload_allocation_table(
3870                                 stream->ctx,
3871                                 stream,
3872                                 &proposed_table,
3873                                 false)) {
3874
3875 #if defined(CONFIG_DRM_AMD_DC_DCN)
3876                         update_mst_stream_alloc_table(
3877                                                 link,
3878                                                 pipe_ctx->stream_res.stream_enc,
3879                                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3880                                                 &proposed_table);
3881 #else
3882                         update_mst_stream_alloc_table(
3883                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3884 #endif
3885                 }
3886                 else {
3887                                 DC_LOG_WARNING("Failed to update"
3888                                                 "MST allocation table for"
3889                                                 "pipe idx:%d\n",
3890                                                 pipe_ctx->pipe_idx);
3891                 }
3892         }
3893
3894         DC_LOG_MST("%s"
3895                         "stream_count: %d: ",
3896                         __func__,
3897                         link->mst_stream_alloc_table.stream_count);
3898
3899         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3900 #if defined(CONFIG_DRM_AMD_DC_DCN)
3901                 DC_LOG_MST("stream_enc[%d]: %p      "
3902                 "stream[%d].hpo_dp_stream_enc: %p      "
3903                 "stream[%d].vcp_id: %d      "
3904                 "stream[%d].slot_count: %d\n",
3905                 i,
3906                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3907                 i,
3908                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3909                 i,
3910                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3911                 i,
3912                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3913 #else
3914                 DC_LOG_MST("stream_enc[%d]: %p      "
3915                 "stream[%d].vcp_id: %d      "
3916                 "stream[%d].slot_count: %d\n",
3917                 i,
3918                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3919                 i,
3920                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3921                 i,
3922                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3923 #endif
3924         }
3925
3926         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3927                 enum dc_status status;
3928                 uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;
3929
3930                 for (i = 0; i < link->mst_stream_alloc_table.stream_count; i++)
3931                         mst_alloc_slots += link->mst_stream_alloc_table.stream_allocations[i].slot_count;
3932
3933                 status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,
3934                         mst_alloc_slots, &prev_mst_slots_in_use);
3935                 ASSERT(status != DC_NOT_SUPPORTED);
3936                 DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n",
3937                                 status, mst_alloc_slots, prev_mst_slots_in_use);
3938         }
3939
3940 #if defined(CONFIG_DRM_AMD_DC_DCN)
3941         switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3942         case DP_8b_10b_ENCODING:
3943                 link_encoder->funcs->update_mst_stream_allocation_table(
3944                         link_encoder,
3945                         &link->mst_stream_alloc_table);
3946                 break;
3947         case DP_128b_132b_ENCODING:
3948                 hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3949                                 hpo_dp_link_encoder,
3950                                 &link->mst_stream_alloc_table);
3951                 break;
3952         case DP_UNKNOWN_ENCODING:
3953                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3954                 return DC_ERROR_UNEXPECTED;
3955         }
3956 #else
3957         link_encoder->funcs->update_mst_stream_allocation_table(
3958                 link_encoder,
3959                 &link->mst_stream_alloc_table);
3960 #endif
3961
3962         if (mst_mode) {
3963                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3964                         stream->ctx,
3965                         stream);
3966
3967                 dm_helpers_dp_mst_send_payload_allocation(
3968                         stream->ctx,
3969                         stream,
3970                         false);
3971         }
3972
3973         return DC_OK;
3974 }
3975
3976
3977 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3978 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3979 {
3980         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3981 #if defined(CONFIG_DRM_AMD_DC_DCN)
3982         struct link_encoder *link_enc = NULL;
3983 #endif
3984
3985         if (cp_psp && cp_psp->funcs.update_stream_config) {
3986                 struct cp_psp_stream_config config = {0};
3987                 enum dp_panel_mode panel_mode =
3988                                 dp_get_panel_mode(pipe_ctx->stream->link);
3989
3990                 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3991                 /*stream_enc_inst*/
3992                 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3993                 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
3994 #if defined(CONFIG_DRM_AMD_DC_DCN)
3995                 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
3996
3997                 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY ||
3998                                 pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3999                         link_enc = pipe_ctx->stream->link->link_enc;
4000                         config.dio_output_type = pipe_ctx->stream->link->ep_type;
4001                         config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4002                         if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY)
4003                                 link_enc = pipe_ctx->stream->link->link_enc;
4004                         else if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
4005                                 if (pipe_ctx->stream->link->dc->res_pool->funcs->link_encs_assign) {
4006                                         link_enc = link_enc_cfg_get_link_enc_used_by_stream(
4007                                                         pipe_ctx->stream->ctx->dc,
4008                                                         pipe_ctx->stream);
4009                         }
4010                         ASSERT(link_enc);
4011
4012                         // Initialize PHY ID with ABCDE - 01234 mapping except when it is B0
4013                         config.phy_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4014
4015                         // Add flag to guard new A0 DIG mapping
4016                         if (pipe_ctx->stream->ctx->dc->enable_c20_dtm_b0 == true &&
4017                                         pipe_ctx->stream->link->dc->ctx->dce_version == DCN_VERSION_3_1) {
4018                                 config.dig_be = link_enc->preferred_engine;
4019                                 config.dio_output_type = pipe_ctx->stream->link->ep_type;
4020                                 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4021                         } else {
4022                                 config.dio_output_type = 0;
4023                                 config.dio_output_idx = 0;
4024                         }
4025
4026                         // Add flag to guard B0 implementation
4027                         if (pipe_ctx->stream->ctx->dc->enable_c20_dtm_b0 == true &&
4028                                         link_enc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
4029                                 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
4030                                         // enum ID 1-4 maps to DPIA PHY ID 0-3
4031                                         config.phy_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1;
4032                                 } else {  // for non DPIA mode over B0, ABCDE maps to 01564
4033
4034                                         switch (link_enc->transmitter) {
4035                                         case TRANSMITTER_UNIPHY_A:
4036                                                 config.phy_idx = 0;
4037                                                 break;
4038                                         case TRANSMITTER_UNIPHY_B:
4039                                                 config.phy_idx = 1;
4040                                                 break;
4041                                         case TRANSMITTER_UNIPHY_C:
4042                                                 config.phy_idx = 5;
4043                                                 break;
4044                                         case TRANSMITTER_UNIPHY_D:
4045                                                 config.phy_idx = 6;
4046                                                 break;
4047                                         case TRANSMITTER_UNIPHY_E:
4048                                                 config.phy_idx = 4;
4049                                                 break;
4050                                         default:
4051                                                 config.phy_idx = 0;
4052                                                 break;
4053                                         }
4054
4055                                 }
4056                         }
4057                 } else if (pipe_ctx->stream->link->dc->res_pool->funcs->link_encs_assign) {
4058                         link_enc = link_enc_cfg_get_link_enc_used_by_stream(
4059                                         pipe_ctx->stream->ctx->dc,
4060                                         pipe_ctx->stream);
4061                         config.phy_idx = 0; /* Clear phy_idx for non-physical display endpoints. */
4062                 }
4063                 ASSERT(link_enc);
4064                 if (link_enc)
4065                         config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4066                 if (is_dp_128b_132b_signal(pipe_ctx)) {
4067                         config.stream_enc_idx = pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
4068                         config.link_enc_idx = pipe_ctx->stream->link->hpo_dp_link_enc->inst;
4069                         config.dp2_enabled = 1;
4070                 }
4071 #endif
4072                 config.dpms_off = dpms_off;
4073                 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
4074                 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
4075                 config.mst_enabled = (pipe_ctx->stream->signal ==
4076                                 SIGNAL_TYPE_DISPLAY_PORT_MST);
4077                 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
4078         }
4079 }
4080 #endif
4081
4082 #if defined(CONFIG_DRM_AMD_DC_DCN)
4083 static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx)
4084 {
4085         struct dc *dc = pipe_ctx->stream->ctx->dc;
4086         struct dc_stream_state *stream = pipe_ctx->stream;
4087         struct link_mst_stream_allocation_table proposed_table = {0};
4088         struct fixed31_32 avg_time_slots_per_mtp;
4089         uint8_t req_slot_count = 0;
4090         uint8_t vc_id = 1; /// VC ID always 1 for SST
4091
4092         struct dc_link_settings link_settings = {0};
4093         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4094
4095         decide_link_settings(stream, &link_settings);
4096         stream->link->cur_link_settings = link_settings;
4097
4098         /*  Enable clock, Configure lane count, and Enable Link Encoder*/
4099         enable_dp_hpo_output(stream->link, &stream->link->cur_link_settings);
4100
4101 #ifdef DIAGS_BUILD
4102         /* Workaround for FPGA HPO capture DP link data:
4103          * HPO capture will set link to active mode
4104          * This workaround is required to get a capture from start of frame
4105          */
4106         if (!dc->debug.fpga_hpo_capture_en) {
4107                 struct encoder_set_dp_phy_pattern_param params = {0};
4108                 params.dp_phy_pattern = DP_TEST_PATTERN_VIDEO_MODE;
4109
4110                 /* Set link active */
4111                 stream->link->hpo_dp_link_enc->funcs->set_link_test_pattern(
4112                                 stream->link->hpo_dp_link_enc,
4113                                 &params);
4114         }
4115 #endif
4116
4117         /* Enable DP_STREAM_ENC */
4118         dc->hwss.enable_stream(pipe_ctx);
4119
4120         /* Set DPS PPS SDP (AKA "info frames") */
4121         if (pipe_ctx->stream->timing.flags.DSC) {
4122                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4123         }
4124
4125         /* Allocate Payload */
4126         if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) {
4127                 // MST case
4128                 uint8_t i;
4129
4130                 proposed_table.stream_count = state->stream_count;
4131                 for (i = 0; i < state->stream_count; i++) {
4132                         avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link);
4133                         req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4134                         proposed_table.stream_allocations[i].slot_count = req_slot_count;
4135                         proposed_table.stream_allocations[i].vcp_id = i+1;
4136                         /* NOTE: This makes assumption that pipe_ctx index is same as stream index */
4137                         proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc;
4138                 }
4139         } else {
4140                 // SST case
4141                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, stream->link);
4142                 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4143                 proposed_table.stream_count = 1; /// Always 1 stream for SST
4144                 proposed_table.stream_allocations[0].slot_count = req_slot_count;
4145                 proposed_table.stream_allocations[0].vcp_id = vc_id;
4146                 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
4147         }
4148
4149         stream->link->hpo_dp_link_enc->funcs->update_stream_allocation_table(
4150                         stream->link->hpo_dp_link_enc,
4151                         &proposed_table);
4152
4153         stream->link->hpo_dp_link_enc->funcs->set_throttled_vcp_size(
4154                         stream->link->hpo_dp_link_enc,
4155                         pipe_ctx->stream_res.hpo_dp_stream_enc->inst,
4156                         avg_time_slots_per_mtp);
4157
4158
4159
4160         dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings);
4161 }
4162 #endif
4163
4164 void core_link_enable_stream(
4165                 struct dc_state *state,
4166                 struct pipe_ctx *pipe_ctx)
4167 {
4168         struct dc *dc = pipe_ctx->stream->ctx->dc;
4169         struct dc_stream_state *stream = pipe_ctx->stream;
4170         struct dc_link *link = stream->sink->link;
4171         enum dc_status status;
4172         struct link_encoder *link_enc;
4173 #if defined(CONFIG_DRM_AMD_DC_DCN)
4174         enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
4175         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4176
4177         if (is_dp_128b_132b_signal(pipe_ctx))
4178                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4179 #endif
4180         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4181
4182         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4183                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4184                 return;
4185
4186         if (dc->res_pool->funcs->link_encs_assign && stream->link->ep_type != DISPLAY_ENDPOINT_PHY)
4187                 link_enc = link_enc_cfg_get_link_enc_used_by_stream(dc, stream);
4188         else
4189                 link_enc = stream->link->link_enc;
4190         ASSERT(link_enc);
4191
4192 #if defined(CONFIG_DRM_AMD_DC_DCN)
4193         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)
4194                         && !is_dp_128b_132b_signal(pipe_ctx)) {
4195 #else
4196         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
4197 #endif
4198                 if (link_enc)
4199                         link_enc->funcs->setup(
4200                                 link_enc,
4201                                 pipe_ctx->stream->signal);
4202                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
4203                         pipe_ctx->stream_res.stream_enc,
4204                         pipe_ctx->stream_res.tg->inst,
4205                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
4206         }
4207
4208 #if defined(CONFIG_DRM_AMD_DC_DCN)
4209         if (is_dp_128b_132b_signal(pipe_ctx)) {
4210                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->set_stream_attribute(
4211                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
4212                                 &stream->timing,
4213                                 stream->output_color_space,
4214                                 stream->use_vsc_sdp_for_colorimetry,
4215                                 stream->timing.flags.DSC,
4216                                 false);
4217                 otg_out_dest = OUT_MUX_HPO_DP;
4218         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
4219                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
4220                                 pipe_ctx->stream_res.stream_enc,
4221                                 &stream->timing,
4222                                 stream->output_color_space,
4223                                 stream->use_vsc_sdp_for_colorimetry,
4224                                 stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4225         }
4226 #else
4227         pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
4228                         pipe_ctx->stream_res.stream_enc,
4229                         &stream->timing,
4230                         stream->output_color_space,
4231                         stream->use_vsc_sdp_for_colorimetry,
4232                         stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4233 #endif
4234
4235         if (dc_is_dp_signal(pipe_ctx->stream->signal))
4236                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR);
4237
4238         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
4239                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
4240                         pipe_ctx->stream_res.stream_enc,
4241                         &stream->timing,
4242                         stream->phy_pix_clk,
4243                         pipe_ctx->stream_res.audio != NULL);
4244
4245         pipe_ctx->stream->link->link_state_valid = true;
4246
4247 #if defined(CONFIG_DRM_AMD_DC_DCN)
4248         if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4249                 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
4250 #endif
4251
4252         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
4253                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
4254                         pipe_ctx->stream_res.stream_enc,
4255                         &stream->timing,
4256                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
4257                         true : false);
4258
4259         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
4260                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
4261                         pipe_ctx->stream_res.stream_enc,
4262                         &stream->timing);
4263
4264         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
4265                 bool apply_edp_fast_boot_optimization =
4266                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
4267
4268                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
4269
4270 #if defined(CONFIG_DRM_AMD_DC_DCN)
4271                 // Enable VPG before building infoframe
4272                 if (vpg && vpg->funcs->vpg_poweron)
4273                         vpg->funcs->vpg_poweron(vpg);
4274 #endif
4275
4276                 resource_build_info_frame(pipe_ctx);
4277                 dc->hwss.update_info_frame(pipe_ctx);
4278
4279                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4280                         dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
4281
4282                 /* Do not touch link on seamless boot optimization. */
4283                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
4284                         pipe_ctx->stream->dpms_off = false;
4285
4286                         /* Still enable stream features & audio on seamless boot for DP external displays */
4287                         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
4288                                 enable_stream_features(pipe_ctx);
4289                                 if (pipe_ctx->stream_res.audio != NULL) {
4290                                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
4291                                         dc->hwss.enable_audio_stream(pipe_ctx);
4292                                 }
4293                         }
4294
4295 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4296                         update_psp_stream_config(pipe_ctx, false);
4297 #endif
4298                         return;
4299                 }
4300
4301                 /* eDP lit up by bios already, no need to enable again. */
4302                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
4303                                         apply_edp_fast_boot_optimization &&
4304                                         !pipe_ctx->stream->timing.flags.DSC &&
4305                                         !pipe_ctx->next_odm_pipe) {
4306                         pipe_ctx->stream->dpms_off = false;
4307 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4308                         update_psp_stream_config(pipe_ctx, false);
4309 #endif
4310                         return;
4311                 }
4312
4313                 if (pipe_ctx->stream->dpms_off)
4314                         return;
4315
4316                 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
4317                  * link training). This is to make sure the bandwidth sent to DIG BE won't be
4318                  * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
4319                  * will be automatically set at a later time when the video is enabled
4320                  * (DP_VID_STREAM_EN = 1).
4321                  */
4322                 if (pipe_ctx->stream->timing.flags.DSC) {
4323                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4324                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4325                                 dp_set_dsc_enable(pipe_ctx, true);
4326                 }
4327
4328                 status = enable_link(state, pipe_ctx);
4329
4330                 if (status != DC_OK) {
4331                         DC_LOG_WARNING("enabling link %u failed: %d\n",
4332                         pipe_ctx->stream->link->link_index,
4333                         status);
4334
4335                         /* Abort stream enable *unless* the failure was due to
4336                          * DP link training - some DP monitors will recover and
4337                          * show the stream anyway. But MST displays can't proceed
4338                          * without link training.
4339                          */
4340                         if (status != DC_FAIL_DP_LINK_TRAINING ||
4341                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
4342                                 if (false == stream->link->link_status.link_active)
4343                                         disable_link(stream->link, pipe_ctx->stream->signal);
4344                                 BREAK_TO_DEBUGGER();
4345                                 return;
4346                         }
4347                 }
4348
4349                 /* turn off otg test pattern if enable */
4350                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4351                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4352                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4353                                         COLOR_DEPTH_UNDEFINED);
4354
4355                 /* This second call is needed to reconfigure the DIG
4356                  * as a workaround for the incorrect value being applied
4357                  * from transmitter control.
4358                  */
4359 #if defined(CONFIG_DRM_AMD_DC_DCN)
4360                 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
4361                                 is_dp_128b_132b_signal(pipe_ctx)))
4362 #else
4363                 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
4364 #endif
4365                         if (link_enc)
4366                                 link_enc->funcs->setup(
4367                                         link_enc,
4368                                         pipe_ctx->stream->signal);
4369
4370                 dc->hwss.enable_stream(pipe_ctx);
4371
4372                 /* Set DPS PPS SDP (AKA "info frames") */
4373                 if (pipe_ctx->stream->timing.flags.DSC) {
4374                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4375                                         dc_is_virtual_signal(pipe_ctx->stream->signal)) {
4376                                 dp_set_dsc_on_rx(pipe_ctx, true);
4377                                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4378                         }
4379                 }
4380
4381                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4382                         dc_link_allocate_mst_payload(pipe_ctx);
4383 #if defined(CONFIG_DRM_AMD_DC_DCN)
4384                 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4385                                 is_dp_128b_132b_signal(pipe_ctx))
4386                         dc_link_update_sst_payload(pipe_ctx, true);
4387 #endif
4388
4389                 dc->hwss.unblank_stream(pipe_ctx,
4390                         &pipe_ctx->stream->link->cur_link_settings);
4391
4392                 if (stream->sink_patches.delay_ignore_msa > 0)
4393                         msleep(stream->sink_patches.delay_ignore_msa);
4394
4395                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4396                         enable_stream_features(pipe_ctx);
4397 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4398                 update_psp_stream_config(pipe_ctx, false);
4399 #endif
4400
4401                 dc->hwss.enable_audio_stream(pipe_ctx);
4402
4403         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
4404 #if defined(CONFIG_DRM_AMD_DC_DCN)
4405                 if (is_dp_128b_132b_signal(pipe_ctx)) {
4406                         fpga_dp_hpo_enable_link_and_stream(state, pipe_ctx);
4407                 }
4408 #endif
4409                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4410                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
4411                         dp_set_dsc_enable(pipe_ctx, true);
4412
4413         }
4414
4415         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
4416                 core_link_set_avmute(pipe_ctx, false);
4417         }
4418 }
4419
4420 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
4421 {
4422         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4423         struct dc_stream_state *stream = pipe_ctx->stream;
4424         struct dc_link *link = stream->sink->link;
4425 #if defined(CONFIG_DRM_AMD_DC_DCN)
4426         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4427
4428         if (is_dp_128b_132b_signal(pipe_ctx))
4429                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4430 #endif
4431
4432         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4433                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4434                 return;
4435
4436         if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
4437                 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
4438                         core_link_set_avmute(pipe_ctx, true);
4439         }
4440
4441         dc->hwss.disable_audio_stream(pipe_ctx);
4442
4443 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4444         update_psp_stream_config(pipe_ctx, true);
4445 #endif
4446         dc->hwss.blank_stream(pipe_ctx);
4447
4448         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4449                 deallocate_mst_payload(pipe_ctx);
4450 #if defined(CONFIG_DRM_AMD_DC_DCN)
4451         else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4452                         is_dp_128b_132b_signal(pipe_ctx))
4453                 dc_link_update_sst_payload(pipe_ctx, false);
4454 #endif
4455
4456         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4457                 struct ext_hdmi_settings settings = {0};
4458                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
4459
4460                 unsigned short masked_chip_caps = link->chip_caps &
4461                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
4462                 //Need to inform that sink is going to use legacy HDMI mode.
4463                 dal_ddc_service_write_scdc_data(
4464                         link->ddc,
4465                         165000,//vbios only handles 165Mhz.
4466                         false);
4467                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
4468                         /* DP159, Retimer settings */
4469                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
4470                                 write_i2c_retimer_setting(pipe_ctx,
4471                                                 false, false, &settings);
4472                         else
4473                                 write_i2c_default_retimer_setting(pipe_ctx,
4474                                                 false, false);
4475                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
4476                         /* PI3EQX1204, Redriver settings */
4477                         write_i2c_redriver_setting(pipe_ctx, false);
4478                 }
4479         }
4480
4481 #if defined(CONFIG_DRM_AMD_DC_DCN)
4482         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4483                         !is_dp_128b_132b_signal(pipe_ctx)) {
4484
4485                 /* In DP1.x SST mode, our encoder will go to TPS1
4486                  * when link is on but stream is off.
4487                  * Disabling link before stream will avoid exposing TPS1 pattern
4488                  * during the disable sequence as it will confuse some receivers
4489                  * state machine.
4490                  * In DP2 or MST mode, our encoder will stay video active
4491                  */
4492                 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4493                 dc->hwss.disable_stream(pipe_ctx);
4494         } else {
4495                 dc->hwss.disable_stream(pipe_ctx);
4496                 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4497         }
4498 #else
4499         disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4500
4501         dc->hwss.disable_stream(pipe_ctx);
4502 #endif
4503
4504         if (pipe_ctx->stream->timing.flags.DSC) {
4505                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4506                         dp_set_dsc_enable(pipe_ctx, false);
4507         }
4508 #if defined(CONFIG_DRM_AMD_DC_DCN)
4509         if (is_dp_128b_132b_signal(pipe_ctx)) {
4510                 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4511                         pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
4512         }
4513 #endif
4514
4515 #if defined(CONFIG_DRM_AMD_DC_DCN)
4516         if (vpg && vpg->funcs->vpg_powerdown)
4517                 vpg->funcs->vpg_powerdown(vpg);
4518 #endif
4519 }
4520
4521 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
4522 {
4523         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4524
4525         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
4526                 return;
4527
4528         dc->hwss.set_avmute(pipe_ctx, enable);
4529 }
4530
4531 /**
4532  *  dc_link_enable_hpd_filter:
4533  *     If enable is true, programs HPD filter on associated HPD line using
4534  *     delay_on_disconnect/delay_on_connect values dependent on
4535  *     link->connector_signal
4536  *
4537  *     If enable is false, programs HPD filter on associated HPD line with no
4538  *     delays on connect or disconnect
4539  *
4540  *  @link:   pointer to the dc link
4541  *  @enable: boolean specifying whether to enable hbd
4542  */
4543 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
4544 {
4545         struct gpio *hpd;
4546
4547         if (enable) {
4548                 link->is_hpd_filter_disabled = false;
4549                 program_hpd_filter(link);
4550         } else {
4551                 link->is_hpd_filter_disabled = true;
4552                 /* Obtain HPD handle */
4553                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4554
4555                 if (!hpd)
4556                         return;
4557
4558                 /* Setup HPD filtering */
4559                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
4560                         struct gpio_hpd_config config;
4561
4562                         config.delay_on_connect = 0;
4563                         config.delay_on_disconnect = 0;
4564
4565                         dal_irq_setup_hpd_filter(hpd, &config);
4566
4567                         dal_gpio_close(hpd);
4568                 } else {
4569                         ASSERT_CRITICAL(false);
4570                 }
4571                 /* Release HPD handle */
4572                 dal_gpio_destroy_irq(&hpd);
4573         }
4574 }
4575
4576 void dc_link_set_drive_settings(struct dc *dc,
4577                                 struct link_training_settings *lt_settings,
4578                                 const struct dc_link *link)
4579 {
4580
4581         int i;
4582
4583         for (i = 0; i < dc->link_count; i++) {
4584                 if (dc->links[i] == link)
4585                         break;
4586         }
4587
4588         if (i >= dc->link_count)
4589                 ASSERT_CRITICAL(false);
4590
4591         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
4592 }
4593
4594 void dc_link_set_preferred_link_settings(struct dc *dc,
4595                                          struct dc_link_settings *link_setting,
4596                                          struct dc_link *link)
4597 {
4598         int i;
4599         struct pipe_ctx *pipe;
4600         struct dc_stream_state *link_stream;
4601         struct dc_link_settings store_settings = *link_setting;
4602
4603         link->preferred_link_setting = store_settings;
4604
4605         /* Retrain with preferred link settings only relevant for
4606          * DP signal type
4607          * Check for non-DP signal or if passive dongle present
4608          */
4609         if (!dc_is_dp_signal(link->connector_signal) ||
4610                 link->dongle_max_pix_clk > 0)
4611                 return;
4612
4613         for (i = 0; i < MAX_PIPES; i++) {
4614                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4615                 if (pipe->stream && pipe->stream->link) {
4616                         if (pipe->stream->link == link) {
4617                                 link_stream = pipe->stream;
4618                                 break;
4619                         }
4620                 }
4621         }
4622
4623         /* Stream not found */
4624         if (i == MAX_PIPES)
4625                 return;
4626
4627         /* Cannot retrain link if backend is off */
4628         if (link_stream->dpms_off)
4629                 return;
4630
4631         decide_link_settings(link_stream, &store_settings);
4632
4633         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
4634                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
4635                 dp_retrain_link_dp_test(link, &store_settings, false);
4636 }
4637
4638 void dc_link_set_preferred_training_settings(struct dc *dc,
4639                                                  struct dc_link_settings *link_setting,
4640                                                  struct dc_link_training_overrides *lt_overrides,
4641                                                  struct dc_link *link,
4642                                                  bool skip_immediate_retrain)
4643 {
4644         if (lt_overrides != NULL)
4645                 link->preferred_training_settings = *lt_overrides;
4646         else
4647                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
4648
4649         if (link_setting != NULL) {
4650                 link->preferred_link_setting = *link_setting;
4651 #if defined(CONFIG_DRM_AMD_DC_DCN)
4652                 if (dp_get_link_encoding_format(link_setting) ==
4653                                 DP_128b_132b_ENCODING && !link->hpo_dp_link_enc) {
4654                         if (!add_dp_hpo_link_encoder_to_link(link))
4655                                 memset(&link->preferred_link_setting, 0, sizeof(link->preferred_link_setting));
4656                 }
4657 #endif
4658         } else {
4659                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
4660                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
4661         }
4662
4663         /* Retrain now, or wait until next stream update to apply */
4664         if (skip_immediate_retrain == false)
4665                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
4666 }
4667
4668 void dc_link_enable_hpd(const struct dc_link *link)
4669 {
4670         dc_link_dp_enable_hpd(link);
4671 }
4672
4673 void dc_link_disable_hpd(const struct dc_link *link)
4674 {
4675         dc_link_dp_disable_hpd(link);
4676 }
4677
4678 void dc_link_set_test_pattern(struct dc_link *link,
4679                               enum dp_test_pattern test_pattern,
4680                               enum dp_test_pattern_color_space test_pattern_color_space,
4681                               const struct link_training_settings *p_link_settings,
4682                               const unsigned char *p_custom_pattern,
4683                               unsigned int cust_pattern_size)
4684 {
4685         if (link != NULL)
4686                 dc_link_dp_set_test_pattern(
4687                         link,
4688                         test_pattern,
4689                         test_pattern_color_space,
4690                         p_link_settings,
4691                         p_custom_pattern,
4692                         cust_pattern_size);
4693 }
4694
4695 uint32_t dc_link_bandwidth_kbps(
4696         const struct dc_link *link,
4697         const struct dc_link_settings *link_setting)
4698 {
4699 #if defined(CONFIG_DRM_AMD_DC_DCN)
4700         uint32_t total_data_bw_efficiency_x10000 = 0;
4701         uint32_t link_rate_per_lane_kbps = 0;
4702
4703         switch (dp_get_link_encoding_format(link_setting)) {
4704         case DP_8b_10b_ENCODING:
4705                 /* For 8b/10b encoding:
4706                  * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
4707                  * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
4708                  */
4709                 link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
4710                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
4711                 if (dc_link_should_enable_fec(link)) {
4712                         total_data_bw_efficiency_x10000 /= 100;
4713                         total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
4714                 }
4715                 break;
4716         case DP_128b_132b_ENCODING:
4717                 /* For 128b/132b encoding:
4718                  * link rate is defined in the unit of 10mbps per lane.
4719                  * total data bandwidth efficiency is always 96.71%.
4720                  */
4721                 link_rate_per_lane_kbps = link_setting->link_rate * 10000;
4722                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
4723                 break;
4724         default:
4725                 break;
4726         }
4727
4728         /* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
4729         return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
4730 #else
4731         uint32_t link_bw_kbps =
4732                 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
4733
4734         link_bw_kbps *= 8;   /* 8 bits per byte*/
4735         link_bw_kbps *= link_setting->lane_count;
4736
4737         if (dc_link_should_enable_fec(link)) {
4738                 /* Account for FEC overhead.
4739                  * We have to do it based on caps,
4740                  * and not based on FEC being set ready,
4741                  * because FEC is set ready too late in
4742                  * the process to correctly be picked up
4743                  * by mode enumeration.
4744                  *
4745                  * There's enough zeros at the end of 'kbps'
4746                  * that make the below operation 100% precise
4747                  * for our purposes.
4748                  * 'long long' makes it work even for HDMI 2.1
4749                  * max bandwidth (and much, much bigger bandwidths
4750                  * than that, actually).
4751                  *
4752                  * NOTE: Reducing link BW by 3% may not be precise
4753                  * because it may be a stream BT that increases by 3%, and so
4754                  * 1/1.03 = 0.970873 factor should have been used instead,
4755                  * but the difference is minimal and is in a safe direction,
4756                  * which all works well around potential ambiguity of DP 1.4a spec.
4757                  */
4758                 long long fec_link_bw_kbps = link_bw_kbps * 970LL;
4759                 link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL));
4760         }
4761         return link_bw_kbps;
4762
4763 #endif
4764 }
4765
4766 const struct dc_link_settings *dc_link_get_link_cap(
4767                 const struct dc_link *link)
4768 {
4769         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
4770                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
4771                 return &link->preferred_link_setting;
4772         return &link->verified_link_cap;
4773 }
4774
4775 void dc_link_overwrite_extended_receiver_cap(
4776                 struct dc_link *link)
4777 {
4778         dp_overwrite_extended_receiver_cap(link);
4779 }
4780
4781 bool dc_link_is_fec_supported(const struct dc_link *link)
4782 {
4783         struct link_encoder *link_enc = NULL;
4784
4785         /* Links supporting dynamically assigned link encoder will be assigned next
4786          * available encoder if one not already assigned.
4787          */
4788         if (link->is_dig_mapping_flexible &&
4789                         link->dc->res_pool->funcs->link_encs_assign) {
4790                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
4791                 if (link_enc == NULL)
4792                         link_enc = link_enc_cfg_get_next_avail_link_enc(link->ctx->dc);
4793         } else
4794                 link_enc = link->link_enc;
4795         ASSERT(link_enc);
4796
4797         return (dc_is_dp_signal(link->connector_signal) && link_enc &&
4798                         link_enc->features.fec_supported &&
4799                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
4800                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
4801 }
4802
4803 bool dc_link_should_enable_fec(const struct dc_link *link)
4804 {
4805         bool is_fec_disable = false;
4806         bool ret = false;
4807
4808         if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
4809                         link->local_sink &&
4810                         link->local_sink->edid_caps.panel_patch.disable_fec) ||
4811                         (link->connector_signal == SIGNAL_TYPE_EDP
4812                                 // enable FEC for EDP if DSC is supported
4813                                 && link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT == false
4814                                 ))
4815                 is_fec_disable = true;
4816
4817         if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
4818                 ret = true;
4819
4820         return ret;
4821 }
4822
4823 uint32_t dc_bandwidth_in_kbps_from_timing(
4824                 const struct dc_crtc_timing *timing)
4825 {
4826         uint32_t bits_per_channel = 0;
4827         uint32_t kbps;
4828
4829 #if defined(CONFIG_DRM_AMD_DC_DCN)
4830         if (timing->flags.DSC)
4831                 return dc_dsc_stream_bandwidth_in_kbps(timing,
4832                                 timing->dsc_cfg.bits_per_pixel,
4833                                 timing->dsc_cfg.num_slices_h,
4834                                 timing->dsc_cfg.is_dp);
4835 #endif /* CONFIG_DRM_AMD_DC_DCN */
4836
4837         switch (timing->display_color_depth) {
4838         case COLOR_DEPTH_666:
4839                 bits_per_channel = 6;
4840                 break;
4841         case COLOR_DEPTH_888:
4842                 bits_per_channel = 8;
4843                 break;
4844         case COLOR_DEPTH_101010:
4845                 bits_per_channel = 10;
4846                 break;
4847         case COLOR_DEPTH_121212:
4848                 bits_per_channel = 12;
4849                 break;
4850         case COLOR_DEPTH_141414:
4851                 bits_per_channel = 14;
4852                 break;
4853         case COLOR_DEPTH_161616:
4854                 bits_per_channel = 16;
4855                 break;
4856         default:
4857                 ASSERT(bits_per_channel != 0);
4858                 bits_per_channel = 8;
4859                 break;
4860         }
4861
4862         kbps = timing->pix_clk_100hz / 10;
4863         kbps *= bits_per_channel;
4864
4865         if (timing->flags.Y_ONLY != 1) {
4866                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
4867                 kbps *= 3;
4868                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
4869                         kbps /= 2;
4870                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
4871                         kbps = kbps * 2 / 3;
4872         }
4873
4874         return kbps;
4875
4876 }