drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atomfirmware.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48 #include "dce/dmub_psr.h"
  49 #include "dmub/dmub_srv.h"
  50 #include "inc/hw/panel_cntl.h"
  51
  52 #define DC_LOGGER_INIT(logger)
  53
  54 #define LINK_INFO(...) \
  55         DC_LOG_HW_HOTPLUG(  \
  56                 __VA_ARGS__)
  57
  58 #define RETIMER_REDRIVER_INFO(...) \
  59         DC_LOG_RETIMER_REDRIVER(  \
  60                 __VA_ARGS__)
  61 /*******************************************************************************
  62  * Private structures
  63  ******************************************************************************/
  64
  65 enum {
  66         PEAK_FACTOR_X1000 = 1006,
  67         /*
  68          * Some receivers fail to train on first try and are good
  69          * on subsequent tries. 2 retries should be plenty. If we
  70          * don't have a successful training then we don't expect to
  71          * ever get one.
  72          */
  73         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  74 };
  75
  76 /*******************************************************************************
  77  * Private functions
  78  ******************************************************************************/
  79 static void dc_link_destruct(struct dc_link *link)
  80 {
  81         int i;
  82
  83         if (link->hpd_gpio) {
  84                 dal_gpio_destroy_irq(&link->hpd_gpio);
  85                 link->hpd_gpio = NULL;
  86         }
  87
  88         if (link->ddc)
  89                 dal_ddc_service_destroy(&link->ddc);
  90
  91         if (link->panel_cntl)
  92                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
  93
  94         if (link->link_enc) {
  95                 /* Update link encoder tracking variables. These are used for the dynamic
  96                  * assignment of link encoders to streams.
  97                  */
  98                 link->dc->res_pool->link_encoders[link->link_enc->preferred_engine] = NULL;
  99                 link->dc->res_pool->dig_link_enc_count--;
 100                 link->link_enc->funcs->destroy(&link->link_enc);
 101         }
 102
 103         if (link->local_sink)
 104                 dc_sink_release(link->local_sink);
 105
 106         for (i = 0; i < link->sink_count; ++i)
 107                 dc_sink_release(link->remote_sinks[i]);
 108 }
 109
 110 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 111                           struct graphics_object_id link_id,
 112                           struct gpio_service *gpio_service)
 113 {
 114         enum bp_result bp_result;
 115         struct graphics_object_hpd_info hpd_info;
 116         struct gpio_pin_info pin_info;
 117
 118         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 119                 return NULL;
 120
 121         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 122                 hpd_info.hpd_int_gpio_uid, &pin_info);
 123
 124         if (bp_result != BP_RESULT_OK) {
 125                 ASSERT(bp_result == BP_RESULT_NORECORD);
 126                 return NULL;
 127         }
 128
 129         return dal_gpio_service_create_irq(gpio_service,
 130                                            pin_info.offset,
 131                                            pin_info.mask);
 132 }
 133
 134 /*
 135  *  Function: program_hpd_filter
 136  *
 137  *  @brief
 138  *     Programs HPD filter on associated HPD line
 139  *
 140  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 141  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 142  *
 143  *  @return
 144  *     true on success, false otherwise
 145  */
 146 static bool program_hpd_filter(const struct dc_link *link)
 147 {
 148         bool result = false;
 149         struct gpio *hpd;
 150         int delay_on_connect_in_ms = 0;
 151         int delay_on_disconnect_in_ms = 0;
 152
 153         if (link->is_hpd_filter_disabled)
 154                 return false;
 155         /* Verify feature is supported */
 156         switch (link->connector_signal) {
 157         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 158         case SIGNAL_TYPE_DVI_DUAL_LINK:
 159         case SIGNAL_TYPE_HDMI_TYPE_A:
 160                 /* Program hpd filter */
 161                 delay_on_connect_in_ms = 500;
 162                 delay_on_disconnect_in_ms = 100;
 163                 break;
 164         case SIGNAL_TYPE_DISPLAY_PORT:
 165         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 166                 /* Program hpd filter to allow DP signal to settle */
 167                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 168                  * only 100ms on DELL U2413
 169                  * 0: some passive dongle still show aux mode instead of i2c
 170                  * 20-50: not enough to hide bouncing HPD with passive dongle.
 171                  * also see intermittent i2c read issues.
 172                  */
 173                 delay_on_connect_in_ms = 80;
 174                 delay_on_disconnect_in_ms = 0;
 175                 break;
 176         case SIGNAL_TYPE_LVDS:
 177         case SIGNAL_TYPE_EDP:
 178         default:
 179                 /* Don't program hpd filter */
 180                 return false;
 181         }
 182
 183         /* Obtain HPD handle */
 184         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 185                            link->ctx->gpio_service);
 186
 187         if (!hpd)
 188                 return result;
 189
 190         /* Setup HPD filtering */
 191         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 192                 struct gpio_hpd_config config;
 193
 194                 config.delay_on_connect = delay_on_connect_in_ms;
 195                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 196
 197                 dal_irq_setup_hpd_filter(hpd, &config);
 198
 199                 dal_gpio_close(hpd);
 200
 201                 result = true;
 202         } else {
 203                 ASSERT_CRITICAL(false);
 204         }
 205
 206         /* Release HPD handle */
 207         dal_gpio_destroy_irq(&hpd);
 208
 209         return result;
 210 }
 211
 212 bool dc_link_wait_for_t12(struct dc_link *link)
 213 {
 214         if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 215                 link->dc->hwss.edp_wait_for_T12(link);
 216
 217                 return true;
 218         }
 219
 220         return false;
 221 }
 222
 223 /**
 224  * dc_link_detect_sink() - Determine if there is a sink connected
 225  *
 226  * @link: pointer to the dc link
 227  * @type: Returned connection type
 228  * Does not detect downstream devices, such as MST sinks
 229  * or display connected through active dongles
 230  */
 231 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 232 {
 233         uint32_t is_hpd_high = 0;
 234         struct gpio *hpd_pin;
 235
 236         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 237                 *type = dc_connection_single;
 238                 return true;
 239         }
 240
 241         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 242                 /*in case it is not on*/
 243                 link->dc->hwss.edp_power_control(link, true);
 244                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 245         }
 246
 247         /* todo: may need to lock gpio access */
 248         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 249                                link->ctx->gpio_service);
 250         if (!hpd_pin)
 251                 goto hpd_gpio_failure;
 252
 253         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 254         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 255         dal_gpio_close(hpd_pin);
 256         dal_gpio_destroy_irq(&hpd_pin);
 257
 258         if (is_hpd_high) {
 259                 *type = dc_connection_single;
 260                 /* TODO: need to do the actual detection */
 261         } else {
 262                 *type = dc_connection_none;
 263         }
 264
 265         return true;
 266
 267 hpd_gpio_failure:
 268         return false;
 269 }
 270
 271 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 272 {
 273         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 274
 275         switch (sink_signal) {
 276         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 277         case SIGNAL_TYPE_DVI_DUAL_LINK:
 278         case SIGNAL_TYPE_HDMI_TYPE_A:
 279         case SIGNAL_TYPE_LVDS:
 280         case SIGNAL_TYPE_RGB:
 281                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 282                 break;
 283
 284         case SIGNAL_TYPE_DISPLAY_PORT:
 285         case SIGNAL_TYPE_EDP:
 286                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 287                 break;
 288
 289         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 290                 /* MST does not use I2COverAux, but there is the
 291                  * SPECIAL use case for "immediate dwnstrm device
 292                  * access" (EPR#370830).
 293                  */
 294                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 295                 break;
 296
 297         default:
 298                 break;
 299         }
 300
 301         return transaction_type;
 302 }
 303
 304 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 305                                               struct graphics_object_id downstream)
 306 {
 307         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 308                 switch (downstream.id) {
 309                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 310                         switch (encoder.id) {
 311                         case ENCODER_ID_INTERNAL_DAC1:
 312                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 313                         case ENCODER_ID_INTERNAL_DAC2:
 314                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 315                                 return SIGNAL_TYPE_RGB;
 316                         default:
 317                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 318                         }
 319                 break;
 320                 case CONNECTOR_ID_DUAL_LINK_DVII:
 321                 {
 322                         switch (encoder.id) {
 323                         case ENCODER_ID_INTERNAL_DAC1:
 324                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 325                         case ENCODER_ID_INTERNAL_DAC2:
 326                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 327                                 return SIGNAL_TYPE_RGB;
 328                         default:
 329                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 330                         }
 331                 }
 332                 break;
 333                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 334                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 335                 case CONNECTOR_ID_DUAL_LINK_DVID:
 336                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 337                 case CONNECTOR_ID_VGA:
 338                         return SIGNAL_TYPE_RGB;
 339                 case CONNECTOR_ID_HDMI_TYPE_A:
 340                         return SIGNAL_TYPE_HDMI_TYPE_A;
 341                 case CONNECTOR_ID_LVDS:
 342                         return SIGNAL_TYPE_LVDS;
 343                 case CONNECTOR_ID_DISPLAY_PORT:
 344                         return SIGNAL_TYPE_DISPLAY_PORT;
 345                 case CONNECTOR_ID_EDP:
 346                         return SIGNAL_TYPE_EDP;
 347                 default:
 348                         return SIGNAL_TYPE_NONE;
 349                 }
 350         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 351                 switch (downstream.id) {
 352                 case ENCODER_ID_EXTERNAL_NUTMEG:
 353                 case ENCODER_ID_EXTERNAL_TRAVIS:
 354                         return SIGNAL_TYPE_DISPLAY_PORT;
 355                 default:
 356                         return SIGNAL_TYPE_NONE;
 357                 }
 358         }
 359
 360         return SIGNAL_TYPE_NONE;
 361 }
 362
 363 /*
 364  * dc_link_is_dp_sink_present() - Check if there is a native DP
 365  * or passive DP-HDMI dongle connected
 366  */
 367 bool dc_link_is_dp_sink_present(struct dc_link *link)
 368 {
 369         enum gpio_result gpio_result;
 370         uint32_t clock_pin = 0;
 371         uint8_t retry = 0;
 372         struct ddc *ddc;
 373
 374         enum connector_id connector_id =
 375                 dal_graphics_object_id_get_connector_id(link->link_id);
 376
 377         bool present =
 378                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 379                 (connector_id == CONNECTOR_ID_EDP));
 380
 381         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 382
 383         if (!ddc) {
 384                 BREAK_TO_DEBUGGER();
 385                 return present;
 386         }
 387
 388         /* Open GPIO and set it to I2C mode */
 389         /* Note: this GpioMode_Input will be converted
 390          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 391          * which indicates we need additional delay
 392          */
 393
 394         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 395                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 396                 dal_ddc_close(ddc);
 397
 398                 return present;
 399         }
 400
 401         /*
 402          * Read GPIO: DP sink is present if both clock and data pins are zero
 403          *
 404          * [W/A] plug-unplug DP cable, sometimes customer board has
 405          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 406          * then monitor can't br light up. Add retry 3 times
 407          * But in real passive dongle, it need additional 3ms to detect
 408          */
 409         do {
 410                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 411                 ASSERT(gpio_result == GPIO_RESULT_OK);
 412                 if (clock_pin)
 413                         udelay(1000);
 414                 else
 415                         break;
 416         } while (retry++ < 3);
 417
 418         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 419
 420         dal_ddc_close(ddc);
 421
 422         return present;
 423 }
 424
 425 /*
 426  * @brief
 427  * Detect output sink type
 428  */
 429 static enum signal_type link_detect_sink(struct dc_link *link,
 430                                          enum dc_detect_reason reason)
 431 {
 432         enum signal_type result = get_basic_signal_type(link->link_enc->id,
 433                                                         link->link_id);
 434
 435         /* Internal digital encoder will detect only dongles
 436          * that require digital signal
 437          */
 438
 439         /* Detection mechanism is different
 440          * for different native connectors.
 441          * LVDS connector supports only LVDS signal;
 442          * PCIE is a bus slot, the actual connector needs to be detected first;
 443          * eDP connector supports only eDP signal;
 444          * HDMI should check straps for audio
 445          */
 446
 447         /* PCIE detects the actual connector on add-on board */
 448         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 449                 /* ZAZTODO implement PCIE add-on card detection */
 450         }
 451
 452         switch (link->link_id.id) {
 453         case CONNECTOR_ID_HDMI_TYPE_A: {
 454                 /* check audio support:
 455                  * if native HDMI is not supported, switch to DVI
 456                  */
 457                 struct audio_support *aud_support =
 458                                         &link->dc->res_pool->audio_support;
 459
 460                 if (!aud_support->hdmi_audio_native)
 461                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 462                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 463         }
 464         break;
 465         case CONNECTOR_ID_DISPLAY_PORT: {
 466                 /* DP HPD short pulse. Passive DP dongle will not
 467                  * have short pulse
 468                  */
 469                 if (reason != DETECT_REASON_HPDRX) {
 470                         /* Check whether DP signal detected: if not -
 471                          * we assume signal is DVI; it could be corrected
 472                          * to HDMI after dongle detection
 473                          */
 474                         if (!dm_helpers_is_dp_sink_present(link))
 475                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 476                 }
 477         }
 478         break;
 479         default:
 480         break;
 481         }
 482
 483         return result;
 484 }
 485
 486 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 487                                                                  struct audio_support *audio_support)
 488 {
 489         enum signal_type signal = SIGNAL_TYPE_NONE;
 490
 491         switch (dongle_type) {
 492         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 493                 if (audio_support->hdmi_audio_on_dongle)
 494                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 495                 else
 496                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 497                 break;
 498         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 499                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 500                 break;
 501         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 502                 if (audio_support->hdmi_audio_native)
 503                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 504                 else
 505                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 506                 break;
 507         default:
 508                 signal = SIGNAL_TYPE_NONE;
 509                 break;
 510         }
 511
 512         return signal;
 513 }
 514
 515 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 516                                                     struct display_sink_capability *sink_cap,
 517                                                     struct audio_support *audio_support)
 518 {
 519         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 520
 521         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 522                                                         audio_support);
 523 }
 524
 525 static void link_disconnect_sink(struct dc_link *link)
 526 {
 527         if (link->local_sink) {
 528                 dc_sink_release(link->local_sink);
 529                 link->local_sink = NULL;
 530         }
 531
 532         link->dpcd_sink_count = 0;
 533 }
 534
 535 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 536 {
 537         dc_sink_release(link->local_sink);
 538         link->local_sink = prev_sink;
 539 }
 540
 541 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 542 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 543 {
 544         bool ret = false;
 545
 546         switch (signal) {
 547         case SIGNAL_TYPE_DISPLAY_PORT:
 548         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 549                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 550                 break;
 551         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 552         case SIGNAL_TYPE_DVI_DUAL_LINK:
 553         case SIGNAL_TYPE_HDMI_TYPE_A:
 554         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 555          * we can poll for bksv but some displays have an issue with this. Since its so rare
 556          * for a display to not be 1.4 capable, this assumtion is ok
 557          */
 558                 ret = true;
 559                 break;
 560         default:
 561                 break;
 562         }
 563         return ret;
 564 }
 565
 566 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 567 {
 568         bool ret = false;
 569
 570         switch (signal) {
 571         case SIGNAL_TYPE_DISPLAY_PORT:
 572         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 573                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 574                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 575                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 576                 break;
 577         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 578         case SIGNAL_TYPE_DVI_DUAL_LINK:
 579         case SIGNAL_TYPE_HDMI_TYPE_A:
 580                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 581                 break;
 582         default:
 583                 break;
 584         }
 585
 586         return ret;
 587 }
 588
 589 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 590 {
 591         struct hdcp_protection_message msg22;
 592         struct hdcp_protection_message msg14;
 593
 594         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 595         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 596         memset(link->hdcp_caps.rx_caps.raw, 0,
 597                 sizeof(link->hdcp_caps.rx_caps.raw));
 598
 599         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 600                         link->ddc->transaction_type ==
 601                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 602                         link->connector_signal == SIGNAL_TYPE_EDP) {
 603                 msg22.data = link->hdcp_caps.rx_caps.raw;
 604                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 605                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 606         } else {
 607                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 608                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 609                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 610         }
 611         msg22.version = HDCP_VERSION_22;
 612         msg22.link = HDCP_LINK_PRIMARY;
 613         msg22.max_retries = 5;
 614         dc_process_hdcp_msg(signal, link, &msg22);
 615
 616         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 617                 msg14.data = &link->hdcp_caps.bcaps.raw;
 618                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 619                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 620                 msg14.version = HDCP_VERSION_14;
 621                 msg14.link = HDCP_LINK_PRIMARY;
 622                 msg14.max_retries = 5;
 623
 624                 dc_process_hdcp_msg(signal, link, &msg14);
 625         }
 626
 627 }
 628 #endif
 629
 630 static void read_current_link_settings_on_detect(struct dc_link *link)
 631 {
 632         union lane_count_set lane_count_set = { {0} };
 633         uint8_t link_bw_set;
 634         uint8_t link_rate_set;
 635         uint32_t read_dpcd_retry_cnt = 10;
 636         enum dc_status status = DC_ERROR_UNEXPECTED;
 637         int i;
 638         union max_down_spread max_down_spread = { {0} };
 639
 640         // Read DPCD 00101h to find out the number of lanes currently set
 641         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 642                 status = core_link_read_dpcd(link,
 643                                              DP_LANE_COUNT_SET,
 644                                              &lane_count_set.raw,
 645                                              sizeof(lane_count_set));
 646                 /* First DPCD read after VDD ON can fail if the particular board
 647                  * does not have HPD pin wired correctly. So if DPCD read fails,
 648                  * which it should never happen, retry a few times. Target worst
 649                  * case scenario of 80 ms.
 650                  */
 651                 if (status == DC_OK) {
 652                         link->cur_link_settings.lane_count =
 653                                         lane_count_set.bits.LANE_COUNT_SET;
 654                         break;
 655                 }
 656
 657                 msleep(8);
 658         }
 659
 660         // Read DPCD 00100h to find if standard link rates are set
 661         core_link_read_dpcd(link, DP_LINK_BW_SET,
 662                             &link_bw_set, sizeof(link_bw_set));
 663
 664         if (link_bw_set == 0) {
 665                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 666                         /* If standard link rates are not being used,
 667                          * Read DPCD 00115h to find the edp link rate set used
 668                          */
 669                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 670                                             &link_rate_set, sizeof(link_rate_set));
 671
 672                         // edp_supported_link_rates_count = 0 for DP
 673                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 674                                 link->cur_link_settings.link_rate =
 675                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 676                                 link->cur_link_settings.link_rate_set = link_rate_set;
 677                                 link->cur_link_settings.use_link_rate_set = true;
 678                         }
 679                 } else {
 680                         // Link Rate not found. Seamless boot may not work.
 681                         ASSERT(false);
 682                 }
 683         } else {
 684                 link->cur_link_settings.link_rate = link_bw_set;
 685                 link->cur_link_settings.use_link_rate_set = false;
 686         }
 687         // Read DPCD 00003h to find the max down spread.
 688         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 689                             &max_down_spread.raw, sizeof(max_down_spread));
 690         link->cur_link_settings.link_spread =
 691                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 692                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 693 }
 694
 695 static bool detect_dp(struct dc_link *link,
 696                       struct display_sink_capability *sink_caps,
 697                       bool *converter_disable_audio,
 698                       struct audio_support *audio_support,
 699                       enum dc_detect_reason reason)
 700 {
 701         bool boot = false;
 702
 703         sink_caps->signal = link_detect_sink(link, reason);
 704         sink_caps->transaction_type =
 705                 get_ddc_transaction_type(sink_caps->signal);
 706
 707         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 708                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 709                 if (!detect_dp_sink_caps(link))
 710                         return false;
 711                 if (is_mst_supported(link)) {
 712                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 713                         link->type = dc_connection_mst_branch;
 714
 715                         dal_ddc_service_set_transaction_type(link->ddc,
 716                                                              sink_caps->transaction_type);
 717
 718 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 719                         /* In case of fallback to SST when topology discovery below fails
 720                          * HDCP caps will be querried again later by the upper layer (caller
 721                          * of this function). */
 722                         query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
 723 #endif
 724                         /*
 725                          * This call will initiate MST topology discovery. Which
 726                          * will detect MST ports and add new DRM connector DRM
 727                          * framework. Then read EDID via remote i2c over aux. In
 728                          * the end, will notify DRM detect result and save EDID
 729                          * into DRM framework.
 730                          *
 731                          * .detect is called by .fill_modes.
 732                          * .fill_modes is called by user mode ioctl
 733                          * DRM_IOCTL_MODE_GETCONNECTOR.
 734                          *
 735                          * .get_modes is called by .fill_modes.
 736                          *
 737                          * call .get_modes, AMDGPU DM implementation will create
 738                          * new dc_sink and add to dc_link. For long HPD plug
 739                          * in/out, MST has its own handle.
 740                          *
 741                          * Therefore, just after dc_create, link->sink is not
 742                          * created for MST until user mode app calls
 743                          * DRM_IOCTL_MODE_GETCONNECTOR.
 744                          *
 745                          * Need check ->sink usages in case ->sink = NULL
 746                          * TODO: s3 resume check
 747                          */
 748                         if (reason == DETECT_REASON_BOOT)
 749                                 boot = true;
 750
 751                         dm_helpers_dp_update_branch_info(link->ctx, link);
 752
 753                         if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
 754                                                              link, boot)) {
 755                                 /* MST not supported */
 756                                 link->type = dc_connection_single;
 757                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 758                         }
 759                 }
 760
 761                 if (link->type != dc_connection_mst_branch &&
 762                     is_dp_active_dongle(link)) {
 763                         /* DP active dongles */
 764                         link->type = dc_connection_active_dongle;
 765                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 766                                 /*
 767                                  * active dongle unplug processing for short irq
 768                                  */
 769                                 link_disconnect_sink(link);
 770                                 return true;
 771                         }
 772
 773                         if (link->dpcd_caps.dongle_type !=
 774                             DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 775                                 *converter_disable_audio = true;
 776                 }
 777         } else {
 778                 /* DP passive dongles */
 779                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 780                                                                 sink_caps,
 781                                                                 audio_support);
 782                 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 783         }
 784
 785         return true;
 786 }
 787
 788 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 789 {
 790         if (old_edid->length != new_edid->length)
 791                 return false;
 792
 793         if (new_edid->length == 0)
 794                 return false;
 795
 796         return (memcmp(old_edid->raw_edid,
 797                        new_edid->raw_edid, new_edid->length) == 0);
 798 }
 799
 800 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 801 {
 802         /**
 803          * something is terribly wrong if time out is > 200ms. (5Hz)
 804          * 500 microseconds * 400 tries us 200 ms
 805          **/
 806         unsigned int sleep_time_in_microseconds = 500;
 807         unsigned int tries_allowed = 400;
 808         bool is_in_alt_mode;
 809         unsigned long long enter_timestamp;
 810         unsigned long long finish_timestamp;
 811         unsigned long long time_taken_in_ns;
 812         int tries_taken;
 813
 814         DC_LOGGER_INIT(link->ctx->logger);
 815
 816         if (!link->link_enc->funcs->is_in_alt_mode)
 817                 return true;
 818
 819         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 820         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 821
 822         if (is_in_alt_mode)
 823                 return true;
 824
 825         enter_timestamp = dm_get_timestamp(link->ctx);
 826
 827         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 828                 udelay(sleep_time_in_microseconds);
 829                 /* ask the link if alt mode is enabled, if so return ok */
 830                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 831                         finish_timestamp = dm_get_timestamp(link->ctx);
 832                         time_taken_in_ns =
 833                                 dm_get_elapse_time_in_ns(link->ctx,
 834                                                          finish_timestamp,
 835                                                          enter_timestamp);
 836                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 837                                        div_u64(time_taken_in_ns, 1000000));
 838                         return true;
 839                 }
 840         }
 841         finish_timestamp = dm_get_timestamp(link->ctx);
 842         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 843                                                     enter_timestamp);
 844         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 845                        div_u64(time_taken_in_ns, 1000000));
 846         return false;
 847 }
 848
 849 /*
 850  * dc_link_detect() - Detect if a sink is attached to a given link
 851  *
 852  * link->local_sink is created or destroyed as needed.
 853  *
 854  * This does not create remote sinks but will trigger DM
 855  * to start MST detection if a branch is detected.
 856  */
 857 static bool dc_link_detect_helper(struct dc_link *link,
 858                                   enum dc_detect_reason reason)
 859 {
 860         struct dc_sink_init_data sink_init_data = { 0 };
 861         struct display_sink_capability sink_caps = { 0 };
 862         uint8_t i;
 863         bool converter_disable_audio = false;
 864         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 865         bool same_edid = false;
 866         enum dc_edid_status edid_status;
 867         struct dc_context *dc_ctx = link->ctx;
 868         struct dc_sink *sink = NULL;
 869         struct dc_sink *prev_sink = NULL;
 870         struct dpcd_caps prev_dpcd_caps;
 871         bool same_dpcd = true;
 872         enum dc_connection_type new_connection_type = dc_connection_none;
 873         enum dc_connection_type pre_connection_type = dc_connection_none;
 874         bool perform_dp_seamless_boot = false;
 875         const uint32_t post_oui_delay = 30; // 30ms
 876
 877         DC_LOGGER_INIT(link->ctx->logger);
 878
 879         if (dc_is_virtual_signal(link->connector_signal))
 880                 return false;
 881
 882         if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
 883              link->connector_signal == SIGNAL_TYPE_EDP) &&
 884             link->local_sink) {
 885                 // need to re-write OUI and brightness in resume case
 886                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 887                         dpcd_set_source_specific_data(link);
 888                         msleep(post_oui_delay);
 889                         dc_link_set_default_brightness_aux(link);
 890                         //TODO: use cached
 891                 }
 892
 893                 return true;
 894         }
 895
 896         if (!dc_link_detect_sink(link, &new_connection_type)) {
 897                 BREAK_TO_DEBUGGER();
 898                 return false;
 899         }
 900
 901         prev_sink = link->local_sink;
 902         if (prev_sink) {
 903                 dc_sink_retain(prev_sink);
 904                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 905         }
 906
 907         link_disconnect_sink(link);
 908         if (new_connection_type != dc_connection_none) {
 909                 pre_connection_type = link->type;
 910                 link->type = new_connection_type;
 911                 link->link_state_valid = false;
 912
 913                 /* From Disconnected-to-Connected. */
 914                 switch (link->connector_signal) {
 915                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 916                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 917                         if (aud_support->hdmi_audio_native)
 918                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 919                         else
 920                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 921                         break;
 922                 }
 923
 924                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 925                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 926                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 927                         break;
 928                 }
 929
 930                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 931                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 932                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 933                         break;
 934                 }
 935
 936                 case SIGNAL_TYPE_LVDS: {
 937                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 938                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 939                         break;
 940                 }
 941
 942                 case SIGNAL_TYPE_EDP: {
 943                         read_current_link_settings_on_detect(link);
 944
 945                         detect_edp_sink_caps(link);
 946                         read_current_link_settings_on_detect(link);
 947                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 948                         sink_caps.signal = SIGNAL_TYPE_EDP;
 949                         break;
 950                 }
 951
 952                 case SIGNAL_TYPE_DISPLAY_PORT: {
 953                         /* wa HPD high coming too early*/
 954                         if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 955                                 /* if alt mode times out, return false */
 956                                 if (!wait_for_entering_dp_alt_mode(link))
 957                                         return false;
 958                         }
 959
 960                         if (!detect_dp(link, &sink_caps,
 961                                        &converter_disable_audio,
 962                                        aud_support, reason)) {
 963                                 if (prev_sink)
 964                                         dc_sink_release(prev_sink);
 965                                 return false;
 966                         }
 967
 968                         // Check if dpcp block is the same
 969                         if (prev_sink) {
 970                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps,
 971                                            sizeof(struct dpcd_caps)))
 972                                         same_dpcd = false;
 973                         }
 974                         /* Active dongle downstream unplug*/
 975                         if (link->type == dc_connection_active_dongle &&
 976                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 977                                 if (prev_sink)
 978                                         /* Downstream unplug */
 979                                         dc_sink_release(prev_sink);
 980                                 return true;
 981                         }
 982
 983                         // link switch from MST to non-MST stop topology manager
 984                         if (pre_connection_type == dc_connection_mst_branch &&
 985                                 link->type != dc_connection_mst_branch) {
 986                                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 987                         }
 988
 989                         if (link->type == dc_connection_mst_branch) {
 990                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 991                                           link->link_index);
 992                                 /* Need to setup mst link_cap struct here
 993                                  * otherwise dc_link_detect() will leave mst link_cap
 994                                  * empty which leads to allocate_mst_payload() has "0"
 995                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 996                                  */
 997                                 dp_verify_mst_link_cap(link);
 998
 999                                 if (prev_sink)
1000                                         dc_sink_release(prev_sink);
1001                                 return false;
1002                         }
1003
1004                         // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
1005                         if (reason == DETECT_REASON_BOOT &&
1006                             !dc_ctx->dc->config.power_down_display_on_boot &&
1007                             link->link_status.link_active)
1008                                 perform_dp_seamless_boot = true;
1009
1010                         if (perform_dp_seamless_boot) {
1011                                 read_current_link_settings_on_detect(link);
1012                                 link->verified_link_cap = link->reported_link_cap;
1013                         }
1014
1015                         break;
1016                 }
1017
1018                 default:
1019                         DC_ERROR("Invalid connector type! signal:%d\n",
1020                                  link->connector_signal);
1021                         if (prev_sink)
1022                                 dc_sink_release(prev_sink);
1023                         return false;
1024                 } /* switch() */
1025
1026                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1027                         link->dpcd_sink_count =
1028                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1029                 else
1030                         link->dpcd_sink_count = 1;
1031
1032                 dal_ddc_service_set_transaction_type(link->ddc,
1033                                                      sink_caps.transaction_type);
1034
1035                 link->aux_mode =
1036                         dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1037
1038                 sink_init_data.link = link;
1039                 sink_init_data.sink_signal = sink_caps.signal;
1040
1041                 sink = dc_sink_create(&sink_init_data);
1042                 if (!sink) {
1043                         DC_ERROR("Failed to create sink!\n");
1044                         if (prev_sink)
1045                                 dc_sink_release(prev_sink);
1046                         return false;
1047                 }
1048
1049                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1050                 sink->converter_disable_audio = converter_disable_audio;
1051
1052                 /* dc_sink_create returns a new reference */
1053                 link->local_sink = sink;
1054
1055                 edid_status = dm_helpers_read_local_edid(link->ctx,
1056                                                          link, sink);
1057
1058                 switch (edid_status) {
1059                 case EDID_BAD_CHECKSUM:
1060                         DC_LOG_ERROR("EDID checksum invalid.\n");
1061                         break;
1062                 case EDID_NO_RESPONSE:
1063                         DC_LOG_ERROR("No EDID read.\n");
1064                         /*
1065                          * Abort detection for non-DP connectors if we have
1066                          * no EDID
1067                          *
1068                          * DP needs to report as connected if HDP is high
1069                          * even if we have no EDID in order to go to
1070                          * fail-safe mode
1071                          */
1072                         if (dc_is_hdmi_signal(link->connector_signal) ||
1073                             dc_is_dvi_signal(link->connector_signal)) {
1074                                 if (prev_sink)
1075                                         dc_sink_release(prev_sink);
1076
1077                                 return false;
1078                         }
1079                         break;
1080                 default:
1081                         break;
1082                 }
1083
1084                 // Check if edid is the same
1085                 if ((prev_sink) &&
1086                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1087                         same_edid = is_same_edid(&prev_sink->dc_edid,
1088                                                  &sink->dc_edid);
1089
1090                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1091                         link->ctx->dc->debug.hdmi20_disable = true;
1092
1093                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1094                     sink_caps.transaction_type ==
1095                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1096                         /*
1097                          * TODO debug why Dell 2413 doesn't like
1098                          *  two link trainings
1099                          */
1100 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1101                         query_hdcp_capability(sink->sink_signal, link);
1102 #endif
1103
1104                         // verify link cap for SST non-seamless boot
1105                         if (!perform_dp_seamless_boot)
1106                                 dp_verify_link_cap_with_retries(link,
1107                                                                 &link->reported_link_cap,
1108                                                                 LINK_TRAINING_MAX_VERIFY_RETRY);
1109                 } else {
1110                         // If edid is the same, then discard new sink and revert back to original sink
1111                         if (same_edid) {
1112                                 link_disconnect_remap(prev_sink, link);
1113                                 sink = prev_sink;
1114                                 prev_sink = NULL;
1115                         }
1116 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1117                         query_hdcp_capability(sink->sink_signal, link);
1118 #endif
1119                 }
1120
1121                 /* HDMI-DVI Dongle */
1122                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1123                     !sink->edid_caps.edid_hdmi)
1124                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1125
1126                 /* Connectivity log: detection */
1127                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1128                         CONN_DATA_DETECT(link,
1129                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1130                                          DC_EDID_BLOCK_SIZE,
1131                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1132                 }
1133
1134                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1135                         "manufacturer_id = %X, "
1136                         "product_id = %X, "
1137                         "serial_number = %X, "
1138                         "manufacture_week = %d, "
1139                         "manufacture_year = %d, "
1140                         "display_name = %s, "
1141                         "speaker_flag = %d, "
1142                         "audio_mode_count = %d\n",
1143                         __func__,
1144                         sink->edid_caps.manufacturer_id,
1145                         sink->edid_caps.product_id,
1146                         sink->edid_caps.serial_number,
1147                         sink->edid_caps.manufacture_week,
1148                         sink->edid_caps.manufacture_year,
1149                         sink->edid_caps.display_name,
1150                         sink->edid_caps.speaker_flags,
1151                         sink->edid_caps.audio_mode_count);
1152
1153                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1154                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1155                                 "format_code = %d, "
1156                                 "channel_count = %d, "
1157                                 "sample_rate = %d, "
1158                                 "sample_size = %d\n",
1159                                 __func__,
1160                                 i,
1161                                 sink->edid_caps.audio_modes[i].format_code,
1162                                 sink->edid_caps.audio_modes[i].channel_count,
1163                                 sink->edid_caps.audio_modes[i].sample_rate,
1164                                 sink->edid_caps.audio_modes[i].sample_size);
1165                 }
1166         } else {
1167                 /* From Connected-to-Disconnected. */
1168                 if (link->type == dc_connection_mst_branch) {
1169                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
1170                                   link->link_index);
1171
1172                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1173
1174                         link->mst_stream_alloc_table.stream_count = 0;
1175                         memset(link->mst_stream_alloc_table.stream_allocations,
1176                                0,
1177                                sizeof(link->mst_stream_alloc_table.stream_allocations));
1178                 }
1179
1180                 link->type = dc_connection_none;
1181                 sink_caps.signal = SIGNAL_TYPE_NONE;
1182                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1183                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1184                  *  the dongle is still there and limits the number of modes we can emulate.
1185                  *  Clear dongle_max_pix_clk on disconnect to fix this
1186                  */
1187                 link->dongle_max_pix_clk = 0;
1188         }
1189
1190         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
1191                   link->link_index, sink,
1192                   (sink_caps.signal ==
1193                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1194                   prev_sink, same_dpcd, same_edid);
1195
1196         if (prev_sink)
1197                 dc_sink_release(prev_sink);
1198
1199         return true;
1200 }
1201
1202 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1203 {
1204         const struct dc *dc = link->dc;
1205         bool ret;
1206
1207         /* get out of low power state */
1208         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1209
1210         ret = dc_link_detect_helper(link, reason);
1211
1212         /* Go back to power optimized state */
1213         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1214
1215         return ret;
1216 }
1217
1218 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1219 {
1220         uint32_t state;
1221
1222         dal_gpio_lock_pin(dc_link->hpd_gpio);
1223         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1224         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1225
1226         return state;
1227 }
1228
1229 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1230 {
1231         struct gpio *hpd;
1232         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1233
1234         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1235                            link->ctx->gpio_service);
1236
1237         if (hpd) {
1238                 switch (dal_irq_get_source(hpd)) {
1239                 case DC_IRQ_SOURCE_HPD1:
1240                         hpd_id = HPD_SOURCEID1;
1241                 break;
1242                 case DC_IRQ_SOURCE_HPD2:
1243                         hpd_id = HPD_SOURCEID2;
1244                 break;
1245                 case DC_IRQ_SOURCE_HPD3:
1246                         hpd_id = HPD_SOURCEID3;
1247                 break;
1248                 case DC_IRQ_SOURCE_HPD4:
1249                         hpd_id = HPD_SOURCEID4;
1250                 break;
1251                 case DC_IRQ_SOURCE_HPD5:
1252                         hpd_id = HPD_SOURCEID5;
1253                 break;
1254                 case DC_IRQ_SOURCE_HPD6:
1255                         hpd_id = HPD_SOURCEID6;
1256                 break;
1257                 default:
1258                         BREAK_TO_DEBUGGER();
1259                 break;
1260                 }
1261
1262                 dal_gpio_destroy_irq(&hpd);
1263         }
1264
1265         return hpd_id;
1266 }
1267
1268 static enum channel_id get_ddc_line(struct dc_link *link)
1269 {
1270         struct ddc *ddc;
1271         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1272
1273         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1274
1275         if (ddc) {
1276                 switch (dal_ddc_get_line(ddc)) {
1277                 case GPIO_DDC_LINE_DDC1:
1278                         channel = CHANNEL_ID_DDC1;
1279                         break;
1280                 case GPIO_DDC_LINE_DDC2:
1281                         channel = CHANNEL_ID_DDC2;
1282                         break;
1283                 case GPIO_DDC_LINE_DDC3:
1284                         channel = CHANNEL_ID_DDC3;
1285                         break;
1286                 case GPIO_DDC_LINE_DDC4:
1287                         channel = CHANNEL_ID_DDC4;
1288                         break;
1289                 case GPIO_DDC_LINE_DDC5:
1290                         channel = CHANNEL_ID_DDC5;
1291                         break;
1292                 case GPIO_DDC_LINE_DDC6:
1293                         channel = CHANNEL_ID_DDC6;
1294                         break;
1295                 case GPIO_DDC_LINE_DDC_VGA:
1296                         channel = CHANNEL_ID_DDC_VGA;
1297                         break;
1298                 case GPIO_DDC_LINE_I2C_PAD:
1299                         channel = CHANNEL_ID_I2C_PAD;
1300                         break;
1301                 default:
1302                         BREAK_TO_DEBUGGER();
1303                         break;
1304                 }
1305         }
1306
1307         return channel;
1308 }
1309
1310 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1311 {
1312         switch (encoder.id) {
1313         case ENCODER_ID_INTERNAL_UNIPHY:
1314                 switch (encoder.enum_id) {
1315                 case ENUM_ID_1:
1316                         return TRANSMITTER_UNIPHY_A;
1317                 case ENUM_ID_2:
1318                         return TRANSMITTER_UNIPHY_B;
1319                 default:
1320                         return TRANSMITTER_UNKNOWN;
1321                 }
1322         break;
1323         case ENCODER_ID_INTERNAL_UNIPHY1:
1324                 switch (encoder.enum_id) {
1325                 case ENUM_ID_1:
1326                         return TRANSMITTER_UNIPHY_C;
1327                 case ENUM_ID_2:
1328                         return TRANSMITTER_UNIPHY_D;
1329                 default:
1330                         return TRANSMITTER_UNKNOWN;
1331                 }
1332         break;
1333         case ENCODER_ID_INTERNAL_UNIPHY2:
1334                 switch (encoder.enum_id) {
1335                 case ENUM_ID_1:
1336                         return TRANSMITTER_UNIPHY_E;
1337                 case ENUM_ID_2:
1338                         return TRANSMITTER_UNIPHY_F;
1339                 default:
1340                         return TRANSMITTER_UNKNOWN;
1341                 }
1342         break;
1343         case ENCODER_ID_INTERNAL_UNIPHY3:
1344                 switch (encoder.enum_id) {
1345                 case ENUM_ID_1:
1346                         return TRANSMITTER_UNIPHY_G;
1347                 default:
1348                         return TRANSMITTER_UNKNOWN;
1349                 }
1350         break;
1351         case ENCODER_ID_EXTERNAL_NUTMEG:
1352                 switch (encoder.enum_id) {
1353                 case ENUM_ID_1:
1354                         return TRANSMITTER_NUTMEG_CRT;
1355                 default:
1356                         return TRANSMITTER_UNKNOWN;
1357                 }
1358         break;
1359         case ENCODER_ID_EXTERNAL_TRAVIS:
1360                 switch (encoder.enum_id) {
1361                 case ENUM_ID_1:
1362                         return TRANSMITTER_TRAVIS_CRT;
1363                 case ENUM_ID_2:
1364                         return TRANSMITTER_TRAVIS_LCD;
1365                 default:
1366                         return TRANSMITTER_UNKNOWN;
1367                 }
1368         break;
1369         default:
1370                 return TRANSMITTER_UNKNOWN;
1371         }
1372 }
1373
1374 static bool dc_link_construct(struct dc_link *link,
1375                               const struct link_init_data *init_params)
1376 {
1377         uint8_t i;
1378         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1379         struct dc_context *dc_ctx = init_params->ctx;
1380         struct encoder_init_data enc_init_data = { 0 };
1381         struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1382         struct integrated_info *info;
1383         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1384         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1385         struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1386
1387         DC_LOGGER_INIT(dc_ctx->logger);
1388
1389         info = kzalloc(sizeof(*info), GFP_KERNEL);
1390         if (!info)
1391                 goto create_fail;
1392
1393         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1394         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1395
1396         link->link_status.dpcd_caps = &link->dpcd_caps;
1397
1398         link->dc = init_params->dc;
1399         link->ctx = dc_ctx;
1400         link->link_index = init_params->link_index;
1401
1402         memset(&link->preferred_training_settings, 0,
1403                sizeof(struct dc_link_training_overrides));
1404         memset(&link->preferred_link_setting, 0,
1405                sizeof(struct dc_link_settings));
1406
1407         link->link_id =
1408                 bios->funcs->get_connector_id(bios, init_params->connector_index);
1409
1410         DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1411
1412         if (bios->funcs->get_disp_connector_caps_info) {
1413                 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1414                 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1415                 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1416         }
1417
1418         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1419                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1420                                      __func__, init_params->connector_index,
1421                                      link->link_id.type, OBJECT_TYPE_CONNECTOR);
1422                 goto create_fail;
1423         }
1424
1425         if (link->dc->res_pool->funcs->link_init)
1426                 link->dc->res_pool->funcs->link_init(link);
1427
1428         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1429                                       link->ctx->gpio_service);
1430
1431         if (link->hpd_gpio) {
1432                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1433                 dal_gpio_unlock_pin(link->hpd_gpio);
1434                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1435
1436                 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1437                 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1438         }
1439
1440         switch (link->link_id.id) {
1441         case CONNECTOR_ID_HDMI_TYPE_A:
1442                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1443
1444                 break;
1445         case CONNECTOR_ID_SINGLE_LINK_DVID:
1446         case CONNECTOR_ID_SINGLE_LINK_DVII:
1447                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1448                 break;
1449         case CONNECTOR_ID_DUAL_LINK_DVID:
1450         case CONNECTOR_ID_DUAL_LINK_DVII:
1451                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1452                 break;
1453         case CONNECTOR_ID_DISPLAY_PORT:
1454                 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1455
1456                 if (link->hpd_gpio)
1457                         link->irq_source_hpd_rx =
1458                                         dal_irq_get_rx_source(link->hpd_gpio);
1459
1460                 break;
1461         case CONNECTOR_ID_EDP:
1462                 link->connector_signal = SIGNAL_TYPE_EDP;
1463
1464                 if (link->hpd_gpio) {
1465                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1466                         link->irq_source_hpd_rx =
1467                                         dal_irq_get_rx_source(link->hpd_gpio);
1468                 }
1469
1470                 break;
1471         case CONNECTOR_ID_LVDS:
1472                 link->connector_signal = SIGNAL_TYPE_LVDS;
1473                 break;
1474         default:
1475                 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1476                                link->link_id.id);
1477                 goto create_fail;
1478         }
1479
1480         /* TODO: #DAL3 Implement id to str function.*/
1481         LINK_INFO("Connector[%d] description:"
1482                   "signal %d\n",
1483                   init_params->connector_index,
1484                   link->connector_signal);
1485
1486         ddc_service_init_data.ctx = link->ctx;
1487         ddc_service_init_data.id = link->link_id;
1488         ddc_service_init_data.link = link;
1489         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1490
1491         if (!link->ddc) {
1492                 DC_ERROR("Failed to create ddc_service!\n");
1493                 goto ddc_create_fail;
1494         }
1495
1496         if (!link->ddc->ddc_pin) {
1497                 DC_ERROR("Failed to get I2C info for connector!\n");
1498                 goto ddc_create_fail;
1499         }
1500
1501         link->ddc_hw_inst =
1502                 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1503
1504
1505         if (link->dc->res_pool->funcs->panel_cntl_create &&
1506                 (link->link_id.id == CONNECTOR_ID_EDP ||
1507                         link->link_id.id == CONNECTOR_ID_LVDS)) {
1508                 panel_cntl_init_data.ctx = dc_ctx;
1509                 panel_cntl_init_data.inst = 0;
1510                 link->panel_cntl =
1511                         link->dc->res_pool->funcs->panel_cntl_create(
1512                                                                 &panel_cntl_init_data);
1513
1514                 if (link->panel_cntl == NULL) {
1515                         DC_ERROR("Failed to create link panel_cntl!\n");
1516                         goto panel_cntl_create_fail;
1517                 }
1518         }
1519
1520         enc_init_data.ctx = dc_ctx;
1521         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1522                               &enc_init_data.encoder);
1523         enc_init_data.connector = link->link_id;
1524         enc_init_data.channel = get_ddc_line(link);
1525         enc_init_data.hpd_source = get_hpd_line(link);
1526
1527         link->hpd_src = enc_init_data.hpd_source;
1528
1529         enc_init_data.transmitter =
1530                 translate_encoder_to_transmitter(enc_init_data.encoder);
1531         link->link_enc =
1532                 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1533
1534         if (!link->link_enc) {
1535                 DC_ERROR("Failed to create link encoder!\n");
1536                 goto link_enc_create_fail;
1537         }
1538
1539         DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1540
1541         /* Update link encoder tracking variables. These are used for the dynamic
1542          * assignment of link encoders to streams.
1543          */
1544         link->dc->res_pool->link_encoders[link->link_enc->preferred_engine] = link->link_enc;
1545         link->dc->res_pool->dig_link_enc_count++;
1546
1547         link->link_enc_hw_inst = link->link_enc->transmitter;
1548
1549         for (i = 0; i < 4; i++) {
1550                 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1551                                              link->link_id, i,
1552                                              &link->device_tag) != BP_RESULT_OK) {
1553                         DC_ERROR("Failed to find device tag!\n");
1554                         goto device_tag_fail;
1555                 }
1556
1557                 /* Look for device tag that matches connector signal,
1558                  * CRT for rgb, LCD for other supported signal tyes
1559                  */
1560                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1561                                                       link->device_tag.dev_id))
1562                         continue;
1563                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1564                     link->connector_signal != SIGNAL_TYPE_RGB)
1565                         continue;
1566                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1567                     link->connector_signal == SIGNAL_TYPE_RGB)
1568                         continue;
1569
1570                 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1571                 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1572                 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1573                 break;
1574         }
1575
1576         if (bios->integrated_info)
1577                 memcpy(info, bios->integrated_info, sizeof(*info));
1578
1579         /* Look for channel mapping corresponding to connector and device tag */
1580         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1581                 struct external_display_path *path =
1582                         &info->ext_disp_conn_info.path[i];
1583
1584                 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1585                     path->device_connector_id.id == link->link_id.id &&
1586                     path->device_connector_id.type == link->link_id.type) {
1587                         if (link->device_tag.acpi_device != 0 &&
1588                             path->device_acpi_enum == link->device_tag.acpi_device) {
1589                                 link->ddi_channel_mapping = path->channel_mapping;
1590                                 link->chip_caps = path->caps;
1591                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1592                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1593                         } else if (path->device_tag ==
1594                                    link->device_tag.dev_id.raw_device_tag) {
1595                                 link->ddi_channel_mapping = path->channel_mapping;
1596                                 link->chip_caps = path->caps;
1597                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1598                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1599                         }
1600                         break;
1601                 }
1602         }
1603
1604         if (bios->funcs->get_atom_dc_golden_table)
1605                 bios->funcs->get_atom_dc_golden_table(bios);
1606
1607         /*
1608          * TODO check if GPIO programmed correctly
1609          *
1610          * If GPIO isn't programmed correctly HPD might not rise or drain
1611          * fast enough, leading to bounces.
1612          */
1613         program_hpd_filter(link);
1614
1615         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1616
1617         DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1618         return true;
1619 device_tag_fail:
1620         link->link_enc->funcs->destroy(&link->link_enc);
1621 link_enc_create_fail:
1622         if (link->panel_cntl != NULL)
1623                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1624 panel_cntl_create_fail:
1625         dal_ddc_service_destroy(&link->ddc);
1626 ddc_create_fail:
1627 create_fail:
1628
1629         if (link->hpd_gpio) {
1630                 dal_gpio_destroy_irq(&link->hpd_gpio);
1631                 link->hpd_gpio = NULL;
1632         }
1633
1634         DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1635         kfree(info);
1636
1637         return false;
1638 }
1639
1640 /*******************************************************************************
1641  * Public functions
1642  ******************************************************************************/
1643 struct dc_link *link_create(const struct link_init_data *init_params)
1644 {
1645         struct dc_link *link =
1646                         kzalloc(sizeof(*link), GFP_KERNEL);
1647
1648         if (NULL == link)
1649                 goto alloc_fail;
1650
1651         if (false == dc_link_construct(link, init_params))
1652                 goto construct_fail;
1653
1654         return link;
1655
1656 construct_fail:
1657         kfree(link);
1658
1659 alloc_fail:
1660         return NULL;
1661 }
1662
1663 void link_destroy(struct dc_link **link)
1664 {
1665         dc_link_destruct(*link);
1666         kfree(*link);
1667         *link = NULL;
1668 }
1669
1670 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1671 {
1672         struct dc_stream_state *stream = pipe_ctx->stream;
1673         struct dc_link *link = stream->link;
1674         union down_spread_ctrl old_downspread;
1675         union down_spread_ctrl new_downspread;
1676
1677         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1678                         &old_downspread.raw, sizeof(old_downspread));
1679
1680         new_downspread.raw = old_downspread.raw;
1681
1682         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1683                         (stream->ignore_msa_timing_param) ? 1 : 0;
1684
1685         if (new_downspread.raw != old_downspread.raw) {
1686                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1687                         &new_downspread.raw, sizeof(new_downspread));
1688         }
1689 }
1690
1691 static enum dc_status enable_link_dp(struct dc_state *state,
1692                                      struct pipe_ctx *pipe_ctx)
1693 {
1694         struct dc_stream_state *stream = pipe_ctx->stream;
1695         enum dc_status status;
1696         bool skip_video_pattern;
1697         struct dc_link *link = stream->link;
1698         struct dc_link_settings link_settings = {0};
1699         bool fec_enable;
1700         int i;
1701         bool apply_seamless_boot_optimization = false;
1702         uint32_t bl_oled_enable_delay = 50; // in ms
1703         const uint32_t post_oui_delay = 30; // 30ms
1704
1705         // check for seamless boot
1706         for (i = 0; i < state->stream_count; i++) {
1707                 if (state->streams[i]->apply_seamless_boot_optimization) {
1708                         apply_seamless_boot_optimization = true;
1709                         break;
1710                 }
1711         }
1712
1713         /* get link settings for video mode timing */
1714         decide_link_settings(stream, &link_settings);
1715
1716         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1717                 /*in case it is not on*/
1718                 link->dc->hwss.edp_power_control(link, true);
1719                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1720         }
1721
1722         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1723                         link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1724         if (state->clk_mgr && !apply_seamless_boot_optimization)
1725                 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1726                                                      state, false);
1727
1728         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1729         dpcd_set_source_specific_data(link);
1730         if (link->dpcd_sink_ext_caps.raw != 0)
1731                 msleep(post_oui_delay);
1732
1733         skip_video_pattern = true;
1734
1735         if (link_settings.link_rate == LINK_RATE_LOW)
1736                 skip_video_pattern = false;
1737
1738         if (perform_link_training_with_retries(&link_settings,
1739                                                skip_video_pattern,
1740                                                LINK_TRAINING_ATTEMPTS,
1741                                                pipe_ctx,
1742                                                pipe_ctx->stream->signal)) {
1743                 link->cur_link_settings = link_settings;
1744                 status = DC_OK;
1745         } else {
1746                 status = DC_FAIL_DP_LINK_TRAINING;
1747         }
1748
1749         if (link->preferred_training_settings.fec_enable)
1750                 fec_enable = *link->preferred_training_settings.fec_enable;
1751         else
1752                 fec_enable = true;
1753
1754         dp_set_fec_enable(link, fec_enable);
1755
1756         // during mode set we do DP_SET_POWER off then on, aux writes are lost
1757         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
1758                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
1759                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
1760                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
1761                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
1762                         msleep(bl_oled_enable_delay);
1763                 dc_link_backlight_enable_aux(link, true);
1764         }
1765
1766         return status;
1767 }
1768
1769 static enum dc_status enable_link_edp(
1770                 struct dc_state *state,
1771                 struct pipe_ctx *pipe_ctx)
1772 {
1773         enum dc_status status;
1774
1775         status = enable_link_dp(state, pipe_ctx);
1776
1777         return status;
1778 }
1779
1780 static enum dc_status enable_link_dp_mst(
1781                 struct dc_state *state,
1782                 struct pipe_ctx *pipe_ctx)
1783 {
1784         struct dc_link *link = pipe_ctx->stream->link;
1785
1786         /* sink signal type after MST branch is MST. Multiple MST sinks
1787          * share one link. Link DP PHY is enable or training only once.
1788          */
1789         if (link->link_status.link_active)
1790                 return DC_OK;
1791
1792         /* clear payload table */
1793         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1794
1795         /* to make sure the pending down rep can be processed
1796          * before enabling the link
1797          */
1798         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1799
1800         /* set the sink to MST mode before enabling the link */
1801         dp_enable_mst_on_sink(link, true);
1802
1803         return enable_link_dp(state, pipe_ctx);
1804 }
1805
1806 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1807                 enum engine_id eng_id,
1808                 struct ext_hdmi_settings *settings)
1809 {
1810         bool result = false;
1811         int i = 0;
1812         struct integrated_info *integrated_info =
1813                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1814
1815         if (integrated_info == NULL)
1816                 return false;
1817
1818         /*
1819          * Get retimer settings from sbios for passing SI eye test for DCE11
1820          * The setting values are varied based on board revision and port id
1821          * Therefore the setting values of each ports is passed by sbios.
1822          */
1823
1824         // Check if current bios contains ext Hdmi settings
1825         if (integrated_info->gpu_cap_info & 0x20) {
1826                 switch (eng_id) {
1827                 case ENGINE_ID_DIGA:
1828                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1829                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1830                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1831                         memmove(settings->reg_settings,
1832                                         integrated_info->dp0_ext_hdmi_reg_settings,
1833                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1834                         memmove(settings->reg_settings_6g,
1835                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1836                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1837                         result = true;
1838                         break;
1839                 case ENGINE_ID_DIGB:
1840                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1841                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1842                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1843                         memmove(settings->reg_settings,
1844                                         integrated_info->dp1_ext_hdmi_reg_settings,
1845                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1846                         memmove(settings->reg_settings_6g,
1847                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1848                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1849                         result = true;
1850                         break;
1851                 case ENGINE_ID_DIGC:
1852                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1853                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1854                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1855                         memmove(settings->reg_settings,
1856                                         integrated_info->dp2_ext_hdmi_reg_settings,
1857                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1858                         memmove(settings->reg_settings_6g,
1859                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1860                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1861                         result = true;
1862                         break;
1863                 case ENGINE_ID_DIGD:
1864                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1865                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1866                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1867                         memmove(settings->reg_settings,
1868                                         integrated_info->dp3_ext_hdmi_reg_settings,
1869                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1870                         memmove(settings->reg_settings_6g,
1871                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1872                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1873                         result = true;
1874                         break;
1875                 default:
1876                         break;
1877                 }
1878
1879                 if (result == true) {
1880                         // Validate settings from bios integrated info table
1881                         if (settings->slv_addr == 0)
1882                                 return false;
1883                         if (settings->reg_num > 9)
1884                                 return false;
1885                         if (settings->reg_num_6g > 3)
1886                                 return false;
1887
1888                         for (i = 0; i < settings->reg_num; i++) {
1889                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1890                                         return false;
1891                         }
1892
1893                         for (i = 0; i < settings->reg_num_6g; i++) {
1894                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1895                                         return false;
1896                         }
1897                 }
1898         }
1899
1900         return result;
1901 }
1902
1903 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1904                 uint8_t address, uint8_t *buffer, uint32_t length)
1905 {
1906         struct i2c_command cmd = {0};
1907         struct i2c_payload payload = {0};
1908
1909         memset(&payload, 0, sizeof(payload));
1910         memset(&cmd, 0, sizeof(cmd));
1911
1912         cmd.number_of_payloads = 1;
1913         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1914         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1915
1916         payload.address = address;
1917         payload.data = buffer;
1918         payload.length = length;
1919         payload.write = true;
1920         cmd.payloads = &payload;
1921
1922         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1923                         pipe_ctx->stream->link, &cmd))
1924                 return true;
1925
1926         return false;
1927 }
1928
1929 static void write_i2c_retimer_setting(
1930                 struct pipe_ctx *pipe_ctx,
1931                 bool is_vga_mode,
1932                 bool is_over_340mhz,
1933                 struct ext_hdmi_settings *settings)
1934 {
1935         uint8_t slave_address = (settings->slv_addr >> 1);
1936         uint8_t buffer[2];
1937         const uint8_t apply_rx_tx_change = 0x4;
1938         uint8_t offset = 0xA;
1939         uint8_t value = 0;
1940         int i = 0;
1941         bool i2c_success = false;
1942         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1943
1944         memset(&buffer, 0, sizeof(buffer));
1945
1946         /* Start Ext-Hdmi programming*/
1947
1948         for (i = 0; i < settings->reg_num; i++) {
1949                 /* Apply 3G settings */
1950                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1951
1952                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1953                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1954                         i2c_success = i2c_write(pipe_ctx, slave_address,
1955                                                 buffer, sizeof(buffer));
1956                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1957                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1958                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1959
1960                         if (!i2c_success)
1961                                 goto i2c_write_fail;
1962
1963                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1964                          * needs to be set to 1 on every 0xA-0xC write.
1965                          */
1966                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1967                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1968                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1969
1970                                 /* Query current value from offset 0xA */
1971                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1972                                         value = settings->reg_settings[i].i2c_reg_val;
1973                                 else {
1974                                         i2c_success =
1975                                                 dal_ddc_service_query_ddc_data(
1976                                                 pipe_ctx->stream->link->ddc,
1977                                                 slave_address, &offset, 1, &value, 1);
1978                                         if (!i2c_success)
1979                                                 goto i2c_write_fail;
1980                                 }
1981
1982                                 buffer[0] = offset;
1983                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1984                                 buffer[1] = value | apply_rx_tx_change;
1985                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1986                                                 buffer, sizeof(buffer));
1987                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1988                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1989                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1990                                 if (!i2c_success)
1991                                         goto i2c_write_fail;
1992                         }
1993                 }
1994         }
1995
1996         /* Apply 3G settings */
1997         if (is_over_340mhz) {
1998                 for (i = 0; i < settings->reg_num_6g; i++) {
1999                         /* Apply 3G settings */
2000                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2001
2002                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2003                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2004                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2005                                                         buffer, sizeof(buffer));
2006                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2007                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2008                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2009
2010                                 if (!i2c_success)
2011                                         goto i2c_write_fail;
2012
2013                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2014                                  * needs to be set to 1 on every 0xA-0xC write.
2015                                  */
2016                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2017                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2018                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2019
2020                                         /* Query current value from offset 0xA */
2021                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2022                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
2023                                         else {
2024                                                 i2c_success =
2025                                                                 dal_ddc_service_query_ddc_data(
2026                                                                 pipe_ctx->stream->link->ddc,
2027                                                                 slave_address, &offset, 1, &value, 1);
2028                                                 if (!i2c_success)
2029                                                         goto i2c_write_fail;
2030                                         }
2031
2032                                         buffer[0] = offset;
2033                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
2034                                         buffer[1] = value | apply_rx_tx_change;
2035                                         i2c_success = i2c_write(pipe_ctx, slave_address,
2036                                                         buffer, sizeof(buffer));
2037                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2038                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2039                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2040                                         if (!i2c_success)
2041                                                 goto i2c_write_fail;
2042                                 }
2043                         }
2044                 }
2045         }
2046
2047         if (is_vga_mode) {
2048                 /* Program additional settings if using 640x480 resolution */
2049
2050                 /* Write offset 0xFF to 0x01 */
2051                 buffer[0] = 0xff;
2052                 buffer[1] = 0x01;
2053                 i2c_success = i2c_write(pipe_ctx, slave_address,
2054                                 buffer, sizeof(buffer));
2055                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2056                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2057                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2058                 if (!i2c_success)
2059                         goto i2c_write_fail;
2060
2061                 /* Write offset 0x00 to 0x23 */
2062                 buffer[0] = 0x00;
2063                 buffer[1] = 0x23;
2064                 i2c_success = i2c_write(pipe_ctx, slave_address,
2065                                 buffer, sizeof(buffer));
2066                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2067                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2068                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2069                 if (!i2c_success)
2070                         goto i2c_write_fail;
2071
2072                 /* Write offset 0xff to 0x00 */
2073                 buffer[0] = 0xff;
2074                 buffer[1] = 0x00;
2075                 i2c_success = i2c_write(pipe_ctx, slave_address,
2076                                 buffer, sizeof(buffer));
2077                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2078                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2079                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2080                 if (!i2c_success)
2081                         goto i2c_write_fail;
2082
2083         }
2084
2085         return;
2086
2087 i2c_write_fail:
2088         DC_LOG_DEBUG("Set retimer failed");
2089 }
2090
2091 static void write_i2c_default_retimer_setting(
2092                 struct pipe_ctx *pipe_ctx,
2093                 bool is_vga_mode,
2094                 bool is_over_340mhz)
2095 {
2096         uint8_t slave_address = (0xBA >> 1);
2097         uint8_t buffer[2];
2098         bool i2c_success = false;
2099         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2100
2101         memset(&buffer, 0, sizeof(buffer));
2102
2103         /* Program Slave Address for tuning single integrity */
2104         /* Write offset 0x0A to 0x13 */
2105         buffer[0] = 0x0A;
2106         buffer[1] = 0x13;
2107         i2c_success = i2c_write(pipe_ctx, slave_address,
2108                         buffer, sizeof(buffer));
2109         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2110                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2111                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2112         if (!i2c_success)
2113                 goto i2c_write_fail;
2114
2115         /* Write offset 0x0A to 0x17 */
2116         buffer[0] = 0x0A;
2117         buffer[1] = 0x17;
2118         i2c_success = i2c_write(pipe_ctx, slave_address,
2119                         buffer, sizeof(buffer));
2120         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2121                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2122                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2123         if (!i2c_success)
2124                 goto i2c_write_fail;
2125
2126         /* Write offset 0x0B to 0xDA or 0xD8 */
2127         buffer[0] = 0x0B;
2128         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2129         i2c_success = i2c_write(pipe_ctx, slave_address,
2130                         buffer, sizeof(buffer));
2131         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2132                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2133                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2134         if (!i2c_success)
2135                 goto i2c_write_fail;
2136
2137         /* Write offset 0x0A to 0x17 */
2138         buffer[0] = 0x0A;
2139         buffer[1] = 0x17;
2140         i2c_success = i2c_write(pipe_ctx, slave_address,
2141                         buffer, sizeof(buffer));
2142         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2143                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2144                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2145         if (!i2c_success)
2146                 goto i2c_write_fail;
2147
2148         /* Write offset 0x0C to 0x1D or 0x91 */
2149         buffer[0] = 0x0C;
2150         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2151         i2c_success = i2c_write(pipe_ctx, slave_address,
2152                         buffer, sizeof(buffer));
2153         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2154                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2155                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2156         if (!i2c_success)
2157                 goto i2c_write_fail;
2158
2159         /* Write offset 0x0A to 0x17 */
2160         buffer[0] = 0x0A;
2161         buffer[1] = 0x17;
2162         i2c_success = i2c_write(pipe_ctx, slave_address,
2163                         buffer, sizeof(buffer));
2164         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2165                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2166                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2167         if (!i2c_success)
2168                 goto i2c_write_fail;
2169
2170
2171         if (is_vga_mode) {
2172                 /* Program additional settings if using 640x480 resolution */
2173
2174                 /* Write offset 0xFF to 0x01 */
2175                 buffer[0] = 0xff;
2176                 buffer[1] = 0x01;
2177                 i2c_success = i2c_write(pipe_ctx, slave_address,
2178                                 buffer, sizeof(buffer));
2179                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2180                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2181                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2182                 if (!i2c_success)
2183                         goto i2c_write_fail;
2184
2185                 /* Write offset 0x00 to 0x23 */
2186                 buffer[0] = 0x00;
2187                 buffer[1] = 0x23;
2188                 i2c_success = i2c_write(pipe_ctx, slave_address,
2189                                 buffer, sizeof(buffer));
2190                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2191                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2192                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2193                 if (!i2c_success)
2194                         goto i2c_write_fail;
2195
2196                 /* Write offset 0xff to 0x00 */
2197                 buffer[0] = 0xff;
2198                 buffer[1] = 0x00;
2199                 i2c_success = i2c_write(pipe_ctx, slave_address,
2200                                 buffer, sizeof(buffer));
2201                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2202                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2203                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2204                 if (!i2c_success)
2205                         goto i2c_write_fail;
2206         }
2207
2208         return;
2209
2210 i2c_write_fail:
2211         DC_LOG_DEBUG("Set default retimer failed");
2212 }
2213
2214 static void write_i2c_redriver_setting(
2215                 struct pipe_ctx *pipe_ctx,
2216                 bool is_over_340mhz)
2217 {
2218         uint8_t slave_address = (0xF0 >> 1);
2219         uint8_t buffer[16];
2220         bool i2c_success = false;
2221         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2222
2223         memset(&buffer, 0, sizeof(buffer));
2224
2225         // Program Slave Address for tuning single integrity
2226         buffer[3] = 0x4E;
2227         buffer[4] = 0x4E;
2228         buffer[5] = 0x4E;
2229         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2230
2231         i2c_success = i2c_write(pipe_ctx, slave_address,
2232                                         buffer, sizeof(buffer));
2233         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2234                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2235                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2236                 i2c_success = %d\n",
2237                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2238
2239         if (!i2c_success)
2240                 DC_LOG_DEBUG("Set redriver failed");
2241 }
2242
2243 static void disable_link(struct dc_link *link, enum signal_type signal)
2244 {
2245         /*
2246          * TODO: implement call for dp_set_hw_test_pattern
2247          * it is needed for compliance testing
2248          */
2249
2250         /* Here we need to specify that encoder output settings
2251          * need to be calculated as for the set mode,
2252          * it will lead to querying dynamic link capabilities
2253          * which should be done before enable output
2254          */
2255
2256         if (dc_is_dp_signal(signal)) {
2257                 /* SST DP, eDP */
2258                 if (dc_is_dp_sst_signal(signal))
2259                         dp_disable_link_phy(link, signal);
2260                 else
2261                         dp_disable_link_phy_mst(link, signal);
2262
2263                 if (dc_is_dp_sst_signal(signal) ||
2264                                 link->mst_stream_alloc_table.stream_count == 0) {
2265                         dp_set_fec_enable(link, false);
2266                         dp_set_fec_ready(link, false);
2267                 }
2268         } else {
2269                 if (signal != SIGNAL_TYPE_VIRTUAL)
2270                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2271         }
2272
2273         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2274                 /* MST disable link only when no stream use the link */
2275                 if (link->mst_stream_alloc_table.stream_count <= 0)
2276                         link->link_status.link_active = false;
2277         } else {
2278                 link->link_status.link_active = false;
2279         }
2280 }
2281
2282 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2283 {
2284         struct dc_stream_state *stream = pipe_ctx->stream;
2285         struct dc_link *link = stream->link;
2286         enum dc_color_depth display_color_depth;
2287         enum engine_id eng_id;
2288         struct ext_hdmi_settings settings = {0};
2289         bool is_over_340mhz = false;
2290         bool is_vga_mode = (stream->timing.h_addressable == 640)
2291                         && (stream->timing.v_addressable == 480);
2292
2293         if (stream->phy_pix_clk == 0)
2294                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2295         if (stream->phy_pix_clk > 340000)
2296                 is_over_340mhz = true;
2297
2298         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2299                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2300                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2301                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2302                         /* DP159, Retimer settings */
2303                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2304
2305                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2306                                 write_i2c_retimer_setting(pipe_ctx,
2307                                                 is_vga_mode, is_over_340mhz, &settings);
2308                         } else {
2309                                 write_i2c_default_retimer_setting(pipe_ctx,
2310                                                 is_vga_mode, is_over_340mhz);
2311                         }
2312                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2313                         /* PI3EQX1204, Redriver settings */
2314                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2315                 }
2316         }
2317
2318         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2319                 dal_ddc_service_write_scdc_data(
2320                         stream->link->ddc,
2321                         stream->phy_pix_clk,
2322                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2323
2324         memset(&stream->link->cur_link_settings, 0,
2325                         sizeof(struct dc_link_settings));
2326
2327         display_color_depth = stream->timing.display_color_depth;
2328         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2329                 display_color_depth = COLOR_DEPTH_888;
2330
2331         link->link_enc->funcs->enable_tmds_output(
2332                         link->link_enc,
2333                         pipe_ctx->clock_source->id,
2334                         display_color_depth,
2335                         pipe_ctx->stream->signal,
2336                         stream->phy_pix_clk);
2337
2338         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2339                 dal_ddc_service_read_scdc_data(link->ddc);
2340 }
2341
2342 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2343 {
2344         struct dc_stream_state *stream = pipe_ctx->stream;
2345         struct dc_link *link = stream->link;
2346
2347         if (stream->phy_pix_clk == 0)
2348                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2349
2350         memset(&stream->link->cur_link_settings, 0,
2351                         sizeof(struct dc_link_settings));
2352
2353         link->link_enc->funcs->enable_lvds_output(
2354                         link->link_enc,
2355                         pipe_ctx->clock_source->id,
2356                         stream->phy_pix_clk);
2357
2358 }
2359
2360 /****************************enable_link***********************************/
2361 static enum dc_status enable_link(
2362                 struct dc_state *state,
2363                 struct pipe_ctx *pipe_ctx)
2364 {
2365         enum dc_status status = DC_ERROR_UNEXPECTED;
2366         struct dc_stream_state *stream = pipe_ctx->stream;
2367         struct dc_link *link = stream->link;
2368
2369         /* There's some scenarios where driver is unloaded with display
2370          * still enabled. When driver is reloaded, it may cause a display
2371          * to not light up if there is a mismatch between old and new
2372          * link settings. Need to call disable first before enabling at
2373          * new link settings.
2374          */
2375         if (link->link_status.link_active) {
2376                 disable_link(link, pipe_ctx->stream->signal);
2377         }
2378
2379         switch (pipe_ctx->stream->signal) {
2380         case SIGNAL_TYPE_DISPLAY_PORT:
2381                 status = enable_link_dp(state, pipe_ctx);
2382                 break;
2383         case SIGNAL_TYPE_EDP:
2384                 status = enable_link_edp(state, pipe_ctx);
2385                 break;
2386         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2387                 status = enable_link_dp_mst(state, pipe_ctx);
2388                 msleep(200);
2389                 break;
2390         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2391         case SIGNAL_TYPE_DVI_DUAL_LINK:
2392         case SIGNAL_TYPE_HDMI_TYPE_A:
2393                 enable_link_hdmi(pipe_ctx);
2394                 status = DC_OK;
2395                 break;
2396         case SIGNAL_TYPE_LVDS:
2397                 enable_link_lvds(pipe_ctx);
2398                 status = DC_OK;
2399                 break;
2400         case SIGNAL_TYPE_VIRTUAL:
2401                 status = DC_OK;
2402                 break;
2403         default:
2404                 break;
2405         }
2406
2407         if (status == DC_OK)
2408                 pipe_ctx->stream->link->link_status.link_active = true;
2409
2410         return status;
2411 }
2412
2413 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2414 {
2415
2416         uint32_t pxl_clk = timing->pix_clk_100hz;
2417
2418         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2419                 pxl_clk /= 2;
2420         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2421                 pxl_clk = pxl_clk * 2 / 3;
2422
2423         if (timing->display_color_depth == COLOR_DEPTH_101010)
2424                 pxl_clk = pxl_clk * 10 / 8;
2425         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2426                 pxl_clk = pxl_clk * 12 / 8;
2427
2428         return pxl_clk;
2429 }
2430
2431 static bool dp_active_dongle_validate_timing(
2432                 const struct dc_crtc_timing *timing,
2433                 const struct dpcd_caps *dpcd_caps)
2434 {
2435         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2436
2437         switch (dpcd_caps->dongle_type) {
2438         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2439         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2440         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2441                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2442                         return true;
2443                 else
2444                         return false;
2445         default:
2446                 break;
2447         }
2448
2449         if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2450                 dongle_caps->extendedCapValid == false)
2451                 return true;
2452
2453         /* Check Pixel Encoding */
2454         switch (timing->pixel_encoding) {
2455         case PIXEL_ENCODING_RGB:
2456         case PIXEL_ENCODING_YCBCR444:
2457                 break;
2458         case PIXEL_ENCODING_YCBCR422:
2459                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2460                         return false;
2461                 break;
2462         case PIXEL_ENCODING_YCBCR420:
2463                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2464                         return false;
2465                 break;
2466         default:
2467                 /* Invalid Pixel Encoding*/
2468                 return false;
2469         }
2470
2471         switch (timing->display_color_depth) {
2472         case COLOR_DEPTH_666:
2473         case COLOR_DEPTH_888:
2474                 /*888 and 666 should always be supported*/
2475                 break;
2476         case COLOR_DEPTH_101010:
2477                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2478                         return false;
2479                 break;
2480         case COLOR_DEPTH_121212:
2481                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2482                         return false;
2483                 break;
2484         case COLOR_DEPTH_141414:
2485         case COLOR_DEPTH_161616:
2486         default:
2487                 /* These color depths are currently not supported */
2488                 return false;
2489         }
2490
2491         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2492                 return false;
2493
2494         return true;
2495 }
2496
2497 enum dc_status dc_link_validate_mode_timing(
2498                 const struct dc_stream_state *stream,
2499                 struct dc_link *link,
2500                 const struct dc_crtc_timing *timing)
2501 {
2502         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2503         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2504
2505         /* A hack to avoid failing any modes for EDID override feature on
2506          * topology change such as lower quality cable for DP or different dongle
2507          */
2508         if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2509                 return DC_OK;
2510
2511         /* Passive Dongle */
2512         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2513                 return DC_EXCEED_DONGLE_CAP;
2514
2515         /* Active Dongle*/
2516         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2517                 return DC_EXCEED_DONGLE_CAP;
2518
2519         switch (stream->signal) {
2520         case SIGNAL_TYPE_EDP:
2521         case SIGNAL_TYPE_DISPLAY_PORT:
2522                 if (!dp_validate_mode_timing(
2523                                 link,
2524                                 timing))
2525                         return DC_NO_DP_LINK_BANDWIDTH;
2526                 break;
2527
2528         default:
2529                 break;
2530         }
2531
2532         return DC_OK;
2533 }
2534
2535 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2536 {
2537         int i;
2538         struct dc *dc = NULL;
2539         struct abm *abm = NULL;
2540
2541         if (!link || !link->ctx)
2542                 return NULL;
2543
2544         dc = link->ctx->dc;
2545
2546         for (i = 0; i < MAX_PIPES; i++) {
2547                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2548                 struct dc_stream_state *stream = pipe_ctx.stream;
2549
2550                 if (stream && stream->link == link) {
2551                         abm = pipe_ctx.stream_res.abm;
2552                         break;
2553                 }
2554         }
2555         return abm;
2556 }
2557
2558 int dc_link_get_backlight_level(const struct dc_link *link)
2559 {
2560
2561         struct abm *abm = get_abm_from_stream_res(link);
2562
2563         if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2564                 return DC_ERROR_UNEXPECTED;
2565
2566         return (int) abm->funcs->get_current_backlight(abm);
2567 }
2568
2569 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
2570 {
2571         struct abm *abm = get_abm_from_stream_res(link);
2572
2573         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
2574                 return DC_ERROR_UNEXPECTED;
2575
2576         return (int) abm->funcs->get_target_backlight(abm);
2577 }
2578
2579 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
2580 {
2581         int i;
2582         struct dc *dc = link->ctx->dc;
2583         struct pipe_ctx *pipe_ctx = NULL;
2584
2585         for (i = 0; i < MAX_PIPES; i++) {
2586                 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
2587                         if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
2588                                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2589                                 break;
2590                         }
2591                 }
2592         }
2593
2594         return pipe_ctx;
2595 }
2596
2597 bool dc_link_set_backlight_level(const struct dc_link *link,
2598                 uint32_t backlight_pwm_u16_16,
2599                 uint32_t frame_ramp)
2600 {
2601         struct dc  *dc = link->ctx->dc;
2602
2603         DC_LOGGER_INIT(link->ctx->logger);
2604         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2605                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2606
2607         if (dc_is_embedded_signal(link->connector_signal)) {
2608                 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
2609
2610                 if (pipe_ctx) {
2611                         /* Disable brightness ramping when the display is blanked
2612                          * as it can hang the DMCU
2613                          */
2614                         if (pipe_ctx->plane_state == NULL)
2615                                 frame_ramp = 0;
2616                 } else {
2617                         ASSERT(false);
2618                         return false;
2619                 }
2620
2621                 dc->hwss.set_backlight_level(
2622                                 pipe_ctx,
2623                                 backlight_pwm_u16_16,
2624                                 frame_ramp);
2625         }
2626         return true;
2627 }
2628
2629 bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
2630                 bool wait, bool force_static)
2631 {
2632         struct dc  *dc = link->ctx->dc;
2633         struct dmcu *dmcu = dc->res_pool->dmcu;
2634         struct dmub_psr *psr = dc->res_pool->psr;
2635
2636         if (psr == NULL && force_static)
2637                 return false;
2638
2639         link->psr_settings.psr_allow_active = allow_active;
2640
2641         if (psr != NULL && link->psr_settings.psr_feature_enabled) {
2642                 if (force_static && psr->funcs->psr_force_static)
2643                         psr->funcs->psr_force_static(psr);
2644                 psr->funcs->psr_enable(psr, allow_active, wait);
2645         } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
2646                 dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
2647         else
2648                 return false;
2649
2650         return true;
2651 }
2652
2653 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
2654 {
2655         struct dc  *dc = link->ctx->dc;
2656         struct dmcu *dmcu = dc->res_pool->dmcu;
2657         struct dmub_psr *psr = dc->res_pool->psr;
2658
2659         if (psr != NULL && link->psr_settings.psr_feature_enabled)
2660                 psr->funcs->psr_get_state(psr, state);
2661         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
2662                 dmcu->funcs->get_psr_state(dmcu, state);
2663
2664         return true;
2665 }
2666
2667 static inline enum physical_phy_id
2668 transmitter_to_phy_id(enum transmitter transmitter_value)
2669 {
2670         switch (transmitter_value) {
2671         case TRANSMITTER_UNIPHY_A:
2672                 return PHYLD_0;
2673         case TRANSMITTER_UNIPHY_B:
2674                 return PHYLD_1;
2675         case TRANSMITTER_UNIPHY_C:
2676                 return PHYLD_2;
2677         case TRANSMITTER_UNIPHY_D:
2678                 return PHYLD_3;
2679         case TRANSMITTER_UNIPHY_E:
2680                 return PHYLD_4;
2681         case TRANSMITTER_UNIPHY_F:
2682                 return PHYLD_5;
2683         case TRANSMITTER_NUTMEG_CRT:
2684                 return PHYLD_6;
2685         case TRANSMITTER_TRAVIS_CRT:
2686                 return PHYLD_7;
2687         case TRANSMITTER_TRAVIS_LCD:
2688                 return PHYLD_8;
2689         case TRANSMITTER_UNIPHY_G:
2690                 return PHYLD_9;
2691         case TRANSMITTER_COUNT:
2692                 return PHYLD_COUNT;
2693         case TRANSMITTER_UNKNOWN:
2694                 return PHYLD_UNKNOWN;
2695         default:
2696                 WARN_ONCE(1, "Unknown transmitter value %d\n",
2697                           transmitter_value);
2698                 return PHYLD_UNKNOWN;
2699         }
2700 }
2701
2702 bool dc_link_setup_psr(struct dc_link *link,
2703                 const struct dc_stream_state *stream, struct psr_config *psr_config,
2704                 struct psr_context *psr_context)
2705 {
2706         struct dc *dc;
2707         struct dmcu *dmcu;
2708         struct dmub_psr *psr;
2709         int i;
2710         /* updateSinkPsrDpcdConfig*/
2711         union dpcd_psr_configuration psr_configuration;
2712
2713         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
2714
2715         if (!link)
2716                 return false;
2717
2718         dc = link->ctx->dc;
2719         dmcu = dc->res_pool->dmcu;
2720         psr = dc->res_pool->psr;
2721
2722         if (!dmcu && !psr)
2723                 return false;
2724
2725
2726         memset(&psr_configuration, 0, sizeof(psr_configuration));
2727
2728         psr_configuration.bits.ENABLE                    = 1;
2729         psr_configuration.bits.CRC_VERIFICATION          = 1;
2730         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
2731                         psr_config->psr_frame_capture_indication_req;
2732
2733         /* Check for PSR v2*/
2734         if (psr_config->psr_version == 0x2) {
2735                 /* For PSR v2 selective update.
2736                  * Indicates whether sink should start capturing
2737                  * immediately following active scan line,
2738                  * or starting with the 2nd active scan line.
2739                  */
2740                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
2741                 /*For PSR v2, determines whether Sink should generate
2742                  * IRQ_HPD when CRC mismatch is detected.
2743                  */
2744                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
2745         }
2746
2747         dm_helpers_dp_write_dpcd(
2748                 link->ctx,
2749                 link,
2750                 368,
2751                 &psr_configuration.raw,
2752                 sizeof(psr_configuration.raw));
2753
2754         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
2755         psr_context->transmitterId = link->link_enc->transmitter;
2756         psr_context->engineId = link->link_enc->preferred_engine;
2757
2758         for (i = 0; i < MAX_PIPES; i++) {
2759                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
2760                                 == stream) {
2761                         /* dmcu -1 for all controller id values,
2762                          * therefore +1 here
2763                          */
2764                         psr_context->controllerId =
2765                                 dc->current_state->res_ctx.
2766                                 pipe_ctx[i].stream_res.tg->inst + 1;
2767                         break;
2768                 }
2769         }
2770
2771         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
2772         psr_context->phyType = PHY_TYPE_UNIPHY;
2773         /*PhyId is associated with the transmitter id*/
2774         psr_context->smuPhyId =
2775                 transmitter_to_phy_id(link->link_enc->transmitter);
2776
2777         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
2778         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
2779                                         timing.pix_clk_100hz * 100),
2780                                         stream->timing.v_total),
2781                                         stream->timing.h_total);
2782
2783         psr_context->psrSupportedDisplayConfig = true;
2784         psr_context->psrExitLinkTrainingRequired =
2785                 psr_config->psr_exit_link_training_required;
2786         psr_context->sdpTransmitLineNumDeadline =
2787                 psr_config->psr_sdp_transmit_line_num_deadline;
2788         psr_context->psrFrameCaptureIndicationReq =
2789                 psr_config->psr_frame_capture_indication_req;
2790
2791         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
2792
2793         psr_context->numberOfControllers =
2794                         link->dc->res_pool->timing_generator_count;
2795
2796         psr_context->rfb_update_auto_en = true;
2797
2798         /* 2 frames before enter PSR. */
2799         psr_context->timehyst_frames = 2;
2800         /* half a frame
2801          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
2802          */
2803         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
2804         psr_context->aux_repeats = 10;
2805
2806         psr_context->psr_level.u32all = 0;
2807
2808 #if defined(CONFIG_DRM_AMD_DC_DCN)
2809         /*skip power down the single pipe since it blocks the cstate*/
2810         if ((link->ctx->asic_id.chip_family == FAMILY_RV) &&
2811              ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
2812                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
2813 #endif
2814
2815         /* SMU will perform additional powerdown sequence.
2816          * For unsupported ASICs, set psr_level flag to skip PSR
2817          *  static screen notification to SMU.
2818          *  (Always set for DAL2, did not check ASIC)
2819          */
2820         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
2821         psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
2822
2823         /* Complete PSR entry before aborting to prevent intermittent
2824          * freezes on certain eDPs
2825          */
2826         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
2827
2828         /* Controls additional delay after remote frame capture before
2829          * continuing power down, default = 0
2830          */
2831         psr_context->frame_delay = 0;
2832
2833         if (psr)
2834                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context);
2835         else
2836                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
2837
2838         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
2839          * should not happen since firmware should be running at this point
2840          */
2841         if (link->psr_settings.psr_feature_enabled == 0)
2842                 ASSERT(0);
2843
2844         return true;
2845
2846 }
2847
2848 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
2849 {
2850         struct dc  *dc = link->ctx->dc;
2851         struct dmub_psr *psr = dc->res_pool->psr;
2852
2853         // PSR residency measurements only supported on DMCUB
2854         if (psr != NULL && link->psr_settings.psr_feature_enabled)
2855                 psr->funcs->psr_get_residency(psr, residency);
2856         else
2857                 *residency = 0;
2858 }
2859
2860 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2861 {
2862         return &link->link_status;
2863 }
2864
2865 void core_link_resume(struct dc_link *link)
2866 {
2867         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2868                 program_hpd_filter(link);
2869 }
2870
2871 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2872 {
2873         struct fixed31_32 mbytes_per_sec;
2874         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
2875                         &stream->link->cur_link_settings);
2876         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
2877
2878         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2879
2880         return dc_fixpt_div_int(mbytes_per_sec, 54);
2881 }
2882
2883 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
2884 {
2885         struct fixed31_32 peak_kbps;
2886         uint32_t numerator;
2887         uint32_t denominator;
2888
2889         /*
2890          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2891          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2892          * common multiplier to render an integer PBN for all link rate/lane
2893          * counts combinations
2894          * calculate
2895          * peak_kbps *= (1006/1000)
2896          * peak_kbps *= (64/54)
2897          * peak_kbps *= 8    convert to bytes
2898          */
2899
2900         numerator = 64 * PEAK_FACTOR_X1000;
2901         denominator = 54 * 8 * 1000 * 1000;
2902         kbps *= numerator;
2903         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2904
2905         return peak_kbps;
2906 }
2907
2908 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2909 {
2910         uint64_t kbps;
2911
2912         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2913         return get_pbn_from_bw_in_kbps(kbps);
2914 }
2915
2916 static void update_mst_stream_alloc_table(
2917         struct dc_link *link,
2918         struct stream_encoder *stream_enc,
2919         const struct dp_mst_stream_allocation_table *proposed_table)
2920 {
2921         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2922                         { 0 } };
2923         struct link_mst_stream_allocation *dc_alloc;
2924
2925         int i;
2926         int j;
2927
2928         /* if DRM proposed_table has more than one new payload */
2929         ASSERT(proposed_table->stream_count -
2930                         link->mst_stream_alloc_table.stream_count < 2);
2931
2932         /* copy proposed_table to link, add stream encoder */
2933         for (i = 0; i < proposed_table->stream_count; i++) {
2934
2935                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2936                         dc_alloc =
2937                         &link->mst_stream_alloc_table.stream_allocations[j];
2938
2939                         if (dc_alloc->vcp_id ==
2940                                 proposed_table->stream_allocations[i].vcp_id) {
2941
2942                                 work_table[i] = *dc_alloc;
2943                                 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
2944                                 break; /* exit j loop */
2945                         }
2946                 }
2947
2948                 /* new vcp_id */
2949                 if (j == link->mst_stream_alloc_table.stream_count) {
2950                         work_table[i].vcp_id =
2951                                 proposed_table->stream_allocations[i].vcp_id;
2952                         work_table[i].slot_count =
2953                                 proposed_table->stream_allocations[i].slot_count;
2954                         work_table[i].stream_enc = stream_enc;
2955                 }
2956         }
2957
2958         /* update link->mst_stream_alloc_table with work_table */
2959         link->mst_stream_alloc_table.stream_count =
2960                         proposed_table->stream_count;
2961         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2962                 link->mst_stream_alloc_table.stream_allocations[i] =
2963                                 work_table[i];
2964 }
2965
2966 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2967  * because stream_encoder is not exposed to dm
2968  */
2969 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2970 {
2971         struct dc_stream_state *stream = pipe_ctx->stream;
2972         struct dc_link *link = stream->link;
2973         struct link_encoder *link_encoder = link->link_enc;
2974         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2975         struct dp_mst_stream_allocation_table proposed_table = {0};
2976         struct fixed31_32 avg_time_slots_per_mtp;
2977         struct fixed31_32 pbn;
2978         struct fixed31_32 pbn_per_slot;
2979         uint8_t i;
2980         enum act_return_status ret;
2981         DC_LOGGER_INIT(link->ctx->logger);
2982
2983         /* enable_link_dp_mst already check link->enabled_stream_count
2984          * and stream is in link->stream[]. This is called during set mode,
2985          * stream_enc is available.
2986          */
2987
2988         /* get calculate VC payload for stream: stream_alloc */
2989         if (dm_helpers_dp_mst_write_payload_allocation_table(
2990                 stream->ctx,
2991                 stream,
2992                 &proposed_table,
2993                 true)) {
2994                 update_mst_stream_alloc_table(
2995                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2996         }
2997         else
2998                 DC_LOG_WARNING("Failed to update"
2999                                 "MST allocation table for"
3000                                 "pipe idx:%d\n",
3001                                 pipe_ctx->pipe_idx);
3002
3003         DC_LOG_MST("%s  "
3004                         "stream_count: %d: \n ",
3005                         __func__,
3006                         link->mst_stream_alloc_table.stream_count);
3007
3008         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3009                 DC_LOG_MST("stream_enc[%d]: %p      "
3010                 "stream[%d].vcp_id: %d      "
3011                 "stream[%d].slot_count: %d\n",
3012                 i,
3013                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3014                 i,
3015                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3016                 i,
3017                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3018         }
3019
3020         ASSERT(proposed_table.stream_count > 0);
3021
3022         /* program DP source TX for payload */
3023         link_encoder->funcs->update_mst_stream_allocation_table(
3024                 link_encoder,
3025                 &link->mst_stream_alloc_table);
3026
3027         /* send down message */
3028         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3029                         stream->ctx,
3030                         stream);
3031
3032         if (ret != ACT_LINK_LOST) {
3033                 dm_helpers_dp_mst_send_payload_allocation(
3034                                 stream->ctx,
3035                                 stream,
3036                                 true);
3037         }
3038
3039         /* slot X.Y for only current stream */
3040         pbn_per_slot = get_pbn_per_slot(stream);
3041         if (pbn_per_slot.value == 0) {
3042                 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3043                 return DC_UNSUPPORTED_VALUE;
3044         }
3045         pbn = get_pbn_from_timing(pipe_ctx);
3046         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3047
3048         stream_encoder->funcs->set_throttled_vcp_size(
3049                 stream_encoder,
3050                 avg_time_slots_per_mtp);
3051
3052         return DC_OK;
3053
3054 }
3055
3056 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3057 {
3058         struct dc_stream_state *stream = pipe_ctx->stream;
3059         struct dc_link *link = stream->link;
3060         struct link_encoder *link_encoder = link->link_enc;
3061         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3062         struct dp_mst_stream_allocation_table proposed_table = {0};
3063         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3064         uint8_t i;
3065         bool mst_mode = (link->type == dc_connection_mst_branch);
3066         DC_LOGGER_INIT(link->ctx->logger);
3067
3068         /* deallocate_mst_payload is called before disable link. When mode or
3069          * disable/enable monitor, new stream is created which is not in link
3070          * stream[] yet. For this, payload is not allocated yet, so de-alloc
3071          * should not done. For new mode set, map_resources will get engine
3072          * for new stream, so stream_enc->id should be validated until here.
3073          */
3074
3075         /* slot X.Y */
3076         stream_encoder->funcs->set_throttled_vcp_size(
3077                 stream_encoder,
3078                 avg_time_slots_per_mtp);
3079
3080         /* TODO: which component is responsible for remove payload table? */
3081         if (mst_mode) {
3082                 if (dm_helpers_dp_mst_write_payload_allocation_table(
3083                                 stream->ctx,
3084                                 stream,
3085                                 &proposed_table,
3086                                 false)) {
3087
3088                         update_mst_stream_alloc_table(
3089                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3090                 }
3091                 else {
3092                                 DC_LOG_WARNING("Failed to update"
3093                                                 "MST allocation table for"
3094                                                 "pipe idx:%d\n",
3095                                                 pipe_ctx->pipe_idx);
3096                 }
3097         }
3098
3099         DC_LOG_MST("%s"
3100                         "stream_count: %d: ",
3101                         __func__,
3102                         link->mst_stream_alloc_table.stream_count);
3103
3104         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3105                 DC_LOG_MST("stream_enc[%d]: %p      "
3106                 "stream[%d].vcp_id: %d      "
3107                 "stream[%d].slot_count: %d\n",
3108                 i,
3109                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3110                 i,
3111                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3112                 i,
3113                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3114         }
3115
3116         link_encoder->funcs->update_mst_stream_allocation_table(
3117                 link_encoder,
3118                 &link->mst_stream_alloc_table);
3119
3120         if (mst_mode) {
3121                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3122                         stream->ctx,
3123                         stream);
3124
3125                 dm_helpers_dp_mst_send_payload_allocation(
3126                         stream->ctx,
3127                         stream,
3128                         false);
3129         }
3130
3131         return DC_OK;
3132 }
3133
3134 enum dc_status dc_link_reallocate_mst_payload(struct dc_link *link)
3135 {
3136         int i;
3137         struct pipe_ctx *pipe_ctx;
3138
3139         // Clear all of MST payload then reallocate
3140         for (i = 0; i < MAX_PIPES; i++) {
3141                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3142
3143                 /* driver enable split pipe for external monitors
3144                  * we have to check pipe_ctx is split pipe or not
3145                  * If it's split pipe, driver using top pipe to
3146                  * reaallocate.
3147                  */
3148                 if (!pipe_ctx || pipe_ctx->top_pipe)
3149                         continue;
3150
3151                 if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
3152                                 pipe_ctx->stream->dpms_off == false &&
3153                                 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3154                         deallocate_mst_payload(pipe_ctx);
3155                 }
3156         }
3157
3158         for (i = 0; i < MAX_PIPES; i++) {
3159                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3160
3161                 if (!pipe_ctx || pipe_ctx->top_pipe)
3162                         continue;
3163
3164                 if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
3165                                 pipe_ctx->stream->dpms_off == false &&
3166                                 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3167                         /* enable/disable PHY will clear connection between BE and FE
3168                          * need to restore it.
3169                          */
3170                         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
3171                                                                         pipe_ctx->stream_res.stream_enc->id, true);
3172                         dc_link_allocate_mst_payload(pipe_ctx);
3173                 }
3174         }
3175
3176         return DC_OK;
3177 }
3178
3179 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3180 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3181 {
3182         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3183         if (cp_psp && cp_psp->funcs.update_stream_config) {
3184                 struct cp_psp_stream_config config = {0};
3185                 enum dp_panel_mode panel_mode =
3186                                 dp_get_panel_mode(pipe_ctx->stream->link);
3187
3188                 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3189                 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3190                 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
3191                 config.dpms_off = dpms_off;
3192                 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
3193                 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
3194                 config.mst_enabled = (pipe_ctx->stream->signal ==
3195                                 SIGNAL_TYPE_DISPLAY_PORT_MST);
3196                 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
3197         }
3198 }
3199 #endif
3200
3201 void core_link_enable_stream(
3202                 struct dc_state *state,
3203                 struct pipe_ctx *pipe_ctx)
3204 {
3205         struct dc *dc = pipe_ctx->stream->ctx->dc;
3206         struct dc_stream_state *stream = pipe_ctx->stream;
3207         enum dc_status status;
3208 #if defined(CONFIG_DRM_AMD_DC_DCN)
3209         enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
3210 #endif
3211         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
3212
3213         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3214                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3215                 return;
3216
3217         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3218                 stream->link->link_enc->funcs->setup(
3219                         stream->link->link_enc,
3220                         pipe_ctx->stream->signal);
3221                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
3222                         pipe_ctx->stream_res.stream_enc,
3223                         pipe_ctx->stream_res.tg->inst,
3224                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
3225         }
3226
3227         if (dc_is_dp_signal(pipe_ctx->stream->signal))
3228                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
3229                         pipe_ctx->stream_res.stream_enc,
3230                         &stream->timing,
3231                         stream->output_color_space,
3232                         stream->use_vsc_sdp_for_colorimetry,
3233                         stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
3234
3235         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
3236                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
3237                         pipe_ctx->stream_res.stream_enc,
3238                         &stream->timing,
3239                         stream->phy_pix_clk,
3240                         pipe_ctx->stream_res.audio != NULL);
3241
3242         pipe_ctx->stream->link->link_state_valid = true;
3243
3244 #if defined(CONFIG_DRM_AMD_DC_DCN)
3245         if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
3246                 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
3247 #endif
3248
3249         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
3250                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
3251                         pipe_ctx->stream_res.stream_enc,
3252                         &stream->timing,
3253                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
3254                         true : false);
3255
3256         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
3257                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
3258                         pipe_ctx->stream_res.stream_enc,
3259                         &stream->timing);
3260
3261         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
3262                 bool apply_edp_fast_boot_optimization =
3263                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
3264
3265                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
3266
3267                 resource_build_info_frame(pipe_ctx);
3268                 dc->hwss.update_info_frame(pipe_ctx);
3269
3270                 /* Do not touch link on seamless boot optimization. */
3271                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
3272                         pipe_ctx->stream->dpms_off = false;
3273
3274                         /* Still enable stream features & audio on seamless boot for DP external displays */
3275                         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
3276                                 enable_stream_features(pipe_ctx);
3277                                 if (pipe_ctx->stream_res.audio != NULL) {
3278                                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
3279                                         dc->hwss.enable_audio_stream(pipe_ctx);
3280                                 }
3281                         }
3282
3283 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3284                         update_psp_stream_config(pipe_ctx, false);
3285 #endif
3286                         return;
3287                 }
3288
3289                 /* eDP lit up by bios already, no need to enable again. */
3290                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
3291                                         apply_edp_fast_boot_optimization) {
3292                         pipe_ctx->stream->dpms_off = false;
3293 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3294                         update_psp_stream_config(pipe_ctx, false);
3295 #endif
3296                         return;
3297                 }
3298
3299                 if (pipe_ctx->stream->dpms_off)
3300                         return;
3301
3302                 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
3303                  * link training). This is to make sure the bandwidth sent to DIG BE won't be
3304                  * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
3305                  * will be automatically set at a later time when the video is enabled
3306                  * (DP_VID_STREAM_EN = 1).
3307                  */
3308                 if (pipe_ctx->stream->timing.flags.DSC) {
3309                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3310                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3311                                 dp_set_dsc_enable(pipe_ctx, true);
3312                 }
3313
3314                 status = enable_link(state, pipe_ctx);
3315
3316                 if (status != DC_OK) {
3317                         DC_LOG_WARNING("enabling link %u failed: %d\n",
3318                         pipe_ctx->stream->link->link_index,
3319                         status);
3320
3321                         /* Abort stream enable *unless* the failure was due to
3322                          * DP link training - some DP monitors will recover and
3323                          * show the stream anyway. But MST displays can't proceed
3324                          * without link training.
3325                          */
3326                         if (status != DC_FAIL_DP_LINK_TRAINING ||
3327                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3328                                 BREAK_TO_DEBUGGER();
3329                                 return;
3330                         }
3331                 }
3332
3333                 /* turn off otg test pattern if enable */
3334                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3335                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3336                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3337                                         COLOR_DEPTH_UNDEFINED);
3338
3339                 /* This second call is needed to reconfigure the DIG
3340                  * as a workaround for the incorrect value being applied
3341                  * from transmitter control.
3342                  */
3343                 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
3344                         stream->link->link_enc->funcs->setup(
3345                                 stream->link->link_enc,
3346                                 pipe_ctx->stream->signal);
3347
3348                 dc->hwss.enable_stream(pipe_ctx);
3349
3350                 /* Set DPS PPS SDP (AKA "info frames") */
3351                 if (pipe_ctx->stream->timing.flags.DSC) {
3352                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3353                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3354                                 dp_set_dsc_pps_sdp(pipe_ctx, true);
3355                 }
3356
3357                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3358                         dc_link_allocate_mst_payload(pipe_ctx);
3359
3360                 dc->hwss.unblank_stream(pipe_ctx,
3361                         &pipe_ctx->stream->link->cur_link_settings);
3362
3363                 if (stream->sink_patches.delay_ignore_msa > 0)
3364                         msleep(stream->sink_patches.delay_ignore_msa);
3365
3366                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3367                         enable_stream_features(pipe_ctx);
3368 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3369                 update_psp_stream_config(pipe_ctx, false);
3370 #endif
3371
3372                 dc->hwss.enable_audio_stream(pipe_ctx);
3373
3374         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
3375                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3376                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
3377                         dp_set_dsc_enable(pipe_ctx, true);
3378
3379         }
3380
3381         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3382                 core_link_set_avmute(pipe_ctx, false);
3383         }
3384 }
3385
3386 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
3387 {
3388         struct dc  *dc = pipe_ctx->stream->ctx->dc;
3389         struct dc_stream_state *stream = pipe_ctx->stream;
3390         struct dc_link *link = stream->sink->link;
3391
3392         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3393                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3394                 return;
3395
3396         if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
3397                 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
3398                         core_link_set_avmute(pipe_ctx, true);
3399         }
3400
3401         dc->hwss.disable_audio_stream(pipe_ctx);
3402
3403 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3404         update_psp_stream_config(pipe_ctx, true);
3405 #endif
3406         dc->hwss.blank_stream(pipe_ctx);
3407
3408         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3409                 deallocate_mst_payload(pipe_ctx);
3410
3411         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
3412                 struct ext_hdmi_settings settings = {0};
3413                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
3414
3415                 unsigned short masked_chip_caps = link->chip_caps &
3416                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
3417                 //Need to inform that sink is going to use legacy HDMI mode.
3418                 dal_ddc_service_write_scdc_data(
3419                         link->ddc,
3420                         165000,//vbios only handles 165Mhz.
3421                         false);
3422                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
3423                         /* DP159, Retimer settings */
3424                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
3425                                 write_i2c_retimer_setting(pipe_ctx,
3426                                                 false, false, &settings);
3427                         else
3428                                 write_i2c_default_retimer_setting(pipe_ctx,
3429                                                 false, false);
3430                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
3431                         /* PI3EQX1204, Redriver settings */
3432                         write_i2c_redriver_setting(pipe_ctx, false);
3433                 }
3434         }
3435
3436         disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
3437
3438         dc->hwss.disable_stream(pipe_ctx);
3439
3440         if (pipe_ctx->stream->timing.flags.DSC) {
3441                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3442                         dp_set_dsc_enable(pipe_ctx, false);
3443         }
3444 }
3445
3446 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
3447 {
3448         struct dc  *dc = pipe_ctx->stream->ctx->dc;
3449
3450         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
3451                 return;
3452
3453         dc->hwss.set_avmute(pipe_ctx, enable);
3454 }
3455
3456 /**
3457  *  dc_link_enable_hpd_filter:
3458  *     If enable is true, programs HPD filter on associated HPD line using
3459  *     delay_on_disconnect/delay_on_connect values dependent on
3460  *     link->connector_signal
3461  *
3462  *     If enable is false, programs HPD filter on associated HPD line with no
3463  *     delays on connect or disconnect
3464  *
3465  *  @link:   pointer to the dc link
3466  *  @enable: boolean specifying whether to enable hbd
3467  */
3468 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
3469 {
3470         struct gpio *hpd;
3471
3472         if (enable) {
3473                 link->is_hpd_filter_disabled = false;
3474                 program_hpd_filter(link);
3475         } else {
3476                 link->is_hpd_filter_disabled = true;
3477                 /* Obtain HPD handle */
3478                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
3479
3480                 if (!hpd)
3481                         return;
3482
3483                 /* Setup HPD filtering */
3484                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
3485                         struct gpio_hpd_config config;
3486
3487                         config.delay_on_connect = 0;
3488                         config.delay_on_disconnect = 0;
3489
3490                         dal_irq_setup_hpd_filter(hpd, &config);
3491
3492                         dal_gpio_close(hpd);
3493                 } else {
3494                         ASSERT_CRITICAL(false);
3495                 }
3496                 /* Release HPD handle */
3497                 dal_gpio_destroy_irq(&hpd);
3498         }
3499 }
3500
3501 uint32_t dc_bandwidth_in_kbps_from_timing(
3502         const struct dc_crtc_timing *timing)
3503 {
3504         uint32_t bits_per_channel = 0;
3505         uint32_t kbps;
3506         struct fixed31_32 link_bw_kbps;
3507
3508         if (timing->flags.DSC) {
3509                 link_bw_kbps = dc_fixpt_from_int(timing->pix_clk_100hz);
3510                 link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160);
3511                 link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps, timing->dsc_cfg.bits_per_pixel);
3512                 kbps = dc_fixpt_ceil(link_bw_kbps);
3513                 return kbps;
3514         }
3515
3516         switch (timing->display_color_depth) {
3517         case COLOR_DEPTH_666:
3518                 bits_per_channel = 6;
3519                 break;
3520         case COLOR_DEPTH_888:
3521                 bits_per_channel = 8;
3522                 break;
3523         case COLOR_DEPTH_101010:
3524                 bits_per_channel = 10;
3525                 break;
3526         case COLOR_DEPTH_121212:
3527                 bits_per_channel = 12;
3528                 break;
3529         case COLOR_DEPTH_141414:
3530                 bits_per_channel = 14;
3531                 break;
3532         case COLOR_DEPTH_161616:
3533                 bits_per_channel = 16;
3534                 break;
3535         default:
3536                 ASSERT(bits_per_channel != 0);
3537                 bits_per_channel = 8;
3538                 break;
3539         }
3540
3541         kbps = timing->pix_clk_100hz / 10;
3542         kbps *= bits_per_channel;
3543
3544         if (timing->flags.Y_ONLY != 1) {
3545                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
3546                 kbps *= 3;
3547                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3548                         kbps /= 2;
3549                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
3550                         kbps = kbps * 2 / 3;
3551         }
3552
3553         return kbps;
3554
3555 }
3556
3557 void dc_link_set_drive_settings(struct dc *dc,
3558                                 struct link_training_settings *lt_settings,
3559                                 const struct dc_link *link)
3560 {
3561
3562         int i;
3563
3564         for (i = 0; i < dc->link_count; i++) {
3565                 if (dc->links[i] == link)
3566                         break;
3567         }
3568
3569         if (i >= dc->link_count)
3570                 ASSERT_CRITICAL(false);
3571
3572         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
3573 }
3574
3575 void dc_link_perform_link_training(struct dc *dc,
3576                                    struct dc_link_settings *link_setting,
3577                                    bool skip_video_pattern)
3578 {
3579         int i;
3580
3581         for (i = 0; i < dc->link_count; i++)
3582                 dc_link_dp_perform_link_training(
3583                         dc->links[i],
3584                         link_setting,
3585                         skip_video_pattern);
3586 }
3587
3588 void dc_link_set_preferred_link_settings(struct dc *dc,
3589                                          struct dc_link_settings *link_setting,
3590                                          struct dc_link *link)
3591 {
3592         int i;
3593         struct pipe_ctx *pipe;
3594         struct dc_stream_state *link_stream;
3595         struct dc_link_settings store_settings = *link_setting;
3596
3597         link->preferred_link_setting = store_settings;
3598
3599         /* Retrain with preferred link settings only relevant for
3600          * DP signal type
3601          * Check for non-DP signal or if passive dongle present
3602          */
3603         if (!dc_is_dp_signal(link->connector_signal) ||
3604                 link->dongle_max_pix_clk > 0)
3605                 return;
3606
3607         for (i = 0; i < MAX_PIPES; i++) {
3608                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3609                 if (pipe->stream && pipe->stream->link) {
3610                         if (pipe->stream->link == link) {
3611                                 link_stream = pipe->stream;
3612                                 break;
3613                         }
3614                 }
3615         }
3616
3617         /* Stream not found */
3618         if (i == MAX_PIPES)
3619                 return;
3620
3621         /* Cannot retrain link if backend is off */
3622         if (link_stream->dpms_off)
3623                 return;
3624
3625         decide_link_settings(link_stream, &store_settings);
3626
3627         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3628                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
3629                 dp_retrain_link_dp_test(link, &store_settings, false);
3630 }
3631
3632 void dc_link_set_preferred_training_settings(struct dc *dc,
3633                                                  struct dc_link_settings *link_setting,
3634                                                  struct dc_link_training_overrides *lt_overrides,
3635                                                  struct dc_link *link,
3636                                                  bool skip_immediate_retrain)
3637 {
3638         if (lt_overrides != NULL)
3639                 link->preferred_training_settings = *lt_overrides;
3640         else
3641                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
3642
3643         if (link_setting != NULL) {
3644                 link->preferred_link_setting = *link_setting;
3645         } else {
3646                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3647                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3648         }
3649
3650         /* Retrain now, or wait until next stream update to apply */
3651         if (skip_immediate_retrain == false)
3652                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
3653 }
3654
3655 void dc_link_enable_hpd(const struct dc_link *link)
3656 {
3657         dc_link_dp_enable_hpd(link);
3658 }
3659
3660 void dc_link_disable_hpd(const struct dc_link *link)
3661 {
3662         dc_link_dp_disable_hpd(link);
3663 }
3664
3665 void dc_link_set_test_pattern(struct dc_link *link,
3666                               enum dp_test_pattern test_pattern,
3667                               enum dp_test_pattern_color_space test_pattern_color_space,
3668                               const struct link_training_settings *p_link_settings,
3669                               const unsigned char *p_custom_pattern,
3670                               unsigned int cust_pattern_size)
3671 {
3672         if (link != NULL)
3673                 dc_link_dp_set_test_pattern(
3674                         link,
3675                         test_pattern,
3676                         test_pattern_color_space,
3677                         p_link_settings,
3678                         p_custom_pattern,
3679                         cust_pattern_size);
3680 }
3681
3682 uint32_t dc_link_bandwidth_kbps(
3683         const struct dc_link *link,
3684         const struct dc_link_settings *link_setting)
3685 {
3686         uint32_t link_bw_kbps =
3687                 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
3688
3689         link_bw_kbps *= 8;   /* 8 bits per byte*/
3690         link_bw_kbps *= link_setting->lane_count;
3691
3692         if (dc_link_should_enable_fec(link)) {
3693                 /* Account for FEC overhead.
3694                  * We have to do it based on caps,
3695                  * and not based on FEC being set ready,
3696                  * because FEC is set ready too late in
3697                  * the process to correctly be picked up
3698                  * by mode enumeration.
3699                  *
3700                  * There's enough zeros at the end of 'kbps'
3701                  * that make the below operation 100% precise
3702                  * for our purposes.
3703                  * 'long long' makes it work even for HDMI 2.1
3704                  * max bandwidth (and much, much bigger bandwidths
3705                  * than that, actually).
3706                  *
3707                  * NOTE: Reducing link BW by 3% may not be precise
3708                  * because it may be a stream BT that increases by 3%, and so
3709                  * 1/1.03 = 0.970873 factor should have been used instead,
3710                  * but the difference is minimal and is in a safe direction,
3711                  * which all works well around potential ambiguity of DP 1.4a spec.
3712                  */
3713                 long long fec_link_bw_kbps = link_bw_kbps * 970LL;
3714                 link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL));
3715         }
3716
3717         return link_bw_kbps;
3718
3719 }
3720
3721 const struct dc_link_settings *dc_link_get_link_cap(
3722                 const struct dc_link *link)
3723 {
3724         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
3725                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
3726                 return &link->preferred_link_setting;
3727         return &link->verified_link_cap;
3728 }
3729
3730 void dc_link_overwrite_extended_receiver_cap(
3731                 struct dc_link *link)
3732 {
3733         dp_overwrite_extended_receiver_cap(link);
3734 }
3735
3736 bool dc_link_is_fec_supported(const struct dc_link *link)
3737 {
3738         return (dc_is_dp_signal(link->connector_signal) &&
3739                         link->link_enc->features.fec_supported &&
3740                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
3741                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
3742 }
3743
3744 bool dc_link_should_enable_fec(const struct dc_link *link)
3745 {
3746         bool is_fec_disable = false;
3747         bool ret = false;
3748
3749         if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
3750                         link->local_sink &&
3751                         link->local_sink->edid_caps.panel_patch.disable_fec) ||
3752                         link->connector_signal == SIGNAL_TYPE_EDP) // Disable FEC for eDP
3753                 is_fec_disable = true;
3754
3755         if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
3756                 ret = true;
3757
3758         return ret;
3759 }