drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atomfirmware.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_dpia.h"
  37 #include "dc_link_ddc.h"
  38 #include "link_hwss.h"
  39 #include "opp.h"
  40
  41 #include "link_encoder.h"
  42 #include "hw_sequencer.h"
  43 #include "resource.h"
  44 #include "abm.h"
  45 #include "fixed31_32.h"
  46 #include "dpcd_defs.h"
  47 #include "dmcu.h"
  48 #include "hw/clk_mgr.h"
  49 #include "dce/dmub_psr.h"
  50 #include "dmub/dmub_srv.h"
  51 #include "inc/hw/panel_cntl.h"
  52 #include "inc/link_enc_cfg.h"
  53 #include "inc/link_dpcd.h"
  54 #include "link/link_dp_trace.h"
  55
  56 #include "dc/dcn30/dcn30_vpg.h"
  57
  58 #define DC_LOGGER_INIT(logger)
  59
  60 #define LINK_INFO(...) \
  61         DC_LOG_HW_HOTPLUG(  \
  62                 __VA_ARGS__)
  63
  64 #define RETIMER_REDRIVER_INFO(...) \
  65         DC_LOG_RETIMER_REDRIVER(  \
  66                 __VA_ARGS__)
  67
  68 /*******************************************************************************
  69  * Private functions
  70  ******************************************************************************/
  71 static void dc_link_destruct(struct dc_link *link)
  72 {
  73         int i;
  74
  75         if (link->hpd_gpio) {
  76                 dal_gpio_destroy_irq(&link->hpd_gpio);
  77                 link->hpd_gpio = NULL;
  78         }
  79
  80         if (link->ddc)
  81                 dal_ddc_service_destroy(&link->ddc);
  82
  83         if (link->panel_cntl)
  84                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
  85
  86         if (link->link_enc) {
  87                 /* Update link encoder resource tracking variables. These are used for
  88                  * the dynamic assignment of link encoders to streams. Virtual links
  89                  * are not assigned encoder resources on creation.
  90                  */
  91                 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
  92                         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
  93                         link->dc->res_pool->dig_link_enc_count--;
  94                 }
  95                 link->link_enc->funcs->destroy(&link->link_enc);
  96         }
  97
  98         if (link->local_sink)
  99                 dc_sink_release(link->local_sink);
 100
 101         for (i = 0; i < link->sink_count; ++i)
 102                 dc_sink_release(link->remote_sinks[i]);
 103 }
 104
 105 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 106                           struct graphics_object_id link_id,
 107                           struct gpio_service *gpio_service)
 108 {
 109         enum bp_result bp_result;
 110         struct graphics_object_hpd_info hpd_info;
 111         struct gpio_pin_info pin_info;
 112
 113         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 114                 return NULL;
 115
 116         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 117                 hpd_info.hpd_int_gpio_uid, &pin_info);
 118
 119         if (bp_result != BP_RESULT_OK) {
 120                 ASSERT(bp_result == BP_RESULT_NORECORD);
 121                 return NULL;
 122         }
 123
 124         return dal_gpio_service_create_irq(gpio_service,
 125                                            pin_info.offset,
 126                                            pin_info.mask);
 127 }
 128
 129 /*
 130  *  Function: program_hpd_filter
 131  *
 132  *  @brief
 133  *     Programs HPD filter on associated HPD line
 134  *
 135  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 136  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 137  *
 138  *  @return
 139  *     true on success, false otherwise
 140  */
 141 static bool program_hpd_filter(const struct dc_link *link)
 142 {
 143         bool result = false;
 144         struct gpio *hpd;
 145         int delay_on_connect_in_ms = 0;
 146         int delay_on_disconnect_in_ms = 0;
 147
 148         if (link->is_hpd_filter_disabled)
 149                 return false;
 150         /* Verify feature is supported */
 151         switch (link->connector_signal) {
 152         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 153         case SIGNAL_TYPE_DVI_DUAL_LINK:
 154         case SIGNAL_TYPE_HDMI_TYPE_A:
 155                 /* Program hpd filter */
 156                 delay_on_connect_in_ms = 500;
 157                 delay_on_disconnect_in_ms = 100;
 158                 break;
 159         case SIGNAL_TYPE_DISPLAY_PORT:
 160         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 161                 /* Program hpd filter to allow DP signal to settle */
 162                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 163                  * only 100ms on DELL U2413
 164                  * 0: some passive dongle still show aux mode instead of i2c
 165                  * 20-50: not enough to hide bouncing HPD with passive dongle.
 166                  * also see intermittent i2c read issues.
 167                  */
 168                 delay_on_connect_in_ms = 80;
 169                 delay_on_disconnect_in_ms = 0;
 170                 break;
 171         case SIGNAL_TYPE_LVDS:
 172         case SIGNAL_TYPE_EDP:
 173         default:
 174                 /* Don't program hpd filter */
 175                 return false;
 176         }
 177
 178         /* Obtain HPD handle */
 179         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 180                            link->ctx->gpio_service);
 181
 182         if (!hpd)
 183                 return result;
 184
 185         /* Setup HPD filtering */
 186         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 187                 struct gpio_hpd_config config;
 188
 189                 config.delay_on_connect = delay_on_connect_in_ms;
 190                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 191
 192                 dal_irq_setup_hpd_filter(hpd, &config);
 193
 194                 dal_gpio_close(hpd);
 195
 196                 result = true;
 197         } else {
 198                 ASSERT_CRITICAL(false);
 199         }
 200
 201         /* Release HPD handle */
 202         dal_gpio_destroy_irq(&hpd);
 203
 204         return result;
 205 }
 206
 207 bool dc_link_wait_for_t12(struct dc_link *link)
 208 {
 209         if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 210                 link->dc->hwss.edp_wait_for_T12(link);
 211
 212                 return true;
 213         }
 214
 215         return false;
 216 }
 217
 218 /**
 219  * dc_link_detect_sink() - Determine if there is a sink connected
 220  *
 221  * @link: pointer to the dc link
 222  * @type: Returned connection type
 223  * Does not detect downstream devices, such as MST sinks
 224  * or display connected through active dongles
 225  */
 226 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 227 {
 228         uint32_t is_hpd_high = 0;
 229         struct gpio *hpd_pin;
 230
 231         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 232                 *type = dc_connection_single;
 233                 return true;
 234         }
 235
 236         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 237                 /*in case it is not on*/
 238                 if (!link->dc->config.edp_no_power_sequencing)
 239                         link->dc->hwss.edp_power_control(link, true);
 240                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 241         }
 242
 243         /* Link may not have physical HPD pin. */
 244         if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
 245                 if (link->is_hpd_pending || !dc_link_dpia_query_hpd_status(link))
 246                         *type = dc_connection_none;
 247                 else
 248                         *type = dc_connection_single;
 249
 250                 return true;
 251         }
 252
 253         /* todo: may need to lock gpio access */
 254         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 255                                link->ctx->gpio_service);
 256         if (!hpd_pin)
 257                 goto hpd_gpio_failure;
 258
 259         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 260         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 261         dal_gpio_close(hpd_pin);
 262         dal_gpio_destroy_irq(&hpd_pin);
 263
 264         if (is_hpd_high) {
 265                 *type = dc_connection_single;
 266                 /* TODO: need to do the actual detection */
 267         } else {
 268                 *type = dc_connection_none;
 269         }
 270
 271         return true;
 272
 273 hpd_gpio_failure:
 274         return false;
 275 }
 276
 277 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 278 {
 279         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 280
 281         switch (sink_signal) {
 282         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 283         case SIGNAL_TYPE_DVI_DUAL_LINK:
 284         case SIGNAL_TYPE_HDMI_TYPE_A:
 285         case SIGNAL_TYPE_LVDS:
 286         case SIGNAL_TYPE_RGB:
 287                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 288                 break;
 289
 290         case SIGNAL_TYPE_DISPLAY_PORT:
 291         case SIGNAL_TYPE_EDP:
 292                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 293                 break;
 294
 295         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 296                 /* MST does not use I2COverAux, but there is the
 297                  * SPECIAL use case for "immediate dwnstrm device
 298                  * access" (EPR#370830).
 299                  */
 300                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 301                 break;
 302
 303         default:
 304                 break;
 305         }
 306
 307         return transaction_type;
 308 }
 309
 310 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 311                                               struct graphics_object_id downstream)
 312 {
 313         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 314                 switch (downstream.id) {
 315                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 316                         switch (encoder.id) {
 317                         case ENCODER_ID_INTERNAL_DAC1:
 318                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 319                         case ENCODER_ID_INTERNAL_DAC2:
 320                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 321                                 return SIGNAL_TYPE_RGB;
 322                         default:
 323                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 324                         }
 325                 break;
 326                 case CONNECTOR_ID_DUAL_LINK_DVII:
 327                 {
 328                         switch (encoder.id) {
 329                         case ENCODER_ID_INTERNAL_DAC1:
 330                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 331                         case ENCODER_ID_INTERNAL_DAC2:
 332                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 333                                 return SIGNAL_TYPE_RGB;
 334                         default:
 335                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 336                         }
 337                 }
 338                 break;
 339                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 340                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 341                 case CONNECTOR_ID_DUAL_LINK_DVID:
 342                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 343                 case CONNECTOR_ID_VGA:
 344                         return SIGNAL_TYPE_RGB;
 345                 case CONNECTOR_ID_HDMI_TYPE_A:
 346                         return SIGNAL_TYPE_HDMI_TYPE_A;
 347                 case CONNECTOR_ID_LVDS:
 348                         return SIGNAL_TYPE_LVDS;
 349                 case CONNECTOR_ID_DISPLAY_PORT:
 350                 case CONNECTOR_ID_USBC:
 351                         return SIGNAL_TYPE_DISPLAY_PORT;
 352                 case CONNECTOR_ID_EDP:
 353                         return SIGNAL_TYPE_EDP;
 354                 default:
 355                         return SIGNAL_TYPE_NONE;
 356                 }
 357         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 358                 switch (downstream.id) {
 359                 case ENCODER_ID_EXTERNAL_NUTMEG:
 360                 case ENCODER_ID_EXTERNAL_TRAVIS:
 361                         return SIGNAL_TYPE_DISPLAY_PORT;
 362                 default:
 363                         return SIGNAL_TYPE_NONE;
 364                 }
 365         }
 366
 367         return SIGNAL_TYPE_NONE;
 368 }
 369
 370 /*
 371  * dc_link_is_dp_sink_present() - Check if there is a native DP
 372  * or passive DP-HDMI dongle connected
 373  */
 374 bool dc_link_is_dp_sink_present(struct dc_link *link)
 375 {
 376         enum gpio_result gpio_result;
 377         uint32_t clock_pin = 0;
 378         uint8_t retry = 0;
 379         struct ddc *ddc;
 380
 381         enum connector_id connector_id =
 382                 dal_graphics_object_id_get_connector_id(link->link_id);
 383
 384         bool present =
 385                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 386                 (connector_id == CONNECTOR_ID_EDP) ||
 387                 (connector_id == CONNECTOR_ID_USBC));
 388
 389         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 390
 391         if (!ddc) {
 392                 BREAK_TO_DEBUGGER();
 393                 return present;
 394         }
 395
 396         /* Open GPIO and set it to I2C mode */
 397         /* Note: this GpioMode_Input will be converted
 398          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 399          * which indicates we need additional delay
 400          */
 401
 402         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 403                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 404                 dal_ddc_close(ddc);
 405
 406                 return present;
 407         }
 408
 409         /*
 410          * Read GPIO: DP sink is present if both clock and data pins are zero
 411          *
 412          * [W/A] plug-unplug DP cable, sometimes customer board has
 413          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 414          * then monitor can't br light up. Add retry 3 times
 415          * But in real passive dongle, it need additional 3ms to detect
 416          */
 417         do {
 418                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 419                 ASSERT(gpio_result == GPIO_RESULT_OK);
 420                 if (clock_pin)
 421                         udelay(1000);
 422                 else
 423                         break;
 424         } while (retry++ < 3);
 425
 426         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 427
 428         dal_ddc_close(ddc);
 429
 430         return present;
 431 }
 432
 433 /*
 434  * @brief
 435  * Detect output sink type
 436  */
 437 static enum signal_type link_detect_sink(struct dc_link *link,
 438                                          enum dc_detect_reason reason)
 439 {
 440         enum signal_type result;
 441         struct graphics_object_id enc_id;
 442
 443         if (link->is_dig_mapping_flexible)
 444                 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
 445         else
 446                 enc_id = link->link_enc->id;
 447         result = get_basic_signal_type(enc_id, link->link_id);
 448
 449         /* Use basic signal type for link without physical connector. */
 450         if (link->ep_type != DISPLAY_ENDPOINT_PHY)
 451                 return result;
 452
 453         /* Internal digital encoder will detect only dongles
 454          * that require digital signal
 455          */
 456
 457         /* Detection mechanism is different
 458          * for different native connectors.
 459          * LVDS connector supports only LVDS signal;
 460          * PCIE is a bus slot, the actual connector needs to be detected first;
 461          * eDP connector supports only eDP signal;
 462          * HDMI should check straps for audio
 463          */
 464
 465         /* PCIE detects the actual connector on add-on board */
 466         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 467                 /* ZAZTODO implement PCIE add-on card detection */
 468         }
 469
 470         switch (link->link_id.id) {
 471         case CONNECTOR_ID_HDMI_TYPE_A: {
 472                 /* check audio support:
 473                  * if native HDMI is not supported, switch to DVI
 474                  */
 475                 struct audio_support *aud_support =
 476                                         &link->dc->res_pool->audio_support;
 477
 478                 if (!aud_support->hdmi_audio_native)
 479                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 480                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 481         }
 482         break;
 483         case CONNECTOR_ID_DISPLAY_PORT:
 484         case CONNECTOR_ID_USBC: {
 485                 /* DP HPD short pulse. Passive DP dongle will not
 486                  * have short pulse
 487                  */
 488                 if (reason != DETECT_REASON_HPDRX) {
 489                         /* Check whether DP signal detected: if not -
 490                          * we assume signal is DVI; it could be corrected
 491                          * to HDMI after dongle detection
 492                          */
 493                         if (!dm_helpers_is_dp_sink_present(link))
 494                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 495                 }
 496         }
 497         break;
 498         default:
 499         break;
 500         }
 501
 502         return result;
 503 }
 504
 505 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 506                                                                  struct audio_support *audio_support)
 507 {
 508         enum signal_type signal = SIGNAL_TYPE_NONE;
 509
 510         switch (dongle_type) {
 511         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 512                 if (audio_support->hdmi_audio_on_dongle)
 513                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 514                 else
 515                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 516                 break;
 517         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 518                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 519                 break;
 520         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 521                 if (audio_support->hdmi_audio_native)
 522                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 523                 else
 524                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 525                 break;
 526         default:
 527                 signal = SIGNAL_TYPE_NONE;
 528                 break;
 529         }
 530
 531         return signal;
 532 }
 533
 534 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 535                                                     struct display_sink_capability *sink_cap,
 536                                                     struct audio_support *audio_support)
 537 {
 538         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 539
 540         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 541                                                         audio_support);
 542 }
 543
 544 static void link_disconnect_sink(struct dc_link *link)
 545 {
 546         if (link->local_sink) {
 547                 dc_sink_release(link->local_sink);
 548                 link->local_sink = NULL;
 549         }
 550
 551         link->dpcd_sink_count = 0;
 552         //link->dpcd_caps.dpcd_rev.raw = 0;
 553 }
 554
 555 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 556 {
 557         dc_sink_release(link->local_sink);
 558         link->local_sink = prev_sink;
 559 }
 560
 561 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 562 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 563 {
 564         bool ret = false;
 565
 566         switch (signal) {
 567         case SIGNAL_TYPE_DISPLAY_PORT:
 568         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 569                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 570                 break;
 571         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 572         case SIGNAL_TYPE_DVI_DUAL_LINK:
 573         case SIGNAL_TYPE_HDMI_TYPE_A:
 574         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 575          * we can poll for bksv but some displays have an issue with this. Since its so rare
 576          * for a display to not be 1.4 capable, this assumtion is ok
 577          */
 578                 ret = true;
 579                 break;
 580         default:
 581                 break;
 582         }
 583         return ret;
 584 }
 585
 586 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 587 {
 588         bool ret = false;
 589
 590         switch (signal) {
 591         case SIGNAL_TYPE_DISPLAY_PORT:
 592         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 593                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 594                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 595                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 596                 break;
 597         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 598         case SIGNAL_TYPE_DVI_DUAL_LINK:
 599         case SIGNAL_TYPE_HDMI_TYPE_A:
 600                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 601                 break;
 602         default:
 603                 break;
 604         }
 605
 606         return ret;
 607 }
 608
 609 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 610 {
 611         struct hdcp_protection_message msg22;
 612         struct hdcp_protection_message msg14;
 613
 614         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 615         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 616         memset(link->hdcp_caps.rx_caps.raw, 0,
 617                 sizeof(link->hdcp_caps.rx_caps.raw));
 618
 619         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 620                         link->ddc->transaction_type ==
 621                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 622                         link->connector_signal == SIGNAL_TYPE_EDP) {
 623                 msg22.data = link->hdcp_caps.rx_caps.raw;
 624                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 625                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 626         } else {
 627                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 628                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 629                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 630         }
 631         msg22.version = HDCP_VERSION_22;
 632         msg22.link = HDCP_LINK_PRIMARY;
 633         msg22.max_retries = 5;
 634         dc_process_hdcp_msg(signal, link, &msg22);
 635
 636         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 637                 msg14.data = &link->hdcp_caps.bcaps.raw;
 638                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 639                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 640                 msg14.version = HDCP_VERSION_14;
 641                 msg14.link = HDCP_LINK_PRIMARY;
 642                 msg14.max_retries = 5;
 643
 644                 dc_process_hdcp_msg(signal, link, &msg14);
 645         }
 646
 647 }
 648 #endif
 649
 650 static void read_current_link_settings_on_detect(struct dc_link *link)
 651 {
 652         union lane_count_set lane_count_set = {0};
 653         uint8_t link_bw_set;
 654         uint8_t link_rate_set;
 655         uint32_t read_dpcd_retry_cnt = 10;
 656         enum dc_status status = DC_ERROR_UNEXPECTED;
 657         int i;
 658         union max_down_spread max_down_spread = {0};
 659
 660         // Read DPCD 00101h to find out the number of lanes currently set
 661         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 662                 status = core_link_read_dpcd(link,
 663                                              DP_LANE_COUNT_SET,
 664                                              &lane_count_set.raw,
 665                                              sizeof(lane_count_set));
 666                 /* First DPCD read after VDD ON can fail if the particular board
 667                  * does not have HPD pin wired correctly. So if DPCD read fails,
 668                  * which it should never happen, retry a few times. Target worst
 669                  * case scenario of 80 ms.
 670                  */
 671                 if (status == DC_OK) {
 672                         link->cur_link_settings.lane_count =
 673                                         lane_count_set.bits.LANE_COUNT_SET;
 674                         break;
 675                 }
 676
 677                 msleep(8);
 678         }
 679
 680         // Read DPCD 00100h to find if standard link rates are set
 681         core_link_read_dpcd(link, DP_LINK_BW_SET,
 682                             &link_bw_set, sizeof(link_bw_set));
 683
 684         if (link_bw_set == 0) {
 685                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 686                         /* If standard link rates are not being used,
 687                          * Read DPCD 00115h to find the edp link rate set used
 688                          */
 689                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 690                                             &link_rate_set, sizeof(link_rate_set));
 691
 692                         // edp_supported_link_rates_count = 0 for DP
 693                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 694                                 link->cur_link_settings.link_rate =
 695                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 696                                 link->cur_link_settings.link_rate_set = link_rate_set;
 697                                 link->cur_link_settings.use_link_rate_set = true;
 698                         }
 699                 } else {
 700                         // Link Rate not found. Seamless boot may not work.
 701                         ASSERT(false);
 702                 }
 703         } else {
 704                 link->cur_link_settings.link_rate = link_bw_set;
 705                 link->cur_link_settings.use_link_rate_set = false;
 706         }
 707         // Read DPCD 00003h to find the max down spread.
 708         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 709                             &max_down_spread.raw, sizeof(max_down_spread));
 710         link->cur_link_settings.link_spread =
 711                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 712                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 713 }
 714
 715 static bool detect_dp(struct dc_link *link,
 716                       struct display_sink_capability *sink_caps,
 717                       enum dc_detect_reason reason)
 718 {
 719         struct audio_support *audio_support = &link->dc->res_pool->audio_support;
 720
 721         sink_caps->signal = link_detect_sink(link, reason);
 722         sink_caps->transaction_type =
 723                 get_ddc_transaction_type(sink_caps->signal);
 724
 725         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 726                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 727                 if (!detect_dp_sink_caps(link))
 728                         return false;
 729
 730                 if (is_dp_branch_device(link))
 731                         /* DP SST branch */
 732                         link->type = dc_connection_sst_branch;
 733         } else {
 734                 /* DP passive dongles */
 735                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 736                                                                 sink_caps,
 737                                                                 audio_support);
 738                 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 739                 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
 740                 link->dpcd_caps.dpcd_rev.raw = 0;
 741         }
 742
 743         return true;
 744 }
 745
 746 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 747 {
 748         if (old_edid->length != new_edid->length)
 749                 return false;
 750
 751         if (new_edid->length == 0)
 752                 return false;
 753
 754         return (memcmp(old_edid->raw_edid,
 755                        new_edid->raw_edid, new_edid->length) == 0);
 756 }
 757
 758 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 759 {
 760         /**
 761          * something is terribly wrong if time out is > 200ms. (5Hz)
 762          * 500 microseconds * 400 tries us 200 ms
 763          **/
 764         unsigned int sleep_time_in_microseconds = 500;
 765         unsigned int tries_allowed = 400;
 766         bool is_in_alt_mode;
 767         unsigned long long enter_timestamp;
 768         unsigned long long finish_timestamp;
 769         unsigned long long time_taken_in_ns;
 770         int tries_taken;
 771
 772         DC_LOGGER_INIT(link->ctx->logger);
 773
 774         if (!link->link_enc->funcs->is_in_alt_mode)
 775                 return true;
 776
 777         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 778         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 779
 780         if (is_in_alt_mode)
 781                 return true;
 782
 783         enter_timestamp = dm_get_timestamp(link->ctx);
 784
 785         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 786                 udelay(sleep_time_in_microseconds);
 787                 /* ask the link if alt mode is enabled, if so return ok */
 788                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 789                         finish_timestamp = dm_get_timestamp(link->ctx);
 790                         time_taken_in_ns =
 791                                 dm_get_elapse_time_in_ns(link->ctx,
 792                                                          finish_timestamp,
 793                                                          enter_timestamp);
 794                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 795                                        div_u64(time_taken_in_ns, 1000000));
 796                         return true;
 797                 }
 798         }
 799         finish_timestamp = dm_get_timestamp(link->ctx);
 800         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 801                                                     enter_timestamp);
 802         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 803                        div_u64(time_taken_in_ns, 1000000));
 804         return false;
 805 }
 806
 807 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 808 {
 809         /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
 810          * reports DSC support.
 811          */
 812         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
 813                         link->type == dc_connection_mst_branch &&
 814                         link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
 815                         link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
 816                         link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
 817                         !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
 818                 link->wa_flags.dpia_mst_dsc_always_on = true;
 819 }
 820
 821 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 822 {
 823         /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
 824         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 825                 link->wa_flags.dpia_mst_dsc_always_on = false;
 826 }
 827
 828 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
 829 {
 830         DC_LOGGER_INIT(link->ctx->logger);
 831
 832         LINK_INFO("link=%d, mst branch is now Connected\n",
 833                   link->link_index);
 834
 835         apply_dpia_mst_dsc_always_on_wa(link);
 836         link->type = dc_connection_mst_branch;
 837         dm_helpers_dp_update_branch_info(link->ctx, link);
 838         if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
 839                         link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
 840                 link_disconnect_sink(link);
 841         } else {
 842                 link->type = dc_connection_sst_branch;
 843         }
 844
 845         return link->type == dc_connection_mst_branch;
 846 }
 847
 848 static bool reset_cur_dp_mst_topology(struct dc_link *link)
 849 {
 850         bool result = false;
 851         DC_LOGGER_INIT(link->ctx->logger);
 852
 853         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 854                   link->link_index);
 855
 856         revert_dpia_mst_dsc_always_on_wa(link);
 857         result = dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 858
 859         link->mst_stream_alloc_table.stream_count = 0;
 860         memset(link->mst_stream_alloc_table.stream_allocations,
 861                         0,
 862                         sizeof(link->mst_stream_alloc_table.stream_allocations));
 863         return result;
 864 }
 865
 866 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
 867                 enum dc_detect_reason reason)
 868 {
 869         int i;
 870         bool can_apply_seamless_boot = false;
 871
 872         for (i = 0; i < dc->current_state->stream_count; i++) {
 873                 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
 874                         can_apply_seamless_boot = true;
 875                         break;
 876                 }
 877         }
 878
 879         return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
 880 }
 881
 882 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 883 {
 884         dc_z10_restore(dc);
 885         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
 886 }
 887
 888 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 889 {
 890         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
 891 }
 892
 893 static void set_all_streams_dpms_off_for_link(struct dc_link *link)
 894 {
 895         int i;
 896         struct pipe_ctx *pipe_ctx;
 897         struct dc_stream_update stream_update;
 898         bool dpms_off = true;
 899         struct link_resource link_res = {0};
 900
 901         memset(&stream_update, 0, sizeof(stream_update));
 902         stream_update.dpms_off = &dpms_off;
 903
 904         for (i = 0; i < MAX_PIPES; i++) {
 905                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
 906                 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
 907                                 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) {
 908                         stream_update.stream = pipe_ctx->stream;
 909                         dc_commit_updates_for_stream(link->ctx->dc, NULL, 0,
 910                                         pipe_ctx->stream, &stream_update,
 911                                         link->ctx->dc->current_state);
 912                 }
 913         }
 914
 915         /* link can be also enabled by vbios. In this case it is not recorded
 916          * in pipe_ctx. Disable link phy here to make sure it is completely off
 917          */
 918         dp_disable_link_phy(link, &link_res, link->connector_signal);
 919 }
 920
 921 static void verify_link_capability_destructive(struct dc_link *link,
 922                 struct dc_sink *sink,
 923                 enum dc_detect_reason reason)
 924 {
 925         bool should_prepare_phy_clocks =
 926                         should_prepare_phy_clocks_for_link_verification(link->dc, reason);
 927
 928         if (should_prepare_phy_clocks)
 929                 prepare_phy_clocks_for_destructive_link_verification(link->dc);
 930
 931         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 932                 struct dc_link_settings known_limit_link_setting =
 933                                 dp_get_max_link_cap(link);
 934                 set_all_streams_dpms_off_for_link(link);
 935                 dp_verify_link_cap_with_retries(
 936                                 link, &known_limit_link_setting,
 937                                 LINK_TRAINING_MAX_VERIFY_RETRY);
 938         } else {
 939                 ASSERT(0);
 940         }
 941
 942         if (should_prepare_phy_clocks)
 943                 restore_phy_clocks_for_destructive_link_verification(link->dc);
 944 }
 945
 946 static void verify_link_capability_non_destructive(struct dc_link *link)
 947 {
 948         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 949                 if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
 950                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 951                         /* TODO - should we check link encoder's max link caps here?
 952                          * How do we know which link encoder to check from?
 953                          */
 954                         link->verified_link_cap = link->reported_link_cap;
 955                 else
 956                         link->verified_link_cap = dp_get_max_link_cap(link);
 957         }
 958 }
 959
 960 static bool should_verify_link_capability_destructively(struct dc_link *link,
 961                 enum dc_detect_reason reason)
 962 {
 963         bool destrictive = false;
 964         struct dc_link_settings max_link_cap;
 965         bool is_link_enc_unavailable = link->link_enc &&
 966                         link->dc->res_pool->funcs->link_encs_assign &&
 967                         !link_enc_cfg_is_link_enc_avail(
 968                                         link->ctx->dc,
 969                                         link->link_enc->preferred_engine,
 970                                         link);
 971
 972         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 973                 max_link_cap = dp_get_max_link_cap(link);
 974                 destrictive = true;
 975
 976                 if (link->dc->debug.skip_detection_link_training ||
 977                                 dc_is_embedded_signal(link->local_sink->sink_signal) ||
 978                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
 979                         destrictive = false;
 980                 } else if (dp_get_link_encoding_format(&max_link_cap) ==
 981                                 DP_8b_10b_ENCODING) {
 982                         if (link->dpcd_caps.is_mst_capable ||
 983                                         is_link_enc_unavailable) {
 984                                 destrictive = false;
 985                         }
 986                 }
 987         }
 988
 989         return destrictive;
 990 }
 991
 992 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,
 993                 enum dc_detect_reason reason)
 994 {
 995         if (should_verify_link_capability_destructively(link, reason))
 996                 verify_link_capability_destructive(link, sink, reason);
 997         else
 998                 verify_link_capability_non_destructive(link);
 999 }
1000
1001
1002 /**
1003  * detect_link_and_local_sink() - Detect if a sink is attached to a given link
1004  *
1005  * link->local_sink is created or destroyed as needed.
1006  *
1007  * This does not create remote sinks.
1008  */
1009 static bool detect_link_and_local_sink(struct dc_link *link,
1010                                   enum dc_detect_reason reason)
1011 {
1012         struct dc_sink_init_data sink_init_data = { 0 };
1013         struct display_sink_capability sink_caps = { 0 };
1014         uint32_t i;
1015         bool converter_disable_audio = false;
1016         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
1017         bool same_edid = false;
1018         enum dc_edid_status edid_status;
1019         struct dc_context *dc_ctx = link->ctx;
1020         struct dc *dc = dc_ctx->dc;
1021         struct dc_sink *sink = NULL;
1022         struct dc_sink *prev_sink = NULL;
1023         struct dpcd_caps prev_dpcd_caps;
1024         enum dc_connection_type new_connection_type = dc_connection_none;
1025         enum dc_connection_type pre_connection_type = dc_connection_none;
1026         const uint32_t post_oui_delay = 30; // 30ms
1027
1028         DC_LOGGER_INIT(link->ctx->logger);
1029
1030         if (dc_is_virtual_signal(link->connector_signal))
1031                 return false;
1032
1033         if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
1034                 link->connector_signal == SIGNAL_TYPE_EDP) &&
1035                 (!link->dc->config.allow_edp_hotplug_detection)) &&
1036                 link->local_sink) {
1037                 // need to re-write OUI and brightness in resume case
1038                 if (link->connector_signal == SIGNAL_TYPE_EDP &&
1039                         (link->dpcd_sink_ext_caps.bits.oled == 1)) {
1040                         dpcd_set_source_specific_data(link);
1041                         msleep(post_oui_delay);
1042                         dc_link_set_default_brightness_aux(link);
1043                         //TODO: use cached
1044                 }
1045
1046                 return true;
1047         }
1048
1049         if (!dc_link_detect_sink(link, &new_connection_type)) {
1050                 BREAK_TO_DEBUGGER();
1051                 return false;
1052         }
1053
1054         prev_sink = link->local_sink;
1055         if (prev_sink) {
1056                 dc_sink_retain(prev_sink);
1057                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
1058         }
1059
1060         link_disconnect_sink(link);
1061         if (new_connection_type != dc_connection_none) {
1062                 pre_connection_type = link->type;
1063                 link->type = new_connection_type;
1064                 link->link_state_valid = false;
1065
1066                 /* From Disconnected-to-Connected. */
1067                 switch (link->connector_signal) {
1068                 case SIGNAL_TYPE_HDMI_TYPE_A: {
1069                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1070                         if (aud_support->hdmi_audio_native)
1071                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1072                         else
1073                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1074                         break;
1075                 }
1076
1077                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1078                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1079                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1080                         break;
1081                 }
1082
1083                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1084                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1085                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1086                         break;
1087                 }
1088
1089                 case SIGNAL_TYPE_LVDS: {
1090                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1091                         sink_caps.signal = SIGNAL_TYPE_LVDS;
1092                         break;
1093                 }
1094
1095                 case SIGNAL_TYPE_EDP: {
1096                         read_current_link_settings_on_detect(link);
1097
1098                         detect_edp_sink_caps(link);
1099                         read_current_link_settings_on_detect(link);
1100
1101                         /* Disable power sequence on MIPI panel + converter
1102                          */
1103                         if (dc->config.enable_mipi_converter_optimization &&
1104                                 dc_ctx->dce_version == DCN_VERSION_3_01 &&
1105                                 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
1106                                 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
1107                                         sizeof(link->dpcd_caps.branch_dev_name)) == 0)
1108                                 dc->config.edp_no_power_sequencing = true;
1109
1110                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1111                         sink_caps.signal = SIGNAL_TYPE_EDP;
1112                         break;
1113                 }
1114
1115                 case SIGNAL_TYPE_DISPLAY_PORT: {
1116                         /* wa HPD high coming too early*/
1117                         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
1118                             link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
1119                                 /* if alt mode times out, return false */
1120                                 if (!wait_for_entering_dp_alt_mode(link))
1121                                         return false;
1122                         }
1123
1124                         if (!detect_dp(link, &sink_caps, reason)) {
1125                                 if (prev_sink)
1126                                         dc_sink_release(prev_sink);
1127                                 return false;
1128                         }
1129
1130                         /* Active SST downstream branch device unplug*/
1131                         if (link->type == dc_connection_sst_branch &&
1132                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1133                                 if (prev_sink)
1134                                         /* Downstream unplug */
1135                                         dc_sink_release(prev_sink);
1136                                 return true;
1137                         }
1138
1139                         /* disable audio for non DP to HDMI active sst converter */
1140                         if (link->type == dc_connection_sst_branch &&
1141                                         is_dp_active_dongle(link) &&
1142                                         (link->dpcd_caps.dongle_type !=
1143                                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1144                                 converter_disable_audio = true;
1145
1146                         // link switch from MST to non-MST stop topology manager
1147                         if (pre_connection_type == dc_connection_mst_branch &&
1148                                         link->type != dc_connection_mst_branch)
1149                                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1150                         break;
1151                 }
1152
1153                 default:
1154                         DC_ERROR("Invalid connector type! signal:%d\n",
1155                                  link->connector_signal);
1156                         if (prev_sink)
1157                                 dc_sink_release(prev_sink);
1158                         return false;
1159                 } /* switch() */
1160
1161                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1162                         link->dpcd_sink_count =
1163                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1164                 else
1165                         link->dpcd_sink_count = 1;
1166
1167                 dal_ddc_service_set_transaction_type(link->ddc,
1168                                                      sink_caps.transaction_type);
1169
1170                 link->aux_mode =
1171                         dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1172
1173                 sink_init_data.link = link;
1174                 sink_init_data.sink_signal = sink_caps.signal;
1175
1176                 sink = dc_sink_create(&sink_init_data);
1177                 if (!sink) {
1178                         DC_ERROR("Failed to create sink!\n");
1179                         if (prev_sink)
1180                                 dc_sink_release(prev_sink);
1181                         return false;
1182                 }
1183
1184                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1185                 sink->converter_disable_audio = converter_disable_audio;
1186
1187                 /* dc_sink_create returns a new reference */
1188                 link->local_sink = sink;
1189
1190                 edid_status = dm_helpers_read_local_edid(link->ctx,
1191                                                          link, sink);
1192
1193                 switch (edid_status) {
1194                 case EDID_BAD_CHECKSUM:
1195                         DC_LOG_ERROR("EDID checksum invalid.\n");
1196                         break;
1197                 case EDID_PARTIAL_VALID:
1198                         DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");
1199                         break;
1200                 case EDID_NO_RESPONSE:
1201                         DC_LOG_ERROR("No EDID read.\n");
1202                         /*
1203                          * Abort detection for non-DP connectors if we have
1204                          * no EDID
1205                          *
1206                          * DP needs to report as connected if HDP is high
1207                          * even if we have no EDID in order to go to
1208                          * fail-safe mode
1209                          */
1210                         if (dc_is_hdmi_signal(link->connector_signal) ||
1211                             dc_is_dvi_signal(link->connector_signal)) {
1212                                 if (prev_sink)
1213                                         dc_sink_release(prev_sink);
1214
1215                                 return false;
1216                         }
1217
1218                         if (link->type == dc_connection_sst_branch &&
1219                                         link->dpcd_caps.dongle_type ==
1220                                                 DISPLAY_DONGLE_DP_VGA_CONVERTER &&
1221                                         reason == DETECT_REASON_HPDRX) {
1222                                 /* Abort detection for DP-VGA adapters when EDID
1223                                  * can't be read and detection reason is VGA-side
1224                                  * hotplug
1225                                  */
1226                                 if (prev_sink)
1227                                         dc_sink_release(prev_sink);
1228                                 link_disconnect_sink(link);
1229
1230                                 return true;
1231                         }
1232
1233                         break;
1234                 default:
1235                         break;
1236                 }
1237
1238                 // Check if edid is the same
1239                 if ((prev_sink) &&
1240                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1241                         same_edid = is_same_edid(&prev_sink->dc_edid,
1242                                                  &sink->dc_edid);
1243
1244                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1245                         link->ctx->dc->debug.hdmi20_disable = true;
1246
1247                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1248                     sink_caps.transaction_type ==
1249                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1250                         /*
1251                          * TODO debug why Dell 2413 doesn't like
1252                          *  two link trainings
1253                          */
1254 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1255                         query_hdcp_capability(sink->sink_signal, link);
1256 #endif
1257                 } else {
1258                         // If edid is the same, then discard new sink and revert back to original sink
1259                         if (same_edid) {
1260                                 link_disconnect_remap(prev_sink, link);
1261                                 sink = prev_sink;
1262                                 prev_sink = NULL;
1263                         }
1264 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1265                         query_hdcp_capability(sink->sink_signal, link);
1266 #endif
1267                 }
1268
1269                 /* HDMI-DVI Dongle */
1270                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1271                     !sink->edid_caps.edid_hdmi)
1272                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1273
1274                 if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
1275                         dp_trace_init(link);
1276
1277                 /* Connectivity log: detection */
1278                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1279                         CONN_DATA_DETECT(link,
1280                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1281                                          DC_EDID_BLOCK_SIZE,
1282                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1283                 }
1284
1285                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1286                         "manufacturer_id = %X, "
1287                         "product_id = %X, "
1288                         "serial_number = %X, "
1289                         "manufacture_week = %d, "
1290                         "manufacture_year = %d, "
1291                         "display_name = %s, "
1292                         "speaker_flag = %d, "
1293                         "audio_mode_count = %d\n",
1294                         __func__,
1295                         sink->edid_caps.manufacturer_id,
1296                         sink->edid_caps.product_id,
1297                         sink->edid_caps.serial_number,
1298                         sink->edid_caps.manufacture_week,
1299                         sink->edid_caps.manufacture_year,
1300                         sink->edid_caps.display_name,
1301                         sink->edid_caps.speaker_flags,
1302                         sink->edid_caps.audio_mode_count);
1303
1304                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1305                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1306                                 "format_code = %d, "
1307                                 "channel_count = %d, "
1308                                 "sample_rate = %d, "
1309                                 "sample_size = %d\n",
1310                                 __func__,
1311                                 i,
1312                                 sink->edid_caps.audio_modes[i].format_code,
1313                                 sink->edid_caps.audio_modes[i].channel_count,
1314                                 sink->edid_caps.audio_modes[i].sample_rate,
1315                                 sink->edid_caps.audio_modes[i].sample_size);
1316                 }
1317         } else {
1318                 /* From Connected-to-Disconnected. */
1319                 link->type = dc_connection_none;
1320                 sink_caps.signal = SIGNAL_TYPE_NONE;
1321                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1322                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1323                  *  the dongle is still there and limits the number of modes we can emulate.
1324                  *  Clear dongle_max_pix_clk on disconnect to fix this
1325                  */
1326                 link->dongle_max_pix_clk = 0;
1327
1328                 dc_link_clear_dprx_states(link);
1329                 dp_trace_reset(link);
1330         }
1331
1332         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1333                   link->link_index, sink,
1334                   (sink_caps.signal ==
1335                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1336                   prev_sink, same_edid);
1337
1338         if (prev_sink)
1339                 dc_sink_release(prev_sink);
1340
1341         return true;
1342 }
1343
1344 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1345 {
1346         bool is_local_sink_detect_success;
1347         bool is_delegated_to_mst_top_mgr = false;
1348         enum dc_connection_type pre_link_type = link->type;
1349
1350         is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
1351
1352         if (is_local_sink_detect_success && link->local_sink)
1353                 verify_link_capability(link, link->local_sink, reason);
1354
1355         if (is_local_sink_detect_success && link->local_sink &&
1356                         dc_is_dp_signal(link->local_sink->sink_signal) &&
1357                         link->dpcd_caps.is_mst_capable)
1358                 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);
1359
1360         if (is_local_sink_detect_success &&
1361                         pre_link_type == dc_connection_mst_branch &&
1362                         link->type != dc_connection_mst_branch)
1363                 is_delegated_to_mst_top_mgr = reset_cur_dp_mst_topology(link);
1364
1365         return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1366 }
1367
1368 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1369 {
1370         uint32_t state;
1371
1372         dal_gpio_lock_pin(dc_link->hpd_gpio);
1373         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1374         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1375
1376         return state;
1377 }
1378
1379 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1380 {
1381         struct gpio *hpd;
1382         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1383
1384         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1385                            link->ctx->gpio_service);
1386
1387         if (hpd) {
1388                 switch (dal_irq_get_source(hpd)) {
1389                 case DC_IRQ_SOURCE_HPD1:
1390                         hpd_id = HPD_SOURCEID1;
1391                 break;
1392                 case DC_IRQ_SOURCE_HPD2:
1393                         hpd_id = HPD_SOURCEID2;
1394                 break;
1395                 case DC_IRQ_SOURCE_HPD3:
1396                         hpd_id = HPD_SOURCEID3;
1397                 break;
1398                 case DC_IRQ_SOURCE_HPD4:
1399                         hpd_id = HPD_SOURCEID4;
1400                 break;
1401                 case DC_IRQ_SOURCE_HPD5:
1402                         hpd_id = HPD_SOURCEID5;
1403                 break;
1404                 case DC_IRQ_SOURCE_HPD6:
1405                         hpd_id = HPD_SOURCEID6;
1406                 break;
1407                 default:
1408                         BREAK_TO_DEBUGGER();
1409                 break;
1410                 }
1411
1412                 dal_gpio_destroy_irq(&hpd);
1413         }
1414
1415         return hpd_id;
1416 }
1417
1418 static enum channel_id get_ddc_line(struct dc_link *link)
1419 {
1420         struct ddc *ddc;
1421         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1422
1423         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1424
1425         if (ddc) {
1426                 switch (dal_ddc_get_line(ddc)) {
1427                 case GPIO_DDC_LINE_DDC1:
1428                         channel = CHANNEL_ID_DDC1;
1429                         break;
1430                 case GPIO_DDC_LINE_DDC2:
1431                         channel = CHANNEL_ID_DDC2;
1432                         break;
1433                 case GPIO_DDC_LINE_DDC3:
1434                         channel = CHANNEL_ID_DDC3;
1435                         break;
1436                 case GPIO_DDC_LINE_DDC4:
1437                         channel = CHANNEL_ID_DDC4;
1438                         break;
1439                 case GPIO_DDC_LINE_DDC5:
1440                         channel = CHANNEL_ID_DDC5;
1441                         break;
1442                 case GPIO_DDC_LINE_DDC6:
1443                         channel = CHANNEL_ID_DDC6;
1444                         break;
1445                 case GPIO_DDC_LINE_DDC_VGA:
1446                         channel = CHANNEL_ID_DDC_VGA;
1447                         break;
1448                 case GPIO_DDC_LINE_I2C_PAD:
1449                         channel = CHANNEL_ID_I2C_PAD;
1450                         break;
1451                 default:
1452                         BREAK_TO_DEBUGGER();
1453                         break;
1454                 }
1455         }
1456
1457         return channel;
1458 }
1459
1460 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1461 {
1462         switch (encoder.id) {
1463         case ENCODER_ID_INTERNAL_UNIPHY:
1464                 switch (encoder.enum_id) {
1465                 case ENUM_ID_1:
1466                         return TRANSMITTER_UNIPHY_A;
1467                 case ENUM_ID_2:
1468                         return TRANSMITTER_UNIPHY_B;
1469                 default:
1470                         return TRANSMITTER_UNKNOWN;
1471                 }
1472         break;
1473         case ENCODER_ID_INTERNAL_UNIPHY1:
1474                 switch (encoder.enum_id) {
1475                 case ENUM_ID_1:
1476                         return TRANSMITTER_UNIPHY_C;
1477                 case ENUM_ID_2:
1478                         return TRANSMITTER_UNIPHY_D;
1479                 default:
1480                         return TRANSMITTER_UNKNOWN;
1481                 }
1482         break;
1483         case ENCODER_ID_INTERNAL_UNIPHY2:
1484                 switch (encoder.enum_id) {
1485                 case ENUM_ID_1:
1486                         return TRANSMITTER_UNIPHY_E;
1487                 case ENUM_ID_2:
1488                         return TRANSMITTER_UNIPHY_F;
1489                 default:
1490                         return TRANSMITTER_UNKNOWN;
1491                 }
1492         break;
1493         case ENCODER_ID_INTERNAL_UNIPHY3:
1494                 switch (encoder.enum_id) {
1495                 case ENUM_ID_1:
1496                         return TRANSMITTER_UNIPHY_G;
1497                 default:
1498                         return TRANSMITTER_UNKNOWN;
1499                 }
1500         break;
1501         case ENCODER_ID_EXTERNAL_NUTMEG:
1502                 switch (encoder.enum_id) {
1503                 case ENUM_ID_1:
1504                         return TRANSMITTER_NUTMEG_CRT;
1505                 default:
1506                         return TRANSMITTER_UNKNOWN;
1507                 }
1508         break;
1509         case ENCODER_ID_EXTERNAL_TRAVIS:
1510                 switch (encoder.enum_id) {
1511                 case ENUM_ID_1:
1512                         return TRANSMITTER_TRAVIS_CRT;
1513                 case ENUM_ID_2:
1514                         return TRANSMITTER_TRAVIS_LCD;
1515                 default:
1516                         return TRANSMITTER_UNKNOWN;
1517                 }
1518         break;
1519         default:
1520                 return TRANSMITTER_UNKNOWN;
1521         }
1522 }
1523
1524 static bool dc_link_construct_legacy(struct dc_link *link,
1525                                      const struct link_init_data *init_params)
1526 {
1527         uint8_t i;
1528         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1529         struct dc_context *dc_ctx = init_params->ctx;
1530         struct encoder_init_data enc_init_data = { 0 };
1531         struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1532         struct integrated_info *info;
1533         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1534         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1535         struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1536
1537         DC_LOGGER_INIT(dc_ctx->logger);
1538
1539         info = kzalloc(sizeof(*info), GFP_KERNEL);
1540         if (!info)
1541                 goto create_fail;
1542
1543         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1544         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1545
1546         link->link_status.dpcd_caps = &link->dpcd_caps;
1547
1548         link->dc = init_params->dc;
1549         link->ctx = dc_ctx;
1550         link->link_index = init_params->link_index;
1551
1552         memset(&link->preferred_training_settings, 0,
1553                sizeof(struct dc_link_training_overrides));
1554         memset(&link->preferred_link_setting, 0,
1555                sizeof(struct dc_link_settings));
1556
1557         link->link_id =
1558                 bios->funcs->get_connector_id(bios, init_params->connector_index);
1559
1560         link->ep_type = DISPLAY_ENDPOINT_PHY;
1561
1562         DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1563
1564         if (bios->funcs->get_disp_connector_caps_info) {
1565                 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1566                 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1567                 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1568         }
1569
1570         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1571                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1572                                      __func__, init_params->connector_index,
1573                                      link->link_id.type, OBJECT_TYPE_CONNECTOR);
1574                 goto create_fail;
1575         }
1576
1577         if (link->dc->res_pool->funcs->link_init)
1578                 link->dc->res_pool->funcs->link_init(link);
1579
1580         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1581                                       link->ctx->gpio_service);
1582
1583         if (link->hpd_gpio) {
1584                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1585                 dal_gpio_unlock_pin(link->hpd_gpio);
1586                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1587
1588                 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1589                 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1590         }
1591
1592         switch (link->link_id.id) {
1593         case CONNECTOR_ID_HDMI_TYPE_A:
1594                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1595
1596                 break;
1597         case CONNECTOR_ID_SINGLE_LINK_DVID:
1598         case CONNECTOR_ID_SINGLE_LINK_DVII:
1599                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1600                 break;
1601         case CONNECTOR_ID_DUAL_LINK_DVID:
1602         case CONNECTOR_ID_DUAL_LINK_DVII:
1603                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1604                 break;
1605         case CONNECTOR_ID_DISPLAY_PORT:
1606         case CONNECTOR_ID_USBC:
1607                 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1608
1609                 if (link->hpd_gpio)
1610                         link->irq_source_hpd_rx =
1611                                         dal_irq_get_rx_source(link->hpd_gpio);
1612
1613                 break;
1614         case CONNECTOR_ID_EDP:
1615                 link->connector_signal = SIGNAL_TYPE_EDP;
1616
1617                 if (link->hpd_gpio) {
1618                         if (!link->dc->config.allow_edp_hotplug_detection)
1619                                 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1620
1621                         switch (link->dc->config.allow_edp_hotplug_detection) {
1622                         case 1: // only the 1st eDP handles hotplug
1623                                 if (link->link_index == 0)
1624                                         link->irq_source_hpd_rx =
1625                                                 dal_irq_get_rx_source(link->hpd_gpio);
1626                                 else
1627                                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1628                                 break;
1629                         case 2: // only the 2nd eDP handles hotplug
1630                                 if (link->link_index == 1)
1631                                         link->irq_source_hpd_rx =
1632                                                 dal_irq_get_rx_source(link->hpd_gpio);
1633                                 else
1634                                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1635                                 break;
1636                         default:
1637                                 break;
1638                         }
1639                 }
1640
1641                 break;
1642         case CONNECTOR_ID_LVDS:
1643                 link->connector_signal = SIGNAL_TYPE_LVDS;
1644                 break;
1645         default:
1646                 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1647                                link->link_id.id);
1648                 goto create_fail;
1649         }
1650
1651         /* TODO: #DAL3 Implement id to str function.*/
1652         LINK_INFO("Connector[%d] description:"
1653                   "signal %d\n",
1654                   init_params->connector_index,
1655                   link->connector_signal);
1656
1657         ddc_service_init_data.ctx = link->ctx;
1658         ddc_service_init_data.id = link->link_id;
1659         ddc_service_init_data.link = link;
1660         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1661
1662         if (!link->ddc) {
1663                 DC_ERROR("Failed to create ddc_service!\n");
1664                 goto ddc_create_fail;
1665         }
1666
1667         if (!link->ddc->ddc_pin) {
1668                 DC_ERROR("Failed to get I2C info for connector!\n");
1669                 goto ddc_create_fail;
1670         }
1671
1672         link->ddc_hw_inst =
1673                 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1674
1675
1676         if (link->dc->res_pool->funcs->panel_cntl_create &&
1677                 (link->link_id.id == CONNECTOR_ID_EDP ||
1678                         link->link_id.id == CONNECTOR_ID_LVDS)) {
1679                 panel_cntl_init_data.ctx = dc_ctx;
1680                 panel_cntl_init_data.inst =
1681                         panel_cntl_init_data.ctx->dc_edp_id_count;
1682                 link->panel_cntl =
1683                         link->dc->res_pool->funcs->panel_cntl_create(
1684                                                                 &panel_cntl_init_data);
1685                 panel_cntl_init_data.ctx->dc_edp_id_count++;
1686
1687                 if (link->panel_cntl == NULL) {
1688                         DC_ERROR("Failed to create link panel_cntl!\n");
1689                         goto panel_cntl_create_fail;
1690                 }
1691         }
1692
1693         enc_init_data.ctx = dc_ctx;
1694         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1695                               &enc_init_data.encoder);
1696         enc_init_data.connector = link->link_id;
1697         enc_init_data.channel = get_ddc_line(link);
1698         enc_init_data.hpd_source = get_hpd_line(link);
1699
1700         link->hpd_src = enc_init_data.hpd_source;
1701
1702         enc_init_data.transmitter =
1703                 translate_encoder_to_transmitter(enc_init_data.encoder);
1704         link->link_enc =
1705                 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1706
1707         if (!link->link_enc) {
1708                 DC_ERROR("Failed to create link encoder!\n");
1709                 goto link_enc_create_fail;
1710         }
1711
1712         DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1713         DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE);
1714
1715         /* Update link encoder tracking variables. These are used for the dynamic
1716          * assignment of link encoders to streams.
1717          */
1718         link->eng_id = link->link_enc->preferred_engine;
1719         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1720         link->dc->res_pool->dig_link_enc_count++;
1721
1722         link->link_enc_hw_inst = link->link_enc->transmitter;
1723
1724         for (i = 0; i < 4; i++) {
1725                 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1726                                              link->link_id, i,
1727                                              &link->device_tag) != BP_RESULT_OK) {
1728                         DC_ERROR("Failed to find device tag!\n");
1729                         goto device_tag_fail;
1730                 }
1731
1732                 /* Look for device tag that matches connector signal,
1733                  * CRT for rgb, LCD for other supported signal tyes
1734                  */
1735                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1736                                                       link->device_tag.dev_id))
1737                         continue;
1738                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1739                     link->connector_signal != SIGNAL_TYPE_RGB)
1740                         continue;
1741                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1742                     link->connector_signal == SIGNAL_TYPE_RGB)
1743                         continue;
1744
1745                 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1746                 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1747                 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1748                 break;
1749         }
1750
1751         if (bios->integrated_info)
1752                 memcpy(info, bios->integrated_info, sizeof(*info));
1753
1754         /* Look for channel mapping corresponding to connector and device tag */
1755         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1756                 struct external_display_path *path =
1757                         &info->ext_disp_conn_info.path[i];
1758
1759                 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1760                     path->device_connector_id.id == link->link_id.id &&
1761                     path->device_connector_id.type == link->link_id.type) {
1762                         if (link->device_tag.acpi_device != 0 &&
1763                             path->device_acpi_enum == link->device_tag.acpi_device) {
1764                                 link->ddi_channel_mapping = path->channel_mapping;
1765                                 link->chip_caps = path->caps;
1766                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1767                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1768                         } else if (path->device_tag ==
1769                                    link->device_tag.dev_id.raw_device_tag) {
1770                                 link->ddi_channel_mapping = path->channel_mapping;
1771                                 link->chip_caps = path->caps;
1772                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1773                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1774                         }
1775
1776                         if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
1777                                 link->bios_forced_drive_settings.VOLTAGE_SWING =
1778                                                 (info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
1779                                 link->bios_forced_drive_settings.PRE_EMPHASIS =
1780                                                 ((info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
1781                         }
1782
1783                         break;
1784                 }
1785         }
1786
1787         if (bios->funcs->get_atom_dc_golden_table)
1788                 bios->funcs->get_atom_dc_golden_table(bios);
1789
1790         /*
1791          * TODO check if GPIO programmed correctly
1792          *
1793          * If GPIO isn't programmed correctly HPD might not rise or drain
1794          * fast enough, leading to bounces.
1795          */
1796         program_hpd_filter(link);
1797
1798         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1799
1800         DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1801         kfree(info);
1802         return true;
1803 device_tag_fail:
1804         link->link_enc->funcs->destroy(&link->link_enc);
1805 link_enc_create_fail:
1806         if (link->panel_cntl != NULL)
1807                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1808 panel_cntl_create_fail:
1809         dal_ddc_service_destroy(&link->ddc);
1810 ddc_create_fail:
1811 create_fail:
1812
1813         if (link->hpd_gpio) {
1814                 dal_gpio_destroy_irq(&link->hpd_gpio);
1815                 link->hpd_gpio = NULL;
1816         }
1817
1818         DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1819         kfree(info);
1820
1821         return false;
1822 }
1823
1824 static bool dc_link_construct_dpia(struct dc_link *link,
1825                                    const struct link_init_data *init_params)
1826 {
1827         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1828         struct dc_context *dc_ctx = init_params->ctx;
1829
1830         DC_LOGGER_INIT(dc_ctx->logger);
1831
1832         /* Initialized irq source for hpd and hpd rx */
1833         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1834         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1835         link->link_status.dpcd_caps = &link->dpcd_caps;
1836
1837         link->dc = init_params->dc;
1838         link->ctx = dc_ctx;
1839         link->link_index = init_params->link_index;
1840
1841         memset(&link->preferred_training_settings, 0,
1842                sizeof(struct dc_link_training_overrides));
1843         memset(&link->preferred_link_setting, 0,
1844                sizeof(struct dc_link_settings));
1845
1846         /* Dummy Init for linkid */
1847         link->link_id.type = OBJECT_TYPE_CONNECTOR;
1848         link->link_id.id = CONNECTOR_ID_DISPLAY_PORT;
1849         link->link_id.enum_id = ENUM_ID_1 + init_params->connector_index;
1850         link->is_internal_display = false;
1851         link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1852         LINK_INFO("Connector[%d] description:signal %d\n",
1853                   init_params->connector_index,
1854                   link->connector_signal);
1855
1856         link->ep_type = DISPLAY_ENDPOINT_USB4_DPIA;
1857         link->is_dig_mapping_flexible = true;
1858
1859         /* TODO: Initialize link : funcs->link_init */
1860
1861         ddc_service_init_data.ctx = link->ctx;
1862         ddc_service_init_data.id = link->link_id;
1863         ddc_service_init_data.link = link;
1864         /* Set indicator for dpia link so that ddc won't be created */
1865         ddc_service_init_data.is_dpia_link = true;
1866
1867         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1868         if (!link->ddc) {
1869                 DC_ERROR("Failed to create ddc_service!\n");
1870                 goto ddc_create_fail;
1871         }
1872
1873         /* Set dpia port index : 0 to number of dpia ports */
1874         link->ddc_hw_inst = init_params->connector_index;
1875
1876         /* TODO: Create link encoder */
1877
1878         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1879
1880         /* Some docks seem to NAK I2C writes to segment pointer with mot=0. */
1881         link->wa_flags.dp_mot_reset_segment = true;
1882
1883         return true;
1884
1885 ddc_create_fail:
1886         return false;
1887 }
1888
1889 static bool dc_link_construct(struct dc_link *link,
1890                               const struct link_init_data *init_params)
1891 {
1892         /* Handle dpia case */
1893         if (init_params->is_dpia_link)
1894                 return dc_link_construct_dpia(link, init_params);
1895         else
1896                 return dc_link_construct_legacy(link, init_params);
1897 }
1898 /*******************************************************************************
1899  * Public functions
1900  ******************************************************************************/
1901 struct dc_link *link_create(const struct link_init_data *init_params)
1902 {
1903         struct dc_link *link =
1904                         kzalloc(sizeof(*link), GFP_KERNEL);
1905
1906         if (NULL == link)
1907                 goto alloc_fail;
1908
1909         if (false == dc_link_construct(link, init_params))
1910                 goto construct_fail;
1911
1912         /*
1913          * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
1914          * since struct preferred_link_setting won't be reset after S3.
1915          */
1916         link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
1917
1918         return link;
1919
1920 construct_fail:
1921         kfree(link);
1922
1923 alloc_fail:
1924         return NULL;
1925 }
1926
1927 void link_destroy(struct dc_link **link)
1928 {
1929         dc_link_destruct(*link);
1930         kfree(*link);
1931         *link = NULL;
1932 }
1933
1934 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1935 {
1936         struct dc_stream_state *stream = pipe_ctx->stream;
1937
1938         if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1939                 struct dc_link *link = stream->link;
1940                 union down_spread_ctrl old_downspread;
1941                 union down_spread_ctrl new_downspread;
1942
1943                 memset(&old_downspread, 0, sizeof(old_downspread));
1944
1945                 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1946                                 &old_downspread.raw, sizeof(old_downspread));
1947
1948                 new_downspread.raw = old_downspread.raw;
1949
1950                 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1951                                 (stream->ignore_msa_timing_param) ? 1 : 0;
1952
1953                 if (new_downspread.raw != old_downspread.raw) {
1954                         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1955                                 &new_downspread.raw, sizeof(new_downspread));
1956                 }
1957
1958         } else {
1959                 dm_helpers_mst_enable_stream_features(stream);
1960         }
1961 }
1962
1963 static enum dc_status enable_link_dp(struct dc_state *state,
1964                                      struct pipe_ctx *pipe_ctx)
1965 {
1966         struct dc_stream_state *stream = pipe_ctx->stream;
1967         enum dc_status status;
1968         bool skip_video_pattern;
1969         struct dc_link *link = stream->link;
1970         struct dc_link_settings link_settings = {0};
1971         bool fec_enable;
1972         int i;
1973         bool apply_seamless_boot_optimization = false;
1974         uint32_t bl_oled_enable_delay = 50; // in ms
1975         const uint32_t post_oui_delay = 30; // 30ms
1976         /* Reduce link bandwidth between failed link training attempts. */
1977         bool do_fallback = false;
1978
1979         // check for seamless boot
1980         for (i = 0; i < state->stream_count; i++) {
1981                 if (state->streams[i]->apply_seamless_boot_optimization) {
1982                         apply_seamless_boot_optimization = true;
1983                         break;
1984                 }
1985         }
1986
1987         /* get link settings for video mode timing */
1988         decide_link_settings(stream, &link_settings);
1989
1990         /* Train with fallback when enabling DPIA link. Conventional links are
1991          * trained with fallback during sink detection.
1992          */
1993         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1994                 do_fallback = true;
1995
1996         /*
1997          * Temporary w/a to get DP2.0 link rates to work with SST.
1998          * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved.
1999          */
2000         if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING &&
2001                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
2002                         link->dc->debug.set_mst_en_for_sst) {
2003                 dp_enable_mst_on_sink(link, true);
2004         }
2005
2006         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
2007                 /*in case it is not on*/
2008                 if (!link->dc->config.edp_no_power_sequencing)
2009                         link->dc->hwss.edp_power_control(link, true);
2010                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
2011         }
2012
2013         if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING) {
2014                 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
2015         } else {
2016                 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
2017                                 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
2018                 if (state->clk_mgr && !apply_seamless_boot_optimization)
2019                         state->clk_mgr->funcs->update_clocks(state->clk_mgr,
2020                                         state, false);
2021         }
2022
2023         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
2024         dpcd_set_source_specific_data(link);
2025         if (link->dpcd_sink_ext_caps.raw != 0)
2026                 msleep(post_oui_delay);
2027
2028         // similarly, mode switch can cause loss of cable ID
2029         dpcd_write_cable_id_to_dprx(link);
2030
2031         skip_video_pattern = true;
2032
2033         if (link_settings.link_rate == LINK_RATE_LOW)
2034                 skip_video_pattern = false;
2035
2036         if (perform_link_training_with_retries(&link_settings,
2037                                                skip_video_pattern,
2038                                                LINK_TRAINING_ATTEMPTS,
2039                                                pipe_ctx,
2040                                                pipe_ctx->stream->signal,
2041                                                do_fallback)) {
2042                 link->cur_link_settings = link_settings;
2043                 status = DC_OK;
2044         } else {
2045                 status = DC_FAIL_DP_LINK_TRAINING;
2046         }
2047
2048         if (link->preferred_training_settings.fec_enable)
2049                 fec_enable = *link->preferred_training_settings.fec_enable;
2050         else
2051                 fec_enable = true;
2052
2053         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING)
2054                 dp_set_fec_enable(link, fec_enable);
2055
2056         // during mode set we do DP_SET_POWER off then on, aux writes are lost
2057         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
2058                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
2059                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
2060                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
2061                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
2062                         msleep(bl_oled_enable_delay);
2063                 dc_link_backlight_enable_aux(link, true);
2064         }
2065
2066         return status;
2067 }
2068
2069 static enum dc_status enable_link_edp(
2070                 struct dc_state *state,
2071                 struct pipe_ctx *pipe_ctx)
2072 {
2073         enum dc_status status;
2074
2075         status = enable_link_dp(state, pipe_ctx);
2076
2077         return status;
2078 }
2079
2080 static enum dc_status enable_link_dp_mst(
2081                 struct dc_state *state,
2082                 struct pipe_ctx *pipe_ctx)
2083 {
2084         struct dc_link *link = pipe_ctx->stream->link;
2085
2086         /* sink signal type after MST branch is MST. Multiple MST sinks
2087          * share one link. Link DP PHY is enable or training only once.
2088          */
2089         if (link->link_status.link_active)
2090                 return DC_OK;
2091
2092         /* clear payload table */
2093         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
2094
2095         /* to make sure the pending down rep can be processed
2096          * before enabling the link
2097          */
2098         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
2099
2100         /* set the sink to MST mode before enabling the link */
2101         dp_enable_mst_on_sink(link, true);
2102
2103         return enable_link_dp(state, pipe_ctx);
2104 }
2105
2106 void dc_link_blank_all_dp_displays(struct dc *dc)
2107 {
2108         unsigned int i;
2109         uint8_t dpcd_power_state = '\0';
2110         enum dc_status status = DC_ERROR_UNEXPECTED;
2111
2112         for (i = 0; i < dc->link_count; i++) {
2113                 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) ||
2114                         (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL))
2115                         continue;
2116
2117                 /* DP 2.0 spec requires that we read LTTPR caps first */
2118                 dp_retrieve_lttpr_cap(dc->links[i]);
2119                 /* if any of the displays are lit up turn them off */
2120                 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
2121                                                         &dpcd_power_state, sizeof(dpcd_power_state));
2122
2123                 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
2124                         dc_link_blank_dp_stream(dc->links[i], true);
2125         }
2126
2127 }
2128
2129 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init)
2130 {
2131         unsigned int j;
2132         struct dc  *dc = link->ctx->dc;
2133         enum signal_type signal = link->connector_signal;
2134
2135         if ((signal == SIGNAL_TYPE_EDP) ||
2136                 (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
2137                 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
2138                         link->link_enc->funcs->get_dig_frontend &&
2139                         link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
2140                         unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2141
2142                         if (fe != ENGINE_ID_UNKNOWN)
2143                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
2144                                         if (fe == dc->res_pool->stream_enc[j]->id) {
2145                                                 dc->res_pool->stream_enc[j]->funcs->dp_blank(link,
2146                                                                         dc->res_pool->stream_enc[j]);
2147                                                 break;
2148                                         }
2149                                 }
2150                 }
2151
2152                 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)
2153                         dp_receiver_power_ctrl(link, false);
2154         }
2155 }
2156
2157 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
2158                 enum engine_id eng_id,
2159                 struct ext_hdmi_settings *settings)
2160 {
2161         bool result = false;
2162         int i = 0;
2163         struct integrated_info *integrated_info =
2164                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
2165
2166         if (integrated_info == NULL)
2167                 return false;
2168
2169         /*
2170          * Get retimer settings from sbios for passing SI eye test for DCE11
2171          * The setting values are varied based on board revision and port id
2172          * Therefore the setting values of each ports is passed by sbios.
2173          */
2174
2175         // Check if current bios contains ext Hdmi settings
2176         if (integrated_info->gpu_cap_info & 0x20) {
2177                 switch (eng_id) {
2178                 case ENGINE_ID_DIGA:
2179                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
2180                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
2181                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
2182                         memmove(settings->reg_settings,
2183                                         integrated_info->dp0_ext_hdmi_reg_settings,
2184                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
2185                         memmove(settings->reg_settings_6g,
2186                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
2187                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
2188                         result = true;
2189                         break;
2190                 case ENGINE_ID_DIGB:
2191                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
2192                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
2193                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
2194                         memmove(settings->reg_settings,
2195                                         integrated_info->dp1_ext_hdmi_reg_settings,
2196                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
2197                         memmove(settings->reg_settings_6g,
2198                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
2199                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
2200                         result = true;
2201                         break;
2202                 case ENGINE_ID_DIGC:
2203                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
2204                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
2205                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
2206                         memmove(settings->reg_settings,
2207                                         integrated_info->dp2_ext_hdmi_reg_settings,
2208                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
2209                         memmove(settings->reg_settings_6g,
2210                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
2211                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
2212                         result = true;
2213                         break;
2214                 case ENGINE_ID_DIGD:
2215                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
2216                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
2217                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
2218                         memmove(settings->reg_settings,
2219                                         integrated_info->dp3_ext_hdmi_reg_settings,
2220                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
2221                         memmove(settings->reg_settings_6g,
2222                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
2223                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
2224                         result = true;
2225                         break;
2226                 default:
2227                         break;
2228                 }
2229
2230                 if (result == true) {
2231                         // Validate settings from bios integrated info table
2232                         if (settings->slv_addr == 0)
2233                                 return false;
2234                         if (settings->reg_num > 9)
2235                                 return false;
2236                         if (settings->reg_num_6g > 3)
2237                                 return false;
2238
2239                         for (i = 0; i < settings->reg_num; i++) {
2240                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
2241                                         return false;
2242                         }
2243
2244                         for (i = 0; i < settings->reg_num_6g; i++) {
2245                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
2246                                         return false;
2247                         }
2248                 }
2249         }
2250
2251         return result;
2252 }
2253
2254 static bool i2c_write(struct pipe_ctx *pipe_ctx,
2255                 uint8_t address, uint8_t *buffer, uint32_t length)
2256 {
2257         struct i2c_command cmd = {0};
2258         struct i2c_payload payload = {0};
2259
2260         memset(&payload, 0, sizeof(payload));
2261         memset(&cmd, 0, sizeof(cmd));
2262
2263         cmd.number_of_payloads = 1;
2264         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
2265         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
2266
2267         payload.address = address;
2268         payload.data = buffer;
2269         payload.length = length;
2270         payload.write = true;
2271         cmd.payloads = &payload;
2272
2273         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
2274                         pipe_ctx->stream->link, &cmd))
2275                 return true;
2276
2277         return false;
2278 }
2279
2280 static void write_i2c_retimer_setting(
2281                 struct pipe_ctx *pipe_ctx,
2282                 bool is_vga_mode,
2283                 bool is_over_340mhz,
2284                 struct ext_hdmi_settings *settings)
2285 {
2286         uint8_t slave_address = (settings->slv_addr >> 1);
2287         uint8_t buffer[2];
2288         const uint8_t apply_rx_tx_change = 0x4;
2289         uint8_t offset = 0xA;
2290         uint8_t value = 0;
2291         int i = 0;
2292         bool i2c_success = false;
2293         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2294
2295         memset(&buffer, 0, sizeof(buffer));
2296
2297         /* Start Ext-Hdmi programming*/
2298
2299         for (i = 0; i < settings->reg_num; i++) {
2300                 /* Apply 3G settings */
2301                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2302
2303                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
2304                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
2305                         i2c_success = i2c_write(pipe_ctx, slave_address,
2306                                                 buffer, sizeof(buffer));
2307                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2308                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2309                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2310
2311                         if (!i2c_success)
2312                                 goto i2c_write_fail;
2313
2314                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2315                          * needs to be set to 1 on every 0xA-0xC write.
2316                          */
2317                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
2318                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
2319                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
2320
2321                                 /* Query current value from offset 0xA */
2322                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
2323                                         value = settings->reg_settings[i].i2c_reg_val;
2324                                 else {
2325                                         i2c_success =
2326                                                 dal_ddc_service_query_ddc_data(
2327                                                 pipe_ctx->stream->link->ddc,
2328                                                 slave_address, &offset, 1, &value, 1);
2329                                         if (!i2c_success)
2330                                                 goto i2c_write_fail;
2331                                 }
2332
2333                                 buffer[0] = offset;
2334                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2335                                 buffer[1] = value | apply_rx_tx_change;
2336                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2337                                                 buffer, sizeof(buffer));
2338                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2339                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2340                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2341                                 if (!i2c_success)
2342                                         goto i2c_write_fail;
2343                         }
2344                 }
2345         }
2346
2347         /* Apply 3G settings */
2348         if (is_over_340mhz) {
2349                 for (i = 0; i < settings->reg_num_6g; i++) {
2350                         /* Apply 3G settings */
2351                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2352
2353                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2354                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2355                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2356                                                         buffer, sizeof(buffer));
2357                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2358                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2359                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2360
2361                                 if (!i2c_success)
2362                                         goto i2c_write_fail;
2363
2364                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2365                                  * needs to be set to 1 on every 0xA-0xC write.
2366                                  */
2367                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2368                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2369                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2370
2371                                         /* Query current value from offset 0xA */
2372                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2373                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
2374                                         else {
2375                                                 i2c_success =
2376                                                                 dal_ddc_service_query_ddc_data(
2377                                                                 pipe_ctx->stream->link->ddc,
2378                                                                 slave_address, &offset, 1, &value, 1);
2379                                                 if (!i2c_success)
2380                                                         goto i2c_write_fail;
2381                                         }
2382
2383                                         buffer[0] = offset;
2384                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
2385                                         buffer[1] = value | apply_rx_tx_change;
2386                                         i2c_success = i2c_write(pipe_ctx, slave_address,
2387                                                         buffer, sizeof(buffer));
2388                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2389                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2390                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2391                                         if (!i2c_success)
2392                                                 goto i2c_write_fail;
2393                                 }
2394                         }
2395                 }
2396         }
2397
2398         if (is_vga_mode) {
2399                 /* Program additional settings if using 640x480 resolution */
2400
2401                 /* Write offset 0xFF to 0x01 */
2402                 buffer[0] = 0xff;
2403                 buffer[1] = 0x01;
2404                 i2c_success = i2c_write(pipe_ctx, slave_address,
2405                                 buffer, sizeof(buffer));
2406                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2407                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2408                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2409                 if (!i2c_success)
2410                         goto i2c_write_fail;
2411
2412                 /* Write offset 0x00 to 0x23 */
2413                 buffer[0] = 0x00;
2414                 buffer[1] = 0x23;
2415                 i2c_success = i2c_write(pipe_ctx, slave_address,
2416                                 buffer, sizeof(buffer));
2417                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2418                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2419                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2420                 if (!i2c_success)
2421                         goto i2c_write_fail;
2422
2423                 /* Write offset 0xff to 0x00 */
2424                 buffer[0] = 0xff;
2425                 buffer[1] = 0x00;
2426                 i2c_success = i2c_write(pipe_ctx, slave_address,
2427                                 buffer, sizeof(buffer));
2428                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2429                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2430                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2431                 if (!i2c_success)
2432                         goto i2c_write_fail;
2433
2434         }
2435
2436         return;
2437
2438 i2c_write_fail:
2439         DC_LOG_DEBUG("Set retimer failed");
2440 }
2441
2442 static void write_i2c_default_retimer_setting(
2443                 struct pipe_ctx *pipe_ctx,
2444                 bool is_vga_mode,
2445                 bool is_over_340mhz)
2446 {
2447         uint8_t slave_address = (0xBA >> 1);
2448         uint8_t buffer[2];
2449         bool i2c_success = false;
2450         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2451
2452         memset(&buffer, 0, sizeof(buffer));
2453
2454         /* Program Slave Address for tuning single integrity */
2455         /* Write offset 0x0A to 0x13 */
2456         buffer[0] = 0x0A;
2457         buffer[1] = 0x13;
2458         i2c_success = i2c_write(pipe_ctx, slave_address,
2459                         buffer, sizeof(buffer));
2460         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2461                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2462                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2463         if (!i2c_success)
2464                 goto i2c_write_fail;
2465
2466         /* Write offset 0x0A to 0x17 */
2467         buffer[0] = 0x0A;
2468         buffer[1] = 0x17;
2469         i2c_success = i2c_write(pipe_ctx, slave_address,
2470                         buffer, sizeof(buffer));
2471         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2472                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2473                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2474         if (!i2c_success)
2475                 goto i2c_write_fail;
2476
2477         /* Write offset 0x0B to 0xDA or 0xD8 */
2478         buffer[0] = 0x0B;
2479         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2480         i2c_success = i2c_write(pipe_ctx, slave_address,
2481                         buffer, sizeof(buffer));
2482         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2483                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2484                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2485         if (!i2c_success)
2486                 goto i2c_write_fail;
2487
2488         /* Write offset 0x0A to 0x17 */
2489         buffer[0] = 0x0A;
2490         buffer[1] = 0x17;
2491         i2c_success = i2c_write(pipe_ctx, slave_address,
2492                         buffer, sizeof(buffer));
2493         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2494                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2495                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2496         if (!i2c_success)
2497                 goto i2c_write_fail;
2498
2499         /* Write offset 0x0C to 0x1D or 0x91 */
2500         buffer[0] = 0x0C;
2501         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2502         i2c_success = i2c_write(pipe_ctx, slave_address,
2503                         buffer, sizeof(buffer));
2504         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2505                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2506                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2507         if (!i2c_success)
2508                 goto i2c_write_fail;
2509
2510         /* Write offset 0x0A to 0x17 */
2511         buffer[0] = 0x0A;
2512         buffer[1] = 0x17;
2513         i2c_success = i2c_write(pipe_ctx, slave_address,
2514                         buffer, sizeof(buffer));
2515         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2516                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2517                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2518         if (!i2c_success)
2519                 goto i2c_write_fail;
2520
2521
2522         if (is_vga_mode) {
2523                 /* Program additional settings if using 640x480 resolution */
2524
2525                 /* Write offset 0xFF to 0x01 */
2526                 buffer[0] = 0xff;
2527                 buffer[1] = 0x01;
2528                 i2c_success = i2c_write(pipe_ctx, slave_address,
2529                                 buffer, sizeof(buffer));
2530                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2531                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2532                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2533                 if (!i2c_success)
2534                         goto i2c_write_fail;
2535
2536                 /* Write offset 0x00 to 0x23 */
2537                 buffer[0] = 0x00;
2538                 buffer[1] = 0x23;
2539                 i2c_success = i2c_write(pipe_ctx, slave_address,
2540                                 buffer, sizeof(buffer));
2541                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2542                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2543                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2544                 if (!i2c_success)
2545                         goto i2c_write_fail;
2546
2547                 /* Write offset 0xff to 0x00 */
2548                 buffer[0] = 0xff;
2549                 buffer[1] = 0x00;
2550                 i2c_success = i2c_write(pipe_ctx, slave_address,
2551                                 buffer, sizeof(buffer));
2552                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2553                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2554                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2555                 if (!i2c_success)
2556                         goto i2c_write_fail;
2557         }
2558
2559         return;
2560
2561 i2c_write_fail:
2562         DC_LOG_DEBUG("Set default retimer failed");
2563 }
2564
2565 static void write_i2c_redriver_setting(
2566                 struct pipe_ctx *pipe_ctx,
2567                 bool is_over_340mhz)
2568 {
2569         uint8_t slave_address = (0xF0 >> 1);
2570         uint8_t buffer[16];
2571         bool i2c_success = false;
2572         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2573
2574         memset(&buffer, 0, sizeof(buffer));
2575
2576         // Program Slave Address for tuning single integrity
2577         buffer[3] = 0x4E;
2578         buffer[4] = 0x4E;
2579         buffer[5] = 0x4E;
2580         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2581
2582         i2c_success = i2c_write(pipe_ctx, slave_address,
2583                                         buffer, sizeof(buffer));
2584         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2585                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2586                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2587                 i2c_success = %d\n",
2588                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2589
2590         if (!i2c_success)
2591                 DC_LOG_DEBUG("Set redriver failed");
2592 }
2593
2594 static void disable_link(struct dc_link *link, const struct link_resource *link_res,
2595                 enum signal_type signal)
2596 {
2597         /*
2598          * TODO: implement call for dp_set_hw_test_pattern
2599          * it is needed for compliance testing
2600          */
2601
2602         /* Here we need to specify that encoder output settings
2603          * need to be calculated as for the set mode,
2604          * it will lead to querying dynamic link capabilities
2605          * which should be done before enable output
2606          */
2607
2608         if (dc_is_dp_signal(signal)) {
2609                 /* SST DP, eDP */
2610                 struct dc_link_settings link_settings = link->cur_link_settings;
2611                 if (dc_is_dp_sst_signal(signal))
2612                         dp_disable_link_phy(link, link_res, signal);
2613                 else
2614                         dp_disable_link_phy_mst(link, link_res, signal);
2615
2616                 if (dc_is_dp_sst_signal(signal) ||
2617                                 link->mst_stream_alloc_table.stream_count == 0) {
2618                         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
2619                                 dp_set_fec_enable(link, false);
2620                                 dp_set_fec_ready(link, link_res, false);
2621                         }
2622                 }
2623         } else {
2624                 if (signal != SIGNAL_TYPE_VIRTUAL)
2625                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2626         }
2627
2628         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2629                 /* MST disable link only when no stream use the link */
2630                 if (link->mst_stream_alloc_table.stream_count <= 0)
2631                         link->link_status.link_active = false;
2632         } else {
2633                 link->link_status.link_active = false;
2634         }
2635 }
2636
2637 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2638 {
2639         struct dc_stream_state *stream = pipe_ctx->stream;
2640         struct dc_link *link = stream->link;
2641         enum dc_color_depth display_color_depth;
2642         enum engine_id eng_id;
2643         struct ext_hdmi_settings settings = {0};
2644         bool is_over_340mhz = false;
2645         bool is_vga_mode = (stream->timing.h_addressable == 640)
2646                         && (stream->timing.v_addressable == 480);
2647
2648         if (stream->phy_pix_clk == 0)
2649                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2650         if (stream->phy_pix_clk > 340000)
2651                 is_over_340mhz = true;
2652
2653         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2654                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2655                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2656                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2657                         /* DP159, Retimer settings */
2658                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2659
2660                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2661                                 write_i2c_retimer_setting(pipe_ctx,
2662                                                 is_vga_mode, is_over_340mhz, &settings);
2663                         } else {
2664                                 write_i2c_default_retimer_setting(pipe_ctx,
2665                                                 is_vga_mode, is_over_340mhz);
2666                         }
2667                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2668                         /* PI3EQX1204, Redriver settings */
2669                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2670                 }
2671         }
2672
2673         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2674                 dal_ddc_service_write_scdc_data(
2675                         stream->link->ddc,
2676                         stream->phy_pix_clk,
2677                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2678
2679         memset(&stream->link->cur_link_settings, 0,
2680                         sizeof(struct dc_link_settings));
2681
2682         display_color_depth = stream->timing.display_color_depth;
2683         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2684                 display_color_depth = COLOR_DEPTH_888;
2685
2686         link->link_enc->funcs->enable_tmds_output(
2687                         link->link_enc,
2688                         pipe_ctx->clock_source->id,
2689                         display_color_depth,
2690                         pipe_ctx->stream->signal,
2691                         stream->phy_pix_clk);
2692
2693         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2694                 dal_ddc_service_read_scdc_data(link->ddc);
2695 }
2696
2697 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2698 {
2699         struct dc_stream_state *stream = pipe_ctx->stream;
2700         struct dc_link *link = stream->link;
2701
2702         if (stream->phy_pix_clk == 0)
2703                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2704
2705         memset(&stream->link->cur_link_settings, 0,
2706                         sizeof(struct dc_link_settings));
2707
2708         link->link_enc->funcs->enable_lvds_output(
2709                         link->link_enc,
2710                         pipe_ctx->clock_source->id,
2711                         stream->phy_pix_clk);
2712
2713 }
2714
2715 /****************************enable_link***********************************/
2716 static enum dc_status enable_link(
2717                 struct dc_state *state,
2718                 struct pipe_ctx *pipe_ctx)
2719 {
2720         enum dc_status status = DC_ERROR_UNEXPECTED;
2721         struct dc_stream_state *stream = pipe_ctx->stream;
2722         struct dc_link *link = stream->link;
2723
2724         /* There's some scenarios where driver is unloaded with display
2725          * still enabled. When driver is reloaded, it may cause a display
2726          * to not light up if there is a mismatch between old and new
2727          * link settings. Need to call disable first before enabling at
2728          * new link settings.
2729          */
2730         if (link->link_status.link_active) {
2731                 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
2732         }
2733
2734         switch (pipe_ctx->stream->signal) {
2735         case SIGNAL_TYPE_DISPLAY_PORT:
2736                 status = enable_link_dp(state, pipe_ctx);
2737                 break;
2738         case SIGNAL_TYPE_EDP:
2739                 status = enable_link_edp(state, pipe_ctx);
2740                 break;
2741         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2742                 status = enable_link_dp_mst(state, pipe_ctx);
2743                 msleep(200);
2744                 break;
2745         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2746         case SIGNAL_TYPE_DVI_DUAL_LINK:
2747         case SIGNAL_TYPE_HDMI_TYPE_A:
2748                 enable_link_hdmi(pipe_ctx);
2749                 status = DC_OK;
2750                 break;
2751         case SIGNAL_TYPE_LVDS:
2752                 enable_link_lvds(pipe_ctx);
2753                 status = DC_OK;
2754                 break;
2755         case SIGNAL_TYPE_VIRTUAL:
2756                 status = DC_OK;
2757                 break;
2758         default:
2759                 break;
2760         }
2761
2762         if (status == DC_OK)
2763                 pipe_ctx->stream->link->link_status.link_active = true;
2764
2765         return status;
2766 }
2767
2768 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2769 {
2770
2771         uint32_t pxl_clk = timing->pix_clk_100hz;
2772
2773         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2774                 pxl_clk /= 2;
2775         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2776                 pxl_clk = pxl_clk * 2 / 3;
2777
2778         if (timing->display_color_depth == COLOR_DEPTH_101010)
2779                 pxl_clk = pxl_clk * 10 / 8;
2780         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2781                 pxl_clk = pxl_clk * 12 / 8;
2782
2783         return pxl_clk;
2784 }
2785
2786 static bool dp_active_dongle_validate_timing(
2787                 const struct dc_crtc_timing *timing,
2788                 const struct dpcd_caps *dpcd_caps)
2789 {
2790         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2791
2792         switch (dpcd_caps->dongle_type) {
2793         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2794         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2795         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2796                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2797                         return true;
2798                 else
2799                         return false;
2800         default:
2801                 break;
2802         }
2803
2804         if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
2805                         dongle_caps->extendedCapValid == true) {
2806                 /* Check Pixel Encoding */
2807                 switch (timing->pixel_encoding) {
2808                 case PIXEL_ENCODING_RGB:
2809                 case PIXEL_ENCODING_YCBCR444:
2810                         break;
2811                 case PIXEL_ENCODING_YCBCR422:
2812                         if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2813                                 return false;
2814                         break;
2815                 case PIXEL_ENCODING_YCBCR420:
2816                         if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2817                                 return false;
2818                         break;
2819                 default:
2820                         /* Invalid Pixel Encoding*/
2821                         return false;
2822                 }
2823
2824                 switch (timing->display_color_depth) {
2825                 case COLOR_DEPTH_666:
2826                 case COLOR_DEPTH_888:
2827                         /*888 and 666 should always be supported*/
2828                         break;
2829                 case COLOR_DEPTH_101010:
2830                         if (dongle_caps->dp_hdmi_max_bpc < 10)
2831                                 return false;
2832                         break;
2833                 case COLOR_DEPTH_121212:
2834                         if (dongle_caps->dp_hdmi_max_bpc < 12)
2835                                 return false;
2836                         break;
2837                 case COLOR_DEPTH_141414:
2838                 case COLOR_DEPTH_161616:
2839                 default:
2840                         /* These color depths are currently not supported */
2841                         return false;
2842                 }
2843
2844                 /* Check 3D format */
2845                 switch (timing->timing_3d_format) {
2846                 case TIMING_3D_FORMAT_NONE:
2847                 case TIMING_3D_FORMAT_FRAME_ALTERNATE:
2848                         /*Only frame alternate 3D is supported on active dongle*/
2849                         break;
2850                 default:
2851                         /*other 3D formats are not supported due to bad infoframe translation */
2852                         return false;
2853                 }
2854
2855 #if defined(CONFIG_DRM_AMD_DC_DCN)
2856                 if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter
2857                         struct dc_crtc_timing outputTiming = *timing;
2858
2859                         if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
2860                                 /* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */
2861                                 outputTiming.flags.DSC = 0;
2862                         if (dc_bandwidth_in_kbps_from_timing(&outputTiming) > dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
2863                                 return false;
2864                 } else { // DP to HDMI TMDS converter
2865                         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2866                                 return false;
2867                 }
2868 #else
2869                 if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2870                         return false;
2871 #endif
2872         }
2873
2874         if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
2875                         dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
2876                         dongle_caps->dfp_cap_ext.supported) {
2877
2878                 if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
2879                         return false;
2880
2881                 if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
2882                         return false;
2883
2884                 if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
2885                         return false;
2886
2887                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
2888                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2889                                 return false;
2890                         if (timing->display_color_depth == COLOR_DEPTH_666 &&
2891                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
2892                                 return false;
2893                         else if (timing->display_color_depth == COLOR_DEPTH_888 &&
2894                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
2895                                 return false;
2896                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2897                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
2898                                 return false;
2899                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2900                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
2901                                 return false;
2902                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2903                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
2904                                 return false;
2905                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
2906                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2907                                 return false;
2908                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2909                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
2910                                 return false;
2911                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2912                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
2913                                 return false;
2914                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2915                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
2916                                 return false;
2917                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2918                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
2919                                 return false;
2920                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
2921                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2922                                 return false;
2923                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2924                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
2925                                 return false;
2926                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2927                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
2928                                 return false;
2929                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2930                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
2931                                 return false;
2932                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2933                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
2934                                 return false;
2935                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2936                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2937                                 return false;
2938                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2939                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
2940                                 return false;
2941                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2942                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
2943                                 return false;
2944                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2945                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
2946                                 return false;
2947                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2948                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
2949                                 return false;
2950                 }
2951         }
2952
2953         return true;
2954 }
2955
2956 enum dc_status dc_link_validate_mode_timing(
2957                 const struct dc_stream_state *stream,
2958                 struct dc_link *link,
2959                 const struct dc_crtc_timing *timing)
2960 {
2961         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2962         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2963
2964         /* A hack to avoid failing any modes for EDID override feature on
2965          * topology change such as lower quality cable for DP or different dongle
2966          */
2967         if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2968                 return DC_OK;
2969
2970         /* Passive Dongle */
2971         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2972                 return DC_EXCEED_DONGLE_CAP;
2973
2974         /* Active Dongle*/
2975         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2976                 return DC_EXCEED_DONGLE_CAP;
2977
2978         switch (stream->signal) {
2979         case SIGNAL_TYPE_EDP:
2980         case SIGNAL_TYPE_DISPLAY_PORT:
2981                 if (!dp_validate_mode_timing(
2982                                 link,
2983                                 timing))
2984                         return DC_NO_DP_LINK_BANDWIDTH;
2985                 break;
2986
2987         default:
2988                 break;
2989         }
2990
2991         return DC_OK;
2992 }
2993
2994 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2995 {
2996         int i;
2997         struct dc *dc = NULL;
2998         struct abm *abm = NULL;
2999
3000         if (!link || !link->ctx)
3001                 return NULL;
3002
3003         dc = link->ctx->dc;
3004
3005         for (i = 0; i < MAX_PIPES; i++) {
3006                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
3007                 struct dc_stream_state *stream = pipe_ctx.stream;
3008
3009                 if (stream && stream->link == link) {
3010                         abm = pipe_ctx.stream_res.abm;
3011                         break;
3012                 }
3013         }
3014         return abm;
3015 }
3016
3017 int dc_link_get_backlight_level(const struct dc_link *link)
3018 {
3019         struct abm *abm = get_abm_from_stream_res(link);
3020         struct panel_cntl *panel_cntl = link->panel_cntl;
3021         struct dc  *dc = link->ctx->dc;
3022         struct dmcu *dmcu = dc->res_pool->dmcu;
3023         bool fw_set_brightness = true;
3024
3025         if (dmcu)
3026                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
3027
3028         if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
3029                 return panel_cntl->funcs->get_current_backlight(panel_cntl);
3030         else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
3031                 return (int) abm->funcs->get_current_backlight(abm);
3032         else
3033                 return DC_ERROR_UNEXPECTED;
3034 }
3035
3036 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
3037 {
3038         struct abm *abm = get_abm_from_stream_res(link);
3039
3040         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
3041                 return DC_ERROR_UNEXPECTED;
3042
3043         return (int) abm->funcs->get_target_backlight(abm);
3044 }
3045
3046 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
3047 {
3048         int i;
3049         struct dc *dc = link->ctx->dc;
3050         struct pipe_ctx *pipe_ctx = NULL;
3051
3052         for (i = 0; i < MAX_PIPES; i++) {
3053                 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
3054                         if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
3055                                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
3056                                 break;
3057                         }
3058                 }
3059         }
3060
3061         return pipe_ctx;
3062 }
3063
3064 bool dc_link_set_backlight_level(const struct dc_link *link,
3065                 uint32_t backlight_pwm_u16_16,
3066                 uint32_t frame_ramp)
3067 {
3068         struct dc  *dc = link->ctx->dc;
3069
3070         DC_LOGGER_INIT(link->ctx->logger);
3071         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
3072                         backlight_pwm_u16_16, backlight_pwm_u16_16);
3073
3074         if (dc_is_embedded_signal(link->connector_signal)) {
3075                 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
3076
3077                 if (pipe_ctx) {
3078                         /* Disable brightness ramping when the display is blanked
3079                          * as it can hang the DMCU
3080                          */
3081                         if (pipe_ctx->plane_state == NULL)
3082                                 frame_ramp = 0;
3083                 } else {
3084                         return false;
3085                 }
3086
3087                 dc->hwss.set_backlight_level(
3088                                 pipe_ctx,
3089                                 backlight_pwm_u16_16,
3090                                 frame_ramp);
3091         }
3092         return true;
3093 }
3094
3095 bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
3096                 bool wait, bool force_static, const unsigned int *power_opts)
3097 {
3098         struct dc  *dc = link->ctx->dc;
3099         struct dmcu *dmcu = dc->res_pool->dmcu;
3100         struct dmub_psr *psr = dc->res_pool->psr;
3101         unsigned int panel_inst;
3102
3103         if (psr == NULL && force_static)
3104                 return false;
3105
3106         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3107                 return false;
3108
3109         if (allow_active && link->type == dc_connection_none) {
3110                 // Don't enter PSR if panel is not connected
3111                 return false;
3112         }
3113
3114         /* Set power optimization flag */
3115         if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
3116                 link->psr_settings.psr_power_opt = *power_opts;
3117
3118                 if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
3119                         psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
3120         }
3121
3122         if (psr != NULL && link->psr_settings.psr_feature_enabled &&
3123                         force_static && psr->funcs->psr_force_static)
3124                 psr->funcs->psr_force_static(psr, panel_inst);
3125
3126         /* Enable or Disable PSR */
3127         if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
3128                 link->psr_settings.psr_allow_active = *allow_active;
3129
3130                 if (!link->psr_settings.psr_allow_active)
3131                         dc_z10_restore(dc);
3132
3133                 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
3134                         psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
3135                 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
3136                         link->psr_settings.psr_feature_enabled)
3137                         dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
3138                 else
3139                         return false;
3140         }
3141
3142         return true;
3143 }
3144
3145 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
3146 {
3147         struct dc  *dc = link->ctx->dc;
3148         struct dmcu *dmcu = dc->res_pool->dmcu;
3149         struct dmub_psr *psr = dc->res_pool->psr;
3150         unsigned int panel_inst;
3151
3152         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3153                 return false;
3154
3155         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3156                 psr->funcs->psr_get_state(psr, state, panel_inst);
3157         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
3158                 dmcu->funcs->get_psr_state(dmcu, state);
3159
3160         return true;
3161 }
3162
3163 static inline enum physical_phy_id
3164 transmitter_to_phy_id(enum transmitter transmitter_value)
3165 {
3166         switch (transmitter_value) {
3167         case TRANSMITTER_UNIPHY_A:
3168                 return PHYLD_0;
3169         case TRANSMITTER_UNIPHY_B:
3170                 return PHYLD_1;
3171         case TRANSMITTER_UNIPHY_C:
3172                 return PHYLD_2;
3173         case TRANSMITTER_UNIPHY_D:
3174                 return PHYLD_3;
3175         case TRANSMITTER_UNIPHY_E:
3176                 return PHYLD_4;
3177         case TRANSMITTER_UNIPHY_F:
3178                 return PHYLD_5;
3179         case TRANSMITTER_NUTMEG_CRT:
3180                 return PHYLD_6;
3181         case TRANSMITTER_TRAVIS_CRT:
3182                 return PHYLD_7;
3183         case TRANSMITTER_TRAVIS_LCD:
3184                 return PHYLD_8;
3185         case TRANSMITTER_UNIPHY_G:
3186                 return PHYLD_9;
3187         case TRANSMITTER_COUNT:
3188                 return PHYLD_COUNT;
3189         case TRANSMITTER_UNKNOWN:
3190                 return PHYLD_UNKNOWN;
3191         default:
3192                 WARN_ONCE(1, "Unknown transmitter value %d\n",
3193                           transmitter_value);
3194                 return PHYLD_UNKNOWN;
3195         }
3196 }
3197
3198 bool dc_link_setup_psr(struct dc_link *link,
3199                 const struct dc_stream_state *stream, struct psr_config *psr_config,
3200                 struct psr_context *psr_context)
3201 {
3202         struct dc *dc;
3203         struct dmcu *dmcu;
3204         struct dmub_psr *psr;
3205         int i;
3206         unsigned int panel_inst;
3207         /* updateSinkPsrDpcdConfig*/
3208         union dpcd_psr_configuration psr_configuration;
3209         union dpcd_alpm_configuration alpm_configuration;
3210
3211         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
3212
3213         if (!link)
3214                 return false;
3215
3216         dc = link->ctx->dc;
3217         dmcu = dc->res_pool->dmcu;
3218         psr = dc->res_pool->psr;
3219
3220         if (!dmcu && !psr)
3221                 return false;
3222
3223         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3224                 return false;
3225
3226
3227         memset(&psr_configuration, 0, sizeof(psr_configuration));
3228
3229         psr_configuration.bits.ENABLE                    = 1;
3230         psr_configuration.bits.CRC_VERIFICATION          = 1;
3231         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
3232                         psr_config->psr_frame_capture_indication_req;
3233
3234         /* Check for PSR v2*/
3235         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
3236                 /* For PSR v2 selective update.
3237                  * Indicates whether sink should start capturing
3238                  * immediately following active scan line,
3239                  * or starting with the 2nd active scan line.
3240                  */
3241                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
3242                 /*For PSR v2, determines whether Sink should generate
3243                  * IRQ_HPD when CRC mismatch is detected.
3244                  */
3245                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
3246                 /* For PSR v2, set the bit when the Source device will
3247                  * be enabling PSR2 operation.
3248                  */
3249                 psr_configuration.bits.ENABLE_PSR2    = 1;
3250                 /* For PSR v2, the Sink device must be able to receive
3251                  * SU region updates early in the frame time.
3252                  */
3253                 psr_configuration.bits.EARLY_TRANSPORT_ENABLE    = 1;
3254         }
3255
3256         dm_helpers_dp_write_dpcd(
3257                 link->ctx,
3258                 link,
3259                 368,
3260                 &psr_configuration.raw,
3261                 sizeof(psr_configuration.raw));
3262
3263         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
3264                 memset(&alpm_configuration, 0, sizeof(alpm_configuration));
3265
3266                 alpm_configuration.bits.ENABLE = 1;
3267                 dm_helpers_dp_write_dpcd(
3268                         link->ctx,
3269                         link,
3270                         DP_RECEIVER_ALPM_CONFIG,
3271                         &alpm_configuration.raw,
3272                         sizeof(alpm_configuration.raw));
3273                 psr_context->su_granularity_required =
3274                         psr_config->su_granularity_required;
3275                 psr_context->su_y_granularity =
3276                         psr_config->su_y_granularity;
3277         }
3278
3279         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
3280         psr_context->transmitterId = link->link_enc->transmitter;
3281         psr_context->engineId = link->link_enc->preferred_engine;
3282
3283         for (i = 0; i < MAX_PIPES; i++) {
3284                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
3285                                 == stream) {
3286                         /* dmcu -1 for all controller id values,
3287                          * therefore +1 here
3288                          */
3289                         psr_context->controllerId =
3290                                 dc->current_state->res_ctx.
3291                                 pipe_ctx[i].stream_res.tg->inst + 1;
3292                         break;
3293                 }
3294         }
3295
3296         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
3297         psr_context->phyType = PHY_TYPE_UNIPHY;
3298         /*PhyId is associated with the transmitter id*/
3299         psr_context->smuPhyId =
3300                 transmitter_to_phy_id(link->link_enc->transmitter);
3301
3302         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
3303         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
3304                                         timing.pix_clk_100hz * 100),
3305                                         stream->timing.v_total),
3306                                         stream->timing.h_total);
3307
3308         psr_context->psrSupportedDisplayConfig = true;
3309         psr_context->psrExitLinkTrainingRequired =
3310                 psr_config->psr_exit_link_training_required;
3311         psr_context->sdpTransmitLineNumDeadline =
3312                 psr_config->psr_sdp_transmit_line_num_deadline;
3313         psr_context->psrFrameCaptureIndicationReq =
3314                 psr_config->psr_frame_capture_indication_req;
3315
3316         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
3317
3318         psr_context->numberOfControllers =
3319                         link->dc->res_pool->timing_generator_count;
3320
3321         psr_context->rfb_update_auto_en = true;
3322
3323         /* 2 frames before enter PSR. */
3324         psr_context->timehyst_frames = 2;
3325         /* half a frame
3326          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
3327          */
3328         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
3329         psr_context->aux_repeats = 10;
3330
3331         psr_context->psr_level.u32all = 0;
3332
3333         /*skip power down the single pipe since it blocks the cstate*/
3334 #if defined(CONFIG_DRM_AMD_DC_DCN)
3335         if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
3336                 switch(link->ctx->asic_id.chip_family) {
3337                 case FAMILY_YELLOW_CARP:
3338                 case AMDGPU_FAMILY_GC_10_3_6:
3339                         if(!dc->debug.disable_z10)
3340                                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
3341                         break;
3342                 default:
3343                         psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3344                         break;
3345                 }
3346         }
3347 #else
3348         if (link->ctx->asic_id.chip_family >= FAMILY_RV)
3349                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3350 #endif
3351
3352         /* SMU will perform additional powerdown sequence.
3353          * For unsupported ASICs, set psr_level flag to skip PSR
3354          *  static screen notification to SMU.
3355          *  (Always set for DAL2, did not check ASIC)
3356          */
3357         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
3358         psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
3359
3360         /* Complete PSR entry before aborting to prevent intermittent
3361          * freezes on certain eDPs
3362          */
3363         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
3364
3365         /* Controls additional delay after remote frame capture before
3366          * continuing power down, default = 0
3367          */
3368         psr_context->frame_delay = 0;
3369
3370         if (psr) {
3371                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
3372                         link, psr_context, panel_inst);
3373                 link->psr_settings.psr_power_opt = 0;
3374                 link->psr_settings.psr_allow_active = 0;
3375         }
3376         else
3377                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
3378
3379         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
3380          * should not happen since firmware should be running at this point
3381          */
3382         if (link->psr_settings.psr_feature_enabled == 0)
3383                 ASSERT(0);
3384
3385         return true;
3386
3387 }
3388
3389 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
3390 {
3391         struct dc  *dc = link->ctx->dc;
3392         struct dmub_psr *psr = dc->res_pool->psr;
3393         unsigned int panel_inst;
3394
3395         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3396                 return;
3397
3398         /* PSR residency measurements only supported on DMCUB */
3399         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3400                 psr->funcs->psr_get_residency(psr, residency, panel_inst);
3401         else
3402                 *residency = 0;
3403 }
3404
3405 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
3406 {
3407         return &link->link_status;
3408 }
3409
3410 void core_link_resume(struct dc_link *link)
3411 {
3412         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
3413                 program_hpd_filter(link);
3414 }
3415
3416 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
3417 {
3418         struct fixed31_32 mbytes_per_sec;
3419         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
3420                         &stream->link->cur_link_settings);
3421         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
3422
3423         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
3424
3425         return dc_fixpt_div_int(mbytes_per_sec, 54);
3426 }
3427
3428 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
3429 {
3430         struct fixed31_32 peak_kbps;
3431         uint32_t numerator = 0;
3432         uint32_t denominator = 1;
3433
3434         /*
3435          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
3436          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
3437          * common multiplier to render an integer PBN for all link rate/lane
3438          * counts combinations
3439          * calculate
3440          * peak_kbps *= (1006/1000)
3441          * peak_kbps *= (64/54)
3442          * peak_kbps *= 8    convert to bytes
3443          */
3444
3445         numerator = 64 * PEAK_FACTOR_X1000;
3446         denominator = 54 * 8 * 1000 * 1000;
3447         kbps *= numerator;
3448         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
3449
3450         return peak_kbps;
3451 }
3452
3453 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
3454 {
3455         uint64_t kbps;
3456
3457         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
3458         return get_pbn_from_bw_in_kbps(kbps);
3459 }
3460
3461 static void update_mst_stream_alloc_table(
3462         struct dc_link *link,
3463         struct stream_encoder *stream_enc,
3464         struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc?
3465         const struct dp_mst_stream_allocation_table *proposed_table)
3466 {
3467         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
3468         struct link_mst_stream_allocation *dc_alloc;
3469
3470         int i;
3471         int j;
3472
3473         /* if DRM proposed_table has more than one new payload */
3474         ASSERT(proposed_table->stream_count -
3475                         link->mst_stream_alloc_table.stream_count < 2);
3476
3477         /* copy proposed_table to link, add stream encoder */
3478         for (i = 0; i < proposed_table->stream_count; i++) {
3479
3480                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
3481                         dc_alloc =
3482                         &link->mst_stream_alloc_table.stream_allocations[j];
3483
3484                         if (dc_alloc->vcp_id ==
3485                                 proposed_table->stream_allocations[i].vcp_id) {
3486
3487                                 work_table[i] = *dc_alloc;
3488                                 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
3489                                 break; /* exit j loop */
3490                         }
3491                 }
3492
3493                 /* new vcp_id */
3494                 if (j == link->mst_stream_alloc_table.stream_count) {
3495                         work_table[i].vcp_id =
3496                                 proposed_table->stream_allocations[i].vcp_id;
3497                         work_table[i].slot_count =
3498                                 proposed_table->stream_allocations[i].slot_count;
3499                         work_table[i].stream_enc = stream_enc;
3500                         work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc;
3501                 }
3502         }
3503
3504         /* update link->mst_stream_alloc_table with work_table */
3505         link->mst_stream_alloc_table.stream_count =
3506                         proposed_table->stream_count;
3507         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
3508                 link->mst_stream_alloc_table.stream_allocations[i] =
3509                                 work_table[i];
3510 }
3511
3512 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
3513 {
3514         const uint32_t VCP_Y_PRECISION = 1000;
3515         uint64_t vcp_x, vcp_y;
3516
3517         // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
3518         avg_time_slots_per_mtp = dc_fixpt_add(
3519                         avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));
3520
3521         vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
3522         vcp_y = dc_fixpt_floor(
3523                         dc_fixpt_mul_int(
3524                                 dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
3525                                 VCP_Y_PRECISION));
3526
3527         if (link->type == dc_connection_mst_branch)
3528                 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
3529                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3530         else
3531                 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
3532                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3533 }
3534
3535 /*
3536  * Payload allocation/deallocation for SST introduced in DP2.0
3537  */
3538 static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
3539                                                  bool allocate)
3540 {
3541         struct dc_stream_state *stream = pipe_ctx->stream;
3542         struct dc_link *link = stream->link;
3543         struct link_mst_stream_allocation_table proposed_table = {0};
3544         struct fixed31_32 avg_time_slots_per_mtp;
3545         const struct dc_link_settings empty_link_settings = {0};
3546         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3547         DC_LOGGER_INIT(link->ctx->logger);
3548
3549         /* slot X.Y for SST payload deallocate */
3550         if (!allocate) {
3551                 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3552
3553                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3554
3555                 if (link_hwss->ext.set_throttled_vcp_size)
3556                         link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3557                                         avg_time_slots_per_mtp);
3558                 if (link_hwss->ext.set_hblank_min_symbol_width)
3559                         link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3560                                         &empty_link_settings,
3561                                         avg_time_slots_per_mtp);
3562         }
3563
3564         /* calculate VC payload and update branch with new payload allocation table*/
3565         if (!dpcd_write_128b_132b_sst_payload_allocation_table(
3566                         stream,
3567                         link,
3568                         &proposed_table,
3569                         allocate)) {
3570                 DC_LOG_ERROR("SST Update Payload: Failed to update "
3571                                                 "allocation table for "
3572                                                 "pipe idx: %d\n",
3573                                                 pipe_ctx->pipe_idx);
3574         }
3575
3576         proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
3577
3578         ASSERT(proposed_table.stream_count == 1);
3579
3580         //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id
3581         DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p      "
3582                 "vcp_id: %d      "
3583                 "slot_count: %d\n",
3584                 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc,
3585                 proposed_table.stream_allocations[0].vcp_id,
3586                 proposed_table.stream_allocations[0].slot_count);
3587
3588         /* program DP source TX for payload */
3589         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3590                         &proposed_table);
3591
3592         /* poll for ACT handled */
3593         if (!dpcd_poll_for_allocation_change_trigger(link)) {
3594                 // Failures will result in blackscreen and errors logged
3595                 BREAK_TO_DEBUGGER();
3596         }
3597
3598         /* slot X.Y for SST payload allocate */
3599         if (allocate && dp_get_link_encoding_format(&link->cur_link_settings) ==
3600                         DP_128b_132b_ENCODING) {
3601                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
3602
3603                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3604
3605                 if (link_hwss->ext.set_throttled_vcp_size)
3606                         link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3607                                         avg_time_slots_per_mtp);
3608                 if (link_hwss->ext.set_hblank_min_symbol_width)
3609                         link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3610                                         &link->cur_link_settings,
3611                                         avg_time_slots_per_mtp);
3612         }
3613
3614         /* Always return DC_OK.
3615          * If part of sequence fails, log failure(s) and show blackscreen
3616          */
3617         return DC_OK;
3618 }
3619
3620 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
3621  * because stream_encoder is not exposed to dm
3622  */
3623 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3624 {
3625         struct dc_stream_state *stream = pipe_ctx->stream;
3626         struct dc_link *link = stream->link;
3627         struct dp_mst_stream_allocation_table proposed_table = {0};
3628         struct fixed31_32 avg_time_slots_per_mtp;
3629         struct fixed31_32 pbn;
3630         struct fixed31_32 pbn_per_slot;
3631         int i;
3632         enum act_return_status ret;
3633         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3634         DC_LOGGER_INIT(link->ctx->logger);
3635
3636         /* enable_link_dp_mst already check link->enabled_stream_count
3637          * and stream is in link->stream[]. This is called during set mode,
3638          * stream_enc is available.
3639          */
3640
3641         /* get calculate VC payload for stream: stream_alloc */
3642         if (dm_helpers_dp_mst_write_payload_allocation_table(
3643                 stream->ctx,
3644                 stream,
3645                 &proposed_table,
3646                 true))
3647                 update_mst_stream_alloc_table(
3648                                         link,
3649                                         pipe_ctx->stream_res.stream_enc,
3650                                         pipe_ctx->stream_res.hpo_dp_stream_enc,
3651                                         &proposed_table);
3652         else
3653                 DC_LOG_WARNING("Failed to update"
3654                                 "MST allocation table for"
3655                                 "pipe idx:%d\n",
3656                                 pipe_ctx->pipe_idx);
3657
3658         DC_LOG_MST("%s  "
3659                         "stream_count: %d: \n ",
3660                         __func__,
3661                         link->mst_stream_alloc_table.stream_count);
3662
3663         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3664                 DC_LOG_MST("stream_enc[%d]: %p      "
3665                 "stream[%d].hpo_dp_stream_enc: %p      "
3666                 "stream[%d].vcp_id: %d      "
3667                 "stream[%d].slot_count: %d\n",
3668                 i,
3669                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3670                 i,
3671                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3672                 i,
3673                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3674                 i,
3675                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3676         }
3677
3678         ASSERT(proposed_table.stream_count > 0);
3679
3680         /* program DP source TX for payload */
3681         if (link_hwss->ext.update_stream_allocation_table == NULL ||
3682                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3683                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3684                 return DC_ERROR_UNEXPECTED;
3685         }
3686
3687         link_hwss->ext.update_stream_allocation_table(link,
3688                         &pipe_ctx->link_res,
3689                         &link->mst_stream_alloc_table);
3690
3691         /* send down message */
3692         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3693                         stream->ctx,
3694                         stream);
3695
3696         if (ret != ACT_LINK_LOST) {
3697                 dm_helpers_dp_mst_send_payload_allocation(
3698                                 stream->ctx,
3699                                 stream,
3700                                 true);
3701         }
3702
3703         /* slot X.Y for only current stream */
3704         pbn_per_slot = get_pbn_per_slot(stream);
3705         if (pbn_per_slot.value == 0) {
3706                 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3707                 return DC_UNSUPPORTED_VALUE;
3708         }
3709         pbn = get_pbn_from_timing(pipe_ctx);
3710         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3711
3712         dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3713
3714         if (link_hwss->ext.set_throttled_vcp_size)
3715                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3716         if (link_hwss->ext.set_hblank_min_symbol_width)
3717                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3718                                 &link->cur_link_settings,
3719                                 avg_time_slots_per_mtp);
3720
3721         return DC_OK;
3722
3723 }
3724
3725 enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3726 {
3727         struct dc_stream_state *stream = pipe_ctx->stream;
3728         struct dc_link *link = stream->link;
3729         struct fixed31_32 avg_time_slots_per_mtp;
3730         struct fixed31_32 pbn;
3731         struct fixed31_32 pbn_per_slot;
3732         struct dp_mst_stream_allocation_table proposed_table = {0};
3733         uint8_t i;
3734         enum act_return_status ret;
3735         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3736         DC_LOGGER_INIT(link->ctx->logger);
3737
3738         /* decrease throttled vcp size */
3739         pbn_per_slot = get_pbn_per_slot(stream);
3740         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3741         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3742
3743         if (link_hwss->ext.set_throttled_vcp_size)
3744                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3745         if (link_hwss->ext.set_hblank_min_symbol_width)
3746                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3747                                 &link->cur_link_settings,
3748                                 avg_time_slots_per_mtp);
3749
3750         /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3751         dm_helpers_dp_mst_send_payload_allocation(
3752                         stream->ctx,
3753                         stream,
3754                         true);
3755
3756         /* notify immediate branch device table update */
3757         if (dm_helpers_dp_mst_write_payload_allocation_table(
3758                         stream->ctx,
3759                         stream,
3760                         &proposed_table,
3761                         true)) {
3762                 /* update mst stream allocation table software state */
3763                 update_mst_stream_alloc_table(
3764                                 link,
3765                                 pipe_ctx->stream_res.stream_enc,
3766                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3767                                 &proposed_table);
3768         } else {
3769                 DC_LOG_WARNING("Failed to update"
3770                                 "MST allocation table for"
3771                                 "pipe idx:%d\n",
3772                                 pipe_ctx->pipe_idx);
3773         }
3774
3775         DC_LOG_MST("%s  "
3776                         "stream_count: %d: \n ",
3777                         __func__,
3778                         link->mst_stream_alloc_table.stream_count);
3779
3780         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3781                 DC_LOG_MST("stream_enc[%d]: %p      "
3782                                 "stream[%d].vcp_id: %d      "
3783                                 "stream[%d].slot_count: %d\n",
3784                                 i,
3785                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3786                                 i,
3787                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3788                                 i,
3789                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3790         }
3791
3792         ASSERT(proposed_table.stream_count > 0);
3793
3794         /* update mst stream allocation table hardware state */
3795         if (link_hwss->ext.update_stream_allocation_table == NULL ||
3796                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3797                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3798                 return DC_ERROR_UNEXPECTED;
3799         }
3800
3801         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3802                         &link->mst_stream_alloc_table);
3803
3804         /* poll for immediate branch device ACT handled */
3805         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3806                         stream->ctx,
3807                         stream);
3808
3809         return DC_OK;
3810 }
3811
3812 enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3813 {
3814         struct dc_stream_state *stream = pipe_ctx->stream;
3815         struct dc_link *link = stream->link;
3816         struct fixed31_32 avg_time_slots_per_mtp;
3817         struct fixed31_32 pbn;
3818         struct fixed31_32 pbn_per_slot;
3819         struct link_encoder *link_encoder = link->link_enc;
3820         struct dp_mst_stream_allocation_table proposed_table = {0};
3821         uint8_t i;
3822         enum act_return_status ret;
3823         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3824         DC_LOGGER_INIT(link->ctx->logger);
3825
3826         /* notify immediate branch device table update */
3827         if (dm_helpers_dp_mst_write_payload_allocation_table(
3828                                 stream->ctx,
3829                                 stream,
3830                                 &proposed_table,
3831                                 true)) {
3832                 /* update mst stream allocation table software state */
3833                 update_mst_stream_alloc_table(
3834                                 link,
3835                                 pipe_ctx->stream_res.stream_enc,
3836                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3837                                 &proposed_table);
3838         }
3839
3840         DC_LOG_MST("%s  "
3841                         "stream_count: %d: \n ",
3842                         __func__,
3843                         link->mst_stream_alloc_table.stream_count);
3844
3845         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3846                 DC_LOG_MST("stream_enc[%d]: %p      "
3847                                 "stream[%d].vcp_id: %d      "
3848                                 "stream[%d].slot_count: %d\n",
3849                                 i,
3850                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3851                                 i,
3852                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3853                                 i,
3854                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3855         }
3856
3857         ASSERT(proposed_table.stream_count > 0);
3858
3859         /* update mst stream allocation table hardware state */
3860         link_encoder->funcs->update_mst_stream_allocation_table(
3861                         link_encoder,
3862                         &link->mst_stream_alloc_table);
3863
3864         /* poll for immediate branch device ACT handled */
3865         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3866                         stream->ctx,
3867                         stream);
3868
3869         if (ret != ACT_LINK_LOST) {
3870                 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3871                 dm_helpers_dp_mst_send_payload_allocation(
3872                                 stream->ctx,
3873                                 stream,
3874                                 true);
3875         }
3876
3877         /* increase throttled vcp size */
3878         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3879         pbn_per_slot = get_pbn_per_slot(stream);
3880         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3881
3882         if (link_hwss->ext.set_throttled_vcp_size)
3883                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3884         if (link_hwss->ext.set_hblank_min_symbol_width)
3885                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3886                                 &link->cur_link_settings,
3887                                 avg_time_slots_per_mtp);
3888
3889         return DC_OK;
3890 }
3891
3892 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3893 {
3894         struct dc_stream_state *stream = pipe_ctx->stream;
3895         struct dc_link *link = stream->link;
3896         struct dp_mst_stream_allocation_table proposed_table = {0};
3897         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3898         int i;
3899         bool mst_mode = (link->type == dc_connection_mst_branch);
3900         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3901         const struct dc_link_settings empty_link_settings = {0};
3902         DC_LOGGER_INIT(link->ctx->logger);
3903
3904         /* deallocate_mst_payload is called before disable link. When mode or
3905          * disable/enable monitor, new stream is created which is not in link
3906          * stream[] yet. For this, payload is not allocated yet, so de-alloc
3907          * should not done. For new mode set, map_resources will get engine
3908          * for new stream, so stream_enc->id should be validated until here.
3909          */
3910
3911         /* slot X.Y */
3912         if (link_hwss->ext.set_throttled_vcp_size)
3913                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3914         if (link_hwss->ext.set_hblank_min_symbol_width)
3915                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3916                                 &empty_link_settings,
3917                                 avg_time_slots_per_mtp);
3918
3919         /* TODO: which component is responsible for remove payload table? */
3920         if (mst_mode) {
3921                 if (dm_helpers_dp_mst_write_payload_allocation_table(
3922                                 stream->ctx,
3923                                 stream,
3924                                 &proposed_table,
3925                                 false)) {
3926
3927                         update_mst_stream_alloc_table(
3928                                                 link,
3929                                                 pipe_ctx->stream_res.stream_enc,
3930                                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3931                                                 &proposed_table);
3932                 }
3933                 else {
3934                                 DC_LOG_WARNING("Failed to update"
3935                                                 "MST allocation table for"
3936                                                 "pipe idx:%d\n",
3937                                                 pipe_ctx->pipe_idx);
3938                 }
3939         }
3940
3941         DC_LOG_MST("%s"
3942                         "stream_count: %d: ",
3943                         __func__,
3944                         link->mst_stream_alloc_table.stream_count);
3945
3946         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3947                 DC_LOG_MST("stream_enc[%d]: %p      "
3948                 "stream[%d].hpo_dp_stream_enc: %p      "
3949                 "stream[%d].vcp_id: %d      "
3950                 "stream[%d].slot_count: %d\n",
3951                 i,
3952                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3953                 i,
3954                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3955                 i,
3956                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3957                 i,
3958                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3959         }
3960
3961         /* update mst stream allocation table hardware state */
3962         if (link_hwss->ext.update_stream_allocation_table == NULL ||
3963                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3964                 DC_LOG_DEBUG("Unknown encoding format\n");
3965                 return DC_ERROR_UNEXPECTED;
3966         }
3967
3968         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3969                         &link->mst_stream_alloc_table);
3970
3971         if (mst_mode) {
3972                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3973                         stream->ctx,
3974                         stream);
3975
3976                 dm_helpers_dp_mst_send_payload_allocation(
3977                         stream->ctx,
3978                         stream,
3979                         false);
3980         }
3981
3982         return DC_OK;
3983 }
3984
3985
3986 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3987 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3988 {
3989         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3990         struct link_encoder *link_enc = NULL;
3991         struct cp_psp_stream_config config = {0};
3992         enum dp_panel_mode panel_mode =
3993                         dp_get_panel_mode(pipe_ctx->stream->link);
3994
3995         if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL)
3996                 return;
3997
3998         link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
3999         ASSERT(link_enc);
4000         if (link_enc == NULL)
4001                 return;
4002
4003         /* otg instance */
4004         config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
4005
4006         /* dig front end */
4007         config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
4008
4009         /* stream encoder index */
4010         config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
4011         if (is_dp_128b_132b_signal(pipe_ctx))
4012                 config.stream_enc_idx =
4013                                 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
4014
4015         /* dig back end */
4016         config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
4017
4018         /* link encoder index */
4019         config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4020         if (is_dp_128b_132b_signal(pipe_ctx))
4021                 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;
4022
4023         /* dio output index is dpia index for DPIA endpoint & dcio index by default */
4024         if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
4025                 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1;
4026         else
4027                 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4028
4029
4030         /* phy index */
4031         config.phy_idx = resource_transmitter_to_phy_idx(
4032                         pipe_ctx->stream->link->dc, link_enc->transmitter);
4033         if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
4034                 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */
4035                 config.phy_idx = 0;
4036
4037         /* stream properties */
4038         config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0;
4039         config.mst_enabled = (pipe_ctx->stream->signal ==
4040                         SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0;
4041         config.dp2_enabled = is_dp_128b_132b_signal(pipe_ctx) ? 1 : 0;
4042         config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ?
4043                         1 : 0;
4044         config.dpms_off = dpms_off;
4045
4046         /* dm stream context */
4047         config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
4048
4049         cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
4050 }
4051 #endif
4052
4053 static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx)
4054 {
4055         struct dc *dc = pipe_ctx->stream->ctx->dc;
4056         struct dc_stream_state *stream = pipe_ctx->stream;
4057         struct link_mst_stream_allocation_table proposed_table = {0};
4058         struct fixed31_32 avg_time_slots_per_mtp;
4059         uint8_t req_slot_count = 0;
4060         uint8_t vc_id = 1; /// VC ID always 1 for SST
4061         struct dc_link_settings link_settings = {0};
4062         const struct link_hwss *link_hwss = get_link_hwss(stream->link, &pipe_ctx->link_res);
4063         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4064
4065         decide_link_settings(stream, &link_settings);
4066         stream->link->cur_link_settings = link_settings;
4067
4068         if (link_hwss->ext.enable_dp_link_output)
4069                 link_hwss->ext.enable_dp_link_output(stream->link, &pipe_ctx->link_res,
4070                                 stream->signal, pipe_ctx->clock_source->id,
4071                                 &link_settings);
4072
4073 #ifdef DIAGS_BUILD
4074         /* Workaround for FPGA HPO capture DP link data:
4075          * HPO capture will set link to active mode
4076          * This workaround is required to get a capture from start of frame
4077          */
4078         if (!dc->debug.fpga_hpo_capture_en) {
4079                 struct encoder_set_dp_phy_pattern_param params = {0};
4080                 params.dp_phy_pattern = DP_TEST_PATTERN_VIDEO_MODE;
4081
4082                 /* Set link active */
4083                 stream->link->hpo_dp_link_enc->funcs->set_link_test_pattern(
4084                                 stream->link->hpo_dp_link_enc,
4085                                 &params);
4086         }
4087 #endif
4088
4089         /* Enable DP_STREAM_ENC */
4090         dc->hwss.enable_stream(pipe_ctx);
4091
4092         /* Set DPS PPS SDP (AKA "info frames") */
4093         if (pipe_ctx->stream->timing.flags.DSC) {
4094                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4095         }
4096
4097         /* Allocate Payload */
4098         if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) {
4099                 // MST case
4100                 uint8_t i;
4101
4102                 proposed_table.stream_count = state->stream_count;
4103                 for (i = 0; i < state->stream_count; i++) {
4104                         avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link);
4105                         req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4106                         proposed_table.stream_allocations[i].slot_count = req_slot_count;
4107                         proposed_table.stream_allocations[i].vcp_id = i+1;
4108                         /* NOTE: This makes assumption that pipe_ctx index is same as stream index */
4109                         proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc;
4110                 }
4111         } else {
4112                 // SST case
4113                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, stream->link);
4114                 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4115                 proposed_table.stream_count = 1; /// Always 1 stream for SST
4116                 proposed_table.stream_allocations[0].slot_count = req_slot_count;
4117                 proposed_table.stream_allocations[0].vcp_id = vc_id;
4118                 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
4119         }
4120
4121         link_hwss->ext.update_stream_allocation_table(stream->link,
4122                         &pipe_ctx->link_res,
4123                         &proposed_table);
4124
4125         if (link_hwss->ext.set_throttled_vcp_size)
4126                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
4127
4128         dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings);
4129 }
4130
4131 void core_link_enable_stream(
4132                 struct dc_state *state,
4133                 struct pipe_ctx *pipe_ctx)
4134 {
4135         struct dc *dc = pipe_ctx->stream->ctx->dc;
4136         struct dc_stream_state *stream = pipe_ctx->stream;
4137         struct dc_link *link = stream->sink->link;
4138         enum dc_status status;
4139         struct link_encoder *link_enc;
4140         enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
4141         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4142         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
4143
4144         if (is_dp_128b_132b_signal(pipe_ctx))
4145                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4146
4147         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4148
4149         if (pipe_ctx->stream->sink) {
4150                 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4151                         pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4152                         DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4153                         pipe_ctx->stream->sink->edid_caps.display_name,
4154                         pipe_ctx->stream->signal);
4155                 }
4156         }
4157
4158         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4159                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4160                 return;
4161
4162         link_enc = link_enc_cfg_get_link_enc(link);
4163         ASSERT(link_enc);
4164
4165         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)
4166                         && !is_dp_128b_132b_signal(pipe_ctx)) {
4167                 if (link_enc)
4168                         link_enc->funcs->setup(
4169                                 link_enc,
4170                                 pipe_ctx->stream->signal);
4171         }
4172
4173         pipe_ctx->stream->link->link_state_valid = true;
4174
4175         if (pipe_ctx->stream_res.tg->funcs->set_out_mux) {
4176                 if (is_dp_128b_132b_signal(pipe_ctx))
4177                         otg_out_dest = OUT_MUX_HPO_DP;
4178                 else
4179                         otg_out_dest = OUT_MUX_DIO;
4180                 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
4181         }
4182
4183         link_hwss->setup_stream_attribute(pipe_ctx);
4184
4185         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
4186                 bool apply_edp_fast_boot_optimization =
4187                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
4188
4189                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
4190
4191                 // Enable VPG before building infoframe
4192                 if (vpg && vpg->funcs->vpg_poweron)
4193                         vpg->funcs->vpg_poweron(vpg);
4194
4195                 resource_build_info_frame(pipe_ctx);
4196                 dc->hwss.update_info_frame(pipe_ctx);
4197
4198                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4199                         dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
4200
4201                 /* Do not touch link on seamless boot optimization. */
4202                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
4203                         pipe_ctx->stream->dpms_off = false;
4204
4205                         /* Still enable stream features & audio on seamless boot for DP external displays */
4206                         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
4207                                 enable_stream_features(pipe_ctx);
4208                                 if (pipe_ctx->stream_res.audio != NULL) {
4209                                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
4210                                         dc->hwss.enable_audio_stream(pipe_ctx);
4211                                 }
4212                         }
4213
4214 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4215                         update_psp_stream_config(pipe_ctx, false);
4216 #endif
4217                         return;
4218                 }
4219
4220                 /* eDP lit up by bios already, no need to enable again. */
4221                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
4222                                         apply_edp_fast_boot_optimization &&
4223                                         !pipe_ctx->stream->timing.flags.DSC &&
4224                                         !pipe_ctx->next_odm_pipe) {
4225                         pipe_ctx->stream->dpms_off = false;
4226 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4227                         update_psp_stream_config(pipe_ctx, false);
4228 #endif
4229                         return;
4230                 }
4231
4232                 if (pipe_ctx->stream->dpms_off)
4233                         return;
4234
4235                 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
4236                  * link training). This is to make sure the bandwidth sent to DIG BE won't be
4237                  * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
4238                  * will be automatically set at a later time when the video is enabled
4239                  * (DP_VID_STREAM_EN = 1).
4240                  */
4241                 if (pipe_ctx->stream->timing.flags.DSC) {
4242                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4243                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4244                                 dp_set_dsc_enable(pipe_ctx, true);
4245                 }
4246
4247                 status = enable_link(state, pipe_ctx);
4248
4249                 if (status != DC_OK) {
4250                         DC_LOG_WARNING("enabling link %u failed: %d\n",
4251                         pipe_ctx->stream->link->link_index,
4252                         status);
4253
4254                         /* Abort stream enable *unless* the failure was due to
4255                          * DP link training - some DP monitors will recover and
4256                          * show the stream anyway. But MST displays can't proceed
4257                          * without link training.
4258                          */
4259                         if (status != DC_FAIL_DP_LINK_TRAINING ||
4260                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
4261                                 if (false == stream->link->link_status.link_active)
4262                                         disable_link(stream->link, &pipe_ctx->link_res,
4263                                                         pipe_ctx->stream->signal);
4264                                 BREAK_TO_DEBUGGER();
4265                                 return;
4266                         }
4267                 }
4268
4269                 /* turn off otg test pattern if enable */
4270                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4271                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4272                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4273                                         COLOR_DEPTH_UNDEFINED);
4274
4275                 /* This second call is needed to reconfigure the DIG
4276                  * as a workaround for the incorrect value being applied
4277                  * from transmitter control.
4278                  */
4279                 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
4280                                 is_dp_128b_132b_signal(pipe_ctx)))
4281                         if (link_enc)
4282                                 link_enc->funcs->setup(
4283                                         link_enc,
4284                                         pipe_ctx->stream->signal);
4285
4286                 dc->hwss.enable_stream(pipe_ctx);
4287
4288                 /* Set DPS PPS SDP (AKA "info frames") */
4289                 if (pipe_ctx->stream->timing.flags.DSC) {
4290                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4291                                         dc_is_virtual_signal(pipe_ctx->stream->signal)) {
4292                                 dp_set_dsc_on_rx(pipe_ctx, true);
4293                                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4294                         }
4295                 }
4296
4297                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4298                         dc_link_allocate_mst_payload(pipe_ctx);
4299                 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4300                                 is_dp_128b_132b_signal(pipe_ctx))
4301                         dc_link_update_sst_payload(pipe_ctx, true);
4302
4303                 dc->hwss.unblank_stream(pipe_ctx,
4304                         &pipe_ctx->stream->link->cur_link_settings);
4305
4306                 if (stream->sink_patches.delay_ignore_msa > 0)
4307                         msleep(stream->sink_patches.delay_ignore_msa);
4308
4309                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4310                         enable_stream_features(pipe_ctx);
4311 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4312                 update_psp_stream_config(pipe_ctx, false);
4313 #endif
4314
4315                 dc->hwss.enable_audio_stream(pipe_ctx);
4316
4317         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
4318                 if (is_dp_128b_132b_signal(pipe_ctx))
4319                         fpga_dp_hpo_enable_link_and_stream(state, pipe_ctx);
4320                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4321                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
4322                         dp_set_dsc_enable(pipe_ctx, true);
4323         }
4324
4325         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
4326                 core_link_set_avmute(pipe_ctx, false);
4327         }
4328 }
4329
4330 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
4331 {
4332         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4333         struct dc_stream_state *stream = pipe_ctx->stream;
4334         struct dc_link *link = stream->sink->link;
4335         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4336
4337         if (is_dp_128b_132b_signal(pipe_ctx))
4338                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4339
4340         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4341
4342         if (pipe_ctx->stream->sink) {
4343                 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4344                         pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4345                         DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4346                         pipe_ctx->stream->sink->edid_caps.display_name,
4347                         pipe_ctx->stream->signal);
4348                 }
4349         }
4350
4351         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4352                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4353                 return;
4354
4355         if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
4356                 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
4357                         core_link_set_avmute(pipe_ctx, true);
4358         }
4359
4360         dc->hwss.disable_audio_stream(pipe_ctx);
4361
4362 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4363         update_psp_stream_config(pipe_ctx, true);
4364 #endif
4365         dc->hwss.blank_stream(pipe_ctx);
4366
4367         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4368                 deallocate_mst_payload(pipe_ctx);
4369         else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4370                         is_dp_128b_132b_signal(pipe_ctx))
4371                 dc_link_update_sst_payload(pipe_ctx, false);
4372
4373         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4374                 struct ext_hdmi_settings settings = {0};
4375                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
4376
4377                 unsigned short masked_chip_caps = link->chip_caps &
4378                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
4379                 //Need to inform that sink is going to use legacy HDMI mode.
4380                 dal_ddc_service_write_scdc_data(
4381                         link->ddc,
4382                         165000,//vbios only handles 165Mhz.
4383                         false);
4384                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
4385                         /* DP159, Retimer settings */
4386                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
4387                                 write_i2c_retimer_setting(pipe_ctx,
4388                                                 false, false, &settings);
4389                         else
4390                                 write_i2c_default_retimer_setting(pipe_ctx,
4391                                                 false, false);
4392                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
4393                         /* PI3EQX1204, Redriver settings */
4394                         write_i2c_redriver_setting(pipe_ctx, false);
4395                 }
4396         }
4397
4398         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4399                         !is_dp_128b_132b_signal(pipe_ctx)) {
4400
4401                 /* In DP1.x SST mode, our encoder will go to TPS1
4402                  * when link is on but stream is off.
4403                  * Disabling link before stream will avoid exposing TPS1 pattern
4404                  * during the disable sequence as it will confuse some receivers
4405                  * state machine.
4406                  * In DP2 or MST mode, our encoder will stay video active
4407                  */
4408                 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4409                 dc->hwss.disable_stream(pipe_ctx);
4410         } else {
4411                 dc->hwss.disable_stream(pipe_ctx);
4412                 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4413         }
4414
4415         if (pipe_ctx->stream->timing.flags.DSC) {
4416                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4417                         dp_set_dsc_enable(pipe_ctx, false);
4418         }
4419         if (is_dp_128b_132b_signal(pipe_ctx)) {
4420                 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4421                         pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
4422         }
4423
4424         if (vpg && vpg->funcs->vpg_powerdown)
4425                 vpg->funcs->vpg_powerdown(vpg);
4426 }
4427
4428 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
4429 {
4430         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4431
4432         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
4433                 return;
4434
4435         dc->hwss.set_avmute(pipe_ctx, enable);
4436 }
4437
4438 /**
4439  *  dc_link_enable_hpd_filter:
4440  *     If enable is true, programs HPD filter on associated HPD line using
4441  *     delay_on_disconnect/delay_on_connect values dependent on
4442  *     link->connector_signal
4443  *
4444  *     If enable is false, programs HPD filter on associated HPD line with no
4445  *     delays on connect or disconnect
4446  *
4447  *  @link:   pointer to the dc link
4448  *  @enable: boolean specifying whether to enable hbd
4449  */
4450 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
4451 {
4452         struct gpio *hpd;
4453
4454         if (enable) {
4455                 link->is_hpd_filter_disabled = false;
4456                 program_hpd_filter(link);
4457         } else {
4458                 link->is_hpd_filter_disabled = true;
4459                 /* Obtain HPD handle */
4460                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4461
4462                 if (!hpd)
4463                         return;
4464
4465                 /* Setup HPD filtering */
4466                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
4467                         struct gpio_hpd_config config;
4468
4469                         config.delay_on_connect = 0;
4470                         config.delay_on_disconnect = 0;
4471
4472                         dal_irq_setup_hpd_filter(hpd, &config);
4473
4474                         dal_gpio_close(hpd);
4475                 } else {
4476                         ASSERT_CRITICAL(false);
4477                 }
4478                 /* Release HPD handle */
4479                 dal_gpio_destroy_irq(&hpd);
4480         }
4481 }
4482
4483 void dc_link_set_drive_settings(struct dc *dc,
4484                                 struct link_training_settings *lt_settings,
4485                                 const struct dc_link *link)
4486 {
4487
4488         int i;
4489         struct link_resource link_res;
4490
4491         for (i = 0; i < dc->link_count; i++)
4492                 if (dc->links[i] == link)
4493                         break;
4494
4495         if (i >= dc->link_count)
4496                 ASSERT_CRITICAL(false);
4497
4498         dc_link_get_cur_link_res(link, &link_res);
4499         dc_link_dp_set_drive_settings(dc->links[i], &link_res, lt_settings);
4500 }
4501
4502 void dc_link_set_preferred_link_settings(struct dc *dc,
4503                                          struct dc_link_settings *link_setting,
4504                                          struct dc_link *link)
4505 {
4506         int i;
4507         struct pipe_ctx *pipe;
4508         struct dc_stream_state *link_stream;
4509         struct dc_link_settings store_settings = *link_setting;
4510
4511         link->preferred_link_setting = store_settings;
4512
4513         /* Retrain with preferred link settings only relevant for
4514          * DP signal type
4515          * Check for non-DP signal or if passive dongle present
4516          */
4517         if (!dc_is_dp_signal(link->connector_signal) ||
4518                 link->dongle_max_pix_clk > 0)
4519                 return;
4520
4521         for (i = 0; i < MAX_PIPES; i++) {
4522                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4523                 if (pipe->stream && pipe->stream->link) {
4524                         if (pipe->stream->link == link) {
4525                                 link_stream = pipe->stream;
4526                                 break;
4527                         }
4528                 }
4529         }
4530
4531         /* Stream not found */
4532         if (i == MAX_PIPES)
4533                 return;
4534
4535         /* Cannot retrain link if backend is off */
4536         if (link_stream->dpms_off)
4537                 return;
4538
4539         decide_link_settings(link_stream, &store_settings);
4540
4541         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
4542                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
4543                 dp_retrain_link_dp_test(link, &store_settings, false);
4544 }
4545
4546 void dc_link_set_preferred_training_settings(struct dc *dc,
4547                                                  struct dc_link_settings *link_setting,
4548                                                  struct dc_link_training_overrides *lt_overrides,
4549                                                  struct dc_link *link,
4550                                                  bool skip_immediate_retrain)
4551 {
4552         if (lt_overrides != NULL)
4553                 link->preferred_training_settings = *lt_overrides;
4554         else
4555                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
4556
4557         if (link_setting != NULL) {
4558                 link->preferred_link_setting = *link_setting;
4559                 if (dp_get_link_encoding_format(link_setting) == DP_128b_132b_ENCODING)
4560                         /* TODO: add dc update for acquiring link res  */
4561                         skip_immediate_retrain = true;
4562         } else {
4563                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
4564                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
4565         }
4566
4567         /* Retrain now, or wait until next stream update to apply */
4568         if (skip_immediate_retrain == false)
4569                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
4570 }
4571
4572 void dc_link_enable_hpd(const struct dc_link *link)
4573 {
4574         dc_link_dp_enable_hpd(link);
4575 }
4576
4577 void dc_link_disable_hpd(const struct dc_link *link)
4578 {
4579         dc_link_dp_disable_hpd(link);
4580 }
4581
4582 void dc_link_set_test_pattern(struct dc_link *link,
4583                               enum dp_test_pattern test_pattern,
4584                               enum dp_test_pattern_color_space test_pattern_color_space,
4585                               const struct link_training_settings *p_link_settings,
4586                               const unsigned char *p_custom_pattern,
4587                               unsigned int cust_pattern_size)
4588 {
4589         if (link != NULL)
4590                 dc_link_dp_set_test_pattern(
4591                         link,
4592                         test_pattern,
4593                         test_pattern_color_space,
4594                         p_link_settings,
4595                         p_custom_pattern,
4596                         cust_pattern_size);
4597 }
4598
4599 uint32_t dc_link_bandwidth_kbps(
4600         const struct dc_link *link,
4601         const struct dc_link_settings *link_setting)
4602 {
4603         uint32_t total_data_bw_efficiency_x10000 = 0;
4604         uint32_t link_rate_per_lane_kbps = 0;
4605
4606         switch (dp_get_link_encoding_format(link_setting)) {
4607         case DP_8b_10b_ENCODING:
4608                 /* For 8b/10b encoding:
4609                  * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
4610                  * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
4611                  */
4612                 link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
4613                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
4614                 if (dc_link_should_enable_fec(link)) {
4615                         total_data_bw_efficiency_x10000 /= 100;
4616                         total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
4617                 }
4618                 break;
4619         case DP_128b_132b_ENCODING:
4620                 /* For 128b/132b encoding:
4621                  * link rate is defined in the unit of 10mbps per lane.
4622                  * total data bandwidth efficiency is always 96.71%.
4623                  */
4624                 link_rate_per_lane_kbps = link_setting->link_rate * 10000;
4625                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
4626                 break;
4627         default:
4628                 break;
4629         }
4630
4631         /* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
4632         return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
4633 }
4634
4635 const struct dc_link_settings *dc_link_get_link_cap(
4636                 const struct dc_link *link)
4637 {
4638         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
4639                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
4640                 return &link->preferred_link_setting;
4641         return &link->verified_link_cap;
4642 }
4643
4644 void dc_link_overwrite_extended_receiver_cap(
4645                 struct dc_link *link)
4646 {
4647         dp_overwrite_extended_receiver_cap(link);
4648 }
4649
4650 bool dc_link_is_fec_supported(const struct dc_link *link)
4651 {
4652         /* TODO - use asic cap instead of link_enc->features
4653          * we no longer know which link enc to use for this link before commit
4654          */
4655         struct link_encoder *link_enc = NULL;
4656
4657         link_enc = link_enc_cfg_get_link_enc(link);
4658         ASSERT(link_enc);
4659
4660         return (dc_is_dp_signal(link->connector_signal) && link_enc &&
4661                         link_enc->features.fec_supported &&
4662                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
4663                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
4664 }
4665
4666 bool dc_link_should_enable_fec(const struct dc_link *link)
4667 {
4668         bool force_disable = false;
4669
4670         if (link->fec_state == dc_link_fec_enabled)
4671                 force_disable = false;
4672         else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
4673                         link->local_sink &&
4674                         link->local_sink->edid_caps.panel_patch.disable_fec)
4675                 force_disable = true;
4676         else if (link->connector_signal == SIGNAL_TYPE_EDP
4677                         && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
4678                          dsc_support.DSC_SUPPORT == false
4679                                 || link->dc->debug.disable_dsc_edp
4680                                 || !link->dc->caps.edp_dsc_support))
4681                 force_disable = true;
4682
4683         return !force_disable && dc_link_is_fec_supported(link);
4684 }
4685
4686 uint32_t dc_bandwidth_in_kbps_from_timing(
4687                 const struct dc_crtc_timing *timing)
4688 {
4689         uint32_t bits_per_channel = 0;
4690         uint32_t kbps;
4691
4692 #if defined(CONFIG_DRM_AMD_DC_DCN)
4693         if (timing->flags.DSC)
4694                 return dc_dsc_stream_bandwidth_in_kbps(timing,
4695                                 timing->dsc_cfg.bits_per_pixel,
4696                                 timing->dsc_cfg.num_slices_h,
4697                                 timing->dsc_cfg.is_dp);
4698 #endif /* CONFIG_DRM_AMD_DC_DCN */
4699
4700         switch (timing->display_color_depth) {
4701         case COLOR_DEPTH_666:
4702                 bits_per_channel = 6;
4703                 break;
4704         case COLOR_DEPTH_888:
4705                 bits_per_channel = 8;
4706                 break;
4707         case COLOR_DEPTH_101010:
4708                 bits_per_channel = 10;
4709                 break;
4710         case COLOR_DEPTH_121212:
4711                 bits_per_channel = 12;
4712                 break;
4713         case COLOR_DEPTH_141414:
4714                 bits_per_channel = 14;
4715                 break;
4716         case COLOR_DEPTH_161616:
4717                 bits_per_channel = 16;
4718                 break;
4719         default:
4720                 ASSERT(bits_per_channel != 0);
4721                 bits_per_channel = 8;
4722                 break;
4723         }
4724
4725         kbps = timing->pix_clk_100hz / 10;
4726         kbps *= bits_per_channel;
4727
4728         if (timing->flags.Y_ONLY != 1) {
4729                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
4730                 kbps *= 3;
4731                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
4732                         kbps /= 2;
4733                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
4734                         kbps = kbps * 2 / 3;
4735         }
4736
4737         return kbps;
4738
4739 }
4740
4741 void dc_link_get_cur_link_res(const struct dc_link *link,
4742                 struct link_resource *link_res)
4743 {
4744         int i;
4745         struct pipe_ctx *pipe = NULL;
4746
4747         memset(link_res, 0, sizeof(*link_res));
4748
4749         for (i = 0; i < MAX_PIPES; i++) {
4750                 pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];
4751                 if (pipe->stream && pipe->stream->link && pipe->top_pipe == NULL) {
4752                         if (pipe->stream->link == link) {
4753                                 *link_res = pipe->link_res;
4754                                 break;
4755                         }
4756                 }
4757         }
4758
4759 }
4760
4761 /**
4762  * dc_get_cur_link_res_map() - take a snapshot of current link resource allocation state
4763  * @dc: pointer to dc of the dm calling this
4764  * @map: a dc link resource snapshot defined internally to dc.
4765  *
4766  * DM needs to capture a snapshot of current link resource allocation mapping
4767  * and store it in its persistent storage.
4768  *
4769  * Some of the link resource is using first come first serve policy.
4770  * The allocation mapping depends on original hotplug order. This information
4771  * is lost after driver is loaded next time. The snapshot is used in order to
4772  * restore link resource to its previous state so user will get consistent
4773  * link capability allocation across reboot.
4774  *
4775  * Return: none (void function)
4776  *
4777  */
4778 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)
4779 {
4780         struct dc_link *link;
4781         uint32_t i;
4782         uint32_t hpo_dp_recycle_map = 0;
4783
4784         *map = 0;
4785
4786         if (dc->caps.dp_hpo) {
4787                 for (i = 0; i < dc->caps.max_links; i++) {
4788                         link = dc->links[i];
4789                         if (link->link_status.link_active &&
4790                                         dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING &&
4791                                         dp_get_link_encoding_format(&link->cur_link_settings) != DP_128b_132b_ENCODING)
4792                                 /* hpo dp link encoder is considered as recycled, when RX reports 128b/132b encoding capability
4793                                  * but current link doesn't use it.
4794                                  */
4795                                 hpo_dp_recycle_map |= (1 << i);
4796                 }
4797                 *map |= (hpo_dp_recycle_map << LINK_RES_HPO_DP_REC_MAP__SHIFT);
4798         }
4799 }
4800
4801 /**
4802  * dc_restore_link_res_map() - restore link resource allocation state from a snapshot
4803  * @dc: pointer to dc of the dm calling this
4804  * @map: a dc link resource snapshot defined internally to dc.
4805  *
4806  * DM needs to call this function after initial link detection on boot and
4807  * before first commit streams to restore link resource allocation state
4808  * from previous boot session.
4809  *
4810  * Some of the link resource is using first come first serve policy.
4811  * The allocation mapping depends on original hotplug order. This information
4812  * is lost after driver is loaded next time. The snapshot is used in order to
4813  * restore link resource to its previous state so user will get consistent
4814  * link capability allocation across reboot.
4815  *
4816  * Return: none (void function)
4817  *
4818  */
4819 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)
4820 {
4821         struct dc_link *link;
4822         uint32_t i;
4823         unsigned int available_hpo_dp_count;
4824         uint32_t hpo_dp_recycle_map = (*map & LINK_RES_HPO_DP_REC_MAP__MASK)
4825                         >> LINK_RES_HPO_DP_REC_MAP__SHIFT;
4826
4827         if (dc->caps.dp_hpo) {
4828                 available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count;
4829                 /* remove excess 128b/132b encoding support for not recycled links */
4830                 for (i = 0; i < dc->caps.max_links; i++) {
4831                         if ((hpo_dp_recycle_map & (1 << i)) == 0) {
4832                                 link = dc->links[i];
4833                                 if (link->type != dc_connection_none &&
4834                                                 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4835                                         if (available_hpo_dp_count > 0)
4836                                                 available_hpo_dp_count--;
4837                                         else
4838                                                 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4839                                                 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4840                                 }
4841                         }
4842                 }
4843                 /* remove excess 128b/132b encoding support for recycled links */
4844                 for (i = 0; i < dc->caps.max_links; i++) {
4845                         if ((hpo_dp_recycle_map & (1 << i)) != 0) {
4846                                 link = dc->links[i];
4847                                 if (link->type != dc_connection_none &&
4848                                                 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4849                                         if (available_hpo_dp_count > 0)
4850                                                 available_hpo_dp_count--;
4851                                         else
4852                                                 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4853                                                 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4854                                 }
4855                         }
4856                 }
4857         }
4858 }