2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/slab.h>
28 #include "dm_services.h"
29 #include "atomfirmware.h"
30 #include "dm_helpers.h"
32 #include "grph_object_id.h"
33 #include "gpio_service_interface.h"
34 #include "core_status.h"
35 #include "dc_link_dp.h"
36 #include "dc_link_ddc.h"
37 #include "link_hwss.h"
40 #include "link_encoder.h"
41 #include "hw_sequencer.h"
44 #include "fixed31_32.h"
45 #include "dpcd_defs.h"
47 #include "hw/clk_mgr.h"
48 #include "dce/dmub_psr.h"
49 #include "dmub/dmub_srv.h"
50 #include "inc/hw/panel_cntl.h"
52 #define DC_LOGGER_INIT(logger)
54 #define LINK_INFO(...) \
58 #define RETIMER_REDRIVER_INFO(...) \
59 DC_LOG_RETIMER_REDRIVER( \
61 /*******************************************************************************
63 ******************************************************************************/
66 PEAK_FACTOR_X1000 = 1006,
68 * Some receivers fail to train on first try and are good
69 * on subsequent tries. 2 retries should be plenty. If we
70 * don't have a successful training then we don't expect to
73 LINK_TRAINING_MAX_VERIFY_RETRY = 2
76 /*******************************************************************************
78 ******************************************************************************/
79 static void dc_link_destruct(struct dc_link *link)
84 dal_gpio_destroy_irq(&link->hpd_gpio);
85 link->hpd_gpio = NULL;
89 dal_ddc_service_destroy(&link->ddc);
92 link->panel_cntl->funcs->destroy(&link->panel_cntl);
95 link->link_enc->funcs->destroy(&link->link_enc);
98 dc_sink_release(link->local_sink);
100 for (i = 0; i < link->sink_count; ++i)
101 dc_sink_release(link->remote_sinks[i]);
104 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
105 struct graphics_object_id link_id,
106 struct gpio_service *gpio_service)
108 enum bp_result bp_result;
109 struct graphics_object_hpd_info hpd_info;
110 struct gpio_pin_info pin_info;
112 if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
115 bp_result = dcb->funcs->get_gpio_pin_info(dcb,
116 hpd_info.hpd_int_gpio_uid, &pin_info);
118 if (bp_result != BP_RESULT_OK) {
119 ASSERT(bp_result == BP_RESULT_NORECORD);
123 return dal_gpio_service_create_irq(gpio_service,
129 * Function: program_hpd_filter
132 * Programs HPD filter on associated HPD line
134 * @param [in] delay_on_connect_in_ms: Connect filter timeout
135 * @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
138 * true on success, false otherwise
140 static bool program_hpd_filter(const struct dc_link *link)
144 int delay_on_connect_in_ms = 0;
145 int delay_on_disconnect_in_ms = 0;
147 if (link->is_hpd_filter_disabled)
149 /* Verify feature is supported */
150 switch (link->connector_signal) {
151 case SIGNAL_TYPE_DVI_SINGLE_LINK:
152 case SIGNAL_TYPE_DVI_DUAL_LINK:
153 case SIGNAL_TYPE_HDMI_TYPE_A:
154 /* Program hpd filter */
155 delay_on_connect_in_ms = 500;
156 delay_on_disconnect_in_ms = 100;
158 case SIGNAL_TYPE_DISPLAY_PORT:
159 case SIGNAL_TYPE_DISPLAY_PORT_MST:
160 /* Program hpd filter to allow DP signal to settle */
161 /* 500: not able to detect MST <-> SST switch as HPD is low for
162 * only 100ms on DELL U2413
163 * 0: some passive dongle still show aux mode instead of i2c
164 * 20-50: not enough to hide bouncing HPD with passive dongle.
165 * also see intermittent i2c read issues.
167 delay_on_connect_in_ms = 80;
168 delay_on_disconnect_in_ms = 0;
170 case SIGNAL_TYPE_LVDS:
171 case SIGNAL_TYPE_EDP:
173 /* Don't program hpd filter */
177 /* Obtain HPD handle */
178 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
179 link->ctx->gpio_service);
184 /* Setup HPD filtering */
185 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
186 struct gpio_hpd_config config;
188 config.delay_on_connect = delay_on_connect_in_ms;
189 config.delay_on_disconnect = delay_on_disconnect_in_ms;
191 dal_irq_setup_hpd_filter(hpd, &config);
197 ASSERT_CRITICAL(false);
200 /* Release HPD handle */
201 dal_gpio_destroy_irq(&hpd);
207 * dc_link_detect_sink() - Determine if there is a sink connected
209 * @type: Returned connection type
210 * Does not detect downstream devices, such as MST sinks
211 * or display connected through active dongles
213 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
215 uint32_t is_hpd_high = 0;
216 struct gpio *hpd_pin;
218 if (link->connector_signal == SIGNAL_TYPE_LVDS) {
219 *type = dc_connection_single;
223 if (link->connector_signal == SIGNAL_TYPE_EDP) {
224 /*in case it is not on*/
225 link->dc->hwss.edp_power_control(link, true);
226 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
229 /* todo: may need to lock gpio access */
230 hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
231 link->ctx->gpio_service);
233 goto hpd_gpio_failure;
235 dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
236 dal_gpio_get_value(hpd_pin, &is_hpd_high);
237 dal_gpio_close(hpd_pin);
238 dal_gpio_destroy_irq(&hpd_pin);
241 *type = dc_connection_single;
242 /* TODO: need to do the actual detection */
244 *type = dc_connection_none;
253 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
255 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
257 switch (sink_signal) {
258 case SIGNAL_TYPE_DVI_SINGLE_LINK:
259 case SIGNAL_TYPE_DVI_DUAL_LINK:
260 case SIGNAL_TYPE_HDMI_TYPE_A:
261 case SIGNAL_TYPE_LVDS:
262 case SIGNAL_TYPE_RGB:
263 transaction_type = DDC_TRANSACTION_TYPE_I2C;
266 case SIGNAL_TYPE_DISPLAY_PORT:
267 case SIGNAL_TYPE_EDP:
268 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
271 case SIGNAL_TYPE_DISPLAY_PORT_MST:
272 /* MST does not use I2COverAux, but there is the
273 * SPECIAL use case for "immediate dwnstrm device
274 * access" (EPR#370830).
276 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
283 return transaction_type;
286 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
287 struct graphics_object_id downstream)
289 if (downstream.type == OBJECT_TYPE_CONNECTOR) {
290 switch (downstream.id) {
291 case CONNECTOR_ID_SINGLE_LINK_DVII:
292 switch (encoder.id) {
293 case ENCODER_ID_INTERNAL_DAC1:
294 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
295 case ENCODER_ID_INTERNAL_DAC2:
296 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
297 return SIGNAL_TYPE_RGB;
299 return SIGNAL_TYPE_DVI_SINGLE_LINK;
302 case CONNECTOR_ID_DUAL_LINK_DVII:
304 switch (encoder.id) {
305 case ENCODER_ID_INTERNAL_DAC1:
306 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
307 case ENCODER_ID_INTERNAL_DAC2:
308 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
309 return SIGNAL_TYPE_RGB;
311 return SIGNAL_TYPE_DVI_DUAL_LINK;
315 case CONNECTOR_ID_SINGLE_LINK_DVID:
316 return SIGNAL_TYPE_DVI_SINGLE_LINK;
317 case CONNECTOR_ID_DUAL_LINK_DVID:
318 return SIGNAL_TYPE_DVI_DUAL_LINK;
319 case CONNECTOR_ID_VGA:
320 return SIGNAL_TYPE_RGB;
321 case CONNECTOR_ID_HDMI_TYPE_A:
322 return SIGNAL_TYPE_HDMI_TYPE_A;
323 case CONNECTOR_ID_LVDS:
324 return SIGNAL_TYPE_LVDS;
325 case CONNECTOR_ID_DISPLAY_PORT:
326 return SIGNAL_TYPE_DISPLAY_PORT;
327 case CONNECTOR_ID_EDP:
328 return SIGNAL_TYPE_EDP;
330 return SIGNAL_TYPE_NONE;
332 } else if (downstream.type == OBJECT_TYPE_ENCODER) {
333 switch (downstream.id) {
334 case ENCODER_ID_EXTERNAL_NUTMEG:
335 case ENCODER_ID_EXTERNAL_TRAVIS:
336 return SIGNAL_TYPE_DISPLAY_PORT;
338 return SIGNAL_TYPE_NONE;
342 return SIGNAL_TYPE_NONE;
346 * dc_link_is_dp_sink_present() - Check if there is a native DP
347 * or passive DP-HDMI dongle connected
349 bool dc_link_is_dp_sink_present(struct dc_link *link)
351 enum gpio_result gpio_result;
352 uint32_t clock_pin = 0;
356 enum connector_id connector_id =
357 dal_graphics_object_id_get_connector_id(link->link_id);
360 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
361 (connector_id == CONNECTOR_ID_EDP));
363 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
370 /* Open GPIO and set it to I2C mode */
371 /* Note: this GpioMode_Input will be converted
372 * to GpioConfigType_I2cAuxDualMode in GPIO component,
373 * which indicates we need additional delay
376 if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
377 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
384 * Read GPIO: DP sink is present if both clock and data pins are zero
386 * [W/A] plug-unplug DP cable, sometimes customer board has
387 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
388 * then monitor can't br light up. Add retry 3 times
389 * But in real passive dongle, it need additional 3ms to detect
392 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
393 ASSERT(gpio_result == GPIO_RESULT_OK);
398 } while (retry++ < 3);
400 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
409 * Detect output sink type
411 static enum signal_type link_detect_sink(struct dc_link *link,
412 enum dc_detect_reason reason)
414 enum signal_type result = get_basic_signal_type(link->link_enc->id,
417 /* Internal digital encoder will detect only dongles
418 * that require digital signal
421 /* Detection mechanism is different
422 * for different native connectors.
423 * LVDS connector supports only LVDS signal;
424 * PCIE is a bus slot, the actual connector needs to be detected first;
425 * eDP connector supports only eDP signal;
426 * HDMI should check straps for audio
429 /* PCIE detects the actual connector on add-on board */
430 if (link->link_id.id == CONNECTOR_ID_PCIE) {
431 /* ZAZTODO implement PCIE add-on card detection */
434 switch (link->link_id.id) {
435 case CONNECTOR_ID_HDMI_TYPE_A: {
436 /* check audio support:
437 * if native HDMI is not supported, switch to DVI
439 struct audio_support *aud_support =
440 &link->dc->res_pool->audio_support;
442 if (!aud_support->hdmi_audio_native)
443 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
444 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
447 case CONNECTOR_ID_DISPLAY_PORT: {
448 /* DP HPD short pulse. Passive DP dongle will not
451 if (reason != DETECT_REASON_HPDRX) {
452 /* Check whether DP signal detected: if not -
453 * we assume signal is DVI; it could be corrected
454 * to HDMI after dongle detection
456 if (!dm_helpers_is_dp_sink_present(link))
457 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
468 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
469 struct audio_support *audio_support)
471 enum signal_type signal = SIGNAL_TYPE_NONE;
473 switch (dongle_type) {
474 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
475 if (audio_support->hdmi_audio_on_dongle)
476 signal = SIGNAL_TYPE_HDMI_TYPE_A;
478 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
480 case DISPLAY_DONGLE_DP_DVI_DONGLE:
481 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
483 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
484 if (audio_support->hdmi_audio_native)
485 signal = SIGNAL_TYPE_HDMI_TYPE_A;
487 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
490 signal = SIGNAL_TYPE_NONE;
497 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
498 struct display_sink_capability *sink_cap,
499 struct audio_support *audio_support)
501 dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
503 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
507 static void link_disconnect_sink(struct dc_link *link)
509 if (link->local_sink) {
510 dc_sink_release(link->local_sink);
511 link->local_sink = NULL;
514 link->dpcd_sink_count = 0;
517 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
519 dc_sink_release(link->local_sink);
520 link->local_sink = prev_sink;
523 #if defined(CONFIG_DRM_AMD_DC_HDCP)
524 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
529 case SIGNAL_TYPE_DISPLAY_PORT:
530 case SIGNAL_TYPE_DISPLAY_PORT_MST:
531 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
533 case SIGNAL_TYPE_DVI_SINGLE_LINK:
534 case SIGNAL_TYPE_DVI_DUAL_LINK:
535 case SIGNAL_TYPE_HDMI_TYPE_A:
536 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
537 * we can poll for bksv but some displays have an issue with this. Since its so rare
538 * for a display to not be 1.4 capable, this assumtion is ok
548 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
553 case SIGNAL_TYPE_DISPLAY_PORT:
554 case SIGNAL_TYPE_DISPLAY_PORT_MST:
555 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
556 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
557 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
559 case SIGNAL_TYPE_DVI_SINGLE_LINK:
560 case SIGNAL_TYPE_DVI_DUAL_LINK:
561 case SIGNAL_TYPE_HDMI_TYPE_A:
562 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
571 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
573 struct hdcp_protection_message msg22;
574 struct hdcp_protection_message msg14;
576 memset(&msg22, 0, sizeof(struct hdcp_protection_message));
577 memset(&msg14, 0, sizeof(struct hdcp_protection_message));
578 memset(link->hdcp_caps.rx_caps.raw, 0,
579 sizeof(link->hdcp_caps.rx_caps.raw));
581 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
582 link->ddc->transaction_type ==
583 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
584 link->connector_signal == SIGNAL_TYPE_EDP) {
585 msg22.data = link->hdcp_caps.rx_caps.raw;
586 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
587 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
589 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
590 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
591 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
593 msg22.version = HDCP_VERSION_22;
594 msg22.link = HDCP_LINK_PRIMARY;
595 msg22.max_retries = 5;
596 dc_process_hdcp_msg(signal, link, &msg22);
598 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
599 enum hdcp_message_status status = HDCP_MESSAGE_UNSUPPORTED;
601 msg14.data = &link->hdcp_caps.bcaps.raw;
602 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
603 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
604 msg14.version = HDCP_VERSION_14;
605 msg14.link = HDCP_LINK_PRIMARY;
606 msg14.max_retries = 5;
608 status = dc_process_hdcp_msg(signal, link, &msg14);
614 static void read_current_link_settings_on_detect(struct dc_link *link)
616 union lane_count_set lane_count_set = { {0} };
618 uint8_t link_rate_set;
619 uint32_t read_dpcd_retry_cnt = 10;
620 enum dc_status status = DC_ERROR_UNEXPECTED;
622 union max_down_spread max_down_spread = { {0} };
624 // Read DPCD 00101h to find out the number of lanes currently set
625 for (i = 0; i < read_dpcd_retry_cnt; i++) {
626 status = core_link_read_dpcd(link,
629 sizeof(lane_count_set));
630 /* First DPCD read after VDD ON can fail if the particular board
631 * does not have HPD pin wired correctly. So if DPCD read fails,
632 * which it should never happen, retry a few times. Target worst
633 * case scenario of 80 ms.
635 if (status == DC_OK) {
636 link->cur_link_settings.lane_count =
637 lane_count_set.bits.LANE_COUNT_SET;
644 // Read DPCD 00100h to find if standard link rates are set
645 core_link_read_dpcd(link, DP_LINK_BW_SET,
646 &link_bw_set, sizeof(link_bw_set));
648 if (link_bw_set == 0) {
649 if (link->connector_signal == SIGNAL_TYPE_EDP) {
650 /* If standard link rates are not being used,
651 * Read DPCD 00115h to find the edp link rate set used
653 core_link_read_dpcd(link, DP_LINK_RATE_SET,
654 &link_rate_set, sizeof(link_rate_set));
656 // edp_supported_link_rates_count = 0 for DP
657 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
658 link->cur_link_settings.link_rate =
659 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
660 link->cur_link_settings.link_rate_set = link_rate_set;
661 link->cur_link_settings.use_link_rate_set = true;
664 // Link Rate not found. Seamless boot may not work.
668 link->cur_link_settings.link_rate = link_bw_set;
669 link->cur_link_settings.use_link_rate_set = false;
671 // Read DPCD 00003h to find the max down spread.
672 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
673 &max_down_spread.raw, sizeof(max_down_spread));
674 link->cur_link_settings.link_spread =
675 max_down_spread.bits.MAX_DOWN_SPREAD ?
676 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
679 static bool detect_dp(struct dc_link *link,
680 struct display_sink_capability *sink_caps,
681 bool *converter_disable_audio,
682 struct audio_support *audio_support,
683 enum dc_detect_reason reason)
687 sink_caps->signal = link_detect_sink(link, reason);
688 sink_caps->transaction_type =
689 get_ddc_transaction_type(sink_caps->signal);
691 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
692 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
693 dpcd_set_source_specific_data(link);
694 if (!detect_dp_sink_caps(link))
696 if (is_mst_supported(link)) {
697 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
698 link->type = dc_connection_mst_branch;
700 dal_ddc_service_set_transaction_type(link->ddc,
701 sink_caps->transaction_type);
703 #if defined(CONFIG_DRM_AMD_DC_HDCP)
704 /* In case of fallback to SST when topology discovery below fails
705 * HDCP caps will be querried again later by the upper layer (caller
706 * of this function). */
707 query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
710 * This call will initiate MST topology discovery. Which
711 * will detect MST ports and add new DRM connector DRM
712 * framework. Then read EDID via remote i2c over aux. In
713 * the end, will notify DRM detect result and save EDID
714 * into DRM framework.
716 * .detect is called by .fill_modes.
717 * .fill_modes is called by user mode ioctl
718 * DRM_IOCTL_MODE_GETCONNECTOR.
720 * .get_modes is called by .fill_modes.
722 * call .get_modes, AMDGPU DM implementation will create
723 * new dc_sink and add to dc_link. For long HPD plug
724 * in/out, MST has its own handle.
726 * Therefore, just after dc_create, link->sink is not
727 * created for MST until user mode app calls
728 * DRM_IOCTL_MODE_GETCONNECTOR.
730 * Need check ->sink usages in case ->sink = NULL
731 * TODO: s3 resume check
733 if (reason == DETECT_REASON_BOOT)
736 dm_helpers_dp_update_branch_info(link->ctx, link);
738 if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
740 /* MST not supported */
741 link->type = dc_connection_single;
742 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
746 if (link->type != dc_connection_mst_branch &&
747 is_dp_active_dongle(link)) {
748 /* DP active dongles */
749 link->type = dc_connection_active_dongle;
750 if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
752 * active dongle unplug processing for short irq
754 link_disconnect_sink(link);
758 if (link->dpcd_caps.dongle_type !=
759 DISPLAY_DONGLE_DP_HDMI_CONVERTER)
760 *converter_disable_audio = true;
763 /* DP passive dongles */
764 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
772 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
774 if (old_edid->length != new_edid->length)
777 if (new_edid->length == 0)
780 return (memcmp(old_edid->raw_edid,
781 new_edid->raw_edid, new_edid->length) == 0);
784 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
787 * something is terribly wrong if time out is > 200ms. (5Hz)
788 * 500 microseconds * 400 tries us 200 ms
790 unsigned int sleep_time_in_microseconds = 500;
791 unsigned int tries_allowed = 400;
793 unsigned long long enter_timestamp;
794 unsigned long long finish_timestamp;
795 unsigned long long time_taken_in_ns;
798 DC_LOGGER_INIT(link->ctx->logger);
800 if (!link->link_enc->funcs->is_in_alt_mode)
803 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
804 DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
809 enter_timestamp = dm_get_timestamp(link->ctx);
811 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
812 udelay(sleep_time_in_microseconds);
813 /* ask the link if alt mode is enabled, if so return ok */
814 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
815 finish_timestamp = dm_get_timestamp(link->ctx);
817 dm_get_elapse_time_in_ns(link->ctx,
820 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
821 div_u64(time_taken_in_ns, 1000000));
825 finish_timestamp = dm_get_timestamp(link->ctx);
826 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
828 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
829 div_u64(time_taken_in_ns, 1000000));
834 * dc_link_detect() - Detect if a sink is attached to a given link
836 * link->local_sink is created or destroyed as needed.
838 * This does not create remote sinks but will trigger DM
839 * to start MST detection if a branch is detected.
841 static bool dc_link_detect_helper(struct dc_link *link,
842 enum dc_detect_reason reason)
844 struct dc_sink_init_data sink_init_data = { 0 };
845 struct display_sink_capability sink_caps = { 0 };
847 bool converter_disable_audio = false;
848 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
849 bool same_edid = false;
850 enum dc_edid_status edid_status;
851 struct dc_context *dc_ctx = link->ctx;
852 struct dc_sink *sink = NULL;
853 struct dc_sink *prev_sink = NULL;
854 struct dpcd_caps prev_dpcd_caps;
855 bool same_dpcd = true;
856 enum dc_connection_type new_connection_type = dc_connection_none;
857 bool perform_dp_seamless_boot = false;
859 DC_LOGGER_INIT(link->ctx->logger);
861 if (dc_is_virtual_signal(link->connector_signal))
864 if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
865 link->connector_signal == SIGNAL_TYPE_EDP) &&
867 // need to re-write OUI and brightness in resume case
868 if (link->connector_signal == SIGNAL_TYPE_EDP) {
869 dpcd_set_source_specific_data(link);
870 dc_link_set_default_brightness_aux(link);
877 if (!dc_link_detect_sink(link, &new_connection_type)) {
882 prev_sink = link->local_sink;
884 dc_sink_retain(prev_sink);
885 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
888 link_disconnect_sink(link);
889 if (new_connection_type != dc_connection_none) {
890 link->type = new_connection_type;
891 link->link_state_valid = false;
893 /* From Disconnected-to-Connected. */
894 switch (link->connector_signal) {
895 case SIGNAL_TYPE_HDMI_TYPE_A: {
896 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
897 if (aud_support->hdmi_audio_native)
898 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
900 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
904 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
905 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
906 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
910 case SIGNAL_TYPE_DVI_DUAL_LINK: {
911 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
912 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
916 case SIGNAL_TYPE_LVDS: {
917 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
918 sink_caps.signal = SIGNAL_TYPE_LVDS;
922 case SIGNAL_TYPE_EDP: {
923 read_current_link_settings_on_detect(link);
925 dpcd_set_source_specific_data(link);
927 detect_edp_sink_caps(link);
928 read_current_link_settings_on_detect(link);
929 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
930 sink_caps.signal = SIGNAL_TYPE_EDP;
934 case SIGNAL_TYPE_DISPLAY_PORT: {
935 /* wa HPD high coming too early*/
936 if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
937 /* if alt mode times out, return false */
938 if (!wait_for_entering_dp_alt_mode(link))
942 if (!detect_dp(link, &sink_caps,
943 &converter_disable_audio,
944 aud_support, reason)) {
946 dc_sink_release(prev_sink);
950 // Check if dpcp block is the same
952 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps,
953 sizeof(struct dpcd_caps)))
956 /* Active dongle downstream unplug*/
957 if (link->type == dc_connection_active_dongle &&
958 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
960 /* Downstream unplug */
961 dc_sink_release(prev_sink);
965 if (link->type == dc_connection_mst_branch) {
966 LINK_INFO("link=%d, mst branch is now Connected\n",
968 /* Need to setup mst link_cap struct here
969 * otherwise dc_link_detect() will leave mst link_cap
970 * empty which leads to allocate_mst_payload() has "0"
971 * pbn_per_slot value leading to exception on dc_fixpt_div()
973 dp_verify_mst_link_cap(link);
976 dc_sink_release(prev_sink);
980 // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
981 if (reason == DETECT_REASON_BOOT &&
982 !dc_ctx->dc->config.power_down_display_on_boot &&
983 link->link_status.link_active)
984 perform_dp_seamless_boot = true;
986 if (perform_dp_seamless_boot) {
987 read_current_link_settings_on_detect(link);
988 link->verified_link_cap = link->reported_link_cap;
995 DC_ERROR("Invalid connector type! signal:%d\n",
996 link->connector_signal);
998 dc_sink_release(prev_sink);
1002 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1003 link->dpcd_sink_count =
1004 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1006 link->dpcd_sink_count = 1;
1008 dal_ddc_service_set_transaction_type(link->ddc,
1009 sink_caps.transaction_type);
1012 dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1014 sink_init_data.link = link;
1015 sink_init_data.sink_signal = sink_caps.signal;
1017 sink = dc_sink_create(&sink_init_data);
1019 DC_ERROR("Failed to create sink!\n");
1021 dc_sink_release(prev_sink);
1025 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1026 sink->converter_disable_audio = converter_disable_audio;
1028 /* dc_sink_create returns a new reference */
1029 link->local_sink = sink;
1031 edid_status = dm_helpers_read_local_edid(link->ctx,
1034 switch (edid_status) {
1035 case EDID_BAD_CHECKSUM:
1036 DC_LOG_ERROR("EDID checksum invalid.\n");
1038 case EDID_NO_RESPONSE:
1039 DC_LOG_ERROR("No EDID read.\n");
1041 * Abort detection for non-DP connectors if we have
1044 * DP needs to report as connected if HDP is high
1045 * even if we have no EDID in order to go to
1048 if (dc_is_hdmi_signal(link->connector_signal) ||
1049 dc_is_dvi_signal(link->connector_signal)) {
1051 dc_sink_release(prev_sink);
1059 if (link->local_sink->edid_caps.panel_patch.disable_fec)
1060 link->ctx->dc->debug.disable_fec = true;
1062 // Check if edid is the same
1064 (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1065 same_edid = is_same_edid(&prev_sink->dc_edid,
1068 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1069 link->ctx->dc->debug.hdmi20_disable = true;
1071 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1072 sink_caps.transaction_type ==
1073 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1075 * TODO debug why Dell 2413 doesn't like
1076 * two link trainings
1078 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1079 query_hdcp_capability(sink->sink_signal, link);
1082 // verify link cap for SST non-seamless boot
1083 if (!perform_dp_seamless_boot)
1084 dp_verify_link_cap_with_retries(link,
1085 &link->reported_link_cap,
1086 LINK_TRAINING_MAX_VERIFY_RETRY);
1088 // If edid is the same, then discard new sink and revert back to original sink
1090 link_disconnect_remap(prev_sink, link);
1094 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1095 query_hdcp_capability(sink->sink_signal, link);
1099 /* HDMI-DVI Dongle */
1100 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1101 !sink->edid_caps.edid_hdmi)
1102 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1104 /* Connectivity log: detection */
1105 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1106 CONN_DATA_DETECT(link,
1107 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1109 "%s: [Block %d] ", sink->edid_caps.display_name, i);
1112 DC_LOG_DETECTION_EDID_PARSER("%s: "
1113 "manufacturer_id = %X, "
1115 "serial_number = %X, "
1116 "manufacture_week = %d, "
1117 "manufacture_year = %d, "
1118 "display_name = %s, "
1119 "speaker_flag = %d, "
1120 "audio_mode_count = %d\n",
1122 sink->edid_caps.manufacturer_id,
1123 sink->edid_caps.product_id,
1124 sink->edid_caps.serial_number,
1125 sink->edid_caps.manufacture_week,
1126 sink->edid_caps.manufacture_year,
1127 sink->edid_caps.display_name,
1128 sink->edid_caps.speaker_flags,
1129 sink->edid_caps.audio_mode_count);
1131 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1132 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1133 "format_code = %d, "
1134 "channel_count = %d, "
1135 "sample_rate = %d, "
1136 "sample_size = %d\n",
1139 sink->edid_caps.audio_modes[i].format_code,
1140 sink->edid_caps.audio_modes[i].channel_count,
1141 sink->edid_caps.audio_modes[i].sample_rate,
1142 sink->edid_caps.audio_modes[i].sample_size);
1145 /* From Connected-to-Disconnected. */
1146 if (link->type == dc_connection_mst_branch) {
1147 LINK_INFO("link=%d, mst branch is now Disconnected\n",
1150 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1152 link->mst_stream_alloc_table.stream_count = 0;
1153 memset(link->mst_stream_alloc_table.stream_allocations,
1155 sizeof(link->mst_stream_alloc_table.stream_allocations));
1158 link->type = dc_connection_none;
1159 sink_caps.signal = SIGNAL_TYPE_NONE;
1160 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1161 * is not cleared. If we emulate a DP signal on this connection, it thinks
1162 * the dongle is still there and limits the number of modes we can emulate.
1163 * Clear dongle_max_pix_clk on disconnect to fix this
1165 link->dongle_max_pix_clk = 0;
1168 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
1169 link->link_index, sink,
1170 (sink_caps.signal ==
1171 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1172 prev_sink, same_dpcd, same_edid);
1175 dc_sink_release(prev_sink);
1180 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1182 const struct dc *dc = link->dc;
1185 /* get out of low power state */
1186 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1188 ret = dc_link_detect_helper(link, reason);
1190 /* Go back to power optimized state */
1191 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1196 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1200 dal_gpio_lock_pin(dc_link->hpd_gpio);
1201 dal_gpio_get_value(dc_link->hpd_gpio, &state);
1202 dal_gpio_unlock_pin(dc_link->hpd_gpio);
1207 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1210 enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1212 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1213 link->ctx->gpio_service);
1216 switch (dal_irq_get_source(hpd)) {
1217 case DC_IRQ_SOURCE_HPD1:
1218 hpd_id = HPD_SOURCEID1;
1220 case DC_IRQ_SOURCE_HPD2:
1221 hpd_id = HPD_SOURCEID2;
1223 case DC_IRQ_SOURCE_HPD3:
1224 hpd_id = HPD_SOURCEID3;
1226 case DC_IRQ_SOURCE_HPD4:
1227 hpd_id = HPD_SOURCEID4;
1229 case DC_IRQ_SOURCE_HPD5:
1230 hpd_id = HPD_SOURCEID5;
1232 case DC_IRQ_SOURCE_HPD6:
1233 hpd_id = HPD_SOURCEID6;
1236 BREAK_TO_DEBUGGER();
1240 dal_gpio_destroy_irq(&hpd);
1246 static enum channel_id get_ddc_line(struct dc_link *link)
1249 enum channel_id channel = CHANNEL_ID_UNKNOWN;
1251 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1254 switch (dal_ddc_get_line(ddc)) {
1255 case GPIO_DDC_LINE_DDC1:
1256 channel = CHANNEL_ID_DDC1;
1258 case GPIO_DDC_LINE_DDC2:
1259 channel = CHANNEL_ID_DDC2;
1261 case GPIO_DDC_LINE_DDC3:
1262 channel = CHANNEL_ID_DDC3;
1264 case GPIO_DDC_LINE_DDC4:
1265 channel = CHANNEL_ID_DDC4;
1267 case GPIO_DDC_LINE_DDC5:
1268 channel = CHANNEL_ID_DDC5;
1270 case GPIO_DDC_LINE_DDC6:
1271 channel = CHANNEL_ID_DDC6;
1273 case GPIO_DDC_LINE_DDC_VGA:
1274 channel = CHANNEL_ID_DDC_VGA;
1276 case GPIO_DDC_LINE_I2C_PAD:
1277 channel = CHANNEL_ID_I2C_PAD;
1280 BREAK_TO_DEBUGGER();
1288 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1290 switch (encoder.id) {
1291 case ENCODER_ID_INTERNAL_UNIPHY:
1292 switch (encoder.enum_id) {
1294 return TRANSMITTER_UNIPHY_A;
1296 return TRANSMITTER_UNIPHY_B;
1298 return TRANSMITTER_UNKNOWN;
1301 case ENCODER_ID_INTERNAL_UNIPHY1:
1302 switch (encoder.enum_id) {
1304 return TRANSMITTER_UNIPHY_C;
1306 return TRANSMITTER_UNIPHY_D;
1308 return TRANSMITTER_UNKNOWN;
1311 case ENCODER_ID_INTERNAL_UNIPHY2:
1312 switch (encoder.enum_id) {
1314 return TRANSMITTER_UNIPHY_E;
1316 return TRANSMITTER_UNIPHY_F;
1318 return TRANSMITTER_UNKNOWN;
1321 case ENCODER_ID_INTERNAL_UNIPHY3:
1322 switch (encoder.enum_id) {
1324 return TRANSMITTER_UNIPHY_G;
1326 return TRANSMITTER_UNKNOWN;
1329 case ENCODER_ID_EXTERNAL_NUTMEG:
1330 switch (encoder.enum_id) {
1332 return TRANSMITTER_NUTMEG_CRT;
1334 return TRANSMITTER_UNKNOWN;
1337 case ENCODER_ID_EXTERNAL_TRAVIS:
1338 switch (encoder.enum_id) {
1340 return TRANSMITTER_TRAVIS_CRT;
1342 return TRANSMITTER_TRAVIS_LCD;
1344 return TRANSMITTER_UNKNOWN;
1348 return TRANSMITTER_UNKNOWN;
1352 static bool dc_link_construct(struct dc_link *link,
1353 const struct link_init_data *init_params)
1356 struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1357 struct dc_context *dc_ctx = init_params->ctx;
1358 struct encoder_init_data enc_init_data = { 0 };
1359 struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1360 struct integrated_info info = {{{ 0 }}};
1361 struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1362 const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1364 DC_LOGGER_INIT(dc_ctx->logger);
1366 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1367 link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1369 link->link_status.dpcd_caps = &link->dpcd_caps;
1371 link->dc = init_params->dc;
1373 link->link_index = init_params->link_index;
1375 memset(&link->preferred_training_settings, 0,
1376 sizeof(struct dc_link_training_overrides));
1377 memset(&link->preferred_link_setting, 0,
1378 sizeof(struct dc_link_settings));
1381 bios->funcs->get_connector_id(bios, init_params->connector_index);
1383 if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1384 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1385 __func__, init_params->connector_index,
1386 link->link_id.type, OBJECT_TYPE_CONNECTOR);
1390 if (link->dc->res_pool->funcs->link_init)
1391 link->dc->res_pool->funcs->link_init(link);
1393 link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1394 link->ctx->gpio_service);
1395 if (link->hpd_gpio) {
1396 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1397 dal_gpio_unlock_pin(link->hpd_gpio);
1398 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1401 switch (link->link_id.id) {
1402 case CONNECTOR_ID_HDMI_TYPE_A:
1403 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1406 case CONNECTOR_ID_SINGLE_LINK_DVID:
1407 case CONNECTOR_ID_SINGLE_LINK_DVII:
1408 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1410 case CONNECTOR_ID_DUAL_LINK_DVID:
1411 case CONNECTOR_ID_DUAL_LINK_DVII:
1412 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1414 case CONNECTOR_ID_DISPLAY_PORT:
1415 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1418 link->irq_source_hpd_rx =
1419 dal_irq_get_rx_source(link->hpd_gpio);
1422 case CONNECTOR_ID_EDP:
1423 link->connector_signal = SIGNAL_TYPE_EDP;
1425 if (link->hpd_gpio) {
1426 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1427 link->irq_source_hpd_rx =
1428 dal_irq_get_rx_source(link->hpd_gpio);
1432 case CONNECTOR_ID_LVDS:
1433 link->connector_signal = SIGNAL_TYPE_LVDS;
1436 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1441 /* TODO: #DAL3 Implement id to str function.*/
1442 LINK_INFO("Connector[%d] description:"
1444 init_params->connector_index,
1445 link->connector_signal);
1447 ddc_service_init_data.ctx = link->ctx;
1448 ddc_service_init_data.id = link->link_id;
1449 ddc_service_init_data.link = link;
1450 link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1453 DC_ERROR("Failed to create ddc_service!\n");
1454 goto ddc_create_fail;
1458 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1461 if (link->dc->res_pool->funcs->panel_cntl_create &&
1462 (link->link_id.id == CONNECTOR_ID_EDP ||
1463 link->link_id.id == CONNECTOR_ID_LVDS)) {
1464 panel_cntl_init_data.ctx = dc_ctx;
1465 panel_cntl_init_data.inst = 0;
1467 link->dc->res_pool->funcs->panel_cntl_create(
1468 &panel_cntl_init_data);
1470 if (link->panel_cntl == NULL) {
1471 DC_ERROR("Failed to create link panel_cntl!\n");
1472 goto panel_cntl_create_fail;
1476 enc_init_data.ctx = dc_ctx;
1477 bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1478 &enc_init_data.encoder);
1479 enc_init_data.connector = link->link_id;
1480 enc_init_data.channel = get_ddc_line(link);
1481 enc_init_data.hpd_source = get_hpd_line(link);
1483 link->hpd_src = enc_init_data.hpd_source;
1485 enc_init_data.transmitter =
1486 translate_encoder_to_transmitter(enc_init_data.encoder);
1488 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1490 if (!link->link_enc) {
1491 DC_ERROR("Failed to create link encoder!\n");
1492 goto link_enc_create_fail;
1495 link->link_enc_hw_inst = link->link_enc->transmitter;
1497 for (i = 0; i < 4; i++) {
1498 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1500 &link->device_tag) != BP_RESULT_OK) {
1501 DC_ERROR("Failed to find device tag!\n");
1502 goto device_tag_fail;
1505 /* Look for device tag that matches connector signal,
1506 * CRT for rgb, LCD for other supported signal tyes
1508 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1509 link->device_tag.dev_id))
1511 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1512 link->connector_signal != SIGNAL_TYPE_RGB)
1514 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1515 link->connector_signal == SIGNAL_TYPE_RGB)
1520 if (bios->integrated_info)
1521 info = *bios->integrated_info;
1523 /* Look for channel mapping corresponding to connector and device tag */
1524 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1525 struct external_display_path *path =
1526 &info.ext_disp_conn_info.path[i];
1528 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1529 path->device_connector_id.id == link->link_id.id &&
1530 path->device_connector_id.type == link->link_id.type) {
1531 if (link->device_tag.acpi_device != 0 &&
1532 path->device_acpi_enum == link->device_tag.acpi_device) {
1533 link->ddi_channel_mapping = path->channel_mapping;
1534 link->chip_caps = path->caps;
1535 } else if (path->device_tag ==
1536 link->device_tag.dev_id.raw_device_tag) {
1537 link->ddi_channel_mapping = path->channel_mapping;
1538 link->chip_caps = path->caps;
1545 * TODO check if GPIO programmed correctly
1547 * If GPIO isn't programmed correctly HPD might not rise or drain
1548 * fast enough, leading to bounces.
1550 program_hpd_filter(link);
1552 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1556 link->link_enc->funcs->destroy(&link->link_enc);
1557 link_enc_create_fail:
1558 if (link->panel_cntl != NULL)
1559 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1560 panel_cntl_create_fail:
1561 dal_ddc_service_destroy(&link->ddc);
1565 if (link->hpd_gpio) {
1566 dal_gpio_destroy_irq(&link->hpd_gpio);
1567 link->hpd_gpio = NULL;
1573 /*******************************************************************************
1575 ******************************************************************************/
1576 struct dc_link *link_create(const struct link_init_data *init_params)
1578 struct dc_link *link =
1579 kzalloc(sizeof(*link), GFP_KERNEL);
1584 if (false == dc_link_construct(link, init_params))
1585 goto construct_fail;
1596 void link_destroy(struct dc_link **link)
1598 dc_link_destruct(*link);
1603 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1605 struct dc_stream_state *stream = pipe_ctx->stream;
1606 struct dc_link *link = stream->link;
1607 union down_spread_ctrl old_downspread;
1608 union down_spread_ctrl new_downspread;
1610 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1611 &old_downspread.raw, sizeof(old_downspread));
1613 new_downspread.raw = old_downspread.raw;
1615 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1616 (stream->ignore_msa_timing_param) ? 1 : 0;
1618 if (new_downspread.raw != old_downspread.raw) {
1619 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1620 &new_downspread.raw, sizeof(new_downspread));
1624 static enum dc_status enable_link_dp(struct dc_state *state,
1625 struct pipe_ctx *pipe_ctx)
1627 struct dc_stream_state *stream = pipe_ctx->stream;
1628 enum dc_status status;
1629 bool skip_video_pattern;
1630 struct dc_link *link = stream->link;
1631 struct dc_link_settings link_settings = {0};
1634 bool apply_seamless_boot_optimization = false;
1635 uint32_t bl_oled_enable_delay = 50; // in ms
1637 // check for seamless boot
1638 for (i = 0; i < state->stream_count; i++) {
1639 if (state->streams[i]->apply_seamless_boot_optimization) {
1640 apply_seamless_boot_optimization = true;
1645 /* get link settings for video mode timing */
1646 decide_link_settings(stream, &link_settings);
1648 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1649 /*in case it is not on*/
1650 link->dc->hwss.edp_power_control(link, true);
1651 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1654 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1655 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1656 if (state->clk_mgr && !apply_seamless_boot_optimization)
1657 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1660 // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1661 dpcd_set_source_specific_data(link);
1663 skip_video_pattern = true;
1665 if (link_settings.link_rate == LINK_RATE_LOW)
1666 skip_video_pattern = false;
1668 if (perform_link_training_with_retries(&link_settings,
1670 LINK_TRAINING_ATTEMPTS,
1672 pipe_ctx->stream->signal)) {
1673 link->cur_link_settings = link_settings;
1676 status = DC_FAIL_DP_LINK_TRAINING;
1679 if (link->preferred_training_settings.fec_enable)
1680 fec_enable = *link->preferred_training_settings.fec_enable;
1684 dp_set_fec_enable(link, fec_enable);
1686 // during mode set we do DP_SET_POWER off then on, aux writes are lost
1687 if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
1688 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
1689 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
1690 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
1691 if (link->dpcd_sink_ext_caps.bits.oled == 1)
1692 msleep(bl_oled_enable_delay);
1693 dc_link_backlight_enable_aux(link, true);
1699 static enum dc_status enable_link_edp(
1700 struct dc_state *state,
1701 struct pipe_ctx *pipe_ctx)
1703 enum dc_status status;
1705 status = enable_link_dp(state, pipe_ctx);
1710 static enum dc_status enable_link_dp_mst(
1711 struct dc_state *state,
1712 struct pipe_ctx *pipe_ctx)
1714 struct dc_link *link = pipe_ctx->stream->link;
1716 /* sink signal type after MST branch is MST. Multiple MST sinks
1717 * share one link. Link DP PHY is enable or training only once.
1719 if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1722 /* clear payload table */
1723 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1725 /* to make sure the pending down rep can be processed
1726 * before enabling the link
1728 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1730 /* set the sink to MST mode before enabling the link */
1731 dp_enable_mst_on_sink(link, true);
1733 return enable_link_dp(state, pipe_ctx);
1736 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1737 enum engine_id eng_id,
1738 struct ext_hdmi_settings *settings)
1740 bool result = false;
1742 struct integrated_info *integrated_info =
1743 pipe_ctx->stream->ctx->dc_bios->integrated_info;
1745 if (integrated_info == NULL)
1749 * Get retimer settings from sbios for passing SI eye test for DCE11
1750 * The setting values are varied based on board revision and port id
1751 * Therefore the setting values of each ports is passed by sbios.
1754 // Check if current bios contains ext Hdmi settings
1755 if (integrated_info->gpu_cap_info & 0x20) {
1757 case ENGINE_ID_DIGA:
1758 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1759 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1760 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1761 memmove(settings->reg_settings,
1762 integrated_info->dp0_ext_hdmi_reg_settings,
1763 sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1764 memmove(settings->reg_settings_6g,
1765 integrated_info->dp0_ext_hdmi_6g_reg_settings,
1766 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1769 case ENGINE_ID_DIGB:
1770 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1771 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1772 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1773 memmove(settings->reg_settings,
1774 integrated_info->dp1_ext_hdmi_reg_settings,
1775 sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1776 memmove(settings->reg_settings_6g,
1777 integrated_info->dp1_ext_hdmi_6g_reg_settings,
1778 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1781 case ENGINE_ID_DIGC:
1782 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1783 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1784 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1785 memmove(settings->reg_settings,
1786 integrated_info->dp2_ext_hdmi_reg_settings,
1787 sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1788 memmove(settings->reg_settings_6g,
1789 integrated_info->dp2_ext_hdmi_6g_reg_settings,
1790 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1793 case ENGINE_ID_DIGD:
1794 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1795 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1796 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1797 memmove(settings->reg_settings,
1798 integrated_info->dp3_ext_hdmi_reg_settings,
1799 sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1800 memmove(settings->reg_settings_6g,
1801 integrated_info->dp3_ext_hdmi_6g_reg_settings,
1802 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1809 if (result == true) {
1810 // Validate settings from bios integrated info table
1811 if (settings->slv_addr == 0)
1813 if (settings->reg_num > 9)
1815 if (settings->reg_num_6g > 3)
1818 for (i = 0; i < settings->reg_num; i++) {
1819 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1823 for (i = 0; i < settings->reg_num_6g; i++) {
1824 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1833 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1834 uint8_t address, uint8_t *buffer, uint32_t length)
1836 struct i2c_command cmd = {0};
1837 struct i2c_payload payload = {0};
1839 memset(&payload, 0, sizeof(payload));
1840 memset(&cmd, 0, sizeof(cmd));
1842 cmd.number_of_payloads = 1;
1843 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1844 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1846 payload.address = address;
1847 payload.data = buffer;
1848 payload.length = length;
1849 payload.write = true;
1850 cmd.payloads = &payload;
1852 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1853 pipe_ctx->stream->link, &cmd))
1859 static void write_i2c_retimer_setting(
1860 struct pipe_ctx *pipe_ctx,
1862 bool is_over_340mhz,
1863 struct ext_hdmi_settings *settings)
1865 uint8_t slave_address = (settings->slv_addr >> 1);
1867 const uint8_t apply_rx_tx_change = 0x4;
1868 uint8_t offset = 0xA;
1871 bool i2c_success = false;
1872 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1874 memset(&buffer, 0, sizeof(buffer));
1876 /* Start Ext-Hdmi programming*/
1878 for (i = 0; i < settings->reg_num; i++) {
1879 /* Apply 3G settings */
1880 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1882 buffer[0] = settings->reg_settings[i].i2c_reg_index;
1883 buffer[1] = settings->reg_settings[i].i2c_reg_val;
1884 i2c_success = i2c_write(pipe_ctx, slave_address,
1885 buffer, sizeof(buffer));
1886 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1887 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1888 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1891 goto i2c_write_fail;
1893 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1894 * needs to be set to 1 on every 0xA-0xC write.
1896 if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1897 settings->reg_settings[i].i2c_reg_index == 0xB ||
1898 settings->reg_settings[i].i2c_reg_index == 0xC) {
1900 /* Query current value from offset 0xA */
1901 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1902 value = settings->reg_settings[i].i2c_reg_val;
1905 dal_ddc_service_query_ddc_data(
1906 pipe_ctx->stream->link->ddc,
1907 slave_address, &offset, 1, &value, 1);
1909 goto i2c_write_fail;
1913 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1914 buffer[1] = value | apply_rx_tx_change;
1915 i2c_success = i2c_write(pipe_ctx, slave_address,
1916 buffer, sizeof(buffer));
1917 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1918 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1919 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1921 goto i2c_write_fail;
1926 /* Apply 3G settings */
1927 if (is_over_340mhz) {
1928 for (i = 0; i < settings->reg_num_6g; i++) {
1929 /* Apply 3G settings */
1930 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1932 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1933 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1934 i2c_success = i2c_write(pipe_ctx, slave_address,
1935 buffer, sizeof(buffer));
1936 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1937 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1938 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1941 goto i2c_write_fail;
1943 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1944 * needs to be set to 1 on every 0xA-0xC write.
1946 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1947 settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1948 settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1950 /* Query current value from offset 0xA */
1951 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1952 value = settings->reg_settings_6g[i].i2c_reg_val;
1955 dal_ddc_service_query_ddc_data(
1956 pipe_ctx->stream->link->ddc,
1957 slave_address, &offset, 1, &value, 1);
1959 goto i2c_write_fail;
1963 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1964 buffer[1] = value | apply_rx_tx_change;
1965 i2c_success = i2c_write(pipe_ctx, slave_address,
1966 buffer, sizeof(buffer));
1967 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1968 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1969 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1971 goto i2c_write_fail;
1978 /* Program additional settings if using 640x480 resolution */
1980 /* Write offset 0xFF to 0x01 */
1983 i2c_success = i2c_write(pipe_ctx, slave_address,
1984 buffer, sizeof(buffer));
1985 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1986 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1987 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1989 goto i2c_write_fail;
1991 /* Write offset 0x00 to 0x23 */
1994 i2c_success = i2c_write(pipe_ctx, slave_address,
1995 buffer, sizeof(buffer));
1996 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1997 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1998 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2000 goto i2c_write_fail;
2002 /* Write offset 0xff to 0x00 */
2005 i2c_success = i2c_write(pipe_ctx, slave_address,
2006 buffer, sizeof(buffer));
2007 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2008 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2009 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2011 goto i2c_write_fail;
2018 DC_LOG_DEBUG("Set retimer failed");
2021 static void write_i2c_default_retimer_setting(
2022 struct pipe_ctx *pipe_ctx,
2024 bool is_over_340mhz)
2026 uint8_t slave_address = (0xBA >> 1);
2028 bool i2c_success = false;
2029 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2031 memset(&buffer, 0, sizeof(buffer));
2033 /* Program Slave Address for tuning single integrity */
2034 /* Write offset 0x0A to 0x13 */
2037 i2c_success = i2c_write(pipe_ctx, slave_address,
2038 buffer, sizeof(buffer));
2039 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2040 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2041 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2043 goto i2c_write_fail;
2045 /* Write offset 0x0A to 0x17 */
2048 i2c_success = i2c_write(pipe_ctx, slave_address,
2049 buffer, sizeof(buffer));
2050 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2051 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2052 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2054 goto i2c_write_fail;
2056 /* Write offset 0x0B to 0xDA or 0xD8 */
2058 buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2059 i2c_success = i2c_write(pipe_ctx, slave_address,
2060 buffer, sizeof(buffer));
2061 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2062 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2063 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2065 goto i2c_write_fail;
2067 /* Write offset 0x0A to 0x17 */
2070 i2c_success = i2c_write(pipe_ctx, slave_address,
2071 buffer, sizeof(buffer));
2072 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2073 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2074 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2076 goto i2c_write_fail;
2078 /* Write offset 0x0C to 0x1D or 0x91 */
2080 buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2081 i2c_success = i2c_write(pipe_ctx, slave_address,
2082 buffer, sizeof(buffer));
2083 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2084 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2085 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2087 goto i2c_write_fail;
2089 /* Write offset 0x0A to 0x17 */
2092 i2c_success = i2c_write(pipe_ctx, slave_address,
2093 buffer, sizeof(buffer));
2094 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2095 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2096 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2098 goto i2c_write_fail;
2102 /* Program additional settings if using 640x480 resolution */
2104 /* Write offset 0xFF to 0x01 */
2107 i2c_success = i2c_write(pipe_ctx, slave_address,
2108 buffer, sizeof(buffer));
2109 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2110 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2111 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2113 goto i2c_write_fail;
2115 /* Write offset 0x00 to 0x23 */
2118 i2c_success = i2c_write(pipe_ctx, slave_address,
2119 buffer, sizeof(buffer));
2120 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2121 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2122 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2124 goto i2c_write_fail;
2126 /* Write offset 0xff to 0x00 */
2129 i2c_success = i2c_write(pipe_ctx, slave_address,
2130 buffer, sizeof(buffer));
2131 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2132 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2133 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2135 goto i2c_write_fail;
2141 DC_LOG_DEBUG("Set default retimer failed");
2144 static void write_i2c_redriver_setting(
2145 struct pipe_ctx *pipe_ctx,
2146 bool is_over_340mhz)
2148 uint8_t slave_address = (0xF0 >> 1);
2150 bool i2c_success = false;
2151 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2153 memset(&buffer, 0, sizeof(buffer));
2155 // Program Slave Address for tuning single integrity
2159 buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2161 i2c_success = i2c_write(pipe_ctx, slave_address,
2162 buffer, sizeof(buffer));
2163 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2164 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2165 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2166 i2c_success = %d\n",
2167 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2170 DC_LOG_DEBUG("Set redriver failed");
2173 static void disable_link(struct dc_link *link, enum signal_type signal)
2176 * TODO: implement call for dp_set_hw_test_pattern
2177 * it is needed for compliance testing
2180 /* Here we need to specify that encoder output settings
2181 * need to be calculated as for the set mode,
2182 * it will lead to querying dynamic link capabilities
2183 * which should be done before enable output
2186 if (dc_is_dp_signal(signal)) {
2188 if (dc_is_dp_sst_signal(signal))
2189 dp_disable_link_phy(link, signal);
2191 dp_disable_link_phy_mst(link, signal);
2193 if (dc_is_dp_sst_signal(signal) ||
2194 link->mst_stream_alloc_table.stream_count == 0) {
2195 dp_set_fec_enable(link, false);
2196 dp_set_fec_ready(link, false);
2199 if (signal != SIGNAL_TYPE_VIRTUAL)
2200 link->link_enc->funcs->disable_output(link->link_enc, signal);
2203 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2204 /* MST disable link only when no stream use the link */
2205 if (link->mst_stream_alloc_table.stream_count <= 0)
2206 link->link_status.link_active = false;
2208 link->link_status.link_active = false;
2212 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2214 struct dc_stream_state *stream = pipe_ctx->stream;
2215 struct dc_link *link = stream->link;
2216 enum dc_color_depth display_color_depth;
2217 enum engine_id eng_id;
2218 struct ext_hdmi_settings settings = {0};
2219 bool is_over_340mhz = false;
2220 bool is_vga_mode = (stream->timing.h_addressable == 640)
2221 && (stream->timing.v_addressable == 480);
2223 if (stream->phy_pix_clk == 0)
2224 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2225 if (stream->phy_pix_clk > 340000)
2226 is_over_340mhz = true;
2228 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2229 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2230 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2231 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2232 /* DP159, Retimer settings */
2233 eng_id = pipe_ctx->stream_res.stream_enc->id;
2235 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2236 write_i2c_retimer_setting(pipe_ctx,
2237 is_vga_mode, is_over_340mhz, &settings);
2239 write_i2c_default_retimer_setting(pipe_ctx,
2240 is_vga_mode, is_over_340mhz);
2242 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2243 /* PI3EQX1204, Redriver settings */
2244 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2248 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2249 dal_ddc_service_write_scdc_data(
2251 stream->phy_pix_clk,
2252 stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2254 memset(&stream->link->cur_link_settings, 0,
2255 sizeof(struct dc_link_settings));
2257 display_color_depth = stream->timing.display_color_depth;
2258 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2259 display_color_depth = COLOR_DEPTH_888;
2261 link->link_enc->funcs->enable_tmds_output(
2263 pipe_ctx->clock_source->id,
2264 display_color_depth,
2265 pipe_ctx->stream->signal,
2266 stream->phy_pix_clk);
2268 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2269 dal_ddc_service_read_scdc_data(link->ddc);
2272 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2274 struct dc_stream_state *stream = pipe_ctx->stream;
2275 struct dc_link *link = stream->link;
2277 if (stream->phy_pix_clk == 0)
2278 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2280 memset(&stream->link->cur_link_settings, 0,
2281 sizeof(struct dc_link_settings));
2283 link->link_enc->funcs->enable_lvds_output(
2285 pipe_ctx->clock_source->id,
2286 stream->phy_pix_clk);
2290 /****************************enable_link***********************************/
2291 static enum dc_status enable_link(
2292 struct dc_state *state,
2293 struct pipe_ctx *pipe_ctx)
2295 enum dc_status status = DC_ERROR_UNEXPECTED;
2296 struct dc_stream_state *stream = pipe_ctx->stream;
2297 struct dc_link *link = stream->link;
2299 /* There's some scenarios where driver is unloaded with display
2300 * still enabled. When driver is reloaded, it may cause a display
2301 * to not light up if there is a mismatch between old and new
2302 * link settings. Need to call disable first before enabling at
2303 * new link settings.
2305 if (link->link_status.link_active) {
2306 disable_link(link, pipe_ctx->stream->signal);
2309 switch (pipe_ctx->stream->signal) {
2310 case SIGNAL_TYPE_DISPLAY_PORT:
2311 status = enable_link_dp(state, pipe_ctx);
2313 case SIGNAL_TYPE_EDP:
2314 status = enable_link_edp(state, pipe_ctx);
2316 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2317 status = enable_link_dp_mst(state, pipe_ctx);
2320 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2321 case SIGNAL_TYPE_DVI_DUAL_LINK:
2322 case SIGNAL_TYPE_HDMI_TYPE_A:
2323 enable_link_hdmi(pipe_ctx);
2326 case SIGNAL_TYPE_LVDS:
2327 enable_link_lvds(pipe_ctx);
2330 case SIGNAL_TYPE_VIRTUAL:
2337 if (status == DC_OK)
2338 pipe_ctx->stream->link->link_status.link_active = true;
2343 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2346 uint32_t pxl_clk = timing->pix_clk_100hz;
2348 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2350 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2351 pxl_clk = pxl_clk * 2 / 3;
2353 if (timing->display_color_depth == COLOR_DEPTH_101010)
2354 pxl_clk = pxl_clk * 10 / 8;
2355 else if (timing->display_color_depth == COLOR_DEPTH_121212)
2356 pxl_clk = pxl_clk * 12 / 8;
2361 static bool dp_active_dongle_validate_timing(
2362 const struct dc_crtc_timing *timing,
2363 const struct dpcd_caps *dpcd_caps)
2365 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2367 switch (dpcd_caps->dongle_type) {
2368 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2369 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2370 case DISPLAY_DONGLE_DP_DVI_DONGLE:
2371 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2379 if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2380 dongle_caps->extendedCapValid == false)
2383 /* Check Pixel Encoding */
2384 switch (timing->pixel_encoding) {
2385 case PIXEL_ENCODING_RGB:
2386 case PIXEL_ENCODING_YCBCR444:
2388 case PIXEL_ENCODING_YCBCR422:
2389 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2392 case PIXEL_ENCODING_YCBCR420:
2393 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2397 /* Invalid Pixel Encoding*/
2401 switch (timing->display_color_depth) {
2402 case COLOR_DEPTH_666:
2403 case COLOR_DEPTH_888:
2404 /*888 and 666 should always be supported*/
2406 case COLOR_DEPTH_101010:
2407 if (dongle_caps->dp_hdmi_max_bpc < 10)
2410 case COLOR_DEPTH_121212:
2411 if (dongle_caps->dp_hdmi_max_bpc < 12)
2414 case COLOR_DEPTH_141414:
2415 case COLOR_DEPTH_161616:
2417 /* These color depths are currently not supported */
2421 if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2427 enum dc_status dc_link_validate_mode_timing(
2428 const struct dc_stream_state *stream,
2429 struct dc_link *link,
2430 const struct dc_crtc_timing *timing)
2432 uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2433 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2435 /* A hack to avoid failing any modes for EDID override feature on
2436 * topology change such as lower quality cable for DP or different dongle
2438 if (link->remote_sinks[0])
2441 /* Passive Dongle */
2442 if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2443 return DC_EXCEED_DONGLE_CAP;
2446 if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2447 return DC_EXCEED_DONGLE_CAP;
2449 switch (stream->signal) {
2450 case SIGNAL_TYPE_EDP:
2451 case SIGNAL_TYPE_DISPLAY_PORT:
2452 if (!dp_validate_mode_timing(
2455 return DC_NO_DP_LINK_BANDWIDTH;
2465 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2468 struct dc *dc = link->ctx->dc;
2469 struct abm *abm = NULL;
2471 for (i = 0; i < MAX_PIPES; i++) {
2472 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2473 struct dc_stream_state *stream = pipe_ctx.stream;
2475 if (stream && stream->link == link) {
2476 abm = pipe_ctx.stream_res.abm;
2483 int dc_link_get_backlight_level(const struct dc_link *link)
2486 struct abm *abm = get_abm_from_stream_res(link);
2488 if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2489 return DC_ERROR_UNEXPECTED;
2491 return (int) abm->funcs->get_current_backlight(abm);
2494 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
2496 struct abm *abm = get_abm_from_stream_res(link);
2498 if (abm == NULL || abm->funcs->get_target_backlight == NULL)
2499 return DC_ERROR_UNEXPECTED;
2501 return (int) abm->funcs->get_target_backlight(abm);
2504 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
2507 struct dc *dc = link->ctx->dc;
2508 struct pipe_ctx *pipe_ctx = NULL;
2510 for (i = 0; i < MAX_PIPES; i++) {
2511 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
2512 if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
2513 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2522 bool dc_link_set_backlight_level(const struct dc_link *link,
2523 uint32_t backlight_pwm_u16_16,
2524 uint32_t frame_ramp)
2526 struct dc *dc = link->ctx->dc;
2528 DC_LOGGER_INIT(link->ctx->logger);
2529 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2530 backlight_pwm_u16_16, backlight_pwm_u16_16);
2532 if (dc_is_embedded_signal(link->connector_signal)) {
2533 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
2536 /* Disable brightness ramping when the display is blanked
2537 * as it can hang the DMCU
2539 if (pipe_ctx->plane_state == NULL)
2546 dc->hwss.set_backlight_level(
2548 backlight_pwm_u16_16,
2554 bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool wait)
2556 struct dc *dc = link->ctx->dc;
2557 struct dmcu *dmcu = dc->res_pool->dmcu;
2558 struct dmub_psr *psr = dc->res_pool->psr;
2560 if (psr != NULL && link->psr_settings.psr_feature_enabled)
2561 psr->funcs->psr_enable(psr, allow_active);
2562 else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
2563 dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
2565 link->psr_settings.psr_allow_active = allow_active;
2570 bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
2572 struct dc *dc = link->ctx->dc;
2573 struct dmcu *dmcu = dc->res_pool->dmcu;
2574 struct dmub_psr *psr = dc->res_pool->psr;
2576 if (psr != NULL && link->psr_settings.psr_feature_enabled)
2577 psr->funcs->psr_get_state(psr, psr_state);
2578 else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
2579 dmcu->funcs->get_psr_state(dmcu, psr_state);
2584 static inline enum physical_phy_id
2585 transmitter_to_phy_id(enum transmitter transmitter_value)
2587 switch (transmitter_value) {
2588 case TRANSMITTER_UNIPHY_A:
2590 case TRANSMITTER_UNIPHY_B:
2592 case TRANSMITTER_UNIPHY_C:
2594 case TRANSMITTER_UNIPHY_D:
2596 case TRANSMITTER_UNIPHY_E:
2598 case TRANSMITTER_UNIPHY_F:
2600 case TRANSMITTER_NUTMEG_CRT:
2602 case TRANSMITTER_TRAVIS_CRT:
2604 case TRANSMITTER_TRAVIS_LCD:
2606 case TRANSMITTER_UNIPHY_G:
2608 case TRANSMITTER_COUNT:
2610 case TRANSMITTER_UNKNOWN:
2611 return PHYLD_UNKNOWN;
2613 WARN_ONCE(1, "Unknown transmitter value %d\n",
2615 return PHYLD_UNKNOWN;
2619 bool dc_link_setup_psr(struct dc_link *link,
2620 const struct dc_stream_state *stream, struct psr_config *psr_config,
2621 struct psr_context *psr_context)
2625 struct dmub_psr *psr;
2627 /* updateSinkPsrDpcdConfig*/
2628 union dpcd_psr_configuration psr_configuration;
2630 psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
2636 dmcu = dc->res_pool->dmcu;
2637 psr = dc->res_pool->psr;
2643 memset(&psr_configuration, 0, sizeof(psr_configuration));
2645 psr_configuration.bits.ENABLE = 1;
2646 psr_configuration.bits.CRC_VERIFICATION = 1;
2647 psr_configuration.bits.FRAME_CAPTURE_INDICATION =
2648 psr_config->psr_frame_capture_indication_req;
2650 /* Check for PSR v2*/
2651 if (psr_config->psr_version == 0x2) {
2652 /* For PSR v2 selective update.
2653 * Indicates whether sink should start capturing
2654 * immediately following active scan line,
2655 * or starting with the 2nd active scan line.
2657 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
2658 /*For PSR v2, determines whether Sink should generate
2659 * IRQ_HPD when CRC mismatch is detected.
2661 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1;
2664 dm_helpers_dp_write_dpcd(
2668 &psr_configuration.raw,
2669 sizeof(psr_configuration.raw));
2671 psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
2672 psr_context->transmitterId = link->link_enc->transmitter;
2673 psr_context->engineId = link->link_enc->preferred_engine;
2675 for (i = 0; i < MAX_PIPES; i++) {
2676 if (dc->current_state->res_ctx.pipe_ctx[i].stream
2678 /* dmcu -1 for all controller id values,
2681 psr_context->controllerId =
2682 dc->current_state->res_ctx.
2683 pipe_ctx[i].stream_res.tg->inst + 1;
2688 /* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/
2689 psr_context->phyType = PHY_TYPE_UNIPHY;
2690 /*PhyId is associated with the transmitter id*/
2691 psr_context->smuPhyId =
2692 transmitter_to_phy_id(link->link_enc->transmitter);
2694 psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
2695 psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
2696 timing.pix_clk_100hz * 100),
2697 stream->timing.v_total),
2698 stream->timing.h_total);
2700 psr_context->psrSupportedDisplayConfig = true;
2701 psr_context->psrExitLinkTrainingRequired =
2702 psr_config->psr_exit_link_training_required;
2703 psr_context->sdpTransmitLineNumDeadline =
2704 psr_config->psr_sdp_transmit_line_num_deadline;
2705 psr_context->psrFrameCaptureIndicationReq =
2706 psr_config->psr_frame_capture_indication_req;
2708 psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
2710 psr_context->numberOfControllers =
2711 link->dc->res_pool->timing_generator_count;
2713 psr_context->rfb_update_auto_en = true;
2715 /* 2 frames before enter PSR. */
2716 psr_context->timehyst_frames = 2;
2718 * (units in 100 lines, i.e. a value of 1 represents 100 lines)
2720 psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
2721 psr_context->aux_repeats = 10;
2723 psr_context->psr_level.u32all = 0;
2725 #if defined(CONFIG_DRM_AMD_DC_DCN)
2726 /*skip power down the single pipe since it blocks the cstate*/
2727 if (ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
2728 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
2731 /* SMU will perform additional powerdown sequence.
2732 * For unsupported ASICs, set psr_level flag to skip PSR
2733 * static screen notification to SMU.
2734 * (Always set for DAL2, did not check ASIC)
2736 psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
2738 /* Complete PSR entry before aborting to prevent intermittent
2739 * freezes on certain eDPs
2741 psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
2743 /* Controls additional delay after remote frame capture before
2744 * continuing power down, default = 0
2746 psr_context->frame_delay = 0;
2749 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context);
2751 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
2753 /* psr_enabled == 0 indicates setup_psr did not succeed, but this
2754 * should not happen since firmware should be running at this point
2756 if (link->psr_settings.psr_feature_enabled == 0)
2763 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2765 return &link->link_status;
2768 void core_link_resume(struct dc_link *link)
2770 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2771 program_hpd_filter(link);
2774 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2776 struct fixed31_32 mbytes_per_sec;
2777 uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
2778 &stream->link->cur_link_settings);
2779 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
2781 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2783 return dc_fixpt_div_int(mbytes_per_sec, 54);
2786 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2789 struct fixed31_32 peak_kbps;
2791 uint32_t denominator;
2793 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2796 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2797 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2798 * common multiplier to render an integer PBN for all link rate/lane
2799 * counts combinations
2801 * peak_kbps *= (1006/1000)
2802 * peak_kbps *= (64/54)
2803 * peak_kbps *= 8 convert to bytes
2806 numerator = 64 * PEAK_FACTOR_X1000;
2807 denominator = 54 * 8 * 1000 * 1000;
2809 peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2814 static void update_mst_stream_alloc_table(
2815 struct dc_link *link,
2816 struct stream_encoder *stream_enc,
2817 const struct dp_mst_stream_allocation_table *proposed_table)
2819 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2821 struct link_mst_stream_allocation *dc_alloc;
2826 /* if DRM proposed_table has more than one new payload */
2827 ASSERT(proposed_table->stream_count -
2828 link->mst_stream_alloc_table.stream_count < 2);
2830 /* copy proposed_table to link, add stream encoder */
2831 for (i = 0; i < proposed_table->stream_count; i++) {
2833 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2835 &link->mst_stream_alloc_table.stream_allocations[j];
2837 if (dc_alloc->vcp_id ==
2838 proposed_table->stream_allocations[i].vcp_id) {
2840 work_table[i] = *dc_alloc;
2841 break; /* exit j loop */
2846 if (j == link->mst_stream_alloc_table.stream_count) {
2847 work_table[i].vcp_id =
2848 proposed_table->stream_allocations[i].vcp_id;
2849 work_table[i].slot_count =
2850 proposed_table->stream_allocations[i].slot_count;
2851 work_table[i].stream_enc = stream_enc;
2855 /* update link->mst_stream_alloc_table with work_table */
2856 link->mst_stream_alloc_table.stream_count =
2857 proposed_table->stream_count;
2858 for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2859 link->mst_stream_alloc_table.stream_allocations[i] =
2863 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2864 * because stream_encoder is not exposed to dm
2866 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2868 struct dc_stream_state *stream = pipe_ctx->stream;
2869 struct dc_link *link = stream->link;
2870 struct link_encoder *link_encoder = link->link_enc;
2871 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2872 struct dp_mst_stream_allocation_table proposed_table = {0};
2873 struct fixed31_32 avg_time_slots_per_mtp;
2874 struct fixed31_32 pbn;
2875 struct fixed31_32 pbn_per_slot;
2877 enum act_return_status ret;
2878 DC_LOGGER_INIT(link->ctx->logger);
2880 /* enable_link_dp_mst already check link->enabled_stream_count
2881 * and stream is in link->stream[]. This is called during set mode,
2882 * stream_enc is available.
2885 /* get calculate VC payload for stream: stream_alloc */
2886 if (dm_helpers_dp_mst_write_payload_allocation_table(
2891 update_mst_stream_alloc_table(
2892 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2895 DC_LOG_WARNING("Failed to update"
2896 "MST allocation table for"
2898 pipe_ctx->pipe_idx);
2901 "stream_count: %d: \n ",
2903 link->mst_stream_alloc_table.stream_count);
2905 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2906 DC_LOG_MST("stream_enc[%d]: %p "
2907 "stream[%d].vcp_id: %d "
2908 "stream[%d].slot_count: %d\n",
2910 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2912 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2914 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2917 ASSERT(proposed_table.stream_count > 0);
2919 /* program DP source TX for payload */
2920 link_encoder->funcs->update_mst_stream_allocation_table(
2922 &link->mst_stream_alloc_table);
2924 /* send down message */
2925 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2929 if (ret != ACT_LINK_LOST) {
2930 dm_helpers_dp_mst_send_payload_allocation(
2936 /* slot X.Y for only current stream */
2937 pbn_per_slot = get_pbn_per_slot(stream);
2938 pbn = get_pbn_from_timing(pipe_ctx);
2939 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2941 stream_encoder->funcs->set_mst_bandwidth(
2943 avg_time_slots_per_mtp);
2949 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2951 struct dc_stream_state *stream = pipe_ctx->stream;
2952 struct dc_link *link = stream->link;
2953 struct link_encoder *link_encoder = link->link_enc;
2954 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2955 struct dp_mst_stream_allocation_table proposed_table = {0};
2956 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2958 bool mst_mode = (link->type == dc_connection_mst_branch);
2959 DC_LOGGER_INIT(link->ctx->logger);
2961 /* deallocate_mst_payload is called before disable link. When mode or
2962 * disable/enable monitor, new stream is created which is not in link
2963 * stream[] yet. For this, payload is not allocated yet, so de-alloc
2964 * should not done. For new mode set, map_resources will get engine
2965 * for new stream, so stream_enc->id should be validated until here.
2969 stream_encoder->funcs->set_mst_bandwidth(
2971 avg_time_slots_per_mtp);
2973 /* TODO: which component is responsible for remove payload table? */
2975 if (dm_helpers_dp_mst_write_payload_allocation_table(
2981 update_mst_stream_alloc_table(
2982 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2985 DC_LOG_WARNING("Failed to update"
2986 "MST allocation table for"
2988 pipe_ctx->pipe_idx);
2993 "stream_count: %d: ",
2995 link->mst_stream_alloc_table.stream_count);
2997 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2998 DC_LOG_MST("stream_enc[%d]: %p "
2999 "stream[%d].vcp_id: %d "
3000 "stream[%d].slot_count: %d\n",
3002 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3004 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3006 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3009 link_encoder->funcs->update_mst_stream_allocation_table(
3011 &link->mst_stream_alloc_table);
3014 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3018 dm_helpers_dp_mst_send_payload_allocation(
3027 enum dc_status dc_link_reallocate_mst_payload(struct dc_link *link)
3030 struct pipe_ctx *pipe_ctx;
3032 // Clear all of MST payload then reallocate
3033 for (i = 0; i < MAX_PIPES; i++) {
3034 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3036 /* driver enable split pipe for external monitors
3037 * we have to check pipe_ctx is split pipe or not
3038 * If it's split pipe, driver using top pipe to
3041 if (!pipe_ctx || pipe_ctx->top_pipe)
3044 if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
3045 pipe_ctx->stream->dpms_off == false &&
3046 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3047 deallocate_mst_payload(pipe_ctx);
3051 for (i = 0; i < MAX_PIPES; i++) {
3052 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3054 if (!pipe_ctx || pipe_ctx->top_pipe)
3057 if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
3058 pipe_ctx->stream->dpms_off == false &&
3059 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3060 /* enable/disable PHY will clear connection between BE and FE
3061 * need to restore it.
3063 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
3064 pipe_ctx->stream_res.stream_enc->id, true);
3065 dc_link_allocate_mst_payload(pipe_ctx);
3072 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3073 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3075 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3076 if (cp_psp && cp_psp->funcs.update_stream_config) {
3077 struct cp_psp_stream_config config;
3079 memset(&config, 0, sizeof(config));
3081 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3083 config.stream_enc_inst = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3084 config.link_enc_inst = pipe_ctx->stream->link->link_enc_hw_inst;
3085 config.dpms_off = dpms_off;
3086 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
3087 config.mst_supported = (pipe_ctx->stream->signal ==
3088 SIGNAL_TYPE_DISPLAY_PORT_MST);
3089 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
3094 void core_link_enable_stream(
3095 struct dc_state *state,
3096 struct pipe_ctx *pipe_ctx)
3098 struct dc *dc = pipe_ctx->stream->ctx->dc;
3099 struct dc_stream_state *stream = pipe_ctx->stream;
3100 enum dc_status status;
3101 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
3103 if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3104 dc_is_virtual_signal(pipe_ctx->stream->signal))
3107 if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3108 stream->link->link_enc->funcs->setup(
3109 stream->link->link_enc,
3110 pipe_ctx->stream->signal);
3111 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
3112 pipe_ctx->stream_res.stream_enc,
3113 pipe_ctx->stream_res.tg->inst,
3114 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
3117 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3118 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
3119 pipe_ctx->stream_res.stream_enc,
3121 stream->output_color_space,
3122 stream->use_vsc_sdp_for_colorimetry,
3123 stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
3125 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
3126 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
3127 pipe_ctx->stream_res.stream_enc,
3129 stream->phy_pix_clk,
3130 pipe_ctx->stream_res.audio != NULL);
3132 pipe_ctx->stream->link->link_state_valid = true;
3134 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
3135 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
3136 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
3139 if (dc_is_dvi_signal(pipe_ctx->stream->signal))
3140 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
3141 pipe_ctx->stream_res.stream_enc,
3143 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
3146 if (dc_is_lvds_signal(pipe_ctx->stream->signal))
3147 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
3148 pipe_ctx->stream_res.stream_enc,
3151 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
3152 bool apply_edp_fast_boot_optimization =
3153 pipe_ctx->stream->apply_edp_fast_boot_optimization;
3155 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
3157 resource_build_info_frame(pipe_ctx);
3158 dc->hwss.update_info_frame(pipe_ctx);
3160 /* Do not touch link on seamless boot optimization. */
3161 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
3162 pipe_ctx->stream->dpms_off = false;
3163 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3164 update_psp_stream_config(pipe_ctx, false);
3169 /* eDP lit up by bios already, no need to enable again. */
3170 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
3171 apply_edp_fast_boot_optimization) {
3172 pipe_ctx->stream->dpms_off = false;
3173 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3174 update_psp_stream_config(pipe_ctx, false);
3179 if (pipe_ctx->stream->dpms_off)
3182 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
3183 * link training). This is to make sure the bandwidth sent to DIG BE won't be
3184 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
3185 * will be automatically set at a later time when the video is enabled
3186 * (DP_VID_STREAM_EN = 1).
3188 if (pipe_ctx->stream->timing.flags.DSC) {
3189 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3190 dc_is_virtual_signal(pipe_ctx->stream->signal))
3191 dp_set_dsc_enable(pipe_ctx, true);
3194 status = enable_link(state, pipe_ctx);
3196 if (status != DC_OK) {
3197 DC_LOG_WARNING("enabling link %u failed: %d\n",
3198 pipe_ctx->stream->link->link_index,
3201 /* Abort stream enable *unless* the failure was due to
3202 * DP link training - some DP monitors will recover and
3203 * show the stream anyway. But MST displays can't proceed
3204 * without link training.
3206 if (status != DC_FAIL_DP_LINK_TRAINING ||
3207 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3208 BREAK_TO_DEBUGGER();
3213 dc->hwss.enable_audio_stream(pipe_ctx);
3215 /* turn off otg test pattern if enable */
3216 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3217 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3218 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3219 COLOR_DEPTH_UNDEFINED);
3221 /* This second call is needed to reconfigure the DIG
3222 * as a workaround for the incorrect value being applied
3223 * from transmitter control.
3225 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
3226 stream->link->link_enc->funcs->setup(
3227 stream->link->link_enc,
3228 pipe_ctx->stream->signal);
3230 dc->hwss.enable_stream(pipe_ctx);
3232 /* Set DPS PPS SDP (AKA "info frames") */
3233 if (pipe_ctx->stream->timing.flags.DSC) {
3234 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3235 dc_is_virtual_signal(pipe_ctx->stream->signal))
3236 dp_set_dsc_pps_sdp(pipe_ctx, true);
3239 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3240 dc_link_allocate_mst_payload(pipe_ctx);
3242 dc->hwss.unblank_stream(pipe_ctx,
3243 &pipe_ctx->stream->link->cur_link_settings);
3245 if (stream->sink_patches.delay_ignore_msa > 0)
3246 msleep(stream->sink_patches.delay_ignore_msa);
3248 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3249 enable_stream_features(pipe_ctx);
3250 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3251 update_psp_stream_config(pipe_ctx, false);
3253 } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
3254 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3255 dc_is_virtual_signal(pipe_ctx->stream->signal))
3256 dp_set_dsc_enable(pipe_ctx, true);
3260 if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3261 core_link_set_avmute(pipe_ctx, false);
3265 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
3267 struct dc *dc = pipe_ctx->stream->ctx->dc;
3268 struct dc_stream_state *stream = pipe_ctx->stream;
3269 struct dc_link *link = stream->sink->link;
3271 if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3272 dc_is_virtual_signal(pipe_ctx->stream->signal))
3275 if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3276 core_link_set_avmute(pipe_ctx, true);
3279 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3280 update_psp_stream_config(pipe_ctx, true);
3283 dc->hwss.blank_stream(pipe_ctx);
3285 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3286 deallocate_mst_payload(pipe_ctx);
3288 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
3289 struct ext_hdmi_settings settings = {0};
3290 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
3292 unsigned short masked_chip_caps = link->chip_caps &
3293 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
3294 //Need to inform that sink is going to use legacy HDMI mode.
3295 dal_ddc_service_write_scdc_data(
3297 165000,//vbios only handles 165Mhz.
3299 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
3300 /* DP159, Retimer settings */
3301 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
3302 write_i2c_retimer_setting(pipe_ctx,
3303 false, false, &settings);
3305 write_i2c_default_retimer_setting(pipe_ctx,
3307 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
3308 /* PI3EQX1204, Redriver settings */
3309 write_i2c_redriver_setting(pipe_ctx, false);
3312 dc->hwss.disable_stream(pipe_ctx);
3314 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
3315 if (pipe_ctx->stream->timing.flags.DSC) {
3316 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3317 dp_set_dsc_enable(pipe_ctx, false);
3321 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
3323 struct dc *dc = pipe_ctx->stream->ctx->dc;
3325 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
3328 dc->hwss.set_avmute(pipe_ctx, enable);
3332 *****************************************************************************
3333 * Function: dc_link_enable_hpd_filter
3336 * If enable is true, programs HPD filter on associated HPD line using
3337 * delay_on_disconnect/delay_on_connect values dependent on
3338 * link->connector_signal
3340 * If enable is false, programs HPD filter on associated HPD line with no
3341 * delays on connect or disconnect
3343 * @param [in] link: pointer to the dc link
3344 * @param [in] enable: boolean specifying whether to enable hbd
3345 *****************************************************************************
3347 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
3352 link->is_hpd_filter_disabled = false;
3353 program_hpd_filter(link);
3355 link->is_hpd_filter_disabled = true;
3356 /* Obtain HPD handle */
3357 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
3362 /* Setup HPD filtering */
3363 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
3364 struct gpio_hpd_config config;
3366 config.delay_on_connect = 0;
3367 config.delay_on_disconnect = 0;
3369 dal_irq_setup_hpd_filter(hpd, &config);
3371 dal_gpio_close(hpd);
3373 ASSERT_CRITICAL(false);
3375 /* Release HPD handle */
3376 dal_gpio_destroy_irq(&hpd);
3380 uint32_t dc_bandwidth_in_kbps_from_timing(
3381 const struct dc_crtc_timing *timing)
3383 uint32_t bits_per_channel = 0;
3386 if (timing->flags.DSC) {
3387 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
3388 kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
3392 switch (timing->display_color_depth) {
3393 case COLOR_DEPTH_666:
3394 bits_per_channel = 6;
3396 case COLOR_DEPTH_888:
3397 bits_per_channel = 8;
3399 case COLOR_DEPTH_101010:
3400 bits_per_channel = 10;
3402 case COLOR_DEPTH_121212:
3403 bits_per_channel = 12;
3405 case COLOR_DEPTH_141414:
3406 bits_per_channel = 14;
3408 case COLOR_DEPTH_161616:
3409 bits_per_channel = 16;
3415 ASSERT(bits_per_channel != 0);
3417 kbps = timing->pix_clk_100hz / 10;
3418 kbps *= bits_per_channel;
3420 if (timing->flags.Y_ONLY != 1) {
3421 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
3423 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3425 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
3426 kbps = kbps * 2 / 3;
3433 void dc_link_set_drive_settings(struct dc *dc,
3434 struct link_training_settings *lt_settings,
3435 const struct dc_link *link)
3440 for (i = 0; i < dc->link_count; i++) {
3441 if (dc->links[i] == link)
3445 if (i >= dc->link_count)
3446 ASSERT_CRITICAL(false);
3448 dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
3451 void dc_link_perform_link_training(struct dc *dc,
3452 struct dc_link_settings *link_setting,
3453 bool skip_video_pattern)
3457 for (i = 0; i < dc->link_count; i++)
3458 dc_link_dp_perform_link_training(
3461 skip_video_pattern);
3464 void dc_link_set_preferred_link_settings(struct dc *dc,
3465 struct dc_link_settings *link_setting,
3466 struct dc_link *link)
3469 struct pipe_ctx *pipe;
3470 struct dc_stream_state *link_stream;
3471 struct dc_link_settings store_settings = *link_setting;
3473 link->preferred_link_setting = store_settings;
3475 /* Retrain with preferred link settings only relevant for
3477 * Check for non-DP signal or if passive dongle present
3479 if (!dc_is_dp_signal(link->connector_signal) ||
3480 link->dongle_max_pix_clk > 0)
3483 for (i = 0; i < MAX_PIPES; i++) {
3484 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3485 if (pipe->stream && pipe->stream->link) {
3486 if (pipe->stream->link == link) {
3487 link_stream = pipe->stream;
3493 /* Stream not found */
3497 /* Cannot retrain link if backend is off */
3498 if (link_stream->dpms_off)
3501 decide_link_settings(link_stream, &store_settings);
3503 if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3504 (store_settings.link_rate != LINK_RATE_UNKNOWN))
3505 dp_retrain_link_dp_test(link, &store_settings, false);
3508 void dc_link_set_preferred_training_settings(struct dc *dc,
3509 struct dc_link_settings *link_setting,
3510 struct dc_link_training_overrides *lt_overrides,
3511 struct dc_link *link,
3512 bool skip_immediate_retrain)
3514 if (lt_overrides != NULL)
3515 link->preferred_training_settings = *lt_overrides;
3517 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
3519 if (link_setting != NULL) {
3520 link->preferred_link_setting = *link_setting;
3522 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3523 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3526 /* Retrain now, or wait until next stream update to apply */
3527 if (skip_immediate_retrain == false)
3528 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
3531 void dc_link_enable_hpd(const struct dc_link *link)
3533 dc_link_dp_enable_hpd(link);
3536 void dc_link_disable_hpd(const struct dc_link *link)
3538 dc_link_dp_disable_hpd(link);
3541 void dc_link_set_test_pattern(struct dc_link *link,
3542 enum dp_test_pattern test_pattern,
3543 enum dp_test_pattern_color_space test_pattern_color_space,
3544 const struct link_training_settings *p_link_settings,
3545 const unsigned char *p_custom_pattern,
3546 unsigned int cust_pattern_size)
3549 dc_link_dp_set_test_pattern(
3552 test_pattern_color_space,
3558 uint32_t dc_link_bandwidth_kbps(
3559 const struct dc_link *link,
3560 const struct dc_link_settings *link_setting)
3562 uint32_t link_bw_kbps =
3563 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
3565 link_bw_kbps *= 8; /* 8 bits per byte*/
3566 link_bw_kbps *= link_setting->lane_count;
3568 if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec) {
3569 /* Account for FEC overhead.
3570 * We have to do it based on caps,
3571 * and not based on FEC being set ready,
3572 * because FEC is set ready too late in
3573 * the process to correctly be picked up
3574 * by mode enumeration.
3576 * There's enough zeros at the end of 'kbps'
3577 * that make the below operation 100% precise
3579 * 'long long' makes it work even for HDMI 2.1
3580 * max bandwidth (and much, much bigger bandwidths
3581 * than that, actually).
3583 * NOTE: Reducing link BW by 3% may not be precise
3584 * because it may be a stream BT that increases by 3%, and so
3585 * 1/1.03 = 0.970873 factor should have been used instead,
3586 * but the difference is minimal and is in a safe direction,
3587 * which all works well around potential ambiguity of DP 1.4a spec.
3589 link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
3593 return link_bw_kbps;
3597 const struct dc_link_settings *dc_link_get_link_cap(
3598 const struct dc_link *link)
3600 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
3601 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
3602 return &link->preferred_link_setting;
3603 return &link->verified_link_cap;
3606 void dc_link_overwrite_extended_receiver_cap(
3607 struct dc_link *link)
3609 dp_overwrite_extended_receiver_cap(link);
3612 bool dc_link_is_fec_supported(const struct dc_link *link)
3614 return (dc_is_dp_signal(link->connector_signal) &&
3615 link->link_enc->features.fec_supported &&
3616 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
3617 !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));