drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atom.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48
  49 #define DC_LOGGER_INIT(logger)
  50
  51
  52 #define LINK_INFO(...) \
  53         DC_LOG_HW_HOTPLUG(  \
  54                 __VA_ARGS__)
  55
  56 #define RETIMER_REDRIVER_INFO(...) \
  57         DC_LOG_RETIMER_REDRIVER(  \
  58                 __VA_ARGS__)
  59 /*******************************************************************************
  60  * Private structures
  61  ******************************************************************************/
  62
  63 enum {
  64         PEAK_FACTOR_X1000 = 1006,
  65         /*
  66         * Some receivers fail to train on first try and are good
  67         * on subsequent tries. 2 retries should be plenty. If we
  68         * don't have a successful training then we don't expect to
  69         * ever get one.
  70         */
  71         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  72 };
  73
  74 /*******************************************************************************
  75  * Private functions
  76  ******************************************************************************/
  77 static void destruct(struct dc_link *link)
  78 {
  79         int i;
  80
  81         if (link->hpd_gpio != NULL) {
  82                 dal_gpio_destroy_irq(&link->hpd_gpio);
  83                 link->hpd_gpio = NULL;
  84         }
  85
  86         if (link->ddc)
  87                 dal_ddc_service_destroy(&link->ddc);
  88
  89         if(link->link_enc)
  90                 link->link_enc->funcs->destroy(&link->link_enc);
  91
  92         if (link->local_sink)
  93                 dc_sink_release(link->local_sink);
  94
  95         for (i = 0; i < link->sink_count; ++i)
  96                 dc_sink_release(link->remote_sinks[i]);
  97 }
  98
  99 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 100                 struct graphics_object_id link_id,
 101                 struct gpio_service *gpio_service)
 102 {
 103         enum bp_result bp_result;
 104         struct graphics_object_hpd_info hpd_info;
 105         struct gpio_pin_info pin_info;
 106
 107         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 108                 return NULL;
 109
 110         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 111                 hpd_info.hpd_int_gpio_uid, &pin_info);
 112
 113         if (bp_result != BP_RESULT_OK) {
 114                 ASSERT(bp_result == BP_RESULT_NORECORD);
 115                 return NULL;
 116         }
 117
 118         return dal_gpio_service_create_irq(
 119                 gpio_service,
 120                 pin_info.offset,
 121                 pin_info.mask);
 122 }
 123
 124 /*
 125  *  Function: program_hpd_filter
 126  *
 127  *  @brief
 128  *     Programs HPD filter on associated HPD line
 129  *
 130  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 131  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 132  *
 133  *  @return
 134  *     true on success, false otherwise
 135  */
 136 static bool program_hpd_filter(
 137         const struct dc_link *link)
 138 {
 139         bool result = false;
 140
 141         struct gpio *hpd;
 142
 143         int delay_on_connect_in_ms = 0;
 144         int delay_on_disconnect_in_ms = 0;
 145
 146         if (link->is_hpd_filter_disabled)
 147                 return false;
 148         /* Verify feature is supported */
 149         switch (link->connector_signal) {
 150         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 151         case SIGNAL_TYPE_DVI_DUAL_LINK:
 152         case SIGNAL_TYPE_HDMI_TYPE_A:
 153                 /* Program hpd filter */
 154                 delay_on_connect_in_ms = 500;
 155                 delay_on_disconnect_in_ms = 100;
 156                 break;
 157         case SIGNAL_TYPE_DISPLAY_PORT:
 158         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 159                 /* Program hpd filter to allow DP signal to settle */
 160                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 161                  *      only 100ms on DELL U2413
 162                  * 0:   some passive dongle still show aux mode instead of i2c
 163                  * 20-50:not enough to hide bouncing HPD with passive dongle.
 164                  *      also see intermittent i2c read issues.
 165                  */
 166                 delay_on_connect_in_ms = 80;
 167                 delay_on_disconnect_in_ms = 0;
 168                 break;
 169         case SIGNAL_TYPE_LVDS:
 170         case SIGNAL_TYPE_EDP:
 171         default:
 172                 /* Don't program hpd filter */
 173                 return false;
 174         }
 175
 176         /* Obtain HPD handle */
 177         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 178
 179         if (!hpd)
 180                 return result;
 181
 182         /* Setup HPD filtering */
 183         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 184                 struct gpio_hpd_config config;
 185
 186                 config.delay_on_connect = delay_on_connect_in_ms;
 187                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 188
 189                 dal_irq_setup_hpd_filter(hpd, &config);
 190
 191                 dal_gpio_close(hpd);
 192
 193                 result = true;
 194         } else {
 195                 ASSERT_CRITICAL(false);
 196         }
 197
 198         /* Release HPD handle */
 199         dal_gpio_destroy_irq(&hpd);
 200
 201         return result;
 202 }
 203
 204 /**
 205  * dc_link_detect_sink() - Determine if there is a sink connected
 206  *
 207  * @type: Returned connection type
 208  * Does not detect downstream devices, such as MST sinks
 209  * or display connected through active dongles
 210  */
 211 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 212 {
 213         uint32_t is_hpd_high = 0;
 214         struct gpio *hpd_pin;
 215
 216         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 217                 *type = dc_connection_single;
 218                 return true;
 219         }
 220
 221         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 222                 /*in case it is not on*/
 223                 link->dc->hwss.edp_power_control(link, true);
 224                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 225         }
 226
 227         /* todo: may need to lock gpio access */
 228         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 229         if (hpd_pin == NULL)
 230                 goto hpd_gpio_failure;
 231
 232         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 233         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 234         dal_gpio_close(hpd_pin);
 235         dal_gpio_destroy_irq(&hpd_pin);
 236
 237         if (is_hpd_high) {
 238                 *type = dc_connection_single;
 239                 /* TODO: need to do the actual detection */
 240         } else {
 241                 *type = dc_connection_none;
 242         }
 243
 244         return true;
 245
 246 hpd_gpio_failure:
 247         return false;
 248 }
 249
 250 static enum ddc_transaction_type get_ddc_transaction_type(
 251                 enum signal_type sink_signal)
 252 {
 253         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 254
 255         switch (sink_signal) {
 256         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 257         case SIGNAL_TYPE_DVI_DUAL_LINK:
 258         case SIGNAL_TYPE_HDMI_TYPE_A:
 259         case SIGNAL_TYPE_LVDS:
 260         case SIGNAL_TYPE_RGB:
 261                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 262                 break;
 263
 264         case SIGNAL_TYPE_DISPLAY_PORT:
 265         case SIGNAL_TYPE_EDP:
 266                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 267                 break;
 268
 269         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 270                 /* MST does not use I2COverAux, but there is the
 271                  * SPECIAL use case for "immediate dwnstrm device
 272                  * access" (EPR#370830). */
 273                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 274                 break;
 275
 276         default:
 277                 break;
 278         }
 279
 280         return transaction_type;
 281 }
 282
 283 static enum signal_type get_basic_signal_type(
 284         struct graphics_object_id encoder,
 285         struct graphics_object_id downstream)
 286 {
 287         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 288                 switch (downstream.id) {
 289                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 290                         switch (encoder.id) {
 291                         case ENCODER_ID_INTERNAL_DAC1:
 292                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 293                         case ENCODER_ID_INTERNAL_DAC2:
 294                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 295                                 return SIGNAL_TYPE_RGB;
 296                         default:
 297                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 298                         }
 299                 break;
 300                 case CONNECTOR_ID_DUAL_LINK_DVII:
 301                 {
 302                         switch (encoder.id) {
 303                         case ENCODER_ID_INTERNAL_DAC1:
 304                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 305                         case ENCODER_ID_INTERNAL_DAC2:
 306                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 307                                 return SIGNAL_TYPE_RGB;
 308                         default:
 309                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 310                         }
 311                 }
 312                 break;
 313                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 314                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 315                 case CONNECTOR_ID_DUAL_LINK_DVID:
 316                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 317                 case CONNECTOR_ID_VGA:
 318                         return SIGNAL_TYPE_RGB;
 319                 case CONNECTOR_ID_HDMI_TYPE_A:
 320                         return SIGNAL_TYPE_HDMI_TYPE_A;
 321                 case CONNECTOR_ID_LVDS:
 322                         return SIGNAL_TYPE_LVDS;
 323                 case CONNECTOR_ID_DISPLAY_PORT:
 324                         return SIGNAL_TYPE_DISPLAY_PORT;
 325                 case CONNECTOR_ID_EDP:
 326                         return SIGNAL_TYPE_EDP;
 327                 default:
 328                         return SIGNAL_TYPE_NONE;
 329                 }
 330         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 331                 switch (downstream.id) {
 332                 case ENCODER_ID_EXTERNAL_NUTMEG:
 333                 case ENCODER_ID_EXTERNAL_TRAVIS:
 334                         return SIGNAL_TYPE_DISPLAY_PORT;
 335                 default:
 336                         return SIGNAL_TYPE_NONE;
 337                 }
 338         }
 339
 340         return SIGNAL_TYPE_NONE;
 341 }
 342
 343 /**
 344  * dc_link_is_dp_sink_present() - Check if there is a native DP
 345  * or passive DP-HDMI dongle connected
 346  */
 347 bool dc_link_is_dp_sink_present(struct dc_link *link)
 348 {
 349         enum gpio_result gpio_result;
 350         uint32_t clock_pin = 0;
 351         uint8_t retry = 0;
 352         struct ddc *ddc;
 353
 354         enum connector_id connector_id =
 355                 dal_graphics_object_id_get_connector_id(link->link_id);
 356
 357         bool present =
 358                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 359                 (connector_id == CONNECTOR_ID_EDP));
 360
 361         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 362
 363         if (!ddc) {
 364                 BREAK_TO_DEBUGGER();
 365                 return present;
 366         }
 367
 368         /* Open GPIO and set it to I2C mode */
 369         /* Note: this GpioMode_Input will be converted
 370          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 371          * which indicates we need additional delay */
 372
 373         if (GPIO_RESULT_OK != dal_ddc_open(
 374                 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
 375                 dal_gpio_destroy_ddc(&ddc);
 376
 377                 return present;
 378         }
 379
 380         /*
 381          * Read GPIO: DP sink is present if both clock and data pins are zero
 382          *
 383          * [W/A] plug-unplug DP cable, sometimes customer board has
 384          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 385          * then monitor can't br light up. Add retry 3 times
 386          * But in real passive dongle, it need additional 3ms to detect
 387          */
 388         do {
 389                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 390                 ASSERT(gpio_result == GPIO_RESULT_OK);
 391                 if (clock_pin)
 392                         udelay(1000);
 393                 else
 394                         break;
 395         } while (retry++ < 3);
 396
 397         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 398
 399         dal_ddc_close(ddc);
 400
 401         return present;
 402 }
 403
 404 /*
 405  * @brief
 406  * Detect output sink type
 407  */
 408 static enum signal_type link_detect_sink(
 409         struct dc_link *link,
 410         enum dc_detect_reason reason)
 411 {
 412         enum signal_type result = get_basic_signal_type(
 413                 link->link_enc->id, link->link_id);
 414
 415         /* Internal digital encoder will detect only dongles
 416          * that require digital signal */
 417
 418         /* Detection mechanism is different
 419          * for different native connectors.
 420          * LVDS connector supports only LVDS signal;
 421          * PCIE is a bus slot, the actual connector needs to be detected first;
 422          * eDP connector supports only eDP signal;
 423          * HDMI should check straps for audio */
 424
 425         /* PCIE detects the actual connector on add-on board */
 426
 427         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 428                 /* ZAZTODO implement PCIE add-on card detection */
 429         }
 430
 431         switch (link->link_id.id) {
 432         case CONNECTOR_ID_HDMI_TYPE_A: {
 433                 /* check audio support:
 434                  * if native HDMI is not supported, switch to DVI */
 435                 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 436
 437                 if (!aud_support->hdmi_audio_native)
 438                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 439                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 440         }
 441         break;
 442         case CONNECTOR_ID_DISPLAY_PORT: {
 443                 /* DP HPD short pulse. Passive DP dongle will not
 444                  * have short pulse
 445                  */
 446                 if (reason != DETECT_REASON_HPDRX) {
 447                         /* Check whether DP signal detected: if not -
 448                          * we assume signal is DVI; it could be corrected
 449                          * to HDMI after dongle detection
 450                          */
 451                         if (!dm_helpers_is_dp_sink_present(link))
 452                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 453                 }
 454         }
 455         break;
 456         default:
 457         break;
 458         }
 459
 460         return result;
 461 }
 462
 463 static enum signal_type decide_signal_from_strap_and_dongle_type(
 464                 enum display_dongle_type dongle_type,
 465                 struct audio_support *audio_support)
 466 {
 467         enum signal_type signal = SIGNAL_TYPE_NONE;
 468
 469         switch (dongle_type) {
 470         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 471                 if (audio_support->hdmi_audio_on_dongle)
 472                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 473                 else
 474                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 475                 break;
 476         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 477                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 478                 break;
 479         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 480                 if (audio_support->hdmi_audio_native)
 481                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 482                 else
 483                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 484                 break;
 485         default:
 486                 signal = SIGNAL_TYPE_NONE;
 487                 break;
 488         }
 489
 490         return signal;
 491 }
 492
 493 static enum signal_type dp_passive_dongle_detection(
 494                 struct ddc_service *ddc,
 495                 struct display_sink_capability *sink_cap,
 496                 struct audio_support *audio_support)
 497 {
 498         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 499                                                 ddc, sink_cap);
 500         return decide_signal_from_strap_and_dongle_type(
 501                         sink_cap->dongle_type,
 502                         audio_support);
 503 }
 504
 505 static void link_disconnect_sink(struct dc_link *link)
 506 {
 507         if (link->local_sink) {
 508                 dc_sink_release(link->local_sink);
 509                 link->local_sink = NULL;
 510         }
 511
 512         link->dpcd_sink_count = 0;
 513 }
 514
 515 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 516 {
 517         dc_sink_release(link->local_sink);
 518         link->local_sink = prev_sink;
 519 }
 520
 521
 522 static void read_current_link_settings_on_detect(struct dc_link *link)
 523 {
 524         union lane_count_set lane_count_set = { {0} };
 525         uint8_t link_bw_set;
 526         uint8_t link_rate_set;
 527         uint32_t read_dpcd_retry_cnt = 10;
 528         enum dc_status status = DC_ERROR_UNEXPECTED;
 529         int i;
 530         union max_down_spread max_down_spread = { {0} };
 531
 532         // Read DPCD 00101h to find out the number of lanes currently set
 533         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 534                 status = core_link_read_dpcd(
 535                                 link,
 536                                 DP_LANE_COUNT_SET,
 537                                 &lane_count_set.raw,
 538                                 sizeof(lane_count_set));
 539                 /* First DPCD read after VDD ON can fail if the particular board
 540                  * does not have HPD pin wired correctly. So if DPCD read fails,
 541                  * which it should never happen, retry a few times. Target worst
 542                  * case scenario of 80 ms.
 543                  */
 544                 if (status == DC_OK) {
 545                         link->cur_link_settings.lane_count = lane_count_set.bits.LANE_COUNT_SET;
 546                         break;
 547                 }
 548
 549                 msleep(8);
 550         }
 551
 552         // Read DPCD 00100h to find if standard link rates are set
 553         core_link_read_dpcd(link, DP_LINK_BW_SET,
 554                         &link_bw_set, sizeof(link_bw_set));
 555
 556         if (link_bw_set == 0) {
 557                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 558                         /* If standard link rates are not being used,
 559                          * Read DPCD 00115h to find the edp link rate set used
 560                          */
 561                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 562                                         &link_rate_set, sizeof(link_rate_set));
 563
 564                         // edp_supported_link_rates_count = 0 for DP
 565                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 566                                 link->cur_link_settings.link_rate =
 567                                                 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 568                                 link->cur_link_settings.link_rate_set = link_rate_set;
 569                                 link->cur_link_settings.use_link_rate_set = true;
 570                         }
 571                 } else {
 572                         // Link Rate not found. Seamless boot may not work.
 573                         ASSERT(false);
 574                 }
 575         } else {
 576                 link->cur_link_settings.link_rate = link_bw_set;
 577                 link->cur_link_settings.use_link_rate_set = false;
 578         }
 579         // Read DPCD 00003h to find the max down spread.
 580         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 581                         &max_down_spread.raw, sizeof(max_down_spread));
 582         link->cur_link_settings.link_spread =
 583                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 584                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 585 }
 586
 587 static bool detect_dp(
 588         struct dc_link *link,
 589         struct display_sink_capability *sink_caps,
 590         bool *converter_disable_audio,
 591         struct audio_support *audio_support,
 592         enum dc_detect_reason reason)
 593 {
 594         bool boot = false;
 595         sink_caps->signal = link_detect_sink(link, reason);
 596         sink_caps->transaction_type =
 597                 get_ddc_transaction_type(sink_caps->signal);
 598
 599         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 600                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 601                 if (!detect_dp_sink_caps(link))
 602                         return false;
 603
 604                 if (is_mst_supported(link)) {
 605                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 606                         link->type = dc_connection_mst_branch;
 607
 608                         dal_ddc_service_set_transaction_type(
 609                                                         link->ddc,
 610                                                         sink_caps->transaction_type);
 611
 612                         /*
 613                          * This call will initiate MST topology discovery. Which
 614                          * will detect MST ports and add new DRM connector DRM
 615                          * framework. Then read EDID via remote i2c over aux. In
 616                          * the end, will notify DRM detect result and save EDID
 617                          * into DRM framework.
 618                          *
 619                          * .detect is called by .fill_modes.
 620                          * .fill_modes is called by user mode ioctl
 621                          * DRM_IOCTL_MODE_GETCONNECTOR.
 622                          *
 623                          * .get_modes is called by .fill_modes.
 624                          *
 625                          * call .get_modes, AMDGPU DM implementation will create
 626                          * new dc_sink and add to dc_link. For long HPD plug
 627                          * in/out, MST has its own handle.
 628                          *
 629                          * Therefore, just after dc_create, link->sink is not
 630                          * created for MST until user mode app calls
 631                          * DRM_IOCTL_MODE_GETCONNECTOR.
 632                          *
 633                          * Need check ->sink usages in case ->sink = NULL
 634                          * TODO: s3 resume check
 635                          */
 636                         if (reason == DETECT_REASON_BOOT)
 637                                 boot = true;
 638
 639                         dm_helpers_dp_update_branch_info(
 640                                 link->ctx,
 641                                 link);
 642
 643                         if (!dm_helpers_dp_mst_start_top_mgr(
 644                                 link->ctx,
 645                                 link, boot)) {
 646                                 /* MST not supported */
 647                                 link->type = dc_connection_single;
 648                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 649                         }
 650                 }
 651
 652                 if (link->type != dc_connection_mst_branch &&
 653                         is_dp_active_dongle(link)) {
 654                         /* DP active dongles */
 655                         link->type = dc_connection_active_dongle;
 656                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 657                                 /*
 658                                  * active dongle unplug processing for short irq
 659                                  */
 660                                 link_disconnect_sink(link);
 661                                 return true;
 662                         }
 663
 664                         if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 665                                 *converter_disable_audio = true;
 666                 }
 667         } else {
 668                 /* DP passive dongles */
 669                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 670                                 sink_caps,
 671                                 audio_support);
 672         }
 673
 674         return true;
 675 }
 676
 677 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 678 {
 679         if (old_edid->length != new_edid->length)
 680                 return false;
 681
 682         if (new_edid->length == 0)
 683                 return false;
 684
 685         return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
 686 }
 687
 688 static bool wait_for_alt_mode(struct dc_link *link)
 689 {
 690
 691         /**
 692          * something is terribly wrong if time out is > 200ms. (5Hz)
 693          * 500 microseconds * 400 tries us 200 ms
 694          **/
 695         unsigned int sleep_time_in_microseconds = 500;
 696         unsigned int tries_allowed = 400;
 697         bool is_in_alt_mode;
 698         unsigned long long enter_timestamp;
 699         unsigned long long finish_timestamp;
 700         unsigned long long time_taken_in_ns;
 701         int tries_taken;
 702
 703         DC_LOGGER_INIT(link->ctx->logger);
 704
 705         if (link->link_enc->funcs->is_in_alt_mode == NULL)
 706                 return true;
 707
 708         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 709         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 710
 711         if (is_in_alt_mode)
 712                 return true;
 713
 714         enter_timestamp = dm_get_timestamp(link->ctx);
 715
 716         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 717                 udelay(sleep_time_in_microseconds);
 718                 /* ask the link if alt mode is enabled, if so return ok */
 719                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 720
 721                         finish_timestamp = dm_get_timestamp(link->ctx);
 722                         time_taken_in_ns = dm_get_elapse_time_in_ns(
 723                                 link->ctx, finish_timestamp, enter_timestamp);
 724                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 725                                        div_u64(time_taken_in_ns, 1000000));
 726                         return true;
 727                 }
 728
 729         }
 730         finish_timestamp = dm_get_timestamp(link->ctx);
 731         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 732                                                     enter_timestamp);
 733         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 734                         div_u64(time_taken_in_ns, 1000000));
 735         return false;
 736 }
 737
 738 /**
 739  * dc_link_detect() - Detect if a sink is attached to a given link
 740  *
 741  * link->local_sink is created or destroyed as needed.
 742  *
 743  * This does not create remote sinks but will trigger DM
 744  * to start MST detection if a branch is detected.
 745  */
 746 static bool dc_link_detect_helper(struct dc_link *link,
 747                                   enum dc_detect_reason reason)
 748 {
 749         struct dc_sink_init_data sink_init_data = { 0 };
 750         struct display_sink_capability sink_caps = { 0 };
 751         uint8_t i;
 752         bool converter_disable_audio = false;
 753         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 754         bool same_edid = false;
 755         enum dc_edid_status edid_status;
 756         struct dc_context *dc_ctx = link->ctx;
 757         struct dc_sink *sink = NULL;
 758         struct dc_sink *prev_sink = NULL;
 759         struct dpcd_caps prev_dpcd_caps;
 760         bool same_dpcd = true;
 761         enum dc_connection_type new_connection_type = dc_connection_none;
 762         bool perform_dp_seamless_boot = false;
 763
 764         DC_LOGGER_INIT(link->ctx->logger);
 765
 766         if (dc_is_virtual_signal(link->connector_signal))
 767                 return false;
 768
 769         if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
 770                         link->connector_signal == SIGNAL_TYPE_EDP) &&
 771                         link->local_sink)
 772                 return true;
 773
 774         if (false == dc_link_detect_sink(link, &new_connection_type)) {
 775                 BREAK_TO_DEBUGGER();
 776                 return false;
 777         }
 778
 779         prev_sink = link->local_sink;
 780         if (prev_sink != NULL) {
 781                 dc_sink_retain(prev_sink);
 782                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 783         }
 784         link_disconnect_sink(link);
 785
 786         if (new_connection_type != dc_connection_none) {
 787                 link->type = new_connection_type;
 788                 link->link_state_valid = false;
 789
 790                 /* From Disconnected-to-Connected. */
 791                 switch (link->connector_signal) {
 792                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 793                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 794                         if (aud_support->hdmi_audio_native)
 795                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 796                         else
 797                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 798                         break;
 799                 }
 800
 801                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 802                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 803                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 804                         break;
 805                 }
 806
 807                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 808                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 809                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 810                         break;
 811                 }
 812
 813                 case SIGNAL_TYPE_LVDS: {
 814                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 815                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 816                         break;
 817                 }
 818
 819                 case SIGNAL_TYPE_EDP: {
 820                         read_current_link_settings_on_detect(link);
 821                         detect_edp_sink_caps(link);
 822                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 823                         sink_caps.signal = SIGNAL_TYPE_EDP;
 824                         break;
 825                 }
 826
 827                 case SIGNAL_TYPE_DISPLAY_PORT: {
 828
 829                         /* wa HPD high coming too early*/
 830                         if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 831
 832                                 /* if alt mode times out, return false */
 833                                 if (wait_for_alt_mode(link) == false) {
 834                                         return false;
 835                                 }
 836                         }
 837
 838                         if (!detect_dp(
 839                                 link,
 840                                 &sink_caps,
 841                                 &converter_disable_audio,
 842                                 aud_support, reason)) {
 843                                 if (prev_sink != NULL)
 844                                         dc_sink_release(prev_sink);
 845                                 return false;
 846                         }
 847
 848                         // Check if dpcp block is the same
 849                         if (prev_sink != NULL) {
 850                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
 851                                         same_dpcd = false;
 852                         }
 853                         /* Active dongle plug in without display or downstream unplug*/
 854                         if (link->type == dc_connection_active_dongle &&
 855                                 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 856                                 if (prev_sink != NULL) {
 857                                         /* Downstream unplug */
 858                                         dc_sink_release(prev_sink);
 859                                 } else {
 860                                         /* Empty dongle plug in */
 861                                         dp_verify_link_cap_with_retries(link,
 862                                                         &link->reported_link_cap,
 863                                                         LINK_TRAINING_MAX_VERIFY_RETRY);
 864                                 }
 865                                 return true;
 866                         }
 867
 868                         if (link->type == dc_connection_mst_branch) {
 869                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 870                                         link->link_index);
 871                                 /* Need to setup mst link_cap struct here
 872                                  * otherwise dc_link_detect() will leave mst link_cap
 873                                  * empty which leads to allocate_mst_payload() has "0"
 874                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 875                                  */
 876                                 dp_verify_mst_link_cap(link);
 877
 878                                 if (prev_sink != NULL)
 879                                         dc_sink_release(prev_sink);
 880                                 return false;
 881                         }
 882
 883                         // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
 884                         if (reason == DETECT_REASON_BOOT &&
 885                                         dc_ctx->dc->config.power_down_display_on_boot == false &&
 886                                         link->link_status.link_active == true)
 887                                 perform_dp_seamless_boot = true;
 888
 889                         if (perform_dp_seamless_boot) {
 890                                 read_current_link_settings_on_detect(link);
 891                                 link->verified_link_cap = link->reported_link_cap;
 892                         }
 893
 894                         break;
 895                 }
 896
 897                 default:
 898                         DC_ERROR("Invalid connector type! signal:%d\n",
 899                                 link->connector_signal);
 900                         if (prev_sink != NULL)
 901                                 dc_sink_release(prev_sink);
 902                         return false;
 903                 } /* switch() */
 904
 905                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
 906                         link->dpcd_sink_count = link->dpcd_caps.sink_count.
 907                                         bits.SINK_COUNT;
 908                 else
 909                         link->dpcd_sink_count = 1;
 910
 911                 dal_ddc_service_set_transaction_type(
 912                                                 link->ddc,
 913                                                 sink_caps.transaction_type);
 914
 915                 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
 916                                 link->ddc);
 917
 918                 sink_init_data.link = link;
 919                 sink_init_data.sink_signal = sink_caps.signal;
 920
 921                 sink = dc_sink_create(&sink_init_data);
 922                 if (!sink) {
 923                         DC_ERROR("Failed to create sink!\n");
 924                         if (prev_sink != NULL)
 925                                 dc_sink_release(prev_sink);
 926                         return false;
 927                 }
 928
 929                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
 930                 sink->converter_disable_audio = converter_disable_audio;
 931
 932                 /* dc_sink_create returns a new reference */
 933                 link->local_sink = sink;
 934
 935                 edid_status = dm_helpers_read_local_edid(
 936                                 link->ctx,
 937                                 link,
 938                                 sink);
 939
 940                 switch (edid_status) {
 941                 case EDID_BAD_CHECKSUM:
 942                         DC_LOG_ERROR("EDID checksum invalid.\n");
 943                         break;
 944                 case EDID_NO_RESPONSE:
 945                         DC_LOG_ERROR("No EDID read.\n");
 946
 947                         /*
 948                          * Abort detection for non-DP connectors if we have
 949                          * no EDID
 950                          *
 951                          * DP needs to report as connected if HDP is high
 952                          * even if we have no EDID in order to go to
 953                          * fail-safe mode
 954                          */
 955                         if (dc_is_hdmi_signal(link->connector_signal) ||
 956                             dc_is_dvi_signal(link->connector_signal)) {
 957                                 if (prev_sink != NULL)
 958                                         dc_sink_release(prev_sink);
 959
 960                                 return false;
 961                         }
 962                 default:
 963                         break;
 964                 }
 965
 966                 // Check if edid is the same
 967                 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
 968                         same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
 969
 970                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 971                         sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX &&
 972                         reason != DETECT_REASON_HPDRX) {
 973                         /*
 974                          * TODO debug why Dell 2413 doesn't like
 975                          *  two link trainings
 976                          */
 977
 978                         // verify link cap for SST non-seamless boot
 979                         if (!perform_dp_seamless_boot)
 980                                 dp_verify_link_cap_with_retries(link,
 981                                                 &link->reported_link_cap,
 982                                                 LINK_TRAINING_MAX_VERIFY_RETRY);
 983                 } else {
 984                         // If edid is the same, then discard new sink and revert back to original sink
 985                         if (same_edid) {
 986                                 link_disconnect_remap(prev_sink, link);
 987                                 sink = prev_sink;
 988                                 prev_sink = NULL;
 989
 990                         }
 991                 }
 992
 993                 /* HDMI-DVI Dongle */
 994                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
 995                                 !sink->edid_caps.edid_hdmi)
 996                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 997
 998                 /* Connectivity log: detection */
 999                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1000                         CONN_DATA_DETECT(link,
1001                                         &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1002                                         DC_EDID_BLOCK_SIZE,
1003                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
1004                 }
1005
1006                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1007                         "manufacturer_id = %X, "
1008                         "product_id = %X, "
1009                         "serial_number = %X, "
1010                         "manufacture_week = %d, "
1011                         "manufacture_year = %d, "
1012                         "display_name = %s, "
1013                         "speaker_flag = %d, "
1014                         "audio_mode_count = %d\n",
1015                         __func__,
1016                         sink->edid_caps.manufacturer_id,
1017                         sink->edid_caps.product_id,
1018                         sink->edid_caps.serial_number,
1019                         sink->edid_caps.manufacture_week,
1020                         sink->edid_caps.manufacture_year,
1021                         sink->edid_caps.display_name,
1022                         sink->edid_caps.speaker_flags,
1023                         sink->edid_caps.audio_mode_count);
1024
1025                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1026                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1027                                 "format_code = %d, "
1028                                 "channel_count = %d, "
1029                                 "sample_rate = %d, "
1030                                 "sample_size = %d\n",
1031                                 __func__,
1032                                 i,
1033                                 sink->edid_caps.audio_modes[i].format_code,
1034                                 sink->edid_caps.audio_modes[i].channel_count,
1035                                 sink->edid_caps.audio_modes[i].sample_rate,
1036                                 sink->edid_caps.audio_modes[i].sample_size);
1037                 }
1038
1039         } else {
1040                 /* From Connected-to-Disconnected. */
1041                 if (link->type == dc_connection_mst_branch) {
1042                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
1043                                 link->link_index);
1044
1045                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1046
1047                         link->mst_stream_alloc_table.stream_count = 0;
1048                         memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
1049                 }
1050
1051                 link->type = dc_connection_none;
1052                 sink_caps.signal = SIGNAL_TYPE_NONE;
1053                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1054                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1055                  *  the dongle is still there and limits the number of modes we can emulate.
1056                  *  Clear dongle_max_pix_clk on disconnect to fix this
1057                  */
1058                 link->dongle_max_pix_clk = 0;
1059         }
1060
1061         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
1062                 link->link_index, sink,
1063                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
1064                         "Disconnected":"Connected"), prev_sink,
1065                         same_dpcd, same_edid);
1066
1067         if (prev_sink != NULL)
1068                 dc_sink_release(prev_sink);
1069
1070         return true;
1071
1072 }
1073
1074 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1075 {
1076         const struct dc *dc = link->dc;
1077         bool ret;
1078
1079         /* get out of low power state */
1080         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1081
1082         ret = dc_link_detect_helper(link, reason);
1083
1084         /* Go back to power optimized state */
1085         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1086
1087         return ret;
1088 }
1089
1090 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1091 {
1092         uint32_t state;
1093
1094         dal_gpio_lock_pin(dc_link->hpd_gpio);
1095         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1096         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1097
1098         return state;
1099 }
1100
1101 static enum hpd_source_id get_hpd_line(
1102                 struct dc_link *link)
1103 {
1104         struct gpio *hpd;
1105         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1106
1107         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1108
1109         if (hpd) {
1110                 switch (dal_irq_get_source(hpd)) {
1111                 case DC_IRQ_SOURCE_HPD1:
1112                         hpd_id = HPD_SOURCEID1;
1113                 break;
1114                 case DC_IRQ_SOURCE_HPD2:
1115                         hpd_id = HPD_SOURCEID2;
1116                 break;
1117                 case DC_IRQ_SOURCE_HPD3:
1118                         hpd_id = HPD_SOURCEID3;
1119                 break;
1120                 case DC_IRQ_SOURCE_HPD4:
1121                         hpd_id = HPD_SOURCEID4;
1122                 break;
1123                 case DC_IRQ_SOURCE_HPD5:
1124                         hpd_id = HPD_SOURCEID5;
1125                 break;
1126                 case DC_IRQ_SOURCE_HPD6:
1127                         hpd_id = HPD_SOURCEID6;
1128                 break;
1129                 default:
1130                         BREAK_TO_DEBUGGER();
1131                 break;
1132                 }
1133
1134                 dal_gpio_destroy_irq(&hpd);
1135         }
1136
1137         return hpd_id;
1138 }
1139
1140 static enum channel_id get_ddc_line(struct dc_link *link)
1141 {
1142         struct ddc *ddc;
1143         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1144
1145         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1146
1147         if (ddc) {
1148                 switch (dal_ddc_get_line(ddc)) {
1149                 case GPIO_DDC_LINE_DDC1:
1150                         channel = CHANNEL_ID_DDC1;
1151                         break;
1152                 case GPIO_DDC_LINE_DDC2:
1153                         channel = CHANNEL_ID_DDC2;
1154                         break;
1155                 case GPIO_DDC_LINE_DDC3:
1156                         channel = CHANNEL_ID_DDC3;
1157                         break;
1158                 case GPIO_DDC_LINE_DDC4:
1159                         channel = CHANNEL_ID_DDC4;
1160                         break;
1161                 case GPIO_DDC_LINE_DDC5:
1162                         channel = CHANNEL_ID_DDC5;
1163                         break;
1164                 case GPIO_DDC_LINE_DDC6:
1165                         channel = CHANNEL_ID_DDC6;
1166                         break;
1167                 case GPIO_DDC_LINE_DDC_VGA:
1168                         channel = CHANNEL_ID_DDC_VGA;
1169                         break;
1170                 case GPIO_DDC_LINE_I2C_PAD:
1171                         channel = CHANNEL_ID_I2C_PAD;
1172                         break;
1173                 default:
1174                         BREAK_TO_DEBUGGER();
1175                         break;
1176                 }
1177         }
1178
1179         return channel;
1180 }
1181
1182 static enum transmitter translate_encoder_to_transmitter(
1183         struct graphics_object_id encoder)
1184 {
1185         switch (encoder.id) {
1186         case ENCODER_ID_INTERNAL_UNIPHY:
1187                 switch (encoder.enum_id) {
1188                 case ENUM_ID_1:
1189                         return TRANSMITTER_UNIPHY_A;
1190                 case ENUM_ID_2:
1191                         return TRANSMITTER_UNIPHY_B;
1192                 default:
1193                         return TRANSMITTER_UNKNOWN;
1194                 }
1195         break;
1196         case ENCODER_ID_INTERNAL_UNIPHY1:
1197                 switch (encoder.enum_id) {
1198                 case ENUM_ID_1:
1199                         return TRANSMITTER_UNIPHY_C;
1200                 case ENUM_ID_2:
1201                         return TRANSMITTER_UNIPHY_D;
1202                 default:
1203                         return TRANSMITTER_UNKNOWN;
1204                 }
1205         break;
1206         case ENCODER_ID_INTERNAL_UNIPHY2:
1207                 switch (encoder.enum_id) {
1208                 case ENUM_ID_1:
1209                         return TRANSMITTER_UNIPHY_E;
1210                 case ENUM_ID_2:
1211                         return TRANSMITTER_UNIPHY_F;
1212                 default:
1213                         return TRANSMITTER_UNKNOWN;
1214                 }
1215         break;
1216         case ENCODER_ID_INTERNAL_UNIPHY3:
1217                 switch (encoder.enum_id) {
1218                 case ENUM_ID_1:
1219                         return TRANSMITTER_UNIPHY_G;
1220                 default:
1221                         return TRANSMITTER_UNKNOWN;
1222                 }
1223         break;
1224         case ENCODER_ID_EXTERNAL_NUTMEG:
1225                 switch (encoder.enum_id) {
1226                 case ENUM_ID_1:
1227                         return TRANSMITTER_NUTMEG_CRT;
1228                 default:
1229                         return TRANSMITTER_UNKNOWN;
1230                 }
1231         break;
1232         case ENCODER_ID_EXTERNAL_TRAVIS:
1233                 switch (encoder.enum_id) {
1234                 case ENUM_ID_1:
1235                         return TRANSMITTER_TRAVIS_CRT;
1236                 case ENUM_ID_2:
1237                         return TRANSMITTER_TRAVIS_LCD;
1238                 default:
1239                         return TRANSMITTER_UNKNOWN;
1240                 }
1241         break;
1242         default:
1243                 return TRANSMITTER_UNKNOWN;
1244         }
1245 }
1246
1247 static bool construct(
1248         struct dc_link *link,
1249         const struct link_init_data *init_params)
1250 {
1251         uint8_t i;
1252         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1253         struct dc_context *dc_ctx = init_params->ctx;
1254         struct encoder_init_data enc_init_data = { 0 };
1255         struct integrated_info info = {{{ 0 }}};
1256         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1257         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1258         DC_LOGGER_INIT(dc_ctx->logger);
1259
1260         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1261         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1262
1263         link->link_status.dpcd_caps = &link->dpcd_caps;
1264
1265         link->dc = init_params->dc;
1266         link->ctx = dc_ctx;
1267         link->link_index = init_params->link_index;
1268
1269         memset(&link->preferred_training_settings, 0, sizeof(struct dc_link_training_overrides));
1270         memset(&link->preferred_link_setting, 0, sizeof(struct dc_link_settings));
1271
1272         link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1273
1274         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1275                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1276                          __func__, init_params->connector_index,
1277                          link->link_id.type, OBJECT_TYPE_CONNECTOR);
1278                 goto create_fail;
1279         }
1280
1281         if (link->dc->res_pool->funcs->link_init)
1282                 link->dc->res_pool->funcs->link_init(link);
1283
1284         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1285         if (link->hpd_gpio != NULL) {
1286                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1287                 dal_gpio_unlock_pin(link->hpd_gpio);
1288                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1289         }
1290
1291         switch (link->link_id.id) {
1292         case CONNECTOR_ID_HDMI_TYPE_A:
1293                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1294
1295                 break;
1296         case CONNECTOR_ID_SINGLE_LINK_DVID:
1297         case CONNECTOR_ID_SINGLE_LINK_DVII:
1298                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1299                 break;
1300         case CONNECTOR_ID_DUAL_LINK_DVID:
1301         case CONNECTOR_ID_DUAL_LINK_DVII:
1302                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1303                 break;
1304         case CONNECTOR_ID_DISPLAY_PORT:
1305                 link->connector_signal =        SIGNAL_TYPE_DISPLAY_PORT;
1306
1307                 if (link->hpd_gpio != NULL)
1308                         link->irq_source_hpd_rx =
1309                                         dal_irq_get_rx_source(link->hpd_gpio);
1310
1311                 break;
1312         case CONNECTOR_ID_EDP:
1313                 link->connector_signal = SIGNAL_TYPE_EDP;
1314
1315                 if (link->hpd_gpio != NULL) {
1316                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1317                         link->irq_source_hpd_rx =
1318                                         dal_irq_get_rx_source(link->hpd_gpio);
1319                 }
1320                 break;
1321         case CONNECTOR_ID_LVDS:
1322                 link->connector_signal = SIGNAL_TYPE_LVDS;
1323                 break;
1324         default:
1325                 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1326                 goto create_fail;
1327         }
1328
1329         /* TODO: #DAL3 Implement id to str function.*/
1330         LINK_INFO("Connector[%d] description:"
1331                         "signal %d\n",
1332                         init_params->connector_index,
1333                         link->connector_signal);
1334
1335         ddc_service_init_data.ctx = link->ctx;
1336         ddc_service_init_data.id = link->link_id;
1337         ddc_service_init_data.link = link;
1338         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1339
1340         if (link->ddc == NULL) {
1341                 DC_ERROR("Failed to create ddc_service!\n");
1342                 goto ddc_create_fail;
1343         }
1344
1345         link->ddc_hw_inst =
1346                 dal_ddc_get_line(
1347                         dal_ddc_service_get_ddc_pin(link->ddc));
1348
1349         enc_init_data.ctx = dc_ctx;
1350         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1351         enc_init_data.connector = link->link_id;
1352         enc_init_data.channel = get_ddc_line(link);
1353         enc_init_data.hpd_source = get_hpd_line(link);
1354
1355         link->hpd_src = enc_init_data.hpd_source;
1356
1357         enc_init_data.transmitter =
1358                         translate_encoder_to_transmitter(enc_init_data.encoder);
1359         link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1360                                                                 &enc_init_data);
1361
1362         if (link->link_enc == NULL) {
1363                 DC_ERROR("Failed to create link encoder!\n");
1364                 goto link_enc_create_fail;
1365         }
1366
1367         link->link_enc_hw_inst = link->link_enc->transmitter;
1368
1369         for (i = 0; i < 4; i++) {
1370                 if (BP_RESULT_OK !=
1371                                 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1372                         DC_ERROR("Failed to find device tag!\n");
1373                         goto device_tag_fail;
1374                 }
1375
1376                 /* Look for device tag that matches connector signal,
1377                  * CRT for rgb, LCD for other supported signal tyes
1378                  */
1379                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1380                         continue;
1381                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1382                         && link->connector_signal != SIGNAL_TYPE_RGB)
1383                         continue;
1384                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1385                         && link->connector_signal == SIGNAL_TYPE_RGB)
1386                         continue;
1387                 break;
1388         }
1389
1390         if (bios->integrated_info)
1391                 info = *bios->integrated_info;
1392
1393         /* Look for channel mapping corresponding to connector and device tag */
1394         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1395                 struct external_display_path *path =
1396                         &info.ext_disp_conn_info.path[i];
1397                 if (path->device_connector_id.enum_id == link->link_id.enum_id
1398                         && path->device_connector_id.id == link->link_id.id
1399                         && path->device_connector_id.type == link->link_id.type) {
1400
1401                         if (link->device_tag.acpi_device != 0
1402                                 && path->device_acpi_enum == link->device_tag.acpi_device) {
1403                                 link->ddi_channel_mapping = path->channel_mapping;
1404                                 link->chip_caps = path->caps;
1405                         } else if (path->device_tag ==
1406                                         link->device_tag.dev_id.raw_device_tag) {
1407                                 link->ddi_channel_mapping = path->channel_mapping;
1408                                 link->chip_caps = path->caps;
1409                         }
1410                         break;
1411                 }
1412         }
1413
1414         /*
1415          * TODO check if GPIO programmed correctly
1416          *
1417          * If GPIO isn't programmed correctly HPD might not rise or drain
1418          * fast enough, leading to bounces.
1419          */
1420         program_hpd_filter(link);
1421
1422         return true;
1423 device_tag_fail:
1424         link->link_enc->funcs->destroy(&link->link_enc);
1425 link_enc_create_fail:
1426         dal_ddc_service_destroy(&link->ddc);
1427 ddc_create_fail:
1428 create_fail:
1429
1430         if (link->hpd_gpio != NULL) {
1431                 dal_gpio_destroy_irq(&link->hpd_gpio);
1432                 link->hpd_gpio = NULL;
1433         }
1434
1435         return false;
1436 }
1437
1438 /*******************************************************************************
1439  * Public functions
1440  ******************************************************************************/
1441 struct dc_link *link_create(const struct link_init_data *init_params)
1442 {
1443         struct dc_link *link =
1444                         kzalloc(sizeof(*link), GFP_KERNEL);
1445
1446         if (NULL == link)
1447                 goto alloc_fail;
1448
1449         if (false == construct(link, init_params))
1450                 goto construct_fail;
1451
1452         return link;
1453
1454 construct_fail:
1455         kfree(link);
1456
1457 alloc_fail:
1458         return NULL;
1459 }
1460
1461 void link_destroy(struct dc_link **link)
1462 {
1463         destruct(*link);
1464         kfree(*link);
1465         *link = NULL;
1466 }
1467
1468 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1469 {
1470         struct dc_stream_state *stream = pipe_ctx->stream;
1471         struct dc_link *link = stream->link;
1472         union down_spread_ctrl old_downspread;
1473         union down_spread_ctrl new_downspread;
1474
1475         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1476                         &old_downspread.raw, sizeof(old_downspread));
1477
1478         new_downspread.raw = old_downspread.raw;
1479
1480         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1481                         (stream->ignore_msa_timing_param) ? 1 : 0;
1482
1483         if (new_downspread.raw != old_downspread.raw) {
1484                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1485                         &new_downspread.raw, sizeof(new_downspread));
1486         }
1487 }
1488
1489 static enum dc_status enable_link_dp(
1490                 struct dc_state *state,
1491                 struct pipe_ctx *pipe_ctx)
1492 {
1493         struct dc_stream_state *stream = pipe_ctx->stream;
1494         enum dc_status status;
1495         bool skip_video_pattern;
1496         struct dc_link *link = stream->link;
1497         struct dc_link_settings link_settings = {0};
1498         enum dp_panel_mode panel_mode;
1499 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1500         bool fec_enable;
1501 #endif
1502         int i;
1503         bool apply_seamless_boot_optimization = false;
1504
1505         // check for seamless boot
1506         for (i = 0; i < state->stream_count; i++) {
1507                 if (state->streams[i]->apply_seamless_boot_optimization) {
1508                         apply_seamless_boot_optimization = true;
1509                         break;
1510                 }
1511         }
1512
1513         /* get link settings for video mode timing */
1514         decide_link_settings(stream, &link_settings);
1515
1516         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1517                 /* If link settings are different than current and link already enabled
1518                  * then need to disable before programming to new rate.
1519                  */
1520                 if (link->link_status.link_active &&
1521                         (link->cur_link_settings.lane_count != link_settings.lane_count ||
1522                          link->cur_link_settings.link_rate != link_settings.link_rate)) {
1523                         dp_disable_link_phy(link, pipe_ctx->stream->signal);
1524                 }
1525
1526                 /*in case it is not on*/
1527                 link->dc->hwss.edp_power_control(link, true);
1528                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1529         }
1530
1531         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1532                         link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1533         if (state->clk_mgr && !apply_seamless_boot_optimization)
1534                 state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
1535
1536         dp_enable_link_phy(
1537                 link,
1538                 pipe_ctx->stream->signal,
1539                 pipe_ctx->clock_source->id,
1540                 &link_settings);
1541
1542         if (stream->sink_patches.dppowerup_delay > 0) {
1543                 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1544
1545                 msleep(delay_dp_power_up_in_ms);
1546         }
1547
1548         panel_mode = dp_get_panel_mode(link);
1549         dp_set_panel_mode(link, panel_mode);
1550
1551         skip_video_pattern = true;
1552
1553         if (link_settings.link_rate == LINK_RATE_LOW)
1554                         skip_video_pattern = false;
1555
1556         if (link->aux_access_disabled) {
1557                 dc_link_dp_perform_link_training_skip_aux(link, &link_settings);
1558
1559                 link->cur_link_settings = link_settings;
1560                 status = DC_OK;
1561         } else if (perform_link_training_with_retries(
1562                         link,
1563                         &link_settings,
1564                         skip_video_pattern,
1565                         LINK_TRAINING_ATTEMPTS)) {
1566                 link->cur_link_settings = link_settings;
1567                 status = DC_OK;
1568         }
1569         else
1570                 status = DC_FAIL_DP_LINK_TRAINING;
1571
1572 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1573         if (link->preferred_training_settings.fec_enable != NULL)
1574                 fec_enable = *link->preferred_training_settings.fec_enable;
1575         else
1576                 fec_enable = true;
1577
1578         dp_set_fec_enable(link, fec_enable);
1579 #endif
1580         return status;
1581 }
1582
1583 static enum dc_status enable_link_edp(
1584                 struct dc_state *state,
1585                 struct pipe_ctx *pipe_ctx)
1586 {
1587         enum dc_status status;
1588
1589         status = enable_link_dp(state, pipe_ctx);
1590
1591         return status;
1592 }
1593
1594 static enum dc_status enable_link_dp_mst(
1595                 struct dc_state *state,
1596                 struct pipe_ctx *pipe_ctx)
1597 {
1598         struct dc_link *link = pipe_ctx->stream->link;
1599
1600         /* sink signal type after MST branch is MST. Multiple MST sinks
1601          * share one link. Link DP PHY is enable or training only once.
1602          */
1603         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1604                 return DC_OK;
1605
1606         /* clear payload table */
1607         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1608
1609         /* to make sure the pending down rep can be processed
1610          * before enabling the link
1611          */
1612         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1613
1614         /* set the sink to MST mode before enabling the link */
1615         dp_enable_mst_on_sink(link, true);
1616
1617         return enable_link_dp(state, pipe_ctx);
1618 }
1619
1620 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1621                 enum engine_id eng_id,
1622                 struct ext_hdmi_settings *settings)
1623 {
1624         bool result = false;
1625         int i = 0;
1626         struct integrated_info *integrated_info =
1627                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1628
1629         if (integrated_info == NULL)
1630                 return false;
1631
1632         /*
1633          * Get retimer settings from sbios for passing SI eye test for DCE11
1634          * The setting values are varied based on board revision and port id
1635          * Therefore the setting values of each ports is passed by sbios.
1636          */
1637
1638         // Check if current bios contains ext Hdmi settings
1639         if (integrated_info->gpu_cap_info & 0x20) {
1640                 switch (eng_id) {
1641                 case ENGINE_ID_DIGA:
1642                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1643                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1644                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1645                         memmove(settings->reg_settings,
1646                                         integrated_info->dp0_ext_hdmi_reg_settings,
1647                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1648                         memmove(settings->reg_settings_6g,
1649                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1650                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1651                         result = true;
1652                         break;
1653                 case ENGINE_ID_DIGB:
1654                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1655                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1656                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1657                         memmove(settings->reg_settings,
1658                                         integrated_info->dp1_ext_hdmi_reg_settings,
1659                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1660                         memmove(settings->reg_settings_6g,
1661                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1662                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1663                         result = true;
1664                         break;
1665                 case ENGINE_ID_DIGC:
1666                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1667                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1668                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1669                         memmove(settings->reg_settings,
1670                                         integrated_info->dp2_ext_hdmi_reg_settings,
1671                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1672                         memmove(settings->reg_settings_6g,
1673                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1674                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1675                         result = true;
1676                         break;
1677                 case ENGINE_ID_DIGD:
1678                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1679                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1680                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1681                         memmove(settings->reg_settings,
1682                                         integrated_info->dp3_ext_hdmi_reg_settings,
1683                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1684                         memmove(settings->reg_settings_6g,
1685                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1686                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1687                         result = true;
1688                         break;
1689                 default:
1690                         break;
1691                 }
1692
1693                 if (result == true) {
1694                         // Validate settings from bios integrated info table
1695                         if (settings->slv_addr == 0)
1696                                 return false;
1697                         if (settings->reg_num > 9)
1698                                 return false;
1699                         if (settings->reg_num_6g > 3)
1700                                 return false;
1701
1702                         for (i = 0; i < settings->reg_num; i++) {
1703                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1704                                         return false;
1705                         }
1706
1707                         for (i = 0; i < settings->reg_num_6g; i++) {
1708                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1709                                         return false;
1710                         }
1711                 }
1712         }
1713
1714         return result;
1715 }
1716
1717 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1718                 uint8_t address, uint8_t *buffer, uint32_t length)
1719 {
1720         struct i2c_command cmd = {0};
1721         struct i2c_payload payload = {0};
1722
1723         memset(&payload, 0, sizeof(payload));
1724         memset(&cmd, 0, sizeof(cmd));
1725
1726         cmd.number_of_payloads = 1;
1727         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1728         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1729
1730         payload.address = address;
1731         payload.data = buffer;
1732         payload.length = length;
1733         payload.write = true;
1734         cmd.payloads = &payload;
1735
1736         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1737                         pipe_ctx->stream->link, &cmd))
1738                 return true;
1739
1740         return false;
1741 }
1742
1743 static void write_i2c_retimer_setting(
1744                 struct pipe_ctx *pipe_ctx,
1745                 bool is_vga_mode,
1746                 bool is_over_340mhz,
1747                 struct ext_hdmi_settings *settings)
1748 {
1749         uint8_t slave_address = (settings->slv_addr >> 1);
1750         uint8_t buffer[2];
1751         const uint8_t apply_rx_tx_change = 0x4;
1752         uint8_t offset = 0xA;
1753         uint8_t value = 0;
1754         int i = 0;
1755         bool i2c_success = false;
1756         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1757
1758         memset(&buffer, 0, sizeof(buffer));
1759
1760         /* Start Ext-Hdmi programming*/
1761
1762         for (i = 0; i < settings->reg_num; i++) {
1763                 /* Apply 3G settings */
1764                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1765
1766                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1767                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1768                         i2c_success = i2c_write(pipe_ctx, slave_address,
1769                                                 buffer, sizeof(buffer));
1770                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1771                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1772                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1773
1774                         if (!i2c_success)
1775                                 /* Write failure */
1776                                 ASSERT(i2c_success);
1777
1778                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1779                          * needs to be set to 1 on every 0xA-0xC write.
1780                          */
1781                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1782                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1783                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1784
1785                                 /* Query current value from offset 0xA */
1786                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1787                                         value = settings->reg_settings[i].i2c_reg_val;
1788                                 else {
1789                                         i2c_success =
1790                                                 dal_ddc_service_query_ddc_data(
1791                                                 pipe_ctx->stream->link->ddc,
1792                                                 slave_address, &offset, 1, &value, 1);
1793                                         if (!i2c_success)
1794                                                 /* Write failure */
1795                                                 ASSERT(i2c_success);
1796                                 }
1797
1798                                 buffer[0] = offset;
1799                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1800                                 buffer[1] = value | apply_rx_tx_change;
1801                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1802                                                 buffer, sizeof(buffer));
1803                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1804                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1805                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1806                                 if (!i2c_success)
1807                                         /* Write failure */
1808                                         ASSERT(i2c_success);
1809                         }
1810                 }
1811         }
1812
1813         /* Apply 3G settings */
1814         if (is_over_340mhz) {
1815                 for (i = 0; i < settings->reg_num_6g; i++) {
1816                         /* Apply 3G settings */
1817                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1818
1819                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1820                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1821                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1822                                                         buffer, sizeof(buffer));
1823                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1824                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1825                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1826
1827                                 if (!i2c_success)
1828                                         /* Write failure */
1829                                         ASSERT(i2c_success);
1830
1831                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1832                                  * needs to be set to 1 on every 0xA-0xC write.
1833                                  */
1834                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1835                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1836                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1837
1838                                         /* Query current value from offset 0xA */
1839                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1840                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1841                                         else {
1842                                                 i2c_success =
1843                                                                 dal_ddc_service_query_ddc_data(
1844                                                                 pipe_ctx->stream->link->ddc,
1845                                                                 slave_address, &offset, 1, &value, 1);
1846                                                 if (!i2c_success)
1847                                                         /* Write failure */
1848                                                         ASSERT(i2c_success);
1849                                         }
1850
1851                                         buffer[0] = offset;
1852                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1853                                         buffer[1] = value | apply_rx_tx_change;
1854                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1855                                                         buffer, sizeof(buffer));
1856                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1857                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1858                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1859                                         if (!i2c_success)
1860                                                 /* Write failure */
1861                                                 ASSERT(i2c_success);
1862                                 }
1863                         }
1864                 }
1865         }
1866
1867         if (is_vga_mode) {
1868                 /* Program additional settings if using 640x480 resolution */
1869
1870                 /* Write offset 0xFF to 0x01 */
1871                 buffer[0] = 0xff;
1872                 buffer[1] = 0x01;
1873                 i2c_success = i2c_write(pipe_ctx, slave_address,
1874                                 buffer, sizeof(buffer));
1875                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1876                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1877                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1878                 if (!i2c_success)
1879                         /* Write failure */
1880                         ASSERT(i2c_success);
1881
1882                 /* Write offset 0x00 to 0x23 */
1883                 buffer[0] = 0x00;
1884                 buffer[1] = 0x23;
1885                 i2c_success = i2c_write(pipe_ctx, slave_address,
1886                                 buffer, sizeof(buffer));
1887                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1888                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1889                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1890                 if (!i2c_success)
1891                         /* Write failure */
1892                         ASSERT(i2c_success);
1893
1894                 /* Write offset 0xff to 0x00 */
1895                 buffer[0] = 0xff;
1896                 buffer[1] = 0x00;
1897                 i2c_success = i2c_write(pipe_ctx, slave_address,
1898                                 buffer, sizeof(buffer));
1899                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1900                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1901                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1902                 if (!i2c_success)
1903                         /* Write failure */
1904                         ASSERT(i2c_success);
1905
1906         }
1907 }
1908
1909 static void write_i2c_default_retimer_setting(
1910                 struct pipe_ctx *pipe_ctx,
1911                 bool is_vga_mode,
1912                 bool is_over_340mhz)
1913 {
1914         uint8_t slave_address = (0xBA >> 1);
1915         uint8_t buffer[2];
1916         bool i2c_success = false;
1917         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1918
1919         memset(&buffer, 0, sizeof(buffer));
1920
1921         /* Program Slave Address for tuning single integrity */
1922         /* Write offset 0x0A to 0x13 */
1923         buffer[0] = 0x0A;
1924         buffer[1] = 0x13;
1925         i2c_success = i2c_write(pipe_ctx, slave_address,
1926                         buffer, sizeof(buffer));
1927         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
1928                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1929                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1930         if (!i2c_success)
1931                 /* Write failure */
1932                 ASSERT(i2c_success);
1933
1934         /* Write offset 0x0A to 0x17 */
1935         buffer[0] = 0x0A;
1936         buffer[1] = 0x17;
1937         i2c_success = i2c_write(pipe_ctx, slave_address,
1938                         buffer, sizeof(buffer));
1939         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1940                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1941                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1942         if (!i2c_success)
1943                 /* Write failure */
1944                 ASSERT(i2c_success);
1945
1946         /* Write offset 0x0B to 0xDA or 0xD8 */
1947         buffer[0] = 0x0B;
1948         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1949         i2c_success = i2c_write(pipe_ctx, slave_address,
1950                         buffer, sizeof(buffer));
1951         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1952                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1953                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1954         if (!i2c_success)
1955                 /* Write failure */
1956                 ASSERT(i2c_success);
1957
1958         /* Write offset 0x0A to 0x17 */
1959         buffer[0] = 0x0A;
1960         buffer[1] = 0x17;
1961         i2c_success = i2c_write(pipe_ctx, slave_address,
1962                         buffer, sizeof(buffer));
1963         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1964                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1965                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1966         if (!i2c_success)
1967                 /* Write failure */
1968                 ASSERT(i2c_success);
1969
1970         /* Write offset 0x0C to 0x1D or 0x91 */
1971         buffer[0] = 0x0C;
1972         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1973         i2c_success = i2c_write(pipe_ctx, slave_address,
1974                         buffer, sizeof(buffer));
1975         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1976                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1977                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1978         if (!i2c_success)
1979                 /* Write failure */
1980                 ASSERT(i2c_success);
1981
1982         /* Write offset 0x0A to 0x17 */
1983         buffer[0] = 0x0A;
1984         buffer[1] = 0x17;
1985         i2c_success = i2c_write(pipe_ctx, slave_address,
1986                         buffer, sizeof(buffer));
1987         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1988                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1989                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1990         if (!i2c_success)
1991                 /* Write failure */
1992                 ASSERT(i2c_success);
1993
1994
1995         if (is_vga_mode) {
1996                 /* Program additional settings if using 640x480 resolution */
1997
1998                 /* Write offset 0xFF to 0x01 */
1999                 buffer[0] = 0xff;
2000                 buffer[1] = 0x01;
2001                 i2c_success = i2c_write(pipe_ctx, slave_address,
2002                                 buffer, sizeof(buffer));
2003                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2004                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2005                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2006                 if (!i2c_success)
2007                         /* Write failure */
2008                         ASSERT(i2c_success);
2009
2010                 /* Write offset 0x00 to 0x23 */
2011                 buffer[0] = 0x00;
2012                 buffer[1] = 0x23;
2013                 i2c_success = i2c_write(pipe_ctx, slave_address,
2014                                 buffer, sizeof(buffer));
2015                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2016                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2017                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2018                 if (!i2c_success)
2019                         /* Write failure */
2020                         ASSERT(i2c_success);
2021
2022                 /* Write offset 0xff to 0x00 */
2023                 buffer[0] = 0xff;
2024                 buffer[1] = 0x00;
2025                 i2c_success = i2c_write(pipe_ctx, slave_address,
2026                                 buffer, sizeof(buffer));
2027                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2028                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2029                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2030                 if (!i2c_success)
2031                         /* Write failure */
2032                         ASSERT(i2c_success);
2033         }
2034 }
2035
2036 static void write_i2c_redriver_setting(
2037                 struct pipe_ctx *pipe_ctx,
2038                 bool is_over_340mhz)
2039 {
2040         uint8_t slave_address = (0xF0 >> 1);
2041         uint8_t buffer[16];
2042         bool i2c_success = false;
2043         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2044
2045         memset(&buffer, 0, sizeof(buffer));
2046
2047         // Program Slave Address for tuning single integrity
2048         buffer[3] = 0x4E;
2049         buffer[4] = 0x4E;
2050         buffer[5] = 0x4E;
2051         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2052
2053         i2c_success = i2c_write(pipe_ctx, slave_address,
2054                                         buffer, sizeof(buffer));
2055         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2056                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2057                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2058                 i2c_success = %d\n",
2059                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2060
2061         if (!i2c_success)
2062                 /* Write failure */
2063                 ASSERT(i2c_success);
2064 }
2065
2066 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2067 {
2068         struct dc_stream_state *stream = pipe_ctx->stream;
2069         struct dc_link *link = stream->link;
2070         enum dc_color_depth display_color_depth;
2071         enum engine_id eng_id;
2072         struct ext_hdmi_settings settings = {0};
2073         bool is_over_340mhz = false;
2074         bool is_vga_mode = (stream->timing.h_addressable == 640)
2075                         && (stream->timing.v_addressable == 480);
2076
2077         if (stream->phy_pix_clk == 0)
2078                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2079         if (stream->phy_pix_clk > 340000)
2080                 is_over_340mhz = true;
2081
2082         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2083                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2084                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2085                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2086                         /* DP159, Retimer settings */
2087                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2088
2089                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2090                                 write_i2c_retimer_setting(pipe_ctx,
2091                                                 is_vga_mode, is_over_340mhz, &settings);
2092                         } else {
2093                                 write_i2c_default_retimer_setting(pipe_ctx,
2094                                                 is_vga_mode, is_over_340mhz);
2095                         }
2096                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2097                         /* PI3EQX1204, Redriver settings */
2098                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2099                 }
2100         }
2101
2102         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2103                 dal_ddc_service_write_scdc_data(
2104                         stream->link->ddc,
2105                         stream->phy_pix_clk,
2106                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2107
2108         memset(&stream->link->cur_link_settings, 0,
2109                         sizeof(struct dc_link_settings));
2110
2111         display_color_depth = stream->timing.display_color_depth;
2112         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2113                 display_color_depth = COLOR_DEPTH_888;
2114
2115         link->link_enc->funcs->enable_tmds_output(
2116                         link->link_enc,
2117                         pipe_ctx->clock_source->id,
2118                         display_color_depth,
2119                         pipe_ctx->stream->signal,
2120                         stream->phy_pix_clk);
2121
2122         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2123                 dal_ddc_service_read_scdc_data(link->ddc);
2124 }
2125
2126 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2127 {
2128         struct dc_stream_state *stream = pipe_ctx->stream;
2129         struct dc_link *link = stream->link;
2130
2131         if (stream->phy_pix_clk == 0)
2132                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2133
2134         memset(&stream->link->cur_link_settings, 0,
2135                         sizeof(struct dc_link_settings));
2136
2137         link->link_enc->funcs->enable_lvds_output(
2138                         link->link_enc,
2139                         pipe_ctx->clock_source->id,
2140                         stream->phy_pix_clk);
2141
2142 }
2143
2144 /****************************enable_link***********************************/
2145 static enum dc_status enable_link(
2146                 struct dc_state *state,
2147                 struct pipe_ctx *pipe_ctx)
2148 {
2149         enum dc_status status = DC_ERROR_UNEXPECTED;
2150         switch (pipe_ctx->stream->signal) {
2151         case SIGNAL_TYPE_DISPLAY_PORT:
2152                 status = enable_link_dp(state, pipe_ctx);
2153                 break;
2154         case SIGNAL_TYPE_EDP:
2155                 status = enable_link_edp(state, pipe_ctx);
2156                 break;
2157         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2158                 status = enable_link_dp_mst(state, pipe_ctx);
2159                 msleep(200);
2160                 break;
2161         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2162         case SIGNAL_TYPE_DVI_DUAL_LINK:
2163         case SIGNAL_TYPE_HDMI_TYPE_A:
2164                 enable_link_hdmi(pipe_ctx);
2165                 status = DC_OK;
2166                 break;
2167         case SIGNAL_TYPE_LVDS:
2168                 enable_link_lvds(pipe_ctx);
2169                 status = DC_OK;
2170                 break;
2171         case SIGNAL_TYPE_VIRTUAL:
2172                 status = DC_OK;
2173                 break;
2174         default:
2175                 break;
2176         }
2177
2178         if (status == DC_OK)
2179                 pipe_ctx->stream->link->link_status.link_active = true;
2180
2181         return status;
2182 }
2183
2184 static void disable_link(struct dc_link *link, enum signal_type signal)
2185 {
2186         /*
2187          * TODO: implement call for dp_set_hw_test_pattern
2188          * it is needed for compliance testing
2189          */
2190
2191         /* here we need to specify that encoder output settings
2192          * need to be calculated as for the set mode,
2193          * it will lead to querying dynamic link capabilities
2194          * which should be done before enable output */
2195
2196         if (dc_is_dp_signal(signal)) {
2197                 /* SST DP, eDP */
2198                 if (dc_is_dp_sst_signal(signal))
2199                         dp_disable_link_phy(link, signal);
2200                 else
2201                         dp_disable_link_phy_mst(link, signal);
2202 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2203
2204                 if (dc_is_dp_sst_signal(signal) ||
2205                                 link->mst_stream_alloc_table.stream_count == 0) {
2206                         dp_set_fec_enable(link, false);
2207                         dp_set_fec_ready(link, false);
2208                 }
2209 #endif
2210         } else {
2211                 if (signal != SIGNAL_TYPE_VIRTUAL)
2212                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2213         }
2214
2215         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2216                 /* MST disable link only when no stream use the link */
2217                 if (link->mst_stream_alloc_table.stream_count <= 0)
2218                         link->link_status.link_active = false;
2219         } else {
2220                 link->link_status.link_active = false;
2221         }
2222 }
2223
2224 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2225 {
2226
2227         uint32_t pxl_clk = timing->pix_clk_100hz;
2228
2229         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2230                 pxl_clk /= 2;
2231         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2232                 pxl_clk = pxl_clk * 2 / 3;
2233
2234         if (timing->display_color_depth == COLOR_DEPTH_101010)
2235                 pxl_clk = pxl_clk * 10 / 8;
2236         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2237                 pxl_clk = pxl_clk * 12 / 8;
2238
2239         return pxl_clk;
2240 }
2241
2242 static bool dp_active_dongle_validate_timing(
2243                 const struct dc_crtc_timing *timing,
2244                 const struct dpcd_caps *dpcd_caps)
2245 {
2246         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2247
2248         switch (dpcd_caps->dongle_type) {
2249         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2250         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2251         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2252                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2253                         return true;
2254                 else
2255                         return false;
2256         default:
2257                 break;
2258         }
2259
2260         if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2261                 dongle_caps->extendedCapValid == false)
2262                 return true;
2263
2264         /* Check Pixel Encoding */
2265         switch (timing->pixel_encoding) {
2266         case PIXEL_ENCODING_RGB:
2267         case PIXEL_ENCODING_YCBCR444:
2268                 break;
2269         case PIXEL_ENCODING_YCBCR422:
2270                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2271                         return false;
2272                 break;
2273         case PIXEL_ENCODING_YCBCR420:
2274                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2275                         return false;
2276                 break;
2277         default:
2278                 /* Invalid Pixel Encoding*/
2279                 return false;
2280         }
2281
2282         switch (timing->display_color_depth) {
2283         case COLOR_DEPTH_666:
2284         case COLOR_DEPTH_888:
2285                 /*888 and 666 should always be supported*/
2286                 break;
2287         case COLOR_DEPTH_101010:
2288                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2289                         return false;
2290                 break;
2291         case COLOR_DEPTH_121212:
2292                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2293                         return false;
2294                 break;
2295         case COLOR_DEPTH_141414:
2296         case COLOR_DEPTH_161616:
2297         default:
2298                 /* These color depths are currently not supported */
2299                 return false;
2300         }
2301
2302         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2303                 return false;
2304
2305         return true;
2306 }
2307
2308 enum dc_status dc_link_validate_mode_timing(
2309                 const struct dc_stream_state *stream,
2310                 struct dc_link *link,
2311                 const struct dc_crtc_timing *timing)
2312 {
2313         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2314         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2315
2316         /* A hack to avoid failing any modes for EDID override feature on
2317          * topology change such as lower quality cable for DP or different dongle
2318          */
2319         if (link->remote_sinks[0])
2320                 return DC_OK;
2321
2322         /* Passive Dongle */
2323         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2324                 return DC_EXCEED_DONGLE_CAP;
2325
2326         /* Active Dongle*/
2327         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2328                 return DC_EXCEED_DONGLE_CAP;
2329
2330         switch (stream->signal) {
2331         case SIGNAL_TYPE_EDP:
2332         case SIGNAL_TYPE_DISPLAY_PORT:
2333                 if (!dp_validate_mode_timing(
2334                                 link,
2335                                 timing))
2336                         return DC_NO_DP_LINK_BANDWIDTH;
2337                 break;
2338
2339         default:
2340                 break;
2341         }
2342
2343         return DC_OK;
2344 }
2345
2346 int dc_link_get_backlight_level(const struct dc_link *link)
2347 {
2348         struct abm *abm = link->ctx->dc->res_pool->abm;
2349
2350         if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2351                 return DC_ERROR_UNEXPECTED;
2352
2353         return (int) abm->funcs->get_current_backlight(abm);
2354 }
2355
2356 bool dc_link_set_backlight_level(const struct dc_link *link,
2357                 uint32_t backlight_pwm_u16_16,
2358                 uint32_t frame_ramp)
2359 {
2360         struct dc  *core_dc = link->ctx->dc;
2361         struct abm *abm = core_dc->res_pool->abm;
2362         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2363         unsigned int controller_id = 0;
2364         bool use_smooth_brightness = true;
2365         int i;
2366         DC_LOGGER_INIT(link->ctx->logger);
2367
2368         if ((dmcu == NULL) ||
2369                 (abm == NULL) ||
2370                 (abm->funcs->set_backlight_level_pwm == NULL))
2371                 return false;
2372
2373         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2374
2375         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2376                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2377
2378         if (dc_is_embedded_signal(link->connector_signal)) {
2379                 for (i = 0; i < MAX_PIPES; i++) {
2380                         if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
2381                                 if (core_dc->current_state->res_ctx.
2382                                                 pipe_ctx[i].stream->link
2383                                                 == link) {
2384                                         /* DMCU -1 for all controller id values,
2385                                          * therefore +1 here
2386                                          */
2387                                         controller_id =
2388                                                 core_dc->current_state->
2389                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2390                                                 1;
2391
2392                                         /* Disable brightness ramping when the display is blanked
2393                                          * as it can hang the DMCU
2394                                          */
2395                                         if (core_dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
2396                                                 frame_ramp = 0;
2397                                 }
2398                         }
2399                 }
2400                 abm->funcs->set_backlight_level_pwm(
2401                                 abm,
2402                                 backlight_pwm_u16_16,
2403                                 frame_ramp,
2404                                 controller_id,
2405                                 use_smooth_brightness);
2406         }
2407
2408         return true;
2409 }
2410
2411 bool dc_link_set_abm_disable(const struct dc_link *link)
2412 {
2413         struct dc  *core_dc = link->ctx->dc;
2414         struct abm *abm = core_dc->res_pool->abm;
2415
2416         if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
2417                 return false;
2418
2419         abm->funcs->set_abm_immediate_disable(abm);
2420
2421         return true;
2422 }
2423
2424 bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool wait)
2425 {
2426         struct dc  *core_dc = link->ctx->dc;
2427         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2428
2429
2430
2431         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_feature_enabled)
2432                 dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
2433
2434         link->psr_allow_active = allow_active;
2435
2436         return true;
2437 }
2438
2439 bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
2440 {
2441         struct dc  *core_dc = link->ctx->dc;
2442         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2443
2444         if (dmcu != NULL && link->psr_feature_enabled)
2445                 dmcu->funcs->get_psr_state(dmcu, psr_state);
2446
2447         return true;
2448 }
2449
2450 static inline enum physical_phy_id
2451 transmitter_to_phy_id(enum transmitter transmitter_value)
2452 {
2453         switch (transmitter_value) {
2454         case TRANSMITTER_UNIPHY_A:
2455                 return PHYLD_0;
2456         case TRANSMITTER_UNIPHY_B:
2457                 return PHYLD_1;
2458         case TRANSMITTER_UNIPHY_C:
2459                 return PHYLD_2;
2460         case TRANSMITTER_UNIPHY_D:
2461                 return PHYLD_3;
2462         case TRANSMITTER_UNIPHY_E:
2463                 return PHYLD_4;
2464         case TRANSMITTER_UNIPHY_F:
2465                 return PHYLD_5;
2466         case TRANSMITTER_NUTMEG_CRT:
2467                 return PHYLD_6;
2468         case TRANSMITTER_TRAVIS_CRT:
2469                 return PHYLD_7;
2470         case TRANSMITTER_TRAVIS_LCD:
2471                 return PHYLD_8;
2472         case TRANSMITTER_UNIPHY_G:
2473                 return PHYLD_9;
2474         case TRANSMITTER_COUNT:
2475                 return PHYLD_COUNT;
2476         case TRANSMITTER_UNKNOWN:
2477                 return PHYLD_UNKNOWN;
2478         default:
2479                 WARN_ONCE(1, "Unknown transmitter value %d\n",
2480                           transmitter_value);
2481                 return PHYLD_UNKNOWN;
2482         }
2483 }
2484
2485 bool dc_link_setup_psr(struct dc_link *link,
2486                 const struct dc_stream_state *stream, struct psr_config *psr_config,
2487                 struct psr_context *psr_context)
2488 {
2489         struct dc *core_dc;
2490         struct dmcu *dmcu;
2491         int i;
2492         /* updateSinkPsrDpcdConfig*/
2493         union dpcd_psr_configuration psr_configuration;
2494
2495         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
2496
2497         if (!link)
2498                 return false;
2499
2500         core_dc = link->ctx->dc;
2501         dmcu = core_dc->res_pool->dmcu;
2502
2503         if (!dmcu)
2504                 return false;
2505
2506
2507         memset(&psr_configuration, 0, sizeof(psr_configuration));
2508
2509         psr_configuration.bits.ENABLE                    = 1;
2510         psr_configuration.bits.CRC_VERIFICATION          = 1;
2511         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
2512                         psr_config->psr_frame_capture_indication_req;
2513
2514         /* Check for PSR v2*/
2515         if (psr_config->psr_version == 0x2) {
2516                 /* For PSR v2 selective update.
2517                  * Indicates whether sink should start capturing
2518                  * immediately following active scan line,
2519                  * or starting with the 2nd active scan line.
2520                  */
2521                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
2522                 /*For PSR v2, determines whether Sink should generate
2523                  * IRQ_HPD when CRC mismatch is detected.
2524                  */
2525                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
2526         }
2527
2528         dm_helpers_dp_write_dpcd(
2529                 link->ctx,
2530                 link,
2531                 368,
2532                 &psr_configuration.raw,
2533                 sizeof(psr_configuration.raw));
2534
2535         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
2536         psr_context->transmitterId = link->link_enc->transmitter;
2537         psr_context->engineId = link->link_enc->preferred_engine;
2538
2539         for (i = 0; i < MAX_PIPES; i++) {
2540                 if (core_dc->current_state->res_ctx.pipe_ctx[i].stream
2541                                 == stream) {
2542                         /* dmcu -1 for all controller id values,
2543                          * therefore +1 here
2544                          */
2545                         psr_context->controllerId =
2546                                 core_dc->current_state->res_ctx.
2547                                 pipe_ctx[i].stream_res.tg->inst + 1;
2548                         break;
2549                 }
2550         }
2551
2552         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
2553         psr_context->phyType = PHY_TYPE_UNIPHY;
2554         /*PhyId is associated with the transmitter id*/
2555         psr_context->smuPhyId =
2556                 transmitter_to_phy_id(link->link_enc->transmitter);
2557
2558         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
2559         psr_context->vsyncRateHz = div64_u64(div64_u64((stream->
2560                                         timing.pix_clk_100hz * 100),
2561                                         stream->timing.v_total),
2562                                         stream->timing.h_total);
2563
2564         psr_context->psrSupportedDisplayConfig = true;
2565         psr_context->psrExitLinkTrainingRequired =
2566                 psr_config->psr_exit_link_training_required;
2567         psr_context->sdpTransmitLineNumDeadline =
2568                 psr_config->psr_sdp_transmit_line_num_deadline;
2569         psr_context->psrFrameCaptureIndicationReq =
2570                 psr_config->psr_frame_capture_indication_req;
2571
2572         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
2573
2574         psr_context->numberOfControllers =
2575                         link->dc->res_pool->timing_generator_count;
2576
2577         psr_context->rfb_update_auto_en = true;
2578
2579         /* 2 frames before enter PSR. */
2580         psr_context->timehyst_frames = 2;
2581         /* half a frame
2582          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
2583          */
2584         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
2585         psr_context->aux_repeats = 10;
2586
2587         psr_context->psr_level.u32all = 0;
2588
2589 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2590         /*skip power down the single pipe since it blocks the cstate*/
2591         if (ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
2592                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
2593 #endif
2594
2595         /* SMU will perform additional powerdown sequence.
2596          * For unsupported ASICs, set psr_level flag to skip PSR
2597          *  static screen notification to SMU.
2598          *  (Always set for DAL2, did not check ASIC)
2599          */
2600         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
2601
2602         /* Complete PSR entry before aborting to prevent intermittent
2603          * freezes on certain eDPs
2604          */
2605         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
2606
2607         /* Controls additional delay after remote frame capture before
2608          * continuing power down, default = 0
2609          */
2610         psr_context->frame_delay = 0;
2611
2612         link->psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
2613
2614         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
2615          * should not happen since firmware should be running at this point
2616          */
2617         if (link->psr_feature_enabled == 0)
2618                 ASSERT(0);
2619
2620         return true;
2621
2622 }
2623
2624 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2625 {
2626         return &link->link_status;
2627 }
2628
2629 void core_link_resume(struct dc_link *link)
2630 {
2631         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2632                 program_hpd_filter(link);
2633 }
2634
2635 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2636 {
2637         struct fixed31_32 mbytes_per_sec;
2638         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
2639                         &stream->link->cur_link_settings);
2640         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
2641
2642         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2643
2644         return dc_fixpt_div_int(mbytes_per_sec, 54);
2645 }
2646
2647 static int get_color_depth(enum dc_color_depth color_depth)
2648 {
2649         switch (color_depth) {
2650         case COLOR_DEPTH_666: return 6;
2651         case COLOR_DEPTH_888: return 8;
2652         case COLOR_DEPTH_101010: return 10;
2653         case COLOR_DEPTH_121212: return 12;
2654         case COLOR_DEPTH_141414: return 14;
2655         case COLOR_DEPTH_161616: return 16;
2656         default: return 0;
2657         }
2658 }
2659
2660 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2661 {
2662         uint32_t bpc;
2663         uint64_t kbps;
2664         struct fixed31_32 peak_kbps;
2665         uint32_t numerator;
2666         uint32_t denominator;
2667
2668         bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2669         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2670
2671         /*
2672          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2673          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2674          * common multiplier to render an integer PBN for all link rate/lane
2675          * counts combinations
2676          * calculate
2677          * peak_kbps *= (1006/1000)
2678          * peak_kbps *= (64/54)
2679          * peak_kbps *= 8    convert to bytes
2680          */
2681
2682         numerator = 64 * PEAK_FACTOR_X1000;
2683         denominator = 54 * 8 * 1000 * 1000;
2684         kbps *= numerator;
2685         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2686
2687         return peak_kbps;
2688 }
2689
2690 static void update_mst_stream_alloc_table(
2691         struct dc_link *link,
2692         struct stream_encoder *stream_enc,
2693         const struct dp_mst_stream_allocation_table *proposed_table)
2694 {
2695         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2696                         { 0 } };
2697         struct link_mst_stream_allocation *dc_alloc;
2698
2699         int i;
2700         int j;
2701
2702         /* if DRM proposed_table has more than one new payload */
2703         ASSERT(proposed_table->stream_count -
2704                         link->mst_stream_alloc_table.stream_count < 2);
2705
2706         /* copy proposed_table to link, add stream encoder */
2707         for (i = 0; i < proposed_table->stream_count; i++) {
2708
2709                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2710                         dc_alloc =
2711                         &link->mst_stream_alloc_table.stream_allocations[j];
2712
2713                         if (dc_alloc->vcp_id ==
2714                                 proposed_table->stream_allocations[i].vcp_id) {
2715
2716                                 work_table[i] = *dc_alloc;
2717                                 break; /* exit j loop */
2718                         }
2719                 }
2720
2721                 /* new vcp_id */
2722                 if (j == link->mst_stream_alloc_table.stream_count) {
2723                         work_table[i].vcp_id =
2724                                 proposed_table->stream_allocations[i].vcp_id;
2725                         work_table[i].slot_count =
2726                                 proposed_table->stream_allocations[i].slot_count;
2727                         work_table[i].stream_enc = stream_enc;
2728                 }
2729         }
2730
2731         /* update link->mst_stream_alloc_table with work_table */
2732         link->mst_stream_alloc_table.stream_count =
2733                         proposed_table->stream_count;
2734         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2735                 link->mst_stream_alloc_table.stream_allocations[i] =
2736                                 work_table[i];
2737 }
2738
2739 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2740  * because stream_encoder is not exposed to dm
2741  */
2742 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2743 {
2744         struct dc_stream_state *stream = pipe_ctx->stream;
2745         struct dc_link *link = stream->link;
2746         struct link_encoder *link_encoder = link->link_enc;
2747         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2748         struct dp_mst_stream_allocation_table proposed_table = {0};
2749         struct fixed31_32 avg_time_slots_per_mtp;
2750         struct fixed31_32 pbn;
2751         struct fixed31_32 pbn_per_slot;
2752         uint8_t i;
2753         enum act_return_status ret;
2754         DC_LOGGER_INIT(link->ctx->logger);
2755
2756         /* enable_link_dp_mst already check link->enabled_stream_count
2757          * and stream is in link->stream[]. This is called during set mode,
2758          * stream_enc is available.
2759          */
2760
2761         /* get calculate VC payload for stream: stream_alloc */
2762         if (dm_helpers_dp_mst_write_payload_allocation_table(
2763                 stream->ctx,
2764                 stream,
2765                 &proposed_table,
2766                 true)) {
2767                 update_mst_stream_alloc_table(
2768                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2769         }
2770         else
2771                 DC_LOG_WARNING("Failed to update"
2772                                 "MST allocation table for"
2773                                 "pipe idx:%d\n",
2774                                 pipe_ctx->pipe_idx);
2775
2776         DC_LOG_MST("%s  "
2777                         "stream_count: %d: \n ",
2778                         __func__,
2779                         link->mst_stream_alloc_table.stream_count);
2780
2781         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2782                 DC_LOG_MST("stream_enc[%d]: %p      "
2783                 "stream[%d].vcp_id: %d      "
2784                 "stream[%d].slot_count: %d\n",
2785                 i,
2786                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2787                 i,
2788                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2789                 i,
2790                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2791         }
2792
2793         ASSERT(proposed_table.stream_count > 0);
2794
2795         /* program DP source TX for payload */
2796         link_encoder->funcs->update_mst_stream_allocation_table(
2797                 link_encoder,
2798                 &link->mst_stream_alloc_table);
2799
2800         /* send down message */
2801         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2802                         stream->ctx,
2803                         stream);
2804
2805         if (ret != ACT_LINK_LOST) {
2806                 dm_helpers_dp_mst_send_payload_allocation(
2807                                 stream->ctx,
2808                                 stream,
2809                                 true);
2810         }
2811
2812         /* slot X.Y for only current stream */
2813         pbn_per_slot = get_pbn_per_slot(stream);
2814         pbn = get_pbn_from_timing(pipe_ctx);
2815         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2816
2817         stream_encoder->funcs->set_mst_bandwidth(
2818                 stream_encoder,
2819                 avg_time_slots_per_mtp);
2820
2821         return DC_OK;
2822
2823 }
2824
2825 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2826 {
2827         struct dc_stream_state *stream = pipe_ctx->stream;
2828         struct dc_link *link = stream->link;
2829         struct link_encoder *link_encoder = link->link_enc;
2830         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2831         struct dp_mst_stream_allocation_table proposed_table = {0};
2832         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2833         uint8_t i;
2834         bool mst_mode = (link->type == dc_connection_mst_branch);
2835         DC_LOGGER_INIT(link->ctx->logger);
2836
2837         /* deallocate_mst_payload is called before disable link. When mode or
2838          * disable/enable monitor, new stream is created which is not in link
2839          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2840          * should not done. For new mode set, map_resources will get engine
2841          * for new stream, so stream_enc->id should be validated until here.
2842          */
2843
2844         /* slot X.Y */
2845         stream_encoder->funcs->set_mst_bandwidth(
2846                 stream_encoder,
2847                 avg_time_slots_per_mtp);
2848
2849         /* TODO: which component is responsible for remove payload table? */
2850         if (mst_mode) {
2851                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2852                                 stream->ctx,
2853                                 stream,
2854                                 &proposed_table,
2855                                 false)) {
2856
2857                         update_mst_stream_alloc_table(
2858                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2859                 }
2860                 else {
2861                                 DC_LOG_WARNING("Failed to update"
2862                                                 "MST allocation table for"
2863                                                 "pipe idx:%d\n",
2864                                                 pipe_ctx->pipe_idx);
2865                 }
2866         }
2867
2868         DC_LOG_MST("%s"
2869                         "stream_count: %d: ",
2870                         __func__,
2871                         link->mst_stream_alloc_table.stream_count);
2872
2873         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2874                 DC_LOG_MST("stream_enc[%d]: %p      "
2875                 "stream[%d].vcp_id: %d      "
2876                 "stream[%d].slot_count: %d\n",
2877                 i,
2878                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2879                 i,
2880                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2881                 i,
2882                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2883         }
2884
2885         link_encoder->funcs->update_mst_stream_allocation_table(
2886                 link_encoder,
2887                 &link->mst_stream_alloc_table);
2888
2889         if (mst_mode) {
2890                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2891                         stream->ctx,
2892                         stream);
2893
2894                 dm_helpers_dp_mst_send_payload_allocation(
2895                         stream->ctx,
2896                         stream,
2897                         false);
2898         }
2899
2900         return DC_OK;
2901 }
2902 #if defined(CONFIG_DRM_AMD_DC_HDCP)
2903 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
2904 {
2905         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
2906         if (cp_psp && cp_psp->funcs.update_stream_config) {
2907                 struct cp_psp_stream_config config;
2908
2909                 memset(&config, 0, sizeof(config));
2910
2911                 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
2912                 config.stream_enc_inst = (uint8_t) pipe_ctx->stream_res.stream_enc->id;
2913                 config.link_enc_inst = pipe_ctx->stream->link->link_enc_hw_inst;
2914                 config.dpms_off = dpms_off;
2915                 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
2916                 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
2917         }
2918 }
2919 #endif
2920
2921 void core_link_enable_stream(
2922                 struct dc_state *state,
2923                 struct pipe_ctx *pipe_ctx)
2924 {
2925         struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2926         struct dc_stream_state *stream = pipe_ctx->stream;
2927         enum dc_status status;
2928         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2929
2930         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) &&
2931                         dc_is_virtual_signal(pipe_ctx->stream->signal))
2932                 return;
2933
2934         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
2935                 stream->link->link_enc->funcs->setup(
2936                         stream->link->link_enc,
2937                         pipe_ctx->stream->signal);
2938                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
2939                         pipe_ctx->stream_res.stream_enc,
2940                         pipe_ctx->stream_res.tg->inst,
2941                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
2942         }
2943
2944         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2945                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
2946                         pipe_ctx->stream_res.stream_enc,
2947                         &stream->timing,
2948                         stream->output_color_space,
2949                         stream->use_vsc_sdp_for_colorimetry,
2950                         stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
2951
2952         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
2953                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
2954                         pipe_ctx->stream_res.stream_enc,
2955                         &stream->timing,
2956                         stream->phy_pix_clk,
2957                         pipe_ctx->stream_res.audio != NULL);
2958
2959         pipe_ctx->stream->link->link_state_valid = true;
2960
2961         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
2962                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
2963                         pipe_ctx->stream_res.stream_enc,
2964                         &stream->timing,
2965                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
2966                         true : false);
2967
2968         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
2969                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
2970                         pipe_ctx->stream_res.stream_enc,
2971                         &stream->timing);
2972
2973         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
2974                 bool apply_edp_fast_boot_optimization =
2975                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
2976
2977                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2978
2979                 resource_build_info_frame(pipe_ctx);
2980                 core_dc->hwss.update_info_frame(pipe_ctx);
2981
2982                 /* Do not touch link on seamless boot optimization. */
2983                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
2984                         pipe_ctx->stream->dpms_off = false;
2985 #if defined(CONFIG_DRM_AMD_DC_HDCP)
2986                         update_psp_stream_config(pipe_ctx, false);
2987 #endif
2988                         return;
2989                 }
2990
2991                 /* eDP lit up by bios already, no need to enable again. */
2992                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2993                                         apply_edp_fast_boot_optimization) {
2994                         pipe_ctx->stream->dpms_off = false;
2995 #if defined(CONFIG_DRM_AMD_DC_HDCP)
2996                         update_psp_stream_config(pipe_ctx, false);
2997 #endif
2998                         return;
2999                 }
3000
3001                 if (pipe_ctx->stream->dpms_off)
3002                         return;
3003
3004                 status = enable_link(state, pipe_ctx);
3005
3006                 if (status != DC_OK) {
3007                         DC_LOG_WARNING("enabling link %u failed: %d\n",
3008                         pipe_ctx->stream->link->link_index,
3009                         status);
3010
3011                         /* Abort stream enable *unless* the failure was due to
3012                          * DP link training - some DP monitors will recover and
3013                          * show the stream anyway. But MST displays can't proceed
3014                          * without link training.
3015                          */
3016                         if (status != DC_FAIL_DP_LINK_TRAINING ||
3017                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3018                                 BREAK_TO_DEBUGGER();
3019                                 return;
3020                         }
3021                 }
3022
3023                 core_dc->hwss.enable_audio_stream(pipe_ctx);
3024
3025                 /* turn off otg test pattern if enable */
3026                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3027                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3028                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3029                                         COLOR_DEPTH_UNDEFINED);
3030
3031 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3032                 if (pipe_ctx->stream->timing.flags.DSC) {
3033                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3034                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3035                                 dp_set_dsc_enable(pipe_ctx, true);
3036                 }
3037 #endif
3038                 core_dc->hwss.enable_stream(pipe_ctx);
3039
3040 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3041                 /* Set DPS PPS SDP (AKA "info frames") */
3042                 if (pipe_ctx->stream->timing.flags.DSC) {
3043                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3044                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3045                                 dp_set_dsc_pps_sdp(pipe_ctx, true);
3046                 }
3047 #endif
3048
3049                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3050                         dc_link_allocate_mst_payload(pipe_ctx);
3051
3052                 core_dc->hwss.unblank_stream(pipe_ctx,
3053                         &pipe_ctx->stream->link->cur_link_settings);
3054
3055                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3056                         enable_stream_features(pipe_ctx);
3057 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3058                 update_psp_stream_config(pipe_ctx, false);
3059 #endif
3060         }
3061 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3062         else { // if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
3063                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3064                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
3065                         dp_set_dsc_enable(pipe_ctx, true);
3066
3067         }
3068 #endif
3069 }
3070
3071 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
3072 {
3073         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
3074         struct dc_stream_state *stream = pipe_ctx->stream;
3075         struct dc_link *link = stream->sink->link;
3076
3077         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) &&
3078                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3079                 return;
3080
3081 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3082         update_psp_stream_config(pipe_ctx, true);
3083 #endif
3084
3085         core_dc->hwss.blank_stream(pipe_ctx);
3086
3087         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3088                 deallocate_mst_payload(pipe_ctx);
3089
3090         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
3091                 struct ext_hdmi_settings settings = {0};
3092                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
3093
3094                 unsigned short masked_chip_caps = link->chip_caps &
3095                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
3096                 //Need to inform that sink is going to use legacy HDMI mode.
3097                 dal_ddc_service_write_scdc_data(
3098                         link->ddc,
3099                         165000,//vbios only handles 165Mhz.
3100                         false);
3101                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
3102                         /* DP159, Retimer settings */
3103                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
3104                                 write_i2c_retimer_setting(pipe_ctx,
3105                                                 false, false, &settings);
3106                         else
3107                                 write_i2c_default_retimer_setting(pipe_ctx,
3108                                                 false, false);
3109                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
3110                         /* PI3EQX1204, Redriver settings */
3111                         write_i2c_redriver_setting(pipe_ctx, false);
3112                 }
3113         }
3114         core_dc->hwss.disable_stream(pipe_ctx);
3115
3116         disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
3117 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3118         if (pipe_ctx->stream->timing.flags.DSC) {
3119                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3120                         dp_set_dsc_enable(pipe_ctx, false);
3121         }
3122 #endif
3123 }
3124
3125 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
3126 {
3127         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
3128
3129         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
3130                 return;
3131
3132         core_dc->hwss.set_avmute(pipe_ctx, enable);
3133 }
3134
3135 /**
3136  *****************************************************************************
3137  *  Function: dc_link_enable_hpd_filter
3138  *
3139  *  @brief
3140  *     If enable is true, programs HPD filter on associated HPD line using
3141  *     delay_on_disconnect/delay_on_connect values dependent on
3142  *     link->connector_signal
3143  *
3144  *     If enable is false, programs HPD filter on associated HPD line with no
3145  *     delays on connect or disconnect
3146  *
3147  *  @param [in] link: pointer to the dc link
3148  *  @param [in] enable: boolean specifying whether to enable hbd
3149  *****************************************************************************
3150  */
3151 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
3152 {
3153         struct gpio *hpd;
3154
3155         if (enable) {
3156                 link->is_hpd_filter_disabled = false;
3157                 program_hpd_filter(link);
3158         } else {
3159                 link->is_hpd_filter_disabled = true;
3160                 /* Obtain HPD handle */
3161                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
3162
3163                 if (!hpd)
3164                         return;
3165
3166                 /* Setup HPD filtering */
3167                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
3168                         struct gpio_hpd_config config;
3169
3170                         config.delay_on_connect = 0;
3171                         config.delay_on_disconnect = 0;
3172
3173                         dal_irq_setup_hpd_filter(hpd, &config);
3174
3175                         dal_gpio_close(hpd);
3176                 } else {
3177                         ASSERT_CRITICAL(false);
3178                 }
3179                 /* Release HPD handle */
3180                 dal_gpio_destroy_irq(&hpd);
3181         }
3182 }
3183
3184 uint32_t dc_bandwidth_in_kbps_from_timing(
3185         const struct dc_crtc_timing *timing)
3186 {
3187         uint32_t bits_per_channel = 0;
3188         uint32_t kbps;
3189
3190 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3191         if (timing->flags.DSC) {
3192                 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
3193                 kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
3194                 return kbps;
3195         }
3196 #endif
3197
3198         switch (timing->display_color_depth) {
3199         case COLOR_DEPTH_666:
3200                 bits_per_channel = 6;
3201                 break;
3202         case COLOR_DEPTH_888:
3203                 bits_per_channel = 8;
3204                 break;
3205         case COLOR_DEPTH_101010:
3206                 bits_per_channel = 10;
3207                 break;
3208         case COLOR_DEPTH_121212:
3209                 bits_per_channel = 12;
3210                 break;
3211         case COLOR_DEPTH_141414:
3212                 bits_per_channel = 14;
3213                 break;
3214         case COLOR_DEPTH_161616:
3215                 bits_per_channel = 16;
3216                 break;
3217         default:
3218                 break;
3219         }
3220
3221         ASSERT(bits_per_channel != 0);
3222
3223         kbps = timing->pix_clk_100hz / 10;
3224         kbps *= bits_per_channel;
3225
3226         if (timing->flags.Y_ONLY != 1) {
3227                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
3228                 kbps *= 3;
3229                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3230                         kbps /= 2;
3231                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
3232                         kbps = kbps * 2 / 3;
3233         }
3234
3235         return kbps;
3236
3237 }
3238
3239 void dc_link_set_drive_settings(struct dc *dc,
3240                                 struct link_training_settings *lt_settings,
3241                                 const struct dc_link *link)
3242 {
3243
3244         int i;
3245
3246         for (i = 0; i < dc->link_count; i++) {
3247                 if (dc->links[i] == link)
3248                         break;
3249         }
3250
3251         if (i >= dc->link_count)
3252                 ASSERT_CRITICAL(false);
3253
3254         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
3255 }
3256
3257 void dc_link_perform_link_training(struct dc *dc,
3258                                    struct dc_link_settings *link_setting,
3259                                    bool skip_video_pattern)
3260 {
3261         int i;
3262
3263         for (i = 0; i < dc->link_count; i++)
3264                 dc_link_dp_perform_link_training(
3265                         dc->links[i],
3266                         link_setting,
3267                         skip_video_pattern);
3268 }
3269
3270 void dc_link_set_preferred_link_settings(struct dc *dc,
3271                                          struct dc_link_settings *link_setting,
3272                                          struct dc_link *link)
3273 {
3274         int i;
3275         struct pipe_ctx *pipe;
3276         struct dc_stream_state *link_stream;
3277         struct dc_link_settings store_settings = *link_setting;
3278
3279         link->preferred_link_setting = store_settings;
3280
3281         /* Retrain with preferred link settings only relevant for
3282          * DP signal type
3283          * Check for non-DP signal or if passive dongle present
3284          */
3285         if (!dc_is_dp_signal(link->connector_signal) ||
3286                 link->dongle_max_pix_clk > 0)
3287                 return;
3288
3289         for (i = 0; i < MAX_PIPES; i++) {
3290                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3291                 if (pipe->stream && pipe->stream->link) {
3292                         if (pipe->stream->link == link) {
3293                                 link_stream = pipe->stream;
3294                                 break;
3295                         }
3296                 }
3297         }
3298
3299         /* Stream not found */
3300         if (i == MAX_PIPES)
3301                 return;
3302
3303         /* Cannot retrain link if backend is off */
3304         if (link_stream->dpms_off)
3305                 return;
3306
3307         decide_link_settings(link_stream, &store_settings);
3308
3309         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3310                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
3311                 dp_retrain_link_dp_test(link, &store_settings, false);
3312 }
3313
3314 void dc_link_set_preferred_training_settings(struct dc *dc,
3315                                                  struct dc_link_settings *link_setting,
3316                                                  struct dc_link_training_overrides *lt_overrides,
3317                                                  struct dc_link *link,
3318                                                  bool skip_immediate_retrain)
3319 {
3320         if (lt_overrides != NULL)
3321                 link->preferred_training_settings = *lt_overrides;
3322         else
3323                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
3324
3325         if (link_setting != NULL) {
3326                 link->preferred_link_setting = *link_setting;
3327         } else {
3328                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3329                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3330         }
3331
3332         /* Retrain now, or wait until next stream update to apply */
3333         if (skip_immediate_retrain == false)
3334                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
3335 }
3336
3337 void dc_link_enable_hpd(const struct dc_link *link)
3338 {
3339         dc_link_dp_enable_hpd(link);
3340 }
3341
3342 void dc_link_disable_hpd(const struct dc_link *link)
3343 {
3344         dc_link_dp_disable_hpd(link);
3345 }
3346
3347 void dc_link_set_test_pattern(struct dc_link *link,
3348                               enum dp_test_pattern test_pattern,
3349                               const struct link_training_settings *p_link_settings,
3350                               const unsigned char *p_custom_pattern,
3351                               unsigned int cust_pattern_size)
3352 {
3353         if (link != NULL)
3354                 dc_link_dp_set_test_pattern(
3355                         link,
3356                         test_pattern,
3357                         p_link_settings,
3358                         p_custom_pattern,
3359                         cust_pattern_size);
3360 }
3361
3362 uint32_t dc_link_bandwidth_kbps(
3363         const struct dc_link *link,
3364         const struct dc_link_settings *link_setting)
3365 {
3366         uint32_t link_bw_kbps =
3367                 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
3368
3369         link_bw_kbps *= 8;   /* 8 bits per byte*/
3370         link_bw_kbps *= link_setting->lane_count;
3371
3372 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3373         if (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
3374                 /* Account for FEC overhead.
3375                  * We have to do it based on caps,
3376                  * and not based on FEC being set ready,
3377                  * because FEC is set ready too late in
3378                  * the process to correctly be picked up
3379                  * by mode enumeration.
3380                  *
3381                  * There's enough zeros at the end of 'kbps'
3382                  * that make the below operation 100% precise
3383                  * for our purposes.
3384                  * 'long long' makes it work even for HDMI 2.1
3385                  * max bandwidth (and much, much bigger bandwidths
3386                  * than that, actually).
3387                  *
3388                  * NOTE: Reducing link BW by 3% may not be precise
3389                  * because it may be a stream BT that increases by 3%, and so
3390                  * 1/1.03 = 0.970873 factor should have been used instead,
3391                  * but the difference is minimal and is in a safe direction,
3392                  * which all works well around potential ambiguity of DP 1.4a spec.
3393                  */
3394                 link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
3395                                                link_bw_kbps, 32);
3396         }
3397 #endif
3398
3399         return link_bw_kbps;
3400
3401 }
3402
3403 const struct dc_link_settings *dc_link_get_link_cap(
3404                 const struct dc_link *link)
3405 {
3406         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
3407                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
3408                 return &link->preferred_link_setting;
3409         return &link->verified_link_cap;
3410 }