drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "atom.h"
  28 #include "dm_helpers.h"
  29 #include "dc.h"
  30 #include "grph_object_id.h"
  31 #include "gpio_service_interface.h"
  32 #include "core_status.h"
  33 #include "dc_link_dp.h"
  34 #include "dc_link_ddc.h"
  35 #include "link_hwss.h"
  36 #include "opp.h"
  37
  38 #include "link_encoder.h"
  39 #include "hw_sequencer.h"
  40 #include "resource.h"
  41 #include "abm.h"
  42 #include "fixed31_32.h"
  43 #include "dpcd_defs.h"
  44 #include "dmcu.h"
  45
  46 #include "dce/dce_11_0_d.h"
  47 #include "dce/dce_11_0_enum.h"
  48 #include "dce/dce_11_0_sh_mask.h"
  49
  50 #define DC_LOGGER_INIT(logger)
  51
  52
  53 #define LINK_INFO(...) \
  54         DC_LOG_HW_HOTPLUG(  \
  55                 __VA_ARGS__)
  56
  57 /*******************************************************************************
  58  * Private structures
  59  ******************************************************************************/
  60
  61 enum {
  62         LINK_RATE_REF_FREQ_IN_MHZ = 27,
  63         PEAK_FACTOR_X1000 = 1006
  64 };
  65
  66 /*******************************************************************************
  67  * Private functions
  68  ******************************************************************************/
  69 static void destruct(struct dc_link *link)
  70 {
  71         int i;
  72
  73         if (link->ddc)
  74                 dal_ddc_service_destroy(&link->ddc);
  75
  76         if(link->link_enc)
  77                 link->link_enc->funcs->destroy(&link->link_enc);
  78
  79         if (link->local_sink)
  80                 dc_sink_release(link->local_sink);
  81
  82         for (i = 0; i < link->sink_count; ++i)
  83                 dc_sink_release(link->remote_sinks[i]);
  84 }
  85
  86 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
  87                 struct graphics_object_id link_id,
  88                 struct gpio_service *gpio_service)
  89 {
  90         enum bp_result bp_result;
  91         struct graphics_object_hpd_info hpd_info;
  92         struct gpio_pin_info pin_info;
  93
  94         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
  95                 return NULL;
  96
  97         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
  98                 hpd_info.hpd_int_gpio_uid, &pin_info);
  99
 100         if (bp_result != BP_RESULT_OK) {
 101                 ASSERT(bp_result == BP_RESULT_NORECORD);
 102                 return NULL;
 103         }
 104
 105         return dal_gpio_service_create_irq(
 106                 gpio_service,
 107                 pin_info.offset,
 108                 pin_info.mask);
 109 }
 110
 111 /*
 112  *  Function: program_hpd_filter
 113  *
 114  *  @brief
 115  *     Programs HPD filter on associated HPD line
 116  *
 117  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 118  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 119  *
 120  *  @return
 121  *     true on success, false otherwise
 122  */
 123 static bool program_hpd_filter(
 124         const struct dc_link *link)
 125 {
 126         bool result = false;
 127
 128         struct gpio *hpd;
 129
 130         int delay_on_connect_in_ms = 0;
 131         int delay_on_disconnect_in_ms = 0;
 132
 133         if (link->is_hpd_filter_disabled)
 134                 return false;
 135         /* Verify feature is supported */
 136         switch (link->connector_signal) {
 137         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 138         case SIGNAL_TYPE_DVI_DUAL_LINK:
 139         case SIGNAL_TYPE_HDMI_TYPE_A:
 140                 /* Program hpd filter */
 141                 delay_on_connect_in_ms = 500;
 142                 delay_on_disconnect_in_ms = 100;
 143                 break;
 144         case SIGNAL_TYPE_DISPLAY_PORT:
 145         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 146                 /* Program hpd filter to allow DP signal to settle */
 147                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 148                  *      only 100ms on DELL U2413
 149                  * 0:   some passive dongle still show aux mode instead of i2c
 150                  * 20-50:not enough to hide bouncing HPD with passive dongle.
 151                  *      also see intermittent i2c read issues.
 152                  */
 153                 delay_on_connect_in_ms = 80;
 154                 delay_on_disconnect_in_ms = 0;
 155                 break;
 156         case SIGNAL_TYPE_LVDS:
 157         case SIGNAL_TYPE_EDP:
 158         default:
 159                 /* Don't program hpd filter */
 160                 return false;
 161         }
 162
 163         /* Obtain HPD handle */
 164         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 165
 166         if (!hpd)
 167                 return result;
 168
 169         /* Setup HPD filtering */
 170         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 171                 struct gpio_hpd_config config;
 172
 173                 config.delay_on_connect = delay_on_connect_in_ms;
 174                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 175
 176                 dal_irq_setup_hpd_filter(hpd, &config);
 177
 178                 dal_gpio_close(hpd);
 179
 180                 result = true;
 181         } else {
 182                 ASSERT_CRITICAL(false);
 183         }
 184
 185         /* Release HPD handle */
 186         dal_gpio_destroy_irq(&hpd);
 187
 188         return result;
 189 }
 190
 191 static bool detect_sink(struct dc_link *link, enum dc_connection_type *type)
 192 {
 193         uint32_t is_hpd_high = 0;
 194         struct gpio *hpd_pin;
 195
 196         /* todo: may need to lock gpio access */
 197         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 198         if (hpd_pin == NULL)
 199                 goto hpd_gpio_failure;
 200
 201         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 202         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 203         dal_gpio_close(hpd_pin);
 204         dal_gpio_destroy_irq(&hpd_pin);
 205
 206         if (is_hpd_high) {
 207                 *type = dc_connection_single;
 208                 /* TODO: need to do the actual detection */
 209         } else {
 210                 *type = dc_connection_none;
 211         }
 212
 213         return true;
 214
 215 hpd_gpio_failure:
 216         return false;
 217 }
 218
 219 static enum ddc_transaction_type get_ddc_transaction_type(
 220                 enum signal_type sink_signal)
 221 {
 222         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 223
 224         switch (sink_signal) {
 225         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 226         case SIGNAL_TYPE_DVI_DUAL_LINK:
 227         case SIGNAL_TYPE_HDMI_TYPE_A:
 228         case SIGNAL_TYPE_LVDS:
 229         case SIGNAL_TYPE_RGB:
 230                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 231                 break;
 232
 233         case SIGNAL_TYPE_DISPLAY_PORT:
 234         case SIGNAL_TYPE_EDP:
 235                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 236                 break;
 237
 238         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 239                 /* MST does not use I2COverAux, but there is the
 240                  * SPECIAL use case for "immediate dwnstrm device
 241                  * access" (EPR#370830). */
 242                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 243                 break;
 244
 245         default:
 246                 break;
 247         }
 248
 249         return transaction_type;
 250 }
 251
 252 static enum signal_type get_basic_signal_type(
 253         struct graphics_object_id encoder,
 254         struct graphics_object_id downstream)
 255 {
 256         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 257                 switch (downstream.id) {
 258                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 259                         switch (encoder.id) {
 260                         case ENCODER_ID_INTERNAL_DAC1:
 261                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 262                         case ENCODER_ID_INTERNAL_DAC2:
 263                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 264                                 return SIGNAL_TYPE_RGB;
 265                         default:
 266                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 267                         }
 268                 break;
 269                 case CONNECTOR_ID_DUAL_LINK_DVII:
 270                 {
 271                         switch (encoder.id) {
 272                         case ENCODER_ID_INTERNAL_DAC1:
 273                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 274                         case ENCODER_ID_INTERNAL_DAC2:
 275                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 276                                 return SIGNAL_TYPE_RGB;
 277                         default:
 278                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 279                         }
 280                 }
 281                 break;
 282                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 283                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 284                 case CONNECTOR_ID_DUAL_LINK_DVID:
 285                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 286                 case CONNECTOR_ID_VGA:
 287                         return SIGNAL_TYPE_RGB;
 288                 case CONNECTOR_ID_HDMI_TYPE_A:
 289                         return SIGNAL_TYPE_HDMI_TYPE_A;
 290                 case CONNECTOR_ID_LVDS:
 291                         return SIGNAL_TYPE_LVDS;
 292                 case CONNECTOR_ID_DISPLAY_PORT:
 293                         return SIGNAL_TYPE_DISPLAY_PORT;
 294                 case CONNECTOR_ID_EDP:
 295                         return SIGNAL_TYPE_EDP;
 296                 default:
 297                         return SIGNAL_TYPE_NONE;
 298                 }
 299         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 300                 switch (downstream.id) {
 301                 case ENCODER_ID_EXTERNAL_NUTMEG:
 302                 case ENCODER_ID_EXTERNAL_TRAVIS:
 303                         return SIGNAL_TYPE_DISPLAY_PORT;
 304                 default:
 305                         return SIGNAL_TYPE_NONE;
 306                 }
 307         }
 308
 309         return SIGNAL_TYPE_NONE;
 310 }
 311
 312 /*
 313  * @brief
 314  * Check whether there is a dongle on DP connector
 315  */
 316 bool dc_link_is_dp_sink_present(struct dc_link *link)
 317 {
 318         enum gpio_result gpio_result;
 319         uint32_t clock_pin = 0;
 320
 321         struct ddc *ddc;
 322
 323         enum connector_id connector_id =
 324                 dal_graphics_object_id_get_connector_id(link->link_id);
 325
 326         bool present =
 327                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 328                 (connector_id == CONNECTOR_ID_EDP));
 329
 330         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 331
 332         if (!ddc) {
 333                 BREAK_TO_DEBUGGER();
 334                 return present;
 335         }
 336
 337         /* Open GPIO and set it to I2C mode */
 338         /* Note: this GpioMode_Input will be converted
 339          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 340          * which indicates we need additional delay */
 341
 342         if (GPIO_RESULT_OK != dal_ddc_open(
 343                 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
 344                 dal_gpio_destroy_ddc(&ddc);
 345
 346                 return present;
 347         }
 348
 349         /* Read GPIO: DP sink is present if both clock and data pins are zero */
 350         /* [anaumov] in DAL2, there was no check for GPIO failure */
 351
 352         gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 353         ASSERT(gpio_result == GPIO_RESULT_OK);
 354
 355         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 356
 357         dal_ddc_close(ddc);
 358
 359         return present;
 360 }
 361
 362 /*
 363  * @brief
 364  * Detect output sink type
 365  */
 366 static enum signal_type link_detect_sink(
 367         struct dc_link *link,
 368         enum dc_detect_reason reason)
 369 {
 370         enum signal_type result = get_basic_signal_type(
 371                 link->link_enc->id, link->link_id);
 372
 373         /* Internal digital encoder will detect only dongles
 374          * that require digital signal */
 375
 376         /* Detection mechanism is different
 377          * for different native connectors.
 378          * LVDS connector supports only LVDS signal;
 379          * PCIE is a bus slot, the actual connector needs to be detected first;
 380          * eDP connector supports only eDP signal;
 381          * HDMI should check straps for audio */
 382
 383         /* PCIE detects the actual connector on add-on board */
 384
 385         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 386                 /* ZAZTODO implement PCIE add-on card detection */
 387         }
 388
 389         switch (link->link_id.id) {
 390         case CONNECTOR_ID_HDMI_TYPE_A: {
 391                 /* check audio support:
 392                  * if native HDMI is not supported, switch to DVI */
 393                 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 394
 395                 if (!aud_support->hdmi_audio_native)
 396                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 397                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 398         }
 399         break;
 400         case CONNECTOR_ID_DISPLAY_PORT: {
 401                 /* DP HPD short pulse. Passive DP dongle will not
 402                  * have short pulse
 403                  */
 404                 if (reason != DETECT_REASON_HPDRX) {
 405                         /* Check whether DP signal detected: if not -
 406                          * we assume signal is DVI; it could be corrected
 407                          * to HDMI after dongle detection
 408                          */
 409                         if (!dm_helpers_is_dp_sink_present(link))
 410                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 411                 }
 412         }
 413         break;
 414         default:
 415         break;
 416         }
 417
 418         return result;
 419 }
 420
 421 static enum signal_type decide_signal_from_strap_and_dongle_type(
 422                 enum display_dongle_type dongle_type,
 423                 struct audio_support *audio_support)
 424 {
 425         enum signal_type signal = SIGNAL_TYPE_NONE;
 426
 427         switch (dongle_type) {
 428         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 429                 if (audio_support->hdmi_audio_on_dongle)
 430                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 431                 else
 432                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 433                 break;
 434         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 435                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 436                 break;
 437         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 438                 if (audio_support->hdmi_audio_native)
 439                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 440                 else
 441                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 442                 break;
 443         default:
 444                 signal = SIGNAL_TYPE_NONE;
 445                 break;
 446         }
 447
 448         return signal;
 449 }
 450
 451 static enum signal_type dp_passive_dongle_detection(
 452                 struct ddc_service *ddc,
 453                 struct display_sink_capability *sink_cap,
 454                 struct audio_support *audio_support)
 455 {
 456         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 457                                                 ddc, sink_cap);
 458         return decide_signal_from_strap_and_dongle_type(
 459                         sink_cap->dongle_type,
 460                         audio_support);
 461 }
 462
 463 static void link_disconnect_sink(struct dc_link *link)
 464 {
 465         if (link->local_sink) {
 466                 dc_sink_release(link->local_sink);
 467                 link->local_sink = NULL;
 468         }
 469
 470         link->dpcd_sink_count = 0;
 471 }
 472
 473 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 474 {
 475         dc_sink_release(link->local_sink);
 476         link->local_sink = prev_sink;
 477 }
 478
 479
 480 static bool detect_dp(
 481         struct dc_link *link,
 482         struct display_sink_capability *sink_caps,
 483         bool *converter_disable_audio,
 484         struct audio_support *audio_support,
 485         enum dc_detect_reason reason)
 486 {
 487         bool boot = false;
 488         sink_caps->signal = link_detect_sink(link, reason);
 489         sink_caps->transaction_type =
 490                 get_ddc_transaction_type(sink_caps->signal);
 491
 492         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 493                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 494                 if (!detect_dp_sink_caps(link))
 495                         return false;
 496
 497                 if (is_mst_supported(link)) {
 498                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 499                         link->type = dc_connection_mst_branch;
 500
 501                         dal_ddc_service_set_transaction_type(
 502                                                         link->ddc,
 503                                                         sink_caps->transaction_type);
 504
 505                         /*
 506                          * This call will initiate MST topology discovery. Which
 507                          * will detect MST ports and add new DRM connector DRM
 508                          * framework. Then read EDID via remote i2c over aux. In
 509                          * the end, will notify DRM detect result and save EDID
 510                          * into DRM framework.
 511                          *
 512                          * .detect is called by .fill_modes.
 513                          * .fill_modes is called by user mode ioctl
 514                          * DRM_IOCTL_MODE_GETCONNECTOR.
 515                          *
 516                          * .get_modes is called by .fill_modes.
 517                          *
 518                          * call .get_modes, AMDGPU DM implementation will create
 519                          * new dc_sink and add to dc_link. For long HPD plug
 520                          * in/out, MST has its own handle.
 521                          *
 522                          * Therefore, just after dc_create, link->sink is not
 523                          * created for MST until user mode app calls
 524                          * DRM_IOCTL_MODE_GETCONNECTOR.
 525                          *
 526                          * Need check ->sink usages in case ->sink = NULL
 527                          * TODO: s3 resume check
 528                          */
 529                         if (reason == DETECT_REASON_BOOT)
 530                                 boot = true;
 531
 532                         dm_helpers_dp_update_branch_info(
 533                                 link->ctx,
 534                                 link);
 535
 536                         if (!dm_helpers_dp_mst_start_top_mgr(
 537                                 link->ctx,
 538                                 link, boot)) {
 539                                 /* MST not supported */
 540                                 link->type = dc_connection_single;
 541                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 542                         }
 543                 }
 544
 545                 if (link->type != dc_connection_mst_branch &&
 546                         is_dp_active_dongle(link)) {
 547                         /* DP active dongles */
 548                         link->type = dc_connection_active_dongle;
 549                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 550                                 /*
 551                                  * active dongle unplug processing for short irq
 552                                  */
 553                                 link_disconnect_sink(link);
 554                                 return true;
 555                         }
 556
 557                         if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 558                                 *converter_disable_audio = true;
 559                 }
 560         } else {
 561                 /* DP passive dongles */
 562                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 563                                 sink_caps,
 564                                 audio_support);
 565         }
 566
 567         return true;
 568 }
 569
 570 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 571 {
 572         if (old_edid->length != new_edid->length)
 573                 return false;
 574
 575         if (new_edid->length == 0)
 576                 return false;
 577
 578         return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
 579 }
 580
 581 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 582 {
 583         struct dc_sink_init_data sink_init_data = { 0 };
 584         struct display_sink_capability sink_caps = { 0 };
 585         uint8_t i;
 586         bool converter_disable_audio = false;
 587         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 588         bool same_edid = false;
 589         enum dc_edid_status edid_status;
 590         struct dc_context *dc_ctx = link->ctx;
 591         struct dc_sink *sink = NULL;
 592         struct dc_sink *prev_sink = NULL;
 593         struct dpcd_caps prev_dpcd_caps;
 594         bool same_dpcd = true;
 595         enum dc_connection_type new_connection_type = dc_connection_none;
 596         DC_LOGGER_INIT(link->ctx->logger);
 597         if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
 598                 return false;
 599
 600         if (false == detect_sink(link, &new_connection_type)) {
 601                 BREAK_TO_DEBUGGER();
 602                 return false;
 603         }
 604
 605         if (link->connector_signal == SIGNAL_TYPE_EDP &&
 606                         link->local_sink)
 607                 return true;
 608
 609         prev_sink = link->local_sink;
 610         if (prev_sink != NULL) {
 611                 dc_sink_retain(prev_sink);
 612                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 613         }
 614         link_disconnect_sink(link);
 615
 616         if (new_connection_type != dc_connection_none) {
 617                 link->type = new_connection_type;
 618
 619                 /* From Disconnected-to-Connected. */
 620                 switch (link->connector_signal) {
 621                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 622                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 623                         if (aud_support->hdmi_audio_native)
 624                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 625                         else
 626                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 627                         break;
 628                 }
 629
 630                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 631                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 632                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 633                         break;
 634                 }
 635
 636                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 637                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 638                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 639                         break;
 640                 }
 641
 642                 case SIGNAL_TYPE_EDP: {
 643                         detect_edp_sink_caps(link);
 644                         sink_caps.transaction_type =
 645                                 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 646                         sink_caps.signal = SIGNAL_TYPE_EDP;
 647                         break;
 648                 }
 649
 650                 case SIGNAL_TYPE_DISPLAY_PORT: {
 651                         if (!detect_dp(
 652                                 link,
 653                                 &sink_caps,
 654                                 &converter_disable_audio,
 655                                 aud_support, reason)) {
 656                                 if (prev_sink != NULL)
 657                                         dc_sink_release(prev_sink);
 658                                 return false;
 659                         }
 660
 661                         // Check if dpcp block is the same
 662                         if (prev_sink != NULL) {
 663                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
 664                                         same_dpcd = false;
 665                         }
 666                         /* Active dongle downstream unplug */
 667                         if (link->type == dc_connection_active_dongle
 668                                         && link->dpcd_caps.sink_count.
 669                                         bits.SINK_COUNT == 0) {
 670                                 if (prev_sink != NULL)
 671                                         dc_sink_release(prev_sink);
 672                                 return true;
 673                         }
 674
 675                         if (link->type == dc_connection_mst_branch) {
 676                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 677                                         link->link_index);
 678                                 /* Need to setup mst link_cap struct here
 679                                  * otherwise dc_link_detect() will leave mst link_cap
 680                                  * empty which leads to allocate_mst_payload() has "0"
 681                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 682                                  */
 683                                 link->verified_link_cap = link->reported_link_cap;
 684                                 if (prev_sink != NULL)
 685                                         dc_sink_release(prev_sink);
 686                                 return false;
 687                         }
 688
 689                         break;
 690                 }
 691
 692                 default:
 693                         DC_ERROR("Invalid connector type! signal:%d\n",
 694                                 link->connector_signal);
 695                         if (prev_sink != NULL)
 696                                 dc_sink_release(prev_sink);
 697                         return false;
 698                 } /* switch() */
 699
 700                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
 701                         link->dpcd_sink_count = link->dpcd_caps.sink_count.
 702                                         bits.SINK_COUNT;
 703                 else
 704                         link->dpcd_sink_count = 1;
 705
 706                 dal_ddc_service_set_transaction_type(
 707                                                 link->ddc,
 708                                                 sink_caps.transaction_type);
 709
 710                 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
 711                                 link->ddc);
 712
 713                 sink_init_data.link = link;
 714                 sink_init_data.sink_signal = sink_caps.signal;
 715
 716                 sink = dc_sink_create(&sink_init_data);
 717                 if (!sink) {
 718                         DC_ERROR("Failed to create sink!\n");
 719                         if (prev_sink != NULL)
 720                                 dc_sink_release(prev_sink);
 721                         return false;
 722                 }
 723
 724                 sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
 725                 sink->converter_disable_audio = converter_disable_audio;
 726
 727                 link->local_sink = sink;
 728
 729                 edid_status = dm_helpers_read_local_edid(
 730                                 link->ctx,
 731                                 link,
 732                                 sink);
 733
 734                 switch (edid_status) {
 735                 case EDID_BAD_CHECKSUM:
 736                         DC_LOG_ERROR("EDID checksum invalid.\n");
 737                         break;
 738                 case EDID_NO_RESPONSE:
 739                         DC_LOG_ERROR("No EDID read.\n");
 740                 default:
 741                         break;
 742                 }
 743
 744                 // Check if edid is the same
 745                 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
 746                         same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
 747
 748                 // If both edid and dpcd are the same, then discard new sink and revert back to original sink
 749                 if ((same_edid) && (same_dpcd)) {
 750                         link_disconnect_remap(prev_sink, link);
 751                         sink = prev_sink;
 752                         prev_sink = NULL;
 753                 } else {
 754                         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 755                                         sink_caps.transaction_type ==
 756                                                 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 757                                 /*
 758                                  * TODO debug why Dell 2413 doesn't like
 759                                  *  two link trainings
 760                                  */
 761
 762                                 /* deal with non-mst cases */
 763                                 dp_hbr_verify_link_cap(link, &link->reported_link_cap);
 764                         }
 765
 766                         /* HDMI-DVI Dongle */
 767                         if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
 768                                         !sink->edid_caps.edid_hdmi)
 769                                 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 770                 }
 771
 772                 /* Connectivity log: detection */
 773                 for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
 774                         CONN_DATA_DETECT(link,
 775                                         &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
 776                                         EDID_BLOCK_SIZE,
 777                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
 778                 }
 779
 780                 DC_LOG_DETECTION_EDID_PARSER("%s: "
 781                         "manufacturer_id = %X, "
 782                         "product_id = %X, "
 783                         "serial_number = %X, "
 784                         "manufacture_week = %d, "
 785                         "manufacture_year = %d, "
 786                         "display_name = %s, "
 787                         "speaker_flag = %d, "
 788                         "audio_mode_count = %d\n",
 789                         __func__,
 790                         sink->edid_caps.manufacturer_id,
 791                         sink->edid_caps.product_id,
 792                         sink->edid_caps.serial_number,
 793                         sink->edid_caps.manufacture_week,
 794                         sink->edid_caps.manufacture_year,
 795                         sink->edid_caps.display_name,
 796                         sink->edid_caps.speaker_flags,
 797                         sink->edid_caps.audio_mode_count);
 798
 799                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
 800                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
 801                                 "format_code = %d, "
 802                                 "channel_count = %d, "
 803                                 "sample_rate = %d, "
 804                                 "sample_size = %d\n",
 805                                 __func__,
 806                                 i,
 807                                 sink->edid_caps.audio_modes[i].format_code,
 808                                 sink->edid_caps.audio_modes[i].channel_count,
 809                                 sink->edid_caps.audio_modes[i].sample_rate,
 810                                 sink->edid_caps.audio_modes[i].sample_size);
 811                 }
 812
 813         } else {
 814                 /* From Connected-to-Disconnected. */
 815                 if (link->type == dc_connection_mst_branch) {
 816                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 817                                 link->link_index);
 818
 819                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 820
 821                         link->mst_stream_alloc_table.stream_count = 0;
 822                         memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
 823                 }
 824
 825                 link->type = dc_connection_none;
 826                 sink_caps.signal = SIGNAL_TYPE_NONE;
 827         }
 828
 829         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
 830                 link->link_index, sink,
 831                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
 832                         "Disconnected":"Connected"), prev_sink,
 833                         same_dpcd, same_edid);
 834
 835         if (prev_sink != NULL)
 836                 dc_sink_release(prev_sink);
 837
 838         return true;
 839 }
 840
 841 static enum hpd_source_id get_hpd_line(
 842                 struct dc_link *link)
 843 {
 844         struct gpio *hpd;
 845         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
 846
 847         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 848
 849         if (hpd) {
 850                 switch (dal_irq_get_source(hpd)) {
 851                 case DC_IRQ_SOURCE_HPD1:
 852                         hpd_id = HPD_SOURCEID1;
 853                 break;
 854                 case DC_IRQ_SOURCE_HPD2:
 855                         hpd_id = HPD_SOURCEID2;
 856                 break;
 857                 case DC_IRQ_SOURCE_HPD3:
 858                         hpd_id = HPD_SOURCEID3;
 859                 break;
 860                 case DC_IRQ_SOURCE_HPD4:
 861                         hpd_id = HPD_SOURCEID4;
 862                 break;
 863                 case DC_IRQ_SOURCE_HPD5:
 864                         hpd_id = HPD_SOURCEID5;
 865                 break;
 866                 case DC_IRQ_SOURCE_HPD6:
 867                         hpd_id = HPD_SOURCEID6;
 868                 break;
 869                 default:
 870                         BREAK_TO_DEBUGGER();
 871                 break;
 872                 }
 873
 874                 dal_gpio_destroy_irq(&hpd);
 875         }
 876
 877         return hpd_id;
 878 }
 879
 880 static enum channel_id get_ddc_line(struct dc_link *link)
 881 {
 882         struct ddc *ddc;
 883         enum channel_id channel = CHANNEL_ID_UNKNOWN;
 884
 885         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 886
 887         if (ddc) {
 888                 switch (dal_ddc_get_line(ddc)) {
 889                 case GPIO_DDC_LINE_DDC1:
 890                         channel = CHANNEL_ID_DDC1;
 891                         break;
 892                 case GPIO_DDC_LINE_DDC2:
 893                         channel = CHANNEL_ID_DDC2;
 894                         break;
 895                 case GPIO_DDC_LINE_DDC3:
 896                         channel = CHANNEL_ID_DDC3;
 897                         break;
 898                 case GPIO_DDC_LINE_DDC4:
 899                         channel = CHANNEL_ID_DDC4;
 900                         break;
 901                 case GPIO_DDC_LINE_DDC5:
 902                         channel = CHANNEL_ID_DDC5;
 903                         break;
 904                 case GPIO_DDC_LINE_DDC6:
 905                         channel = CHANNEL_ID_DDC6;
 906                         break;
 907                 case GPIO_DDC_LINE_DDC_VGA:
 908                         channel = CHANNEL_ID_DDC_VGA;
 909                         break;
 910                 case GPIO_DDC_LINE_I2C_PAD:
 911                         channel = CHANNEL_ID_I2C_PAD;
 912                         break;
 913                 default:
 914                         BREAK_TO_DEBUGGER();
 915                         break;
 916                 }
 917         }
 918
 919         return channel;
 920 }
 921
 922 static enum transmitter translate_encoder_to_transmitter(
 923         struct graphics_object_id encoder)
 924 {
 925         switch (encoder.id) {
 926         case ENCODER_ID_INTERNAL_UNIPHY:
 927                 switch (encoder.enum_id) {
 928                 case ENUM_ID_1:
 929                         return TRANSMITTER_UNIPHY_A;
 930                 case ENUM_ID_2:
 931                         return TRANSMITTER_UNIPHY_B;
 932                 default:
 933                         return TRANSMITTER_UNKNOWN;
 934                 }
 935         break;
 936         case ENCODER_ID_INTERNAL_UNIPHY1:
 937                 switch (encoder.enum_id) {
 938                 case ENUM_ID_1:
 939                         return TRANSMITTER_UNIPHY_C;
 940                 case ENUM_ID_2:
 941                         return TRANSMITTER_UNIPHY_D;
 942                 default:
 943                         return TRANSMITTER_UNKNOWN;
 944                 }
 945         break;
 946         case ENCODER_ID_INTERNAL_UNIPHY2:
 947                 switch (encoder.enum_id) {
 948                 case ENUM_ID_1:
 949                         return TRANSMITTER_UNIPHY_E;
 950                 case ENUM_ID_2:
 951                         return TRANSMITTER_UNIPHY_F;
 952                 default:
 953                         return TRANSMITTER_UNKNOWN;
 954                 }
 955         break;
 956         case ENCODER_ID_INTERNAL_UNIPHY3:
 957                 switch (encoder.enum_id) {
 958                 case ENUM_ID_1:
 959                         return TRANSMITTER_UNIPHY_G;
 960                 default:
 961                         return TRANSMITTER_UNKNOWN;
 962                 }
 963         break;
 964         case ENCODER_ID_EXTERNAL_NUTMEG:
 965                 switch (encoder.enum_id) {
 966                 case ENUM_ID_1:
 967                         return TRANSMITTER_NUTMEG_CRT;
 968                 default:
 969                         return TRANSMITTER_UNKNOWN;
 970                 }
 971         break;
 972         case ENCODER_ID_EXTERNAL_TRAVIS:
 973                 switch (encoder.enum_id) {
 974                 case ENUM_ID_1:
 975                         return TRANSMITTER_TRAVIS_CRT;
 976                 case ENUM_ID_2:
 977                         return TRANSMITTER_TRAVIS_LCD;
 978                 default:
 979                         return TRANSMITTER_UNKNOWN;
 980                 }
 981         break;
 982         default:
 983                 return TRANSMITTER_UNKNOWN;
 984         }
 985 }
 986
 987 static bool construct(
 988         struct dc_link *link,
 989         const struct link_init_data *init_params)
 990 {
 991         uint8_t i;
 992         struct gpio *hpd_gpio = NULL;
 993         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
 994         struct dc_context *dc_ctx = init_params->ctx;
 995         struct encoder_init_data enc_init_data = { 0 };
 996         struct integrated_info info = {{{ 0 }}};
 997         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
 998         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
 999         DC_LOGGER_INIT(dc_ctx->logger);
1000
1001         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1002         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1003
1004         link->link_status.dpcd_caps = &link->dpcd_caps;
1005
1006         link->dc = init_params->dc;
1007         link->ctx = dc_ctx;
1008         link->link_index = init_params->link_index;
1009
1010         link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1011
1012         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1013                 dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1014                          __func__, init_params->connector_index,
1015                          link->link_id.type, OBJECT_TYPE_CONNECTOR);
1016                 goto create_fail;
1017         }
1018
1019         hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1020
1021         if (hpd_gpio != NULL)
1022                 link->irq_source_hpd = dal_irq_get_source(hpd_gpio);
1023
1024         switch (link->link_id.id) {
1025         case CONNECTOR_ID_HDMI_TYPE_A:
1026                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1027
1028                 break;
1029         case CONNECTOR_ID_SINGLE_LINK_DVID:
1030         case CONNECTOR_ID_SINGLE_LINK_DVII:
1031                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1032                 break;
1033         case CONNECTOR_ID_DUAL_LINK_DVID:
1034         case CONNECTOR_ID_DUAL_LINK_DVII:
1035                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1036                 break;
1037         case CONNECTOR_ID_DISPLAY_PORT:
1038                 link->connector_signal =        SIGNAL_TYPE_DISPLAY_PORT;
1039
1040                 if (hpd_gpio != NULL)
1041                         link->irq_source_hpd_rx =
1042                                         dal_irq_get_rx_source(hpd_gpio);
1043
1044                 break;
1045         case CONNECTOR_ID_EDP:
1046                 link->connector_signal = SIGNAL_TYPE_EDP;
1047
1048                 if (hpd_gpio != NULL) {
1049                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1050                         link->irq_source_hpd_rx =
1051                                         dal_irq_get_rx_source(hpd_gpio);
1052                 }
1053                 break;
1054         default:
1055                 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1056                 goto create_fail;
1057         }
1058
1059         if (hpd_gpio != NULL) {
1060                 dal_gpio_destroy_irq(&hpd_gpio);
1061                 hpd_gpio = NULL;
1062         }
1063
1064         /* TODO: #DAL3 Implement id to str function.*/
1065         LINK_INFO("Connector[%d] description:"
1066                         "signal %d\n",
1067                         init_params->connector_index,
1068                         link->connector_signal);
1069
1070         ddc_service_init_data.ctx = link->ctx;
1071         ddc_service_init_data.id = link->link_id;
1072         ddc_service_init_data.link = link;
1073         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1074
1075         if (link->ddc == NULL) {
1076                 DC_ERROR("Failed to create ddc_service!\n");
1077                 goto ddc_create_fail;
1078         }
1079
1080         link->ddc_hw_inst =
1081                 dal_ddc_get_line(
1082                         dal_ddc_service_get_ddc_pin(link->ddc));
1083
1084         enc_init_data.ctx = dc_ctx;
1085         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1086         enc_init_data.connector = link->link_id;
1087         enc_init_data.channel = get_ddc_line(link);
1088         enc_init_data.hpd_source = get_hpd_line(link);
1089
1090         link->hpd_src = enc_init_data.hpd_source;
1091
1092         enc_init_data.transmitter =
1093                         translate_encoder_to_transmitter(enc_init_data.encoder);
1094         link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1095                                                                 &enc_init_data);
1096
1097         if( link->link_enc == NULL) {
1098                 DC_ERROR("Failed to create link encoder!\n");
1099                 goto link_enc_create_fail;
1100         }
1101
1102         link->link_enc_hw_inst = link->link_enc->transmitter;
1103
1104         for (i = 0; i < 4; i++) {
1105                 if (BP_RESULT_OK !=
1106                                 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1107                         DC_ERROR("Failed to find device tag!\n");
1108                         goto device_tag_fail;
1109                 }
1110
1111                 /* Look for device tag that matches connector signal,
1112                  * CRT for rgb, LCD for other supported signal tyes
1113                  */
1114                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1115                         continue;
1116                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1117                         && link->connector_signal != SIGNAL_TYPE_RGB)
1118                         continue;
1119                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1120                         && link->connector_signal == SIGNAL_TYPE_RGB)
1121                         continue;
1122                 break;
1123         }
1124
1125         if (bios->integrated_info)
1126                 info = *bios->integrated_info;
1127
1128         /* Look for channel mapping corresponding to connector and device tag */
1129         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1130                 struct external_display_path *path =
1131                         &info.ext_disp_conn_info.path[i];
1132                 if (path->device_connector_id.enum_id == link->link_id.enum_id
1133                         && path->device_connector_id.id == link->link_id.id
1134                         && path->device_connector_id.type == link->link_id.type) {
1135
1136                         if (link->device_tag.acpi_device != 0
1137                                 && path->device_acpi_enum == link->device_tag.acpi_device) {
1138                                 link->ddi_channel_mapping = path->channel_mapping;
1139                                 link->chip_caps = path->caps;
1140                         } else if (path->device_tag ==
1141                                         link->device_tag.dev_id.raw_device_tag) {
1142                                 link->ddi_channel_mapping = path->channel_mapping;
1143                                 link->chip_caps = path->caps;
1144                         }
1145                         break;
1146                 }
1147         }
1148
1149         /*
1150          * TODO check if GPIO programmed correctly
1151          *
1152          * If GPIO isn't programmed correctly HPD might not rise or drain
1153          * fast enough, leading to bounces.
1154          */
1155         program_hpd_filter(link);
1156
1157         return true;
1158 device_tag_fail:
1159         link->link_enc->funcs->destroy(&link->link_enc);
1160 link_enc_create_fail:
1161         dal_ddc_service_destroy(&link->ddc);
1162 ddc_create_fail:
1163 create_fail:
1164
1165         if (hpd_gpio != NULL) {
1166                 dal_gpio_destroy_irq(&hpd_gpio);
1167         }
1168
1169         return false;
1170 }
1171
1172 /*******************************************************************************
1173  * Public functions
1174  ******************************************************************************/
1175 struct dc_link *link_create(const struct link_init_data *init_params)
1176 {
1177         struct dc_link *link =
1178                         kzalloc(sizeof(*link), GFP_KERNEL);
1179
1180         if (NULL == link)
1181                 goto alloc_fail;
1182
1183         if (false == construct(link, init_params))
1184                 goto construct_fail;
1185
1186         return link;
1187
1188 construct_fail:
1189         kfree(link);
1190
1191 alloc_fail:
1192         return NULL;
1193 }
1194
1195 void link_destroy(struct dc_link **link)
1196 {
1197         destruct(*link);
1198         kfree(*link);
1199         *link = NULL;
1200 }
1201
1202 static void dpcd_configure_panel_mode(
1203         struct dc_link *link,
1204         enum dp_panel_mode panel_mode)
1205 {
1206         union dpcd_edp_config edp_config_set;
1207         bool panel_mode_edp = false;
1208         DC_LOGGER_INIT(link->ctx->logger);
1209
1210         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
1211
1212         if (DP_PANEL_MODE_DEFAULT != panel_mode) {
1213
1214                 switch (panel_mode) {
1215                 case DP_PANEL_MODE_EDP:
1216                 case DP_PANEL_MODE_SPECIAL:
1217                         panel_mode_edp = true;
1218                         break;
1219
1220                 default:
1221                         break;
1222                 }
1223
1224                 /*set edp panel mode in receiver*/
1225                 core_link_read_dpcd(
1226                         link,
1227                         DP_EDP_CONFIGURATION_SET,
1228                         &edp_config_set.raw,
1229                         sizeof(edp_config_set.raw));
1230
1231                 if (edp_config_set.bits.PANEL_MODE_EDP
1232                         != panel_mode_edp) {
1233                         enum ddc_result result = DDC_RESULT_UNKNOWN;
1234
1235                         edp_config_set.bits.PANEL_MODE_EDP =
1236                         panel_mode_edp;
1237                         result = core_link_write_dpcd(
1238                                 link,
1239                                 DP_EDP_CONFIGURATION_SET,
1240                                 &edp_config_set.raw,
1241                                 sizeof(edp_config_set.raw));
1242
1243                         ASSERT(result == DDC_RESULT_SUCESSFULL);
1244                 }
1245         }
1246         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
1247                         "eDP panel mode enabled: %d \n",
1248                         link->link_index,
1249                         link->dpcd_caps.panel_mode_edp,
1250                         panel_mode_edp);
1251 }
1252
1253 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1254 {
1255         struct dc_stream_state *stream = pipe_ctx->stream;
1256         struct dc_link *link = stream->sink->link;
1257         union down_spread_ctrl old_downspread;
1258         union down_spread_ctrl new_downspread;
1259
1260         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1261                         &old_downspread.raw, sizeof(old_downspread));
1262
1263         new_downspread.raw = old_downspread.raw;
1264
1265         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1266                         (stream->ignore_msa_timing_param) ? 1 : 0;
1267
1268         if (new_downspread.raw != old_downspread.raw) {
1269                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1270                         &new_downspread.raw, sizeof(new_downspread));
1271         }
1272 }
1273
1274 static enum dc_status enable_link_dp(
1275                 struct dc_state *state,
1276                 struct pipe_ctx *pipe_ctx)
1277 {
1278         struct dc_stream_state *stream = pipe_ctx->stream;
1279         enum dc_status status;
1280         bool skip_video_pattern;
1281         struct dc_link *link = stream->sink->link;
1282         struct dc_link_settings link_settings = {0};
1283         enum dp_panel_mode panel_mode;
1284         enum dc_link_rate max_link_rate = LINK_RATE_HIGH2;
1285
1286         /* get link settings for video mode timing */
1287         decide_link_settings(stream, &link_settings);
1288
1289         /* raise clock state for HBR3 if required. Confirmed with HW DCE/DPCS
1290          * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
1291          */
1292         if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1293                 max_link_rate = LINK_RATE_HIGH3;
1294
1295         if (link_settings.link_rate == max_link_rate) {
1296                 struct dc_clocks clocks = state->bw.dcn.clk;
1297
1298                 /* dce/dcn compat, do not update dispclk */
1299                 clocks.dispclk_khz = 0;
1300                 /* 27mhz = 27000000hz= 27000khz */
1301                 clocks.phyclk_khz = link_settings.link_rate * 27000;
1302
1303                 state->dis_clk->funcs->update_clocks(
1304                                 state->dis_clk, &clocks, false);
1305         }
1306
1307         dp_enable_link_phy(
1308                 link,
1309                 pipe_ctx->stream->signal,
1310                 pipe_ctx->clock_source->id,
1311                 &link_settings);
1312
1313         if (stream->sink->edid_caps.panel_patch.dppowerup_delay > 0) {
1314                 int delay_dp_power_up_in_ms = stream->sink->edid_caps.panel_patch.dppowerup_delay;
1315
1316                 msleep(delay_dp_power_up_in_ms);
1317         }
1318
1319         panel_mode = dp_get_panel_mode(link);
1320         dpcd_configure_panel_mode(link, panel_mode);
1321
1322         skip_video_pattern = true;
1323
1324         if (link_settings.link_rate == LINK_RATE_LOW)
1325                         skip_video_pattern = false;
1326
1327         if (perform_link_training_with_retries(
1328                         link,
1329                         &link_settings,
1330                         skip_video_pattern,
1331                         LINK_TRAINING_ATTEMPTS)) {
1332                 link->cur_link_settings = link_settings;
1333                 status = DC_OK;
1334         }
1335         else
1336                 status = DC_FAIL_DP_LINK_TRAINING;
1337
1338         enable_stream_features(pipe_ctx);
1339
1340         return status;
1341 }
1342
1343 static enum dc_status enable_link_edp(
1344                 struct dc_state *state,
1345                 struct pipe_ctx *pipe_ctx)
1346 {
1347         enum dc_status status;
1348         struct dc_stream_state *stream = pipe_ctx->stream;
1349         struct dc_link *link = stream->sink->link;
1350         /*in case it is not on*/
1351         link->dc->hwss.edp_power_control(link, true);
1352         link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1353
1354         status = enable_link_dp(state, pipe_ctx);
1355
1356
1357         return status;
1358 }
1359
1360 static enum dc_status enable_link_dp_mst(
1361                 struct dc_state *state,
1362                 struct pipe_ctx *pipe_ctx)
1363 {
1364         struct dc_link *link = pipe_ctx->stream->sink->link;
1365
1366         /* sink signal type after MST branch is MST. Multiple MST sinks
1367          * share one link. Link DP PHY is enable or training only once.
1368          */
1369         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1370                 return DC_OK;
1371
1372         /* clear payload table */
1373         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1374
1375         /* set the sink to MST mode before enabling the link */
1376         dp_enable_mst_on_sink(link, true);
1377
1378         return enable_link_dp(state, pipe_ctx);
1379 }
1380
1381 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1382                 enum engine_id eng_id,
1383                 struct ext_hdmi_settings *settings)
1384 {
1385         bool result = false;
1386         int i = 0;
1387         struct integrated_info *integrated_info =
1388                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1389
1390         if (integrated_info == NULL)
1391                 return false;
1392
1393         /*
1394          * Get retimer settings from sbios for passing SI eye test for DCE11
1395          * The setting values are varied based on board revision and port id
1396          * Therefore the setting values of each ports is passed by sbios.
1397          */
1398
1399         // Check if current bios contains ext Hdmi settings
1400         if (integrated_info->gpu_cap_info & 0x20) {
1401                 switch (eng_id) {
1402                 case ENGINE_ID_DIGA:
1403                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1404                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1405                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1406                         memmove(settings->reg_settings,
1407                                         integrated_info->dp0_ext_hdmi_reg_settings,
1408                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1409                         memmove(settings->reg_settings_6g,
1410                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1411                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1412                         result = true;
1413                         break;
1414                 case ENGINE_ID_DIGB:
1415                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1416                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1417                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1418                         memmove(settings->reg_settings,
1419                                         integrated_info->dp1_ext_hdmi_reg_settings,
1420                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1421                         memmove(settings->reg_settings_6g,
1422                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1423                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1424                         result = true;
1425                         break;
1426                 case ENGINE_ID_DIGC:
1427                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1428                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1429                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1430                         memmove(settings->reg_settings,
1431                                         integrated_info->dp2_ext_hdmi_reg_settings,
1432                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1433                         memmove(settings->reg_settings_6g,
1434                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1435                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1436                         result = true;
1437                         break;
1438                 case ENGINE_ID_DIGD:
1439                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1440                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1441                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1442                         memmove(settings->reg_settings,
1443                                         integrated_info->dp3_ext_hdmi_reg_settings,
1444                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1445                         memmove(settings->reg_settings_6g,
1446                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1447                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1448                         result = true;
1449                         break;
1450                 default:
1451                         break;
1452                 }
1453
1454                 if (result == true) {
1455                         // Validate settings from bios integrated info table
1456                         if (settings->slv_addr == 0)
1457                                 return false;
1458                         if (settings->reg_num > 9)
1459                                 return false;
1460                         if (settings->reg_num_6g > 3)
1461                                 return false;
1462
1463                         for (i = 0; i < settings->reg_num; i++) {
1464                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1465                                         return false;
1466                         }
1467
1468                         for (i = 0; i < settings->reg_num_6g; i++) {
1469                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1470                                         return false;
1471                         }
1472                 }
1473         }
1474
1475         return result;
1476 }
1477
1478 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1479                 uint8_t address, uint8_t *buffer, uint32_t length)
1480 {
1481         struct i2c_command cmd = {0};
1482         struct i2c_payload payload = {0};
1483
1484         memset(&payload, 0, sizeof(payload));
1485         memset(&cmd, 0, sizeof(cmd));
1486
1487         cmd.number_of_payloads = 1;
1488         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1489         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1490
1491         payload.address = address;
1492         payload.data = buffer;
1493         payload.length = length;
1494         payload.write = true;
1495         cmd.payloads = &payload;
1496
1497         if (dc_submit_i2c(pipe_ctx->stream->ctx->dc,
1498                         pipe_ctx->stream->sink->link->link_index, &cmd))
1499                 return true;
1500
1501         return false;
1502 }
1503
1504 static void write_i2c_retimer_setting(
1505                 struct pipe_ctx *pipe_ctx,
1506                 bool is_vga_mode,
1507                 bool is_over_340mhz,
1508                 struct ext_hdmi_settings *settings)
1509 {
1510         uint8_t slave_address = (settings->slv_addr >> 1);
1511         uint8_t buffer[2];
1512         const uint8_t apply_rx_tx_change = 0x4;
1513         uint8_t offset = 0xA;
1514         uint8_t value = 0;
1515         int i = 0;
1516         bool i2c_success = false;
1517
1518         memset(&buffer, 0, sizeof(buffer));
1519
1520         /* Start Ext-Hdmi programming*/
1521
1522         for (i = 0; i < settings->reg_num; i++) {
1523                 /* Apply 3G settings */
1524                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1525
1526                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1527                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1528                         i2c_success = i2c_write(pipe_ctx, slave_address,
1529                                                 buffer, sizeof(buffer));
1530
1531                         if (!i2c_success)
1532                                 /* Write failure */
1533                                 ASSERT(i2c_success);
1534
1535                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1536                          * needs to be set to 1 on every 0xA-0xC write.
1537                          */
1538                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1539                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1540                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1541
1542                                 /* Query current value from offset 0xA */
1543                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1544                                         value = settings->reg_settings[i].i2c_reg_val;
1545                                 else {
1546                                         i2c_success =
1547                                                 dal_ddc_service_query_ddc_data(
1548                                                 pipe_ctx->stream->sink->link->ddc,
1549                                                 slave_address, &offset, 1, &value, 1);
1550                                         if (!i2c_success)
1551                                                 /* Write failure */
1552                                                 ASSERT(i2c_success);
1553                                 }
1554
1555                                 buffer[0] = offset;
1556                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1557                                 buffer[1] = value | apply_rx_tx_change;
1558                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1559                                                 buffer, sizeof(buffer));
1560                                 if (!i2c_success)
1561                                         /* Write failure */
1562                                         ASSERT(i2c_success);
1563                         }
1564                 }
1565         }
1566
1567         /* Apply 3G settings */
1568         if (is_over_340mhz) {
1569                 for (i = 0; i < settings->reg_num_6g; i++) {
1570                         /* Apply 3G settings */
1571                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1572
1573                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1574                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1575                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1576                                                         buffer, sizeof(buffer));
1577
1578                                 if (!i2c_success)
1579                                         /* Write failure */
1580                                         ASSERT(i2c_success);
1581
1582                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1583                                  * needs to be set to 1 on every 0xA-0xC write.
1584                                  */
1585                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1586                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1587                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1588
1589                                         /* Query current value from offset 0xA */
1590                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1591                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1592                                         else {
1593                                                 i2c_success =
1594                                                                 dal_ddc_service_query_ddc_data(
1595                                                                 pipe_ctx->stream->sink->link->ddc,
1596                                                                 slave_address, &offset, 1, &value, 1);
1597                                                 if (!i2c_success)
1598                                                         /* Write failure */
1599                                                         ASSERT(i2c_success);
1600                                         }
1601
1602                                         buffer[0] = offset;
1603                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1604                                         buffer[1] = value | apply_rx_tx_change;
1605                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1606                                                         buffer, sizeof(buffer));
1607                                         if (!i2c_success)
1608                                                 /* Write failure */
1609                                                 ASSERT(i2c_success);
1610                                 }
1611                         }
1612                 }
1613         }
1614
1615         if (is_vga_mode) {
1616                 /* Program additional settings if using 640x480 resolution */
1617
1618                 /* Write offset 0xFF to 0x01 */
1619                 buffer[0] = 0xff;
1620                 buffer[1] = 0x01;
1621                 i2c_success = i2c_write(pipe_ctx, slave_address,
1622                                 buffer, sizeof(buffer));
1623                 if (!i2c_success)
1624                         /* Write failure */
1625                         ASSERT(i2c_success);
1626
1627                 /* Write offset 0x00 to 0x23 */
1628                 buffer[0] = 0x00;
1629                 buffer[1] = 0x23;
1630                 i2c_success = i2c_write(pipe_ctx, slave_address,
1631                                 buffer, sizeof(buffer));
1632                 if (!i2c_success)
1633                         /* Write failure */
1634                         ASSERT(i2c_success);
1635
1636                 /* Write offset 0xff to 0x00 */
1637                 buffer[0] = 0xff;
1638                 buffer[1] = 0x00;
1639                 i2c_success = i2c_write(pipe_ctx, slave_address,
1640                                 buffer, sizeof(buffer));
1641                 if (!i2c_success)
1642                         /* Write failure */
1643                         ASSERT(i2c_success);
1644
1645         }
1646 }
1647
1648 static void write_i2c_default_retimer_setting(
1649                 struct pipe_ctx *pipe_ctx,
1650                 bool is_vga_mode,
1651                 bool is_over_340mhz)
1652 {
1653         uint8_t slave_address = (0xBA >> 1);
1654         uint8_t buffer[2];
1655         bool i2c_success = false;
1656
1657         memset(&buffer, 0, sizeof(buffer));
1658
1659         /* Program Slave Address for tuning single integrity */
1660         /* Write offset 0x0A to 0x13 */
1661         buffer[0] = 0x0A;
1662         buffer[1] = 0x13;
1663         i2c_success = i2c_write(pipe_ctx, slave_address,
1664                         buffer, sizeof(buffer));
1665         if (!i2c_success)
1666                 /* Write failure */
1667                 ASSERT(i2c_success);
1668
1669         /* Write offset 0x0A to 0x17 */
1670         buffer[0] = 0x0A;
1671         buffer[1] = 0x17;
1672         i2c_success = i2c_write(pipe_ctx, slave_address,
1673                         buffer, sizeof(buffer));
1674         if (!i2c_success)
1675                 /* Write failure */
1676                 ASSERT(i2c_success);
1677
1678         /* Write offset 0x0B to 0xDA or 0xD8 */
1679         buffer[0] = 0x0B;
1680         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1681         i2c_success = i2c_write(pipe_ctx, slave_address,
1682                         buffer, sizeof(buffer));
1683         if (!i2c_success)
1684                 /* Write failure */
1685                 ASSERT(i2c_success);
1686
1687         /* Write offset 0x0A to 0x17 */
1688         buffer[0] = 0x0A;
1689         buffer[1] = 0x17;
1690         i2c_success = i2c_write(pipe_ctx, slave_address,
1691                         buffer, sizeof(buffer));
1692         if (!i2c_success)
1693                 /* Write failure */
1694                 ASSERT(i2c_success);
1695
1696         /* Write offset 0x0C to 0x1D or 0x91 */
1697         buffer[0] = 0x0C;
1698         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1699         i2c_success = i2c_write(pipe_ctx, slave_address,
1700                         buffer, sizeof(buffer));
1701         if (!i2c_success)
1702                 /* Write failure */
1703                 ASSERT(i2c_success);
1704
1705         /* Write offset 0x0A to 0x17 */
1706         buffer[0] = 0x0A;
1707         buffer[1] = 0x17;
1708         i2c_success = i2c_write(pipe_ctx, slave_address,
1709                         buffer, sizeof(buffer));
1710         if (!i2c_success)
1711                 /* Write failure */
1712                 ASSERT(i2c_success);
1713
1714
1715         if (is_vga_mode) {
1716                 /* Program additional settings if using 640x480 resolution */
1717
1718                 /* Write offset 0xFF to 0x01 */
1719                 buffer[0] = 0xff;
1720                 buffer[1] = 0x01;
1721                 i2c_success = i2c_write(pipe_ctx, slave_address,
1722                                 buffer, sizeof(buffer));
1723                 if (!i2c_success)
1724                         /* Write failure */
1725                         ASSERT(i2c_success);
1726
1727                 /* Write offset 0x00 to 0x23 */
1728                 buffer[0] = 0x00;
1729                 buffer[1] = 0x23;
1730                 i2c_success = i2c_write(pipe_ctx, slave_address,
1731                                 buffer, sizeof(buffer));
1732                 if (!i2c_success)
1733                         /* Write failure */
1734                         ASSERT(i2c_success);
1735
1736                 /* Write offset 0xff to 0x00 */
1737                 buffer[0] = 0xff;
1738                 buffer[1] = 0x00;
1739                 i2c_success = i2c_write(pipe_ctx, slave_address,
1740                                 buffer, sizeof(buffer));
1741                 if (!i2c_success)
1742                         /* Write failure */
1743                         ASSERT(i2c_success);
1744         }
1745 }
1746
1747 static void write_i2c_redriver_setting(
1748                 struct pipe_ctx *pipe_ctx,
1749                 bool is_over_340mhz)
1750 {
1751         uint8_t slave_address = (0xF0 >> 1);
1752         uint8_t buffer[16];
1753         bool i2c_success = false;
1754
1755         memset(&buffer, 0, sizeof(buffer));
1756
1757         // Program Slave Address for tuning single integrity
1758         buffer[3] = 0x4E;
1759         buffer[4] = 0x4E;
1760         buffer[5] = 0x4E;
1761         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
1762
1763         i2c_success = i2c_write(pipe_ctx, slave_address,
1764                                         buffer, sizeof(buffer));
1765
1766         if (!i2c_success)
1767                 /* Write failure */
1768                 ASSERT(i2c_success);
1769 }
1770
1771 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1772 {
1773         struct dc_stream_state *stream = pipe_ctx->stream;
1774         struct dc_link *link = stream->sink->link;
1775         enum dc_color_depth display_color_depth;
1776         enum engine_id eng_id;
1777         struct ext_hdmi_settings settings = {0};
1778         bool is_over_340mhz = false;
1779         bool is_vga_mode = (stream->timing.h_addressable == 640)
1780                         && (stream->timing.v_addressable == 480);
1781
1782         if (stream->phy_pix_clk > 340000)
1783                 is_over_340mhz = true;
1784
1785         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
1786                 unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
1787                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1788                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1789                         /* DP159, Retimer settings */
1790                         eng_id = pipe_ctx->stream_res.stream_enc->id;
1791
1792                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
1793                                 write_i2c_retimer_setting(pipe_ctx,
1794                                                 is_vga_mode, is_over_340mhz, &settings);
1795                         } else {
1796                                 write_i2c_default_retimer_setting(pipe_ctx,
1797                                                 is_vga_mode, is_over_340mhz);
1798                         }
1799                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
1800                         /* PI3EQX1204, Redriver settings */
1801                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
1802                 }
1803         }
1804
1805         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1806                 dal_ddc_service_write_scdc_data(
1807                         stream->sink->link->ddc,
1808                         stream->phy_pix_clk,
1809                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
1810
1811         memset(&stream->sink->link->cur_link_settings, 0,
1812                         sizeof(struct dc_link_settings));
1813
1814         display_color_depth = stream->timing.display_color_depth;
1815         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1816                 display_color_depth = COLOR_DEPTH_888;
1817
1818         link->link_enc->funcs->enable_tmds_output(
1819                         link->link_enc,
1820                         pipe_ctx->clock_source->id,
1821                         display_color_depth,
1822                         pipe_ctx->stream->signal,
1823                         stream->phy_pix_clk);
1824
1825         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
1826                 dal_ddc_service_read_scdc_data(link->ddc);
1827 }
1828
1829 /****************************enable_link***********************************/
1830 static enum dc_status enable_link(
1831                 struct dc_state *state,
1832                 struct pipe_ctx *pipe_ctx)
1833 {
1834         enum dc_status status = DC_ERROR_UNEXPECTED;
1835         switch (pipe_ctx->stream->signal) {
1836         case SIGNAL_TYPE_DISPLAY_PORT:
1837                 status = enable_link_dp(state, pipe_ctx);
1838                 break;
1839         case SIGNAL_TYPE_EDP:
1840                 status = enable_link_edp(state, pipe_ctx);
1841                 break;
1842         case SIGNAL_TYPE_DISPLAY_PORT_MST:
1843                 status = enable_link_dp_mst(state, pipe_ctx);
1844                 msleep(200);
1845                 break;
1846         case SIGNAL_TYPE_DVI_SINGLE_LINK:
1847         case SIGNAL_TYPE_DVI_DUAL_LINK:
1848         case SIGNAL_TYPE_HDMI_TYPE_A:
1849                 enable_link_hdmi(pipe_ctx);
1850                 status = DC_OK;
1851                 break;
1852         case SIGNAL_TYPE_VIRTUAL:
1853                 status = DC_OK;
1854                 break;
1855         default:
1856                 break;
1857         }
1858
1859         return status;
1860 }
1861
1862 static void disable_link(struct dc_link *link, enum signal_type signal)
1863 {
1864         /*
1865          * TODO: implement call for dp_set_hw_test_pattern
1866          * it is needed for compliance testing
1867          */
1868
1869         /* here we need to specify that encoder output settings
1870          * need to be calculated as for the set mode,
1871          * it will lead to querying dynamic link capabilities
1872          * which should be done before enable output */
1873
1874         if (dc_is_dp_signal(signal)) {
1875                 /* SST DP, eDP */
1876                 if (dc_is_dp_sst_signal(signal))
1877                         dp_disable_link_phy(link, signal);
1878                 else
1879                         dp_disable_link_phy_mst(link, signal);
1880         } else
1881                 link->link_enc->funcs->disable_output(link->link_enc, signal);
1882 }
1883
1884 static bool dp_active_dongle_validate_timing(
1885                 const struct dc_crtc_timing *timing,
1886                 const struct dpcd_caps *dpcd_caps)
1887 {
1888         unsigned int required_pix_clk = timing->pix_clk_khz;
1889         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
1890
1891         switch (dpcd_caps->dongle_type) {
1892         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
1893         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
1894         case DISPLAY_DONGLE_DP_DVI_DONGLE:
1895                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
1896                         return true;
1897                 else
1898                         return false;
1899         default:
1900                 break;
1901         }
1902
1903         if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
1904                 dongle_caps->extendedCapValid == false)
1905                 return true;
1906
1907         /* Check Pixel Encoding */
1908         switch (timing->pixel_encoding) {
1909         case PIXEL_ENCODING_RGB:
1910         case PIXEL_ENCODING_YCBCR444:
1911                 break;
1912         case PIXEL_ENCODING_YCBCR422:
1913                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
1914                         return false;
1915                 break;
1916         case PIXEL_ENCODING_YCBCR420:
1917                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
1918                         return false;
1919                 break;
1920         default:
1921                 /* Invalid Pixel Encoding*/
1922                 return false;
1923         }
1924
1925
1926         /* Check Color Depth and Pixel Clock */
1927         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1928                 required_pix_clk /= 2;
1929         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
1930                 required_pix_clk = required_pix_clk * 2 / 3;
1931
1932         switch (timing->display_color_depth) {
1933         case COLOR_DEPTH_666:
1934         case COLOR_DEPTH_888:
1935                 /*888 and 666 should always be supported*/
1936                 break;
1937         case COLOR_DEPTH_101010:
1938                 if (dongle_caps->dp_hdmi_max_bpc < 10)
1939                         return false;
1940                 required_pix_clk = required_pix_clk * 10 / 8;
1941                 break;
1942         case COLOR_DEPTH_121212:
1943                 if (dongle_caps->dp_hdmi_max_bpc < 12)
1944                         return false;
1945                 required_pix_clk = required_pix_clk * 12 / 8;
1946                 break;
1947
1948         case COLOR_DEPTH_141414:
1949         case COLOR_DEPTH_161616:
1950         default:
1951                 /* These color depths are currently not supported */
1952                 return false;
1953         }
1954
1955         if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
1956                 return false;
1957
1958         return true;
1959 }
1960
1961 enum dc_status dc_link_validate_mode_timing(
1962                 const struct dc_stream_state *stream,
1963                 struct dc_link *link,
1964                 const struct dc_crtc_timing *timing)
1965 {
1966         uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
1967         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
1968
1969         /* A hack to avoid failing any modes for EDID override feature on
1970          * topology change such as lower quality cable for DP or different dongle
1971          */
1972         if (link->remote_sinks[0])
1973                 return DC_OK;
1974
1975         /* Passive Dongle */
1976         if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
1977                 return DC_EXCEED_DONGLE_CAP;
1978
1979         /* Active Dongle*/
1980         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
1981                 return DC_EXCEED_DONGLE_CAP;
1982
1983         switch (stream->signal) {
1984         case SIGNAL_TYPE_EDP:
1985         case SIGNAL_TYPE_DISPLAY_PORT:
1986                 if (!dp_validate_mode_timing(
1987                                 link,
1988                                 timing))
1989                         return DC_NO_DP_LINK_BANDWIDTH;
1990                 break;
1991
1992         default:
1993                 break;
1994         }
1995
1996         return DC_OK;
1997 }
1998
1999
2000 bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
2001                 uint32_t frame_ramp, const struct dc_stream_state *stream)
2002 {
2003         struct dc  *core_dc = link->ctx->dc;
2004         struct abm *abm = core_dc->res_pool->abm;
2005         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2006         unsigned int controller_id = 0;
2007         bool use_smooth_brightness = true;
2008         int i;
2009         DC_LOGGER_INIT(link->ctx->logger);
2010
2011         if ((dmcu == NULL) ||
2012                 (abm == NULL) ||
2013                 (abm->funcs->set_backlight_level == NULL))
2014                 return false;
2015
2016         if (stream) {
2017                 if (stream->bl_pwm_level == EDP_BACKLIGHT_RAMP_DISABLE_LEVEL)
2018                         frame_ramp = 0;
2019
2020                 ((struct dc_stream_state *)stream)->bl_pwm_level = level;
2021         }
2022
2023         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2024
2025         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n", level, level);
2026
2027         if (dc_is_embedded_signal(link->connector_signal)) {
2028                 if (stream != NULL) {
2029                         for (i = 0; i < MAX_PIPES; i++) {
2030                                 if (core_dc->current_state->res_ctx.
2031                                                 pipe_ctx[i].stream
2032                                                 == stream)
2033                                         /* DMCU -1 for all controller id values,
2034                                          * therefore +1 here
2035                                          */
2036                                         controller_id =
2037                                                 core_dc->current_state->
2038                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2039                                                 1;
2040                         }
2041                 }
2042                 abm->funcs->set_backlight_level(
2043                                 abm,
2044                                 level,
2045                                 frame_ramp,
2046                                 controller_id,
2047                                 use_smooth_brightness);
2048         }
2049
2050         return true;
2051 }
2052
2053 bool dc_link_set_abm_disable(const struct dc_link *link)
2054 {
2055         struct dc  *core_dc = link->ctx->dc;
2056         struct abm *abm = core_dc->res_pool->abm;
2057
2058         if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL))
2059                 return false;
2060
2061         abm->funcs->set_abm_immediate_disable(abm);
2062
2063         return true;
2064 }
2065
2066 bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
2067 {
2068         struct dc  *core_dc = link->ctx->dc;
2069         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2070
2071         if (dmcu != NULL && link->psr_enabled)
2072                 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
2073
2074         return true;
2075 }
2076
2077 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2078 {
2079         return &link->link_status;
2080 }
2081
2082 void core_link_resume(struct dc_link *link)
2083 {
2084         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2085                 program_hpd_filter(link);
2086 }
2087
2088 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2089 {
2090         struct dc_link_settings *link_settings =
2091                         &stream->sink->link->cur_link_settings;
2092         uint32_t link_rate_in_mbps =
2093                         link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
2094         struct fixed31_32 mbps = dc_fixpt_from_int(
2095                         link_rate_in_mbps * link_settings->lane_count);
2096
2097         return dc_fixpt_div_int(mbps, 54);
2098 }
2099
2100 static int get_color_depth(enum dc_color_depth color_depth)
2101 {
2102         switch (color_depth) {
2103         case COLOR_DEPTH_666: return 6;
2104         case COLOR_DEPTH_888: return 8;
2105         case COLOR_DEPTH_101010: return 10;
2106         case COLOR_DEPTH_121212: return 12;
2107         case COLOR_DEPTH_141414: return 14;
2108         case COLOR_DEPTH_161616: return 16;
2109         default: return 0;
2110         }
2111 }
2112
2113 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2114 {
2115         uint32_t bpc;
2116         uint64_t kbps;
2117         struct fixed31_32 peak_kbps;
2118         uint32_t numerator;
2119         uint32_t denominator;
2120
2121         bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2122         kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
2123
2124         /*
2125          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2126          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2127          * common multiplier to render an integer PBN for all link rate/lane
2128          * counts combinations
2129          * calculate
2130          * peak_kbps *= (1006/1000)
2131          * peak_kbps *= (64/54)
2132          * peak_kbps *= 8    convert to bytes
2133          */
2134
2135         numerator = 64 * PEAK_FACTOR_X1000;
2136         denominator = 54 * 8 * 1000 * 1000;
2137         kbps *= numerator;
2138         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2139
2140         return peak_kbps;
2141 }
2142
2143 static void update_mst_stream_alloc_table(
2144         struct dc_link *link,
2145         struct stream_encoder *stream_enc,
2146         const struct dp_mst_stream_allocation_table *proposed_table)
2147 {
2148         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2149                         { 0 } };
2150         struct link_mst_stream_allocation *dc_alloc;
2151
2152         int i;
2153         int j;
2154
2155         /* if DRM proposed_table has more than one new payload */
2156         ASSERT(proposed_table->stream_count -
2157                         link->mst_stream_alloc_table.stream_count < 2);
2158
2159         /* copy proposed_table to link, add stream encoder */
2160         for (i = 0; i < proposed_table->stream_count; i++) {
2161
2162                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2163                         dc_alloc =
2164                         &link->mst_stream_alloc_table.stream_allocations[j];
2165
2166                         if (dc_alloc->vcp_id ==
2167                                 proposed_table->stream_allocations[i].vcp_id) {
2168
2169                                 work_table[i] = *dc_alloc;
2170                                 break; /* exit j loop */
2171                         }
2172                 }
2173
2174                 /* new vcp_id */
2175                 if (j == link->mst_stream_alloc_table.stream_count) {
2176                         work_table[i].vcp_id =
2177                                 proposed_table->stream_allocations[i].vcp_id;
2178                         work_table[i].slot_count =
2179                                 proposed_table->stream_allocations[i].slot_count;
2180                         work_table[i].stream_enc = stream_enc;
2181                 }
2182         }
2183
2184         /* update link->mst_stream_alloc_table with work_table */
2185         link->mst_stream_alloc_table.stream_count =
2186                         proposed_table->stream_count;
2187         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2188                 link->mst_stream_alloc_table.stream_allocations[i] =
2189                                 work_table[i];
2190 }
2191
2192 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2193  * because stream_encoder is not exposed to dm
2194  */
2195 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2196 {
2197         struct dc_stream_state *stream = pipe_ctx->stream;
2198         struct dc_link *link = stream->sink->link;
2199         struct link_encoder *link_encoder = link->link_enc;
2200         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2201         struct dp_mst_stream_allocation_table proposed_table = {0};
2202         struct fixed31_32 avg_time_slots_per_mtp;
2203         struct fixed31_32 pbn;
2204         struct fixed31_32 pbn_per_slot;
2205         uint8_t i;
2206         DC_LOGGER_INIT(link->ctx->logger);
2207
2208         /* enable_link_dp_mst already check link->enabled_stream_count
2209          * and stream is in link->stream[]. This is called during set mode,
2210          * stream_enc is available.
2211          */
2212
2213         /* get calculate VC payload for stream: stream_alloc */
2214         if (dm_helpers_dp_mst_write_payload_allocation_table(
2215                 stream->ctx,
2216                 stream,
2217                 &proposed_table,
2218                 true)) {
2219                 update_mst_stream_alloc_table(
2220                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2221         }
2222         else
2223                 DC_LOG_WARNING("Failed to update"
2224                                 "MST allocation table for"
2225                                 "pipe idx:%d\n",
2226                                 pipe_ctx->pipe_idx);
2227
2228         DC_LOG_MST("%s  "
2229                         "stream_count: %d: \n ",
2230                         __func__,
2231                         link->mst_stream_alloc_table.stream_count);
2232
2233         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2234                 DC_LOG_MST("stream_enc[%d]: %p      "
2235                 "stream[%d].vcp_id: %d      "
2236                 "stream[%d].slot_count: %d\n",
2237                 i,
2238                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2239                 i,
2240                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2241                 i,
2242                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2243         }
2244
2245         ASSERT(proposed_table.stream_count > 0);
2246
2247         /* program DP source TX for payload */
2248         link_encoder->funcs->update_mst_stream_allocation_table(
2249                 link_encoder,
2250                 &link->mst_stream_alloc_table);
2251
2252         /* send down message */
2253         dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2254                         stream->ctx,
2255                         stream);
2256
2257         dm_helpers_dp_mst_send_payload_allocation(
2258                         stream->ctx,
2259                         stream,
2260                         true);
2261
2262         /* slot X.Y for only current stream */
2263         pbn_per_slot = get_pbn_per_slot(stream);
2264         pbn = get_pbn_from_timing(pipe_ctx);
2265         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2266
2267         stream_encoder->funcs->set_mst_bandwidth(
2268                 stream_encoder,
2269                 avg_time_slots_per_mtp);
2270
2271         return DC_OK;
2272
2273 }
2274
2275 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2276 {
2277         struct dc_stream_state *stream = pipe_ctx->stream;
2278         struct dc_link *link = stream->sink->link;
2279         struct link_encoder *link_encoder = link->link_enc;
2280         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2281         struct dp_mst_stream_allocation_table proposed_table = {0};
2282         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2283         uint8_t i;
2284         bool mst_mode = (link->type == dc_connection_mst_branch);
2285         DC_LOGGER_INIT(link->ctx->logger);
2286
2287         /* deallocate_mst_payload is called before disable link. When mode or
2288          * disable/enable monitor, new stream is created which is not in link
2289          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2290          * should not done. For new mode set, map_resources will get engine
2291          * for new stream, so stream_enc->id should be validated until here.
2292          */
2293
2294         /* slot X.Y */
2295         stream_encoder->funcs->set_mst_bandwidth(
2296                 stream_encoder,
2297                 avg_time_slots_per_mtp);
2298
2299         /* TODO: which component is responsible for remove payload table? */
2300         if (mst_mode) {
2301                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2302                                 stream->ctx,
2303                                 stream,
2304                                 &proposed_table,
2305                                 false)) {
2306
2307                         update_mst_stream_alloc_table(
2308                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2309                 }
2310                 else {
2311                                 DC_LOG_WARNING("Failed to update"
2312                                                 "MST allocation table for"
2313                                                 "pipe idx:%d\n",
2314                                                 pipe_ctx->pipe_idx);
2315                 }
2316         }
2317
2318         DC_LOG_MST("%s"
2319                         "stream_count: %d: ",
2320                         __func__,
2321                         link->mst_stream_alloc_table.stream_count);
2322
2323         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2324                 DC_LOG_MST("stream_enc[%d]: %p      "
2325                 "stream[%d].vcp_id: %d      "
2326                 "stream[%d].slot_count: %d\n",
2327                 i,
2328                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2329                 i,
2330                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2331                 i,
2332                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2333         }
2334
2335         link_encoder->funcs->update_mst_stream_allocation_table(
2336                 link_encoder,
2337                 &link->mst_stream_alloc_table);
2338
2339         if (mst_mode) {
2340                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2341                         stream->ctx,
2342                         stream);
2343
2344                 dm_helpers_dp_mst_send_payload_allocation(
2345                         stream->ctx,
2346                         stream,
2347                         false);
2348         }
2349
2350         return DC_OK;
2351 }
2352
2353 void core_link_enable_stream(
2354                 struct dc_state *state,
2355                 struct pipe_ctx *pipe_ctx)
2356 {
2357         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2358         enum dc_status status;
2359         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2360
2361         /* eDP lit up by bios already, no need to enable again. */
2362         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2363                 core_dc->apply_edp_fast_boot_optimization) {
2364                 core_dc->apply_edp_fast_boot_optimization = false;
2365                 pipe_ctx->stream->dpms_off = false;
2366                 return;
2367         }
2368
2369         if (pipe_ctx->stream->dpms_off)
2370                 return;
2371
2372         status = enable_link(state, pipe_ctx);
2373
2374         if (status != DC_OK) {
2375                         DC_LOG_WARNING("enabling link %u failed: %d\n",
2376                         pipe_ctx->stream->sink->link->link_index,
2377                         status);
2378
2379                         /* Abort stream enable *unless* the failure was due to
2380                          * DP link training - some DP monitors will recover and
2381                          * show the stream anyway. But MST displays can't proceed
2382                          * without link training.
2383                          */
2384                         if (status != DC_FAIL_DP_LINK_TRAINING ||
2385                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2386                                 BREAK_TO_DEBUGGER();
2387                                 return;
2388                         }
2389         }
2390
2391         core_dc->hwss.enable_audio_stream(pipe_ctx);
2392
2393         /* turn off otg test pattern if enable */
2394         if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2395                 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2396                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2397                                 COLOR_DEPTH_UNDEFINED);
2398
2399         core_dc->hwss.enable_stream(pipe_ctx);
2400
2401         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2402                 allocate_mst_payload(pipe_ctx);
2403
2404         core_dc->hwss.unblank_stream(pipe_ctx,
2405                 &pipe_ctx->stream->sink->link->cur_link_settings);
2406 }
2407
2408 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
2409 {
2410         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2411
2412         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2413                 deallocate_mst_payload(pipe_ctx);
2414
2415         core_dc->hwss.blank_stream(pipe_ctx);
2416
2417         core_dc->hwss.disable_stream(pipe_ctx, option);
2418
2419         disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
2420 }
2421
2422 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2423 {
2424         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2425
2426         if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2427                 return;
2428
2429         core_dc->hwss.set_avmute(pipe_ctx, enable);
2430 }
2431
2432 /**
2433  *****************************************************************************
2434  *  Function: dc_link_enable_hpd_filter
2435  *
2436  *  @brief
2437  *     If enable is true, programs HPD filter on associated HPD line using
2438  *     delay_on_disconnect/delay_on_connect values dependent on
2439  *     link->connector_signal
2440  *
2441  *     If enable is false, programs HPD filter on associated HPD line with no
2442  *     delays on connect or disconnect
2443  *
2444  *  @param [in] link: pointer to the dc link
2445  *  @param [in] enable: boolean specifying whether to enable hbd
2446  *****************************************************************************
2447  */
2448 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
2449 {
2450         struct gpio *hpd;
2451
2452         if (enable) {
2453                 link->is_hpd_filter_disabled = false;
2454                 program_hpd_filter(link);
2455         } else {
2456                 link->is_hpd_filter_disabled = true;
2457                 /* Obtain HPD handle */
2458                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
2459
2460                 if (!hpd)
2461                         return;
2462
2463                 /* Setup HPD filtering */
2464                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
2465                         struct gpio_hpd_config config;
2466
2467                         config.delay_on_connect = 0;
2468                         config.delay_on_disconnect = 0;
2469
2470                         dal_irq_setup_hpd_filter(hpd, &config);
2471
2472                         dal_gpio_close(hpd);
2473                 } else {
2474                         ASSERT_CRITICAL(false);
2475                 }
2476                 /* Release HPD handle */
2477                 dal_gpio_destroy_irq(&hpd);
2478         }
2479 }
2480