drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "atom.h"
  28 #include "dm_helpers.h"
  29 #include "dc.h"
  30 #include "grph_object_id.h"
  31 #include "gpio_service_interface.h"
  32 #include "core_status.h"
  33 #include "dc_link_dp.h"
  34 #include "dc_link_ddc.h"
  35 #include "link_hwss.h"
  36 #include "opp.h"
  37
  38 #include "link_encoder.h"
  39 #include "hw_sequencer.h"
  40 #include "resource.h"
  41 #include "abm.h"
  42 #include "fixed31_32.h"
  43 #include "dpcd_defs.h"
  44 #include "dmcu.h"
  45
  46 #include "dce/dce_11_0_d.h"
  47 #include "dce/dce_11_0_enum.h"
  48 #include "dce/dce_11_0_sh_mask.h"
  49
  50 #define DC_LOGGER_INIT(logger)
  51
  52
  53 #define LINK_INFO(...) \
  54         DC_LOG_HW_HOTPLUG(  \
  55                 __VA_ARGS__)
  56
  57 /*******************************************************************************
  58  * Private structures
  59  ******************************************************************************/
  60
  61 enum {
  62         LINK_RATE_REF_FREQ_IN_MHZ = 27,
  63         PEAK_FACTOR_X1000 = 1006
  64 };
  65
  66 /*******************************************************************************
  67  * Private functions
  68  ******************************************************************************/
  69 static void destruct(struct dc_link *link)
  70 {
  71         int i;
  72
  73         if (link->ddc)
  74                 dal_ddc_service_destroy(&link->ddc);
  75
  76         if(link->link_enc)
  77                 link->link_enc->funcs->destroy(&link->link_enc);
  78
  79         if (link->local_sink)
  80                 dc_sink_release(link->local_sink);
  81
  82         for (i = 0; i < link->sink_count; ++i)
  83                 dc_sink_release(link->remote_sinks[i]);
  84 }
  85
  86 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
  87                 struct graphics_object_id link_id,
  88                 struct gpio_service *gpio_service)
  89 {
  90         enum bp_result bp_result;
  91         struct graphics_object_hpd_info hpd_info;
  92         struct gpio_pin_info pin_info;
  93
  94         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
  95                 return NULL;
  96
  97         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
  98                 hpd_info.hpd_int_gpio_uid, &pin_info);
  99
 100         if (bp_result != BP_RESULT_OK) {
 101                 ASSERT(bp_result == BP_RESULT_NORECORD);
 102                 return NULL;
 103         }
 104
 105         return dal_gpio_service_create_irq(
 106                 gpio_service,
 107                 pin_info.offset,
 108                 pin_info.mask);
 109 }
 110
 111 /*
 112  *  Function: program_hpd_filter
 113  *
 114  *  @brief
 115  *     Programs HPD filter on associated HPD line
 116  *
 117  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 118  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 119  *
 120  *  @return
 121  *     true on success, false otherwise
 122  */
 123 static bool program_hpd_filter(
 124         const struct dc_link *link)
 125 {
 126         bool result = false;
 127
 128         struct gpio *hpd;
 129
 130         int delay_on_connect_in_ms = 0;
 131         int delay_on_disconnect_in_ms = 0;
 132
 133         if (link->is_hpd_filter_disabled)
 134                 return false;
 135         /* Verify feature is supported */
 136         switch (link->connector_signal) {
 137         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 138         case SIGNAL_TYPE_DVI_DUAL_LINK:
 139         case SIGNAL_TYPE_HDMI_TYPE_A:
 140                 /* Program hpd filter */
 141                 delay_on_connect_in_ms = 500;
 142                 delay_on_disconnect_in_ms = 100;
 143                 break;
 144         case SIGNAL_TYPE_DISPLAY_PORT:
 145         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 146                 /* Program hpd filter to allow DP signal to settle */
 147                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 148                  *      only 100ms on DELL U2413
 149                  * 0:   some passive dongle still show aux mode instead of i2c
 150                  * 20-50:not enough to hide bouncing HPD with passive dongle.
 151                  *      also see intermittent i2c read issues.
 152                  */
 153                 delay_on_connect_in_ms = 80;
 154                 delay_on_disconnect_in_ms = 0;
 155                 break;
 156         case SIGNAL_TYPE_LVDS:
 157         case SIGNAL_TYPE_EDP:
 158         default:
 159                 /* Don't program hpd filter */
 160                 return false;
 161         }
 162
 163         /* Obtain HPD handle */
 164         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 165
 166         if (!hpd)
 167                 return result;
 168
 169         /* Setup HPD filtering */
 170         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 171                 struct gpio_hpd_config config;
 172
 173                 config.delay_on_connect = delay_on_connect_in_ms;
 174                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 175
 176                 dal_irq_setup_hpd_filter(hpd, &config);
 177
 178                 dal_gpio_close(hpd);
 179
 180                 result = true;
 181         } else {
 182                 ASSERT_CRITICAL(false);
 183         }
 184
 185         /* Release HPD handle */
 186         dal_gpio_destroy_irq(&hpd);
 187
 188         return result;
 189 }
 190
 191 static bool detect_sink(struct dc_link *link, enum dc_connection_type *type)
 192 {
 193         uint32_t is_hpd_high = 0;
 194         struct gpio *hpd_pin;
 195
 196         /* todo: may need to lock gpio access */
 197         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 198         if (hpd_pin == NULL)
 199                 goto hpd_gpio_failure;
 200
 201         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 202         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 203         dal_gpio_close(hpd_pin);
 204         dal_gpio_destroy_irq(&hpd_pin);
 205
 206         if (is_hpd_high) {
 207                 *type = dc_connection_single;
 208                 /* TODO: need to do the actual detection */
 209         } else {
 210                 *type = dc_connection_none;
 211         }
 212
 213         return true;
 214
 215 hpd_gpio_failure:
 216         return false;
 217 }
 218
 219 static enum ddc_transaction_type get_ddc_transaction_type(
 220                 enum signal_type sink_signal)
 221 {
 222         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 223
 224         switch (sink_signal) {
 225         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 226         case SIGNAL_TYPE_DVI_DUAL_LINK:
 227         case SIGNAL_TYPE_HDMI_TYPE_A:
 228         case SIGNAL_TYPE_LVDS:
 229         case SIGNAL_TYPE_RGB:
 230                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 231                 break;
 232
 233         case SIGNAL_TYPE_DISPLAY_PORT:
 234         case SIGNAL_TYPE_EDP:
 235                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 236                 break;
 237
 238         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 239                 /* MST does not use I2COverAux, but there is the
 240                  * SPECIAL use case for "immediate dwnstrm device
 241                  * access" (EPR#370830). */
 242                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 243                 break;
 244
 245         default:
 246                 break;
 247         }
 248
 249         return transaction_type;
 250 }
 251
 252 static enum signal_type get_basic_signal_type(
 253         struct graphics_object_id encoder,
 254         struct graphics_object_id downstream)
 255 {
 256         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 257                 switch (downstream.id) {
 258                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 259                         switch (encoder.id) {
 260                         case ENCODER_ID_INTERNAL_DAC1:
 261                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 262                         case ENCODER_ID_INTERNAL_DAC2:
 263                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 264                                 return SIGNAL_TYPE_RGB;
 265                         default:
 266                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 267                         }
 268                 break;
 269                 case CONNECTOR_ID_DUAL_LINK_DVII:
 270                 {
 271                         switch (encoder.id) {
 272                         case ENCODER_ID_INTERNAL_DAC1:
 273                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 274                         case ENCODER_ID_INTERNAL_DAC2:
 275                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 276                                 return SIGNAL_TYPE_RGB;
 277                         default:
 278                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 279                         }
 280                 }
 281                 break;
 282                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 283                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 284                 case CONNECTOR_ID_DUAL_LINK_DVID:
 285                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 286                 case CONNECTOR_ID_VGA:
 287                         return SIGNAL_TYPE_RGB;
 288                 case CONNECTOR_ID_HDMI_TYPE_A:
 289                         return SIGNAL_TYPE_HDMI_TYPE_A;
 290                 case CONNECTOR_ID_LVDS:
 291                         return SIGNAL_TYPE_LVDS;
 292                 case CONNECTOR_ID_DISPLAY_PORT:
 293                         return SIGNAL_TYPE_DISPLAY_PORT;
 294                 case CONNECTOR_ID_EDP:
 295                         return SIGNAL_TYPE_EDP;
 296                 default:
 297                         return SIGNAL_TYPE_NONE;
 298                 }
 299         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 300                 switch (downstream.id) {
 301                 case ENCODER_ID_EXTERNAL_NUTMEG:
 302                 case ENCODER_ID_EXTERNAL_TRAVIS:
 303                         return SIGNAL_TYPE_DISPLAY_PORT;
 304                 default:
 305                         return SIGNAL_TYPE_NONE;
 306                 }
 307         }
 308
 309         return SIGNAL_TYPE_NONE;
 310 }
 311
 312 /*
 313  * @brief
 314  * Check whether there is a dongle on DP connector
 315  */
 316 static bool is_dp_sink_present(struct dc_link *link)
 317 {
 318         enum gpio_result gpio_result;
 319         uint32_t clock_pin = 0;
 320
 321         struct ddc *ddc;
 322
 323         enum connector_id connector_id =
 324                 dal_graphics_object_id_get_connector_id(link->link_id);
 325
 326         bool present =
 327                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 328                 (connector_id == CONNECTOR_ID_EDP));
 329
 330         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 331
 332         if (!ddc) {
 333                 BREAK_TO_DEBUGGER();
 334                 return present;
 335         }
 336
 337         /* Open GPIO and set it to I2C mode */
 338         /* Note: this GpioMode_Input will be converted
 339          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 340          * which indicates we need additional delay */
 341
 342         if (GPIO_RESULT_OK != dal_ddc_open(
 343                 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
 344                 dal_gpio_destroy_ddc(&ddc);
 345
 346                 return present;
 347         }
 348
 349         /* Read GPIO: DP sink is present if both clock and data pins are zero */
 350         /* [anaumov] in DAL2, there was no check for GPIO failure */
 351
 352         gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 353         ASSERT(gpio_result == GPIO_RESULT_OK);
 354
 355         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 356
 357         dal_ddc_close(ddc);
 358
 359         return present;
 360 }
 361
 362 /*
 363  * @brief
 364  * Detect output sink type
 365  */
 366 static enum signal_type link_detect_sink(
 367         struct dc_link *link,
 368         enum dc_detect_reason reason)
 369 {
 370         enum signal_type result = get_basic_signal_type(
 371                 link->link_enc->id, link->link_id);
 372
 373         /* Internal digital encoder will detect only dongles
 374          * that require digital signal */
 375
 376         /* Detection mechanism is different
 377          * for different native connectors.
 378          * LVDS connector supports only LVDS signal;
 379          * PCIE is a bus slot, the actual connector needs to be detected first;
 380          * eDP connector supports only eDP signal;
 381          * HDMI should check straps for audio */
 382
 383         /* PCIE detects the actual connector on add-on board */
 384
 385         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 386                 /* ZAZTODO implement PCIE add-on card detection */
 387         }
 388
 389         switch (link->link_id.id) {
 390         case CONNECTOR_ID_HDMI_TYPE_A: {
 391                 /* check audio support:
 392                  * if native HDMI is not supported, switch to DVI */
 393                 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 394
 395                 if (!aud_support->hdmi_audio_native)
 396                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 397                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 398         }
 399         break;
 400         case CONNECTOR_ID_DISPLAY_PORT: {
 401                 /* DP HPD short pulse. Passive DP dongle will not
 402                  * have short pulse
 403                  */
 404                 if (reason != DETECT_REASON_HPDRX) {
 405                         /* Check whether DP signal detected: if not -
 406                          * we assume signal is DVI; it could be corrected
 407                          * to HDMI after dongle detection
 408                          */
 409                         if (!is_dp_sink_present(link))
 410                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 411                 }
 412         }
 413         break;
 414         default:
 415         break;
 416         }
 417
 418         return result;
 419 }
 420
 421 static enum signal_type decide_signal_from_strap_and_dongle_type(
 422                 enum display_dongle_type dongle_type,
 423                 struct audio_support *audio_support)
 424 {
 425         enum signal_type signal = SIGNAL_TYPE_NONE;
 426
 427         switch (dongle_type) {
 428         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 429                 if (audio_support->hdmi_audio_on_dongle)
 430                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 431                 else
 432                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 433                 break;
 434         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 435                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 436                 break;
 437         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 438                 if (audio_support->hdmi_audio_native)
 439                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 440                 else
 441                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 442                 break;
 443         default:
 444                 signal = SIGNAL_TYPE_NONE;
 445                 break;
 446         }
 447
 448         return signal;
 449 }
 450
 451 static enum signal_type dp_passive_dongle_detection(
 452                 struct ddc_service *ddc,
 453                 struct display_sink_capability *sink_cap,
 454                 struct audio_support *audio_support)
 455 {
 456         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 457                                                 ddc, sink_cap);
 458         return decide_signal_from_strap_and_dongle_type(
 459                         sink_cap->dongle_type,
 460                         audio_support);
 461 }
 462
 463 static void link_disconnect_sink(struct dc_link *link)
 464 {
 465         if (link->local_sink) {
 466                 dc_sink_release(link->local_sink);
 467                 link->local_sink = NULL;
 468         }
 469
 470         link->dpcd_sink_count = 0;
 471 }
 472
 473 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 474 {
 475         dc_sink_release(link->local_sink);
 476         link->local_sink = prev_sink;
 477 }
 478
 479
 480 static bool detect_dp(
 481         struct dc_link *link,
 482         struct display_sink_capability *sink_caps,
 483         bool *converter_disable_audio,
 484         struct audio_support *audio_support,
 485         enum dc_detect_reason reason)
 486 {
 487         bool boot = false;
 488         sink_caps->signal = link_detect_sink(link, reason);
 489         sink_caps->transaction_type =
 490                 get_ddc_transaction_type(sink_caps->signal);
 491
 492         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 493                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 494                 if (!detect_dp_sink_caps(link))
 495                         return false;
 496
 497                 if (is_mst_supported(link)) {
 498                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 499                         link->type = dc_connection_mst_branch;
 500
 501                         dal_ddc_service_set_transaction_type(
 502                                                         link->ddc,
 503                                                         sink_caps->transaction_type);
 504
 505                         /*
 506                          * This call will initiate MST topology discovery. Which
 507                          * will detect MST ports and add new DRM connector DRM
 508                          * framework. Then read EDID via remote i2c over aux. In
 509                          * the end, will notify DRM detect result and save EDID
 510                          * into DRM framework.
 511                          *
 512                          * .detect is called by .fill_modes.
 513                          * .fill_modes is called by user mode ioctl
 514                          * DRM_IOCTL_MODE_GETCONNECTOR.
 515                          *
 516                          * .get_modes is called by .fill_modes.
 517                          *
 518                          * call .get_modes, AMDGPU DM implementation will create
 519                          * new dc_sink and add to dc_link. For long HPD plug
 520                          * in/out, MST has its own handle.
 521                          *
 522                          * Therefore, just after dc_create, link->sink is not
 523                          * created for MST until user mode app calls
 524                          * DRM_IOCTL_MODE_GETCONNECTOR.
 525                          *
 526                          * Need check ->sink usages in case ->sink = NULL
 527                          * TODO: s3 resume check
 528                          */
 529                         if (reason == DETECT_REASON_BOOT)
 530                                 boot = true;
 531
 532                         if (!dm_helpers_dp_mst_start_top_mgr(
 533                                 link->ctx,
 534                                 link, boot)) {
 535                                 /* MST not supported */
 536                                 link->type = dc_connection_single;
 537                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 538                         }
 539                 }
 540
 541                 if (link->type != dc_connection_mst_branch &&
 542                         is_dp_active_dongle(link)) {
 543                         /* DP active dongles */
 544                         link->type = dc_connection_active_dongle;
 545                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 546                                 /*
 547                                  * active dongle unplug processing for short irq
 548                                  */
 549                                 link_disconnect_sink(link);
 550                                 return true;
 551                         }
 552
 553                         if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 554                                 *converter_disable_audio = true;
 555                 }
 556         } else {
 557                 /* DP passive dongles */
 558                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 559                                 sink_caps,
 560                                 audio_support);
 561         }
 562
 563         return true;
 564 }
 565
 566 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 567 {
 568         if (old_edid->length != new_edid->length)
 569                 return false;
 570
 571         if (new_edid->length == 0)
 572                 return false;
 573
 574         return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
 575 }
 576
 577 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 578 {
 579         struct dc_sink_init_data sink_init_data = { 0 };
 580         struct display_sink_capability sink_caps = { 0 };
 581         uint8_t i;
 582         bool converter_disable_audio = false;
 583         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 584         bool same_edid = false;
 585         enum dc_edid_status edid_status;
 586         struct dc_context *dc_ctx = link->ctx;
 587         struct dc_sink *sink = NULL;
 588         struct dc_sink *prev_sink = NULL;
 589         struct dpcd_caps prev_dpcd_caps;
 590         bool same_dpcd = true;
 591         enum dc_connection_type new_connection_type = dc_connection_none;
 592         DC_LOGGER_INIT(link->ctx->logger);
 593         if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
 594                 return false;
 595
 596         if (false == detect_sink(link, &new_connection_type)) {
 597                 BREAK_TO_DEBUGGER();
 598                 return false;
 599         }
 600
 601         if (link->connector_signal == SIGNAL_TYPE_EDP &&
 602                         link->local_sink)
 603                 return true;
 604
 605         prev_sink = link->local_sink;
 606         if (prev_sink != NULL) {
 607                 dc_sink_retain(prev_sink);
 608                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 609         }
 610         link_disconnect_sink(link);
 611
 612         if (new_connection_type != dc_connection_none) {
 613                 link->type = new_connection_type;
 614
 615                 /* From Disconnected-to-Connected. */
 616                 switch (link->connector_signal) {
 617                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 618                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 619                         if (aud_support->hdmi_audio_native)
 620                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 621                         else
 622                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 623                         break;
 624                 }
 625
 626                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 627                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 628                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 629                         break;
 630                 }
 631
 632                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 633                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 634                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 635                         break;
 636                 }
 637
 638                 case SIGNAL_TYPE_EDP: {
 639                         detect_edp_sink_caps(link);
 640                         sink_caps.transaction_type =
 641                                 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 642                         sink_caps.signal = SIGNAL_TYPE_EDP;
 643                         break;
 644                 }
 645
 646                 case SIGNAL_TYPE_DISPLAY_PORT: {
 647                         if (!detect_dp(
 648                                 link,
 649                                 &sink_caps,
 650                                 &converter_disable_audio,
 651                                 aud_support, reason)) {
 652                                 if (prev_sink != NULL)
 653                                         dc_sink_release(prev_sink);
 654                                 return false;
 655                         }
 656
 657                         // Check if dpcp block is the same
 658                         if (prev_sink != NULL) {
 659                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
 660                                         same_dpcd = false;
 661                         }
 662                         /* Active dongle downstream unplug */
 663                         if (link->type == dc_connection_active_dongle
 664                                         && link->dpcd_caps.sink_count.
 665                                         bits.SINK_COUNT == 0) {
 666                                 if (prev_sink != NULL)
 667                                         dc_sink_release(prev_sink);
 668                                 return true;
 669                         }
 670
 671                         if (link->type == dc_connection_mst_branch) {
 672                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 673                                         link->link_index);
 674                                 /* Need to setup mst link_cap struct here
 675                                  * otherwise dc_link_detect() will leave mst link_cap
 676                                  * empty which leads to allocate_mst_payload() has "0"
 677                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 678                                  */
 679                                 link->verified_link_cap = link->reported_link_cap;
 680                                 if (prev_sink != NULL)
 681                                         dc_sink_release(prev_sink);
 682                                 return false;
 683                         }
 684
 685                         break;
 686                 }
 687
 688                 default:
 689                         DC_ERROR("Invalid connector type! signal:%d\n",
 690                                 link->connector_signal);
 691                         if (prev_sink != NULL)
 692                                 dc_sink_release(prev_sink);
 693                         return false;
 694                 } /* switch() */
 695
 696                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
 697                         link->dpcd_sink_count = link->dpcd_caps.sink_count.
 698                                         bits.SINK_COUNT;
 699                 else
 700                         link->dpcd_sink_count = 1;
 701
 702                 dal_ddc_service_set_transaction_type(
 703                                                 link->ddc,
 704                                                 sink_caps.transaction_type);
 705
 706                 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
 707                                 link->ddc);
 708
 709                 sink_init_data.link = link;
 710                 sink_init_data.sink_signal = sink_caps.signal;
 711
 712                 sink = dc_sink_create(&sink_init_data);
 713                 if (!sink) {
 714                         DC_ERROR("Failed to create sink!\n");
 715                         if (prev_sink != NULL)
 716                                 dc_sink_release(prev_sink);
 717                         return false;
 718                 }
 719
 720                 sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
 721                 sink->converter_disable_audio = converter_disable_audio;
 722
 723                 link->local_sink = sink;
 724
 725                 edid_status = dm_helpers_read_local_edid(
 726                                 link->ctx,
 727                                 link,
 728                                 sink);
 729
 730                 switch (edid_status) {
 731                 case EDID_BAD_CHECKSUM:
 732                         DC_LOG_ERROR("EDID checksum invalid.\n");
 733                         break;
 734                 case EDID_NO_RESPONSE:
 735                         DC_LOG_ERROR("No EDID read.\n");
 736                 default:
 737                         break;
 738                 }
 739
 740                 // Check if edid is the same
 741                 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
 742                         same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
 743
 744                 // If both edid and dpcd are the same, then discard new sink and revert back to original sink
 745                 if ((same_edid) && (same_dpcd)) {
 746                         link_disconnect_remap(prev_sink, link);
 747                         sink = prev_sink;
 748                         prev_sink = NULL;
 749                 } else {
 750                         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 751                                         sink_caps.transaction_type ==
 752                                                 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 753                                 /*
 754                                  * TODO debug why Dell 2413 doesn't like
 755                                  *  two link trainings
 756                                  */
 757
 758                                 /* deal with non-mst cases */
 759                                 dp_hbr_verify_link_cap(link, &link->reported_link_cap);
 760                         }
 761
 762                         /* HDMI-DVI Dongle */
 763                         if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
 764                                         !sink->edid_caps.edid_hdmi)
 765                                 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 766                 }
 767
 768                 /* Connectivity log: detection */
 769                 for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
 770                         CONN_DATA_DETECT(link,
 771                                         &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
 772                                         EDID_BLOCK_SIZE,
 773                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
 774                 }
 775
 776                 DC_LOG_DETECTION_EDID_PARSER("%s: "
 777                         "manufacturer_id = %X, "
 778                         "product_id = %X, "
 779                         "serial_number = %X, "
 780                         "manufacture_week = %d, "
 781                         "manufacture_year = %d, "
 782                         "display_name = %s, "
 783                         "speaker_flag = %d, "
 784                         "audio_mode_count = %d\n",
 785                         __func__,
 786                         sink->edid_caps.manufacturer_id,
 787                         sink->edid_caps.product_id,
 788                         sink->edid_caps.serial_number,
 789                         sink->edid_caps.manufacture_week,
 790                         sink->edid_caps.manufacture_year,
 791                         sink->edid_caps.display_name,
 792                         sink->edid_caps.speaker_flags,
 793                         sink->edid_caps.audio_mode_count);
 794
 795                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
 796                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
 797                                 "format_code = %d, "
 798                                 "channel_count = %d, "
 799                                 "sample_rate = %d, "
 800                                 "sample_size = %d\n",
 801                                 __func__,
 802                                 i,
 803                                 sink->edid_caps.audio_modes[i].format_code,
 804                                 sink->edid_caps.audio_modes[i].channel_count,
 805                                 sink->edid_caps.audio_modes[i].sample_rate,
 806                                 sink->edid_caps.audio_modes[i].sample_size);
 807                 }
 808
 809         } else {
 810                 /* From Connected-to-Disconnected. */
 811                 if (link->type == dc_connection_mst_branch) {
 812                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 813                                 link->link_index);
 814
 815                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 816
 817                         link->mst_stream_alloc_table.stream_count = 0;
 818                         memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
 819                 }
 820
 821                 link->type = dc_connection_none;
 822                 sink_caps.signal = SIGNAL_TYPE_NONE;
 823         }
 824
 825         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
 826                 link->link_index, sink,
 827                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
 828                         "Disconnected":"Connected"), prev_sink,
 829                         same_dpcd, same_edid);
 830
 831         if (prev_sink != NULL)
 832                 dc_sink_release(prev_sink);
 833
 834         return true;
 835 }
 836
 837 static enum hpd_source_id get_hpd_line(
 838                 struct dc_link *link)
 839 {
 840         struct gpio *hpd;
 841         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
 842
 843         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 844
 845         if (hpd) {
 846                 switch (dal_irq_get_source(hpd)) {
 847                 case DC_IRQ_SOURCE_HPD1:
 848                         hpd_id = HPD_SOURCEID1;
 849                 break;
 850                 case DC_IRQ_SOURCE_HPD2:
 851                         hpd_id = HPD_SOURCEID2;
 852                 break;
 853                 case DC_IRQ_SOURCE_HPD3:
 854                         hpd_id = HPD_SOURCEID3;
 855                 break;
 856                 case DC_IRQ_SOURCE_HPD4:
 857                         hpd_id = HPD_SOURCEID4;
 858                 break;
 859                 case DC_IRQ_SOURCE_HPD5:
 860                         hpd_id = HPD_SOURCEID5;
 861                 break;
 862                 case DC_IRQ_SOURCE_HPD6:
 863                         hpd_id = HPD_SOURCEID6;
 864                 break;
 865                 default:
 866                         BREAK_TO_DEBUGGER();
 867                 break;
 868                 }
 869
 870                 dal_gpio_destroy_irq(&hpd);
 871         }
 872
 873         return hpd_id;
 874 }
 875
 876 static enum channel_id get_ddc_line(struct dc_link *link)
 877 {
 878         struct ddc *ddc;
 879         enum channel_id channel = CHANNEL_ID_UNKNOWN;
 880
 881         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 882
 883         if (ddc) {
 884                 switch (dal_ddc_get_line(ddc)) {
 885                 case GPIO_DDC_LINE_DDC1:
 886                         channel = CHANNEL_ID_DDC1;
 887                         break;
 888                 case GPIO_DDC_LINE_DDC2:
 889                         channel = CHANNEL_ID_DDC2;
 890                         break;
 891                 case GPIO_DDC_LINE_DDC3:
 892                         channel = CHANNEL_ID_DDC3;
 893                         break;
 894                 case GPIO_DDC_LINE_DDC4:
 895                         channel = CHANNEL_ID_DDC4;
 896                         break;
 897                 case GPIO_DDC_LINE_DDC5:
 898                         channel = CHANNEL_ID_DDC5;
 899                         break;
 900                 case GPIO_DDC_LINE_DDC6:
 901                         channel = CHANNEL_ID_DDC6;
 902                         break;
 903                 case GPIO_DDC_LINE_DDC_VGA:
 904                         channel = CHANNEL_ID_DDC_VGA;
 905                         break;
 906                 case GPIO_DDC_LINE_I2C_PAD:
 907                         channel = CHANNEL_ID_I2C_PAD;
 908                         break;
 909                 default:
 910                         BREAK_TO_DEBUGGER();
 911                         break;
 912                 }
 913         }
 914
 915         return channel;
 916 }
 917
 918 static enum transmitter translate_encoder_to_transmitter(
 919         struct graphics_object_id encoder)
 920 {
 921         switch (encoder.id) {
 922         case ENCODER_ID_INTERNAL_UNIPHY:
 923                 switch (encoder.enum_id) {
 924                 case ENUM_ID_1:
 925                         return TRANSMITTER_UNIPHY_A;
 926                 case ENUM_ID_2:
 927                         return TRANSMITTER_UNIPHY_B;
 928                 default:
 929                         return TRANSMITTER_UNKNOWN;
 930                 }
 931         break;
 932         case ENCODER_ID_INTERNAL_UNIPHY1:
 933                 switch (encoder.enum_id) {
 934                 case ENUM_ID_1:
 935                         return TRANSMITTER_UNIPHY_C;
 936                 case ENUM_ID_2:
 937                         return TRANSMITTER_UNIPHY_D;
 938                 default:
 939                         return TRANSMITTER_UNKNOWN;
 940                 }
 941         break;
 942         case ENCODER_ID_INTERNAL_UNIPHY2:
 943                 switch (encoder.enum_id) {
 944                 case ENUM_ID_1:
 945                         return TRANSMITTER_UNIPHY_E;
 946                 case ENUM_ID_2:
 947                         return TRANSMITTER_UNIPHY_F;
 948                 default:
 949                         return TRANSMITTER_UNKNOWN;
 950                 }
 951         break;
 952         case ENCODER_ID_INTERNAL_UNIPHY3:
 953                 switch (encoder.enum_id) {
 954                 case ENUM_ID_1:
 955                         return TRANSMITTER_UNIPHY_G;
 956                 default:
 957                         return TRANSMITTER_UNKNOWN;
 958                 }
 959         break;
 960         case ENCODER_ID_EXTERNAL_NUTMEG:
 961                 switch (encoder.enum_id) {
 962                 case ENUM_ID_1:
 963                         return TRANSMITTER_NUTMEG_CRT;
 964                 default:
 965                         return TRANSMITTER_UNKNOWN;
 966                 }
 967         break;
 968         case ENCODER_ID_EXTERNAL_TRAVIS:
 969                 switch (encoder.enum_id) {
 970                 case ENUM_ID_1:
 971                         return TRANSMITTER_TRAVIS_CRT;
 972                 case ENUM_ID_2:
 973                         return TRANSMITTER_TRAVIS_LCD;
 974                 default:
 975                         return TRANSMITTER_UNKNOWN;
 976                 }
 977         break;
 978         default:
 979                 return TRANSMITTER_UNKNOWN;
 980         }
 981 }
 982
 983 static bool construct(
 984         struct dc_link *link,
 985         const struct link_init_data *init_params)
 986 {
 987         uint8_t i;
 988         struct gpio *hpd_gpio = NULL;
 989         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
 990         struct dc_context *dc_ctx = init_params->ctx;
 991         struct encoder_init_data enc_init_data = { 0 };
 992         struct integrated_info info = {{{ 0 }}};
 993         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
 994         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
 995         DC_LOGGER_INIT(dc_ctx->logger);
 996
 997         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
 998         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
 999
1000         link->link_status.dpcd_caps = &link->dpcd_caps;
1001
1002         link->dc = init_params->dc;
1003         link->ctx = dc_ctx;
1004         link->link_index = init_params->link_index;
1005
1006         link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1007
1008         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1009                 dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1010                          __func__, init_params->connector_index,
1011                          link->link_id.type, OBJECT_TYPE_CONNECTOR);
1012                 goto create_fail;
1013         }
1014
1015         hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1016
1017         if (hpd_gpio != NULL)
1018                 link->irq_source_hpd = dal_irq_get_source(hpd_gpio);
1019
1020         switch (link->link_id.id) {
1021         case CONNECTOR_ID_HDMI_TYPE_A:
1022                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1023
1024                 break;
1025         case CONNECTOR_ID_SINGLE_LINK_DVID:
1026         case CONNECTOR_ID_SINGLE_LINK_DVII:
1027                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1028                 break;
1029         case CONNECTOR_ID_DUAL_LINK_DVID:
1030         case CONNECTOR_ID_DUAL_LINK_DVII:
1031                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1032                 break;
1033         case CONNECTOR_ID_DISPLAY_PORT:
1034                 link->connector_signal =        SIGNAL_TYPE_DISPLAY_PORT;
1035
1036                 if (hpd_gpio != NULL)
1037                         link->irq_source_hpd_rx =
1038                                         dal_irq_get_rx_source(hpd_gpio);
1039
1040                 break;
1041         case CONNECTOR_ID_EDP:
1042                 link->connector_signal = SIGNAL_TYPE_EDP;
1043
1044                 if (hpd_gpio != NULL) {
1045                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1046                         link->irq_source_hpd_rx =
1047                                         dal_irq_get_rx_source(hpd_gpio);
1048                 }
1049                 break;
1050         default:
1051                 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1052                 goto create_fail;
1053         }
1054
1055         if (hpd_gpio != NULL) {
1056                 dal_gpio_destroy_irq(&hpd_gpio);
1057                 hpd_gpio = NULL;
1058         }
1059
1060         /* TODO: #DAL3 Implement id to str function.*/
1061         LINK_INFO("Connector[%d] description:"
1062                         "signal %d\n",
1063                         init_params->connector_index,
1064                         link->connector_signal);
1065
1066         ddc_service_init_data.ctx = link->ctx;
1067         ddc_service_init_data.id = link->link_id;
1068         ddc_service_init_data.link = link;
1069         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1070
1071         if (link->ddc == NULL) {
1072                 DC_ERROR("Failed to create ddc_service!\n");
1073                 goto ddc_create_fail;
1074         }
1075
1076         link->ddc_hw_inst =
1077                 dal_ddc_get_line(
1078                         dal_ddc_service_get_ddc_pin(link->ddc));
1079
1080         enc_init_data.ctx = dc_ctx;
1081         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1082         enc_init_data.connector = link->link_id;
1083         enc_init_data.channel = get_ddc_line(link);
1084         enc_init_data.hpd_source = get_hpd_line(link);
1085
1086         link->hpd_src = enc_init_data.hpd_source;
1087
1088         enc_init_data.transmitter =
1089                         translate_encoder_to_transmitter(enc_init_data.encoder);
1090         link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1091                                                                 &enc_init_data);
1092
1093         if( link->link_enc == NULL) {
1094                 DC_ERROR("Failed to create link encoder!\n");
1095                 goto link_enc_create_fail;
1096         }
1097
1098         link->link_enc_hw_inst = link->link_enc->transmitter;
1099
1100         for (i = 0; i < 4; i++) {
1101                 if (BP_RESULT_OK !=
1102                                 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1103                         DC_ERROR("Failed to find device tag!\n");
1104                         goto device_tag_fail;
1105                 }
1106
1107                 /* Look for device tag that matches connector signal,
1108                  * CRT for rgb, LCD for other supported signal tyes
1109                  */
1110                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1111                         continue;
1112                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1113                         && link->connector_signal != SIGNAL_TYPE_RGB)
1114                         continue;
1115                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1116                         && link->connector_signal == SIGNAL_TYPE_RGB)
1117                         continue;
1118                 break;
1119         }
1120
1121         if (bios->integrated_info)
1122                 info = *bios->integrated_info;
1123
1124         /* Look for channel mapping corresponding to connector and device tag */
1125         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1126                 struct external_display_path *path =
1127                         &info.ext_disp_conn_info.path[i];
1128                 if (path->device_connector_id.enum_id == link->link_id.enum_id
1129                         && path->device_connector_id.id == link->link_id.id
1130                         && path->device_connector_id.type == link->link_id.type) {
1131
1132                         if (link->device_tag.acpi_device != 0
1133                                 && path->device_acpi_enum == link->device_tag.acpi_device) {
1134                                 link->ddi_channel_mapping = path->channel_mapping;
1135                                 link->chip_caps = path->caps;
1136                         } else if (path->device_tag ==
1137                                         link->device_tag.dev_id.raw_device_tag) {
1138                                 link->ddi_channel_mapping = path->channel_mapping;
1139                                 link->chip_caps = path->caps;
1140                         }
1141                         break;
1142                 }
1143         }
1144
1145         /*
1146          * TODO check if GPIO programmed correctly
1147          *
1148          * If GPIO isn't programmed correctly HPD might not rise or drain
1149          * fast enough, leading to bounces.
1150          */
1151         program_hpd_filter(link);
1152
1153         return true;
1154 device_tag_fail:
1155         link->link_enc->funcs->destroy(&link->link_enc);
1156 link_enc_create_fail:
1157         dal_ddc_service_destroy(&link->ddc);
1158 ddc_create_fail:
1159 create_fail:
1160
1161         if (hpd_gpio != NULL) {
1162                 dal_gpio_destroy_irq(&hpd_gpio);
1163         }
1164
1165         return false;
1166 }
1167
1168 /*******************************************************************************
1169  * Public functions
1170  ******************************************************************************/
1171 struct dc_link *link_create(const struct link_init_data *init_params)
1172 {
1173         struct dc_link *link =
1174                         kzalloc(sizeof(*link), GFP_KERNEL);
1175
1176         if (NULL == link)
1177                 goto alloc_fail;
1178
1179         if (false == construct(link, init_params))
1180                 goto construct_fail;
1181
1182         return link;
1183
1184 construct_fail:
1185         kfree(link);
1186
1187 alloc_fail:
1188         return NULL;
1189 }
1190
1191 void link_destroy(struct dc_link **link)
1192 {
1193         destruct(*link);
1194         kfree(*link);
1195         *link = NULL;
1196 }
1197
1198 static void dpcd_configure_panel_mode(
1199         struct dc_link *link,
1200         enum dp_panel_mode panel_mode)
1201 {
1202         union dpcd_edp_config edp_config_set;
1203         bool panel_mode_edp = false;
1204         DC_LOGGER_INIT(link->ctx->logger);
1205
1206         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
1207
1208         if (DP_PANEL_MODE_DEFAULT != panel_mode) {
1209
1210                 switch (panel_mode) {
1211                 case DP_PANEL_MODE_EDP:
1212                 case DP_PANEL_MODE_SPECIAL:
1213                         panel_mode_edp = true;
1214                         break;
1215
1216                 default:
1217                         break;
1218                 }
1219
1220                 /*set edp panel mode in receiver*/
1221                 core_link_read_dpcd(
1222                         link,
1223                         DP_EDP_CONFIGURATION_SET,
1224                         &edp_config_set.raw,
1225                         sizeof(edp_config_set.raw));
1226
1227                 if (edp_config_set.bits.PANEL_MODE_EDP
1228                         != panel_mode_edp) {
1229                         enum ddc_result result = DDC_RESULT_UNKNOWN;
1230
1231                         edp_config_set.bits.PANEL_MODE_EDP =
1232                         panel_mode_edp;
1233                         result = core_link_write_dpcd(
1234                                 link,
1235                                 DP_EDP_CONFIGURATION_SET,
1236                                 &edp_config_set.raw,
1237                                 sizeof(edp_config_set.raw));
1238
1239                         ASSERT(result == DDC_RESULT_SUCESSFULL);
1240                 }
1241         }
1242         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
1243                         "eDP panel mode enabled: %d \n",
1244                         link->link_index,
1245                         link->dpcd_caps.panel_mode_edp,
1246                         panel_mode_edp);
1247 }
1248
1249 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1250 {
1251         struct dc_stream_state *stream = pipe_ctx->stream;
1252         struct dc_link *link = stream->sink->link;
1253         union down_spread_ctrl old_downspread;
1254         union down_spread_ctrl new_downspread;
1255
1256         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1257                         &old_downspread.raw, sizeof(old_downspread));
1258
1259         new_downspread.raw = old_downspread.raw;
1260
1261         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1262                         (stream->ignore_msa_timing_param) ? 1 : 0;
1263
1264         if (new_downspread.raw != old_downspread.raw) {
1265                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1266                         &new_downspread.raw, sizeof(new_downspread));
1267         }
1268 }
1269
1270 static enum dc_status enable_link_dp(
1271                 struct dc_state *state,
1272                 struct pipe_ctx *pipe_ctx)
1273 {
1274         struct dc_stream_state *stream = pipe_ctx->stream;
1275         enum dc_status status;
1276         bool skip_video_pattern;
1277         struct dc_link *link = stream->sink->link;
1278         struct dc_link_settings link_settings = {0};
1279         enum dp_panel_mode panel_mode;
1280         enum dc_link_rate max_link_rate = LINK_RATE_HIGH2;
1281
1282         /* get link settings for video mode timing */
1283         decide_link_settings(stream, &link_settings);
1284
1285         /* raise clock state for HBR3 if required. Confirmed with HW DCE/DPCS
1286          * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
1287          */
1288         if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1289                 max_link_rate = LINK_RATE_HIGH3;
1290
1291         if (link_settings.link_rate == max_link_rate) {
1292                 struct dc_clocks clocks = state->bw.dcn.clk;
1293
1294                 /* dce/dcn compat, do not update dispclk */
1295                 clocks.dispclk_khz = 0;
1296                 /* 27mhz = 27000000hz= 27000khz */
1297                 clocks.phyclk_khz = link_settings.link_rate * 27000;
1298
1299                 state->dis_clk->funcs->update_clocks(
1300                                 state->dis_clk, &clocks, false);
1301         }
1302
1303         dp_enable_link_phy(
1304                 link,
1305                 pipe_ctx->stream->signal,
1306                 pipe_ctx->clock_source->id,
1307                 &link_settings);
1308
1309         if (stream->sink->edid_caps.panel_patch.dppowerup_delay > 0) {
1310                 int delay_dp_power_up_in_ms = stream->sink->edid_caps.panel_patch.dppowerup_delay;
1311
1312                 msleep(delay_dp_power_up_in_ms);
1313         }
1314
1315         panel_mode = dp_get_panel_mode(link);
1316         dpcd_configure_panel_mode(link, panel_mode);
1317
1318         skip_video_pattern = true;
1319
1320         if (link_settings.link_rate == LINK_RATE_LOW)
1321                         skip_video_pattern = false;
1322
1323         if (perform_link_training_with_retries(
1324                         link,
1325                         &link_settings,
1326                         skip_video_pattern,
1327                         LINK_TRAINING_ATTEMPTS)) {
1328                 link->cur_link_settings = link_settings;
1329                 status = DC_OK;
1330         }
1331         else
1332                 status = DC_FAIL_DP_LINK_TRAINING;
1333
1334         enable_stream_features(pipe_ctx);
1335
1336         return status;
1337 }
1338
1339 static enum dc_status enable_link_edp(
1340                 struct dc_state *state,
1341                 struct pipe_ctx *pipe_ctx)
1342 {
1343         enum dc_status status;
1344         struct dc_stream_state *stream = pipe_ctx->stream;
1345         struct dc_link *link = stream->sink->link;
1346         /*in case it is not on*/
1347         link->dc->hwss.edp_power_control(link, true);
1348         link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1349
1350         status = enable_link_dp(state, pipe_ctx);
1351
1352
1353         return status;
1354 }
1355
1356 static enum dc_status enable_link_dp_mst(
1357                 struct dc_state *state,
1358                 struct pipe_ctx *pipe_ctx)
1359 {
1360         struct dc_link *link = pipe_ctx->stream->sink->link;
1361
1362         /* sink signal type after MST branch is MST. Multiple MST sinks
1363          * share one link. Link DP PHY is enable or training only once.
1364          */
1365         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1366                 return DC_OK;
1367
1368         /* clear payload table */
1369         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1370
1371         /* set the sink to MST mode before enabling the link */
1372         dp_enable_mst_on_sink(link, true);
1373
1374         return enable_link_dp(state, pipe_ctx);
1375 }
1376
1377 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1378                 enum engine_id eng_id,
1379                 struct ext_hdmi_settings *settings)
1380 {
1381         bool result = false;
1382         int i = 0;
1383         struct integrated_info *integrated_info =
1384                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1385
1386         if (integrated_info == NULL)
1387                 return false;
1388
1389         /*
1390          * Get retimer settings from sbios for passing SI eye test for DCE11
1391          * The setting values are varied based on board revision and port id
1392          * Therefore the setting values of each ports is passed by sbios.
1393          */
1394
1395         // Check if current bios contains ext Hdmi settings
1396         if (integrated_info->gpu_cap_info & 0x20) {
1397                 switch (eng_id) {
1398                 case ENGINE_ID_DIGA:
1399                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1400                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1401                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1402                         memmove(settings->reg_settings,
1403                                         integrated_info->dp0_ext_hdmi_reg_settings,
1404                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1405                         memmove(settings->reg_settings_6g,
1406                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1407                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1408                         result = true;
1409                         break;
1410                 case ENGINE_ID_DIGB:
1411                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1412                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1413                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1414                         memmove(settings->reg_settings,
1415                                         integrated_info->dp1_ext_hdmi_reg_settings,
1416                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1417                         memmove(settings->reg_settings_6g,
1418                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1419                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1420                         result = true;
1421                         break;
1422                 case ENGINE_ID_DIGC:
1423                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1424                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1425                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1426                         memmove(settings->reg_settings,
1427                                         integrated_info->dp2_ext_hdmi_reg_settings,
1428                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1429                         memmove(settings->reg_settings_6g,
1430                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1431                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1432                         result = true;
1433                         break;
1434                 case ENGINE_ID_DIGD:
1435                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1436                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1437                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1438                         memmove(settings->reg_settings,
1439                                         integrated_info->dp3_ext_hdmi_reg_settings,
1440                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1441                         memmove(settings->reg_settings_6g,
1442                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1443                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1444                         result = true;
1445                         break;
1446                 default:
1447                         break;
1448                 }
1449
1450                 if (result == true) {
1451                         // Validate settings from bios integrated info table
1452                         if (settings->slv_addr == 0)
1453                                 return false;
1454                         if (settings->reg_num > 9)
1455                                 return false;
1456                         if (settings->reg_num_6g > 3)
1457                                 return false;
1458
1459                         for (i = 0; i < settings->reg_num; i++) {
1460                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1461                                         return false;
1462                         }
1463
1464                         for (i = 0; i < settings->reg_num_6g; i++) {
1465                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1466                                         return false;
1467                         }
1468                 }
1469         }
1470
1471         return result;
1472 }
1473
1474 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1475                 uint8_t address, uint8_t *buffer, uint32_t length)
1476 {
1477         struct i2c_command cmd = {0};
1478         struct i2c_payload payload = {0};
1479
1480         memset(&payload, 0, sizeof(payload));
1481         memset(&cmd, 0, sizeof(cmd));
1482
1483         cmd.number_of_payloads = 1;
1484         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1485         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1486
1487         payload.address = address;
1488         payload.data = buffer;
1489         payload.length = length;
1490         payload.write = true;
1491         cmd.payloads = &payload;
1492
1493         if (dc_submit_i2c(pipe_ctx->stream->ctx->dc,
1494                         pipe_ctx->stream->sink->link->link_index, &cmd))
1495                 return true;
1496
1497         return false;
1498 }
1499
1500 static void write_i2c_retimer_setting(
1501                 struct pipe_ctx *pipe_ctx,
1502                 bool is_vga_mode,
1503                 bool is_over_340mhz,
1504                 struct ext_hdmi_settings *settings)
1505 {
1506         uint8_t slave_address = (settings->slv_addr >> 1);
1507         uint8_t buffer[2];
1508         const uint8_t apply_rx_tx_change = 0x4;
1509         uint8_t offset = 0xA;
1510         uint8_t value = 0;
1511         int i = 0;
1512         bool i2c_success = false;
1513
1514         memset(&buffer, 0, sizeof(buffer));
1515
1516         /* Start Ext-Hdmi programming*/
1517
1518         for (i = 0; i < settings->reg_num; i++) {
1519                 /* Apply 3G settings */
1520                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1521
1522                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1523                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1524                         i2c_success = i2c_write(pipe_ctx, slave_address,
1525                                                 buffer, sizeof(buffer));
1526
1527                         if (!i2c_success)
1528                                 /* Write failure */
1529                                 ASSERT(i2c_success);
1530
1531                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1532                          * needs to be set to 1 on every 0xA-0xC write.
1533                          */
1534                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1535                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1536                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1537
1538                                 /* Query current value from offset 0xA */
1539                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1540                                         value = settings->reg_settings[i].i2c_reg_val;
1541                                 else {
1542                                         i2c_success =
1543                                                 dal_ddc_service_query_ddc_data(
1544                                                 pipe_ctx->stream->sink->link->ddc,
1545                                                 slave_address, &offset, 1, &value, 1);
1546                                         if (!i2c_success)
1547                                                 /* Write failure */
1548                                                 ASSERT(i2c_success);
1549                                 }
1550
1551                                 buffer[0] = offset;
1552                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1553                                 buffer[1] = value | apply_rx_tx_change;
1554                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1555                                                 buffer, sizeof(buffer));
1556                                 if (!i2c_success)
1557                                         /* Write failure */
1558                                         ASSERT(i2c_success);
1559                         }
1560                 }
1561         }
1562
1563         /* Apply 3G settings */
1564         if (is_over_340mhz) {
1565                 for (i = 0; i < settings->reg_num_6g; i++) {
1566                         /* Apply 3G settings */
1567                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1568
1569                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1570                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1571                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1572                                                         buffer, sizeof(buffer));
1573
1574                                 if (!i2c_success)
1575                                         /* Write failure */
1576                                         ASSERT(i2c_success);
1577
1578                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1579                                  * needs to be set to 1 on every 0xA-0xC write.
1580                                  */
1581                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1582                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1583                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1584
1585                                         /* Query current value from offset 0xA */
1586                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1587                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1588                                         else {
1589                                                 i2c_success =
1590                                                                 dal_ddc_service_query_ddc_data(
1591                                                                 pipe_ctx->stream->sink->link->ddc,
1592                                                                 slave_address, &offset, 1, &value, 1);
1593                                                 if (!i2c_success)
1594                                                         /* Write failure */
1595                                                         ASSERT(i2c_success);
1596                                         }
1597
1598                                         buffer[0] = offset;
1599                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1600                                         buffer[1] = value | apply_rx_tx_change;
1601                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1602                                                         buffer, sizeof(buffer));
1603                                         if (!i2c_success)
1604                                                 /* Write failure */
1605                                                 ASSERT(i2c_success);
1606                                 }
1607                         }
1608                 }
1609         }
1610
1611         if (is_vga_mode) {
1612                 /* Program additional settings if using 640x480 resolution */
1613
1614                 /* Write offset 0xFF to 0x01 */
1615                 buffer[0] = 0xff;
1616                 buffer[1] = 0x01;
1617                 i2c_success = i2c_write(pipe_ctx, slave_address,
1618                                 buffer, sizeof(buffer));
1619                 if (!i2c_success)
1620                         /* Write failure */
1621                         ASSERT(i2c_success);
1622
1623                 /* Write offset 0x00 to 0x23 */
1624                 buffer[0] = 0x00;
1625                 buffer[1] = 0x23;
1626                 i2c_success = i2c_write(pipe_ctx, slave_address,
1627                                 buffer, sizeof(buffer));
1628                 if (!i2c_success)
1629                         /* Write failure */
1630                         ASSERT(i2c_success);
1631
1632                 /* Write offset 0xff to 0x00 */
1633                 buffer[0] = 0xff;
1634                 buffer[1] = 0x00;
1635                 i2c_success = i2c_write(pipe_ctx, slave_address,
1636                                 buffer, sizeof(buffer));
1637                 if (!i2c_success)
1638                         /* Write failure */
1639                         ASSERT(i2c_success);
1640
1641         }
1642 }
1643
1644 static void write_i2c_default_retimer_setting(
1645                 struct pipe_ctx *pipe_ctx,
1646                 bool is_vga_mode,
1647                 bool is_over_340mhz)
1648 {
1649         uint8_t slave_address = (0xBA >> 1);
1650         uint8_t buffer[2];
1651         bool i2c_success = false;
1652
1653         memset(&buffer, 0, sizeof(buffer));
1654
1655         /* Program Slave Address for tuning single integrity */
1656         /* Write offset 0x0A to 0x13 */
1657         buffer[0] = 0x0A;
1658         buffer[1] = 0x13;
1659         i2c_success = i2c_write(pipe_ctx, slave_address,
1660                         buffer, sizeof(buffer));
1661         if (!i2c_success)
1662                 /* Write failure */
1663                 ASSERT(i2c_success);
1664
1665         /* Write offset 0x0A to 0x17 */
1666         buffer[0] = 0x0A;
1667         buffer[1] = 0x17;
1668         i2c_success = i2c_write(pipe_ctx, slave_address,
1669                         buffer, sizeof(buffer));
1670         if (!i2c_success)
1671                 /* Write failure */
1672                 ASSERT(i2c_success);
1673
1674         /* Write offset 0x0B to 0xDA or 0xD8 */
1675         buffer[0] = 0x0B;
1676         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1677         i2c_success = i2c_write(pipe_ctx, slave_address,
1678                         buffer, sizeof(buffer));
1679         if (!i2c_success)
1680                 /* Write failure */
1681                 ASSERT(i2c_success);
1682
1683         /* Write offset 0x0A to 0x17 */
1684         buffer[0] = 0x0A;
1685         buffer[1] = 0x17;
1686         i2c_success = i2c_write(pipe_ctx, slave_address,
1687                         buffer, sizeof(buffer));
1688         if (!i2c_success)
1689                 /* Write failure */
1690                 ASSERT(i2c_success);
1691
1692         /* Write offset 0x0C to 0x1D or 0x91 */
1693         buffer[0] = 0x0C;
1694         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1695         i2c_success = i2c_write(pipe_ctx, slave_address,
1696                         buffer, sizeof(buffer));
1697         if (!i2c_success)
1698                 /* Write failure */
1699                 ASSERT(i2c_success);
1700
1701         /* Write offset 0x0A to 0x17 */
1702         buffer[0] = 0x0A;
1703         buffer[1] = 0x17;
1704         i2c_success = i2c_write(pipe_ctx, slave_address,
1705                         buffer, sizeof(buffer));
1706         if (!i2c_success)
1707                 /* Write failure */
1708                 ASSERT(i2c_success);
1709
1710
1711         if (is_vga_mode) {
1712                 /* Program additional settings if using 640x480 resolution */
1713
1714                 /* Write offset 0xFF to 0x01 */
1715                 buffer[0] = 0xff;
1716                 buffer[1] = 0x01;
1717                 i2c_success = i2c_write(pipe_ctx, slave_address,
1718                                 buffer, sizeof(buffer));
1719                 if (!i2c_success)
1720                         /* Write failure */
1721                         ASSERT(i2c_success);
1722
1723                 /* Write offset 0x00 to 0x23 */
1724                 buffer[0] = 0x00;
1725                 buffer[1] = 0x23;
1726                 i2c_success = i2c_write(pipe_ctx, slave_address,
1727                                 buffer, sizeof(buffer));
1728                 if (!i2c_success)
1729                         /* Write failure */
1730                         ASSERT(i2c_success);
1731
1732                 /* Write offset 0xff to 0x00 */
1733                 buffer[0] = 0xff;
1734                 buffer[1] = 0x00;
1735                 i2c_success = i2c_write(pipe_ctx, slave_address,
1736                                 buffer, sizeof(buffer));
1737                 if (!i2c_success)
1738                         /* Write failure */
1739                         ASSERT(i2c_success);
1740         }
1741 }
1742
1743 static void write_i2c_redriver_setting(
1744                 struct pipe_ctx *pipe_ctx,
1745                 bool is_over_340mhz)
1746 {
1747         uint8_t slave_address = (0xF0 >> 1);
1748         uint8_t buffer[16];
1749         bool i2c_success = false;
1750
1751         memset(&buffer, 0, sizeof(buffer));
1752
1753         // Program Slave Address for tuning single integrity
1754         buffer[3] = 0x4E;
1755         buffer[4] = 0x4E;
1756         buffer[5] = 0x4E;
1757         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
1758
1759         i2c_success = i2c_write(pipe_ctx, slave_address,
1760                                         buffer, sizeof(buffer));
1761
1762         if (!i2c_success)
1763                 /* Write failure */
1764                 ASSERT(i2c_success);
1765 }
1766
1767 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1768 {
1769         struct dc_stream_state *stream = pipe_ctx->stream;
1770         struct dc_link *link = stream->sink->link;
1771         enum dc_color_depth display_color_depth;
1772         enum engine_id eng_id;
1773         struct ext_hdmi_settings settings = {0};
1774         bool is_over_340mhz = false;
1775         bool is_vga_mode = (stream->timing.h_addressable == 640)
1776                         && (stream->timing.v_addressable == 480);
1777
1778         if (stream->phy_pix_clk > 340000)
1779                 is_over_340mhz = true;
1780
1781         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
1782                 unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
1783                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1784                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1785                         /* DP159, Retimer settings */
1786                         eng_id = pipe_ctx->stream_res.stream_enc->id;
1787
1788                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
1789                                 write_i2c_retimer_setting(pipe_ctx,
1790                                                 is_vga_mode, is_over_340mhz, &settings);
1791                         } else {
1792                                 write_i2c_default_retimer_setting(pipe_ctx,
1793                                                 is_vga_mode, is_over_340mhz);
1794                         }
1795                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
1796                         /* PI3EQX1204, Redriver settings */
1797                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
1798                 }
1799         }
1800
1801         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1802                 dal_ddc_service_write_scdc_data(
1803                         stream->sink->link->ddc,
1804                         stream->phy_pix_clk,
1805                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
1806
1807         memset(&stream->sink->link->cur_link_settings, 0,
1808                         sizeof(struct dc_link_settings));
1809
1810         display_color_depth = stream->timing.display_color_depth;
1811         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1812                 display_color_depth = COLOR_DEPTH_888;
1813
1814         link->link_enc->funcs->enable_tmds_output(
1815                         link->link_enc,
1816                         pipe_ctx->clock_source->id,
1817                         display_color_depth,
1818                         pipe_ctx->stream->signal,
1819                         stream->phy_pix_clk);
1820
1821         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
1822                 dal_ddc_service_read_scdc_data(link->ddc);
1823 }
1824
1825 /****************************enable_link***********************************/
1826 static enum dc_status enable_link(
1827                 struct dc_state *state,
1828                 struct pipe_ctx *pipe_ctx)
1829 {
1830         enum dc_status status = DC_ERROR_UNEXPECTED;
1831         switch (pipe_ctx->stream->signal) {
1832         case SIGNAL_TYPE_DISPLAY_PORT:
1833                 status = enable_link_dp(state, pipe_ctx);
1834                 break;
1835         case SIGNAL_TYPE_EDP:
1836                 status = enable_link_edp(state, pipe_ctx);
1837                 break;
1838         case SIGNAL_TYPE_DISPLAY_PORT_MST:
1839                 status = enable_link_dp_mst(state, pipe_ctx);
1840                 msleep(200);
1841                 break;
1842         case SIGNAL_TYPE_DVI_SINGLE_LINK:
1843         case SIGNAL_TYPE_DVI_DUAL_LINK:
1844         case SIGNAL_TYPE_HDMI_TYPE_A:
1845                 enable_link_hdmi(pipe_ctx);
1846                 status = DC_OK;
1847                 break;
1848         case SIGNAL_TYPE_VIRTUAL:
1849                 status = DC_OK;
1850                 break;
1851         default:
1852                 break;
1853         }
1854
1855         return status;
1856 }
1857
1858 static void disable_link(struct dc_link *link, enum signal_type signal)
1859 {
1860         /*
1861          * TODO: implement call for dp_set_hw_test_pattern
1862          * it is needed for compliance testing
1863          */
1864
1865         /* here we need to specify that encoder output settings
1866          * need to be calculated as for the set mode,
1867          * it will lead to querying dynamic link capabilities
1868          * which should be done before enable output */
1869
1870         if (dc_is_dp_signal(signal)) {
1871                 /* SST DP, eDP */
1872                 if (dc_is_dp_sst_signal(signal))
1873                         dp_disable_link_phy(link, signal);
1874                 else
1875                         dp_disable_link_phy_mst(link, signal);
1876         } else
1877                 link->link_enc->funcs->disable_output(link->link_enc, signal);
1878 }
1879
1880 static bool dp_active_dongle_validate_timing(
1881                 const struct dc_crtc_timing *timing,
1882                 const struct dpcd_caps *dpcd_caps)
1883 {
1884         unsigned int required_pix_clk = timing->pix_clk_khz;
1885         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
1886
1887         switch (dpcd_caps->dongle_type) {
1888         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
1889         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
1890         case DISPLAY_DONGLE_DP_DVI_DONGLE:
1891                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
1892                         return true;
1893                 else
1894                         return false;
1895         default:
1896                 break;
1897         }
1898
1899         if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
1900                 dongle_caps->extendedCapValid == false)
1901                 return true;
1902
1903         /* Check Pixel Encoding */
1904         switch (timing->pixel_encoding) {
1905         case PIXEL_ENCODING_RGB:
1906         case PIXEL_ENCODING_YCBCR444:
1907                 break;
1908         case PIXEL_ENCODING_YCBCR422:
1909                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
1910                         return false;
1911                 break;
1912         case PIXEL_ENCODING_YCBCR420:
1913                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
1914                         return false;
1915                 break;
1916         default:
1917                 /* Invalid Pixel Encoding*/
1918                 return false;
1919         }
1920
1921
1922         /* Check Color Depth and Pixel Clock */
1923         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1924                 required_pix_clk /= 2;
1925         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
1926                 required_pix_clk = required_pix_clk * 2 / 3;
1927
1928         switch (timing->display_color_depth) {
1929         case COLOR_DEPTH_666:
1930         case COLOR_DEPTH_888:
1931                 /*888 and 666 should always be supported*/
1932                 break;
1933         case COLOR_DEPTH_101010:
1934                 if (dongle_caps->dp_hdmi_max_bpc < 10)
1935                         return false;
1936                 required_pix_clk = required_pix_clk * 10 / 8;
1937                 break;
1938         case COLOR_DEPTH_121212:
1939                 if (dongle_caps->dp_hdmi_max_bpc < 12)
1940                         return false;
1941                 required_pix_clk = required_pix_clk * 12 / 8;
1942                 break;
1943
1944         case COLOR_DEPTH_141414:
1945         case COLOR_DEPTH_161616:
1946         default:
1947                 /* These color depths are currently not supported */
1948                 return false;
1949         }
1950
1951         if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
1952                 return false;
1953
1954         return true;
1955 }
1956
1957 enum dc_status dc_link_validate_mode_timing(
1958                 const struct dc_stream_state *stream,
1959                 struct dc_link *link,
1960                 const struct dc_crtc_timing *timing)
1961 {
1962         uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
1963         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
1964
1965         /* A hack to avoid failing any modes for EDID override feature on
1966          * topology change such as lower quality cable for DP or different dongle
1967          */
1968         if (link->remote_sinks[0])
1969                 return DC_OK;
1970
1971         /* Passive Dongle */
1972         if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
1973                 return DC_EXCEED_DONGLE_CAP;
1974
1975         /* Active Dongle*/
1976         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
1977                 return DC_EXCEED_DONGLE_CAP;
1978
1979         switch (stream->signal) {
1980         case SIGNAL_TYPE_EDP:
1981         case SIGNAL_TYPE_DISPLAY_PORT:
1982                 if (!dp_validate_mode_timing(
1983                                 link,
1984                                 timing))
1985                         return DC_NO_DP_LINK_BANDWIDTH;
1986                 break;
1987
1988         default:
1989                 break;
1990         }
1991
1992         return DC_OK;
1993 }
1994
1995
1996 bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
1997                 uint32_t frame_ramp, const struct dc_stream_state *stream)
1998 {
1999         struct dc  *core_dc = link->ctx->dc;
2000         struct abm *abm = core_dc->res_pool->abm;
2001         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2002         unsigned int controller_id = 0;
2003         bool use_smooth_brightness = true;
2004         int i;
2005         DC_LOGGER_INIT(link->ctx->logger);
2006
2007         if ((dmcu == NULL) ||
2008                 (abm == NULL) ||
2009                 (abm->funcs->set_backlight_level == NULL))
2010                 return false;
2011
2012         if (stream) {
2013                 if (stream->bl_pwm_level == EDP_BACKLIGHT_RAMP_DISABLE_LEVEL)
2014                         frame_ramp = 0;
2015
2016                 ((struct dc_stream_state *)stream)->bl_pwm_level = level;
2017         }
2018
2019         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2020
2021         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n", level, level);
2022
2023         if (dc_is_embedded_signal(link->connector_signal)) {
2024                 if (stream != NULL) {
2025                         for (i = 0; i < MAX_PIPES; i++) {
2026                                 if (core_dc->current_state->res_ctx.
2027                                                 pipe_ctx[i].stream
2028                                                 == stream)
2029                                         /* DMCU -1 for all controller id values,
2030                                          * therefore +1 here
2031                                          */
2032                                         controller_id =
2033                                                 core_dc->current_state->
2034                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2035                                                 1;
2036                         }
2037                 }
2038                 abm->funcs->set_backlight_level(
2039                                 abm,
2040                                 level,
2041                                 frame_ramp,
2042                                 controller_id,
2043                                 use_smooth_brightness);
2044         }
2045
2046         return true;
2047 }
2048
2049 bool dc_link_set_abm_disable(const struct dc_link *link)
2050 {
2051         struct dc  *core_dc = link->ctx->dc;
2052         struct abm *abm = core_dc->res_pool->abm;
2053
2054         if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL))
2055                 return false;
2056
2057         abm->funcs->set_abm_immediate_disable(abm);
2058
2059         return true;
2060 }
2061
2062 bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
2063 {
2064         struct dc  *core_dc = link->ctx->dc;
2065         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2066
2067         if (dmcu != NULL && link->psr_enabled)
2068                 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
2069
2070         return true;
2071 }
2072
2073 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2074 {
2075         return &link->link_status;
2076 }
2077
2078 void core_link_resume(struct dc_link *link)
2079 {
2080         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2081                 program_hpd_filter(link);
2082 }
2083
2084 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2085 {
2086         struct dc_link_settings *link_settings =
2087                         &stream->sink->link->cur_link_settings;
2088         uint32_t link_rate_in_mbps =
2089                         link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
2090         struct fixed31_32 mbps = dc_fixpt_from_int(
2091                         link_rate_in_mbps * link_settings->lane_count);
2092
2093         return dc_fixpt_div_int(mbps, 54);
2094 }
2095
2096 static int get_color_depth(enum dc_color_depth color_depth)
2097 {
2098         switch (color_depth) {
2099         case COLOR_DEPTH_666: return 6;
2100         case COLOR_DEPTH_888: return 8;
2101         case COLOR_DEPTH_101010: return 10;
2102         case COLOR_DEPTH_121212: return 12;
2103         case COLOR_DEPTH_141414: return 14;
2104         case COLOR_DEPTH_161616: return 16;
2105         default: return 0;
2106         }
2107 }
2108
2109 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2110 {
2111         uint32_t bpc;
2112         uint64_t kbps;
2113         struct fixed31_32 peak_kbps;
2114         uint32_t numerator;
2115         uint32_t denominator;
2116
2117         bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2118         kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
2119
2120         /*
2121          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2122          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2123          * common multiplier to render an integer PBN for all link rate/lane
2124          * counts combinations
2125          * calculate
2126          * peak_kbps *= (1006/1000)
2127          * peak_kbps *= (64/54)
2128          * peak_kbps *= 8    convert to bytes
2129          */
2130
2131         numerator = 64 * PEAK_FACTOR_X1000;
2132         denominator = 54 * 8 * 1000 * 1000;
2133         kbps *= numerator;
2134         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2135
2136         return peak_kbps;
2137 }
2138
2139 static void update_mst_stream_alloc_table(
2140         struct dc_link *link,
2141         struct stream_encoder *stream_enc,
2142         const struct dp_mst_stream_allocation_table *proposed_table)
2143 {
2144         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2145                         { 0 } };
2146         struct link_mst_stream_allocation *dc_alloc;
2147
2148         int i;
2149         int j;
2150
2151         /* if DRM proposed_table has more than one new payload */
2152         ASSERT(proposed_table->stream_count -
2153                         link->mst_stream_alloc_table.stream_count < 2);
2154
2155         /* copy proposed_table to link, add stream encoder */
2156         for (i = 0; i < proposed_table->stream_count; i++) {
2157
2158                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2159                         dc_alloc =
2160                         &link->mst_stream_alloc_table.stream_allocations[j];
2161
2162                         if (dc_alloc->vcp_id ==
2163                                 proposed_table->stream_allocations[i].vcp_id) {
2164
2165                                 work_table[i] = *dc_alloc;
2166                                 break; /* exit j loop */
2167                         }
2168                 }
2169
2170                 /* new vcp_id */
2171                 if (j == link->mst_stream_alloc_table.stream_count) {
2172                         work_table[i].vcp_id =
2173                                 proposed_table->stream_allocations[i].vcp_id;
2174                         work_table[i].slot_count =
2175                                 proposed_table->stream_allocations[i].slot_count;
2176                         work_table[i].stream_enc = stream_enc;
2177                 }
2178         }
2179
2180         /* update link->mst_stream_alloc_table with work_table */
2181         link->mst_stream_alloc_table.stream_count =
2182                         proposed_table->stream_count;
2183         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2184                 link->mst_stream_alloc_table.stream_allocations[i] =
2185                                 work_table[i];
2186 }
2187
2188 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2189  * because stream_encoder is not exposed to dm
2190  */
2191 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2192 {
2193         struct dc_stream_state *stream = pipe_ctx->stream;
2194         struct dc_link *link = stream->sink->link;
2195         struct link_encoder *link_encoder = link->link_enc;
2196         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2197         struct dp_mst_stream_allocation_table proposed_table = {0};
2198         struct fixed31_32 avg_time_slots_per_mtp;
2199         struct fixed31_32 pbn;
2200         struct fixed31_32 pbn_per_slot;
2201         uint8_t i;
2202         DC_LOGGER_INIT(link->ctx->logger);
2203
2204         /* enable_link_dp_mst already check link->enabled_stream_count
2205          * and stream is in link->stream[]. This is called during set mode,
2206          * stream_enc is available.
2207          */
2208
2209         /* get calculate VC payload for stream: stream_alloc */
2210         if (dm_helpers_dp_mst_write_payload_allocation_table(
2211                 stream->ctx,
2212                 stream,
2213                 &proposed_table,
2214                 true)) {
2215                 update_mst_stream_alloc_table(
2216                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2217         }
2218         else
2219                 DC_LOG_WARNING("Failed to update"
2220                                 "MST allocation table for"
2221                                 "pipe idx:%d\n",
2222                                 pipe_ctx->pipe_idx);
2223
2224         DC_LOG_MST("%s  "
2225                         "stream_count: %d: \n ",
2226                         __func__,
2227                         link->mst_stream_alloc_table.stream_count);
2228
2229         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2230                 DC_LOG_MST("stream_enc[%d]: %p      "
2231                 "stream[%d].vcp_id: %d      "
2232                 "stream[%d].slot_count: %d\n",
2233                 i,
2234                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2235                 i,
2236                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2237                 i,
2238                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2239         }
2240
2241         ASSERT(proposed_table.stream_count > 0);
2242
2243         /* program DP source TX for payload */
2244         link_encoder->funcs->update_mst_stream_allocation_table(
2245                 link_encoder,
2246                 &link->mst_stream_alloc_table);
2247
2248         /* send down message */
2249         dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2250                         stream->ctx,
2251                         stream);
2252
2253         dm_helpers_dp_mst_send_payload_allocation(
2254                         stream->ctx,
2255                         stream,
2256                         true);
2257
2258         /* slot X.Y for only current stream */
2259         pbn_per_slot = get_pbn_per_slot(stream);
2260         pbn = get_pbn_from_timing(pipe_ctx);
2261         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2262
2263         stream_encoder->funcs->set_mst_bandwidth(
2264                 stream_encoder,
2265                 avg_time_slots_per_mtp);
2266
2267         return DC_OK;
2268
2269 }
2270
2271 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2272 {
2273         struct dc_stream_state *stream = pipe_ctx->stream;
2274         struct dc_link *link = stream->sink->link;
2275         struct link_encoder *link_encoder = link->link_enc;
2276         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2277         struct dp_mst_stream_allocation_table proposed_table = {0};
2278         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2279         uint8_t i;
2280         bool mst_mode = (link->type == dc_connection_mst_branch);
2281         DC_LOGGER_INIT(link->ctx->logger);
2282
2283         /* deallocate_mst_payload is called before disable link. When mode or
2284          * disable/enable monitor, new stream is created which is not in link
2285          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2286          * should not done. For new mode set, map_resources will get engine
2287          * for new stream, so stream_enc->id should be validated until here.
2288          */
2289
2290         /* slot X.Y */
2291         stream_encoder->funcs->set_mst_bandwidth(
2292                 stream_encoder,
2293                 avg_time_slots_per_mtp);
2294
2295         /* TODO: which component is responsible for remove payload table? */
2296         if (mst_mode) {
2297                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2298                                 stream->ctx,
2299                                 stream,
2300                                 &proposed_table,
2301                                 false)) {
2302
2303                         update_mst_stream_alloc_table(
2304                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2305                 }
2306                 else {
2307                                 DC_LOG_WARNING("Failed to update"
2308                                                 "MST allocation table for"
2309                                                 "pipe idx:%d\n",
2310                                                 pipe_ctx->pipe_idx);
2311                 }
2312         }
2313
2314         DC_LOG_MST("%s"
2315                         "stream_count: %d: ",
2316                         __func__,
2317                         link->mst_stream_alloc_table.stream_count);
2318
2319         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2320                 DC_LOG_MST("stream_enc[%d]: %p      "
2321                 "stream[%d].vcp_id: %d      "
2322                 "stream[%d].slot_count: %d\n",
2323                 i,
2324                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2325                 i,
2326                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2327                 i,
2328                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2329         }
2330
2331         link_encoder->funcs->update_mst_stream_allocation_table(
2332                 link_encoder,
2333                 &link->mst_stream_alloc_table);
2334
2335         if (mst_mode) {
2336                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2337                         stream->ctx,
2338                         stream);
2339
2340                 dm_helpers_dp_mst_send_payload_allocation(
2341                         stream->ctx,
2342                         stream,
2343                         false);
2344         }
2345
2346         return DC_OK;
2347 }
2348
2349 void core_link_enable_stream(
2350                 struct dc_state *state,
2351                 struct pipe_ctx *pipe_ctx)
2352 {
2353         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2354         enum dc_status status;
2355         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2356
2357         /* eDP lit up by bios already, no need to enable again. */
2358         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2359                 core_dc->apply_edp_fast_boot_optimization) {
2360                 core_dc->apply_edp_fast_boot_optimization = false;
2361                 pipe_ctx->stream->dpms_off = false;
2362                 return;
2363         }
2364
2365         if (pipe_ctx->stream->dpms_off)
2366                 return;
2367
2368         status = enable_link(state, pipe_ctx);
2369
2370         if (status != DC_OK) {
2371                         DC_LOG_WARNING("enabling link %u failed: %d\n",
2372                         pipe_ctx->stream->sink->link->link_index,
2373                         status);
2374
2375                         /* Abort stream enable *unless* the failure was due to
2376                          * DP link training - some DP monitors will recover and
2377                          * show the stream anyway. But MST displays can't proceed
2378                          * without link training.
2379                          */
2380                         if (status != DC_FAIL_DP_LINK_TRAINING ||
2381                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2382                                 BREAK_TO_DEBUGGER();
2383                                 return;
2384                         }
2385         }
2386
2387         core_dc->hwss.enable_audio_stream(pipe_ctx);
2388
2389         /* turn off otg test pattern if enable */
2390         if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2391                 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2392                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2393                                 COLOR_DEPTH_UNDEFINED);
2394
2395         core_dc->hwss.enable_stream(pipe_ctx);
2396
2397         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2398                 allocate_mst_payload(pipe_ctx);
2399
2400         core_dc->hwss.unblank_stream(pipe_ctx,
2401                 &pipe_ctx->stream->sink->link->cur_link_settings);
2402 }
2403
2404 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
2405 {
2406         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2407
2408         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2409                 deallocate_mst_payload(pipe_ctx);
2410
2411         core_dc->hwss.blank_stream(pipe_ctx);
2412
2413         core_dc->hwss.disable_stream(pipe_ctx, option);
2414
2415         disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
2416 }
2417
2418 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2419 {
2420         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2421
2422         if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2423                 return;
2424
2425         core_dc->hwss.set_avmute(pipe_ctx, enable);
2426 }
2427
2428 /**
2429  *****************************************************************************
2430  *  Function: dc_link_enable_hpd_filter
2431  *
2432  *  @brief
2433  *     If enable is true, programs HPD filter on associated HPD line using
2434  *     delay_on_disconnect/delay_on_connect values dependent on
2435  *     link->connector_signal
2436  *
2437  *     If enable is false, programs HPD filter on associated HPD line with no
2438  *     delays on connect or disconnect
2439  *
2440  *  @param [in] link: pointer to the dc link
2441  *  @param [in] enable: boolean specifying whether to enable hbd
2442  *****************************************************************************
2443  */
2444 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
2445 {
2446         struct gpio *hpd;
2447
2448         if (enable) {
2449                 link->is_hpd_filter_disabled = false;
2450                 program_hpd_filter(link);
2451         } else {
2452                 link->is_hpd_filter_disabled = true;
2453                 /* Obtain HPD handle */
2454                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
2455
2456                 if (!hpd)
2457                         return;
2458
2459                 /* Setup HPD filtering */
2460                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
2461                         struct gpio_hpd_config config;
2462
2463                         config.delay_on_connect = 0;
2464                         config.delay_on_disconnect = 0;
2465
2466                         dal_irq_setup_hpd_filter(hpd, &config);
2467
2468                         dal_gpio_close(hpd);
2469                 } else {
2470                         ASSERT_CRITICAL(false);
2471                 }
2472                 /* Release HPD handle */
2473                 dal_gpio_destroy_irq(&hpd);
2474         }
2475 }
2476