drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atomfirmware.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48 #include "dce/dmub_psr.h"
  49 #include "dmub/dmub_srv.h"
  50 #include "inc/hw/panel_cntl.h"
  51 #include "inc/link_enc_cfg.h"
  52 #include "inc/link_dpcd.h"
  53
  54 #include "dc/dcn30/dcn30_vpg.h"
  55
  56 #define DC_LOGGER_INIT(logger)
  57
  58 #define LINK_INFO(...) \
  59         DC_LOG_HW_HOTPLUG(  \
  60                 __VA_ARGS__)
  61
  62 #define RETIMER_REDRIVER_INFO(...) \
  63         DC_LOG_RETIMER_REDRIVER(  \
  64                 __VA_ARGS__)
  65
  66 /*******************************************************************************
  67  * Private functions
  68  ******************************************************************************/
  69 #if defined(CONFIG_DRM_AMD_DC_DCN)
  70 static bool add_dp_hpo_link_encoder_to_link(struct dc_link *link)
  71 {
  72         struct hpo_dp_link_encoder *enc = resource_get_unused_hpo_dp_link_encoder(
  73                                         link->dc->res_pool);
  74
  75         if (!link->hpo_dp_link_enc && enc) {
  76                 link->hpo_dp_link_enc = enc;
  77                 link->hpo_dp_link_enc->transmitter = link->link_enc->transmitter;
  78                 link->hpo_dp_link_enc->hpd_source = link->link_enc->hpd_source;
  79         }
  80
  81         return (link->hpo_dp_link_enc != NULL);
  82 }
  83
  84 static void remove_dp_hpo_link_encoder_from_link(struct dc_link *link)
  85 {
  86         if (link->hpo_dp_link_enc) {
  87                 link->hpo_dp_link_enc->hpd_source = HPD_SOURCEID_UNKNOWN;
  88                 link->hpo_dp_link_enc->transmitter = TRANSMITTER_UNKNOWN;
  89                 link->hpo_dp_link_enc = NULL;
  90         }
  91 }
  92 #endif
  93
  94 static void dc_link_destruct(struct dc_link *link)
  95 {
  96         int i;
  97
  98         if (link->hpd_gpio) {
  99                 dal_gpio_destroy_irq(&link->hpd_gpio);
 100                 link->hpd_gpio = NULL;
 101         }
 102
 103         if (link->ddc)
 104                 dal_ddc_service_destroy(&link->ddc);
 105
 106         if (link->panel_cntl)
 107                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
 108
 109         if (link->link_enc) {
 110                 /* Update link encoder resource tracking variables. These are used for
 111                  * the dynamic assignment of link encoders to streams. Virtual links
 112                  * are not assigned encoder resources on creation.
 113                  */
 114                 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
 115                         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
 116                         link->dc->res_pool->dig_link_enc_count--;
 117                 }
 118                 link->link_enc->funcs->destroy(&link->link_enc);
 119         }
 120
 121 #if defined(CONFIG_DRM_AMD_DC_DCN)
 122         if (link->hpo_dp_link_enc) {
 123                 remove_dp_hpo_link_encoder_from_link(link);
 124         }
 125 #endif
 126
 127         if (link->local_sink)
 128                 dc_sink_release(link->local_sink);
 129
 130         for (i = 0; i < link->sink_count; ++i)
 131                 dc_sink_release(link->remote_sinks[i]);
 132 }
 133
 134 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 135                           struct graphics_object_id link_id,
 136                           struct gpio_service *gpio_service)
 137 {
 138         enum bp_result bp_result;
 139         struct graphics_object_hpd_info hpd_info;
 140         struct gpio_pin_info pin_info;
 141
 142         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 143                 return NULL;
 144
 145         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 146                 hpd_info.hpd_int_gpio_uid, &pin_info);
 147
 148         if (bp_result != BP_RESULT_OK) {
 149                 ASSERT(bp_result == BP_RESULT_NORECORD);
 150                 return NULL;
 151         }
 152
 153         return dal_gpio_service_create_irq(gpio_service,
 154                                            pin_info.offset,
 155                                            pin_info.mask);
 156 }
 157
 158 /*
 159  *  Function: program_hpd_filter
 160  *
 161  *  @brief
 162  *     Programs HPD filter on associated HPD line
 163  *
 164  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 165  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 166  *
 167  *  @return
 168  *     true on success, false otherwise
 169  */
 170 static bool program_hpd_filter(const struct dc_link *link)
 171 {
 172         bool result = false;
 173         struct gpio *hpd;
 174         int delay_on_connect_in_ms = 0;
 175         int delay_on_disconnect_in_ms = 0;
 176
 177         if (link->is_hpd_filter_disabled)
 178                 return false;
 179         /* Verify feature is supported */
 180         switch (link->connector_signal) {
 181         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 182         case SIGNAL_TYPE_DVI_DUAL_LINK:
 183         case SIGNAL_TYPE_HDMI_TYPE_A:
 184                 /* Program hpd filter */
 185                 delay_on_connect_in_ms = 500;
 186                 delay_on_disconnect_in_ms = 100;
 187                 break;
 188         case SIGNAL_TYPE_DISPLAY_PORT:
 189         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 190                 /* Program hpd filter to allow DP signal to settle */
 191                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 192                  * only 100ms on DELL U2413
 193                  * 0: some passive dongle still show aux mode instead of i2c
 194                  * 20-50: not enough to hide bouncing HPD with passive dongle.
 195                  * also see intermittent i2c read issues.
 196                  */
 197                 delay_on_connect_in_ms = 80;
 198                 delay_on_disconnect_in_ms = 0;
 199                 break;
 200         case SIGNAL_TYPE_LVDS:
 201         case SIGNAL_TYPE_EDP:
 202         default:
 203                 /* Don't program hpd filter */
 204                 return false;
 205         }
 206
 207         /* Obtain HPD handle */
 208         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 209                            link->ctx->gpio_service);
 210
 211         if (!hpd)
 212                 return result;
 213
 214         /* Setup HPD filtering */
 215         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 216                 struct gpio_hpd_config config;
 217
 218                 config.delay_on_connect = delay_on_connect_in_ms;
 219                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 220
 221                 dal_irq_setup_hpd_filter(hpd, &config);
 222
 223                 dal_gpio_close(hpd);
 224
 225                 result = true;
 226         } else {
 227                 ASSERT_CRITICAL(false);
 228         }
 229
 230         /* Release HPD handle */
 231         dal_gpio_destroy_irq(&hpd);
 232
 233         return result;
 234 }
 235
 236 bool dc_link_wait_for_t12(struct dc_link *link)
 237 {
 238         if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 239                 link->dc->hwss.edp_wait_for_T12(link);
 240
 241                 return true;
 242         }
 243
 244         return false;
 245 }
 246
 247 /**
 248  * dc_link_detect_sink() - Determine if there is a sink connected
 249  *
 250  * @link: pointer to the dc link
 251  * @type: Returned connection type
 252  * Does not detect downstream devices, such as MST sinks
 253  * or display connected through active dongles
 254  */
 255 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 256 {
 257         uint32_t is_hpd_high = 0;
 258         struct gpio *hpd_pin;
 259
 260         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 261                 *type = dc_connection_single;
 262                 return true;
 263         }
 264
 265         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 266                 /*in case it is not on*/
 267                 link->dc->hwss.edp_power_control(link, true);
 268                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 269         }
 270
 271         /* Link may not have physical HPD pin. */
 272         if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
 273                 if (link->hpd_status)
 274                         *type = dc_connection_single;
 275                 else
 276                         *type = dc_connection_none;
 277
 278                 return true;
 279         }
 280
 281         /* todo: may need to lock gpio access */
 282         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 283                                link->ctx->gpio_service);
 284         if (!hpd_pin)
 285                 goto hpd_gpio_failure;
 286
 287         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 288         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 289         dal_gpio_close(hpd_pin);
 290         dal_gpio_destroy_irq(&hpd_pin);
 291
 292         if (is_hpd_high) {
 293                 *type = dc_connection_single;
 294                 /* TODO: need to do the actual detection */
 295         } else {
 296                 *type = dc_connection_none;
 297         }
 298
 299         return true;
 300
 301 hpd_gpio_failure:
 302         return false;
 303 }
 304
 305 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 306 {
 307         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 308
 309         switch (sink_signal) {
 310         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 311         case SIGNAL_TYPE_DVI_DUAL_LINK:
 312         case SIGNAL_TYPE_HDMI_TYPE_A:
 313         case SIGNAL_TYPE_LVDS:
 314         case SIGNAL_TYPE_RGB:
 315                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 316                 break;
 317
 318         case SIGNAL_TYPE_DISPLAY_PORT:
 319         case SIGNAL_TYPE_EDP:
 320                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 321                 break;
 322
 323         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 324                 /* MST does not use I2COverAux, but there is the
 325                  * SPECIAL use case for "immediate dwnstrm device
 326                  * access" (EPR#370830).
 327                  */
 328                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 329                 break;
 330
 331         default:
 332                 break;
 333         }
 334
 335         return transaction_type;
 336 }
 337
 338 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 339                                               struct graphics_object_id downstream)
 340 {
 341         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 342                 switch (downstream.id) {
 343                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 344                         switch (encoder.id) {
 345                         case ENCODER_ID_INTERNAL_DAC1:
 346                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 347                         case ENCODER_ID_INTERNAL_DAC2:
 348                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 349                                 return SIGNAL_TYPE_RGB;
 350                         default:
 351                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 352                         }
 353                 break;
 354                 case CONNECTOR_ID_DUAL_LINK_DVII:
 355                 {
 356                         switch (encoder.id) {
 357                         case ENCODER_ID_INTERNAL_DAC1:
 358                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 359                         case ENCODER_ID_INTERNAL_DAC2:
 360                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 361                                 return SIGNAL_TYPE_RGB;
 362                         default:
 363                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 364                         }
 365                 }
 366                 break;
 367                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 368                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 369                 case CONNECTOR_ID_DUAL_LINK_DVID:
 370                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 371                 case CONNECTOR_ID_VGA:
 372                         return SIGNAL_TYPE_RGB;
 373                 case CONNECTOR_ID_HDMI_TYPE_A:
 374                         return SIGNAL_TYPE_HDMI_TYPE_A;
 375                 case CONNECTOR_ID_LVDS:
 376                         return SIGNAL_TYPE_LVDS;
 377                 case CONNECTOR_ID_DISPLAY_PORT:
 378                         return SIGNAL_TYPE_DISPLAY_PORT;
 379                 case CONNECTOR_ID_EDP:
 380                         return SIGNAL_TYPE_EDP;
 381                 default:
 382                         return SIGNAL_TYPE_NONE;
 383                 }
 384         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 385                 switch (downstream.id) {
 386                 case ENCODER_ID_EXTERNAL_NUTMEG:
 387                 case ENCODER_ID_EXTERNAL_TRAVIS:
 388                         return SIGNAL_TYPE_DISPLAY_PORT;
 389                 default:
 390                         return SIGNAL_TYPE_NONE;
 391                 }
 392         }
 393
 394         return SIGNAL_TYPE_NONE;
 395 }
 396
 397 /*
 398  * dc_link_is_dp_sink_present() - Check if there is a native DP
 399  * or passive DP-HDMI dongle connected
 400  */
 401 bool dc_link_is_dp_sink_present(struct dc_link *link)
 402 {
 403         enum gpio_result gpio_result;
 404         uint32_t clock_pin = 0;
 405         uint8_t retry = 0;
 406         struct ddc *ddc;
 407
 408         enum connector_id connector_id =
 409                 dal_graphics_object_id_get_connector_id(link->link_id);
 410
 411         bool present =
 412                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 413                 (connector_id == CONNECTOR_ID_EDP));
 414
 415         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 416
 417         if (!ddc) {
 418                 BREAK_TO_DEBUGGER();
 419                 return present;
 420         }
 421
 422         /* Open GPIO and set it to I2C mode */
 423         /* Note: this GpioMode_Input will be converted
 424          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 425          * which indicates we need additional delay
 426          */
 427
 428         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 429                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 430                 dal_ddc_close(ddc);
 431
 432                 return present;
 433         }
 434
 435         /*
 436          * Read GPIO: DP sink is present if both clock and data pins are zero
 437          *
 438          * [W/A] plug-unplug DP cable, sometimes customer board has
 439          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 440          * then monitor can't br light up. Add retry 3 times
 441          * But in real passive dongle, it need additional 3ms to detect
 442          */
 443         do {
 444                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 445                 ASSERT(gpio_result == GPIO_RESULT_OK);
 446                 if (clock_pin)
 447                         udelay(1000);
 448                 else
 449                         break;
 450         } while (retry++ < 3);
 451
 452         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 453
 454         dal_ddc_close(ddc);
 455
 456         return present;
 457 }
 458
 459 /*
 460  * @brief
 461  * Detect output sink type
 462  */
 463 static enum signal_type link_detect_sink(struct dc_link *link,
 464                                          enum dc_detect_reason reason)
 465 {
 466         enum signal_type result;
 467         struct graphics_object_id enc_id;
 468
 469         if (link->is_dig_mapping_flexible)
 470                 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
 471         else
 472                 enc_id = link->link_enc->id;
 473         result = get_basic_signal_type(enc_id, link->link_id);
 474
 475         /* Use basic signal type for link without physical connector. */
 476         if (link->ep_type != DISPLAY_ENDPOINT_PHY)
 477                 return result;
 478
 479         /* Internal digital encoder will detect only dongles
 480          * that require digital signal
 481          */
 482
 483         /* Detection mechanism is different
 484          * for different native connectors.
 485          * LVDS connector supports only LVDS signal;
 486          * PCIE is a bus slot, the actual connector needs to be detected first;
 487          * eDP connector supports only eDP signal;
 488          * HDMI should check straps for audio
 489          */
 490
 491         /* PCIE detects the actual connector on add-on board */
 492         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 493                 /* ZAZTODO implement PCIE add-on card detection */
 494         }
 495
 496         switch (link->link_id.id) {
 497         case CONNECTOR_ID_HDMI_TYPE_A: {
 498                 /* check audio support:
 499                  * if native HDMI is not supported, switch to DVI
 500                  */
 501                 struct audio_support *aud_support =
 502                                         &link->dc->res_pool->audio_support;
 503
 504                 if (!aud_support->hdmi_audio_native)
 505                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 506                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 507         }
 508         break;
 509         case CONNECTOR_ID_DISPLAY_PORT: {
 510                 /* DP HPD short pulse. Passive DP dongle will not
 511                  * have short pulse
 512                  */
 513                 if (reason != DETECT_REASON_HPDRX) {
 514                         /* Check whether DP signal detected: if not -
 515                          * we assume signal is DVI; it could be corrected
 516                          * to HDMI after dongle detection
 517                          */
 518                         if (!dm_helpers_is_dp_sink_present(link))
 519                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 520                 }
 521         }
 522         break;
 523         default:
 524         break;
 525         }
 526
 527         return result;
 528 }
 529
 530 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 531                                                                  struct audio_support *audio_support)
 532 {
 533         enum signal_type signal = SIGNAL_TYPE_NONE;
 534
 535         switch (dongle_type) {
 536         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 537                 if (audio_support->hdmi_audio_on_dongle)
 538                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 539                 else
 540                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 541                 break;
 542         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 543                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 544                 break;
 545         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 546                 if (audio_support->hdmi_audio_native)
 547                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 548                 else
 549                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 550                 break;
 551         default:
 552                 signal = SIGNAL_TYPE_NONE;
 553                 break;
 554         }
 555
 556         return signal;
 557 }
 558
 559 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 560                                                     struct display_sink_capability *sink_cap,
 561                                                     struct audio_support *audio_support)
 562 {
 563         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 564
 565         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 566                                                         audio_support);
 567 }
 568
 569 static void link_disconnect_sink(struct dc_link *link)
 570 {
 571         if (link->local_sink) {
 572                 dc_sink_release(link->local_sink);
 573                 link->local_sink = NULL;
 574         }
 575
 576         link->dpcd_sink_count = 0;
 577         //link->dpcd_caps.dpcd_rev.raw = 0;
 578 }
 579
 580 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 581 {
 582         dc_sink_release(link->local_sink);
 583         link->local_sink = prev_sink;
 584 }
 585
 586 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 587 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 588 {
 589         bool ret = false;
 590
 591         switch (signal) {
 592         case SIGNAL_TYPE_DISPLAY_PORT:
 593         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 594                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 595                 break;
 596         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 597         case SIGNAL_TYPE_DVI_DUAL_LINK:
 598         case SIGNAL_TYPE_HDMI_TYPE_A:
 599         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 600          * we can poll for bksv but some displays have an issue with this. Since its so rare
 601          * for a display to not be 1.4 capable, this assumtion is ok
 602          */
 603                 ret = true;
 604                 break;
 605         default:
 606                 break;
 607         }
 608         return ret;
 609 }
 610
 611 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 612 {
 613         bool ret = false;
 614
 615         switch (signal) {
 616         case SIGNAL_TYPE_DISPLAY_PORT:
 617         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 618                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 619                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 620                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 621                 break;
 622         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 623         case SIGNAL_TYPE_DVI_DUAL_LINK:
 624         case SIGNAL_TYPE_HDMI_TYPE_A:
 625                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 626                 break;
 627         default:
 628                 break;
 629         }
 630
 631         return ret;
 632 }
 633
 634 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 635 {
 636         struct hdcp_protection_message msg22;
 637         struct hdcp_protection_message msg14;
 638
 639         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 640         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 641         memset(link->hdcp_caps.rx_caps.raw, 0,
 642                 sizeof(link->hdcp_caps.rx_caps.raw));
 643
 644         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 645                         link->ddc->transaction_type ==
 646                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 647                         link->connector_signal == SIGNAL_TYPE_EDP) {
 648                 msg22.data = link->hdcp_caps.rx_caps.raw;
 649                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 650                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 651         } else {
 652                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 653                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 654                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 655         }
 656         msg22.version = HDCP_VERSION_22;
 657         msg22.link = HDCP_LINK_PRIMARY;
 658         msg22.max_retries = 5;
 659         dc_process_hdcp_msg(signal, link, &msg22);
 660
 661         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 662                 msg14.data = &link->hdcp_caps.bcaps.raw;
 663                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 664                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 665                 msg14.version = HDCP_VERSION_14;
 666                 msg14.link = HDCP_LINK_PRIMARY;
 667                 msg14.max_retries = 5;
 668
 669                 dc_process_hdcp_msg(signal, link, &msg14);
 670         }
 671
 672 }
 673 #endif
 674
 675 static void read_current_link_settings_on_detect(struct dc_link *link)
 676 {
 677         union lane_count_set lane_count_set = { {0} };
 678         uint8_t link_bw_set;
 679         uint8_t link_rate_set;
 680         uint32_t read_dpcd_retry_cnt = 10;
 681         enum dc_status status = DC_ERROR_UNEXPECTED;
 682         int i;
 683         union max_down_spread max_down_spread = { {0} };
 684
 685         // Read DPCD 00101h to find out the number of lanes currently set
 686         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 687                 status = core_link_read_dpcd(link,
 688                                              DP_LANE_COUNT_SET,
 689                                              &lane_count_set.raw,
 690                                              sizeof(lane_count_set));
 691                 /* First DPCD read after VDD ON can fail if the particular board
 692                  * does not have HPD pin wired correctly. So if DPCD read fails,
 693                  * which it should never happen, retry a few times. Target worst
 694                  * case scenario of 80 ms.
 695                  */
 696                 if (status == DC_OK) {
 697                         link->cur_link_settings.lane_count =
 698                                         lane_count_set.bits.LANE_COUNT_SET;
 699                         break;
 700                 }
 701
 702                 msleep(8);
 703         }
 704
 705         // Read DPCD 00100h to find if standard link rates are set
 706         core_link_read_dpcd(link, DP_LINK_BW_SET,
 707                             &link_bw_set, sizeof(link_bw_set));
 708
 709         if (link_bw_set == 0) {
 710                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 711                         /* If standard link rates are not being used,
 712                          * Read DPCD 00115h to find the edp link rate set used
 713                          */
 714                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 715                                             &link_rate_set, sizeof(link_rate_set));
 716
 717                         // edp_supported_link_rates_count = 0 for DP
 718                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 719                                 link->cur_link_settings.link_rate =
 720                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 721                                 link->cur_link_settings.link_rate_set = link_rate_set;
 722                                 link->cur_link_settings.use_link_rate_set = true;
 723                         }
 724                 } else {
 725                         // Link Rate not found. Seamless boot may not work.
 726                         ASSERT(false);
 727                 }
 728         } else {
 729                 link->cur_link_settings.link_rate = link_bw_set;
 730                 link->cur_link_settings.use_link_rate_set = false;
 731         }
 732         // Read DPCD 00003h to find the max down spread.
 733         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 734                             &max_down_spread.raw, sizeof(max_down_spread));
 735         link->cur_link_settings.link_spread =
 736                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 737                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 738 }
 739
 740 static bool detect_dp(struct dc_link *link,
 741                       struct display_sink_capability *sink_caps,
 742                       enum dc_detect_reason reason)
 743 {
 744         struct audio_support *audio_support = &link->dc->res_pool->audio_support;
 745
 746         sink_caps->signal = link_detect_sink(link, reason);
 747         sink_caps->transaction_type =
 748                 get_ddc_transaction_type(sink_caps->signal);
 749
 750         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 751                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 752                 if (!detect_dp_sink_caps(link))
 753                         return false;
 754                 if (is_mst_supported(link)) {
 755                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 756                         link->type = dc_connection_mst_branch;
 757
 758                         dal_ddc_service_set_transaction_type(link->ddc,
 759                                                              sink_caps->transaction_type);
 760
 761 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 762                         /* In case of fallback to SST when topology discovery below fails
 763                          * HDCP caps will be querried again later by the upper layer (caller
 764                          * of this function). */
 765                         query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
 766 #endif
 767                 }
 768
 769                 if (link->type != dc_connection_mst_branch &&
 770                                 is_dp_branch_device(link))
 771                         /* DP SST branch */
 772                         link->type = dc_connection_sst_branch;
 773         } else {
 774                 /* DP passive dongles */
 775                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 776                                                                 sink_caps,
 777                                                                 audio_support);
 778                 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 779                 link->dpcd_caps.dpcd_rev.raw = 0;
 780         }
 781
 782         return true;
 783 }
 784
 785 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 786 {
 787         if (old_edid->length != new_edid->length)
 788                 return false;
 789
 790         if (new_edid->length == 0)
 791                 return false;
 792
 793         return (memcmp(old_edid->raw_edid,
 794                        new_edid->raw_edid, new_edid->length) == 0);
 795 }
 796
 797 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 798 {
 799         /**
 800          * something is terribly wrong if time out is > 200ms. (5Hz)
 801          * 500 microseconds * 400 tries us 200 ms
 802          **/
 803         unsigned int sleep_time_in_microseconds = 500;
 804         unsigned int tries_allowed = 400;
 805         bool is_in_alt_mode;
 806         unsigned long long enter_timestamp;
 807         unsigned long long finish_timestamp;
 808         unsigned long long time_taken_in_ns;
 809         int tries_taken;
 810
 811         DC_LOGGER_INIT(link->ctx->logger);
 812
 813         if (!link->link_enc->funcs->is_in_alt_mode)
 814                 return true;
 815
 816         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 817         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 818
 819         if (is_in_alt_mode)
 820                 return true;
 821
 822         enter_timestamp = dm_get_timestamp(link->ctx);
 823
 824         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 825                 udelay(sleep_time_in_microseconds);
 826                 /* ask the link if alt mode is enabled, if so return ok */
 827                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 828                         finish_timestamp = dm_get_timestamp(link->ctx);
 829                         time_taken_in_ns =
 830                                 dm_get_elapse_time_in_ns(link->ctx,
 831                                                          finish_timestamp,
 832                                                          enter_timestamp);
 833                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 834                                        div_u64(time_taken_in_ns, 1000000));
 835                         return true;
 836                 }
 837         }
 838         finish_timestamp = dm_get_timestamp(link->ctx);
 839         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 840                                                     enter_timestamp);
 841         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 842                        div_u64(time_taken_in_ns, 1000000));
 843         return false;
 844 }
 845
 846 /*
 847  * dc_link_detect() - Detect if a sink is attached to a given link
 848  *
 849  * link->local_sink is created or destroyed as needed.
 850  *
 851  * This does not create remote sinks but will trigger DM
 852  * to start MST detection if a branch is detected.
 853  */
 854 static bool dc_link_detect_helper(struct dc_link *link,
 855                                   enum dc_detect_reason reason)
 856 {
 857         struct dc_sink_init_data sink_init_data = { 0 };
 858         struct display_sink_capability sink_caps = { 0 };
 859         uint32_t i;
 860         bool converter_disable_audio = false;
 861         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 862         bool same_edid = false;
 863         enum dc_edid_status edid_status;
 864         struct dc_context *dc_ctx = link->ctx;
 865         struct dc_sink *sink = NULL;
 866         struct dc_sink *prev_sink = NULL;
 867         struct dpcd_caps prev_dpcd_caps;
 868         enum dc_connection_type new_connection_type = dc_connection_none;
 869         enum dc_connection_type pre_connection_type = dc_connection_none;
 870         bool perform_dp_seamless_boot = false;
 871         const uint32_t post_oui_delay = 30; // 30ms
 872
 873         DC_LOGGER_INIT(link->ctx->logger);
 874
 875         if (dc_is_virtual_signal(link->connector_signal))
 876                 return false;
 877
 878         if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
 879                 link->connector_signal == SIGNAL_TYPE_EDP) &&
 880                 (!link->dc->config.allow_edp_hotplug_detection)) &&
 881                 link->local_sink) {
 882                 // need to re-write OUI and brightness in resume case
 883                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 884                         dpcd_set_source_specific_data(link);
 885                         msleep(post_oui_delay);
 886                         dc_link_set_default_brightness_aux(link);
 887                         //TODO: use cached
 888                 }
 889
 890                 return true;
 891         }
 892
 893         if (!dc_link_detect_sink(link, &new_connection_type)) {
 894                 BREAK_TO_DEBUGGER();
 895                 return false;
 896         }
 897
 898         prev_sink = link->local_sink;
 899         if (prev_sink) {
 900                 dc_sink_retain(prev_sink);
 901                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 902         }
 903
 904         link_disconnect_sink(link);
 905         if (new_connection_type != dc_connection_none) {
 906                 pre_connection_type = link->type;
 907                 link->type = new_connection_type;
 908                 link->link_state_valid = false;
 909
 910                 /* From Disconnected-to-Connected. */
 911                 switch (link->connector_signal) {
 912                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 913                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 914                         if (aud_support->hdmi_audio_native)
 915                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 916                         else
 917                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 918                         break;
 919                 }
 920
 921                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 922                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 923                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 924                         break;
 925                 }
 926
 927                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 928                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 929                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 930                         break;
 931                 }
 932
 933                 case SIGNAL_TYPE_LVDS: {
 934                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 935                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 936                         break;
 937                 }
 938
 939                 case SIGNAL_TYPE_EDP: {
 940                         read_current_link_settings_on_detect(link);
 941
 942                         detect_edp_sink_caps(link);
 943                         read_current_link_settings_on_detect(link);
 944                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 945                         sink_caps.signal = SIGNAL_TYPE_EDP;
 946                         break;
 947                 }
 948
 949                 case SIGNAL_TYPE_DISPLAY_PORT: {
 950                         /* wa HPD high coming too early*/
 951                         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
 952                             link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 953                                 /* if alt mode times out, return false */
 954                                 if (!wait_for_entering_dp_alt_mode(link))
 955                                         return false;
 956                         }
 957
 958                         if (!detect_dp(link, &sink_caps, reason)) {
 959                                 if (prev_sink)
 960                                         dc_sink_release(prev_sink);
 961                                 return false;
 962                         }
 963
 964 #if defined(CONFIG_DRM_AMD_DC_DCN)
 965                         if (dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING)
 966                                 add_dp_hpo_link_encoder_to_link(link);
 967 #endif
 968
 969                         if (link->type == dc_connection_mst_branch) {
 970                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 971                                           link->link_index);
 972                                 /* Need to setup mst link_cap struct here
 973                                  * otherwise dc_link_detect() will leave mst link_cap
 974                                  * empty which leads to allocate_mst_payload() has "0"
 975                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 976                                  */
 977                                 dp_verify_mst_link_cap(link);
 978
 979                                 /*
 980                                  * This call will initiate MST topology discovery. Which
 981                                  * will detect MST ports and add new DRM connector DRM
 982                                  * framework. Then read EDID via remote i2c over aux. In
 983                                  * the end, will notify DRM detect result and save EDID
 984                                  * into DRM framework.
 985                                  *
 986                                  * .detect is called by .fill_modes.
 987                                  * .fill_modes is called by user mode ioctl
 988                                  * DRM_IOCTL_MODE_GETCONNECTOR.
 989                                  *
 990                                  * .get_modes is called by .fill_modes.
 991                                  *
 992                                  * call .get_modes, AMDGPU DM implementation will create
 993                                  * new dc_sink and add to dc_link. For long HPD plug
 994                                  * in/out, MST has its own handle.
 995                                  *
 996                                  * Therefore, just after dc_create, link->sink is not
 997                                  * created for MST until user mode app calls
 998                                  * DRM_IOCTL_MODE_GETCONNECTOR.
 999                                  *
1000                                  * Need check ->sink usages in case ->sink = NULL
1001                                  * TODO: s3 resume check
1002                                  */
1003
1004                                 dm_helpers_dp_update_branch_info(link->ctx, link);
1005                                 if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
1006                                                 link, reason == DETECT_REASON_BOOT)) {
1007                                         if (prev_sink)
1008                                                 dc_sink_release(prev_sink);
1009                                         return false;
1010                                 } else {
1011                                         link->type = dc_connection_sst_branch;
1012                                         sink_caps.signal = SIGNAL_TYPE_DISPLAY_PORT;
1013                                 }
1014                         }
1015
1016                         /* Active SST downstream branch device unplug*/
1017                         if (link->type == dc_connection_sst_branch &&
1018                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1019                                 if (prev_sink)
1020                                         /* Downstream unplug */
1021                                         dc_sink_release(prev_sink);
1022                                 return true;
1023                         }
1024
1025                         /* disable audio for non DP to HDMI active sst converter */
1026                         if (link->type == dc_connection_sst_branch &&
1027                                         is_dp_active_dongle(link) &&
1028                                         (link->dpcd_caps.dongle_type !=
1029                                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1030                                 converter_disable_audio = true;
1031
1032                         // link switch from MST to non-MST stop topology manager
1033                         if (pre_connection_type == dc_connection_mst_branch &&
1034                                         link->type != dc_connection_mst_branch)
1035                                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1036
1037
1038                         // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
1039                         if (reason == DETECT_REASON_BOOT &&
1040                                         !dc_ctx->dc->config.power_down_display_on_boot &&
1041                                         link->link_status.link_active)
1042                                 perform_dp_seamless_boot = true;
1043
1044                         if (perform_dp_seamless_boot) {
1045                                 read_current_link_settings_on_detect(link);
1046                                 link->verified_link_cap = link->reported_link_cap;
1047                         }
1048
1049                         break;
1050                 }
1051
1052                 default:
1053                         DC_ERROR("Invalid connector type! signal:%d\n",
1054                                  link->connector_signal);
1055                         if (prev_sink)
1056                                 dc_sink_release(prev_sink);
1057                         return false;
1058                 } /* switch() */
1059
1060                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1061                         link->dpcd_sink_count =
1062                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1063                 else
1064                         link->dpcd_sink_count = 1;
1065
1066                 dal_ddc_service_set_transaction_type(link->ddc,
1067                                                      sink_caps.transaction_type);
1068
1069                 link->aux_mode =
1070                         dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1071
1072                 sink_init_data.link = link;
1073                 sink_init_data.sink_signal = sink_caps.signal;
1074
1075                 sink = dc_sink_create(&sink_init_data);
1076                 if (!sink) {
1077                         DC_ERROR("Failed to create sink!\n");
1078                         if (prev_sink)
1079                                 dc_sink_release(prev_sink);
1080                         return false;
1081                 }
1082
1083                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1084                 sink->converter_disable_audio = converter_disable_audio;
1085
1086                 /* dc_sink_create returns a new reference */
1087                 link->local_sink = sink;
1088
1089                 edid_status = dm_helpers_read_local_edid(link->ctx,
1090                                                          link, sink);
1091
1092                 switch (edid_status) {
1093                 case EDID_BAD_CHECKSUM:
1094                         DC_LOG_ERROR("EDID checksum invalid.\n");
1095                         break;
1096                 case EDID_NO_RESPONSE:
1097                         DC_LOG_ERROR("No EDID read.\n");
1098                         /*
1099                          * Abort detection for non-DP connectors if we have
1100                          * no EDID
1101                          *
1102                          * DP needs to report as connected if HDP is high
1103                          * even if we have no EDID in order to go to
1104                          * fail-safe mode
1105                          */
1106                         if (dc_is_hdmi_signal(link->connector_signal) ||
1107                             dc_is_dvi_signal(link->connector_signal)) {
1108                                 if (prev_sink)
1109                                         dc_sink_release(prev_sink);
1110
1111                                 return false;
1112                         }
1113                         break;
1114                 default:
1115                         break;
1116                 }
1117
1118                 // Check if edid is the same
1119                 if ((prev_sink) &&
1120                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1121                         same_edid = is_same_edid(&prev_sink->dc_edid,
1122                                                  &sink->dc_edid);
1123
1124                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1125                         link->ctx->dc->debug.hdmi20_disable = true;
1126
1127                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1128                     sink_caps.transaction_type ==
1129                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1130                         /*
1131                          * TODO debug why Dell 2413 doesn't like
1132                          *  two link trainings
1133                          */
1134 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1135                         query_hdcp_capability(sink->sink_signal, link);
1136 #endif
1137
1138                         // verify link cap for SST non-seamless boot
1139                         if (!perform_dp_seamless_boot)
1140                                 dp_verify_link_cap_with_retries(link,
1141                                                                 &link->reported_link_cap,
1142                                                                 LINK_TRAINING_MAX_VERIFY_RETRY);
1143                 } else {
1144                         // If edid is the same, then discard new sink and revert back to original sink
1145                         if (same_edid) {
1146                                 link_disconnect_remap(prev_sink, link);
1147                                 sink = prev_sink;
1148                                 prev_sink = NULL;
1149                         }
1150 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1151                         query_hdcp_capability(sink->sink_signal, link);
1152 #endif
1153                 }
1154
1155                 /* HDMI-DVI Dongle */
1156                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1157                     !sink->edid_caps.edid_hdmi)
1158                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1159
1160                 /* Connectivity log: detection */
1161                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1162                         CONN_DATA_DETECT(link,
1163                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1164                                          DC_EDID_BLOCK_SIZE,
1165                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1166                 }
1167
1168                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1169                         "manufacturer_id = %X, "
1170                         "product_id = %X, "
1171                         "serial_number = %X, "
1172                         "manufacture_week = %d, "
1173                         "manufacture_year = %d, "
1174                         "display_name = %s, "
1175                         "speaker_flag = %d, "
1176                         "audio_mode_count = %d\n",
1177                         __func__,
1178                         sink->edid_caps.manufacturer_id,
1179                         sink->edid_caps.product_id,
1180                         sink->edid_caps.serial_number,
1181                         sink->edid_caps.manufacture_week,
1182                         sink->edid_caps.manufacture_year,
1183                         sink->edid_caps.display_name,
1184                         sink->edid_caps.speaker_flags,
1185                         sink->edid_caps.audio_mode_count);
1186
1187                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1188                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1189                                 "format_code = %d, "
1190                                 "channel_count = %d, "
1191                                 "sample_rate = %d, "
1192                                 "sample_size = %d\n",
1193                                 __func__,
1194                                 i,
1195                                 sink->edid_caps.audio_modes[i].format_code,
1196                                 sink->edid_caps.audio_modes[i].channel_count,
1197                                 sink->edid_caps.audio_modes[i].sample_rate,
1198                                 sink->edid_caps.audio_modes[i].sample_size);
1199                 }
1200         } else {
1201                 /* From Connected-to-Disconnected. */
1202                 if (link->type == dc_connection_mst_branch) {
1203                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
1204                                   link->link_index);
1205
1206                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1207
1208                         link->mst_stream_alloc_table.stream_count = 0;
1209                         memset(link->mst_stream_alloc_table.stream_allocations,
1210                                0,
1211                                sizeof(link->mst_stream_alloc_table.stream_allocations));
1212                 }
1213
1214 #if defined(CONFIG_DRM_AMD_DC_DCN)
1215                 if (dp_get_link_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING)
1216                         reset_dp_hpo_stream_encoders_for_link(link);
1217 #endif
1218
1219                 link->type = dc_connection_none;
1220                 sink_caps.signal = SIGNAL_TYPE_NONE;
1221                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1222                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1223                  *  the dongle is still there and limits the number of modes we can emulate.
1224                  *  Clear dongle_max_pix_clk on disconnect to fix this
1225                  */
1226                 link->dongle_max_pix_clk = 0;
1227         }
1228
1229         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1230                   link->link_index, sink,
1231                   (sink_caps.signal ==
1232                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1233                   prev_sink, same_edid);
1234
1235         if (prev_sink)
1236                 dc_sink_release(prev_sink);
1237
1238         return true;
1239 }
1240
1241 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1242 {
1243         const struct dc *dc = link->dc;
1244         bool ret;
1245         bool can_apply_seamless_boot = false;
1246         int i;
1247
1248         for (i = 0; i < dc->current_state->stream_count; i++) {
1249                 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
1250                         can_apply_seamless_boot = true;
1251                         break;
1252                 }
1253         }
1254
1255 #if defined(CONFIG_DRM_AMD_DC_DCN)
1256         dc_z10_restore(dc);
1257 #endif
1258
1259         /* get out of low power state */
1260         if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
1261                 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1262
1263         ret = dc_link_detect_helper(link, reason);
1264
1265         /* Go back to power optimized state */
1266         if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
1267                 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1268
1269         return ret;
1270 }
1271
1272 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1273 {
1274         uint32_t state;
1275
1276         dal_gpio_lock_pin(dc_link->hpd_gpio);
1277         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1278         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1279
1280         return state;
1281 }
1282
1283 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1284 {
1285         struct gpio *hpd;
1286         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1287
1288         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1289                            link->ctx->gpio_service);
1290
1291         if (hpd) {
1292                 switch (dal_irq_get_source(hpd)) {
1293                 case DC_IRQ_SOURCE_HPD1:
1294                         hpd_id = HPD_SOURCEID1;
1295                 break;
1296                 case DC_IRQ_SOURCE_HPD2:
1297                         hpd_id = HPD_SOURCEID2;
1298                 break;
1299                 case DC_IRQ_SOURCE_HPD3:
1300                         hpd_id = HPD_SOURCEID3;
1301                 break;
1302                 case DC_IRQ_SOURCE_HPD4:
1303                         hpd_id = HPD_SOURCEID4;
1304                 break;
1305                 case DC_IRQ_SOURCE_HPD5:
1306                         hpd_id = HPD_SOURCEID5;
1307                 break;
1308                 case DC_IRQ_SOURCE_HPD6:
1309                         hpd_id = HPD_SOURCEID6;
1310                 break;
1311                 default:
1312                         BREAK_TO_DEBUGGER();
1313                 break;
1314                 }
1315
1316                 dal_gpio_destroy_irq(&hpd);
1317         }
1318
1319         return hpd_id;
1320 }
1321
1322 static enum channel_id get_ddc_line(struct dc_link *link)
1323 {
1324         struct ddc *ddc;
1325         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1326
1327         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1328
1329         if (ddc) {
1330                 switch (dal_ddc_get_line(ddc)) {
1331                 case GPIO_DDC_LINE_DDC1:
1332                         channel = CHANNEL_ID_DDC1;
1333                         break;
1334                 case GPIO_DDC_LINE_DDC2:
1335                         channel = CHANNEL_ID_DDC2;
1336                         break;
1337                 case GPIO_DDC_LINE_DDC3:
1338                         channel = CHANNEL_ID_DDC3;
1339                         break;
1340                 case GPIO_DDC_LINE_DDC4:
1341                         channel = CHANNEL_ID_DDC4;
1342                         break;
1343                 case GPIO_DDC_LINE_DDC5:
1344                         channel = CHANNEL_ID_DDC5;
1345                         break;
1346                 case GPIO_DDC_LINE_DDC6:
1347                         channel = CHANNEL_ID_DDC6;
1348                         break;
1349                 case GPIO_DDC_LINE_DDC_VGA:
1350                         channel = CHANNEL_ID_DDC_VGA;
1351                         break;
1352                 case GPIO_DDC_LINE_I2C_PAD:
1353                         channel = CHANNEL_ID_I2C_PAD;
1354                         break;
1355                 default:
1356                         BREAK_TO_DEBUGGER();
1357                         break;
1358                 }
1359         }
1360
1361         return channel;
1362 }
1363
1364 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1365 {
1366         switch (encoder.id) {
1367         case ENCODER_ID_INTERNAL_UNIPHY:
1368                 switch (encoder.enum_id) {
1369                 case ENUM_ID_1:
1370                         return TRANSMITTER_UNIPHY_A;
1371                 case ENUM_ID_2:
1372                         return TRANSMITTER_UNIPHY_B;
1373                 default:
1374                         return TRANSMITTER_UNKNOWN;
1375                 }
1376         break;
1377         case ENCODER_ID_INTERNAL_UNIPHY1:
1378                 switch (encoder.enum_id) {
1379                 case ENUM_ID_1:
1380                         return TRANSMITTER_UNIPHY_C;
1381                 case ENUM_ID_2:
1382                         return TRANSMITTER_UNIPHY_D;
1383                 default:
1384                         return TRANSMITTER_UNKNOWN;
1385                 }
1386         break;
1387         case ENCODER_ID_INTERNAL_UNIPHY2:
1388                 switch (encoder.enum_id) {
1389                 case ENUM_ID_1:
1390                         return TRANSMITTER_UNIPHY_E;
1391                 case ENUM_ID_2:
1392                         return TRANSMITTER_UNIPHY_F;
1393                 default:
1394                         return TRANSMITTER_UNKNOWN;
1395                 }
1396         break;
1397         case ENCODER_ID_INTERNAL_UNIPHY3:
1398                 switch (encoder.enum_id) {
1399                 case ENUM_ID_1:
1400                         return TRANSMITTER_UNIPHY_G;
1401                 default:
1402                         return TRANSMITTER_UNKNOWN;
1403                 }
1404         break;
1405         case ENCODER_ID_EXTERNAL_NUTMEG:
1406                 switch (encoder.enum_id) {
1407                 case ENUM_ID_1:
1408                         return TRANSMITTER_NUTMEG_CRT;
1409                 default:
1410                         return TRANSMITTER_UNKNOWN;
1411                 }
1412         break;
1413         case ENCODER_ID_EXTERNAL_TRAVIS:
1414                 switch (encoder.enum_id) {
1415                 case ENUM_ID_1:
1416                         return TRANSMITTER_TRAVIS_CRT;
1417                 case ENUM_ID_2:
1418                         return TRANSMITTER_TRAVIS_LCD;
1419                 default:
1420                         return TRANSMITTER_UNKNOWN;
1421                 }
1422         break;
1423         default:
1424                 return TRANSMITTER_UNKNOWN;
1425         }
1426 }
1427
1428 static bool dc_link_construct_legacy(struct dc_link *link,
1429                                      const struct link_init_data *init_params)
1430 {
1431         uint8_t i;
1432         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1433         struct dc_context *dc_ctx = init_params->ctx;
1434         struct encoder_init_data enc_init_data = { 0 };
1435         struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1436         struct integrated_info *info;
1437         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1438         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1439         struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1440
1441         DC_LOGGER_INIT(dc_ctx->logger);
1442
1443         info = kzalloc(sizeof(*info), GFP_KERNEL);
1444         if (!info)
1445                 goto create_fail;
1446
1447         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1448         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1449
1450         link->link_status.dpcd_caps = &link->dpcd_caps;
1451
1452         link->dc = init_params->dc;
1453         link->ctx = dc_ctx;
1454         link->link_index = init_params->link_index;
1455
1456         memset(&link->preferred_training_settings, 0,
1457                sizeof(struct dc_link_training_overrides));
1458         memset(&link->preferred_link_setting, 0,
1459                sizeof(struct dc_link_settings));
1460
1461         link->link_id =
1462                 bios->funcs->get_connector_id(bios, init_params->connector_index);
1463
1464         link->ep_type = DISPLAY_ENDPOINT_PHY;
1465
1466         DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1467
1468         if (bios->funcs->get_disp_connector_caps_info) {
1469                 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1470                 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1471                 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1472         }
1473
1474         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1475                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1476                                      __func__, init_params->connector_index,
1477                                      link->link_id.type, OBJECT_TYPE_CONNECTOR);
1478                 goto create_fail;
1479         }
1480
1481         if (link->dc->res_pool->funcs->link_init)
1482                 link->dc->res_pool->funcs->link_init(link);
1483
1484         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1485                                       link->ctx->gpio_service);
1486
1487         if (link->hpd_gpio) {
1488                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1489                 dal_gpio_unlock_pin(link->hpd_gpio);
1490                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1491
1492                 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1493                 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1494         }
1495
1496         switch (link->link_id.id) {
1497         case CONNECTOR_ID_HDMI_TYPE_A:
1498                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1499
1500                 break;
1501         case CONNECTOR_ID_SINGLE_LINK_DVID:
1502         case CONNECTOR_ID_SINGLE_LINK_DVII:
1503                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1504                 break;
1505         case CONNECTOR_ID_DUAL_LINK_DVID:
1506         case CONNECTOR_ID_DUAL_LINK_DVII:
1507                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1508                 break;
1509         case CONNECTOR_ID_DISPLAY_PORT:
1510                 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1511
1512                 if (link->hpd_gpio)
1513                         link->irq_source_hpd_rx =
1514                                         dal_irq_get_rx_source(link->hpd_gpio);
1515
1516                 break;
1517         case CONNECTOR_ID_EDP:
1518                 link->connector_signal = SIGNAL_TYPE_EDP;
1519
1520                 if (link->hpd_gpio) {
1521                         if (!link->dc->config.allow_edp_hotplug_detection)
1522                                 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1523                         link->irq_source_hpd_rx =
1524                                         dal_irq_get_rx_source(link->hpd_gpio);
1525                 }
1526
1527                 break;
1528         case CONNECTOR_ID_LVDS:
1529                 link->connector_signal = SIGNAL_TYPE_LVDS;
1530                 break;
1531         default:
1532                 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1533                                link->link_id.id);
1534                 goto create_fail;
1535         }
1536
1537         /* TODO: #DAL3 Implement id to str function.*/
1538         LINK_INFO("Connector[%d] description:"
1539                   "signal %d\n",
1540                   init_params->connector_index,
1541                   link->connector_signal);
1542
1543         ddc_service_init_data.ctx = link->ctx;
1544         ddc_service_init_data.id = link->link_id;
1545         ddc_service_init_data.link = link;
1546         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1547
1548         if (!link->ddc) {
1549                 DC_ERROR("Failed to create ddc_service!\n");
1550                 goto ddc_create_fail;
1551         }
1552
1553         if (!link->ddc->ddc_pin) {
1554                 DC_ERROR("Failed to get I2C info for connector!\n");
1555                 goto ddc_create_fail;
1556         }
1557
1558         link->ddc_hw_inst =
1559                 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1560
1561
1562         if (link->dc->res_pool->funcs->panel_cntl_create &&
1563                 (link->link_id.id == CONNECTOR_ID_EDP ||
1564                         link->link_id.id == CONNECTOR_ID_LVDS)) {
1565                 panel_cntl_init_data.ctx = dc_ctx;
1566                 panel_cntl_init_data.inst =
1567                         panel_cntl_init_data.ctx->dc_edp_id_count;
1568                 link->panel_cntl =
1569                         link->dc->res_pool->funcs->panel_cntl_create(
1570                                                                 &panel_cntl_init_data);
1571                 panel_cntl_init_data.ctx->dc_edp_id_count++;
1572
1573                 if (link->panel_cntl == NULL) {
1574                         DC_ERROR("Failed to create link panel_cntl!\n");
1575                         goto panel_cntl_create_fail;
1576                 }
1577         }
1578
1579         enc_init_data.ctx = dc_ctx;
1580         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1581                               &enc_init_data.encoder);
1582         enc_init_data.connector = link->link_id;
1583         enc_init_data.channel = get_ddc_line(link);
1584         enc_init_data.hpd_source = get_hpd_line(link);
1585
1586         link->hpd_src = enc_init_data.hpd_source;
1587
1588         enc_init_data.transmitter =
1589                 translate_encoder_to_transmitter(enc_init_data.encoder);
1590         link->link_enc =
1591                 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1592
1593         if (!link->link_enc) {
1594                 DC_ERROR("Failed to create link encoder!\n");
1595                 goto link_enc_create_fail;
1596         }
1597
1598         DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1599 #if defined(CONFIG_DRM_AMD_DC_DCN)
1600         DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE);
1601 #endif
1602
1603         /* Update link encoder tracking variables. These are used for the dynamic
1604          * assignment of link encoders to streams.
1605          */
1606         link->eng_id = link->link_enc->preferred_engine;
1607         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1608         link->dc->res_pool->dig_link_enc_count++;
1609
1610         link->link_enc_hw_inst = link->link_enc->transmitter;
1611
1612         for (i = 0; i < 4; i++) {
1613                 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1614                                              link->link_id, i,
1615                                              &link->device_tag) != BP_RESULT_OK) {
1616                         DC_ERROR("Failed to find device tag!\n");
1617                         goto device_tag_fail;
1618                 }
1619
1620                 /* Look for device tag that matches connector signal,
1621                  * CRT for rgb, LCD for other supported signal tyes
1622                  */
1623                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1624                                                       link->device_tag.dev_id))
1625                         continue;
1626                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1627                     link->connector_signal != SIGNAL_TYPE_RGB)
1628                         continue;
1629                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1630                     link->connector_signal == SIGNAL_TYPE_RGB)
1631                         continue;
1632
1633                 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1634                 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1635                 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1636                 break;
1637         }
1638
1639         if (bios->integrated_info)
1640                 memcpy(info, bios->integrated_info, sizeof(*info));
1641
1642         /* Look for channel mapping corresponding to connector and device tag */
1643         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1644                 struct external_display_path *path =
1645                         &info->ext_disp_conn_info.path[i];
1646
1647                 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1648                     path->device_connector_id.id == link->link_id.id &&
1649                     path->device_connector_id.type == link->link_id.type) {
1650                         if (link->device_tag.acpi_device != 0 &&
1651                             path->device_acpi_enum == link->device_tag.acpi_device) {
1652                                 link->ddi_channel_mapping = path->channel_mapping;
1653                                 link->chip_caps = path->caps;
1654                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1655                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1656                         } else if (path->device_tag ==
1657                                    link->device_tag.dev_id.raw_device_tag) {
1658                                 link->ddi_channel_mapping = path->channel_mapping;
1659                                 link->chip_caps = path->caps;
1660                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1661                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1662                         }
1663                         break;
1664                 }
1665         }
1666
1667         if (bios->funcs->get_atom_dc_golden_table)
1668                 bios->funcs->get_atom_dc_golden_table(bios);
1669
1670         /*
1671          * TODO check if GPIO programmed correctly
1672          *
1673          * If GPIO isn't programmed correctly HPD might not rise or drain
1674          * fast enough, leading to bounces.
1675          */
1676         program_hpd_filter(link);
1677
1678         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1679
1680         DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1681         kfree(info);
1682         return true;
1683 device_tag_fail:
1684         link->link_enc->funcs->destroy(&link->link_enc);
1685 link_enc_create_fail:
1686         if (link->panel_cntl != NULL)
1687                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1688 panel_cntl_create_fail:
1689         dal_ddc_service_destroy(&link->ddc);
1690 ddc_create_fail:
1691 create_fail:
1692
1693         if (link->hpd_gpio) {
1694                 dal_gpio_destroy_irq(&link->hpd_gpio);
1695                 link->hpd_gpio = NULL;
1696         }
1697
1698         DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1699         kfree(info);
1700
1701         return false;
1702 }
1703
1704 static bool dc_link_construct_dpia(struct dc_link *link,
1705                                    const struct link_init_data *init_params)
1706 {
1707         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1708         struct dc_context *dc_ctx = init_params->ctx;
1709
1710         DC_LOGGER_INIT(dc_ctx->logger);
1711
1712         /* Initialized dummy hpd and hpd rx */
1713         link->irq_source_hpd = DC_IRQ_SOURCE_USB4_DMUB_HPD;
1714         link->irq_source_hpd_rx = DC_IRQ_SOURCE_USB4_DMUB_HPDRX;
1715         link->link_status.dpcd_caps = &link->dpcd_caps;
1716
1717         link->dc = init_params->dc;
1718         link->ctx = dc_ctx;
1719         link->link_index = init_params->link_index;
1720
1721         memset(&link->preferred_training_settings, 0,
1722                sizeof(struct dc_link_training_overrides));
1723         memset(&link->preferred_link_setting, 0,
1724                sizeof(struct dc_link_settings));
1725
1726         /* Dummy Init for linkid */
1727         link->link_id.type = OBJECT_TYPE_CONNECTOR;
1728         link->link_id.id = CONNECTOR_ID_DISPLAY_PORT;
1729         link->is_internal_display = false;
1730         link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1731         LINK_INFO("Connector[%d] description:signal %d\n",
1732                   init_params->connector_index,
1733                   link->connector_signal);
1734
1735         link->ep_type = DISPLAY_ENDPOINT_USB4_DPIA;
1736
1737         /* TODO: Initialize link : funcs->link_init */
1738
1739         ddc_service_init_data.ctx = link->ctx;
1740         ddc_service_init_data.id = link->link_id;
1741         ddc_service_init_data.link = link;
1742         /* Set indicator for dpia link so that ddc won't be created */
1743         ddc_service_init_data.is_dpia_link = true;
1744
1745         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1746         if (!link->ddc) {
1747                 DC_ERROR("Failed to create ddc_service!\n");
1748                 goto ddc_create_fail;
1749         }
1750
1751         /* Set dpia port index : 0 to number of dpia ports */
1752         link->ddc_hw_inst = init_params->connector_index;
1753
1754         /* TODO: Create link encoder */
1755
1756         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1757
1758         return true;
1759
1760 ddc_create_fail:
1761         return false;
1762 }
1763
1764 static bool dc_link_construct(struct dc_link *link,
1765                               const struct link_init_data *init_params)
1766 {
1767         /* Handle dpia case */
1768         if (init_params->is_dpia_link)
1769                 return dc_link_construct_dpia(link, init_params);
1770         else
1771                 return dc_link_construct_legacy(link, init_params);
1772 }
1773 /*******************************************************************************
1774  * Public functions
1775  ******************************************************************************/
1776 struct dc_link *link_create(const struct link_init_data *init_params)
1777 {
1778         struct dc_link *link =
1779                         kzalloc(sizeof(*link), GFP_KERNEL);
1780
1781         if (NULL == link)
1782                 goto alloc_fail;
1783
1784         if (false == dc_link_construct(link, init_params))
1785                 goto construct_fail;
1786
1787         /*
1788          * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
1789          * since struct preferred_link_setting won't be reset after S3.
1790          */
1791         link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
1792
1793         return link;
1794
1795 construct_fail:
1796         kfree(link);
1797
1798 alloc_fail:
1799         return NULL;
1800 }
1801
1802 void link_destroy(struct dc_link **link)
1803 {
1804         dc_link_destruct(*link);
1805         kfree(*link);
1806         *link = NULL;
1807 }
1808
1809 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1810 {
1811         struct dc_stream_state *stream = pipe_ctx->stream;
1812
1813         if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1814                 struct dc_link *link = stream->link;
1815                 union down_spread_ctrl old_downspread;
1816                 union down_spread_ctrl new_downspread;
1817
1818                 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1819                                 &old_downspread.raw, sizeof(old_downspread));
1820
1821                 new_downspread.raw = old_downspread.raw;
1822
1823                 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1824                                 (stream->ignore_msa_timing_param) ? 1 : 0;
1825
1826                 if (new_downspread.raw != old_downspread.raw) {
1827                         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1828                                 &new_downspread.raw, sizeof(new_downspread));
1829                 }
1830
1831         } else {
1832                 dm_helpers_mst_enable_stream_features(stream);
1833         }
1834 }
1835
1836 static enum dc_status enable_link_dp(struct dc_state *state,
1837                                      struct pipe_ctx *pipe_ctx)
1838 {
1839         struct dc_stream_state *stream = pipe_ctx->stream;
1840         enum dc_status status;
1841         bool skip_video_pattern;
1842         struct dc_link *link = stream->link;
1843         struct dc_link_settings link_settings = {0};
1844         bool fec_enable;
1845         int i;
1846         bool apply_seamless_boot_optimization = false;
1847         uint32_t bl_oled_enable_delay = 50; // in ms
1848         const uint32_t post_oui_delay = 30; // 30ms
1849         /* Reduce link bandwidth between failed link training attempts. */
1850         bool do_fallback = false;
1851
1852         // check for seamless boot
1853         for (i = 0; i < state->stream_count; i++) {
1854                 if (state->streams[i]->apply_seamless_boot_optimization) {
1855                         apply_seamless_boot_optimization = true;
1856                         break;
1857                 }
1858         }
1859
1860         /* get link settings for video mode timing */
1861         decide_link_settings(stream, &link_settings);
1862
1863 #if defined(CONFIG_DRM_AMD_DC_DCN)
1864         if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING &&
1865                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
1866                 dp_enable_mst_on_sink(link, true);
1867         }
1868 #endif
1869
1870         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1871                 /*in case it is not on*/
1872                 link->dc->hwss.edp_power_control(link, true);
1873                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1874         }
1875
1876 #if defined(CONFIG_DRM_AMD_DC_DCN)
1877         if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING) {
1878                 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
1879         } else {
1880                 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1881                                 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1882                 if (state->clk_mgr && !apply_seamless_boot_optimization)
1883                         state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1884                                         state, false);
1885         }
1886 #else
1887         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1888                 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1889         if (state->clk_mgr && !apply_seamless_boot_optimization)
1890                 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1891                                                                                         state, false);
1892 #endif
1893
1894         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1895         dpcd_set_source_specific_data(link);
1896         if (link->dpcd_sink_ext_caps.raw != 0)
1897                 msleep(post_oui_delay);
1898
1899         skip_video_pattern = true;
1900
1901         if (link_settings.link_rate == LINK_RATE_LOW)
1902                 skip_video_pattern = false;
1903
1904         if (perform_link_training_with_retries(&link_settings,
1905                                                skip_video_pattern,
1906                                                LINK_TRAINING_ATTEMPTS,
1907                                                pipe_ctx,
1908                                                pipe_ctx->stream->signal,
1909                                                do_fallback)) {
1910                 link->cur_link_settings = link_settings;
1911                 status = DC_OK;
1912         } else {
1913                 status = DC_FAIL_DP_LINK_TRAINING;
1914         }
1915
1916         if (link->preferred_training_settings.fec_enable)
1917                 fec_enable = *link->preferred_training_settings.fec_enable;
1918         else
1919                 fec_enable = true;
1920
1921 #if defined(CONFIG_DRM_AMD_DC_DCN)
1922         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING)
1923                 dp_set_fec_enable(link, fec_enable);
1924 #else
1925         dp_set_fec_enable(link, fec_enable);
1926 #endif
1927
1928         // during mode set we do DP_SET_POWER off then on, aux writes are lost
1929         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
1930                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
1931                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
1932                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
1933                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
1934                         msleep(bl_oled_enable_delay);
1935                 dc_link_backlight_enable_aux(link, true);
1936         }
1937
1938         return status;
1939 }
1940
1941 static enum dc_status enable_link_edp(
1942                 struct dc_state *state,
1943                 struct pipe_ctx *pipe_ctx)
1944 {
1945         enum dc_status status;
1946
1947         status = enable_link_dp(state, pipe_ctx);
1948
1949         return status;
1950 }
1951
1952 static enum dc_status enable_link_dp_mst(
1953                 struct dc_state *state,
1954                 struct pipe_ctx *pipe_ctx)
1955 {
1956         struct dc_link *link = pipe_ctx->stream->link;
1957
1958         /* sink signal type after MST branch is MST. Multiple MST sinks
1959          * share one link. Link DP PHY is enable or training only once.
1960          */
1961         if (link->link_status.link_active)
1962                 return DC_OK;
1963
1964         /* clear payload table */
1965         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1966
1967         /* to make sure the pending down rep can be processed
1968          * before enabling the link
1969          */
1970         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1971
1972         /* set the sink to MST mode before enabling the link */
1973         dp_enable_mst_on_sink(link, true);
1974
1975         return enable_link_dp(state, pipe_ctx);
1976 }
1977
1978 void blank_all_dp_displays(struct dc *dc, bool hw_init)
1979 {
1980         unsigned int i, j, fe;
1981         uint8_t dpcd_power_state = '\0';
1982         enum dc_status status = DC_ERROR_UNEXPECTED;
1983
1984         for (i = 0; i < dc->link_count; i++) {
1985                 enum signal_type signal = dc->links[i]->connector_signal;
1986
1987                 if ((signal == SIGNAL_TYPE_EDP) ||
1988                         (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
1989                         if (hw_init && signal != SIGNAL_TYPE_EDP && dc->links[i]->priv != NULL) {
1990                                 /* DP 2.0 spec requires that we read LTTPR caps first */
1991                                 dp_retrieve_lttpr_cap(dc->links[i]);
1992                                 /* if any of the displays are lit up turn them off */
1993                                 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
1994                                                         &dpcd_power_state, sizeof(dpcd_power_state));
1995                         }
1996
1997                         if ((signal != SIGNAL_TYPE_EDP && status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) ||
1998                                         (!hw_init && dc->links[i]->link_enc &&
1999                                         dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc))) {
2000                                 if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
2001                                         fe = dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
2002                                         if (fe == ENGINE_ID_UNKNOWN)
2003                                                 continue;
2004
2005                                         for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
2006                                                 if (fe == dc->res_pool->stream_enc[j]->id) {
2007                                                         dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
2008                                                                         dc->res_pool->stream_enc[j]);
2009                                                         break;
2010                                                 }
2011                                         }
2012                                 }
2013
2014                                 if (!dc->links[i]->wa_flags.dp_keep_receiver_powered ||
2015                                         (hw_init && signal != SIGNAL_TYPE_EDP && dc->links[i]->priv != NULL))
2016                                         dp_receiver_power_ctrl(dc->links[i], false);
2017                         }
2018                 }
2019         }
2020
2021 }
2022
2023 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
2024                 enum engine_id eng_id,
2025                 struct ext_hdmi_settings *settings)
2026 {
2027         bool result = false;
2028         int i = 0;
2029         struct integrated_info *integrated_info =
2030                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
2031
2032         if (integrated_info == NULL)
2033                 return false;
2034
2035         /*
2036          * Get retimer settings from sbios for passing SI eye test for DCE11
2037          * The setting values are varied based on board revision and port id
2038          * Therefore the setting values of each ports is passed by sbios.
2039          */
2040
2041         // Check if current bios contains ext Hdmi settings
2042         if (integrated_info->gpu_cap_info & 0x20) {
2043                 switch (eng_id) {
2044                 case ENGINE_ID_DIGA:
2045                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
2046                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
2047                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
2048                         memmove(settings->reg_settings,
2049                                         integrated_info->dp0_ext_hdmi_reg_settings,
2050                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
2051                         memmove(settings->reg_settings_6g,
2052                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
2053                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
2054                         result = true;
2055                         break;
2056                 case ENGINE_ID_DIGB:
2057                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
2058                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
2059                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
2060                         memmove(settings->reg_settings,
2061                                         integrated_info->dp1_ext_hdmi_reg_settings,
2062                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
2063                         memmove(settings->reg_settings_6g,
2064                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
2065                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
2066                         result = true;
2067                         break;
2068                 case ENGINE_ID_DIGC:
2069                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
2070                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
2071                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
2072                         memmove(settings->reg_settings,
2073                                         integrated_info->dp2_ext_hdmi_reg_settings,
2074                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
2075                         memmove(settings->reg_settings_6g,
2076                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
2077                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
2078                         result = true;
2079                         break;
2080                 case ENGINE_ID_DIGD:
2081                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
2082                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
2083                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
2084                         memmove(settings->reg_settings,
2085                                         integrated_info->dp3_ext_hdmi_reg_settings,
2086                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
2087                         memmove(settings->reg_settings_6g,
2088                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
2089                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
2090                         result = true;
2091                         break;
2092                 default:
2093                         break;
2094                 }
2095
2096                 if (result == true) {
2097                         // Validate settings from bios integrated info table
2098                         if (settings->slv_addr == 0)
2099                                 return false;
2100                         if (settings->reg_num > 9)
2101                                 return false;
2102                         if (settings->reg_num_6g > 3)
2103                                 return false;
2104
2105                         for (i = 0; i < settings->reg_num; i++) {
2106                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
2107                                         return false;
2108                         }
2109
2110                         for (i = 0; i < settings->reg_num_6g; i++) {
2111                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
2112                                         return false;
2113                         }
2114                 }
2115         }
2116
2117         return result;
2118 }
2119
2120 static bool i2c_write(struct pipe_ctx *pipe_ctx,
2121                 uint8_t address, uint8_t *buffer, uint32_t length)
2122 {
2123         struct i2c_command cmd = {0};
2124         struct i2c_payload payload = {0};
2125
2126         memset(&payload, 0, sizeof(payload));
2127         memset(&cmd, 0, sizeof(cmd));
2128
2129         cmd.number_of_payloads = 1;
2130         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
2131         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
2132
2133         payload.address = address;
2134         payload.data = buffer;
2135         payload.length = length;
2136         payload.write = true;
2137         cmd.payloads = &payload;
2138
2139         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
2140                         pipe_ctx->stream->link, &cmd))
2141                 return true;
2142
2143         return false;
2144 }
2145
2146 static void write_i2c_retimer_setting(
2147                 struct pipe_ctx *pipe_ctx,
2148                 bool is_vga_mode,
2149                 bool is_over_340mhz,
2150                 struct ext_hdmi_settings *settings)
2151 {
2152         uint8_t slave_address = (settings->slv_addr >> 1);
2153         uint8_t buffer[2];
2154         const uint8_t apply_rx_tx_change = 0x4;
2155         uint8_t offset = 0xA;
2156         uint8_t value = 0;
2157         int i = 0;
2158         bool i2c_success = false;
2159         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2160
2161         memset(&buffer, 0, sizeof(buffer));
2162
2163         /* Start Ext-Hdmi programming*/
2164
2165         for (i = 0; i < settings->reg_num; i++) {
2166                 /* Apply 3G settings */
2167                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2168
2169                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
2170                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
2171                         i2c_success = i2c_write(pipe_ctx, slave_address,
2172                                                 buffer, sizeof(buffer));
2173                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2174                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2175                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2176
2177                         if (!i2c_success)
2178                                 goto i2c_write_fail;
2179
2180                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2181                          * needs to be set to 1 on every 0xA-0xC write.
2182                          */
2183                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
2184                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
2185                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
2186
2187                                 /* Query current value from offset 0xA */
2188                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
2189                                         value = settings->reg_settings[i].i2c_reg_val;
2190                                 else {
2191                                         i2c_success =
2192                                                 dal_ddc_service_query_ddc_data(
2193                                                 pipe_ctx->stream->link->ddc,
2194                                                 slave_address, &offset, 1, &value, 1);
2195                                         if (!i2c_success)
2196                                                 goto i2c_write_fail;
2197                                 }
2198
2199                                 buffer[0] = offset;
2200                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2201                                 buffer[1] = value | apply_rx_tx_change;
2202                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2203                                                 buffer, sizeof(buffer));
2204                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2205                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2206                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2207                                 if (!i2c_success)
2208                                         goto i2c_write_fail;
2209                         }
2210                 }
2211         }
2212
2213         /* Apply 3G settings */
2214         if (is_over_340mhz) {
2215                 for (i = 0; i < settings->reg_num_6g; i++) {
2216                         /* Apply 3G settings */
2217                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2218
2219                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2220                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2221                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2222                                                         buffer, sizeof(buffer));
2223                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2224                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2225                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2226
2227                                 if (!i2c_success)
2228                                         goto i2c_write_fail;
2229
2230                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2231                                  * needs to be set to 1 on every 0xA-0xC write.
2232                                  */
2233                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2234                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2235                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2236
2237                                         /* Query current value from offset 0xA */
2238                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2239                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
2240                                         else {
2241                                                 i2c_success =
2242                                                                 dal_ddc_service_query_ddc_data(
2243                                                                 pipe_ctx->stream->link->ddc,
2244                                                                 slave_address, &offset, 1, &value, 1);
2245                                                 if (!i2c_success)
2246                                                         goto i2c_write_fail;
2247                                         }
2248
2249                                         buffer[0] = offset;
2250                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
2251                                         buffer[1] = value | apply_rx_tx_change;
2252                                         i2c_success = i2c_write(pipe_ctx, slave_address,
2253                                                         buffer, sizeof(buffer));
2254                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2255                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2256                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2257                                         if (!i2c_success)
2258                                                 goto i2c_write_fail;
2259                                 }
2260                         }
2261                 }
2262         }
2263
2264         if (is_vga_mode) {
2265                 /* Program additional settings if using 640x480 resolution */
2266
2267                 /* Write offset 0xFF to 0x01 */
2268                 buffer[0] = 0xff;
2269                 buffer[1] = 0x01;
2270                 i2c_success = i2c_write(pipe_ctx, slave_address,
2271                                 buffer, sizeof(buffer));
2272                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2273                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2274                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2275                 if (!i2c_success)
2276                         goto i2c_write_fail;
2277
2278                 /* Write offset 0x00 to 0x23 */
2279                 buffer[0] = 0x00;
2280                 buffer[1] = 0x23;
2281                 i2c_success = i2c_write(pipe_ctx, slave_address,
2282                                 buffer, sizeof(buffer));
2283                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2284                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2285                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2286                 if (!i2c_success)
2287                         goto i2c_write_fail;
2288
2289                 /* Write offset 0xff to 0x00 */
2290                 buffer[0] = 0xff;
2291                 buffer[1] = 0x00;
2292                 i2c_success = i2c_write(pipe_ctx, slave_address,
2293                                 buffer, sizeof(buffer));
2294                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2295                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2296                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2297                 if (!i2c_success)
2298                         goto i2c_write_fail;
2299
2300         }
2301
2302         return;
2303
2304 i2c_write_fail:
2305         DC_LOG_DEBUG("Set retimer failed");
2306 }
2307
2308 static void write_i2c_default_retimer_setting(
2309                 struct pipe_ctx *pipe_ctx,
2310                 bool is_vga_mode,
2311                 bool is_over_340mhz)
2312 {
2313         uint8_t slave_address = (0xBA >> 1);
2314         uint8_t buffer[2];
2315         bool i2c_success = false;
2316         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2317
2318         memset(&buffer, 0, sizeof(buffer));
2319
2320         /* Program Slave Address for tuning single integrity */
2321         /* Write offset 0x0A to 0x13 */
2322         buffer[0] = 0x0A;
2323         buffer[1] = 0x13;
2324         i2c_success = i2c_write(pipe_ctx, slave_address,
2325                         buffer, sizeof(buffer));
2326         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2327                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2328                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2329         if (!i2c_success)
2330                 goto i2c_write_fail;
2331
2332         /* Write offset 0x0A to 0x17 */
2333         buffer[0] = 0x0A;
2334         buffer[1] = 0x17;
2335         i2c_success = i2c_write(pipe_ctx, slave_address,
2336                         buffer, sizeof(buffer));
2337         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2338                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2339                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2340         if (!i2c_success)
2341                 goto i2c_write_fail;
2342
2343         /* Write offset 0x0B to 0xDA or 0xD8 */
2344         buffer[0] = 0x0B;
2345         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2346         i2c_success = i2c_write(pipe_ctx, slave_address,
2347                         buffer, sizeof(buffer));
2348         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2349                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2350                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2351         if (!i2c_success)
2352                 goto i2c_write_fail;
2353
2354         /* Write offset 0x0A to 0x17 */
2355         buffer[0] = 0x0A;
2356         buffer[1] = 0x17;
2357         i2c_success = i2c_write(pipe_ctx, slave_address,
2358                         buffer, sizeof(buffer));
2359         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2360                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2361                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2362         if (!i2c_success)
2363                 goto i2c_write_fail;
2364
2365         /* Write offset 0x0C to 0x1D or 0x91 */
2366         buffer[0] = 0x0C;
2367         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2368         i2c_success = i2c_write(pipe_ctx, slave_address,
2369                         buffer, sizeof(buffer));
2370         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2371                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2372                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2373         if (!i2c_success)
2374                 goto i2c_write_fail;
2375
2376         /* Write offset 0x0A to 0x17 */
2377         buffer[0] = 0x0A;
2378         buffer[1] = 0x17;
2379         i2c_success = i2c_write(pipe_ctx, slave_address,
2380                         buffer, sizeof(buffer));
2381         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2382                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2383                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2384         if (!i2c_success)
2385                 goto i2c_write_fail;
2386
2387
2388         if (is_vga_mode) {
2389                 /* Program additional settings if using 640x480 resolution */
2390
2391                 /* Write offset 0xFF to 0x01 */
2392                 buffer[0] = 0xff;
2393                 buffer[1] = 0x01;
2394                 i2c_success = i2c_write(pipe_ctx, slave_address,
2395                                 buffer, sizeof(buffer));
2396                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2397                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2398                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2399                 if (!i2c_success)
2400                         goto i2c_write_fail;
2401
2402                 /* Write offset 0x00 to 0x23 */
2403                 buffer[0] = 0x00;
2404                 buffer[1] = 0x23;
2405                 i2c_success = i2c_write(pipe_ctx, slave_address,
2406                                 buffer, sizeof(buffer));
2407                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2408                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2409                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2410                 if (!i2c_success)
2411                         goto i2c_write_fail;
2412
2413                 /* Write offset 0xff to 0x00 */
2414                 buffer[0] = 0xff;
2415                 buffer[1] = 0x00;
2416                 i2c_success = i2c_write(pipe_ctx, slave_address,
2417                                 buffer, sizeof(buffer));
2418                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2419                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2420                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2421                 if (!i2c_success)
2422                         goto i2c_write_fail;
2423         }
2424
2425         return;
2426
2427 i2c_write_fail:
2428         DC_LOG_DEBUG("Set default retimer failed");
2429 }
2430
2431 static void write_i2c_redriver_setting(
2432                 struct pipe_ctx *pipe_ctx,
2433                 bool is_over_340mhz)
2434 {
2435         uint8_t slave_address = (0xF0 >> 1);
2436         uint8_t buffer[16];
2437         bool i2c_success = false;
2438         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2439
2440         memset(&buffer, 0, sizeof(buffer));
2441
2442         // Program Slave Address for tuning single integrity
2443         buffer[3] = 0x4E;
2444         buffer[4] = 0x4E;
2445         buffer[5] = 0x4E;
2446         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2447
2448         i2c_success = i2c_write(pipe_ctx, slave_address,
2449                                         buffer, sizeof(buffer));
2450         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2451                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2452                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2453                 i2c_success = %d\n",
2454                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2455
2456         if (!i2c_success)
2457                 DC_LOG_DEBUG("Set redriver failed");
2458 }
2459
2460 static void disable_link(struct dc_link *link, enum signal_type signal)
2461 {
2462         /*
2463          * TODO: implement call for dp_set_hw_test_pattern
2464          * it is needed for compliance testing
2465          */
2466
2467         /* Here we need to specify that encoder output settings
2468          * need to be calculated as for the set mode,
2469          * it will lead to querying dynamic link capabilities
2470          * which should be done before enable output
2471          */
2472
2473         if (dc_is_dp_signal(signal)) {
2474                 /* SST DP, eDP */
2475 #if defined(CONFIG_DRM_AMD_DC_DCN)
2476                 struct dc_link_settings link_settings = link->cur_link_settings;
2477 #endif
2478                 if (dc_is_dp_sst_signal(signal))
2479                         dp_disable_link_phy(link, signal);
2480                 else
2481                         dp_disable_link_phy_mst(link, signal);
2482
2483                 if (dc_is_dp_sst_signal(signal) ||
2484                                 link->mst_stream_alloc_table.stream_count == 0) {
2485 #if defined(CONFIG_DRM_AMD_DC_DCN)
2486                         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
2487                                 dp_set_fec_enable(link, false);
2488                                 dp_set_fec_ready(link, false);
2489                         }
2490 #else
2491                         dp_set_fec_enable(link, false);
2492                         dp_set_fec_ready(link, false);
2493 #endif
2494                 }
2495         } else {
2496                 if (signal != SIGNAL_TYPE_VIRTUAL)
2497                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2498         }
2499
2500         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2501                 /* MST disable link only when no stream use the link */
2502                 if (link->mst_stream_alloc_table.stream_count <= 0)
2503                         link->link_status.link_active = false;
2504         } else {
2505                 link->link_status.link_active = false;
2506         }
2507 }
2508
2509 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2510 {
2511         struct dc_stream_state *stream = pipe_ctx->stream;
2512         struct dc_link *link = stream->link;
2513         enum dc_color_depth display_color_depth;
2514         enum engine_id eng_id;
2515         struct ext_hdmi_settings settings = {0};
2516         bool is_over_340mhz = false;
2517         bool is_vga_mode = (stream->timing.h_addressable == 640)
2518                         && (stream->timing.v_addressable == 480);
2519
2520         if (stream->phy_pix_clk == 0)
2521                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2522         if (stream->phy_pix_clk > 340000)
2523                 is_over_340mhz = true;
2524
2525         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2526                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2527                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2528                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2529                         /* DP159, Retimer settings */
2530                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2531
2532                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2533                                 write_i2c_retimer_setting(pipe_ctx,
2534                                                 is_vga_mode, is_over_340mhz, &settings);
2535                         } else {
2536                                 write_i2c_default_retimer_setting(pipe_ctx,
2537                                                 is_vga_mode, is_over_340mhz);
2538                         }
2539                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2540                         /* PI3EQX1204, Redriver settings */
2541                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2542                 }
2543         }
2544
2545         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2546                 dal_ddc_service_write_scdc_data(
2547                         stream->link->ddc,
2548                         stream->phy_pix_clk,
2549                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2550
2551         memset(&stream->link->cur_link_settings, 0,
2552                         sizeof(struct dc_link_settings));
2553
2554         display_color_depth = stream->timing.display_color_depth;
2555         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2556                 display_color_depth = COLOR_DEPTH_888;
2557
2558         link->link_enc->funcs->enable_tmds_output(
2559                         link->link_enc,
2560                         pipe_ctx->clock_source->id,
2561                         display_color_depth,
2562                         pipe_ctx->stream->signal,
2563                         stream->phy_pix_clk);
2564
2565         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2566                 dal_ddc_service_read_scdc_data(link->ddc);
2567 }
2568
2569 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2570 {
2571         struct dc_stream_state *stream = pipe_ctx->stream;
2572         struct dc_link *link = stream->link;
2573
2574         if (stream->phy_pix_clk == 0)
2575                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2576
2577         memset(&stream->link->cur_link_settings, 0,
2578                         sizeof(struct dc_link_settings));
2579
2580         link->link_enc->funcs->enable_lvds_output(
2581                         link->link_enc,
2582                         pipe_ctx->clock_source->id,
2583                         stream->phy_pix_clk);
2584
2585 }
2586
2587 /****************************enable_link***********************************/
2588 static enum dc_status enable_link(
2589                 struct dc_state *state,
2590                 struct pipe_ctx *pipe_ctx)
2591 {
2592         enum dc_status status = DC_ERROR_UNEXPECTED;
2593         struct dc_stream_state *stream = pipe_ctx->stream;
2594         struct dc_link *link = stream->link;
2595
2596         /* There's some scenarios where driver is unloaded with display
2597          * still enabled. When driver is reloaded, it may cause a display
2598          * to not light up if there is a mismatch between old and new
2599          * link settings. Need to call disable first before enabling at
2600          * new link settings.
2601          */
2602         if (link->link_status.link_active) {
2603                 disable_link(link, pipe_ctx->stream->signal);
2604         }
2605
2606         switch (pipe_ctx->stream->signal) {
2607         case SIGNAL_TYPE_DISPLAY_PORT:
2608                 status = enable_link_dp(state, pipe_ctx);
2609                 break;
2610         case SIGNAL_TYPE_EDP:
2611                 status = enable_link_edp(state, pipe_ctx);
2612                 break;
2613         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2614                 status = enable_link_dp_mst(state, pipe_ctx);
2615                 msleep(200);
2616                 break;
2617         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2618         case SIGNAL_TYPE_DVI_DUAL_LINK:
2619         case SIGNAL_TYPE_HDMI_TYPE_A:
2620                 enable_link_hdmi(pipe_ctx);
2621                 status = DC_OK;
2622                 break;
2623         case SIGNAL_TYPE_LVDS:
2624                 enable_link_lvds(pipe_ctx);
2625                 status = DC_OK;
2626                 break;
2627         case SIGNAL_TYPE_VIRTUAL:
2628                 status = DC_OK;
2629                 break;
2630         default:
2631                 break;
2632         }
2633
2634         if (status == DC_OK)
2635                 pipe_ctx->stream->link->link_status.link_active = true;
2636
2637         return status;
2638 }
2639
2640 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2641 {
2642
2643         uint32_t pxl_clk = timing->pix_clk_100hz;
2644
2645         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2646                 pxl_clk /= 2;
2647         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2648                 pxl_clk = pxl_clk * 2 / 3;
2649
2650         if (timing->display_color_depth == COLOR_DEPTH_101010)
2651                 pxl_clk = pxl_clk * 10 / 8;
2652         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2653                 pxl_clk = pxl_clk * 12 / 8;
2654
2655         return pxl_clk;
2656 }
2657
2658 static bool dp_active_dongle_validate_timing(
2659                 const struct dc_crtc_timing *timing,
2660                 const struct dpcd_caps *dpcd_caps)
2661 {
2662         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2663
2664         switch (dpcd_caps->dongle_type) {
2665         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2666         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2667         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2668                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2669                         return true;
2670                 else
2671                         return false;
2672         default:
2673                 break;
2674         }
2675
2676 #if defined(CONFIG_DRM_AMD_DC_DCN)
2677         if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
2678                         dongle_caps->extendedCapValid == true) {
2679 #else
2680         if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2681                 dongle_caps->extendedCapValid == false)
2682                 return true;
2683 #endif
2684
2685         /* Check Pixel Encoding */
2686         switch (timing->pixel_encoding) {
2687         case PIXEL_ENCODING_RGB:
2688         case PIXEL_ENCODING_YCBCR444:
2689                 break;
2690         case PIXEL_ENCODING_YCBCR422:
2691                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2692                         return false;
2693                 break;
2694         case PIXEL_ENCODING_YCBCR420:
2695                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2696                         return false;
2697                 break;
2698         default:
2699                 /* Invalid Pixel Encoding*/
2700                 return false;
2701         }
2702
2703         switch (timing->display_color_depth) {
2704         case COLOR_DEPTH_666:
2705         case COLOR_DEPTH_888:
2706                 /*888 and 666 should always be supported*/
2707                 break;
2708         case COLOR_DEPTH_101010:
2709                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2710                         return false;
2711                 break;
2712         case COLOR_DEPTH_121212:
2713                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2714                         return false;
2715                 break;
2716         case COLOR_DEPTH_141414:
2717         case COLOR_DEPTH_161616:
2718         default:
2719                 /* These color depths are currently not supported */
2720                 return false;
2721         }
2722
2723         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2724                 return false;
2725
2726 #if defined(CONFIG_DRM_AMD_DC_DCN)
2727         }
2728
2729         if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
2730                         dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
2731                         dongle_caps->dfp_cap_ext.supported) {
2732
2733                 if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
2734                         return false;
2735
2736                 if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
2737                         return false;
2738
2739                 if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
2740                         return false;
2741
2742                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
2743                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2744                                 return false;
2745                         if (timing->display_color_depth == COLOR_DEPTH_666 &&
2746                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
2747                                 return false;
2748                         else if (timing->display_color_depth == COLOR_DEPTH_888 &&
2749                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
2750                                 return false;
2751                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2752                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
2753                                 return false;
2754                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2755                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
2756                                 return false;
2757                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2758                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
2759                                 return false;
2760                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
2761                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2762                                 return false;
2763                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2764                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
2765                                 return false;
2766                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2767                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
2768                                 return false;
2769                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2770                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
2771                                 return false;
2772                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2773                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
2774                                 return false;
2775                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
2776                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2777                                 return false;
2778                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2779                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
2780                                 return false;
2781                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2782                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
2783                                 return false;
2784                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2785                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
2786                                 return false;
2787                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2788                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
2789                                 return false;
2790                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2791                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2792                                 return false;
2793                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2794                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
2795                                 return false;
2796                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2797                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
2798                                 return false;
2799                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2800                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
2801                                 return false;
2802                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2803                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
2804                                 return false;
2805                 }
2806         }
2807 #endif
2808
2809         return true;
2810 }
2811
2812 enum dc_status dc_link_validate_mode_timing(
2813                 const struct dc_stream_state *stream,
2814                 struct dc_link *link,
2815                 const struct dc_crtc_timing *timing)
2816 {
2817         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2818         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2819
2820         /* A hack to avoid failing any modes for EDID override feature on
2821          * topology change such as lower quality cable for DP or different dongle
2822          */
2823         if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2824                 return DC_OK;
2825
2826         /* Passive Dongle */
2827         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2828                 return DC_EXCEED_DONGLE_CAP;
2829
2830         /* Active Dongle*/
2831         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2832                 return DC_EXCEED_DONGLE_CAP;
2833
2834         switch (stream->signal) {
2835         case SIGNAL_TYPE_EDP:
2836         case SIGNAL_TYPE_DISPLAY_PORT:
2837                 if (!dp_validate_mode_timing(
2838                                 link,
2839                                 timing))
2840                         return DC_NO_DP_LINK_BANDWIDTH;
2841                 break;
2842
2843         default:
2844                 break;
2845         }
2846
2847         return DC_OK;
2848 }
2849
2850 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2851 {
2852         int i;
2853         struct dc *dc = NULL;
2854         struct abm *abm = NULL;
2855
2856         if (!link || !link->ctx)
2857                 return NULL;
2858
2859         dc = link->ctx->dc;
2860
2861         for (i = 0; i < MAX_PIPES; i++) {
2862                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2863                 struct dc_stream_state *stream = pipe_ctx.stream;
2864
2865                 if (stream && stream->link == link) {
2866                         abm = pipe_ctx.stream_res.abm;
2867                         break;
2868                 }
2869         }
2870         return abm;
2871 }
2872
2873 int dc_link_get_backlight_level(const struct dc_link *link)
2874 {
2875         struct abm *abm = get_abm_from_stream_res(link);
2876         struct panel_cntl *panel_cntl = link->panel_cntl;
2877         struct dc  *dc = link->ctx->dc;
2878         struct dmcu *dmcu = dc->res_pool->dmcu;
2879         bool fw_set_brightness = true;
2880
2881         if (dmcu)
2882                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2883
2884         if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
2885                 return panel_cntl->funcs->get_current_backlight(panel_cntl);
2886         else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
2887                 return (int) abm->funcs->get_current_backlight(abm);
2888         else
2889                 return DC_ERROR_UNEXPECTED;
2890 }
2891
2892 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
2893 {
2894         struct abm *abm = get_abm_from_stream_res(link);
2895
2896         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
2897                 return DC_ERROR_UNEXPECTED;
2898
2899         return (int) abm->funcs->get_target_backlight(abm);
2900 }
2901
2902 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
2903 {
2904         int i;
2905         struct dc *dc = link->ctx->dc;
2906         struct pipe_ctx *pipe_ctx = NULL;
2907
2908         for (i = 0; i < MAX_PIPES; i++) {
2909                 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
2910                         if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
2911                                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2912                                 break;
2913                         }
2914                 }
2915         }
2916
2917         return pipe_ctx;
2918 }
2919
2920 bool dc_link_set_backlight_level(const struct dc_link *link,
2921                 uint32_t backlight_pwm_u16_16,
2922                 uint32_t frame_ramp)
2923 {
2924         struct dc  *dc = link->ctx->dc;
2925
2926         DC_LOGGER_INIT(link->ctx->logger);
2927         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2928                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2929
2930         if (dc_is_embedded_signal(link->connector_signal)) {
2931                 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
2932
2933                 if (pipe_ctx) {
2934                         /* Disable brightness ramping when the display is blanked
2935                          * as it can hang the DMCU
2936                          */
2937                         if (pipe_ctx->plane_state == NULL)
2938                                 frame_ramp = 0;
2939                 } else {
2940                         return false;
2941                 }
2942
2943                 dc->hwss.set_backlight_level(
2944                                 pipe_ctx,
2945                                 backlight_pwm_u16_16,
2946                                 frame_ramp);
2947         }
2948         return true;
2949 }
2950
2951 bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
2952                 bool wait, bool force_static)
2953 {
2954         struct dc  *dc = link->ctx->dc;
2955         struct dmcu *dmcu = dc->res_pool->dmcu;
2956         struct dmub_psr *psr = dc->res_pool->psr;
2957         unsigned int panel_inst;
2958
2959         if (psr == NULL && force_static)
2960                 return false;
2961
2962         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2963                 return false;
2964
2965         link->psr_settings.psr_allow_active = allow_active;
2966 #if defined(CONFIG_DRM_AMD_DC_DCN)
2967         if (!allow_active)
2968                 dc_z10_restore(dc);
2969 #endif
2970
2971         if (psr != NULL && link->psr_settings.psr_feature_enabled) {
2972                 if (force_static && psr->funcs->psr_force_static)
2973                         psr->funcs->psr_force_static(psr, panel_inst);
2974                 psr->funcs->psr_enable(psr, allow_active, wait, panel_inst);
2975         } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
2976                 dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
2977         else
2978                 return false;
2979
2980         return true;
2981 }
2982
2983 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
2984 {
2985         struct dc  *dc = link->ctx->dc;
2986         struct dmcu *dmcu = dc->res_pool->dmcu;
2987         struct dmub_psr *psr = dc->res_pool->psr;
2988         unsigned int panel_inst;
2989
2990         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2991                 return false;
2992
2993         if (psr != NULL && link->psr_settings.psr_feature_enabled)
2994                 psr->funcs->psr_get_state(psr, state, panel_inst);
2995         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
2996                 dmcu->funcs->get_psr_state(dmcu, state);
2997
2998         return true;
2999 }
3000
3001 static inline enum physical_phy_id
3002 transmitter_to_phy_id(enum transmitter transmitter_value)
3003 {
3004         switch (transmitter_value) {
3005         case TRANSMITTER_UNIPHY_A:
3006                 return PHYLD_0;
3007         case TRANSMITTER_UNIPHY_B:
3008                 return PHYLD_1;
3009         case TRANSMITTER_UNIPHY_C:
3010                 return PHYLD_2;
3011         case TRANSMITTER_UNIPHY_D:
3012                 return PHYLD_3;
3013         case TRANSMITTER_UNIPHY_E:
3014                 return PHYLD_4;
3015         case TRANSMITTER_UNIPHY_F:
3016                 return PHYLD_5;
3017         case TRANSMITTER_NUTMEG_CRT:
3018                 return PHYLD_6;
3019         case TRANSMITTER_TRAVIS_CRT:
3020                 return PHYLD_7;
3021         case TRANSMITTER_TRAVIS_LCD:
3022                 return PHYLD_8;
3023         case TRANSMITTER_UNIPHY_G:
3024                 return PHYLD_9;
3025         case TRANSMITTER_COUNT:
3026                 return PHYLD_COUNT;
3027         case TRANSMITTER_UNKNOWN:
3028                 return PHYLD_UNKNOWN;
3029         default:
3030                 WARN_ONCE(1, "Unknown transmitter value %d\n",
3031                           transmitter_value);
3032                 return PHYLD_UNKNOWN;
3033         }
3034 }
3035
3036 bool dc_link_setup_psr(struct dc_link *link,
3037                 const struct dc_stream_state *stream, struct psr_config *psr_config,
3038                 struct psr_context *psr_context)
3039 {
3040         struct dc *dc;
3041         struct dmcu *dmcu;
3042         struct dmub_psr *psr;
3043         int i;
3044         unsigned int panel_inst;
3045         /* updateSinkPsrDpcdConfig*/
3046         union dpcd_psr_configuration psr_configuration;
3047
3048         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
3049
3050         if (!link)
3051                 return false;
3052
3053         dc = link->ctx->dc;
3054         dmcu = dc->res_pool->dmcu;
3055         psr = dc->res_pool->psr;
3056
3057         if (!dmcu && !psr)
3058                 return false;
3059
3060         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3061                 return false;
3062
3063
3064         memset(&psr_configuration, 0, sizeof(psr_configuration));
3065
3066         psr_configuration.bits.ENABLE                    = 1;
3067         psr_configuration.bits.CRC_VERIFICATION          = 1;
3068         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
3069                         psr_config->psr_frame_capture_indication_req;
3070
3071         /* Check for PSR v2*/
3072         if (psr_config->psr_version == 0x2) {
3073                 /* For PSR v2 selective update.
3074                  * Indicates whether sink should start capturing
3075                  * immediately following active scan line,
3076                  * or starting with the 2nd active scan line.
3077                  */
3078                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
3079                 /*For PSR v2, determines whether Sink should generate
3080                  * IRQ_HPD when CRC mismatch is detected.
3081                  */
3082                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
3083         }
3084
3085         dm_helpers_dp_write_dpcd(
3086                 link->ctx,
3087                 link,
3088                 368,
3089                 &psr_configuration.raw,
3090                 sizeof(psr_configuration.raw));
3091
3092         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
3093         psr_context->transmitterId = link->link_enc->transmitter;
3094         psr_context->engineId = link->link_enc->preferred_engine;
3095
3096         for (i = 0; i < MAX_PIPES; i++) {
3097                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
3098                                 == stream) {
3099                         /* dmcu -1 for all controller id values,
3100                          * therefore +1 here
3101                          */
3102                         psr_context->controllerId =
3103                                 dc->current_state->res_ctx.
3104                                 pipe_ctx[i].stream_res.tg->inst + 1;
3105                         break;
3106                 }
3107         }
3108
3109         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
3110         psr_context->phyType = PHY_TYPE_UNIPHY;
3111         /*PhyId is associated with the transmitter id*/
3112         psr_context->smuPhyId =
3113                 transmitter_to_phy_id(link->link_enc->transmitter);
3114
3115         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
3116         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
3117                                         timing.pix_clk_100hz * 100),
3118                                         stream->timing.v_total),
3119                                         stream->timing.h_total);
3120
3121         psr_context->psrSupportedDisplayConfig = true;
3122         psr_context->psrExitLinkTrainingRequired =
3123                 psr_config->psr_exit_link_training_required;
3124         psr_context->sdpTransmitLineNumDeadline =
3125                 psr_config->psr_sdp_transmit_line_num_deadline;
3126         psr_context->psrFrameCaptureIndicationReq =
3127                 psr_config->psr_frame_capture_indication_req;
3128
3129         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
3130
3131         psr_context->numberOfControllers =
3132                         link->dc->res_pool->timing_generator_count;
3133
3134         psr_context->rfb_update_auto_en = true;
3135
3136         /* 2 frames before enter PSR. */
3137         psr_context->timehyst_frames = 2;
3138         /* half a frame
3139          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
3140          */
3141         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
3142         psr_context->aux_repeats = 10;
3143
3144         psr_context->psr_level.u32all = 0;
3145
3146         /*skip power down the single pipe since it blocks the cstate*/
3147 #if defined(CONFIG_DRM_AMD_DC_DCN)
3148         if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
3149                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3150                 if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10)
3151                         psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
3152         }
3153 #else
3154         if (link->ctx->asic_id.chip_family >= FAMILY_RV)
3155                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3156 #endif
3157
3158         /* SMU will perform additional powerdown sequence.
3159          * For unsupported ASICs, set psr_level flag to skip PSR
3160          *  static screen notification to SMU.
3161          *  (Always set for DAL2, did not check ASIC)
3162          */
3163         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
3164         psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
3165
3166         /* Complete PSR entry before aborting to prevent intermittent
3167          * freezes on certain eDPs
3168          */
3169         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
3170
3171         /* Controls additional delay after remote frame capture before
3172          * continuing power down, default = 0
3173          */
3174         psr_context->frame_delay = 0;
3175
3176         if (psr)
3177                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
3178                         link, psr_context, panel_inst);
3179         else
3180                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
3181
3182         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
3183          * should not happen since firmware should be running at this point
3184          */
3185         if (link->psr_settings.psr_feature_enabled == 0)
3186                 ASSERT(0);
3187
3188         return true;
3189
3190 }
3191
3192 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
3193 {
3194         struct dc  *dc = link->ctx->dc;
3195         struct dmub_psr *psr = dc->res_pool->psr;
3196         unsigned int panel_inst;
3197
3198         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3199                 return;
3200
3201         /* PSR residency measurements only supported on DMCUB */
3202         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3203                 psr->funcs->psr_get_residency(psr, residency, panel_inst);
3204         else
3205                 *residency = 0;
3206 }
3207
3208 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
3209 {
3210         return &link->link_status;
3211 }
3212
3213 void core_link_resume(struct dc_link *link)
3214 {
3215         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
3216                 program_hpd_filter(link);
3217 }
3218
3219 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
3220 {
3221         struct fixed31_32 mbytes_per_sec;
3222         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
3223                         &stream->link->cur_link_settings);
3224         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
3225
3226         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
3227
3228         return dc_fixpt_div_int(mbytes_per_sec, 54);
3229 }
3230
3231 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
3232 {
3233         struct fixed31_32 peak_kbps;
3234         uint32_t numerator = 0;
3235         uint32_t denominator = 1;
3236
3237         /*
3238          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
3239          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
3240          * common multiplier to render an integer PBN for all link rate/lane
3241          * counts combinations
3242          * calculate
3243          * peak_kbps *= (1006/1000)
3244          * peak_kbps *= (64/54)
3245          * peak_kbps *= 8    convert to bytes
3246          */
3247
3248         numerator = 64 * PEAK_FACTOR_X1000;
3249         denominator = 54 * 8 * 1000 * 1000;
3250         kbps *= numerator;
3251         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
3252
3253         return peak_kbps;
3254 }
3255
3256 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
3257 {
3258         uint64_t kbps;
3259
3260         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
3261         return get_pbn_from_bw_in_kbps(kbps);
3262 }
3263
3264 static void update_mst_stream_alloc_table(
3265         struct dc_link *link,
3266         struct stream_encoder *stream_enc,
3267         const struct dp_mst_stream_allocation_table *proposed_table)
3268 {
3269         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
3270                         { 0 } };
3271         struct link_mst_stream_allocation *dc_alloc;
3272
3273         int i;
3274         int j;
3275
3276         /* if DRM proposed_table has more than one new payload */
3277         ASSERT(proposed_table->stream_count -
3278                         link->mst_stream_alloc_table.stream_count < 2);
3279
3280         /* copy proposed_table to link, add stream encoder */
3281         for (i = 0; i < proposed_table->stream_count; i++) {
3282
3283                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
3284                         dc_alloc =
3285                         &link->mst_stream_alloc_table.stream_allocations[j];
3286
3287                         if (dc_alloc->vcp_id ==
3288                                 proposed_table->stream_allocations[i].vcp_id) {
3289
3290                                 work_table[i] = *dc_alloc;
3291                                 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
3292                                 break; /* exit j loop */
3293                         }
3294                 }
3295
3296                 /* new vcp_id */
3297                 if (j == link->mst_stream_alloc_table.stream_count) {
3298                         work_table[i].vcp_id =
3299                                 proposed_table->stream_allocations[i].vcp_id;
3300                         work_table[i].slot_count =
3301                                 proposed_table->stream_allocations[i].slot_count;
3302                         work_table[i].stream_enc = stream_enc;
3303                 }
3304         }
3305
3306         /* update link->mst_stream_alloc_table with work_table */
3307         link->mst_stream_alloc_table.stream_count =
3308                         proposed_table->stream_count;
3309         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
3310                 link->mst_stream_alloc_table.stream_allocations[i] =
3311                                 work_table[i];
3312 }
3313 #if defined(CONFIG_DRM_AMD_DC_DCN)
3314 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
3315 {
3316         const uint32_t VCP_Y_PRECISION = 1000;
3317         uint64_t vcp_x, vcp_y;
3318
3319         // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
3320         avg_time_slots_per_mtp = dc_fixpt_add(
3321                         avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));
3322
3323         vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
3324         vcp_y = dc_fixpt_floor(
3325                         dc_fixpt_mul_int(
3326                                 dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
3327                                 VCP_Y_PRECISION));
3328
3329         if (link->type == dc_connection_mst_branch)
3330                 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
3331                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3332         else
3333                 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
3334                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3335 }
3336
3337 /*
3338  * Payload allocation/deallocation for SST introduced in DP2.0
3339  */
3340 enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx, bool allocate)
3341 {
3342         struct dc_stream_state *stream = pipe_ctx->stream;
3343         struct dc_link *link = stream->link;
3344         struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3345         struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3346         struct link_mst_stream_allocation_table proposed_table = {0};
3347         struct fixed31_32 avg_time_slots_per_mtp;
3348         DC_LOGGER_INIT(link->ctx->logger);
3349
3350         /* slot X.Y for SST payload deallocate */
3351         if (!allocate) {
3352                 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3353
3354                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3355
3356                 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3357                                 hpo_dp_link_encoder,
3358                                 hpo_dp_stream_encoder->inst,
3359                                 avg_time_slots_per_mtp);
3360         }
3361
3362         /* calculate VC payload and update branch with new payload allocation table*/
3363         if (!dpcd_write_128b_132b_sst_payload_allocation_table(
3364                         stream,
3365                         link,
3366                         &proposed_table,
3367                         allocate)) {
3368                 DC_LOG_ERROR("SST Update Payload: Failed to update "
3369                                                 "allocation table for "
3370                                                 "pipe idx: %d\n",
3371                                                 pipe_ctx->pipe_idx);
3372         }
3373
3374         proposed_table.stream_allocations[0].hpo_dp_stream_enc = hpo_dp_stream_encoder;
3375
3376         ASSERT(proposed_table.stream_count == 1);
3377
3378         //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id
3379         DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p      "
3380                 "vcp_id: %d      "
3381                 "slot_count: %d\n",
3382                 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc,
3383                 proposed_table.stream_allocations[0].vcp_id,
3384                 proposed_table.stream_allocations[0].slot_count);
3385
3386         /* program DP source TX for payload */
3387         hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3388                         hpo_dp_link_encoder,
3389                         &proposed_table);
3390
3391         /* poll for ACT handled */
3392         if (!dpcd_poll_for_allocation_change_trigger(link)) {
3393                 // Failures will result in blackscreen and errors logged
3394                 BREAK_TO_DEBUGGER();
3395         }
3396
3397         /* slot X.Y for SST payload allocate */
3398         if (allocate) {
3399                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
3400
3401                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3402
3403                 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3404                                 hpo_dp_link_encoder,
3405                                 hpo_dp_stream_encoder->inst,
3406                                 avg_time_slots_per_mtp);
3407         }
3408
3409         /* Always return DC_OK.
3410          * If part of sequence fails, log failure(s) and show blackscreen
3411          */
3412         return DC_OK;
3413 }
3414 #endif
3415
3416 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
3417  * because stream_encoder is not exposed to dm
3418  */
3419 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3420 {
3421         struct dc_stream_state *stream = pipe_ctx->stream;
3422         struct dc_link *link = stream->link;
3423         struct link_encoder *link_encoder = NULL;
3424         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3425         struct dp_mst_stream_allocation_table proposed_table = {0};
3426         struct fixed31_32 avg_time_slots_per_mtp;
3427         struct fixed31_32 pbn;
3428         struct fixed31_32 pbn_per_slot;
3429         uint8_t i;
3430         enum act_return_status ret;
3431         DC_LOGGER_INIT(link->ctx->logger);
3432
3433         /* Link encoder may have been dynamically assigned to non-physical display endpoint. */
3434         if (link->ep_type == DISPLAY_ENDPOINT_PHY)
3435                 link_encoder = link->link_enc;
3436         else if (link->dc->res_pool->funcs->link_encs_assign)
3437                 link_encoder = link_enc_cfg_get_link_enc_used_by_stream(pipe_ctx->stream->ctx->dc, stream);
3438         ASSERT(link_encoder);
3439
3440         /* enable_link_dp_mst already check link->enabled_stream_count
3441          * and stream is in link->stream[]. This is called during set mode,
3442          * stream_enc is available.
3443          */
3444
3445         /* get calculate VC payload for stream: stream_alloc */
3446         if (dm_helpers_dp_mst_write_payload_allocation_table(
3447                 stream->ctx,
3448                 stream,
3449                 &proposed_table,
3450                 true)) {
3451                 update_mst_stream_alloc_table(
3452                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3453         }
3454         else
3455                 DC_LOG_WARNING("Failed to update"
3456                                 "MST allocation table for"
3457                                 "pipe idx:%d\n",
3458                                 pipe_ctx->pipe_idx);
3459
3460         DC_LOG_MST("%s  "
3461                         "stream_count: %d: \n ",
3462                         __func__,
3463                         link->mst_stream_alloc_table.stream_count);
3464
3465         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3466                 DC_LOG_MST("stream_enc[%d]: %p      "
3467                 "stream[%d].vcp_id: %d      "
3468                 "stream[%d].slot_count: %d\n",
3469                 i,
3470                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3471                 i,
3472                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3473                 i,
3474                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3475         }
3476
3477         ASSERT(proposed_table.stream_count > 0);
3478
3479         /* program DP source TX for payload */
3480         link_encoder->funcs->update_mst_stream_allocation_table(
3481                 link_encoder,
3482                 &link->mst_stream_alloc_table);
3483
3484         /* send down message */
3485         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3486                         stream->ctx,
3487                         stream);
3488
3489         if (ret != ACT_LINK_LOST) {
3490                 dm_helpers_dp_mst_send_payload_allocation(
3491                                 stream->ctx,
3492                                 stream,
3493                                 true);
3494         }
3495
3496         /* slot X.Y for only current stream */
3497         pbn_per_slot = get_pbn_per_slot(stream);
3498         if (pbn_per_slot.value == 0) {
3499                 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3500                 return DC_UNSUPPORTED_VALUE;
3501         }
3502         pbn = get_pbn_from_timing(pipe_ctx);
3503         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3504
3505         stream_encoder->funcs->set_throttled_vcp_size(
3506                 stream_encoder,
3507                 avg_time_slots_per_mtp);
3508
3509         return DC_OK;
3510
3511 }
3512
3513 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3514 {
3515         struct dc_stream_state *stream = pipe_ctx->stream;
3516         struct dc_link *link = stream->link;
3517         struct link_encoder *link_encoder = NULL;
3518         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3519         struct dp_mst_stream_allocation_table proposed_table = {0};
3520         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3521         uint8_t i;
3522         bool mst_mode = (link->type == dc_connection_mst_branch);
3523         DC_LOGGER_INIT(link->ctx->logger);
3524
3525         /* Link encoder may have been dynamically assigned to non-physical display endpoint. */
3526         if (link->ep_type == DISPLAY_ENDPOINT_PHY)
3527                 link_encoder = link->link_enc;
3528         else if (link->dc->res_pool->funcs->link_encs_assign)
3529                 link_encoder = link_enc_cfg_get_link_enc_used_by_stream(pipe_ctx->stream->ctx->dc, stream);
3530         ASSERT(link_encoder);
3531
3532         /* deallocate_mst_payload is called before disable link. When mode or
3533          * disable/enable monitor, new stream is created which is not in link
3534          * stream[] yet. For this, payload is not allocated yet, so de-alloc
3535          * should not done. For new mode set, map_resources will get engine
3536          * for new stream, so stream_enc->id should be validated until here.
3537          */
3538
3539         /* slot X.Y */
3540         stream_encoder->funcs->set_throttled_vcp_size(
3541                 stream_encoder,
3542                 avg_time_slots_per_mtp);
3543
3544         /* TODO: which component is responsible for remove payload table? */
3545         if (mst_mode) {
3546                 if (dm_helpers_dp_mst_write_payload_allocation_table(
3547                                 stream->ctx,
3548                                 stream,
3549                                 &proposed_table,
3550                                 false)) {
3551
3552                         update_mst_stream_alloc_table(
3553                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3554                 }
3555                 else {
3556                                 DC_LOG_WARNING("Failed to update"
3557                                                 "MST allocation table for"
3558                                                 "pipe idx:%d\n",
3559                                                 pipe_ctx->pipe_idx);
3560                 }
3561         }
3562
3563         DC_LOG_MST("%s"
3564                         "stream_count: %d: ",
3565                         __func__,
3566                         link->mst_stream_alloc_table.stream_count);
3567
3568         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3569                 DC_LOG_MST("stream_enc[%d]: %p      "
3570                 "stream[%d].vcp_id: %d      "
3571                 "stream[%d].slot_count: %d\n",
3572                 i,
3573                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3574                 i,
3575                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3576                 i,
3577                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3578         }
3579
3580         link_encoder->funcs->update_mst_stream_allocation_table(
3581                 link_encoder,
3582                 &link->mst_stream_alloc_table);
3583
3584         if (mst_mode) {
3585                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3586                         stream->ctx,
3587                         stream);
3588
3589                 dm_helpers_dp_mst_send_payload_allocation(
3590                         stream->ctx,
3591                         stream,
3592                         false);
3593         }
3594
3595         return DC_OK;
3596 }
3597
3598
3599 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3600 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3601 {
3602         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3603 #if defined(CONFIG_DRM_AMD_DC_DCN)
3604         struct link_encoder *link_enc = NULL;
3605 #endif
3606
3607         if (cp_psp && cp_psp->funcs.update_stream_config) {
3608                 struct cp_psp_stream_config config = {0};
3609                 enum dp_panel_mode panel_mode =
3610                                 dp_get_panel_mode(pipe_ctx->stream->link);
3611
3612                 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3613                 /*stream_enc_inst*/
3614                 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3615                 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
3616 #if defined(CONFIG_DRM_AMD_DC_DCN)
3617                 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
3618                 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY) {
3619                         link_enc = pipe_ctx->stream->link->link_enc;
3620                         config.phy_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
3621                 } else if (pipe_ctx->stream->link->dc->res_pool->funcs->link_encs_assign) {
3622                         link_enc = link_enc_cfg_get_link_enc_used_by_stream(
3623                                         pipe_ctx->stream->ctx->dc,
3624                                         pipe_ctx->stream);
3625                         config.phy_idx = 0; /* Clear phy_idx for non-physical display endpoints. */
3626                 }
3627                 ASSERT(link_enc);
3628                 if (link_enc)
3629                         config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
3630                 if (is_dp_128b_132b_signal(pipe_ctx)) {
3631                         config.stream_enc_idx = pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
3632                         config.link_enc_idx = pipe_ctx->stream->link->hpo_dp_link_enc->inst;
3633                         config.dp2_enabled = 1;
3634                 }
3635 #endif
3636                 config.dpms_off = dpms_off;
3637                 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
3638                 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
3639                 config.mst_enabled = (pipe_ctx->stream->signal ==
3640                                 SIGNAL_TYPE_DISPLAY_PORT_MST);
3641                 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
3642         }
3643 }
3644 #endif
3645
3646 #if defined(CONFIG_DRM_AMD_DC_DCN)
3647 static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx)
3648 {
3649         struct dc *dc = pipe_ctx->stream->ctx->dc;
3650         struct dc_stream_state *stream = pipe_ctx->stream;
3651         struct link_mst_stream_allocation_table proposed_table = {0};
3652         struct fixed31_32 avg_time_slots_per_mtp;
3653         uint8_t req_slot_count = 0;
3654         uint8_t vc_id = 1; /// VC ID always 1 for SST
3655
3656         struct dc_link_settings link_settings = {0};
3657         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
3658
3659         decide_link_settings(stream, &link_settings);
3660         stream->link->cur_link_settings = link_settings;
3661
3662         /*  Enable clock, Configure lane count, and Enable Link Encoder*/
3663         enable_dp_hpo_output(stream->link, &stream->link->cur_link_settings);
3664
3665 #ifdef DIAGS_BUILD
3666         /* Workaround for FPGA HPO capture DP link data:
3667          * HPO capture will set link to active mode
3668          * This workaround is required to get a capture from start of frame
3669          */
3670         if (!dc->debug.fpga_hpo_capture_en) {
3671                 struct encoder_set_dp_phy_pattern_param params = {0};
3672                 params.dp_phy_pattern = DP_TEST_PATTERN_VIDEO_MODE;
3673
3674                 /* Set link active */
3675                 stream->link->hpo_dp_link_enc->funcs->set_link_test_pattern(
3676                                 stream->link->hpo_dp_link_enc,
3677                                 &params);
3678         }
3679 #endif
3680
3681         /* Enable DP_STREAM_ENC */
3682         dc->hwss.enable_stream(pipe_ctx);
3683
3684         /* Set DPS PPS SDP (AKA "info frames") */
3685         if (pipe_ctx->stream->timing.flags.DSC) {
3686                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
3687         }
3688
3689         /* Allocate Payload */
3690         if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) {
3691                 // MST case
3692                 uint8_t i;
3693
3694                 proposed_table.stream_count = state->stream_count;
3695                 for (i = 0; i < state->stream_count; i++) {
3696                         avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link);
3697                         req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
3698                         proposed_table.stream_allocations[i].slot_count = req_slot_count;
3699                         proposed_table.stream_allocations[i].vcp_id = i+1;
3700                         /* NOTE: This makes assumption that pipe_ctx index is same as stream index */
3701                         proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc;
3702                 }
3703         } else {
3704                 // SST case
3705                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, stream->link);
3706                 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
3707                 proposed_table.stream_count = 1; /// Always 1 stream for SST
3708                 proposed_table.stream_allocations[0].slot_count = req_slot_count;
3709                 proposed_table.stream_allocations[0].vcp_id = vc_id;
3710                 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
3711         }
3712
3713         stream->link->hpo_dp_link_enc->funcs->update_stream_allocation_table(
3714                         stream->link->hpo_dp_link_enc,
3715                         &proposed_table);
3716
3717         stream->link->hpo_dp_link_enc->funcs->set_throttled_vcp_size(
3718                         stream->link->hpo_dp_link_enc,
3719                         pipe_ctx->stream_res.hpo_dp_stream_enc->inst,
3720                         avg_time_slots_per_mtp);
3721
3722
3723
3724         dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings);
3725 }
3726 #endif
3727
3728 void core_link_enable_stream(
3729                 struct dc_state *state,
3730                 struct pipe_ctx *pipe_ctx)
3731 {
3732         struct dc *dc = pipe_ctx->stream->ctx->dc;
3733         struct dc_stream_state *stream = pipe_ctx->stream;
3734         struct dc_link *link = stream->sink->link;
3735         enum dc_status status;
3736         struct link_encoder *link_enc;
3737 #if defined(CONFIG_DRM_AMD_DC_DCN)
3738         enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
3739         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
3740
3741         if (is_dp_128b_132b_signal(pipe_ctx))
3742                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
3743 #endif
3744         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
3745
3746         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3747                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3748                 return;
3749
3750         if (dc->res_pool->funcs->link_encs_assign && stream->link->ep_type != DISPLAY_ENDPOINT_PHY)
3751                 link_enc = link_enc_cfg_get_link_enc_used_by_stream(dc, stream);
3752         else
3753                 link_enc = stream->link->link_enc;
3754         ASSERT(link_enc);
3755
3756 #if defined(CONFIG_DRM_AMD_DC_DCN)
3757         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)
3758                         && !is_dp_128b_132b_signal(pipe_ctx)) {
3759 #else
3760         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3761 #endif
3762                 if (link_enc)
3763                         link_enc->funcs->setup(
3764                                 link_enc,
3765                                 pipe_ctx->stream->signal);
3766                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
3767                         pipe_ctx->stream_res.stream_enc,
3768                         pipe_ctx->stream_res.tg->inst,
3769                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
3770         }
3771
3772 #if defined(CONFIG_DRM_AMD_DC_DCN)
3773         if (is_dp_128b_132b_signal(pipe_ctx)) {
3774                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->set_stream_attribute(
3775                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3776                                 &stream->timing,
3777                                 stream->output_color_space,
3778                                 stream->use_vsc_sdp_for_colorimetry,
3779                                 stream->timing.flags.DSC,
3780                                 false);
3781                 otg_out_dest = OUT_MUX_HPO_DP;
3782         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
3783                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
3784                                 pipe_ctx->stream_res.stream_enc,
3785                                 &stream->timing,
3786                                 stream->output_color_space,
3787                                 stream->use_vsc_sdp_for_colorimetry,
3788                                 stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
3789         }
3790 #else
3791         pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
3792                         pipe_ctx->stream_res.stream_enc,
3793                         &stream->timing,
3794                         stream->output_color_space,
3795                         stream->use_vsc_sdp_for_colorimetry,
3796                         stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
3797 #endif
3798
3799         if (dc_is_dp_signal(pipe_ctx->stream->signal))
3800                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR);
3801
3802         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
3803                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
3804                         pipe_ctx->stream_res.stream_enc,
3805                         &stream->timing,
3806                         stream->phy_pix_clk,
3807                         pipe_ctx->stream_res.audio != NULL);
3808
3809         pipe_ctx->stream->link->link_state_valid = true;
3810
3811 #if defined(CONFIG_DRM_AMD_DC_DCN)
3812         if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
3813                 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
3814 #endif
3815
3816         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
3817                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
3818                         pipe_ctx->stream_res.stream_enc,
3819                         &stream->timing,
3820                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
3821                         true : false);
3822
3823         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
3824                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
3825                         pipe_ctx->stream_res.stream_enc,
3826                         &stream->timing);
3827
3828         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
3829                 bool apply_edp_fast_boot_optimization =
3830                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
3831
3832                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
3833
3834 #if defined(CONFIG_DRM_AMD_DC_DCN)
3835                 // Enable VPG before building infoframe
3836                 if (vpg && vpg->funcs->vpg_poweron)
3837                         vpg->funcs->vpg_poweron(vpg);
3838 #endif
3839
3840                 resource_build_info_frame(pipe_ctx);
3841                 dc->hwss.update_info_frame(pipe_ctx);
3842
3843                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3844                         dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
3845
3846                 /* Do not touch link on seamless boot optimization. */
3847                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
3848                         pipe_ctx->stream->dpms_off = false;
3849
3850                         /* Still enable stream features & audio on seamless boot for DP external displays */
3851                         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
3852                                 enable_stream_features(pipe_ctx);
3853                                 if (pipe_ctx->stream_res.audio != NULL) {
3854                                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
3855                                         dc->hwss.enable_audio_stream(pipe_ctx);
3856                                 }
3857                         }
3858
3859 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3860                         update_psp_stream_config(pipe_ctx, false);
3861 #endif
3862                         return;
3863                 }
3864
3865                 /* eDP lit up by bios already, no need to enable again. */
3866                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
3867                                         apply_edp_fast_boot_optimization &&
3868                                         !pipe_ctx->stream->timing.flags.DSC) {
3869                         pipe_ctx->stream->dpms_off = false;
3870 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3871                         update_psp_stream_config(pipe_ctx, false);
3872 #endif
3873                         return;
3874                 }
3875
3876                 if (pipe_ctx->stream->dpms_off)
3877                         return;
3878
3879                 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
3880                  * link training). This is to make sure the bandwidth sent to DIG BE won't be
3881                  * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
3882                  * will be automatically set at a later time when the video is enabled
3883                  * (DP_VID_STREAM_EN = 1).
3884                  */
3885                 if (pipe_ctx->stream->timing.flags.DSC) {
3886                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3887                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3888                                 dp_set_dsc_enable(pipe_ctx, true);
3889                 }
3890
3891                 status = enable_link(state, pipe_ctx);
3892
3893                 if (status != DC_OK) {
3894                         DC_LOG_WARNING("enabling link %u failed: %d\n",
3895                         pipe_ctx->stream->link->link_index,
3896                         status);
3897
3898                         /* Abort stream enable *unless* the failure was due to
3899                          * DP link training - some DP monitors will recover and
3900                          * show the stream anyway. But MST displays can't proceed
3901                          * without link training.
3902                          */
3903                         if (status != DC_FAIL_DP_LINK_TRAINING ||
3904                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3905                                 BREAK_TO_DEBUGGER();
3906                                 return;
3907                         }
3908                 }
3909
3910                 /* turn off otg test pattern if enable */
3911                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3912                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3913                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3914                                         COLOR_DEPTH_UNDEFINED);
3915
3916                 /* This second call is needed to reconfigure the DIG
3917                  * as a workaround for the incorrect value being applied
3918                  * from transmitter control.
3919                  */
3920 #if defined(CONFIG_DRM_AMD_DC_DCN)
3921                 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
3922                                 is_dp_128b_132b_signal(pipe_ctx)))
3923 #else
3924                 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
3925 #endif
3926                         if (link_enc)
3927                                 link_enc->funcs->setup(
3928                                         link_enc,
3929                                         pipe_ctx->stream->signal);
3930
3931                 dc->hwss.enable_stream(pipe_ctx);
3932
3933                 /* Set DPS PPS SDP (AKA "info frames") */
3934                 if (pipe_ctx->stream->timing.flags.DSC) {
3935                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3936                                         dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3937                                 dp_set_dsc_on_rx(pipe_ctx, true);
3938                                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
3939                         }
3940                 }
3941
3942                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3943                         dc_link_allocate_mst_payload(pipe_ctx);
3944 #if defined(CONFIG_DRM_AMD_DC_DCN)
3945                 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
3946                                 is_dp_128b_132b_signal(pipe_ctx))
3947                         dc_link_update_sst_payload(pipe_ctx, true);
3948 #endif
3949
3950                 dc->hwss.unblank_stream(pipe_ctx,
3951                         &pipe_ctx->stream->link->cur_link_settings);
3952
3953                 if (stream->sink_patches.delay_ignore_msa > 0)
3954                         msleep(stream->sink_patches.delay_ignore_msa);
3955
3956                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3957                         enable_stream_features(pipe_ctx);
3958 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3959                 update_psp_stream_config(pipe_ctx, false);
3960 #endif
3961
3962                 dc->hwss.enable_audio_stream(pipe_ctx);
3963
3964         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
3965 #if defined(CONFIG_DRM_AMD_DC_DCN)
3966                 if (is_dp_128b_132b_signal(pipe_ctx)) {
3967                         fpga_dp_hpo_enable_link_and_stream(state, pipe_ctx);
3968                 }
3969 #endif
3970                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3971                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
3972                         dp_set_dsc_enable(pipe_ctx, true);
3973
3974         }
3975
3976         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3977                 core_link_set_avmute(pipe_ctx, false);
3978         }
3979 }
3980
3981 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
3982 {
3983         struct dc  *dc = pipe_ctx->stream->ctx->dc;
3984         struct dc_stream_state *stream = pipe_ctx->stream;
3985         struct dc_link *link = stream->sink->link;
3986 #if defined(CONFIG_DRM_AMD_DC_DCN)
3987         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
3988
3989         if (is_dp_128b_132b_signal(pipe_ctx))
3990                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
3991 #endif
3992
3993         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3994                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3995                 return;
3996
3997         if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
3998                 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
3999                         core_link_set_avmute(pipe_ctx, true);
4000         }
4001
4002         dc->hwss.disable_audio_stream(pipe_ctx);
4003
4004 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4005         update_psp_stream_config(pipe_ctx, true);
4006 #endif
4007         dc->hwss.blank_stream(pipe_ctx);
4008
4009         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4010                 deallocate_mst_payload(pipe_ctx);
4011 #if defined(CONFIG_DRM_AMD_DC_DCN)
4012         else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4013                         is_dp_128b_132b_signal(pipe_ctx))
4014                 dc_link_update_sst_payload(pipe_ctx, false);
4015 #endif
4016
4017         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4018                 struct ext_hdmi_settings settings = {0};
4019                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
4020
4021                 unsigned short masked_chip_caps = link->chip_caps &
4022                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
4023                 //Need to inform that sink is going to use legacy HDMI mode.
4024                 dal_ddc_service_write_scdc_data(
4025                         link->ddc,
4026                         165000,//vbios only handles 165Mhz.
4027                         false);
4028                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
4029                         /* DP159, Retimer settings */
4030                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
4031                                 write_i2c_retimer_setting(pipe_ctx,
4032                                                 false, false, &settings);
4033                         else
4034                                 write_i2c_default_retimer_setting(pipe_ctx,
4035                                                 false, false);
4036                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
4037                         /* PI3EQX1204, Redriver settings */
4038                         write_i2c_redriver_setting(pipe_ctx, false);
4039                 }
4040         }
4041
4042 #if defined(CONFIG_DRM_AMD_DC_DCN)
4043         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4044                         !is_dp_128b_132b_signal(pipe_ctx)) {
4045
4046                 /* In DP1.x SST mode, our encoder will go to TPS1
4047                  * when link is on but stream is off.
4048                  * Disabling link before stream will avoid exposing TPS1 pattern
4049                  * during the disable sequence as it will confuse some receivers
4050                  * state machine.
4051                  * In DP2 or MST mode, our encoder will stay video active
4052                  */
4053                 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4054                 dc->hwss.disable_stream(pipe_ctx);
4055         } else {
4056                 dc->hwss.disable_stream(pipe_ctx);
4057                 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4058         }
4059 #else
4060         disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4061
4062         dc->hwss.disable_stream(pipe_ctx);
4063 #endif
4064
4065         if (pipe_ctx->stream->timing.flags.DSC) {
4066                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4067                         dp_set_dsc_enable(pipe_ctx, false);
4068         }
4069 #if defined(CONFIG_DRM_AMD_DC_DCN)
4070         if (is_dp_128b_132b_signal(pipe_ctx)) {
4071                 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4072                         pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
4073         }
4074 #endif
4075
4076 #if defined(CONFIG_DRM_AMD_DC_DCN)
4077         if (vpg && vpg->funcs->vpg_powerdown)
4078                 vpg->funcs->vpg_powerdown(vpg);
4079 #endif
4080 }
4081
4082 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
4083 {
4084         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4085
4086         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
4087                 return;
4088
4089         dc->hwss.set_avmute(pipe_ctx, enable);
4090 }
4091
4092 /**
4093  *  dc_link_enable_hpd_filter:
4094  *     If enable is true, programs HPD filter on associated HPD line using
4095  *     delay_on_disconnect/delay_on_connect values dependent on
4096  *     link->connector_signal
4097  *
4098  *     If enable is false, programs HPD filter on associated HPD line with no
4099  *     delays on connect or disconnect
4100  *
4101  *  @link:   pointer to the dc link
4102  *  @enable: boolean specifying whether to enable hbd
4103  */
4104 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
4105 {
4106         struct gpio *hpd;
4107
4108         if (enable) {
4109                 link->is_hpd_filter_disabled = false;
4110                 program_hpd_filter(link);
4111         } else {
4112                 link->is_hpd_filter_disabled = true;
4113                 /* Obtain HPD handle */
4114                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4115
4116                 if (!hpd)
4117                         return;
4118
4119                 /* Setup HPD filtering */
4120                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
4121                         struct gpio_hpd_config config;
4122
4123                         config.delay_on_connect = 0;
4124                         config.delay_on_disconnect = 0;
4125
4126                         dal_irq_setup_hpd_filter(hpd, &config);
4127
4128                         dal_gpio_close(hpd);
4129                 } else {
4130                         ASSERT_CRITICAL(false);
4131                 }
4132                 /* Release HPD handle */
4133                 dal_gpio_destroy_irq(&hpd);
4134         }
4135 }
4136
4137 void dc_link_set_drive_settings(struct dc *dc,
4138                                 struct link_training_settings *lt_settings,
4139                                 const struct dc_link *link)
4140 {
4141
4142         int i;
4143
4144         for (i = 0; i < dc->link_count; i++) {
4145                 if (dc->links[i] == link)
4146                         break;
4147         }
4148
4149         if (i >= dc->link_count)
4150                 ASSERT_CRITICAL(false);
4151
4152         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
4153 }
4154
4155 void dc_link_set_preferred_link_settings(struct dc *dc,
4156                                          struct dc_link_settings *link_setting,
4157                                          struct dc_link *link)
4158 {
4159         int i;
4160         struct pipe_ctx *pipe;
4161         struct dc_stream_state *link_stream;
4162         struct dc_link_settings store_settings = *link_setting;
4163
4164         link->preferred_link_setting = store_settings;
4165
4166         /* Retrain with preferred link settings only relevant for
4167          * DP signal type
4168          * Check for non-DP signal or if passive dongle present
4169          */
4170         if (!dc_is_dp_signal(link->connector_signal) ||
4171                 link->dongle_max_pix_clk > 0)
4172                 return;
4173
4174         for (i = 0; i < MAX_PIPES; i++) {
4175                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4176                 if (pipe->stream && pipe->stream->link) {
4177                         if (pipe->stream->link == link) {
4178                                 link_stream = pipe->stream;
4179                                 break;
4180                         }
4181                 }
4182         }
4183
4184         /* Stream not found */
4185         if (i == MAX_PIPES)
4186                 return;
4187
4188         /* Cannot retrain link if backend is off */
4189         if (link_stream->dpms_off)
4190                 return;
4191
4192         decide_link_settings(link_stream, &store_settings);
4193
4194         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
4195                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
4196                 dp_retrain_link_dp_test(link, &store_settings, false);
4197 }
4198
4199 void dc_link_set_preferred_training_settings(struct dc *dc,
4200                                                  struct dc_link_settings *link_setting,
4201                                                  struct dc_link_training_overrides *lt_overrides,
4202                                                  struct dc_link *link,
4203                                                  bool skip_immediate_retrain)
4204 {
4205         if (lt_overrides != NULL)
4206                 link->preferred_training_settings = *lt_overrides;
4207         else
4208                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
4209
4210         if (link_setting != NULL) {
4211                 link->preferred_link_setting = *link_setting;
4212 #if defined(CONFIG_DRM_AMD_DC_DCN)
4213                 if (dp_get_link_encoding_format(link_setting) ==
4214                                 DP_128b_132b_ENCODING && !link->hpo_dp_link_enc) {
4215                         if (!add_dp_hpo_link_encoder_to_link(link))
4216                                 memset(&link->preferred_link_setting, 0, sizeof(link->preferred_link_setting));
4217                 }
4218 #endif
4219         } else {
4220                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
4221                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
4222         }
4223
4224         /* Retrain now, or wait until next stream update to apply */
4225         if (skip_immediate_retrain == false)
4226                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
4227 }
4228
4229 void dc_link_enable_hpd(const struct dc_link *link)
4230 {
4231         dc_link_dp_enable_hpd(link);
4232 }
4233
4234 void dc_link_disable_hpd(const struct dc_link *link)
4235 {
4236         dc_link_dp_disable_hpd(link);
4237 }
4238
4239 void dc_link_set_test_pattern(struct dc_link *link,
4240                               enum dp_test_pattern test_pattern,
4241                               enum dp_test_pattern_color_space test_pattern_color_space,
4242                               const struct link_training_settings *p_link_settings,
4243                               const unsigned char *p_custom_pattern,
4244                               unsigned int cust_pattern_size)
4245 {
4246         if (link != NULL)
4247                 dc_link_dp_set_test_pattern(
4248                         link,
4249                         test_pattern,
4250                         test_pattern_color_space,
4251                         p_link_settings,
4252                         p_custom_pattern,
4253                         cust_pattern_size);
4254 }
4255
4256 uint32_t dc_link_bandwidth_kbps(
4257         const struct dc_link *link,
4258         const struct dc_link_settings *link_setting)
4259 {
4260 #if defined(CONFIG_DRM_AMD_DC_DCN)
4261         uint32_t total_data_bw_efficiency_x10000 = 0;
4262         uint32_t link_rate_per_lane_kbps = 0;
4263
4264         switch (dp_get_link_encoding_format(link_setting)) {
4265         case DP_8b_10b_ENCODING:
4266                 /* For 8b/10b encoding:
4267                  * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
4268                  * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
4269                  */
4270                 link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
4271                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
4272                 if (dc_link_should_enable_fec(link)) {
4273                         total_data_bw_efficiency_x10000 /= 100;
4274                         total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
4275                 }
4276                 break;
4277         case DP_128b_132b_ENCODING:
4278                 /* For 128b/132b encoding:
4279                  * link rate is defined in the unit of 10mbps per lane.
4280                  * total data bandwidth efficiency is always 96.71%.
4281                  */
4282                 link_rate_per_lane_kbps = link_setting->link_rate * 10000;
4283                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
4284                 break;
4285         default:
4286                 break;
4287         }
4288
4289         /* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
4290         return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
4291 #else
4292         uint32_t link_bw_kbps =
4293                 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
4294
4295         link_bw_kbps *= 8;   /* 8 bits per byte*/
4296         link_bw_kbps *= link_setting->lane_count;
4297
4298         if (dc_link_should_enable_fec(link)) {
4299                 /* Account for FEC overhead.
4300                  * We have to do it based on caps,
4301                  * and not based on FEC being set ready,
4302                  * because FEC is set ready too late in
4303                  * the process to correctly be picked up
4304                  * by mode enumeration.
4305                  *
4306                  * There's enough zeros at the end of 'kbps'
4307                  * that make the below operation 100% precise
4308                  * for our purposes.
4309                  * 'long long' makes it work even for HDMI 2.1
4310                  * max bandwidth (and much, much bigger bandwidths
4311                  * than that, actually).
4312                  *
4313                  * NOTE: Reducing link BW by 3% may not be precise
4314                  * because it may be a stream BT that increases by 3%, and so
4315                  * 1/1.03 = 0.970873 factor should have been used instead,
4316                  * but the difference is minimal and is in a safe direction,
4317                  * which all works well around potential ambiguity of DP 1.4a spec.
4318                  */
4319                 long long fec_link_bw_kbps = link_bw_kbps * 970LL;
4320                 link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL));
4321         }
4322         return link_bw_kbps;
4323
4324 #endif
4325 }
4326
4327 const struct dc_link_settings *dc_link_get_link_cap(
4328                 const struct dc_link *link)
4329 {
4330         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
4331                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
4332                 return &link->preferred_link_setting;
4333         return &link->verified_link_cap;
4334 }
4335
4336 void dc_link_overwrite_extended_receiver_cap(
4337                 struct dc_link *link)
4338 {
4339         dp_overwrite_extended_receiver_cap(link);
4340 }
4341
4342 bool dc_link_is_fec_supported(const struct dc_link *link)
4343 {
4344         struct link_encoder *link_enc = NULL;
4345
4346         /* Links supporting dynamically assigned link encoder will be assigned next
4347          * available encoder if one not already assigned.
4348          */
4349         if (link->is_dig_mapping_flexible &&
4350                         link->dc->res_pool->funcs->link_encs_assign) {
4351                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
4352                 if (link_enc == NULL)
4353                         link_enc = link_enc_cfg_get_next_avail_link_enc(link->ctx->dc);
4354         } else
4355                 link_enc = link->link_enc;
4356         ASSERT(link_enc);
4357
4358         return (dc_is_dp_signal(link->connector_signal) && link_enc &&
4359                         link_enc->features.fec_supported &&
4360                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
4361                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
4362 }
4363
4364 bool dc_link_should_enable_fec(const struct dc_link *link)
4365 {
4366         bool is_fec_disable = false;
4367         bool ret = false;
4368
4369         if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
4370                         link->local_sink &&
4371                         link->local_sink->edid_caps.panel_patch.disable_fec) ||
4372                         (link->connector_signal == SIGNAL_TYPE_EDP
4373                                 ))
4374                 is_fec_disable = true;
4375
4376         if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
4377                 ret = true;
4378
4379         return ret;
4380 }
4381
4382 uint32_t dc_bandwidth_in_kbps_from_timing(
4383                 const struct dc_crtc_timing *timing)
4384 {
4385         uint32_t bits_per_channel = 0;
4386         uint32_t kbps;
4387
4388 #if defined(CONFIG_DRM_AMD_DC_DCN)
4389         if (timing->flags.DSC)
4390                 return dc_dsc_stream_bandwidth_in_kbps(timing,
4391                                 timing->dsc_cfg.bits_per_pixel,
4392                                 timing->dsc_cfg.num_slices_h,
4393                                 timing->dsc_cfg.is_dp);
4394 #endif
4395
4396         switch (timing->display_color_depth) {
4397         case COLOR_DEPTH_666:
4398                 bits_per_channel = 6;
4399                 break;
4400         case COLOR_DEPTH_888:
4401                 bits_per_channel = 8;
4402                 break;
4403         case COLOR_DEPTH_101010:
4404                 bits_per_channel = 10;
4405                 break;
4406         case COLOR_DEPTH_121212:
4407                 bits_per_channel = 12;
4408                 break;
4409         case COLOR_DEPTH_141414:
4410                 bits_per_channel = 14;
4411                 break;
4412         case COLOR_DEPTH_161616:
4413                 bits_per_channel = 16;
4414                 break;
4415         default:
4416                 ASSERT(bits_per_channel != 0);
4417                 bits_per_channel = 8;
4418                 break;
4419         }
4420
4421         kbps = timing->pix_clk_100hz / 10;
4422         kbps *= bits_per_channel;
4423
4424         if (timing->flags.Y_ONLY != 1) {
4425                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
4426                 kbps *= 3;
4427                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
4428                         kbps /= 2;
4429                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
4430                         kbps = kbps * 2 / 3;
4431         }
4432
4433         return kbps;
4434
4435 }