2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
29 #include "core_status.h"
30 #include "core_types.h"
31 #include "hw_sequencer.h"
35 #include "clock_source.h"
36 #include "dc_bios_types.h"
38 #include "dce_calcs.h"
39 #include "bios_parser_interface.h"
40 #include "include/irq_service_interface.h"
41 #include "transform.h"
42 #include "timing_generator.h"
43 #include "virtual/virtual_link_encoder.h"
45 #include "link_hwss.h"
46 #include "link_encoder.h"
48 #include "dc_link_ddc.h"
49 #include "dm_helpers.h"
50 #include "mem_input.h"
52 /*******************************************************************************
54 ******************************************************************************/
55 static void destroy_links(struct core_dc *dc)
59 for (i = 0; i < dc->link_count; i++) {
60 if (NULL != dc->links[i])
61 link_destroy(&dc->links[i]);
65 static bool create_links(
67 uint32_t num_virtual_links)
71 struct dc_bios *bios = dc->ctx->dc_bios;
75 connectors_num = bios->funcs->get_connectors_number(bios);
77 if (connectors_num > ENUM_ID_COUNT) {
79 "DC: Number of connectors %d exceeds maximum of %d!\n",
85 if (connectors_num == 0 && num_virtual_links == 0) {
86 dm_error("DC: Number of connectors is zero!\n");
90 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
95 for (i = 0; i < connectors_num; i++) {
96 struct link_init_data link_init_params = {0};
97 struct core_link *link;
99 link_init_params.ctx = dc->ctx;
100 link_init_params.connector_index = i;
101 link_init_params.link_index = dc->link_count;
102 link_init_params.dc = dc;
103 link = link_create(&link_init_params);
106 dc->links[dc->link_count] = link;
110 dm_error("DC: failed to create link!\n");
114 for (i = 0; i < num_virtual_links; i++) {
115 struct core_link *link = dm_alloc(sizeof(*link));
116 struct encoder_init_data enc_init = {0};
125 link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
126 link->link_id.type = OBJECT_TYPE_CONNECTOR;
127 link->link_id.id = CONNECTOR_ID_VIRTUAL;
128 link->link_id.enum_id = ENUM_ID_1;
129 link->link_enc = dm_alloc(sizeof(*link->link_enc));
131 enc_init.ctx = dc->ctx;
132 enc_init.channel = CHANNEL_ID_UNKNOWN;
133 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
134 enc_init.transmitter = TRANSMITTER_UNKNOWN;
135 enc_init.connector = link->link_id;
136 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
137 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
138 enc_init.encoder.enum_id = ENUM_ID_1;
139 virtual_link_encoder_construct(link->link_enc, &enc_init);
141 link->public.link_index = dc->link_count;
142 dc->links[dc->link_count] = link;
152 static bool stream_adjust_vmin_vmax(struct dc *dc,
153 const struct dc_stream **stream, int num_streams,
156 /* TODO: Support multiple streams */
157 struct core_dc *core_dc = DC_TO_CORE(dc);
158 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
162 for (i = 0; i < MAX_PIPES; i++) {
163 struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
165 if (pipe->stream == core_stream && pipe->stream_enc) {
166 core_dc->hwss.set_drr(&pipe, 1, vmin, vmax);
168 /* build and update the info frame */
169 resource_build_info_frame(pipe);
170 core_dc->hwss.update_info_frame(pipe);
179 static bool set_gamut_remap(struct dc *dc,
180 const struct dc_stream **stream, int num_streams)
182 struct core_dc *core_dc = DC_TO_CORE(dc);
183 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
186 struct pipe_ctx *pipes;
188 for (i = 0; i < MAX_PIPES; i++) {
189 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
192 pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
193 core_dc->hwss.set_plane_config(core_dc, pipes,
194 &core_dc->current_context->res_ctx);
202 /* This function is not expected to fail, proper implementation of
203 * validation will prevent this from ever being called for unsupported
206 static void stream_update_scaling(
208 const struct dc_stream *dc_stream,
209 const struct rect *src,
210 const struct rect *dst)
212 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
213 struct core_dc *core_dc = DC_TO_CORE(dc);
214 struct validate_context *cur_ctx = core_dc->current_context;
218 stream->public.src = *src;
221 stream->public.dst = *dst;
223 for (i = 0; i < cur_ctx->stream_count; i++) {
224 struct core_stream *cur_stream = cur_ctx->streams[i];
226 if (stream == cur_stream) {
227 struct dc_stream_status *status = &cur_ctx->stream_status[i];
229 if (status->surface_count)
230 if (!dc_commit_surfaces_to_stream(
233 status->surface_count,
234 &cur_stream->public))
235 /* Need to debug validation */
243 static bool set_psr_enable(struct dc *dc, bool enable)
245 struct core_dc *core_dc = DC_TO_CORE(dc);
248 for (i = 0; i < core_dc->link_count; i++)
249 dc_link_set_psr_enable(&core_dc->links[i]->public,
256 static bool setup_psr(struct dc *dc, const struct dc_stream *stream)
258 struct core_dc *core_dc = DC_TO_CORE(dc);
259 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
260 struct pipe_ctx *pipes;
262 unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
264 for (i = 0; i < core_dc->link_count; i++) {
265 if (core_stream->sink->link == core_dc->links[i])
266 dc_link_setup_psr(&core_dc->links[i]->public,
270 for (i = 0; i < MAX_PIPES; i++) {
271 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
272 == core_stream && i != underlay_idx) {
273 pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
274 core_dc->hwss.set_static_screen_control(&pipes, 1,
282 static void set_drive_settings(struct dc *dc,
283 struct link_training_settings *lt_settings,
284 const struct dc_link *link)
286 struct core_dc *core_dc = DC_TO_CORE(dc);
289 for (i = 0; i < core_dc->link_count; i++) {
290 if (&core_dc->links[i]->public == link)
294 if (i >= core_dc->link_count)
295 ASSERT_CRITICAL(false);
297 dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings);
300 static void perform_link_training(struct dc *dc,
301 struct dc_link_settings *link_setting,
302 bool skip_video_pattern)
304 struct core_dc *core_dc = DC_TO_CORE(dc);
307 for (i = 0; i < core_dc->link_count; i++)
308 dc_link_dp_perform_link_training(
309 &core_dc->links[i]->public,
314 static void set_preferred_link_settings(struct dc *dc,
315 struct dc_link_settings *link_setting,
316 const struct dc_link *link)
318 struct core_link *core_link = DC_LINK_TO_CORE(link);
320 core_link->public.verified_link_cap.lane_count =
321 link_setting->lane_count;
322 core_link->public.verified_link_cap.link_rate =
323 link_setting->link_rate;
324 dp_retrain_link_dp_test(core_link, link_setting, false);
327 static void enable_hpd(const struct dc_link *link)
329 dc_link_dp_enable_hpd(link);
332 static void disable_hpd(const struct dc_link *link)
334 dc_link_dp_disable_hpd(link);
338 static void set_test_pattern(
339 const struct dc_link *link,
340 enum dp_test_pattern test_pattern,
341 const struct link_training_settings *p_link_settings,
342 const unsigned char *p_custom_pattern,
343 unsigned int cust_pattern_size)
346 dc_link_dp_set_test_pattern(
354 static void allocate_dc_stream_funcs(struct core_dc *core_dc)
356 core_dc->public.stream_funcs.stream_update_scaling = stream_update_scaling;
357 if (core_dc->hwss.set_drr != NULL) {
358 core_dc->public.stream_funcs.adjust_vmin_vmax =
359 stream_adjust_vmin_vmax;
362 core_dc->public.stream_funcs.set_gamut_remap =
365 core_dc->public.stream_funcs.set_psr_enable =
368 core_dc->public.stream_funcs.setup_psr =
371 core_dc->public.link_funcs.set_drive_settings =
374 core_dc->public.link_funcs.perform_link_training =
375 perform_link_training;
377 core_dc->public.link_funcs.set_preferred_link_settings =
378 set_preferred_link_settings;
380 core_dc->public.link_funcs.enable_hpd =
383 core_dc->public.link_funcs.disable_hpd =
386 core_dc->public.link_funcs.set_test_pattern =
390 static void destruct(struct core_dc *dc)
392 resource_validate_ctx_destruct(dc->current_context);
396 dc_destroy_resource_pool(dc);
398 if (dc->ctx->gpio_service)
399 dal_gpio_service_destroy(&dc->ctx->gpio_service);
402 dal_i2caux_destroy(&dc->ctx->i2caux);
404 if (dc->ctx->created_bios)
405 dal_bios_parser_destroy(&dc->ctx->dc_bios);
408 dal_logger_destroy(&dc->ctx->logger);
410 dm_free(dc->current_context);
411 dc->current_context = NULL;
412 dm_free(dc->temp_flip_context);
413 dc->temp_flip_context = NULL;
414 dm_free(dc->scratch_val_ctx);
415 dc->scratch_val_ctx = NULL;
421 static bool construct(struct core_dc *dc,
422 const struct dc_init_data *init_params)
424 struct dal_logger *logger;
425 struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
426 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
429 dm_error("%s: failed to create ctx\n", __func__);
433 dc->current_context = dm_alloc(sizeof(*dc->current_context));
434 dc->temp_flip_context = dm_alloc(sizeof(*dc->temp_flip_context));
435 dc->scratch_val_ctx = dm_alloc(sizeof(*dc->scratch_val_ctx));
437 if (!dc->current_context || !dc->temp_flip_context) {
438 dm_error("%s: failed to create validate ctx\n", __func__);
442 dc_ctx->cgs_device = init_params->cgs_device;
443 dc_ctx->driver_context = init_params->driver;
444 dc_ctx->dc = &dc->public;
445 dc_ctx->asic_id = init_params->asic_id;
448 logger = dal_logger_create(dc_ctx);
451 /* can *not* call logger. call base driver 'print error' */
452 dm_error("%s: failed to create Logger!\n", __func__);
455 dc_ctx->logger = logger;
457 dc->ctx->dce_environment = init_params->dce_environment;
459 dc_version = resource_parse_asic_id(init_params->asic_id);
460 dc->ctx->dce_version = dc_version;
462 /* Resource should construct all asic specific resources.
463 * This should be the only place where we need to parse the asic id
465 if (init_params->vbios_override)
466 dc_ctx->dc_bios = init_params->vbios_override;
468 /* Create BIOS parser */
469 struct bp_init_data bp_init_data;
471 bp_init_data.ctx = dc_ctx;
472 bp_init_data.bios = init_params->asic_id.atombios_base_address;
474 dc_ctx->dc_bios = dal_bios_parser_create(
475 &bp_init_data, dc_version);
477 if (!dc_ctx->dc_bios) {
478 ASSERT_CRITICAL(false);
482 dc_ctx->created_bios = true;
486 dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
488 if (!dc_ctx->i2caux) {
489 ASSERT_CRITICAL(false);
490 goto failed_to_create_i2caux;
493 /* Create GPIO service */
494 dc_ctx->gpio_service = dal_gpio_service_create(
496 dc_ctx->dce_environment,
499 if (!dc_ctx->gpio_service) {
500 ASSERT_CRITICAL(false);
504 dc->res_pool = dc_create_resource_pool(
506 init_params->num_virtual_links,
508 init_params->asic_id);
510 goto create_resource_fail;
512 if (!create_links(dc, init_params->num_virtual_links))
513 goto create_links_fail;
515 allocate_dc_stream_funcs(dc);
519 /**** error handling here ****/
521 create_resource_fail:
523 failed_to_create_i2caux:
533 void ProgramPixelDurationV(unsigned int pixelClockInKHz )
535 fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
536 unsigned int pixDurationInPico = round(pixel_duration);
538 DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
540 arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
541 arb_control.bits.PIXEL_DURATION = pixDurationInPico;
542 WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
544 arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
545 arb_control.bits.PIXEL_DURATION = pixDurationInPico;
546 WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
548 WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
549 WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
551 WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
552 WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
556 /*******************************************************************************
558 ******************************************************************************/
560 struct dc *dc_create(const struct dc_init_data *init_params)
562 struct core_dc *core_dc = dm_alloc(sizeof(*core_dc));
563 unsigned int full_pipe_count;
568 if (false == construct(core_dc, init_params))
571 /*TODO: separate HW and SW initialization*/
572 core_dc->hwss.init_hw(core_dc);
574 full_pipe_count = core_dc->res_pool->pipe_count;
575 if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
577 core_dc->public.caps.max_streams = min(
579 core_dc->res_pool->stream_enc_count);
581 core_dc->public.caps.max_links = core_dc->link_count;
582 core_dc->public.caps.max_audios = core_dc->res_pool->audio_count;
584 core_dc->public.config = init_params->flags;
586 dm_logger_write(core_dc->ctx->logger, LOG_DC,
587 "Display Core initialized\n");
590 /* TODO: missing feature to be enabled */
591 core_dc->public.debug.disable_dfs_bypass = true;
593 return &core_dc->public;
602 void dc_destroy(struct dc **dc)
604 struct core_dc *core_dc = DC_TO_CORE(*dc);
610 static bool is_validation_required(
611 const struct core_dc *dc,
612 const struct dc_validation_set set[],
615 const struct validate_context *context = dc->current_context;
618 if (context->stream_count != set_count)
621 for (i = 0; i < set_count; i++) {
623 if (set[i].surface_count != context->stream_status[i].surface_count)
625 if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i]))
628 for (j = 0; j < set[i].surface_count; j++) {
629 struct dc_surface temp_surf = { 0 };
631 temp_surf = *context->stream_status[i].surfaces[j];
632 temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
633 temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
634 temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
636 if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0)
644 bool dc_validate_resources(
646 const struct dc_validation_set set[],
649 struct core_dc *core_dc = DC_TO_CORE(dc);
650 enum dc_status result = DC_ERROR_UNEXPECTED;
651 struct validate_context *context;
653 if (!is_validation_required(core_dc, set, set_count))
656 context = dm_alloc(sizeof(struct validate_context));
658 goto context_alloc_fail;
660 result = core_dc->res_pool->funcs->validate_with_context(
661 core_dc, set, set_count, context);
663 resource_validate_ctx_destruct(context);
667 if (result != DC_OK) {
668 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
669 "%s:resource validation failed, dc_status:%d\n",
674 return (result == DC_OK);
678 bool dc_validate_guaranteed(
680 const struct dc_stream *stream)
682 struct core_dc *core_dc = DC_TO_CORE(dc);
683 enum dc_status result = DC_ERROR_UNEXPECTED;
684 struct validate_context *context;
686 context = dm_alloc(sizeof(struct validate_context));
688 goto context_alloc_fail;
690 result = core_dc->res_pool->funcs->validate_guaranteed(
691 core_dc, stream, context);
693 resource_validate_ctx_destruct(context);
697 if (result != DC_OK) {
698 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
699 "%s:guaranteed validation failed, dc_status:%d\n",
704 return (result == DC_OK);
707 static void program_timing_sync(
708 struct core_dc *core_dc,
709 struct validate_context *ctx)
713 int pipe_count = ctx->res_ctx.pool->pipe_count;
714 struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
716 for (i = 0; i < pipe_count; i++) {
717 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
720 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
723 for (i = 0; i < pipe_count; i++) {
725 struct pipe_ctx *pipe_set[MAX_PIPES];
727 if (!unsynced_pipes[i])
730 pipe_set[0] = unsynced_pipes[i];
731 unsynced_pipes[i] = NULL;
733 /* Add tg to the set, search rest of the tg's for ones with
734 * same timing, add all tgs with same timing to the group
736 for (j = i + 1; j < pipe_count; j++) {
737 if (!unsynced_pipes[j])
740 if (resource_are_streams_timing_synchronizable(
741 unsynced_pipes[j]->stream,
742 pipe_set[0]->stream)) {
743 pipe_set[group_size] = unsynced_pipes[j];
744 unsynced_pipes[j] = NULL;
749 /* set first unblanked pipe as master */
750 for (j = 0; j < group_size; j++) {
751 struct pipe_ctx *temp;
753 if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
758 pipe_set[0] = pipe_set[j];
764 /* remove any other unblanked pipes as they have already been synced */
765 for (j = j + 1; j < group_size; j++) {
766 if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
768 pipe_set[j] = pipe_set[group_size];
773 if (group_size > 1) {
774 core_dc->hwss.enable_timing_synchronization(
775 core_dc, group_index, group_size, pipe_set);
781 static bool streams_changed(
783 const struct dc_stream *streams[],
784 uint8_t stream_count)
788 if (stream_count != dc->current_context->stream_count)
791 for (i = 0; i < dc->current_context->stream_count; i++) {
792 if (&dc->current_context->streams[i]->public != streams[i])
799 bool dc_commit_streams(
801 const struct dc_stream *streams[],
802 uint8_t stream_count)
804 struct core_dc *core_dc = DC_TO_CORE(dc);
805 struct dc_bios *dcb = core_dc->ctx->dc_bios;
806 enum dc_status result = DC_ERROR_UNEXPECTED;
807 struct validate_context *context;
808 struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
811 if (false == streams_changed(core_dc, streams, stream_count))
814 dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
815 __func__, stream_count);
817 for (i = 0; i < stream_count; i++) {
818 const struct dc_stream *stream = streams[i];
819 const struct dc_stream_status *status = dc_stream_get_status(stream);
822 dc_stream_log(stream,
823 core_dc->ctx->logger,
826 set[i].stream = stream;
829 set[i].surface_count = status->surface_count;
830 for (j = 0; j < status->surface_count; j++)
831 set[i].surfaces[j] = status->surfaces[j];
836 context = dm_alloc(sizeof(struct validate_context));
838 goto context_alloc_fail;
840 result = core_dc->res_pool->funcs->validate_with_context(core_dc, set, stream_count, context);
841 if (result != DC_OK){
842 dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
843 "%s: Context validation failed! dc_status:%d\n",
847 resource_validate_ctx_destruct(context);
851 if (!dcb->funcs->is_accelerated_mode(dcb)) {
852 core_dc->hwss.enable_accelerated_mode(core_dc);
855 if (result == DC_OK) {
856 result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
859 program_timing_sync(core_dc, context);
861 for (i = 0; i < context->stream_count; i++) {
862 const struct core_sink *sink = context->streams[i]->sink;
864 for (j = 0; j < context->stream_status[i].surface_count; j++) {
865 struct core_surface *surface =
866 DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
868 core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
871 CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
872 context->streams[i]->public.timing.h_addressable,
873 context->streams[i]->public.timing.v_addressable,
874 context->streams[i]->public.timing.h_total,
875 context->streams[i]->public.timing.v_total,
876 context->streams[i]->public.timing.pix_clk_khz);
879 resource_validate_ctx_destruct(core_dc->current_context);
881 if (core_dc->temp_flip_context != core_dc->current_context) {
882 dm_free(core_dc->temp_flip_context);
883 core_dc->temp_flip_context = core_dc->current_context;
885 core_dc->current_context = context;
886 memset(core_dc->temp_flip_context, 0, sizeof(*core_dc->temp_flip_context));
888 return (result == DC_OK);
894 return (result == DC_OK);
897 bool dc_pre_update_surfaces_to_stream(
899 const struct dc_surface *const *new_surfaces,
900 uint8_t new_surface_count,
901 const struct dc_stream *dc_stream)
906 bool dc_post_update_surfaces_to_stream(struct dc *dc)
909 struct core_dc *core_dc = DC_TO_CORE(dc);
910 struct validate_context *context = dm_alloc(sizeof(struct validate_context));
913 dm_error("%s: failed to create validate ctx\n", __func__);
916 resource_validate_ctx_copy_construct(core_dc->current_context, context);
918 post_surface_trace(dc);
920 for (i = 0; i < context->res_ctx.pool->pipe_count; i++)
921 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
922 context->res_ctx.pipe_ctx[i].pipe_idx = i;
923 core_dc->hwss.power_down_front_end(
924 core_dc, &context->res_ctx.pipe_ctx[i]);
926 if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
931 core_dc->hwss.set_bandwidth(core_dc, context, true);
933 resource_validate_ctx_destruct(core_dc->current_context);
934 if (core_dc->current_context)
935 dm_free(core_dc->current_context);
937 core_dc->current_context = context;
942 bool dc_commit_surfaces_to_stream(
944 const struct dc_surface **new_surfaces,
945 uint8_t new_surface_count,
946 const struct dc_stream *dc_stream)
948 struct dc_surface_update updates[MAX_SURFACES];
949 struct dc_flip_addrs flip_addr[MAX_SURFACES];
950 struct dc_plane_info plane_info[MAX_SURFACES];
951 struct dc_scaling_info scaling_info[MAX_SURFACES];
954 memset(updates, 0, sizeof(updates));
955 memset(flip_addr, 0, sizeof(flip_addr));
956 memset(plane_info, 0, sizeof(plane_info));
957 memset(scaling_info, 0, sizeof(scaling_info));
959 for (i = 0; i < new_surface_count; i++) {
960 updates[i].surface = new_surfaces[i];
962 (struct dc_gamma *)new_surfaces[i]->gamma_correction;
963 flip_addr[i].address = new_surfaces[i]->address;
964 flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
965 plane_info[i].color_space = new_surfaces[i]->color_space;
966 plane_info[i].format = new_surfaces[i]->format;
967 plane_info[i].plane_size = new_surfaces[i]->plane_size;
968 plane_info[i].rotation = new_surfaces[i]->rotation;
969 plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror;
970 plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
971 plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
972 plane_info[i].visible = new_surfaces[i]->visible;
973 plane_info[i].dcc = new_surfaces[i]->dcc;
974 scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
975 scaling_info[i].src_rect = new_surfaces[i]->src_rect;
976 scaling_info[i].dst_rect = new_surfaces[i]->dst_rect;
977 scaling_info[i].clip_rect = new_surfaces[i]->clip_rect;
979 updates[i].flip_addr = &flip_addr[i];
980 updates[i].plane_info = &plane_info[i];
981 updates[i].scaling_info = &scaling_info[i];
983 dc_update_surfaces_for_stream(dc, updates, new_surface_count, dc_stream);
985 return dc_post_update_surfaces_to_stream(dc);
988 static bool is_surface_in_context(
989 const struct validate_context *context,
990 const struct dc_surface *surface)
994 for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
995 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
997 if (surface == &pipe_ctx->surface->public) {
1005 static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
1008 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1009 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1011 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1012 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1013 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1014 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1016 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1017 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1018 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1021 ASSERT_CRITICAL(false);
1026 static enum surface_update_type get_plane_info_update_type(
1027 const struct dc_surface_update *u,
1030 struct dc_plane_info temp_plane_info = { { { { 0 } } } };
1033 return UPDATE_TYPE_FAST;
1035 /* Copy all parameters that will cause a full update
1036 * from current surface, the rest of the parameters
1037 * from provided plane configuration.
1038 * Perform memory compare and special validation
1039 * for those that can cause fast/medium updates
1042 /* Full update parameters */
1043 temp_plane_info.color_space = u->surface->color_space;
1044 temp_plane_info.dcc = u->surface->dcc;
1045 temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
1046 temp_plane_info.plane_size = u->surface->plane_size;
1047 temp_plane_info.rotation = u->surface->rotation;
1048 temp_plane_info.stereo_format = u->surface->stereo_format;
1049 temp_plane_info.tiling_info = u->surface->tiling_info;
1051 /* Special Validation parameters */
1052 temp_plane_info.format = u->plane_info->format;
1054 if (surface_index == 0)
1055 temp_plane_info.visible = u->plane_info->visible;
1057 temp_plane_info.visible = u->surface->visible;
1059 if (memcmp(u->plane_info, &temp_plane_info,
1060 sizeof(struct dc_plane_info)) != 0)
1061 return UPDATE_TYPE_FULL;
1063 if (pixel_format_to_bpp(u->plane_info->format) !=
1064 pixel_format_to_bpp(u->surface->format)) {
1065 return UPDATE_TYPE_FULL;
1067 return UPDATE_TYPE_MED;
1071 static enum surface_update_type get_scaling_info_update_type(
1072 const struct dc_surface_update *u)
1074 struct dc_scaling_info temp_scaling_info = { { 0 } };
1076 if (!u->scaling_info)
1077 return UPDATE_TYPE_FAST;
1079 /* Copy all parameters that will cause a full update
1080 * from current surface, the rest of the parameters
1081 * from provided plane configuration.
1082 * Perform memory compare and special validation
1083 * for those that can cause fast/medium updates
1086 /* Full Update Parameters */
1087 temp_scaling_info.dst_rect = u->surface->dst_rect;
1088 temp_scaling_info.src_rect = u->surface->src_rect;
1089 temp_scaling_info.scaling_quality = u->surface->scaling_quality;
1091 /* Special validation required */
1092 temp_scaling_info.clip_rect = u->scaling_info->clip_rect;
1094 if (memcmp(u->scaling_info, &temp_scaling_info,
1095 sizeof(struct dc_scaling_info)) != 0)
1096 return UPDATE_TYPE_FULL;
1098 /* Check Clip rectangles if not equal
1099 * difference is in offsets == > UPDATE_TYPE_FAST
1100 * difference is in dimensions == > UPDATE_TYPE_FULL
1102 if (memcmp(&u->scaling_info->clip_rect,
1103 &u->surface->clip_rect, sizeof(struct rect)) != 0) {
1104 if ((u->scaling_info->clip_rect.height ==
1105 u->surface->clip_rect.height) &&
1106 (u->scaling_info->clip_rect.width ==
1107 u->surface->clip_rect.width)) {
1108 return UPDATE_TYPE_FAST;
1110 return UPDATE_TYPE_FULL;
1114 return UPDATE_TYPE_FAST;
1117 static enum surface_update_type det_surface_update(
1118 const struct core_dc *dc,
1119 const struct dc_surface_update *u,
1122 const struct validate_context *context = dc->current_context;
1123 enum surface_update_type type = UPDATE_TYPE_FAST;
1124 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1126 if (!is_surface_in_context(context, u->surface))
1127 return UPDATE_TYPE_FULL;
1129 type = get_plane_info_update_type(u, surface_index);
1130 if (overall_type < type)
1131 overall_type = type;
1133 type = get_scaling_info_update_type(u);
1134 if (overall_type < type)
1135 overall_type = type;
1137 if (u->in_transfer_func ||
1138 u->out_transfer_func ||
1139 u->hdr_static_metadata) {
1140 if (overall_type < UPDATE_TYPE_MED)
1141 overall_type = UPDATE_TYPE_MED;
1144 return overall_type;
1147 enum surface_update_type dc_check_update_surfaces_for_stream(
1149 struct dc_surface_update *updates,
1151 struct dc_stream_update *stream_update,
1152 const struct dc_stream_status *stream_status)
1154 struct core_dc *core_dc = DC_TO_CORE(dc);
1156 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1158 if (stream_status->surface_count != surface_count)
1159 return UPDATE_TYPE_FULL;
1162 return UPDATE_TYPE_FULL;
1164 for (i = 0 ; i < surface_count; i++) {
1165 enum surface_update_type type =
1166 det_surface_update(core_dc, &updates[i], i);
1168 if (type == UPDATE_TYPE_FULL)
1171 if (overall_type < type)
1172 overall_type = type;
1175 return overall_type;
1178 void dc_update_surfaces_for_stream(struct dc *dc,
1179 struct dc_surface_update *surface_updates, int surface_count,
1180 const struct dc_stream *dc_stream)
1182 dc_update_surfaces_and_stream(dc, surface_updates, surface_count,
1186 enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1188 void dc_update_surfaces_and_stream(struct dc *dc,
1189 struct dc_surface_update *srf_updates, int surface_count,
1190 const struct dc_stream *dc_stream,
1191 struct dc_stream_update *stream_update)
1193 struct core_dc *core_dc = DC_TO_CORE(dc);
1194 struct validate_context *context;
1196 enum surface_update_type update_type;
1197 const struct dc_stream_status *stream_status;
1198 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
1200 stream_status = dc_stream_get_status(dc_stream);
1201 ASSERT(stream_status);
1203 return; /* Cannot commit surface to stream that is not committed */
1205 update_type = dc_check_update_surfaces_for_stream(
1206 dc, srf_updates, surface_count, stream_update, stream_status);
1208 if (update_type >= update_surface_trace_level)
1209 update_surface_trace(dc, srf_updates, surface_count);
1211 if (update_type >= UPDATE_TYPE_FULL) {
1212 const struct dc_surface *new_surfaces[MAX_SURFACES] = { 0 };
1214 for (i = 0; i < surface_count; i++)
1215 new_surfaces[i] = srf_updates[i].surface;
1217 /* initialize scratch memory for building context */
1218 context = core_dc->temp_flip_context;
1219 resource_validate_ctx_copy_construct(
1220 core_dc->current_context, context);
1222 /* add surface to context */
1223 if (!resource_attach_surfaces_to_context(
1224 new_surfaces, surface_count, dc_stream, context)) {
1225 BREAK_TO_DEBUGGER();
1229 context = core_dc->current_context;
1232 /* update current stream with the new updates */
1233 if (stream_update) {
1234 stream->public.src = stream_update->src;
1235 stream->public.dst = stream_update->dst;
1238 /* save update parameters into surface */
1239 for (i = 0; i < surface_count; i++) {
1240 struct core_surface *surface =
1241 DC_SURFACE_TO_CORE(srf_updates[i].surface);
1243 if (srf_updates[i].flip_addr) {
1244 surface->public.address = srf_updates[i].flip_addr->address;
1245 surface->public.flip_immediate =
1246 srf_updates[i].flip_addr->flip_immediate;
1249 if (srf_updates[i].scaling_info) {
1250 surface->public.scaling_quality =
1251 srf_updates[i].scaling_info->scaling_quality;
1252 surface->public.dst_rect =
1253 srf_updates[i].scaling_info->dst_rect;
1254 surface->public.src_rect =
1255 srf_updates[i].scaling_info->src_rect;
1256 surface->public.clip_rect =
1257 srf_updates[i].scaling_info->clip_rect;
1260 if (srf_updates[i].plane_info) {
1261 surface->public.color_space =
1262 srf_updates[i].plane_info->color_space;
1263 surface->public.format =
1264 srf_updates[i].plane_info->format;
1265 surface->public.plane_size =
1266 srf_updates[i].plane_info->plane_size;
1267 surface->public.rotation =
1268 srf_updates[i].plane_info->rotation;
1269 surface->public.horizontal_mirror =
1270 srf_updates[i].plane_info->horizontal_mirror;
1271 surface->public.stereo_format =
1272 srf_updates[i].plane_info->stereo_format;
1273 surface->public.tiling_info =
1274 srf_updates[i].plane_info->tiling_info;
1275 surface->public.visible =
1276 srf_updates[i].plane_info->visible;
1277 surface->public.dcc =
1278 srf_updates[i].plane_info->dcc;
1281 /* not sure if we still need this */
1282 if (update_type == UPDATE_TYPE_FULL) {
1283 for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
1284 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1286 if (pipe_ctx->surface != surface)
1289 resource_build_scaling_params(pipe_ctx);
1293 if (srf_updates[i].gamma &&
1294 srf_updates[i].gamma != surface->public.gamma_correction) {
1295 if (surface->public.gamma_correction != NULL)
1296 dc_gamma_release(&surface->public.
1299 dc_gamma_retain(srf_updates[i].gamma);
1300 surface->public.gamma_correction =
1301 srf_updates[i].gamma;
1304 if (srf_updates[i].in_transfer_func &&
1305 srf_updates[i].in_transfer_func != surface->public.in_transfer_func) {
1306 if (surface->public.in_transfer_func != NULL)
1307 dc_transfer_func_release(
1311 dc_transfer_func_retain(
1312 srf_updates[i].in_transfer_func);
1313 surface->public.in_transfer_func =
1314 srf_updates[i].in_transfer_func;
1317 if (srf_updates[i].out_transfer_func &&
1318 srf_updates[i].out_transfer_func != dc_stream->out_transfer_func) {
1319 if (dc_stream->out_transfer_func != NULL)
1320 dc_transfer_func_release(dc_stream->out_transfer_func);
1321 dc_transfer_func_retain(srf_updates[i].out_transfer_func);
1322 stream->public.out_transfer_func = srf_updates[i].out_transfer_func;
1324 if (srf_updates[i].hdr_static_metadata)
1325 surface->public.hdr_static_ctx =
1326 *(srf_updates[i].hdr_static_metadata);
1329 if (update_type == UPDATE_TYPE_FULL) {
1330 if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
1331 BREAK_TO_DEBUGGER();
1334 core_dc->hwss.set_bandwidth(core_dc, context, false);
1337 if (!surface_count) /* reset */
1338 core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
1340 /* Lock pipes for provided surfaces */
1341 for (i = 0; i < surface_count; i++) {
1342 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1344 for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
1345 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1347 if (pipe_ctx->surface != surface)
1349 if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1350 core_dc->hwss.pipe_control_lock(
1358 /* Perform requested Updates */
1359 for (i = 0; i < surface_count; i++) {
1360 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1362 if (update_type >= UPDATE_TYPE_MED) {
1363 core_dc->hwss.apply_ctx_for_surface(
1364 core_dc, surface, context);
1365 context_timing_trace(dc, &context->res_ctx);
1368 for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
1369 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1370 struct pipe_ctx *cur_pipe_ctx;
1371 bool is_new_pipe_surface = true;
1373 if (pipe_ctx->surface != surface)
1376 if (srf_updates[i].flip_addr)
1377 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1379 if (update_type == UPDATE_TYPE_FAST)
1382 cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
1383 if (cur_pipe_ctx->surface == pipe_ctx->surface)
1384 is_new_pipe_surface = false;
1386 if (is_new_pipe_surface ||
1387 srf_updates[i].in_transfer_func)
1388 core_dc->hwss.set_input_transfer_func(
1389 pipe_ctx, pipe_ctx->surface);
1391 if (is_new_pipe_surface ||
1392 srf_updates[i].out_transfer_func)
1393 core_dc->hwss.set_output_transfer_func(
1398 if (srf_updates[i].hdr_static_metadata) {
1399 resource_build_info_frame(pipe_ctx);
1400 core_dc->hwss.update_info_frame(pipe_ctx);
1406 for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) {
1407 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1409 for (j = 0; j < surface_count; j++) {
1410 if (srf_updates[j].surface == &pipe_ctx->surface->public) {
1411 if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1412 core_dc->hwss.pipe_control_lock(
1422 if (core_dc->current_context != context) {
1423 resource_validate_ctx_destruct(core_dc->current_context);
1424 core_dc->temp_flip_context = core_dc->current_context;
1426 core_dc->current_context = context;
1430 uint8_t dc_get_current_stream_count(const struct dc *dc)
1432 struct core_dc *core_dc = DC_TO_CORE(dc);
1433 return core_dc->current_context->stream_count;
1436 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i)
1438 struct core_dc *core_dc = DC_TO_CORE(dc);
1439 if (i < core_dc->current_context->stream_count)
1440 return &(core_dc->current_context->streams[i]->public);
1444 const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index)
1446 struct core_dc *core_dc = DC_TO_CORE(dc);
1447 return &core_dc->links[link_index]->public;
1450 const struct graphics_object_id dc_get_link_id_at_index(
1451 struct dc *dc, uint32_t link_index)
1453 struct core_dc *core_dc = DC_TO_CORE(dc);
1454 return core_dc->links[link_index]->link_id;
1457 const struct ddc_service *dc_get_ddc_at_index(
1458 struct dc *dc, uint32_t link_index)
1460 struct core_dc *core_dc = DC_TO_CORE(dc);
1461 return core_dc->links[link_index]->ddc;
1464 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1465 struct dc *dc, uint32_t link_index)
1467 struct core_dc *core_dc = DC_TO_CORE(dc);
1468 return core_dc->links[link_index]->public.irq_source_hpd;
1471 const struct audio **dc_get_audios(struct dc *dc)
1473 struct core_dc *core_dc = DC_TO_CORE(dc);
1474 return (const struct audio **)core_dc->res_pool->audios;
1477 void dc_flip_surface_addrs(
1479 const struct dc_surface *const surfaces[],
1480 struct dc_flip_addrs flip_addrs[],
1483 struct core_dc *core_dc = DC_TO_CORE(dc);
1486 for (i = 0; i < count; i++) {
1487 struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]);
1489 surface->public.address = flip_addrs[i].address;
1490 surface->public.flip_immediate = flip_addrs[i].flip_immediate;
1492 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1493 struct pipe_ctx *pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
1495 if (pipe_ctx->surface != surface)
1498 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1503 enum dc_irq_source dc_interrupt_to_irq_source(
1508 struct core_dc *core_dc = DC_TO_CORE(dc);
1509 return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id);
1512 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
1514 struct core_dc *core_dc = DC_TO_CORE(dc);
1515 dal_irq_service_set(core_dc->res_pool->irqs, src, enable);
1518 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1520 struct core_dc *core_dc = DC_TO_CORE(dc);
1521 dal_irq_service_ack(core_dc->res_pool->irqs, src);
1524 void dc_set_power_state(
1526 enum dc_acpi_cm_power_state power_state)
1528 struct core_dc *core_dc = DC_TO_CORE(dc);
1530 switch (power_state) {
1531 case DC_ACPI_CM_POWER_STATE_D0:
1532 core_dc->hwss.init_hw(core_dc);
1536 core_dc->hwss.power_down(core_dc);
1538 /* Zero out the current context so that on resume we start with
1539 * clean state, and dc hw programming optimizations will not
1540 * cause any trouble.
1542 memset(core_dc->current_context, 0,
1543 sizeof(*core_dc->current_context));
1545 core_dc->current_context->res_ctx.pool = core_dc->res_pool;
1552 void dc_resume(const struct dc *dc)
1554 struct core_dc *core_dc = DC_TO_CORE(dc);
1558 for (i = 0; i < core_dc->link_count; i++)
1559 core_link_resume(core_dc->links[i]);
1562 bool dc_read_aux_dpcd(
1564 uint32_t link_index,
1569 struct core_dc *core_dc = DC_TO_CORE(dc);
1571 struct core_link *link = core_dc->links[link_index];
1572 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1579 return r == DDC_RESULT_SUCESSFULL;
1582 bool dc_write_aux_dpcd(
1584 uint32_t link_index,
1586 const uint8_t *data,
1589 struct core_dc *core_dc = DC_TO_CORE(dc);
1590 struct core_link *link = core_dc->links[link_index];
1592 enum ddc_result r = dal_ddc_service_write_dpcd_data(
1599 return r == DDC_RESULT_SUCESSFULL;
1602 bool dc_read_aux_i2c(
1604 uint32_t link_index,
1605 enum i2c_mot_mode mot,
1610 struct core_dc *core_dc = DC_TO_CORE(dc);
1612 struct core_link *link = core_dc->links[link_index];
1613 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1620 return r == DDC_RESULT_SUCESSFULL;
1623 bool dc_write_aux_i2c(
1625 uint32_t link_index,
1626 enum i2c_mot_mode mot,
1628 const uint8_t *data,
1631 struct core_dc *core_dc = DC_TO_CORE(dc);
1632 struct core_link *link = core_dc->links[link_index];
1634 enum ddc_result r = dal_ddc_service_write_dpcd_data(
1641 return r == DDC_RESULT_SUCESSFULL;
1644 bool dc_query_ddc_data(
1646 uint32_t link_index,
1649 uint32_t write_size,
1651 uint32_t read_size) {
1653 struct core_dc *core_dc = DC_TO_CORE(dc);
1655 struct core_link *link = core_dc->links[link_index];
1657 bool result = dal_ddc_service_query_ddc_data(
1670 uint32_t link_index,
1671 struct i2c_command *cmd)
1673 struct core_dc *core_dc = DC_TO_CORE(dc);
1675 struct core_link *link = core_dc->links[link_index];
1676 struct ddc_service *ddc = link->ddc;
1678 return dal_i2caux_submit_i2c_command(
1684 static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink)
1686 struct dc_link *dc_link = &core_link->public;
1688 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1689 BREAK_TO_DEBUGGER();
1693 dc_sink_retain(sink);
1695 dc_link->remote_sinks[dc_link->sink_count] = sink;
1696 dc_link->sink_count++;
1701 struct dc_sink *dc_link_add_remote_sink(
1702 const struct dc_link *link,
1703 const uint8_t *edid,
1705 struct dc_sink_init_data *init_data)
1707 struct dc_sink *dc_sink;
1708 enum dc_edid_status edid_status;
1709 struct core_link *core_link = DC_LINK_TO_LINK(link);
1711 if (len > MAX_EDID_BUFFER_SIZE) {
1712 dm_error("Max EDID buffer size breached!\n");
1717 BREAK_TO_DEBUGGER();
1721 if (!init_data->link) {
1722 BREAK_TO_DEBUGGER();
1726 dc_sink = dc_sink_create(init_data);
1731 memmove(dc_sink->dc_edid.raw_edid, edid, len);
1732 dc_sink->dc_edid.length = len;
1734 if (!link_add_remote_sink_helper(
1739 edid_status = dm_helpers_parse_edid_caps(
1742 &dc_sink->edid_caps);
1744 if (edid_status != EDID_OK)
1749 dc_link_remove_remote_sink(link, dc_sink);
1751 dc_sink_release(dc_sink);
1755 void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink)
1757 struct core_link *core_link = DC_LINK_TO_LINK(link);
1758 struct dc_link *dc_link = &core_link->public;
1760 dc_link->local_sink = sink;
1763 dc_link->type = dc_connection_none;
1765 dc_link->type = dc_connection_single;
1769 void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
1772 struct core_link *core_link = DC_LINK_TO_LINK(link);
1773 struct dc_link *dc_link = &core_link->public;
1775 if (!link->sink_count) {
1776 BREAK_TO_DEBUGGER();
1780 for (i = 0; i < dc_link->sink_count; i++) {
1781 if (dc_link->remote_sinks[i] == sink) {
1782 dc_sink_release(sink);
1783 dc_link->remote_sinks[i] = NULL;
1785 /* shrink array to remove empty place */
1786 while (i < dc_link->sink_count - 1) {
1787 dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1];
1791 dc_link->sink_count--;
1797 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
1800 struct core_dc *core_dc = DC_TO_CORE(dc);
1801 struct mem_input *mi = NULL;
1803 for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
1804 if (core_dc->res_pool->mis[i] != NULL) {
1805 mi = core_dc->res_pool->mis[i];
1810 dm_error("no mem_input!\n");
1814 if (mi->funcs->mem_input_update_dchub)
1815 mi->funcs->mem_input_update_dchub(mi, dh_data);
1817 ASSERT(mi->funcs->mem_input_update_dchub);